drivers/net/qlge/qlge_main.c

   1 /*
   2  * QLogic qlge NIC HBA Driver
   3  * Copyright (c)  2003-2008 QLogic Corporation
   4  * See LICENSE.qlge for copyright and licensing details.
   5  * Author:     Linux qlge network device driver by
   6  *                      Ron Mercer <ron.mercer@qlogic.com>
   7  */
   8 #include <linux/kernel.h>
   9 #include <linux/init.h>
  10 #include <linux/types.h>
  11 #include <linux/module.h>
  12 #include <linux/list.h>
  13 #include <linux/pci.h>
  14 #include <linux/dma-mapping.h>
  15 #include <linux/pagemap.h>
  16 #include <linux/sched.h>
  17 #include <linux/slab.h>
  18 #include <linux/dmapool.h>
  19 #include <linux/mempool.h>
  20 #include <linux/spinlock.h>
  21 #include <linux/kthread.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/errno.h>
  24 #include <linux/ioport.h>
  25 #include <linux/in.h>
  26 #include <linux/ip.h>
  27 #include <linux/ipv6.h>
  28 #include <net/ipv6.h>
  29 #include <linux/tcp.h>
  30 #include <linux/udp.h>
  31 #include <linux/if_arp.h>
  32 #include <linux/if_ether.h>
  33 #include <linux/netdevice.h>
  34 #include <linux/etherdevice.h>
  35 #include <linux/ethtool.h>
  36 #include <linux/skbuff.h>
  37 #include <linux/rtnetlink.h>
  38 #include <linux/if_vlan.h>
  39 #include <linux/delay.h>
  40 #include <linux/mm.h>
  41 #include <linux/vmalloc.h>
  42 #include <net/ip6_checksum.h>
  43
  44 #include "qlge.h"
  45
  46 char qlge_driver_name[] = DRV_NAME;
  47 const char qlge_driver_version[] = DRV_VERSION;
  48
  49 MODULE_AUTHOR("Ron Mercer <ron.mercer@qlogic.com>");
  50 MODULE_DESCRIPTION(DRV_STRING " ");
  51 MODULE_LICENSE("GPL");
  52 MODULE_VERSION(DRV_VERSION);
  53
  54 static const u32 default_msg =
  55     NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK |
  56 /* NETIF_MSG_TIMER |    */
  57     NETIF_MSG_IFDOWN |
  58     NETIF_MSG_IFUP |
  59     NETIF_MSG_RX_ERR |
  60     NETIF_MSG_TX_ERR |
  61     NETIF_MSG_TX_QUEUED |
  62     NETIF_MSG_INTR | NETIF_MSG_TX_DONE | NETIF_MSG_RX_STATUS |
  63 /* NETIF_MSG_PKTDATA | */
  64     NETIF_MSG_HW | NETIF_MSG_WOL | 0;
  65
  66 static int debug = 0x00007fff;  /* defaults above */
  67 module_param(debug, int, 0);
  68 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
  69
  70 #define MSIX_IRQ 0
  71 #define MSI_IRQ 1
  72 #define LEG_IRQ 2
  73 static int irq_type = MSIX_IRQ;
  74 module_param(irq_type, int, MSIX_IRQ);
  75 MODULE_PARM_DESC(irq_type, "0 = MSI-X, 1 = MSI, 2 = Legacy.");
  76
  77 static struct pci_device_id qlge_pci_tbl[] __devinitdata = {
  78         {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QLGE_DEVICE_ID)},
  79         /* required last entry */
  80         {0,}
  81 };
  82
  83 MODULE_DEVICE_TABLE(pci, qlge_pci_tbl);
  84
  85 /* This hardware semaphore causes exclusive access to
  86  * resources shared between the NIC driver, MPI firmware,
  87  * FCOE firmware and the FC driver.
  88  */
  89 static int ql_sem_trylock(struct ql_adapter *qdev, u32 sem_mask)
  90 {
  91         u32 sem_bits = 0;
  92
  93         switch (sem_mask) {
  94         case SEM_XGMAC0_MASK:
  95                 sem_bits = SEM_SET << SEM_XGMAC0_SHIFT;
  96                 break;
  97         case SEM_XGMAC1_MASK:
  98                 sem_bits = SEM_SET << SEM_XGMAC1_SHIFT;
  99                 break;
 100         case SEM_ICB_MASK:
 101                 sem_bits = SEM_SET << SEM_ICB_SHIFT;
 102                 break;
 103         case SEM_MAC_ADDR_MASK:
 104                 sem_bits = SEM_SET << SEM_MAC_ADDR_SHIFT;
 105                 break;
 106         case SEM_FLASH_MASK:
 107                 sem_bits = SEM_SET << SEM_FLASH_SHIFT;
 108                 break;
 109         case SEM_PROBE_MASK:
 110                 sem_bits = SEM_SET << SEM_PROBE_SHIFT;
 111                 break;
 112         case SEM_RT_IDX_MASK:
 113                 sem_bits = SEM_SET << SEM_RT_IDX_SHIFT;
 114                 break;
 115         case SEM_PROC_REG_MASK:
 116                 sem_bits = SEM_SET << SEM_PROC_REG_SHIFT;
 117                 break;
 118         default:
 119                 QPRINTK(qdev, PROBE, ALERT, "Bad Semaphore mask!.\n");
 120                 return -EINVAL;
 121         }
 122
 123         ql_write32(qdev, SEM, sem_bits | sem_mask);
 124         return !(ql_read32(qdev, SEM) & sem_bits);
 125 }
 126
 127 int ql_sem_spinlock(struct ql_adapter *qdev, u32 sem_mask)
 128 {
 129         unsigned int wait_count = 30;
 130         do {
 131                 if (!ql_sem_trylock(qdev, sem_mask))
 132                         return 0;
 133                 udelay(100);
 134         } while (--wait_count);
 135         return -ETIMEDOUT;
 136 }
 137
 138 void ql_sem_unlock(struct ql_adapter *qdev, u32 sem_mask)
 139 {
 140         ql_write32(qdev, SEM, sem_mask);
 141         ql_read32(qdev, SEM);   /* flush */
 142 }
 143
 144 /* This function waits for a specific bit to come ready
 145  * in a given register.  It is used mostly by the initialize
 146  * process, but is also used in kernel thread API such as
 147  * netdev->set_multi, netdev->set_mac_address, netdev->vlan_rx_add_vid.
 148  */
 149 int ql_wait_reg_rdy(struct ql_adapter *qdev, u32 reg, u32 bit, u32 err_bit)
 150 {
 151         u32 temp;
 152         int count = UDELAY_COUNT;
 153
 154         while (count) {
 155                 temp = ql_read32(qdev, reg);
 156
 157                 /* check for errors */
 158                 if (temp & err_bit) {
 159                         QPRINTK(qdev, PROBE, ALERT,
 160                                 "register 0x%.08x access error, value = 0x%.08x!.\n",
 161                                 reg, temp);
 162                         return -EIO;
 163                 } else if (temp & bit)
 164                         return 0;
 165                 udelay(UDELAY_DELAY);
 166                 count--;
 167         }
 168         QPRINTK(qdev, PROBE, ALERT,
 169                 "Timed out waiting for reg %x to come ready.\n", reg);
 170         return -ETIMEDOUT;
 171 }
 172
 173 /* The CFG register is used to download TX and RX control blocks
 174  * to the chip. This function waits for an operation to complete.
 175  */
 176 static int ql_wait_cfg(struct ql_adapter *qdev, u32 bit)
 177 {
 178         int count = UDELAY_COUNT;
 179         u32 temp;
 180
 181         while (count) {
 182                 temp = ql_read32(qdev, CFG);
 183                 if (temp & CFG_LE)
 184                         return -EIO;
 185                 if (!(temp & bit))
 186                         return 0;
 187                 udelay(UDELAY_DELAY);
 188                 count--;
 189         }
 190         return -ETIMEDOUT;
 191 }
 192
 193
 194 /* Used to issue init control blocks to hw. Maps control block,
 195  * sets address, triggers download, waits for completion.
 196  */
 197 int ql_write_cfg(struct ql_adapter *qdev, void *ptr, int size, u32 bit,
 198                  u16 q_id)
 199 {
 200         u64 map;
 201         int status = 0;
 202         int direction;
 203         u32 mask;
 204         u32 value;
 205
 206         direction =
 207             (bit & (CFG_LRQ | CFG_LR | CFG_LCQ)) ? PCI_DMA_TODEVICE :
 208             PCI_DMA_FROMDEVICE;
 209
 210         map = pci_map_single(qdev->pdev, ptr, size, direction);
 211         if (pci_dma_mapping_error(qdev->pdev, map)) {
 212                 QPRINTK(qdev, IFUP, ERR, "Couldn't map DMA area.\n");
 213                 return -ENOMEM;
 214         }
 215
 216         status = ql_wait_cfg(qdev, bit);
 217         if (status) {
 218                 QPRINTK(qdev, IFUP, ERR,
 219                         "Timed out waiting for CFG to come ready.\n");
 220                 goto exit;
 221         }
 222
 223         status = ql_sem_spinlock(qdev, SEM_ICB_MASK);
 224         if (status)
 225                 goto exit;
 226         ql_write32(qdev, ICB_L, (u32) map);
 227         ql_write32(qdev, ICB_H, (u32) (map >> 32));
 228         ql_sem_unlock(qdev, SEM_ICB_MASK);      /* does flush too */
 229
 230         mask = CFG_Q_MASK | (bit << 16);
 231         value = bit | (q_id << CFG_Q_SHIFT);
 232         ql_write32(qdev, CFG, (mask | value));
 233
 234         /*
 235          * Wait for the bit to clear after signaling hw.
 236          */
 237         status = ql_wait_cfg(qdev, bit);
 238 exit:
 239         pci_unmap_single(qdev->pdev, map, size, direction);
 240         return status;
 241 }
 242
 243 /* Get a specific MAC address from the CAM.  Used for debug and reg dump. */
 244 int ql_get_mac_addr_reg(struct ql_adapter *qdev, u32 type, u16 index,
 245                         u32 *value)
 246 {
 247         u32 offset = 0;
 248         int status;
 249
 250         status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
 251         if (status)
 252                 return status;
 253         switch (type) {
 254         case MAC_ADDR_TYPE_MULTI_MAC:
 255         case MAC_ADDR_TYPE_CAM_MAC:
 256                 {
 257                         status =
 258                             ql_wait_reg_rdy(qdev,
 259                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 260                         if (status)
 261                                 goto exit;
 262                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
 263                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
 264                                    MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
 265                         status =
 266                             ql_wait_reg_rdy(qdev,
 267                                 MAC_ADDR_IDX, MAC_ADDR_MR, 0);
 268                         if (status)
 269                                 goto exit;
 270                         *value++ = ql_read32(qdev, MAC_ADDR_DATA);
 271                         status =
 272                             ql_wait_reg_rdy(qdev,
 273                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 274                         if (status)
 275                                 goto exit;
 276                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
 277                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
 278                                    MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
 279                         status =
 280                             ql_wait_reg_rdy(qdev,
 281                                 MAC_ADDR_IDX, MAC_ADDR_MR, 0);
 282                         if (status)
 283                                 goto exit;
 284                         *value++ = ql_read32(qdev, MAC_ADDR_DATA);
 285                         if (type == MAC_ADDR_TYPE_CAM_MAC) {
 286                                 status =
 287                                     ql_wait_reg_rdy(qdev,
 288                                         MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 289                                 if (status)
 290                                         goto exit;
 291                                 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
 292                                            (index << MAC_ADDR_IDX_SHIFT) | /* index */
 293                                            MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
 294                                 status =
 295                                     ql_wait_reg_rdy(qdev, MAC_ADDR_IDX,
 296                                                     MAC_ADDR_MR, 0);
 297                                 if (status)
 298                                         goto exit;
 299                                 *value++ = ql_read32(qdev, MAC_ADDR_DATA);
 300                         }
 301                         break;
 302                 }
 303         case MAC_ADDR_TYPE_VLAN:
 304         case MAC_ADDR_TYPE_MULTI_FLTR:
 305         default:
 306                 QPRINTK(qdev, IFUP, CRIT,
 307                         "Address type %d not yet supported.\n", type);
 308                 status = -EPERM;
 309         }
 310 exit:
 311         ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
 312         return status;
 313 }
 314
 315 /* Set up a MAC, multicast or VLAN address for the
 316  * inbound frame matching.
 317  */
 318 static int ql_set_mac_addr_reg(struct ql_adapter *qdev, u8 *addr, u32 type,
 319                                u16 index)
 320 {
 321         u32 offset = 0;
 322         int status = 0;
 323
 324         status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
 325         if (status)
 326                 return status;
 327         switch (type) {
 328         case MAC_ADDR_TYPE_MULTI_MAC:
 329         case MAC_ADDR_TYPE_CAM_MAC:
 330                 {
 331                         u32 cam_output;
 332                         u32 upper = (addr[0] << 8) | addr[1];
 333                         u32 lower =
 334                             (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) |
 335                             (addr[5]);
 336
 337                         QPRINTK(qdev, IFUP, INFO,
 338                                 "Adding %s address %pM"
 339                                 " at index %d in the CAM.\n",
 340                                 ((type ==
 341                                   MAC_ADDR_TYPE_MULTI_MAC) ? "MULTICAST" :
 342                                  "UNICAST"), addr, index);
 343
 344                         status =
 345                             ql_wait_reg_rdy(qdev,
 346                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 347                         if (status)
 348                                 goto exit;
 349                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
 350                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
 351                                    type);       /* type */
 352                         ql_write32(qdev, MAC_ADDR_DATA, lower);
 353                         status =
 354                             ql_wait_reg_rdy(qdev,
 355                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 356                         if (status)
 357                                 goto exit;
 358                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
 359                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
 360                                    type);       /* type */
 361                         ql_write32(qdev, MAC_ADDR_DATA, upper);
 362                         status =
 363                             ql_wait_reg_rdy(qdev,
 364                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 365                         if (status)
 366                                 goto exit;
 367                         ql_write32(qdev, MAC_ADDR_IDX, (offset) |       /* offset */
 368                                    (index << MAC_ADDR_IDX_SHIFT) |      /* index */
 369                                    type);       /* type */
 370                         /* This field should also include the queue id
 371                            and possibly the function id.  Right now we hardcode
 372                            the route field to NIC core.
 373                          */
 374                         if (type == MAC_ADDR_TYPE_CAM_MAC) {
 375                                 cam_output = (CAM_OUT_ROUTE_NIC |
 376                                               (qdev->
 377                                                func << CAM_OUT_FUNC_SHIFT) |
 378                                               (qdev->
 379                                                rss_ring_first_cq_id <<
 380                                                CAM_OUT_CQ_ID_SHIFT));
 381                                 if (qdev->vlgrp)
 382                                         cam_output |= CAM_OUT_RV;
 383                                 /* route to NIC core */
 384                                 ql_write32(qdev, MAC_ADDR_DATA, cam_output);
 385                         }
 386                         break;
 387                 }
 388         case MAC_ADDR_TYPE_VLAN:
 389                 {
 390                         u32 enable_bit = *((u32 *) &addr[0]);
 391                         /* For VLAN, the addr actually holds a bit that
 392                          * either enables or disables the vlan id we are
 393                          * addressing. It's either MAC_ADDR_E on or off.
 394                          * That's bit-27 we're talking about.
 395                          */
 396                         QPRINTK(qdev, IFUP, INFO, "%s VLAN ID %d %s the CAM.\n",
 397                                 (enable_bit ? "Adding" : "Removing"),
 398                                 index, (enable_bit ? "to" : "from"));
 399
 400                         status =
 401                             ql_wait_reg_rdy(qdev,
 402                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 403                         if (status)
 404                                 goto exit;
 405                         ql_write32(qdev, MAC_ADDR_IDX, offset | /* offset */
 406                                    (index << MAC_ADDR_IDX_SHIFT) |      /* index */
 407                                    type |       /* type */
 408                                    enable_bit); /* enable/disable */
 409                         break;
 410                 }
 411         case MAC_ADDR_TYPE_MULTI_FLTR:
 412         default:
 413                 QPRINTK(qdev, IFUP, CRIT,
 414                         "Address type %d not yet supported.\n", type);
 415                 status = -EPERM;
 416         }
 417 exit:
 418         ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
 419         return status;
 420 }
 421
 422 /* Get a specific frame routing value from the CAM.
 423  * Used for debug and reg dump.
 424  */
 425 int ql_get_routing_reg(struct ql_adapter *qdev, u32 index, u32 *value)
 426 {
 427         int status = 0;
 428
 429         status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
 430         if (status)
 431                 goto exit;
 432
 433         status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, 0);
 434         if (status)
 435                 goto exit;
 436
 437         ql_write32(qdev, RT_IDX,
 438                    RT_IDX_TYPE_NICQ | RT_IDX_RS | (index << RT_IDX_IDX_SHIFT));
 439         status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MR, 0);
 440         if (status)
 441                 goto exit;
 442         *value = ql_read32(qdev, RT_DATA);
 443 exit:
 444         ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
 445         return status;
 446 }
 447
 448 /* The NIC function for this chip has 16 routing indexes.  Each one can be used
 449  * to route different frame types to various inbound queues.  We send broadcast/
 450  * multicast/error frames to the default queue for slow handling,
 451  * and CAM hit/RSS frames to the fast handling queues.
 452  */
 453 static int ql_set_routing_reg(struct ql_adapter *qdev, u32 index, u32 mask,
 454                               int enable)
 455 {
 456         int status;
 457         u32 value = 0;
 458
 459         status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
 460         if (status)
 461                 return status;
 462
 463         QPRINTK(qdev, IFUP, DEBUG,
 464                 "%s %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s mask %s the routing reg.\n",
 465                 (enable ? "Adding" : "Removing"),
 466                 ((index == RT_IDX_ALL_ERR_SLOT) ? "MAC ERROR/ALL ERROR" : ""),
 467                 ((index == RT_IDX_IP_CSUM_ERR_SLOT) ? "IP CSUM ERROR" : ""),
 468                 ((index ==
 469                   RT_IDX_TCP_UDP_CSUM_ERR_SLOT) ? "TCP/UDP CSUM ERROR" : ""),
 470                 ((index == RT_IDX_BCAST_SLOT) ? "BROADCAST" : ""),
 471                 ((index == RT_IDX_MCAST_MATCH_SLOT) ? "MULTICAST MATCH" : ""),
 472                 ((index == RT_IDX_ALLMULTI_SLOT) ? "ALL MULTICAST MATCH" : ""),
 473                 ((index == RT_IDX_UNUSED6_SLOT) ? "UNUSED6" : ""),
 474                 ((index == RT_IDX_UNUSED7_SLOT) ? "UNUSED7" : ""),
 475                 ((index == RT_IDX_RSS_MATCH_SLOT) ? "RSS ALL/IPV4 MATCH" : ""),
 476                 ((index == RT_IDX_RSS_IPV6_SLOT) ? "RSS IPV6" : ""),
 477                 ((index == RT_IDX_RSS_TCP4_SLOT) ? "RSS TCP4" : ""),
 478                 ((index == RT_IDX_RSS_TCP6_SLOT) ? "RSS TCP6" : ""),
 479                 ((index == RT_IDX_CAM_HIT_SLOT) ? "CAM HIT" : ""),
 480                 ((index == RT_IDX_UNUSED013) ? "UNUSED13" : ""),
 481                 ((index == RT_IDX_UNUSED014) ? "UNUSED14" : ""),
 482                 ((index == RT_IDX_PROMISCUOUS_SLOT) ? "PROMISCUOUS" : ""),
 483                 (enable ? "to" : "from"));
 484
 485         switch (mask) {
 486         case RT_IDX_CAM_HIT:
 487                 {
 488                         value = RT_IDX_DST_CAM_Q |      /* dest */
 489                             RT_IDX_TYPE_NICQ |  /* type */
 490                             (RT_IDX_CAM_HIT_SLOT << RT_IDX_IDX_SHIFT);/* index */
 491                         break;
 492                 }
 493         case RT_IDX_VALID:      /* Promiscuous Mode frames. */
 494                 {
 495                         value = RT_IDX_DST_DFLT_Q |     /* dest */
 496                             RT_IDX_TYPE_NICQ |  /* type */
 497                             (RT_IDX_PROMISCUOUS_SLOT << RT_IDX_IDX_SHIFT);/* index */
 498                         break;
 499                 }
 500         case RT_IDX_ERR:        /* Pass up MAC,IP,TCP/UDP error frames. */
 501                 {
 502                         value = RT_IDX_DST_DFLT_Q |     /* dest */
 503                             RT_IDX_TYPE_NICQ |  /* type */
 504                             (RT_IDX_ALL_ERR_SLOT << RT_IDX_IDX_SHIFT);/* index */
 505                         break;
 506                 }
 507         case RT_IDX_BCAST:      /* Pass up Broadcast frames to default Q. */
 508                 {
 509                         value = RT_IDX_DST_DFLT_Q |     /* dest */
 510                             RT_IDX_TYPE_NICQ |  /* type */
 511                             (RT_IDX_BCAST_SLOT << RT_IDX_IDX_SHIFT);/* index */
 512                         break;
 513                 }
 514         case RT_IDX_MCAST:      /* Pass up All Multicast frames. */
 515                 {
 516                         value = RT_IDX_DST_CAM_Q |      /* dest */
 517                             RT_IDX_TYPE_NICQ |  /* type */
 518                             (RT_IDX_ALLMULTI_SLOT << RT_IDX_IDX_SHIFT);/* index */
 519                         break;
 520                 }
 521         case RT_IDX_MCAST_MATCH:        /* Pass up matched Multicast frames. */
 522                 {
 523                         value = RT_IDX_DST_CAM_Q |      /* dest */
 524                             RT_IDX_TYPE_NICQ |  /* type */
 525                             (RT_IDX_MCAST_MATCH_SLOT << RT_IDX_IDX_SHIFT);/* index */
 526                         break;
 527                 }
 528         case RT_IDX_RSS_MATCH:  /* Pass up matched RSS frames. */
 529                 {
 530                         value = RT_IDX_DST_RSS |        /* dest */
 531                             RT_IDX_TYPE_NICQ |  /* type */
 532                             (RT_IDX_RSS_MATCH_SLOT << RT_IDX_IDX_SHIFT);/* index */
 533                         break;
 534                 }
 535         case 0:         /* Clear the E-bit on an entry. */
 536                 {
 537                         value = RT_IDX_DST_DFLT_Q |     /* dest */
 538                             RT_IDX_TYPE_NICQ |  /* type */
 539                             (index << RT_IDX_IDX_SHIFT);/* index */
 540                         break;
 541                 }
 542         default:
 543                 QPRINTK(qdev, IFUP, ERR, "Mask type %d not yet supported.\n",
 544                         mask);
 545                 status = -EPERM;
 546                 goto exit;
 547         }
 548
 549         if (value) {
 550                 status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, 0);
 551                 if (status)
 552                         goto exit;
 553                 value |= (enable ? RT_IDX_E : 0);
 554                 ql_write32(qdev, RT_IDX, value);
 555                 ql_write32(qdev, RT_DATA, enable ? mask : 0);
 556         }
 557 exit:
 558         ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
 559         return status;
 560 }
 561
 562 static void ql_enable_interrupts(struct ql_adapter *qdev)
 563 {
 564         ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16) | INTR_EN_EI);
 565 }
 566
 567 static void ql_disable_interrupts(struct ql_adapter *qdev)
 568 {
 569         ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16));
 570 }
 571
 572 /* If we're running with multiple MSI-X vectors then we enable on the fly.
 573  * Otherwise, we may have multiple outstanding workers and don't want to
 574  * enable until the last one finishes. In this case, the irq_cnt gets
 575  * incremented everytime we queue a worker and decremented everytime
 576  * a worker finishes.  Once it hits zero we enable the interrupt.
 577  */
 578 u32 ql_enable_completion_interrupt(struct ql_adapter *qdev, u32 intr)
 579 {
 580         u32 var = 0;
 581         unsigned long hw_flags = 0;
 582         struct intr_context *ctx = qdev->intr_context + intr;
 583
 584         if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags) && intr)) {
 585                 /* Always enable if we're MSIX multi interrupts and
 586                  * it's not the default (zeroeth) interrupt.
 587                  */
 588                 ql_write32(qdev, INTR_EN,
 589                            ctx->intr_en_mask);
 590                 var = ql_read32(qdev, STS);
 591                 return var;
 592         }
 593
 594         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
 595         if (atomic_dec_and_test(&ctx->irq_cnt)) {
 596                 ql_write32(qdev, INTR_EN,
 597                            ctx->intr_en_mask);
 598                 var = ql_read32(qdev, STS);
 599         }
 600         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
 601         return var;
 602 }
 603
 604 static u32 ql_disable_completion_interrupt(struct ql_adapter *qdev, u32 intr)
 605 {
 606         u32 var = 0;
 607         unsigned long hw_flags;
 608         struct intr_context *ctx;
 609
 610         /* HW disables for us if we're MSIX multi interrupts and
 611          * it's not the default (zeroeth) interrupt.
 612          */
 613         if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags) && intr))
 614                 return 0;
 615
 616         ctx = qdev->intr_context + intr;
 617         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
 618         if (!atomic_read(&ctx->irq_cnt)) {
 619                 ql_write32(qdev, INTR_EN,
 620                 ctx->intr_dis_mask);
 621                 var = ql_read32(qdev, STS);
 622         }
 623         atomic_inc(&ctx->irq_cnt);
 624         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
 625         return var;
 626 }
 627
 628 static void ql_enable_all_completion_interrupts(struct ql_adapter *qdev)
 629 {
 630         int i;
 631         for (i = 0; i < qdev->intr_count; i++) {
 632                 /* The enable call does a atomic_dec_and_test
 633                  * and enables only if the result is zero.
 634                  * So we precharge it here.
 635                  */
 636                 if (unlikely(!test_bit(QL_MSIX_ENABLED, &qdev->flags) ||
 637                         i == 0))
 638                         atomic_set(&qdev->intr_context[i].irq_cnt, 1);
 639                 ql_enable_completion_interrupt(qdev, i);
 640         }
 641
 642 }
 643
 644 static int ql_read_flash_word(struct ql_adapter *qdev, int offset, __le32 *data)
 645 {
 646         int status = 0;
 647         /* wait for reg to come ready */
 648         status = ql_wait_reg_rdy(qdev,
 649                         FLASH_ADDR, FLASH_ADDR_RDY, FLASH_ADDR_ERR);
 650         if (status)
 651                 goto exit;
 652         /* set up for reg read */
 653         ql_write32(qdev, FLASH_ADDR, FLASH_ADDR_R | offset);
 654         /* wait for reg to come ready */
 655         status = ql_wait_reg_rdy(qdev,
 656                         FLASH_ADDR, FLASH_ADDR_RDY, FLASH_ADDR_ERR);
 657         if (status)
 658                 goto exit;
 659          /* This data is stored on flash as an array of
 660          * __le32.  Since ql_read32() returns cpu endian
 661          * we need to swap it back.
 662          */
 663         *data = cpu_to_le32(ql_read32(qdev, FLASH_DATA));
 664 exit:
 665         return status;
 666 }
 667
 668 static int ql_get_flash_params(struct ql_adapter *qdev)
 669 {
 670         int i;
 671         int status;
 672         __le32 *p = (__le32 *)&qdev->flash;
 673         u32 offset = 0;
 674
 675         /* Second function's parameters follow the first
 676          * function's.
 677          */
 678         if (qdev->func)
 679                 offset = sizeof(qdev->flash) / sizeof(u32);
 680
 681         if (ql_sem_spinlock(qdev, SEM_FLASH_MASK))
 682                 return -ETIMEDOUT;
 683
 684         for (i = 0; i < sizeof(qdev->flash) / sizeof(u32); i++, p++) {
 685                 status = ql_read_flash_word(qdev, i+offset, p);
 686                 if (status) {
 687                         QPRINTK(qdev, IFUP, ERR, "Error reading flash.\n");
 688                         goto exit;
 689                 }
 690
 691         }
 692 exit:
 693         ql_sem_unlock(qdev, SEM_FLASH_MASK);
 694         return status;
 695 }
 696
 697 /* xgmac register are located behind the xgmac_addr and xgmac_data
 698  * register pair.  Each read/write requires us to wait for the ready
 699  * bit before reading/writing the data.
 700  */
 701 static int ql_write_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 data)
 702 {
 703         int status;
 704         /* wait for reg to come ready */
 705         status = ql_wait_reg_rdy(qdev,
 706                         XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
 707         if (status)
 708                 return status;
 709         /* write the data to the data reg */
 710         ql_write32(qdev, XGMAC_DATA, data);
 711         /* trigger the write */
 712         ql_write32(qdev, XGMAC_ADDR, reg);
 713         return status;
 714 }
 715
 716 /* xgmac register are located behind the xgmac_addr and xgmac_data
 717  * register pair.  Each read/write requires us to wait for the ready
 718  * bit before reading/writing the data.
 719  */
 720 int ql_read_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 *data)
 721 {
 722         int status = 0;
 723         /* wait for reg to come ready */
 724         status = ql_wait_reg_rdy(qdev,
 725                         XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
 726         if (status)
 727                 goto exit;
 728         /* set up for reg read */
 729         ql_write32(qdev, XGMAC_ADDR, reg | XGMAC_ADDR_R);
 730         /* wait for reg to come ready */
 731         status = ql_wait_reg_rdy(qdev,
 732                         XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
 733         if (status)
 734                 goto exit;
 735         /* get the data */
 736         *data = ql_read32(qdev, XGMAC_DATA);
 737 exit:
 738         return status;
 739 }
 740
 741 /* This is used for reading the 64-bit statistics regs. */
 742 int ql_read_xgmac_reg64(struct ql_adapter *qdev, u32 reg, u64 *data)
 743 {
 744         int status = 0;
 745         u32 hi = 0;
 746         u32 lo = 0;
 747
 748         status = ql_read_xgmac_reg(qdev, reg, &lo);
 749         if (status)
 750                 goto exit;
 751
 752         status = ql_read_xgmac_reg(qdev, reg + 4, &hi);
 753         if (status)
 754                 goto exit;
 755
 756         *data = (u64) lo | ((u64) hi << 32);
 757
 758 exit:
 759         return status;
 760 }
 761
 762 /* Take the MAC Core out of reset.
 763  * Enable statistics counting.
 764  * Take the transmitter/receiver out of reset.
 765  * This functionality may be done in the MPI firmware at a
 766  * later date.
 767  */
 768 static int ql_port_initialize(struct ql_adapter *qdev)
 769 {
 770         int status = 0;
 771         u32 data;
 772
 773         if (ql_sem_trylock(qdev, qdev->xg_sem_mask)) {
 774                 /* Another function has the semaphore, so
 775                  * wait for the port init bit to come ready.
 776                  */
 777                 QPRINTK(qdev, LINK, INFO,
 778                         "Another function has the semaphore, so wait for the port init bit to come ready.\n");
 779                 status = ql_wait_reg_rdy(qdev, STS, qdev->port_init, 0);
 780                 if (status) {
 781                         QPRINTK(qdev, LINK, CRIT,
 782                                 "Port initialize timed out.\n");
 783                 }
 784                 return status;
 785         }
 786
 787         QPRINTK(qdev, LINK, INFO, "Got xgmac semaphore!.\n");
 788         /* Set the core reset. */
 789         status = ql_read_xgmac_reg(qdev, GLOBAL_CFG, &data);
 790         if (status)
 791                 goto end;
 792         data |= GLOBAL_CFG_RESET;
 793         status = ql_write_xgmac_reg(qdev, GLOBAL_CFG, data);
 794         if (status)
 795                 goto end;
 796
 797         /* Clear the core reset and turn on jumbo for receiver. */
 798         data &= ~GLOBAL_CFG_RESET;      /* Clear core reset. */
 799         data |= GLOBAL_CFG_JUMBO;       /* Turn on jumbo. */
 800         data |= GLOBAL_CFG_TX_STAT_EN;
 801         data |= GLOBAL_CFG_RX_STAT_EN;
 802         status = ql_write_xgmac_reg(qdev, GLOBAL_CFG, data);
 803         if (status)
 804                 goto end;
 805
 806         /* Enable transmitter, and clear it's reset. */
 807         status = ql_read_xgmac_reg(qdev, TX_CFG, &data);
 808         if (status)
 809                 goto end;
 810         data &= ~TX_CFG_RESET;  /* Clear the TX MAC reset. */
 811         data |= TX_CFG_EN;      /* Enable the transmitter. */
 812         status = ql_write_xgmac_reg(qdev, TX_CFG, data);
 813         if (status)
 814                 goto end;
 815
 816         /* Enable receiver and clear it's reset. */
 817         status = ql_read_xgmac_reg(qdev, RX_CFG, &data);
 818         if (status)
 819                 goto end;
 820         data &= ~RX_CFG_RESET;  /* Clear the RX MAC reset. */
 821         data |= RX_CFG_EN;      /* Enable the receiver. */
 822         status = ql_write_xgmac_reg(qdev, RX_CFG, data);
 823         if (status)
 824                 goto end;
 825
 826         /* Turn on jumbo. */
 827         status =
 828             ql_write_xgmac_reg(qdev, MAC_TX_PARAMS, MAC_TX_PARAMS_JUMBO | (0x2580 << 16));
 829         if (status)
 830                 goto end;
 831         status =
 832             ql_write_xgmac_reg(qdev, MAC_RX_PARAMS, 0x2580);
 833         if (status)
 834                 goto end;
 835
 836         /* Signal to the world that the port is enabled.        */
 837         ql_write32(qdev, STS, ((qdev->port_init << 16) | qdev->port_init));
 838 end:
 839         ql_sem_unlock(qdev, qdev->xg_sem_mask);
 840         return status;
 841 }
 842
 843 /* Get the next large buffer. */
 844 static struct bq_desc *ql_get_curr_lbuf(struct rx_ring *rx_ring)
 845 {
 846         struct bq_desc *lbq_desc = &rx_ring->lbq[rx_ring->lbq_curr_idx];
 847         rx_ring->lbq_curr_idx++;
 848         if (rx_ring->lbq_curr_idx == rx_ring->lbq_len)
 849                 rx_ring->lbq_curr_idx = 0;
 850         rx_ring->lbq_free_cnt++;
 851         return lbq_desc;
 852 }
 853
 854 /* Get the next small buffer. */
 855 static struct bq_desc *ql_get_curr_sbuf(struct rx_ring *rx_ring)
 856 {
 857         struct bq_desc *sbq_desc = &rx_ring->sbq[rx_ring->sbq_curr_idx];
 858         rx_ring->sbq_curr_idx++;
 859         if (rx_ring->sbq_curr_idx == rx_ring->sbq_len)
 860                 rx_ring->sbq_curr_idx = 0;
 861         rx_ring->sbq_free_cnt++;
 862         return sbq_desc;
 863 }
 864
 865 /* Update an rx ring index. */
 866 static void ql_update_cq(struct rx_ring *rx_ring)
 867 {
 868         rx_ring->cnsmr_idx++;
 869         rx_ring->curr_entry++;
 870         if (unlikely(rx_ring->cnsmr_idx == rx_ring->cq_len)) {
 871                 rx_ring->cnsmr_idx = 0;
 872                 rx_ring->curr_entry = rx_ring->cq_base;
 873         }
 874 }
 875
 876 static void ql_write_cq_idx(struct rx_ring *rx_ring)
 877 {
 878         ql_write_db_reg(rx_ring->cnsmr_idx, rx_ring->cnsmr_idx_db_reg);
 879 }
 880
 881 /* Process (refill) a large buffer queue. */
 882 static void ql_update_lbq(struct ql_adapter *qdev, struct rx_ring *rx_ring)
 883 {
 884         int clean_idx = rx_ring->lbq_clean_idx;
 885         struct bq_desc *lbq_desc;
 886         u64 map;
 887         int i;
 888
 889         while (rx_ring->lbq_free_cnt > 16) {
 890                 for (i = 0; i < 16; i++) {
 891                         QPRINTK(qdev, RX_STATUS, DEBUG,
 892                                 "lbq: try cleaning clean_idx = %d.\n",
 893                                 clean_idx);
 894                         lbq_desc = &rx_ring->lbq[clean_idx];
 895                         if (lbq_desc->p.lbq_page == NULL) {
 896                                 QPRINTK(qdev, RX_STATUS, DEBUG,
 897                                         "lbq: getting new page for index %d.\n",
 898                                         lbq_desc->index);
 899                                 lbq_desc->p.lbq_page = alloc_page(GFP_ATOMIC);
 900                                 if (lbq_desc->p.lbq_page == NULL) {
 901                                         QPRINTK(qdev, RX_STATUS, ERR,
 902                                                 "Couldn't get a page.\n");
 903                                         return;
 904                                 }
 905                                 map = pci_map_page(qdev->pdev,
 906                                                    lbq_desc->p.lbq_page,
 907                                                    0, PAGE_SIZE,
 908                                                    PCI_DMA_FROMDEVICE);
 909                                 if (pci_dma_mapping_error(qdev->pdev, map)) {
 910                                         QPRINTK(qdev, RX_STATUS, ERR,
 911                                                 "PCI mapping failed.\n");
 912                                         return;
 913                                 }
 914                                 pci_unmap_addr_set(lbq_desc, mapaddr, map);
 915                                 pci_unmap_len_set(lbq_desc, maplen, PAGE_SIZE);
 916                                 *lbq_desc->addr = cpu_to_le64(map);
 917                         }
 918                         clean_idx++;
 919                         if (clean_idx == rx_ring->lbq_len)
 920                                 clean_idx = 0;
 921                 }
 922
 923                 rx_ring->lbq_clean_idx = clean_idx;
 924                 rx_ring->lbq_prod_idx += 16;
 925                 if (rx_ring->lbq_prod_idx == rx_ring->lbq_len)
 926                         rx_ring->lbq_prod_idx = 0;
 927                 QPRINTK(qdev, RX_STATUS, DEBUG,
 928                         "lbq: updating prod idx = %d.\n",
 929                         rx_ring->lbq_prod_idx);
 930                 ql_write_db_reg(rx_ring->lbq_prod_idx,
 931                                 rx_ring->lbq_prod_idx_db_reg);
 932                 rx_ring->lbq_free_cnt -= 16;
 933         }
 934 }
 935
 936 /* Process (refill) a small buffer queue. */
 937 static void ql_update_sbq(struct ql_adapter *qdev, struct rx_ring *rx_ring)
 938 {
 939         int clean_idx = rx_ring->sbq_clean_idx;
 940         struct bq_desc *sbq_desc;
 941         u64 map;
 942         int i;
 943
 944         while (rx_ring->sbq_free_cnt > 16) {
 945                 for (i = 0; i < 16; i++) {
 946                         sbq_desc = &rx_ring->sbq[clean_idx];
 947                         QPRINTK(qdev, RX_STATUS, DEBUG,
 948                                 "sbq: try cleaning clean_idx = %d.\n",
 949                                 clean_idx);
 950                         if (sbq_desc->p.skb == NULL) {
 951                                 QPRINTK(qdev, RX_STATUS, DEBUG,
 952                                         "sbq: getting new skb for index %d.\n",
 953                                         sbq_desc->index);
 954                                 sbq_desc->p.skb =
 955                                     netdev_alloc_skb(qdev->ndev,
 956                                                      rx_ring->sbq_buf_size);
 957                                 if (sbq_desc->p.skb == NULL) {
 958                                         QPRINTK(qdev, PROBE, ERR,
 959                                                 "Couldn't get an skb.\n");
 960                                         rx_ring->sbq_clean_idx = clean_idx;
 961                                         return;
 962                                 }
 963                                 skb_reserve(sbq_desc->p.skb, QLGE_SB_PAD);
 964                                 map = pci_map_single(qdev->pdev,
 965                                                      sbq_desc->p.skb->data,
 966                                                      rx_ring->sbq_buf_size /
 967                                                      2, PCI_DMA_FROMDEVICE);
 968                                 if (pci_dma_mapping_error(qdev->pdev, map)) {
 969                                         QPRINTK(qdev, IFUP, ERR, "PCI mapping failed.\n");
 970                                         rx_ring->sbq_clean_idx = clean_idx;
 971                                         return;
 972                                 }
 973                                 pci_unmap_addr_set(sbq_desc, mapaddr, map);
 974                                 pci_unmap_len_set(sbq_desc, maplen,
 975                                                   rx_ring->sbq_buf_size / 2);
 976                                 *sbq_desc->addr = cpu_to_le64(map);
 977                         }
 978
 979                         clean_idx++;
 980                         if (clean_idx == rx_ring->sbq_len)
 981                                 clean_idx = 0;
 982                 }
 983                 rx_ring->sbq_clean_idx = clean_idx;
 984                 rx_ring->sbq_prod_idx += 16;
 985                 if (rx_ring->sbq_prod_idx == rx_ring->sbq_len)
 986                         rx_ring->sbq_prod_idx = 0;
 987                 QPRINTK(qdev, RX_STATUS, DEBUG,
 988                         "sbq: updating prod idx = %d.\n",
 989                         rx_ring->sbq_prod_idx);
 990                 ql_write_db_reg(rx_ring->sbq_prod_idx,
 991                                 rx_ring->sbq_prod_idx_db_reg);
 992
 993                 rx_ring->sbq_free_cnt -= 16;
 994         }
 995 }
 996
 997 static void ql_update_buffer_queues(struct ql_adapter *qdev,
 998                                     struct rx_ring *rx_ring)
 999 {
1000         ql_update_sbq(qdev, rx_ring);
1001         ql_update_lbq(qdev, rx_ring);
1002 }
1003
1004 /* Unmaps tx buffers.  Can be called from send() if a pci mapping
1005  * fails at some stage, or from the interrupt when a tx completes.
1006  */
1007 static void ql_unmap_send(struct ql_adapter *qdev,
1008                           struct tx_ring_desc *tx_ring_desc, int mapped)
1009 {
1010         int i;
1011         for (i = 0; i < mapped; i++) {
1012                 if (i == 0 || (i == 7 && mapped > 7)) {
1013                         /*
1014                          * Unmap the skb->data area, or the
1015                          * external sglist (AKA the Outbound
1016                          * Address List (OAL)).
1017                          * If its the zeroeth element, then it's
1018                          * the skb->data area.  If it's the 7th
1019                          * element and there is more than 6 frags,
1020                          * then its an OAL.
1021                          */
1022                         if (i == 7) {
1023                                 QPRINTK(qdev, TX_DONE, DEBUG,
1024                                         "unmapping OAL area.\n");
1025                         }
1026                         pci_unmap_single(qdev->pdev,
1027                                          pci_unmap_addr(&tx_ring_desc->map[i],
1028                                                         mapaddr),
1029                                          pci_unmap_len(&tx_ring_desc->map[i],
1030                                                        maplen),
1031                                          PCI_DMA_TODEVICE);
1032                 } else {
1033                         QPRINTK(qdev, TX_DONE, DEBUG, "unmapping frag %d.\n",
1034                                 i);
1035                         pci_unmap_page(qdev->pdev,
1036                                        pci_unmap_addr(&tx_ring_desc->map[i],
1037                                                       mapaddr),
1038                                        pci_unmap_len(&tx_ring_desc->map[i],
1039                                                      maplen), PCI_DMA_TODEVICE);
1040                 }
1041         }
1042
1043 }
1044
1045 /* Map the buffers for this transmit.  This will return
1046  * NETDEV_TX_BUSY or NETDEV_TX_OK based on success.
1047  */
1048 static int ql_map_send(struct ql_adapter *qdev,
1049                        struct ob_mac_iocb_req *mac_iocb_ptr,
1050                        struct sk_buff *skb, struct tx_ring_desc *tx_ring_desc)
1051 {
1052         int len = skb_headlen(skb);
1053         dma_addr_t map;
1054         int frag_idx, err, map_idx = 0;
1055         struct tx_buf_desc *tbd = mac_iocb_ptr->tbd;
1056         int frag_cnt = skb_shinfo(skb)->nr_frags;
1057
1058         if (frag_cnt) {
1059                 QPRINTK(qdev, TX_QUEUED, DEBUG, "frag_cnt = %d.\n", frag_cnt);
1060         }
1061         /*
1062          * Map the skb buffer first.
1063          */
1064         map = pci_map_single(qdev->pdev, skb->data, len, PCI_DMA_TODEVICE);
1065
1066         err = pci_dma_mapping_error(qdev->pdev, map);
1067         if (err) {
1068                 QPRINTK(qdev, TX_QUEUED, ERR,
1069                         "PCI mapping failed with error: %d\n", err);
1070
1071                 return NETDEV_TX_BUSY;
1072         }
1073
1074         tbd->len = cpu_to_le32(len);
1075         tbd->addr = cpu_to_le64(map);
1076         pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr, map);
1077         pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen, len);
1078         map_idx++;
1079
1080         /*
1081          * This loop fills the remainder of the 8 address descriptors
1082          * in the IOCB.  If there are more than 7 fragments, then the
1083          * eighth address desc will point to an external list (OAL).
1084          * When this happens, the remainder of the frags will be stored
1085          * in this list.
1086          */
1087         for (frag_idx = 0; frag_idx < frag_cnt; frag_idx++, map_idx++) {
1088                 skb_frag_t *frag = &skb_shinfo(skb)->frags[frag_idx];
1089                 tbd++;
1090                 if (frag_idx == 6 && frag_cnt > 7) {
1091                         /* Let's tack on an sglist.
1092                          * Our control block will now
1093                          * look like this:
1094                          * iocb->seg[0] = skb->data
1095                          * iocb->seg[1] = frag[0]
1096                          * iocb->seg[2] = frag[1]
1097                          * iocb->seg[3] = frag[2]
1098                          * iocb->seg[4] = frag[3]
1099                          * iocb->seg[5] = frag[4]
1100                          * iocb->seg[6] = frag[5]
1101                          * iocb->seg[7] = ptr to OAL (external sglist)
1102                          * oal->seg[0] = frag[6]
1103                          * oal->seg[1] = frag[7]
1104                          * oal->seg[2] = frag[8]
1105                          * oal->seg[3] = frag[9]
1106                          * oal->seg[4] = frag[10]
1107                          *      etc...
1108                          */
1109                         /* Tack on the OAL in the eighth segment of IOCB. */
1110                         map = pci_map_single(qdev->pdev, &tx_ring_desc->oal,
1111                                              sizeof(struct oal),
1112                                              PCI_DMA_TODEVICE);
1113                         err = pci_dma_mapping_error(qdev->pdev, map);
1114                         if (err) {
1115                                 QPRINTK(qdev, TX_QUEUED, ERR,
1116                                         "PCI mapping outbound address list with error: %d\n",
1117                                         err);
1118                                 goto map_error;
1119                         }
1120
1121                         tbd->addr = cpu_to_le64(map);
1122                         /*
1123                          * The length is the number of fragments
1124                          * that remain to be mapped times the length
1125                          * of our sglist (OAL).
1126                          */
1127                         tbd->len =
1128                             cpu_to_le32((sizeof(struct tx_buf_desc) *
1129                                          (frag_cnt - frag_idx)) | TX_DESC_C);
1130                         pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr,
1131                                            map);
1132                         pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen,
1133                                           sizeof(struct oal));
1134                         tbd = (struct tx_buf_desc *)&tx_ring_desc->oal;
1135                         map_idx++;
1136                 }
1137
1138                 map =
1139                     pci_map_page(qdev->pdev, frag->page,
1140                                  frag->page_offset, frag->size,
1141                                  PCI_DMA_TODEVICE);
1142
1143                 err = pci_dma_mapping_error(qdev->pdev, map);
1144                 if (err) {
1145                         QPRINTK(qdev, TX_QUEUED, ERR,
1146                                 "PCI mapping frags failed with error: %d.\n",
1147                                 err);
1148                         goto map_error;
1149                 }
1150
1151                 tbd->addr = cpu_to_le64(map);
1152                 tbd->len = cpu_to_le32(frag->size);
1153                 pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr, map);
1154                 pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen,
1155                                   frag->size);
1156
1157         }
1158         /* Save the number of segments we've mapped. */
1159         tx_ring_desc->map_cnt = map_idx;
1160         /* Terminate the last segment. */
1161         tbd->len = cpu_to_le32(le32_to_cpu(tbd->len) | TX_DESC_E);
1162         return NETDEV_TX_OK;
1163
1164 map_error:
1165         /*
1166          * If the first frag mapping failed, then i will be zero.
1167          * This causes the unmap of the skb->data area.  Otherwise
1168          * we pass in the number of frags that mapped successfully
1169          * so they can be umapped.
1170          */
1171         ql_unmap_send(qdev, tx_ring_desc, map_idx);
1172         return NETDEV_TX_BUSY;
1173 }
1174
1175 static void ql_realign_skb(struct sk_buff *skb, int len)
1176 {
1177         void *temp_addr = skb->data;
1178
1179         /* Undo the skb_reserve(skb,32) we did before
1180          * giving to hardware, and realign data on
1181          * a 2-byte boundary.
1182          */
1183         skb->data -= QLGE_SB_PAD - NET_IP_ALIGN;
1184         skb->tail -= QLGE_SB_PAD - NET_IP_ALIGN;
1185         skb_copy_to_linear_data(skb, temp_addr,
1186                 (unsigned int)len);
1187 }
1188
1189 /*
1190  * This function builds an skb for the given inbound
1191  * completion.  It will be rewritten for readability in the near
1192  * future, but for not it works well.
1193  */
1194 static struct sk_buff *ql_build_rx_skb(struct ql_adapter *qdev,
1195                                        struct rx_ring *rx_ring,
1196                                        struct ib_mac_iocb_rsp *ib_mac_rsp)
1197 {
1198         struct bq_desc *lbq_desc;
1199         struct bq_desc *sbq_desc;
1200         struct sk_buff *skb = NULL;
1201         u32 length = le32_to_cpu(ib_mac_rsp->data_len);
1202        u32 hdr_len = le32_to_cpu(ib_mac_rsp->hdr_len);
1203
1204         /*
1205          * Handle the header buffer if present.
1206          */
1207         if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HV &&
1208             ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1209                 QPRINTK(qdev, RX_STATUS, DEBUG, "Header of %d bytes in small buffer.\n", hdr_len);
1210                 /*
1211                  * Headers fit nicely into a small buffer.
1212                  */
1213                 sbq_desc = ql_get_curr_sbuf(rx_ring);
1214                 pci_unmap_single(qdev->pdev,
1215                                 pci_unmap_addr(sbq_desc, mapaddr),
1216                                 pci_unmap_len(sbq_desc, maplen),
1217                                 PCI_DMA_FROMDEVICE);
1218                 skb = sbq_desc->p.skb;
1219                 ql_realign_skb(skb, hdr_len);
1220                 skb_put(skb, hdr_len);
1221                 sbq_desc->p.skb = NULL;
1222         }
1223
1224         /*
1225          * Handle the data buffer(s).
1226          */
1227         if (unlikely(!length)) {        /* Is there data too? */
1228                 QPRINTK(qdev, RX_STATUS, DEBUG,
1229                         "No Data buffer in this packet.\n");
1230                 return skb;
1231         }
1232
1233         if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DS) {
1234                 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1235                         QPRINTK(qdev, RX_STATUS, DEBUG,
1236                                 "Headers in small, data of %d bytes in small, combine them.\n", length);
1237                         /*
1238                          * Data is less than small buffer size so it's
1239                          * stuffed in a small buffer.
1240                          * For this case we append the data
1241                          * from the "data" small buffer to the "header" small
1242                          * buffer.
1243                          */
1244                         sbq_desc = ql_get_curr_sbuf(rx_ring);
1245                         pci_dma_sync_single_for_cpu(qdev->pdev,
1246                                                     pci_unmap_addr
1247                                                     (sbq_desc, mapaddr),
1248                                                     pci_unmap_len
1249                                                     (sbq_desc, maplen),
1250                                                     PCI_DMA_FROMDEVICE);
1251                         memcpy(skb_put(skb, length),
1252                                sbq_desc->p.skb->data, length);
1253                         pci_dma_sync_single_for_device(qdev->pdev,
1254                                                        pci_unmap_addr
1255                                                        (sbq_desc,
1256                                                         mapaddr),
1257                                                        pci_unmap_len
1258                                                        (sbq_desc,
1259                                                         maplen),
1260                                                        PCI_DMA_FROMDEVICE);
1261                 } else {
1262                         QPRINTK(qdev, RX_STATUS, DEBUG,
1263                                 "%d bytes in a single small buffer.\n", length);
1264                         sbq_desc = ql_get_curr_sbuf(rx_ring);
1265                         skb = sbq_desc->p.skb;
1266                         ql_realign_skb(skb, length);
1267                         skb_put(skb, length);
1268                         pci_unmap_single(qdev->pdev,
1269                                          pci_unmap_addr(sbq_desc,
1270                                                         mapaddr),
1271                                          pci_unmap_len(sbq_desc,
1272                                                        maplen),
1273                                          PCI_DMA_FROMDEVICE);
1274                         sbq_desc->p.skb = NULL;
1275                 }
1276         } else if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DL) {
1277                 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1278                         QPRINTK(qdev, RX_STATUS, DEBUG,
1279                                 "Header in small, %d bytes in large. Chain large to small!\n", length);
1280                         /*
1281                          * The data is in a single large buffer.  We
1282                          * chain it to the header buffer's skb and let
1283                          * it rip.
1284                          */
1285                         lbq_desc = ql_get_curr_lbuf(rx_ring);
1286                         pci_unmap_page(qdev->pdev,
1287                                        pci_unmap_addr(lbq_desc,
1288                                                       mapaddr),
1289                                        pci_unmap_len(lbq_desc, maplen),
1290                                        PCI_DMA_FROMDEVICE);
1291                         QPRINTK(qdev, RX_STATUS, DEBUG,
1292                                 "Chaining page to skb.\n");
1293                         skb_fill_page_desc(skb, 0, lbq_desc->p.lbq_page,
1294                                            0, length);
1295                         skb->len += length;
1296                         skb->data_len += length;
1297                         skb->truesize += length;
1298                         lbq_desc->p.lbq_page = NULL;
1299                 } else {
1300                         /*
1301                          * The headers and data are in a single large buffer. We
1302                          * copy it to a new skb and let it go. This can happen with
1303                          * jumbo mtu on a non-TCP/UDP frame.
1304                          */
1305                         lbq_desc = ql_get_curr_lbuf(rx_ring);
1306                         skb = netdev_alloc_skb(qdev->ndev, length);
1307                         if (skb == NULL) {
1308                                 QPRINTK(qdev, PROBE, DEBUG,
1309                                         "No skb available, drop the packet.\n");
1310                                 return NULL;
1311                         }
1312                         pci_unmap_page(qdev->pdev,
1313                                        pci_unmap_addr(lbq_desc,
1314                                                       mapaddr),
1315                                        pci_unmap_len(lbq_desc, maplen),
1316                                        PCI_DMA_FROMDEVICE);
1317                         skb_reserve(skb, NET_IP_ALIGN);
1318                         QPRINTK(qdev, RX_STATUS, DEBUG,
1319                                 "%d bytes of headers and data in large. Chain page to new skb and pull tail.\n", length);
1320                         skb_fill_page_desc(skb, 0, lbq_desc->p.lbq_page,
1321                                            0, length);
1322                         skb->len += length;
1323                         skb->data_len += length;
1324                         skb->truesize += length;
1325                         length -= length;
1326                         lbq_desc->p.lbq_page = NULL;
1327                         __pskb_pull_tail(skb,
1328                                 (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) ?
1329                                 VLAN_ETH_HLEN : ETH_HLEN);
1330                 }
1331         } else {
1332                 /*
1333                  * The data is in a chain of large buffers
1334                  * pointed to by a small buffer.  We loop
1335                  * thru and chain them to the our small header
1336                  * buffer's skb.
1337                  * frags:  There are 18 max frags and our small
1338                  *         buffer will hold 32 of them. The thing is,
1339                  *         we'll use 3 max for our 9000 byte jumbo
1340                  *         frames.  If the MTU goes up we could
1341                  *          eventually be in trouble.
1342                  */
1343                 int size, offset, i = 0;
1344                 __le64 *bq, bq_array[8];
1345                 sbq_desc = ql_get_curr_sbuf(rx_ring);
1346                 pci_unmap_single(qdev->pdev,
1347                                  pci_unmap_addr(sbq_desc, mapaddr),
1348                                  pci_unmap_len(sbq_desc, maplen),
1349                                  PCI_DMA_FROMDEVICE);
1350                 if (!(ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS)) {
1351                         /*
1352                          * This is an non TCP/UDP IP frame, so
1353                          * the headers aren't split into a small
1354                          * buffer.  We have to use the small buffer
1355                          * that contains our sg list as our skb to
1356                          * send upstairs. Copy the sg list here to
1357                          * a local buffer and use it to find the
1358                          * pages to chain.
1359                          */
1360                         QPRINTK(qdev, RX_STATUS, DEBUG,
1361                                 "%d bytes of headers & data in chain of large.\n", length);
1362                         skb = sbq_desc->p.skb;
1363                         bq = &bq_array[0];
1364                         memcpy(bq, skb->data, sizeof(bq_array));
1365                         sbq_desc->p.skb = NULL;
1366                         skb_reserve(skb, NET_IP_ALIGN);
1367                 } else {
1368                         QPRINTK(qdev, RX_STATUS, DEBUG,
1369                                 "Headers in small, %d bytes of data in chain of large.\n", length);
1370                         bq = (__le64 *)sbq_desc->p.skb->data;
1371                 }
1372                 while (length > 0) {
1373                         lbq_desc = ql_get_curr_lbuf(rx_ring);
1374                         pci_unmap_page(qdev->pdev,
1375                                        pci_unmap_addr(lbq_desc,
1376                                                       mapaddr),
1377                                        pci_unmap_len(lbq_desc,
1378                                                      maplen),
1379                                        PCI_DMA_FROMDEVICE);
1380                         size = (length < PAGE_SIZE) ? length : PAGE_SIZE;
1381                         offset = 0;
1382
1383                         QPRINTK(qdev, RX_STATUS, DEBUG,
1384                                 "Adding page %d to skb for %d bytes.\n",
1385                                 i, size);
1386                         skb_fill_page_desc(skb, i, lbq_desc->p.lbq_page,
1387                                            offset, size);
1388                         skb->len += size;
1389                         skb->data_len += size;
1390                         skb->truesize += size;
1391                         length -= size;
1392                         lbq_desc->p.lbq_page = NULL;
1393                         bq++;
1394                         i++;
1395                 }
1396                 __pskb_pull_tail(skb, (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) ?
1397                                 VLAN_ETH_HLEN : ETH_HLEN);
1398         }
1399         return skb;
1400 }
1401
1402 /* Process an inbound completion from an rx ring. */
1403 static void ql_process_mac_rx_intr(struct ql_adapter *qdev,
1404                                    struct rx_ring *rx_ring,
1405                                    struct ib_mac_iocb_rsp *ib_mac_rsp)
1406 {
1407         struct net_device *ndev = qdev->ndev;
1408         struct sk_buff *skb = NULL;
1409
1410         QL_DUMP_IB_MAC_RSP(ib_mac_rsp);
1411
1412         skb = ql_build_rx_skb(qdev, rx_ring, ib_mac_rsp);
1413         if (unlikely(!skb)) {
1414                 QPRINTK(qdev, RX_STATUS, DEBUG,
1415                         "No skb available, drop packet.\n");
1416                 return;
1417         }
1418
1419         prefetch(skb->data);
1420         skb->dev = ndev;
1421         if (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) {
1422                 QPRINTK(qdev, RX_STATUS, DEBUG, "%s%s%s Multicast.\n",
1423                         (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1424                         IB_MAC_IOCB_RSP_M_HASH ? "Hash" : "",
1425                         (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1426                         IB_MAC_IOCB_RSP_M_REG ? "Registered" : "",
1427                         (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1428                         IB_MAC_IOCB_RSP_M_PROM ? "Promiscuous" : "");
1429         }
1430         if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_P) {
1431                 QPRINTK(qdev, RX_STATUS, DEBUG, "Promiscuous Packet.\n");
1432         }
1433         if (ib_mac_rsp->flags1 & (IB_MAC_IOCB_RSP_IE | IB_MAC_IOCB_RSP_TE)) {
1434                 QPRINTK(qdev, RX_STATUS, ERR,
1435                         "Bad checksum for this %s packet.\n",
1436                         ((ib_mac_rsp->
1437                           flags2 & IB_MAC_IOCB_RSP_T) ? "TCP" : "UDP"));
1438                 skb->ip_summed = CHECKSUM_NONE;
1439         } else if (qdev->rx_csum &&
1440                    ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_T) ||
1441                     ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_U) &&
1442                      !(ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_NU)))) {
1443                 QPRINTK(qdev, RX_STATUS, DEBUG, "RX checksum done!\n");
1444                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1445         }
1446         qdev->stats.rx_packets++;
1447         qdev->stats.rx_bytes += skb->len;
1448         skb->protocol = eth_type_trans(skb, ndev);
1449         if (qdev->vlgrp && (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V)) {
1450                 QPRINTK(qdev, RX_STATUS, DEBUG,
1451                         "Passing a VLAN packet upstream.\n");
1452                 vlan_hwaccel_receive_skb(skb, qdev->vlgrp,
1453                                 le16_to_cpu(ib_mac_rsp->vlan_id));
1454         } else {
1455                 QPRINTK(qdev, RX_STATUS, DEBUG,
1456                         "Passing a normal packet upstream.\n");
1457                 netif_receive_skb(skb);
1458         }
1459 }
1460
1461 /* Process an outbound completion from an rx ring. */
1462 static void ql_process_mac_tx_intr(struct ql_adapter *qdev,
1463                                    struct ob_mac_iocb_rsp *mac_rsp)
1464 {
1465         struct tx_ring *tx_ring;
1466         struct tx_ring_desc *tx_ring_desc;
1467
1468         QL_DUMP_OB_MAC_RSP(mac_rsp);
1469         tx_ring = &qdev->tx_ring[mac_rsp->txq_idx];
1470         tx_ring_desc = &tx_ring->q[mac_rsp->tid];
1471         ql_unmap_send(qdev, tx_ring_desc, tx_ring_desc->map_cnt);
1472         qdev->stats.tx_bytes += tx_ring_desc->map_cnt;
1473         qdev->stats.tx_packets++;
1474         dev_kfree_skb(tx_ring_desc->skb);
1475         tx_ring_desc->skb = NULL;
1476
1477         if (unlikely(mac_rsp->flags1 & (OB_MAC_IOCB_RSP_E |
1478                                         OB_MAC_IOCB_RSP_S |
1479                                         OB_MAC_IOCB_RSP_L |
1480                                         OB_MAC_IOCB_RSP_P | OB_MAC_IOCB_RSP_B))) {
1481                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_E) {
1482                         QPRINTK(qdev, TX_DONE, WARNING,
1483                                 "Total descriptor length did not match transfer length.\n");
1484                 }
1485                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_S) {
1486                         QPRINTK(qdev, TX_DONE, WARNING,
1487                                 "Frame too short to be legal, not sent.\n");
1488                 }
1489                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_L) {
1490                         QPRINTK(qdev, TX_DONE, WARNING,
1491                                 "Frame too long, but sent anyway.\n");
1492                 }
1493                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_B) {
1494                         QPRINTK(qdev, TX_DONE, WARNING,
1495                                 "PCI backplane error. Frame not sent.\n");
1496                 }
1497         }
1498         atomic_inc(&tx_ring->tx_count);
1499 }
1500
1501 /* Fire up a handler to reset the MPI processor. */
1502 void ql_queue_fw_error(struct ql_adapter *qdev)
1503 {
1504         netif_stop_queue(qdev->ndev);
1505         netif_carrier_off(qdev->ndev);
1506         queue_delayed_work(qdev->workqueue, &qdev->mpi_reset_work, 0);
1507 }
1508
1509 void ql_queue_asic_error(struct ql_adapter *qdev)
1510 {
1511         netif_stop_queue(qdev->ndev);
1512         netif_carrier_off(qdev->ndev);
1513         ql_disable_interrupts(qdev);
1514         /* Clear adapter up bit to signal the recovery
1515          * process that it shouldn't kill the reset worker
1516          * thread
1517          */
1518         clear_bit(QL_ADAPTER_UP, &qdev->flags);
1519         queue_delayed_work(qdev->workqueue, &qdev->asic_reset_work, 0);
1520 }
1521
1522 static void ql_process_chip_ae_intr(struct ql_adapter *qdev,
1523                                     struct ib_ae_iocb_rsp *ib_ae_rsp)
1524 {
1525         switch (ib_ae_rsp->event) {
1526         case MGMT_ERR_EVENT:
1527                 QPRINTK(qdev, RX_ERR, ERR,
1528                         "Management Processor Fatal Error.\n");
1529                 ql_queue_fw_error(qdev);
1530                 return;
1531
1532         case CAM_LOOKUP_ERR_EVENT:
1533                 QPRINTK(qdev, LINK, ERR,
1534                         "Multiple CAM hits lookup occurred.\n");
1535                 QPRINTK(qdev, DRV, ERR, "This event shouldn't occur.\n");
1536                 ql_queue_asic_error(qdev);
1537                 return;
1538
1539         case SOFT_ECC_ERROR_EVENT:
1540                 QPRINTK(qdev, RX_ERR, ERR, "Soft ECC error detected.\n");
1541                 ql_queue_asic_error(qdev);
1542                 break;
1543
1544         case PCI_ERR_ANON_BUF_RD:
1545                 QPRINTK(qdev, RX_ERR, ERR,
1546                         "PCI error occurred when reading anonymous buffers from rx_ring %d.\n",
1547                         ib_ae_rsp->q_id);
1548                 ql_queue_asic_error(qdev);
1549                 break;
1550
1551         default:
1552                 QPRINTK(qdev, DRV, ERR, "Unexpected event %d.\n",
1553                         ib_ae_rsp->event);
1554                 ql_queue_asic_error(qdev);
1555                 break;
1556         }
1557 }
1558
1559 static int ql_clean_outbound_rx_ring(struct rx_ring *rx_ring)
1560 {
1561         struct ql_adapter *qdev = rx_ring->qdev;
1562         u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1563         struct ob_mac_iocb_rsp *net_rsp = NULL;
1564         int count = 0;
1565
1566         /* While there are entries in the completion queue. */
1567         while (prod != rx_ring->cnsmr_idx) {
1568
1569                 QPRINTK(qdev, RX_STATUS, DEBUG,
1570                         "cq_id = %d, prod = %d, cnsmr = %d.\n.", rx_ring->cq_id,
1571                         prod, rx_ring->cnsmr_idx);
1572
1573                 net_rsp = (struct ob_mac_iocb_rsp *)rx_ring->curr_entry;
1574                 rmb();
1575                 switch (net_rsp->opcode) {
1576
1577                 case OPCODE_OB_MAC_TSO_IOCB:
1578                 case OPCODE_OB_MAC_IOCB:
1579                         ql_process_mac_tx_intr(qdev, net_rsp);
1580                         break;
1581                 default:
1582                         QPRINTK(qdev, RX_STATUS, DEBUG,
1583                                 "Hit default case, not handled! dropping the packet, opcode = %x.\n",
1584                                 net_rsp->opcode);
1585                 }
1586                 count++;
1587                 ql_update_cq(rx_ring);
1588                 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1589         }
1590         ql_write_cq_idx(rx_ring);
1591         if (netif_queue_stopped(qdev->ndev) && net_rsp != NULL) {
1592                 struct tx_ring *tx_ring = &qdev->tx_ring[net_rsp->txq_idx];
1593                 if (atomic_read(&tx_ring->queue_stopped) &&
1594                     (atomic_read(&tx_ring->tx_count) > (tx_ring->wq_len / 4)))
1595                         /*
1596                          * The queue got stopped because the tx_ring was full.
1597                          * Wake it up, because it's now at least 25% empty.
1598                          */
1599                         netif_wake_queue(qdev->ndev);
1600         }
1601
1602         return count;
1603 }
1604
1605 static int ql_clean_inbound_rx_ring(struct rx_ring *rx_ring, int budget)
1606 {
1607         struct ql_adapter *qdev = rx_ring->qdev;
1608         u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1609         struct ql_net_rsp_iocb *net_rsp;
1610         int count = 0;
1611
1612         /* While there are entries in the completion queue. */
1613         while (prod != rx_ring->cnsmr_idx) {
1614
1615                 QPRINTK(qdev, RX_STATUS, DEBUG,
1616                         "cq_id = %d, prod = %d, cnsmr = %d.\n.", rx_ring->cq_id,
1617                         prod, rx_ring->cnsmr_idx);
1618
1619                 net_rsp = rx_ring->curr_entry;
1620                 rmb();
1621                 switch (net_rsp->opcode) {
1622                 case OPCODE_IB_MAC_IOCB:
1623                         ql_process_mac_rx_intr(qdev, rx_ring,
1624                                                (struct ib_mac_iocb_rsp *)
1625                                                net_rsp);
1626                         break;
1627
1628                 case OPCODE_IB_AE_IOCB:
1629                         ql_process_chip_ae_intr(qdev, (struct ib_ae_iocb_rsp *)
1630                                                 net_rsp);
1631                         break;
1632                 default:
1633                         {
1634                                 QPRINTK(qdev, RX_STATUS, DEBUG,
1635                                         "Hit default case, not handled! dropping the packet, opcode = %x.\n",
1636                                         net_rsp->opcode);
1637                         }
1638                 }
1639                 count++;
1640                 ql_update_cq(rx_ring);
1641                 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1642                 if (count == budget)
1643                         break;
1644         }
1645         ql_update_buffer_queues(qdev, rx_ring);
1646         ql_write_cq_idx(rx_ring);
1647         return count;
1648 }
1649
1650 static int ql_napi_poll_msix(struct napi_struct *napi, int budget)
1651 {
1652         struct rx_ring *rx_ring = container_of(napi, struct rx_ring, napi);
1653         struct ql_adapter *qdev = rx_ring->qdev;
1654         int work_done = ql_clean_inbound_rx_ring(rx_ring, budget);
1655
1656         QPRINTK(qdev, RX_STATUS, DEBUG, "Enter, NAPI POLL cq_id = %d.\n",
1657                 rx_ring->cq_id);
1658
1659         if (work_done < budget) {
1660                 __netif_rx_complete(napi);
1661                 ql_enable_completion_interrupt(qdev, rx_ring->irq);
1662         }
1663         return work_done;
1664 }
1665
1666 static void ql_vlan_rx_register(struct net_device *ndev, struct vlan_group *grp)
1667 {
1668         struct ql_adapter *qdev = netdev_priv(ndev);
1669
1670         qdev->vlgrp = grp;
1671         if (grp) {
1672                 QPRINTK(qdev, IFUP, DEBUG, "Turning on VLAN in NIC_RCV_CFG.\n");
1673                 ql_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK |
1674                            NIC_RCV_CFG_VLAN_MATCH_AND_NON);
1675         } else {
1676                 QPRINTK(qdev, IFUP, DEBUG,
1677                         "Turning off VLAN in NIC_RCV_CFG.\n");
1678                 ql_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK);
1679         }
1680 }
1681
1682 static void ql_vlan_rx_add_vid(struct net_device *ndev, u16 vid)
1683 {
1684         struct ql_adapter *qdev = netdev_priv(ndev);
1685         u32 enable_bit = MAC_ADDR_E;
1686
1687         spin_lock(&qdev->hw_lock);
1688         if (ql_set_mac_addr_reg
1689             (qdev, (u8 *) &enable_bit, MAC_ADDR_TYPE_VLAN, vid)) {
1690                 QPRINTK(qdev, IFUP, ERR, "Failed to init vlan address.\n");
1691         }
1692         spin_unlock(&qdev->hw_lock);
1693 }
1694
1695 static void ql_vlan_rx_kill_vid(struct net_device *ndev, u16 vid)
1696 {
1697         struct ql_adapter *qdev = netdev_priv(ndev);
1698         u32 enable_bit = 0;
1699
1700         spin_lock(&qdev->hw_lock);
1701         if (ql_set_mac_addr_reg
1702             (qdev, (u8 *) &enable_bit, MAC_ADDR_TYPE_VLAN, vid)) {
1703                 QPRINTK(qdev, IFUP, ERR, "Failed to clear vlan address.\n");
1704         }
1705         spin_unlock(&qdev->hw_lock);
1706
1707 }
1708
1709 /* Worker thread to process a given rx_ring that is dedicated
1710  * to outbound completions.
1711  */
1712 static void ql_tx_clean(struct work_struct *work)
1713 {
1714         struct rx_ring *rx_ring =
1715             container_of(work, struct rx_ring, rx_work.work);
1716         ql_clean_outbound_rx_ring(rx_ring);
1717         ql_enable_completion_interrupt(rx_ring->qdev, rx_ring->irq);
1718
1719 }
1720
1721 /* Worker thread to process a given rx_ring that is dedicated
1722  * to inbound completions.
1723  */
1724 static void ql_rx_clean(struct work_struct *work)
1725 {
1726         struct rx_ring *rx_ring =
1727             container_of(work, struct rx_ring, rx_work.work);
1728         ql_clean_inbound_rx_ring(rx_ring, 64);
1729         ql_enable_completion_interrupt(rx_ring->qdev, rx_ring->irq);
1730 }
1731
1732 /* MSI-X Multiple Vector Interrupt Handler for outbound completions. */
1733 static irqreturn_t qlge_msix_tx_isr(int irq, void *dev_id)
1734 {
1735         struct rx_ring *rx_ring = dev_id;
1736         queue_delayed_work_on(rx_ring->cpu, rx_ring->qdev->q_workqueue,
1737                               &rx_ring->rx_work, 0);
1738         return IRQ_HANDLED;
1739 }
1740
1741 /* MSI-X Multiple Vector Interrupt Handler for inbound completions. */
1742 static irqreturn_t qlge_msix_rx_isr(int irq, void *dev_id)
1743 {
1744         struct rx_ring *rx_ring = dev_id;
1745         netif_rx_schedule(&rx_ring->napi);
1746         return IRQ_HANDLED;
1747 }
1748
1749 /* This handles a fatal error, MPI activity, and the default
1750  * rx_ring in an MSI-X multiple vector environment.
1751  * In MSI/Legacy environment it also process the rest of
1752  * the rx_rings.
1753  */
1754 static irqreturn_t qlge_isr(int irq, void *dev_id)
1755 {
1756         struct rx_ring *rx_ring = dev_id;
1757         struct ql_adapter *qdev = rx_ring->qdev;
1758         struct intr_context *intr_context = &qdev->intr_context[0];
1759         u32 var;
1760         int i;
1761         int work_done = 0;
1762
1763         spin_lock(&qdev->hw_lock);
1764         if (atomic_read(&qdev->intr_context[0].irq_cnt)) {
1765                 QPRINTK(qdev, INTR, DEBUG, "Shared Interrupt, Not ours!\n");
1766                 spin_unlock(&qdev->hw_lock);
1767                 return IRQ_NONE;
1768         }
1769         spin_unlock(&qdev->hw_lock);
1770
1771         var = ql_disable_completion_interrupt(qdev, intr_context->intr);
1772
1773         /*
1774          * Check for fatal error.
1775          */
1776         if (var & STS_FE) {
1777                 ql_queue_asic_error(qdev);
1778                 QPRINTK(qdev, INTR, ERR, "Got fatal error, STS = %x.\n", var);
1779                 var = ql_read32(qdev, ERR_STS);
1780                 QPRINTK(qdev, INTR, ERR,
1781                         "Resetting chip. Error Status Register = 0x%x\n", var);
1782                 return IRQ_HANDLED;
1783         }
1784
1785         /*
1786          * Check MPI processor activity.
1787          */
1788         if (var & STS_PI) {
1789                 /*
1790                  * We've got an async event or mailbox completion.
1791                  * Handle it and clear the source of the interrupt.
1792                  */
1793                 QPRINTK(qdev, INTR, ERR, "Got MPI processor interrupt.\n");
1794                 ql_disable_completion_interrupt(qdev, intr_context->intr);
1795                 queue_delayed_work_on(smp_processor_id(), qdev->workqueue,
1796                                       &qdev->mpi_work, 0);
1797                 work_done++;
1798         }
1799
1800         /*
1801          * Check the default queue and wake handler if active.
1802          */
1803         rx_ring = &qdev->rx_ring[0];
1804         if (ql_read_sh_reg(rx_ring->prod_idx_sh_reg) != rx_ring->cnsmr_idx) {
1805                 QPRINTK(qdev, INTR, INFO, "Waking handler for rx_ring[0].\n");
1806                 ql_disable_completion_interrupt(qdev, intr_context->intr);
1807                 queue_delayed_work_on(smp_processor_id(), qdev->q_workqueue,
1808                                       &rx_ring->rx_work, 0);
1809                 work_done++;
1810         }
1811
1812         if (!test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
1813                 /*
1814                  * Start the DPC for each active queue.
1815                  */
1816                 for (i = 1; i < qdev->rx_ring_count; i++) {
1817                         rx_ring = &qdev->rx_ring[i];
1818                         if (ql_read_sh_reg(rx_ring->prod_idx_sh_reg) !=
1819                             rx_ring->cnsmr_idx) {
1820                                 QPRINTK(qdev, INTR, INFO,
1821                                         "Waking handler for rx_ring[%d].\n", i);
1822                                 ql_disable_completion_interrupt(qdev,
1823                                                                 intr_context->
1824                                                                 intr);
1825                                 if (i < qdev->rss_ring_first_cq_id)
1826                                         queue_delayed_work_on(rx_ring->cpu,
1827                                                               qdev->q_workqueue,
1828                                                               &rx_ring->rx_work,
1829                                                               0);
1830                                 else
1831                                         netif_rx_schedule(&rx_ring->napi);
1832                                 work_done++;
1833                         }
1834                 }
1835         }
1836         ql_enable_completion_interrupt(qdev, intr_context->intr);
1837         return work_done ? IRQ_HANDLED : IRQ_NONE;
1838 }
1839
1840 static int ql_tso(struct sk_buff *skb, struct ob_mac_tso_iocb_req *mac_iocb_ptr)
1841 {
1842
1843         if (skb_is_gso(skb)) {
1844                 int err;
1845                 if (skb_header_cloned(skb)) {
1846                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
1847                         if (err)
1848                                 return err;
1849                 }
1850
1851                 mac_iocb_ptr->opcode = OPCODE_OB_MAC_TSO_IOCB;
1852                 mac_iocb_ptr->flags3 |= OB_MAC_TSO_IOCB_IC;
1853                 mac_iocb_ptr->frame_len = cpu_to_le32((u32) skb->len);
1854                 mac_iocb_ptr->total_hdrs_len =
1855                     cpu_to_le16(skb_transport_offset(skb) + tcp_hdrlen(skb));
1856                 mac_iocb_ptr->net_trans_offset =
1857                     cpu_to_le16(skb_network_offset(skb) |
1858                                 skb_transport_offset(skb)
1859                                 << OB_MAC_TRANSPORT_HDR_SHIFT);
1860                 mac_iocb_ptr->mss = cpu_to_le16(skb_shinfo(skb)->gso_size);
1861                 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_LSO;
1862                 if (likely(skb->protocol == htons(ETH_P_IP))) {
1863                         struct iphdr *iph = ip_hdr(skb);
1864                         iph->check = 0;
1865                         mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP4;
1866                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
1867                                                                  iph->daddr, 0,
1868                                                                  IPPROTO_TCP,
1869                                                                  0);
1870                 } else if (skb->protocol == htons(ETH_P_IPV6)) {
1871                         mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP6;
1872                         tcp_hdr(skb)->check =
1873                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
1874                                              &ipv6_hdr(skb)->daddr,
1875                                              0, IPPROTO_TCP, 0);
1876                 }
1877                 return 1;
1878         }
1879         return 0;
1880 }
1881
1882 static void ql_hw_csum_setup(struct sk_buff *skb,
1883                              struct ob_mac_tso_iocb_req *mac_iocb_ptr)
1884 {
1885         int len;
1886         struct iphdr *iph = ip_hdr(skb);
1887         __sum16 *check;
1888         mac_iocb_ptr->opcode = OPCODE_OB_MAC_TSO_IOCB;
1889         mac_iocb_ptr->frame_len = cpu_to_le32((u32) skb->len);
1890         mac_iocb_ptr->net_trans_offset =
1891                 cpu_to_le16(skb_network_offset(skb) |
1892                 skb_transport_offset(skb) << OB_MAC_TRANSPORT_HDR_SHIFT);
1893
1894         mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP4;
1895         len = (ntohs(iph->tot_len) - (iph->ihl << 2));
1896         if (likely(iph->protocol == IPPROTO_TCP)) {
1897                 check = &(tcp_hdr(skb)->check);
1898                 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_TC;
1899                 mac_iocb_ptr->total_hdrs_len =
1900                     cpu_to_le16(skb_transport_offset(skb) +
1901                                 (tcp_hdr(skb)->doff << 2));
1902         } else {
1903                 check = &(udp_hdr(skb)->check);
1904                 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_UC;
1905                 mac_iocb_ptr->total_hdrs_len =
1906                     cpu_to_le16(skb_transport_offset(skb) +
1907                                 sizeof(struct udphdr));
1908         }
1909         *check = ~csum_tcpudp_magic(iph->saddr,
1910                                     iph->daddr, len, iph->protocol, 0);
1911 }
1912
1913 static int qlge_send(struct sk_buff *skb, struct net_device *ndev)
1914 {
1915         struct tx_ring_desc *tx_ring_desc;
1916         struct ob_mac_iocb_req *mac_iocb_ptr;
1917         struct ql_adapter *qdev = netdev_priv(ndev);
1918         int tso;
1919         struct tx_ring *tx_ring;
1920         u32 tx_ring_idx = (u32) QL_TXQ_IDX(qdev, skb);
1921
1922         tx_ring = &qdev->tx_ring[tx_ring_idx];
1923
1924         if (unlikely(atomic_read(&tx_ring->tx_count) < 2)) {
1925                 QPRINTK(qdev, TX_QUEUED, INFO,
1926                         "%s: shutting down tx queue %d du to lack of resources.\n",
1927                         __func__, tx_ring_idx);
1928                 netif_stop_queue(ndev);
1929                 atomic_inc(&tx_ring->queue_stopped);
1930                 return NETDEV_TX_BUSY;
1931         }
1932         tx_ring_desc = &tx_ring->q[tx_ring->prod_idx];
1933         mac_iocb_ptr = tx_ring_desc->queue_entry;
1934         memset((void *)mac_iocb_ptr, 0, sizeof(mac_iocb_ptr));
1935         if (ql_map_send(qdev, mac_iocb_ptr, skb, tx_ring_desc) != NETDEV_TX_OK) {
1936                 QPRINTK(qdev, TX_QUEUED, ERR, "Could not map the segments.\n");
1937                 return NETDEV_TX_BUSY;
1938         }
1939
1940         mac_iocb_ptr->opcode = OPCODE_OB_MAC_IOCB;
1941         mac_iocb_ptr->tid = tx_ring_desc->index;
1942         /* We use the upper 32-bits to store the tx queue for this IO.
1943          * When we get the completion we can use it to establish the context.
1944          */
1945         mac_iocb_ptr->txq_idx = tx_ring_idx;
1946         tx_ring_desc->skb = skb;
1947
1948         mac_iocb_ptr->frame_len = cpu_to_le16((u16) skb->len);
1949
1950         if (qdev->vlgrp && vlan_tx_tag_present(skb)) {
1951                 QPRINTK(qdev, TX_QUEUED, DEBUG, "Adding a vlan tag %d.\n",
1952                         vlan_tx_tag_get(skb));
1953                 mac_iocb_ptr->flags3 |= OB_MAC_IOCB_V;
1954                 mac_iocb_ptr->vlan_tci = cpu_to_le16(vlan_tx_tag_get(skb));
1955         }
1956         tso = ql_tso(skb, (struct ob_mac_tso_iocb_req *)mac_iocb_ptr);
1957         if (tso < 0) {
1958                 dev_kfree_skb_any(skb);
1959                 return NETDEV_TX_OK;
1960         } else if (unlikely(!tso) && (skb->ip_summed == CHECKSUM_PARTIAL)) {
1961                 ql_hw_csum_setup(skb,
1962                                  (struct ob_mac_tso_iocb_req *)mac_iocb_ptr);
1963         }
1964         QL_DUMP_OB_MAC_IOCB(mac_iocb_ptr);
1965         tx_ring->prod_idx++;
1966         if (tx_ring->prod_idx == tx_ring->wq_len)
1967                 tx_ring->prod_idx = 0;
1968         wmb();
1969
1970         ql_write_db_reg(tx_ring->prod_idx, tx_ring->prod_idx_db_reg);
1971         ndev->trans_start = jiffies;
1972         QPRINTK(qdev, TX_QUEUED, DEBUG, "tx queued, slot %d, len %d\n",
1973                 tx_ring->prod_idx, skb->len);
1974
1975         atomic_dec(&tx_ring->tx_count);
1976         return NETDEV_TX_OK;
1977 }
1978
1979 static void ql_free_shadow_space(struct ql_adapter *qdev)
1980 {
1981         if (qdev->rx_ring_shadow_reg_area) {
1982                 pci_free_consistent(qdev->pdev,
1983                                     PAGE_SIZE,
1984                                     qdev->rx_ring_shadow_reg_area,
1985                                     qdev->rx_ring_shadow_reg_dma);
1986                 qdev->rx_ring_shadow_reg_area = NULL;
1987         }
1988         if (qdev->tx_ring_shadow_reg_area) {
1989                 pci_free_consistent(qdev->pdev,
1990                                     PAGE_SIZE,
1991                                     qdev->tx_ring_shadow_reg_area,
1992                                     qdev->tx_ring_shadow_reg_dma);
1993                 qdev->tx_ring_shadow_reg_area = NULL;
1994         }
1995 }
1996
1997 static int ql_alloc_shadow_space(struct ql_adapter *qdev)
1998 {
1999         qdev->rx_ring_shadow_reg_area =
2000             pci_alloc_consistent(qdev->pdev,
2001                                  PAGE_SIZE, &qdev->rx_ring_shadow_reg_dma);
2002         if (qdev->rx_ring_shadow_reg_area == NULL) {
2003                 QPRINTK(qdev, IFUP, ERR,
2004                         "Allocation of RX shadow space failed.\n");
2005                 return -ENOMEM;
2006         }
2007         qdev->tx_ring_shadow_reg_area =
2008             pci_alloc_consistent(qdev->pdev, PAGE_SIZE,
2009                                  &qdev->tx_ring_shadow_reg_dma);
2010         if (qdev->tx_ring_shadow_reg_area == NULL) {
2011                 QPRINTK(qdev, IFUP, ERR,
2012                         "Allocation of TX shadow space failed.\n");
2013                 goto err_wqp_sh_area;
2014         }
2015         return 0;
2016
2017 err_wqp_sh_area:
2018         pci_free_consistent(qdev->pdev,
2019                             PAGE_SIZE,
2020                             qdev->rx_ring_shadow_reg_area,
2021                             qdev->rx_ring_shadow_reg_dma);
2022         return -ENOMEM;
2023 }
2024
2025 static void ql_init_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring)
2026 {
2027         struct tx_ring_desc *tx_ring_desc;
2028         int i;
2029         struct ob_mac_iocb_req *mac_iocb_ptr;
2030
2031         mac_iocb_ptr = tx_ring->wq_base;
2032         tx_ring_desc = tx_ring->q;
2033         for (i = 0; i < tx_ring->wq_len; i++) {
2034                 tx_ring_desc->index = i;
2035                 tx_ring_desc->skb = NULL;
2036                 tx_ring_desc->queue_entry = mac_iocb_ptr;
2037                 mac_iocb_ptr++;
2038                 tx_ring_desc++;
2039         }
2040         atomic_set(&tx_ring->tx_count, tx_ring->wq_len);
2041         atomic_set(&tx_ring->queue_stopped, 0);
2042 }
2043
2044 static void ql_free_tx_resources(struct ql_adapter *qdev,
2045                                  struct tx_ring *tx_ring)
2046 {
2047         if (tx_ring->wq_base) {
2048                 pci_free_consistent(qdev->pdev, tx_ring->wq_size,
2049                                     tx_ring->wq_base, tx_ring->wq_base_dma);
2050                 tx_ring->wq_base = NULL;
2051         }
2052         kfree(tx_ring->q);
2053         tx_ring->q = NULL;
2054 }
2055
2056 static int ql_alloc_tx_resources(struct ql_adapter *qdev,
2057                                  struct tx_ring *tx_ring)
2058 {
2059         tx_ring->wq_base =
2060             pci_alloc_consistent(qdev->pdev, tx_ring->wq_size,
2061                                  &tx_ring->wq_base_dma);
2062
2063         if ((tx_ring->wq_base == NULL)
2064             || tx_ring->wq_base_dma & (tx_ring->wq_size - 1)) {
2065                 QPRINTK(qdev, IFUP, ERR, "tx_ring alloc failed.\n");
2066                 return -ENOMEM;
2067         }
2068         tx_ring->q =
2069             kmalloc(tx_ring->wq_len * sizeof(struct tx_ring_desc), GFP_KERNEL);
2070         if (tx_ring->q == NULL)
2071                 goto err;
2072
2073         return 0;
2074 err:
2075         pci_free_consistent(qdev->pdev, tx_ring->wq_size,
2076                             tx_ring->wq_base, tx_ring->wq_base_dma);
2077         return -ENOMEM;
2078 }
2079
2080 static void ql_free_lbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2081 {
2082         int i;
2083         struct bq_desc *lbq_desc;
2084
2085         for (i = 0; i < rx_ring->lbq_len; i++) {
2086                 lbq_desc = &rx_ring->lbq[i];
2087                 if (lbq_desc->p.lbq_page) {
2088                         pci_unmap_page(qdev->pdev,
2089                                        pci_unmap_addr(lbq_desc, mapaddr),
2090                                        pci_unmap_len(lbq_desc, maplen),
2091                                        PCI_DMA_FROMDEVICE);
2092
2093                         put_page(lbq_desc->p.lbq_page);
2094                         lbq_desc->p.lbq_page = NULL;
2095                 }
2096         }
2097 }
2098
2099 /*
2100  * Allocate and map a page for each element of the lbq.
2101  */
2102 static int ql_alloc_lbq_buffers(struct ql_adapter *qdev,
2103                                 struct rx_ring *rx_ring)
2104 {
2105         int i;
2106         struct bq_desc *lbq_desc;
2107         u64 map;
2108         __le64 *bq = rx_ring->lbq_base;
2109
2110         for (i = 0; i < rx_ring->lbq_len; i++) {
2111                 lbq_desc = &rx_ring->lbq[i];
2112                 memset(lbq_desc, 0, sizeof(lbq_desc));
2113                 lbq_desc->addr = bq;
2114                 lbq_desc->index = i;
2115                 lbq_desc->p.lbq_page = alloc_page(GFP_ATOMIC);
2116                 if (unlikely(!lbq_desc->p.lbq_page)) {
2117                         QPRINTK(qdev, IFUP, ERR, "failed alloc_page().\n");
2118                         goto mem_error;
2119                 } else {
2120                         map = pci_map_page(qdev->pdev,
2121                                            lbq_desc->p.lbq_page,
2122                                            0, PAGE_SIZE, PCI_DMA_FROMDEVICE);
2123                         if (pci_dma_mapping_error(qdev->pdev, map)) {
2124                                 QPRINTK(qdev, IFUP, ERR,
2125                                         "PCI mapping failed.\n");
2126                                 goto mem_error;
2127                         }
2128                         pci_unmap_addr_set(lbq_desc, mapaddr, map);
2129                         pci_unmap_len_set(lbq_desc, maplen, PAGE_SIZE);
2130                         *lbq_desc->addr = cpu_to_le64(map);
2131                 }
2132                 bq++;
2133         }
2134         return 0;
2135 mem_error:
2136         ql_free_lbq_buffers(qdev, rx_ring);
2137         return -ENOMEM;
2138 }
2139
2140 static void ql_free_sbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2141 {
2142         int i;
2143         struct bq_desc *sbq_desc;
2144
2145         for (i = 0; i < rx_ring->sbq_len; i++) {
2146                 sbq_desc = &rx_ring->sbq[i];
2147                 if (sbq_desc == NULL) {
2148                         QPRINTK(qdev, IFUP, ERR, "sbq_desc %d is NULL.\n", i);
2149                         return;
2150                 }
2151                 if (sbq_desc->p.skb) {
2152                         pci_unmap_single(qdev->pdev,
2153                                          pci_unmap_addr(sbq_desc, mapaddr),
2154                                          pci_unmap_len(sbq_desc, maplen),
2155                                          PCI_DMA_FROMDEVICE);
2156                         dev_kfree_skb(sbq_desc->p.skb);
2157                         sbq_desc->p.skb = NULL;
2158                 }
2159         }
2160 }
2161
2162 /* Allocate and map an skb for each element of the sbq. */
2163 static int ql_alloc_sbq_buffers(struct ql_adapter *qdev,
2164                                 struct rx_ring *rx_ring)
2165 {
2166         int i;
2167         struct bq_desc *sbq_desc;
2168         struct sk_buff *skb;
2169         u64 map;
2170         __le64 *bq = rx_ring->sbq_base;
2171
2172         for (i = 0; i < rx_ring->sbq_len; i++) {
2173                 sbq_desc = &rx_ring->sbq[i];
2174                 memset(sbq_desc, 0, sizeof(sbq_desc));
2175                 sbq_desc->index = i;
2176                 sbq_desc->addr = bq;
2177                 skb = netdev_alloc_skb(qdev->ndev, rx_ring->sbq_buf_size);
2178                 if (unlikely(!skb)) {
2179                         /* Better luck next round */
2180                         QPRINTK(qdev, IFUP, ERR,
2181                                 "small buff alloc failed for %d bytes at index %d.\n",
2182                                 rx_ring->sbq_buf_size, i);
2183                         goto mem_err;
2184                 }
2185                 skb_reserve(skb, QLGE_SB_PAD);
2186                 sbq_desc->p.skb = skb;
2187                 /*
2188                  * Map only half the buffer. Because the
2189                  * other half may get some data copied to it
2190                  * when the completion arrives.
2191                  */
2192                 map = pci_map_single(qdev->pdev,
2193                                      skb->data,
2194                                      rx_ring->sbq_buf_size / 2,
2195                                      PCI_DMA_FROMDEVICE);
2196                 if (pci_dma_mapping_error(qdev->pdev, map)) {
2197                         QPRINTK(qdev, IFUP, ERR, "PCI mapping failed.\n");
2198                         goto mem_err;
2199                 }
2200                 pci_unmap_addr_set(sbq_desc, mapaddr, map);
2201                 pci_unmap_len_set(sbq_desc, maplen, rx_ring->sbq_buf_size / 2);
2202                 *sbq_desc->addr = cpu_to_le64(map);
2203                 bq++;
2204         }
2205         return 0;
2206 mem_err:
2207         ql_free_sbq_buffers(qdev, rx_ring);
2208         return -ENOMEM;
2209 }
2210
2211 static void ql_free_rx_resources(struct ql_adapter *qdev,
2212                                  struct rx_ring *rx_ring)
2213 {
2214         if (rx_ring->sbq_len)
2215                 ql_free_sbq_buffers(qdev, rx_ring);
2216         if (rx_ring->lbq_len)
2217                 ql_free_lbq_buffers(qdev, rx_ring);
2218
2219         /* Free the small buffer queue. */
2220         if (rx_ring->sbq_base) {
2221                 pci_free_consistent(qdev->pdev,
2222                                     rx_ring->sbq_size,
2223                                     rx_ring->sbq_base, rx_ring->sbq_base_dma);
2224                 rx_ring->sbq_base = NULL;
2225         }
2226
2227         /* Free the small buffer queue control blocks. */
2228         kfree(rx_ring->sbq);
2229         rx_ring->sbq = NULL;
2230
2231         /* Free the large buffer queue. */
2232         if (rx_ring->lbq_base) {
2233                 pci_free_consistent(qdev->pdev,
2234                                     rx_ring->lbq_size,
2235                                     rx_ring->lbq_base, rx_ring->lbq_base_dma);
2236                 rx_ring->lbq_base = NULL;
2237         }
2238
2239         /* Free the large buffer queue control blocks. */
2240         kfree(rx_ring->lbq);
2241         rx_ring->lbq = NULL;
2242
2243         /* Free the rx queue. */
2244         if (rx_ring->cq_base) {
2245                 pci_free_consistent(qdev->pdev,
2246                                     rx_ring->cq_size,
2247                                     rx_ring->cq_base, rx_ring->cq_base_dma);
2248                 rx_ring->cq_base = NULL;
2249         }
2250 }
2251
2252 /* Allocate queues and buffers for this completions queue based
2253  * on the values in the parameter structure. */
2254 static int ql_alloc_rx_resources(struct ql_adapter *qdev,
2255                                  struct rx_ring *rx_ring)
2256 {
2257
2258         /*
2259          * Allocate the completion queue for this rx_ring.
2260          */
2261         rx_ring->cq_base =
2262             pci_alloc_consistent(qdev->pdev, rx_ring->cq_size,
2263                                  &rx_ring->cq_base_dma);
2264
2265         if (rx_ring->cq_base == NULL) {
2266                 QPRINTK(qdev, IFUP, ERR, "rx_ring alloc failed.\n");
2267                 return -ENOMEM;
2268         }
2269
2270         if (rx_ring->sbq_len) {
2271                 /*
2272                  * Allocate small buffer queue.
2273                  */
2274                 rx_ring->sbq_base =
2275                     pci_alloc_consistent(qdev->pdev, rx_ring->sbq_size,
2276                                          &rx_ring->sbq_base_dma);
2277
2278                 if (rx_ring->sbq_base == NULL) {
2279                         QPRINTK(qdev, IFUP, ERR,
2280                                 "Small buffer queue allocation failed.\n");
2281                         goto err_mem;
2282                 }
2283
2284                 /*
2285                  * Allocate small buffer queue control blocks.
2286                  */
2287                 rx_ring->sbq =
2288                     kmalloc(rx_ring->sbq_len * sizeof(struct bq_desc),
2289                             GFP_KERNEL);
2290                 if (rx_ring->sbq == NULL) {
2291                         QPRINTK(qdev, IFUP, ERR,
2292                                 "Small buffer queue control block allocation failed.\n");
2293                         goto err_mem;
2294                 }
2295
2296                 if (ql_alloc_sbq_buffers(qdev, rx_ring)) {
2297                         QPRINTK(qdev, IFUP, ERR,
2298                                 "Small buffer allocation failed.\n");
2299                         goto err_mem;
2300                 }
2301         }
2302
2303         if (rx_ring->lbq_len) {
2304                 /*
2305                  * Allocate large buffer queue.
2306                  */
2307                 rx_ring->lbq_base =
2308                     pci_alloc_consistent(qdev->pdev, rx_ring->lbq_size,
2309                                          &rx_ring->lbq_base_dma);
2310
2311                 if (rx_ring->lbq_base == NULL) {
2312                         QPRINTK(qdev, IFUP, ERR,
2313                                 "Large buffer queue allocation failed.\n");
2314                         goto err_mem;
2315                 }
2316                 /*
2317                  * Allocate large buffer queue control blocks.
2318                  */
2319                 rx_ring->lbq =
2320                     kmalloc(rx_ring->lbq_len * sizeof(struct bq_desc),
2321                             GFP_KERNEL);
2322                 if (rx_ring->lbq == NULL) {
2323                         QPRINTK(qdev, IFUP, ERR,
2324                                 "Large buffer queue control block allocation failed.\n");
2325                         goto err_mem;
2326                 }
2327
2328                 /*
2329                  * Allocate the buffers.
2330                  */
2331                 if (ql_alloc_lbq_buffers(qdev, rx_ring)) {
2332                         QPRINTK(qdev, IFUP, ERR,
2333                                 "Large buffer allocation failed.\n");
2334                         goto err_mem;
2335                 }
2336         }
2337
2338         return 0;
2339
2340 err_mem:
2341         ql_free_rx_resources(qdev, rx_ring);
2342         return -ENOMEM;
2343 }
2344
2345 static void ql_tx_ring_clean(struct ql_adapter *qdev)
2346 {
2347         struct tx_ring *tx_ring;
2348         struct tx_ring_desc *tx_ring_desc;
2349         int i, j;
2350
2351         /*
2352          * Loop through all queues and free
2353          * any resources.
2354          */
2355         for (j = 0; j < qdev->tx_ring_count; j++) {
2356                 tx_ring = &qdev->tx_ring[j];
2357                 for (i = 0; i < tx_ring->wq_len; i++) {
2358                         tx_ring_desc = &tx_ring->q[i];
2359                         if (tx_ring_desc && tx_ring_desc->skb) {
2360                                 QPRINTK(qdev, IFDOWN, ERR,
2361                                 "Freeing lost SKB %p, from queue %d, index %d.\n",
2362                                         tx_ring_desc->skb, j,
2363                                         tx_ring_desc->index);
2364                                 ql_unmap_send(qdev, tx_ring_desc,
2365                                               tx_ring_desc->map_cnt);
2366                                 dev_kfree_skb(tx_ring_desc->skb);
2367                                 tx_ring_desc->skb = NULL;
2368                         }
2369                 }
2370         }
2371 }
2372
2373 static void ql_free_mem_resources(struct ql_adapter *qdev)
2374 {
2375         int i;
2376
2377         for (i = 0; i < qdev->tx_ring_count; i++)
2378                 ql_free_tx_resources(qdev, &qdev->tx_ring[i]);
2379         for (i = 0; i < qdev->rx_ring_count; i++)
2380                 ql_free_rx_resources(qdev, &qdev->rx_ring[i]);
2381         ql_free_shadow_space(qdev);
2382 }
2383
2384 static int ql_alloc_mem_resources(struct ql_adapter *qdev)
2385 {
2386         int i;
2387
2388         /* Allocate space for our shadow registers and such. */
2389         if (ql_alloc_shadow_space(qdev))
2390                 return -ENOMEM;
2391
2392         for (i = 0; i < qdev->rx_ring_count; i++) {
2393                 if (ql_alloc_rx_resources(qdev, &qdev->rx_ring[i]) != 0) {
2394                         QPRINTK(qdev, IFUP, ERR,
2395                                 "RX resource allocation failed.\n");
2396                         goto err_mem;
2397                 }
2398         }
2399         /* Allocate tx queue resources */
2400         for (i = 0; i < qdev->tx_ring_count; i++) {
2401                 if (ql_alloc_tx_resources(qdev, &qdev->tx_ring[i]) != 0) {
2402                         QPRINTK(qdev, IFUP, ERR,
2403                                 "TX resource allocation failed.\n");
2404                         goto err_mem;
2405                 }
2406         }
2407         return 0;
2408
2409 err_mem:
2410         ql_free_mem_resources(qdev);
2411         return -ENOMEM;
2412 }
2413
2414 /* Set up the rx ring control block and pass it to the chip.
2415  * The control block is defined as
2416  * "Completion Queue Initialization Control Block", or cqicb.
2417  */
2418 static int ql_start_rx_ring(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2419 {
2420         struct cqicb *cqicb = &rx_ring->cqicb;
2421         void *shadow_reg = qdev->rx_ring_shadow_reg_area +
2422             (rx_ring->cq_id * sizeof(u64) * 4);
2423         u64 shadow_reg_dma = qdev->rx_ring_shadow_reg_dma +
2424             (rx_ring->cq_id * sizeof(u64) * 4);
2425         void __iomem *doorbell_area =
2426             qdev->doorbell_area + (DB_PAGE_SIZE * (128 + rx_ring->cq_id));
2427         int err = 0;
2428         u16 bq_len;
2429
2430         /* Set up the shadow registers for this ring. */
2431         rx_ring->prod_idx_sh_reg = shadow_reg;
2432         rx_ring->prod_idx_sh_reg_dma = shadow_reg_dma;
2433         shadow_reg += sizeof(u64);
2434         shadow_reg_dma += sizeof(u64);
2435         rx_ring->lbq_base_indirect = shadow_reg;
2436         rx_ring->lbq_base_indirect_dma = shadow_reg_dma;
2437         shadow_reg += sizeof(u64);
2438         shadow_reg_dma += sizeof(u64);
2439         rx_ring->sbq_base_indirect = shadow_reg;
2440         rx_ring->sbq_base_indirect_dma = shadow_reg_dma;
2441
2442         /* PCI doorbell mem area + 0x00 for consumer index register */
2443         rx_ring->cnsmr_idx_db_reg = (u32 __iomem *) doorbell_area;
2444         rx_ring->cnsmr_idx = 0;
2445         rx_ring->curr_entry = rx_ring->cq_base;
2446
2447         /* PCI doorbell mem area + 0x04 for valid register */
2448         rx_ring->valid_db_reg = doorbell_area + 0x04;
2449
2450         /* PCI doorbell mem area + 0x18 for large buffer consumer */
2451         rx_ring->lbq_prod_idx_db_reg = (u32 __iomem *) (doorbell_area + 0x18);
2452
2453         /* PCI doorbell mem area + 0x1c */
2454         rx_ring->sbq_prod_idx_db_reg = (u32 __iomem *) (doorbell_area + 0x1c);
2455
2456         memset((void *)cqicb, 0, sizeof(struct cqicb));
2457         cqicb->msix_vect = rx_ring->irq;
2458
2459         bq_len = (rx_ring->cq_len == 65536) ? 0 : (u16) rx_ring->cq_len;
2460         cqicb->len = cpu_to_le16(bq_len | LEN_V | LEN_CPP_CONT);
2461
2462         cqicb->addr = cpu_to_le64(rx_ring->cq_base_dma);
2463
2464         cqicb->prod_idx_addr = cpu_to_le64(rx_ring->prod_idx_sh_reg_dma);
2465
2466         /*
2467          * Set up the control block load flags.
2468          */
2469         cqicb->flags = FLAGS_LC |       /* Load queue base address */
2470             FLAGS_LV |          /* Load MSI-X vector */
2471             FLAGS_LI;           /* Load irq delay values */
2472         if (rx_ring->lbq_len) {
2473                 cqicb->flags |= FLAGS_LL;       /* Load lbq values */
2474                 *((u64 *) rx_ring->lbq_base_indirect) = rx_ring->lbq_base_dma;
2475                 cqicb->lbq_addr =
2476                     cpu_to_le64(rx_ring->lbq_base_indirect_dma);
2477                 bq_len = (rx_ring->lbq_buf_size == 65536) ? 0 :
2478                         (u16) rx_ring->lbq_buf_size;
2479                 cqicb->lbq_buf_size = cpu_to_le16(bq_len);
2480                 bq_len = (rx_ring->lbq_len == 65536) ? 0 :
2481                         (u16) rx_ring->lbq_len;
2482                 cqicb->lbq_len = cpu_to_le16(bq_len);
2483                 rx_ring->lbq_prod_idx = rx_ring->lbq_len - 16;
2484                 rx_ring->lbq_curr_idx = 0;
2485                 rx_ring->lbq_clean_idx = rx_ring->lbq_prod_idx;
2486                 rx_ring->lbq_free_cnt = 16;
2487         }
2488         if (rx_ring->sbq_len) {
2489                 cqicb->flags |= FLAGS_LS;       /* Load sbq values */
2490                 *((u64 *) rx_ring->sbq_base_indirect) = rx_ring->sbq_base_dma;
2491                 cqicb->sbq_addr =
2492                     cpu_to_le64(rx_ring->sbq_base_indirect_dma);
2493                 cqicb->sbq_buf_size =
2494                     cpu_to_le16(((rx_ring->sbq_buf_size / 2) + 8) & 0xfffffff8);
2495                 bq_len = (rx_ring->sbq_len == 65536) ? 0 :
2496                         (u16) rx_ring->sbq_len;
2497                 cqicb->sbq_len = cpu_to_le16(bq_len);
2498                 rx_ring->sbq_prod_idx = rx_ring->sbq_len - 16;
2499                 rx_ring->sbq_curr_idx = 0;
2500                 rx_ring->sbq_clean_idx = rx_ring->sbq_prod_idx;
2501                 rx_ring->sbq_free_cnt = 16;
2502         }
2503         switch (rx_ring->type) {
2504         case TX_Q:
2505                 /* If there's only one interrupt, then we use
2506                  * worker threads to process the outbound
2507                  * completion handling rx_rings. We do this so
2508                  * they can be run on multiple CPUs. There is
2509                  * room to play with this more where we would only
2510                  * run in a worker if there are more than x number
2511                  * of outbound completions on the queue and more
2512                  * than one queue active.  Some threshold that
2513                  * would indicate a benefit in spite of the cost
2514                  * of a context switch.
2515                  * If there's more than one interrupt, then the
2516                  * outbound completions are processed in the ISR.
2517                  */
2518                 if (!test_bit(QL_MSIX_ENABLED, &qdev->flags))
2519                         INIT_DELAYED_WORK(&rx_ring->rx_work, ql_tx_clean);
2520                 else {
2521                         /* With all debug warnings on we see a WARN_ON message
2522                          * when we free the skb in the interrupt context.
2523                          */
2524                         INIT_DELAYED_WORK(&rx_ring->rx_work, ql_tx_clean);
2525                 }
2526                 cqicb->irq_delay = cpu_to_le16(qdev->tx_coalesce_usecs);
2527                 cqicb->pkt_delay = cpu_to_le16(qdev->tx_max_coalesced_frames);
2528                 break;
2529         case DEFAULT_Q:
2530                 INIT_DELAYED_WORK(&rx_ring->rx_work, ql_rx_clean);
2531                 cqicb->irq_delay = 0;
2532                 cqicb->pkt_delay = 0;
2533                 break;
2534         case RX_Q:
2535                 /* Inbound completion handling rx_rings run in
2536                  * separate NAPI contexts.
2537                  */
2538                 netif_napi_add(qdev->ndev, &rx_ring->napi, ql_napi_poll_msix,
2539                                64);
2540                 cqicb->irq_delay = cpu_to_le16(qdev->rx_coalesce_usecs);
2541                 cqicb->pkt_delay = cpu_to_le16(qdev->rx_max_coalesced_frames);
2542                 break;
2543         default:
2544                 QPRINTK(qdev, IFUP, DEBUG, "Invalid rx_ring->type = %d.\n",
2545                         rx_ring->type);
2546         }
2547         QPRINTK(qdev, IFUP, INFO, "Initializing rx work queue.\n");
2548         err = ql_write_cfg(qdev, cqicb, sizeof(struct cqicb),
2549                            CFG_LCQ, rx_ring->cq_id);
2550         if (err) {
2551                 QPRINTK(qdev, IFUP, ERR, "Failed to load CQICB.\n");
2552                 return err;
2553         }
2554         QPRINTK(qdev, IFUP, INFO, "Successfully loaded CQICB.\n");
2555         /*
2556          * Advance the producer index for the buffer queues.
2557          */
2558         wmb();
2559         if (rx_ring->lbq_len)
2560                 ql_write_db_reg(rx_ring->lbq_prod_idx,
2561                                 rx_ring->lbq_prod_idx_db_reg);
2562         if (rx_ring->sbq_len)
2563                 ql_write_db_reg(rx_ring->sbq_prod_idx,
2564                                 rx_ring->sbq_prod_idx_db_reg);
2565         return err;
2566 }
2567
2568 static int ql_start_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring)
2569 {
2570         struct wqicb *wqicb = (struct wqicb *)tx_ring;
2571         void __iomem *doorbell_area =
2572             qdev->doorbell_area + (DB_PAGE_SIZE * tx_ring->wq_id);
2573         void *shadow_reg = qdev->tx_ring_shadow_reg_area +
2574             (tx_ring->wq_id * sizeof(u64));
2575         u64 shadow_reg_dma = qdev->tx_ring_shadow_reg_dma +
2576             (tx_ring->wq_id * sizeof(u64));
2577         int err = 0;
2578
2579         /*
2580          * Assign doorbell registers for this tx_ring.
2581          */
2582         /* TX PCI doorbell mem area for tx producer index */
2583         tx_ring->prod_idx_db_reg = (u32 __iomem *) doorbell_area;
2584         tx_ring->prod_idx = 0;
2585         /* TX PCI doorbell mem area + 0x04 */
2586         tx_ring->valid_db_reg = doorbell_area + 0x04;
2587
2588         /*
2589          * Assign shadow registers for this tx_ring.
2590          */
2591         tx_ring->cnsmr_idx_sh_reg = shadow_reg;
2592         tx_ring->cnsmr_idx_sh_reg_dma = shadow_reg_dma;
2593
2594         wqicb->len = cpu_to_le16(tx_ring->wq_len | Q_LEN_V | Q_LEN_CPP_CONT);
2595         wqicb->flags = cpu_to_le16(Q_FLAGS_LC |
2596                                    Q_FLAGS_LB | Q_FLAGS_LI | Q_FLAGS_LO);
2597         wqicb->cq_id_rss = cpu_to_le16(tx_ring->cq_id);
2598         wqicb->rid = 0;
2599         wqicb->addr = cpu_to_le64(tx_ring->wq_base_dma);
2600
2601         wqicb->cnsmr_idx_addr = cpu_to_le64(tx_ring->cnsmr_idx_sh_reg_dma);
2602
2603         ql_init_tx_ring(qdev, tx_ring);
2604
2605         err = ql_write_cfg(qdev, wqicb, sizeof(wqicb), CFG_LRQ,
2606                            (u16) tx_ring->wq_id);
2607         if (err) {
2608                 QPRINTK(qdev, IFUP, ERR, "Failed to load tx_ring.\n");
2609                 return err;
2610         }
2611         QPRINTK(qdev, IFUP, INFO, "Successfully loaded WQICB.\n");
2612         return err;
2613 }
2614
2615 static void ql_disable_msix(struct ql_adapter *qdev)
2616 {
2617         if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2618                 pci_disable_msix(qdev->pdev);
2619                 clear_bit(QL_MSIX_ENABLED, &qdev->flags);
2620                 kfree(qdev->msi_x_entry);
2621                 qdev->msi_x_entry = NULL;
2622         } else if (test_bit(QL_MSI_ENABLED, &qdev->flags)) {
2623                 pci_disable_msi(qdev->pdev);
2624                 clear_bit(QL_MSI_ENABLED, &qdev->flags);
2625         }
2626 }
2627
2628 static void ql_enable_msix(struct ql_adapter *qdev)
2629 {
2630         int i;
2631
2632         qdev->intr_count = 1;
2633         /* Get the MSIX vectors. */
2634         if (irq_type == MSIX_IRQ) {
2635                 /* Try to alloc space for the msix struct,
2636                  * if it fails then go to MSI/legacy.
2637                  */
2638                 qdev->msi_x_entry = kcalloc(qdev->rx_ring_count,
2639                                             sizeof(struct msix_entry),
2640                                             GFP_KERNEL);
2641                 if (!qdev->msi_x_entry) {
2642                         irq_type = MSI_IRQ;
2643                         goto msi;
2644                 }
2645
2646                 for (i = 0; i < qdev->rx_ring_count; i++)
2647                         qdev->msi_x_entry[i].entry = i;
2648
2649                 if (!pci_enable_msix
2650                     (qdev->pdev, qdev->msi_x_entry, qdev->rx_ring_count)) {
2651                         set_bit(QL_MSIX_ENABLED, &qdev->flags);
2652                         qdev->intr_count = qdev->rx_ring_count;
2653                         QPRINTK(qdev, IFUP, INFO,
2654                                 "MSI-X Enabled, got %d vectors.\n",
2655                                 qdev->intr_count);
2656                         return;
2657                 } else {
2658                         kfree(qdev->msi_x_entry);
2659                         qdev->msi_x_entry = NULL;
2660                         QPRINTK(qdev, IFUP, WARNING,
2661                                 "MSI-X Enable failed, trying MSI.\n");
2662                         irq_type = MSI_IRQ;
2663                 }
2664         }
2665 msi:
2666         if (irq_type == MSI_IRQ) {
2667                 if (!pci_enable_msi(qdev->pdev)) {
2668                         set_bit(QL_MSI_ENABLED, &qdev->flags);
2669                         QPRINTK(qdev, IFUP, INFO,
2670                                 "Running with MSI interrupts.\n");
2671                         return;
2672                 }
2673         }
2674         irq_type = LEG_IRQ;
2675         QPRINTK(qdev, IFUP, DEBUG, "Running with legacy interrupts.\n");
2676 }
2677
2678 /*
2679  * Here we build the intr_context structures based on
2680  * our rx_ring count and intr vector count.
2681  * The intr_context structure is used to hook each vector
2682  * to possibly different handlers.
2683  */
2684 static void ql_resolve_queues_to_irqs(struct ql_adapter *qdev)
2685 {
2686         int i = 0;
2687         struct intr_context *intr_context = &qdev->intr_context[0];
2688
2689         ql_enable_msix(qdev);
2690
2691         if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags))) {
2692                 /* Each rx_ring has it's
2693                  * own intr_context since we have separate
2694                  * vectors for each queue.
2695                  * This only true when MSI-X is enabled.
2696                  */
2697                 for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2698                         qdev->rx_ring[i].irq = i;
2699                         intr_context->intr = i;
2700                         intr_context->qdev = qdev;
2701                         /*
2702                          * We set up each vectors enable/disable/read bits so
2703                          * there's no bit/mask calculations in the critical path.
2704                          */
2705                         intr_context->intr_en_mask =
2706                             INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2707                             INTR_EN_TYPE_ENABLE | INTR_EN_IHD_MASK | INTR_EN_IHD
2708                             | i;
2709                         intr_context->intr_dis_mask =
2710                             INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2711                             INTR_EN_TYPE_DISABLE | INTR_EN_IHD_MASK |
2712                             INTR_EN_IHD | i;
2713                         intr_context->intr_read_mask =
2714                             INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2715                             INTR_EN_TYPE_READ | INTR_EN_IHD_MASK | INTR_EN_IHD |
2716                             i;
2717
2718                         if (i == 0) {
2719                                 /*
2720                                  * Default queue handles bcast/mcast plus
2721                                  * async events.  Needs buffers.
2722                                  */
2723                                 intr_context->handler = qlge_isr;
2724                                 sprintf(intr_context->name, "%s-default-queue",
2725                                         qdev->ndev->name);
2726                         } else if (i < qdev->rss_ring_first_cq_id) {
2727                                 /*
2728                                  * Outbound queue is for outbound completions only.
2729                                  */
2730                                 intr_context->handler = qlge_msix_tx_isr;
2731                                 sprintf(intr_context->name, "%s-tx-%d",
2732                                         qdev->ndev->name, i);
2733                         } else {
2734                                 /*
2735                                  * Inbound queues handle unicast frames only.
2736                                  */
2737                                 intr_context->handler = qlge_msix_rx_isr;
2738                                 sprintf(intr_context->name, "%s-rx-%d",
2739                                         qdev->ndev->name, i);
2740                         }
2741                 }
2742         } else {
2743                 /*
2744                  * All rx_rings use the same intr_context since
2745                  * there is only one vector.
2746                  */
2747                 intr_context->intr = 0;
2748                 intr_context->qdev = qdev;
2749                 /*
2750                  * We set up each vectors enable/disable/read bits so
2751                  * there's no bit/mask calculations in the critical path.
2752                  */
2753                 intr_context->intr_en_mask =
2754                     INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | INTR_EN_TYPE_ENABLE;
2755                 intr_context->intr_dis_mask =
2756                     INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2757                     INTR_EN_TYPE_DISABLE;
2758                 intr_context->intr_read_mask =
2759                     INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | INTR_EN_TYPE_READ;
2760                 /*
2761                  * Single interrupt means one handler for all rings.
2762                  */
2763                 intr_context->handler = qlge_isr;
2764                 sprintf(intr_context->name, "%s-single_irq", qdev->ndev->name);
2765                 for (i = 0; i < qdev->rx_ring_count; i++)
2766                         qdev->rx_ring[i].irq = 0;
2767         }
2768 }
2769
2770 static void ql_free_irq(struct ql_adapter *qdev)
2771 {
2772         int i;
2773         struct intr_context *intr_context = &qdev->intr_context[0];
2774
2775         for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2776                 if (intr_context->hooked) {
2777                         if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2778                                 free_irq(qdev->msi_x_entry[i].vector,
2779                                          &qdev->rx_ring[i]);
2780                                 QPRINTK(qdev, IFDOWN, ERR,
2781                                         "freeing msix interrupt %d.\n", i);
2782                         } else {
2783                                 free_irq(qdev->pdev->irq, &qdev->rx_ring[0]);
2784                                 QPRINTK(qdev, IFDOWN, ERR,
2785                                         "freeing msi interrupt %d.\n", i);
2786                         }
2787                 }
2788         }
2789         ql_disable_msix(qdev);
2790 }
2791
2792 static int ql_request_irq(struct ql_adapter *qdev)
2793 {
2794         int i;
2795         int status = 0;
2796         struct pci_dev *pdev = qdev->pdev;
2797         struct intr_context *intr_context = &qdev->intr_context[0];
2798
2799         ql_resolve_queues_to_irqs(qdev);
2800
2801         for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2802                 atomic_set(&intr_context->irq_cnt, 0);
2803                 if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2804                         status = request_irq(qdev->msi_x_entry[i].vector,
2805                                              intr_context->handler,
2806                                              0,
2807                                              intr_context->name,
2808                                              &qdev->rx_ring[i]);
2809                         if (status) {
2810                                 QPRINTK(qdev, IFUP, ERR,
2811                                         "Failed request for MSIX interrupt %d.\n",
2812                                         i);
2813                                 goto err_irq;
2814                         } else {
2815                                 QPRINTK(qdev, IFUP, INFO,
2816                                         "Hooked intr %d, queue type %s%s%s, with name %s.\n",
2817                                         i,
2818                                         qdev->rx_ring[i].type ==
2819                                         DEFAULT_Q ? "DEFAULT_Q" : "",
2820                                         qdev->rx_ring[i].type ==
2821                                         TX_Q ? "TX_Q" : "",
2822                                         qdev->rx_ring[i].type ==
2823                                         RX_Q ? "RX_Q" : "", intr_context->name);
2824                         }
2825                 } else {
2826                         QPRINTK(qdev, IFUP, DEBUG,
2827                                 "trying msi or legacy interrupts.\n");
2828                         QPRINTK(qdev, IFUP, DEBUG,
2829                                 "%s: irq = %d.\n", __func__, pdev->irq);
2830                         QPRINTK(qdev, IFUP, DEBUG,
2831                                 "%s: context->name = %s.\n", __func__,
2832                                intr_context->name);
2833                         QPRINTK(qdev, IFUP, DEBUG,
2834                                 "%s: dev_id = 0x%p.\n", __func__,
2835                                &qdev->rx_ring[0]);
2836                         status =
2837                             request_irq(pdev->irq, qlge_isr,
2838                                         test_bit(QL_MSI_ENABLED,
2839                                                  &qdev->
2840                                                  flags) ? 0 : IRQF_SHARED,
2841                                         intr_context->name, &qdev->rx_ring[0]);
2842                         if (status)
2843                                 goto err_irq;
2844
2845                         QPRINTK(qdev, IFUP, ERR,
2846                                 "Hooked intr %d, queue type %s%s%s, with name %s.\n",
2847                                 i,
2848                                 qdev->rx_ring[0].type ==
2849                                 DEFAULT_Q ? "DEFAULT_Q" : "",
2850                                 qdev->rx_ring[0].type == TX_Q ? "TX_Q" : "",
2851                                 qdev->rx_ring[0].type == RX_Q ? "RX_Q" : "",
2852                                 intr_context->name);
2853                 }
2854                 intr_context->hooked = 1;
2855         }
2856         return status;
2857 err_irq:
2858         QPRINTK(qdev, IFUP, ERR, "Failed to get the interrupts!!!/n");
2859         ql_free_irq(qdev);
2860         return status;
2861 }
2862
2863 static int ql_start_rss(struct ql_adapter *qdev)
2864 {
2865         struct ricb *ricb = &qdev->ricb;
2866         int status = 0;
2867         int i;
2868         u8 *hash_id = (u8 *) ricb->hash_cq_id;
2869
2870         memset((void *)ricb, 0, sizeof(ricb));
2871
2872         ricb->base_cq = qdev->rss_ring_first_cq_id | RSS_L4K;
2873         ricb->flags =
2874             (RSS_L6K | RSS_LI | RSS_LB | RSS_LM | RSS_RI4 | RSS_RI6 | RSS_RT4 |
2875              RSS_RT6);
2876         ricb->mask = cpu_to_le16(qdev->rss_ring_count - 1);
2877
2878         /*
2879          * Fill out the Indirection Table.
2880          */
2881         for (i = 0; i < 32; i++)
2882                 hash_id[i] = i & 1;
2883
2884         /*
2885          * Random values for the IPv6 and IPv4 Hash Keys.
2886          */
2887         get_random_bytes((void *)&ricb->ipv6_hash_key[0], 40);
2888         get_random_bytes((void *)&ricb->ipv4_hash_key[0], 16);
2889
2890         QPRINTK(qdev, IFUP, INFO, "Initializing RSS.\n");
2891
2892         status = ql_write_cfg(qdev, ricb, sizeof(ricb), CFG_LR, 0);
2893         if (status) {
2894                 QPRINTK(qdev, IFUP, ERR, "Failed to load RICB.\n");
2895                 return status;
2896         }
2897         QPRINTK(qdev, IFUP, INFO, "Successfully loaded RICB.\n");
2898         return status;
2899 }
2900
2901 /* Initialize the frame-to-queue routing. */
2902 static int ql_route_initialize(struct ql_adapter *qdev)
2903 {
2904         int status = 0;
2905         int i;
2906
2907         /* Clear all the entries in the routing table. */
2908         for (i = 0; i < 16; i++) {
2909                 status = ql_set_routing_reg(qdev, i, 0, 0);
2910                 if (status) {
2911                         QPRINTK(qdev, IFUP, ERR,
2912                                 "Failed to init routing register for CAM packets.\n");
2913                         return status;
2914                 }
2915         }
2916
2917         status = ql_set_routing_reg(qdev, RT_IDX_ALL_ERR_SLOT, RT_IDX_ERR, 1);
2918         if (status) {
2919                 QPRINTK(qdev, IFUP, ERR,
2920                         "Failed to init routing register for error packets.\n");
2921                 return status;
2922         }
2923         status = ql_set_routing_reg(qdev, RT_IDX_BCAST_SLOT, RT_IDX_BCAST, 1);
2924         if (status) {
2925                 QPRINTK(qdev, IFUP, ERR,
2926                         "Failed to init routing register for broadcast packets.\n");
2927                 return status;
2928         }
2929         /* If we have more than one inbound queue, then turn on RSS in the
2930          * routing block.
2931          */
2932         if (qdev->rss_ring_count > 1) {
2933                 status = ql_set_routing_reg(qdev, RT_IDX_RSS_MATCH_SLOT,
2934                                         RT_IDX_RSS_MATCH, 1);
2935                 if (status) {
2936                         QPRINTK(qdev, IFUP, ERR,
2937                                 "Failed to init routing register for MATCH RSS packets.\n");
2938                         return status;
2939                 }
2940         }
2941
2942         status = ql_set_routing_reg(qdev, RT_IDX_CAM_HIT_SLOT,
2943                                     RT_IDX_CAM_HIT, 1);
2944         if (status) {
2945                 QPRINTK(qdev, IFUP, ERR,
2946                         "Failed to init routing register for CAM packets.\n");
2947                 return status;
2948         }
2949         return status;
2950 }
2951
2952 static int ql_adapter_initialize(struct ql_adapter *qdev)
2953 {
2954         u32 value, mask;
2955         int i;
2956         int status = 0;
2957
2958         /*
2959          * Set up the System register to halt on errors.
2960          */
2961         value = SYS_EFE | SYS_FAE;
2962         mask = value << 16;
2963         ql_write32(qdev, SYS, mask | value);
2964
2965         /* Set the default queue. */
2966         value = NIC_RCV_CFG_DFQ;
2967         mask = NIC_RCV_CFG_DFQ_MASK;
2968         ql_write32(qdev, NIC_RCV_CFG, (mask | value));
2969
2970         /* Set the MPI interrupt to enabled. */
2971         ql_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16) | INTR_MASK_PI);
2972
2973         /* Enable the function, set pagesize, enable error checking. */
2974         value = FSC_FE | FSC_EPC_INBOUND | FSC_EPC_OUTBOUND |
2975             FSC_EC | FSC_VM_PAGE_4K | FSC_SH;
2976
2977         /* Set/clear header splitting. */
2978         mask = FSC_VM_PAGESIZE_MASK |
2979             FSC_DBL_MASK | FSC_DBRST_MASK | (value << 16);
2980         ql_write32(qdev, FSC, mask | value);
2981
2982         ql_write32(qdev, SPLT_HDR, SPLT_HDR_EP |
2983                 min(SMALL_BUFFER_SIZE, MAX_SPLIT_SIZE));
2984
2985         /* Start up the rx queues. */
2986         for (i = 0; i < qdev->rx_ring_count; i++) {
2987                 status = ql_start_rx_ring(qdev, &qdev->rx_ring[i]);
2988                 if (status) {
2989                         QPRINTK(qdev, IFUP, ERR,
2990                                 "Failed to start rx ring[%d].\n", i);
2991                         return status;
2992                 }
2993         }
2994
2995         /* If there is more than one inbound completion queue
2996          * then download a RICB to configure RSS.
2997          */
2998         if (qdev->rss_ring_count > 1) {
2999                 status = ql_start_rss(qdev);
3000                 if (status) {
3001                         QPRINTK(qdev, IFUP, ERR, "Failed to start RSS.\n");
3002                         return status;
3003                 }
3004         }
3005
3006         /* Start up the tx queues. */
3007         for (i = 0; i < qdev->tx_ring_count; i++) {
3008                 status = ql_start_tx_ring(qdev, &qdev->tx_ring[i]);
3009                 if (status) {
3010                         QPRINTK(qdev, IFUP, ERR,
3011                                 "Failed to start tx ring[%d].\n", i);
3012                         return status;
3013                 }
3014         }
3015
3016         status = ql_port_initialize(qdev);
3017         if (status) {
3018                 QPRINTK(qdev, IFUP, ERR, "Failed to start port.\n");
3019                 return status;
3020         }
3021
3022         status = ql_set_mac_addr_reg(qdev, (u8 *) qdev->ndev->perm_addr,
3023                                      MAC_ADDR_TYPE_CAM_MAC, qdev->func);
3024         if (status) {
3025                 QPRINTK(qdev, IFUP, ERR, "Failed to init mac address.\n");
3026                 return status;
3027         }
3028
3029         status = ql_route_initialize(qdev);
3030         if (status) {
3031                 QPRINTK(qdev, IFUP, ERR, "Failed to init routing table.\n");
3032                 return status;
3033         }
3034
3035         /* Start NAPI for the RSS queues. */
3036         for (i = qdev->rss_ring_first_cq_id; i < qdev->rx_ring_count; i++) {
3037                 QPRINTK(qdev, IFUP, INFO, "Enabling NAPI for rx_ring[%d].\n",
3038                         i);
3039                 napi_enable(&qdev->rx_ring[i].napi);
3040         }
3041
3042         return status;
3043 }
3044
3045 /* Issue soft reset to chip. */
3046 static int ql_adapter_reset(struct ql_adapter *qdev)
3047 {
3048         u32 value;
3049         int max_wait_time;
3050         int status = 0;
3051         int resetCnt = 0;
3052
3053 #define MAX_RESET_CNT   1
3054 issueReset:
3055         resetCnt++;
3056         QPRINTK(qdev, IFDOWN, DEBUG, "Issue soft reset to chip.\n");
3057         ql_write32(qdev, RST_FO, (RST_FO_FR << 16) | RST_FO_FR);
3058         /* Wait for reset to complete. */
3059         max_wait_time = 3;
3060         QPRINTK(qdev, IFDOWN, DEBUG, "Wait %d seconds for reset to complete.\n",
3061                 max_wait_time);
3062         do {
3063                 value = ql_read32(qdev, RST_FO);
3064                 if ((value & RST_FO_FR) == 0)
3065                         break;
3066
3067                 ssleep(1);
3068         } while ((--max_wait_time));
3069         if (value & RST_FO_FR) {
3070                 QPRINTK(qdev, IFDOWN, ERR,
3071                         "Stuck in SoftReset:  FSC_SR:0x%08x\n", value);
3072                 if (resetCnt < MAX_RESET_CNT)
3073                         goto issueReset;
3074         }
3075         if (max_wait_time == 0) {
3076                 status = -ETIMEDOUT;
3077                 QPRINTK(qdev, IFDOWN, ERR,
3078                         "ETIMEOUT!!! errored out of resetting the chip!\n");
3079         }
3080
3081         return status;
3082 }
3083
3084 static void ql_display_dev_info(struct net_device *ndev)
3085 {
3086         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3087
3088         QPRINTK(qdev, PROBE, INFO,
3089                 "Function #%d, NIC Roll %d, NIC Rev = %d, "
3090                 "XG Roll = %d, XG Rev = %d.\n",
3091                 qdev->func,
3092                 qdev->chip_rev_id & 0x0000000f,
3093                 qdev->chip_rev_id >> 4 & 0x0000000f,
3094                 qdev->chip_rev_id >> 8 & 0x0000000f,
3095                 qdev->chip_rev_id >> 12 & 0x0000000f);
3096         QPRINTK(qdev, PROBE, INFO, "MAC address %pM\n", ndev->dev_addr);
3097 }
3098
3099 static int ql_adapter_down(struct ql_adapter *qdev)
3100 {
3101         struct net_device *ndev = qdev->ndev;
3102         int i, status = 0;
3103         struct rx_ring *rx_ring;
3104
3105         netif_stop_queue(ndev);
3106         netif_carrier_off(ndev);
3107
3108         /* Don't kill the reset worker thread if we
3109          * are in the process of recovery.
3110          */
3111         if (test_bit(QL_ADAPTER_UP, &qdev->flags))
3112                 cancel_delayed_work_sync(&qdev->asic_reset_work);
3113         cancel_delayed_work_sync(&qdev->mpi_reset_work);
3114         cancel_delayed_work_sync(&qdev->mpi_work);
3115
3116         /* The default queue at index 0 is always processed in
3117          * a workqueue.
3118          */
3119         cancel_delayed_work_sync(&qdev->rx_ring[0].rx_work);
3120
3121         /* The rest of the rx_rings are processed in
3122          * a workqueue only if it's a single interrupt
3123          * environment (MSI/Legacy).
3124          */
3125         for (i = 1; i < qdev->rx_ring_count; i++) {
3126                 rx_ring = &qdev->rx_ring[i];
3127                 /* Only the RSS rings use NAPI on multi irq
3128                  * environment.  Outbound completion processing
3129                  * is done in interrupt context.
3130                  */
3131                 if (i >= qdev->rss_ring_first_cq_id) {
3132                         napi_disable(&rx_ring->napi);
3133                 } else {
3134                         cancel_delayed_work_sync(&rx_ring->rx_work);
3135                 }
3136         }
3137
3138         clear_bit(QL_ADAPTER_UP, &qdev->flags);
3139
3140         ql_disable_interrupts(qdev);
3141
3142         ql_tx_ring_clean(qdev);
3143
3144         spin_lock(&qdev->hw_lock);
3145         status = ql_adapter_reset(qdev);
3146         if (status)
3147                 QPRINTK(qdev, IFDOWN, ERR, "reset(func #%d) FAILED!\n",
3148                         qdev->func);
3149         spin_unlock(&qdev->hw_lock);
3150         return status;
3151 }
3152
3153 static int ql_adapter_up(struct ql_adapter *qdev)
3154 {
3155         int err = 0;
3156
3157         spin_lock(&qdev->hw_lock);
3158         err = ql_adapter_initialize(qdev);
3159         if (err) {
3160                 QPRINTK(qdev, IFUP, INFO, "Unable to initialize adapter.\n");
3161                 spin_unlock(&qdev->hw_lock);
3162                 goto err_init;
3163         }
3164         spin_unlock(&qdev->hw_lock);
3165         set_bit(QL_ADAPTER_UP, &qdev->flags);
3166         ql_enable_interrupts(qdev);
3167         ql_enable_all_completion_interrupts(qdev);
3168         if ((ql_read32(qdev, STS) & qdev->port_init)) {
3169                 netif_carrier_on(qdev->ndev);
3170                 netif_start_queue(qdev->ndev);
3171         }
3172
3173         return 0;
3174 err_init:
3175         ql_adapter_reset(qdev);
3176         return err;
3177 }
3178
3179 static int ql_cycle_adapter(struct ql_adapter *qdev)
3180 {
3181         int status;
3182
3183         status = ql_adapter_down(qdev);
3184         if (status)
3185                 goto error;
3186
3187         status = ql_adapter_up(qdev);
3188         if (status)
3189                 goto error;
3190
3191         return status;
3192 error:
3193         QPRINTK(qdev, IFUP, ALERT,
3194                 "Driver up/down cycle failed, closing device\n");
3195         rtnl_lock();
3196         dev_close(qdev->ndev);
3197         rtnl_unlock();
3198         return status;
3199 }
3200
3201 static void ql_release_adapter_resources(struct ql_adapter *qdev)
3202 {
3203         ql_free_mem_resources(qdev);
3204         ql_free_irq(qdev);
3205 }
3206
3207 static int ql_get_adapter_resources(struct ql_adapter *qdev)
3208 {
3209         int status = 0;
3210
3211         if (ql_alloc_mem_resources(qdev)) {
3212                 QPRINTK(qdev, IFUP, ERR, "Unable to  allocate memory.\n");
3213                 return -ENOMEM;
3214         }
3215         status = ql_request_irq(qdev);
3216         if (status)
3217                 goto err_irq;
3218         return status;
3219 err_irq:
3220         ql_free_mem_resources(qdev);
3221         return status;
3222 }
3223
3224 static int qlge_close(struct net_device *ndev)
3225 {
3226         struct ql_adapter *qdev = netdev_priv(ndev);
3227
3228         /*
3229          * Wait for device to recover from a reset.
3230          * (Rarely happens, but possible.)
3231          */
3232         while (!test_bit(QL_ADAPTER_UP, &qdev->flags))
3233                 msleep(1);
3234         ql_adapter_down(qdev);
3235         ql_release_adapter_resources(qdev);
3236         return 0;
3237 }
3238
3239 static int ql_configure_rings(struct ql_adapter *qdev)
3240 {
3241         int i;
3242         struct rx_ring *rx_ring;
3243         struct tx_ring *tx_ring;
3244         int cpu_cnt = num_online_cpus();
3245
3246         /*
3247          * For each processor present we allocate one
3248          * rx_ring for outbound completions, and one
3249          * rx_ring for inbound completions.  Plus there is
3250          * always the one default queue.  For the CPU
3251          * counts we end up with the following rx_rings:
3252          * rx_ring count =
3253          *  one default queue +
3254          *  (CPU count * outbound completion rx_ring) +
3255          *  (CPU count * inbound (RSS) completion rx_ring)
3256          * To keep it simple we limit the total number of
3257          * queues to < 32, so we truncate CPU to 8.
3258          * This limitation can be removed when requested.
3259          */
3260
3261         if (cpu_cnt > MAX_CPUS)
3262                 cpu_cnt = MAX_CPUS;
3263
3264         /*
3265          * rx_ring[0] is always the default queue.
3266          */
3267         /* Allocate outbound completion ring for each CPU. */
3268         qdev->tx_ring_count = cpu_cnt;
3269         /* Allocate inbound completion (RSS) ring for each CPU. */
3270         qdev->rss_ring_count = cpu_cnt;
3271         /* cq_id for the first inbound ring handler. */
3272         qdev->rss_ring_first_cq_id = cpu_cnt + 1;
3273         /*
3274          * qdev->rx_ring_count:
3275          * Total number of rx_rings.  This includes the one
3276          * default queue, a number of outbound completion
3277          * handler rx_rings, and the number of inbound
3278          * completion handler rx_rings.
3279          */
3280         qdev->rx_ring_count = qdev->tx_ring_count + qdev->rss_ring_count + 1;
3281
3282         for (i = 0; i < qdev->tx_ring_count; i++) {
3283                 tx_ring = &qdev->tx_ring[i];
3284                 memset((void *)tx_ring, 0, sizeof(tx_ring));
3285                 tx_ring->qdev = qdev;
3286                 tx_ring->wq_id = i;
3287                 tx_ring->wq_len = qdev->tx_ring_size;
3288                 tx_ring->wq_size =
3289                     tx_ring->wq_len * sizeof(struct ob_mac_iocb_req);
3290
3291                 /*
3292                  * The completion queue ID for the tx rings start
3293                  * immediately after the default Q ID, which is zero.
3294                  */
3295                 tx_ring->cq_id = i + 1;
3296         }
3297
3298         for (i = 0; i < qdev->rx_ring_count; i++) {
3299                 rx_ring = &qdev->rx_ring[i];
3300                 memset((void *)rx_ring, 0, sizeof(rx_ring));
3301                 rx_ring->qdev = qdev;
3302                 rx_ring->cq_id = i;
3303                 rx_ring->cpu = i % cpu_cnt;     /* CPU to run handler on. */
3304                 if (i == 0) {   /* Default queue at index 0. */
3305                         /*
3306                          * Default queue handles bcast/mcast plus
3307                          * async events.  Needs buffers.
3308                          */
3309                         rx_ring->cq_len = qdev->rx_ring_size;
3310                         rx_ring->cq_size =
3311                             rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3312                         rx_ring->lbq_len = NUM_LARGE_BUFFERS;
3313                         rx_ring->lbq_size =
3314                             rx_ring->lbq_len * sizeof(__le64);
3315                         rx_ring->lbq_buf_size = LARGE_BUFFER_SIZE;
3316                         rx_ring->sbq_len = NUM_SMALL_BUFFERS;
3317                         rx_ring->sbq_size =
3318                             rx_ring->sbq_len * sizeof(__le64);
3319                         rx_ring->sbq_buf_size = SMALL_BUFFER_SIZE * 2;
3320                         rx_ring->type = DEFAULT_Q;
3321                 } else if (i < qdev->rss_ring_first_cq_id) {
3322                         /*
3323                          * Outbound queue handles outbound completions only.
3324                          */
3325                         /* outbound cq is same size as tx_ring it services. */
3326                         rx_ring->cq_len = qdev->tx_ring_size;
3327                         rx_ring->cq_size =
3328                             rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3329                         rx_ring->lbq_len = 0;
3330                         rx_ring->lbq_size = 0;
3331                         rx_ring->lbq_buf_size = 0;
3332                         rx_ring->sbq_len = 0;
3333                         rx_ring->sbq_size = 0;
3334                         rx_ring->sbq_buf_size = 0;
3335                         rx_ring->type = TX_Q;
3336                 } else {        /* Inbound completions (RSS) queues */
3337                         /*
3338                          * Inbound queues handle unicast frames only.
3339                          */
3340                         rx_ring->cq_len = qdev->rx_ring_size;
3341                         rx_ring->cq_size =
3342                             rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3343                         rx_ring->lbq_len = NUM_LARGE_BUFFERS;
3344                         rx_ring->lbq_size =
3345                             rx_ring->lbq_len * sizeof(__le64);
3346                         rx_ring->lbq_buf_size = LARGE_BUFFER_SIZE;
3347                         rx_ring->sbq_len = NUM_SMALL_BUFFERS;
3348                         rx_ring->sbq_size =
3349                             rx_ring->sbq_len * sizeof(__le64);
3350                         rx_ring->sbq_buf_size = SMALL_BUFFER_SIZE * 2;
3351                         rx_ring->type = RX_Q;
3352                 }
3353         }
3354         return 0;
3355 }
3356
3357 static int qlge_open(struct net_device *ndev)
3358 {
3359         int err = 0;
3360         struct ql_adapter *qdev = netdev_priv(ndev);
3361
3362         err = ql_configure_rings(qdev);
3363         if (err)
3364                 return err;
3365
3366         err = ql_get_adapter_resources(qdev);
3367         if (err)
3368                 goto error_up;
3369
3370         err = ql_adapter_up(qdev);
3371         if (err)
3372                 goto error_up;
3373
3374         return err;
3375
3376 error_up:
3377         ql_release_adapter_resources(qdev);
3378         return err;
3379 }
3380
3381 static int qlge_change_mtu(struct net_device *ndev, int new_mtu)
3382 {
3383         struct ql_adapter *qdev = netdev_priv(ndev);
3384
3385         if (ndev->mtu == 1500 && new_mtu == 9000) {
3386                 QPRINTK(qdev, IFUP, ERR, "Changing to jumbo MTU.\n");
3387         } else if (ndev->mtu == 9000 && new_mtu == 1500) {
3388                 QPRINTK(qdev, IFUP, ERR, "Changing to normal MTU.\n");
3389         } else if ((ndev->mtu == 1500 && new_mtu == 1500) ||
3390                    (ndev->mtu == 9000 && new_mtu == 9000)) {
3391                 return 0;
3392         } else
3393                 return -EINVAL;
3394         ndev->mtu = new_mtu;
3395         return 0;
3396 }
3397
3398 static struct net_device_stats *qlge_get_stats(struct net_device
3399                                                *ndev)
3400 {
3401         struct ql_adapter *qdev = netdev_priv(ndev);
3402         return &qdev->stats;
3403 }
3404
3405 static void qlge_set_multicast_list(struct net_device *ndev)
3406 {
3407         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3408         struct dev_mc_list *mc_ptr;
3409         int i;
3410
3411         spin_lock(&qdev->hw_lock);
3412         /*
3413          * Set or clear promiscuous mode if a
3414          * transition is taking place.
3415          */
3416         if (ndev->flags & IFF_PROMISC) {
3417                 if (!test_bit(QL_PROMISCUOUS, &qdev->flags)) {
3418                         if (ql_set_routing_reg
3419                             (qdev, RT_IDX_PROMISCUOUS_SLOT, RT_IDX_VALID, 1)) {
3420                                 QPRINTK(qdev, HW, ERR,
3421                                         "Failed to set promiscous mode.\n");
3422                         } else {
3423                                 set_bit(QL_PROMISCUOUS, &qdev->flags);
3424                         }
3425                 }
3426         } else {
3427                 if (test_bit(QL_PROMISCUOUS, &qdev->flags)) {
3428                         if (ql_set_routing_reg
3429                             (qdev, RT_IDX_PROMISCUOUS_SLOT, RT_IDX_VALID, 0)) {
3430                                 QPRINTK(qdev, HW, ERR,
3431                                         "Failed to clear promiscous mode.\n");
3432                         } else {
3433                                 clear_bit(QL_PROMISCUOUS, &qdev->flags);
3434                         }
3435                 }
3436         }
3437
3438         /*
3439          * Set or clear all multicast mode if a
3440          * transition is taking place.
3441          */
3442         if ((ndev->flags & IFF_ALLMULTI) ||
3443             (ndev->mc_count > MAX_MULTICAST_ENTRIES)) {
3444                 if (!test_bit(QL_ALLMULTI, &qdev->flags)) {
3445                         if (ql_set_routing_reg
3446                             (qdev, RT_IDX_ALLMULTI_SLOT, RT_IDX_MCAST, 1)) {
3447                                 QPRINTK(qdev, HW, ERR,
3448                                         "Failed to set all-multi mode.\n");
3449                         } else {
3450                                 set_bit(QL_ALLMULTI, &qdev->flags);
3451                         }
3452                 }
3453         } else {
3454                 if (test_bit(QL_ALLMULTI, &qdev->flags)) {
3455                         if (ql_set_routing_reg
3456                             (qdev, RT_IDX_ALLMULTI_SLOT, RT_IDX_MCAST, 0)) {
3457                                 QPRINTK(qdev, HW, ERR,
3458                                         "Failed to clear all-multi mode.\n");
3459                         } else {
3460                                 clear_bit(QL_ALLMULTI, &qdev->flags);
3461                         }
3462                 }
3463         }
3464
3465         if (ndev->mc_count) {
3466                 for (i = 0, mc_ptr = ndev->mc_list; mc_ptr;
3467                      i++, mc_ptr = mc_ptr->next)
3468                         if (ql_set_mac_addr_reg(qdev, (u8 *) mc_ptr->dmi_addr,
3469                                                 MAC_ADDR_TYPE_MULTI_MAC, i)) {
3470                                 QPRINTK(qdev, HW, ERR,
3471                                         "Failed to loadmulticast address.\n");
3472                                 goto exit;
3473                         }
3474                 if (ql_set_routing_reg
3475                     (qdev, RT_IDX_MCAST_MATCH_SLOT, RT_IDX_MCAST_MATCH, 1)) {
3476                         QPRINTK(qdev, HW, ERR,
3477                                 "Failed to set multicast match mode.\n");
3478                 } else {
3479                         set_bit(QL_ALLMULTI, &qdev->flags);
3480                 }
3481         }
3482 exit:
3483         spin_unlock(&qdev->hw_lock);
3484 }
3485
3486 static int qlge_set_mac_address(struct net_device *ndev, void *p)
3487 {
3488         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3489         struct sockaddr *addr = p;
3490         int ret = 0;
3491
3492         if (netif_running(ndev))
3493                 return -EBUSY;
3494
3495         if (!is_valid_ether_addr(addr->sa_data))
3496                 return -EADDRNOTAVAIL;
3497         memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
3498
3499         spin_lock(&qdev->hw_lock);
3500         if (ql_set_mac_addr_reg(qdev, (u8 *) ndev->dev_addr,
3501                         MAC_ADDR_TYPE_CAM_MAC, qdev->func)) {/* Unicast */
3502                 QPRINTK(qdev, HW, ERR, "Failed to load MAC address.\n");
3503                 ret = -1;
3504         }
3505         spin_unlock(&qdev->hw_lock);
3506
3507         return ret;
3508 }
3509
3510 static void qlge_tx_timeout(struct net_device *ndev)
3511 {
3512         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3513         ql_queue_asic_error(qdev);
3514 }
3515
3516 static void ql_asic_reset_work(struct work_struct *work)
3517 {
3518         struct ql_adapter *qdev =
3519             container_of(work, struct ql_adapter, asic_reset_work.work);
3520         ql_cycle_adapter(qdev);
3521 }
3522
3523 static void ql_get_board_info(struct ql_adapter *qdev)
3524 {
3525         qdev->func =
3526             (ql_read32(qdev, STS) & STS_FUNC_ID_MASK) >> STS_FUNC_ID_SHIFT;
3527         if (qdev->func) {
3528                 qdev->xg_sem_mask = SEM_XGMAC1_MASK;
3529                 qdev->port_link_up = STS_PL1;
3530                 qdev->port_init = STS_PI1;
3531                 qdev->mailbox_in = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC2_MBI;
3532                 qdev->mailbox_out = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC2_MBO;
3533         } else {
3534                 qdev->xg_sem_mask = SEM_XGMAC0_MASK;
3535                 qdev->port_link_up = STS_PL0;
3536                 qdev->port_init = STS_PI0;
3537                 qdev->mailbox_in = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC0_MBI;
3538                 qdev->mailbox_out = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC0_MBO;
3539         }
3540         qdev->chip_rev_id = ql_read32(qdev, REV_ID);
3541 }
3542
3543 static void ql_release_all(struct pci_dev *pdev)
3544 {
3545         struct net_device *ndev = pci_get_drvdata(pdev);
3546         struct ql_adapter *qdev = netdev_priv(ndev);
3547
3548         if (qdev->workqueue) {
3549                 destroy_workqueue(qdev->workqueue);
3550                 qdev->workqueue = NULL;
3551         }
3552         if (qdev->q_workqueue) {
3553                 destroy_workqueue(qdev->q_workqueue);
3554                 qdev->q_workqueue = NULL;
3555         }
3556         if (qdev->reg_base)
3557                 iounmap(qdev->reg_base);
3558         if (qdev->doorbell_area)
3559                 iounmap(qdev->doorbell_area);
3560         pci_release_regions(pdev);
3561         pci_set_drvdata(pdev, NULL);
3562 }
3563
3564 static int __devinit ql_init_device(struct pci_dev *pdev,
3565                                     struct net_device *ndev, int cards_found)
3566 {
3567         struct ql_adapter *qdev = netdev_priv(ndev);
3568         int pos, err = 0;
3569         u16 val16;
3570
3571         memset((void *)qdev, 0, sizeof(qdev));
3572         err = pci_enable_device(pdev);
3573         if (err) {
3574                 dev_err(&pdev->dev, "PCI device enable failed.\n");
3575                 return err;
3576         }
3577
3578         pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3579         if (pos <= 0) {
3580                 dev_err(&pdev->dev, PFX "Cannot find PCI Express capability, "
3581                         "aborting.\n");
3582                 goto err_out;
3583         } else {
3584                 pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &val16);
3585                 val16 &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
3586                 val16 |= (PCI_EXP_DEVCTL_CERE |
3587                           PCI_EXP_DEVCTL_NFERE |
3588                           PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE);
3589                 pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, val16);
3590         }
3591
3592         err = pci_request_regions(pdev, DRV_NAME);
3593         if (err) {
3594                 dev_err(&pdev->dev, "PCI region request failed.\n");
3595                 goto err_out;
3596         }
3597
3598         pci_set_master(pdev);
3599         if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3600                 set_bit(QL_DMA64, &qdev->flags);
3601                 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3602         } else {
3603                 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3604                 if (!err)
3605                        err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3606         }
3607
3608         if (err) {
3609                 dev_err(&pdev->dev, "No usable DMA configuration.\n");
3610                 goto err_out;
3611         }
3612
3613         pci_set_drvdata(pdev, ndev);
3614         qdev->reg_base =
3615             ioremap_nocache(pci_resource_start(pdev, 1),
3616                             pci_resource_len(pdev, 1));
3617         if (!qdev->reg_base) {
3618                 dev_err(&pdev->dev, "Register mapping failed.\n");
3619                 err = -ENOMEM;
3620                 goto err_out;
3621         }
3622
3623         qdev->doorbell_area_size = pci_resource_len(pdev, 3);
3624         qdev->doorbell_area =
3625             ioremap_nocache(pci_resource_start(pdev, 3),
3626                             pci_resource_len(pdev, 3));
3627         if (!qdev->doorbell_area) {
3628                 dev_err(&pdev->dev, "Doorbell register mapping failed.\n");
3629                 err = -ENOMEM;
3630                 goto err_out;
3631         }
3632
3633         ql_get_board_info(qdev);
3634         qdev->ndev = ndev;
3635         qdev->pdev = pdev;
3636         qdev->msg_enable = netif_msg_init(debug, default_msg);
3637         spin_lock_init(&qdev->hw_lock);
3638         spin_lock_init(&qdev->stats_lock);
3639
3640         /* make sure the EEPROM is good */
3641         err = ql_get_flash_params(qdev);
3642         if (err) {
3643                 dev_err(&pdev->dev, "Invalid FLASH.\n");
3644                 goto err_out;
3645         }
3646
3647         if (!is_valid_ether_addr(qdev->flash.mac_addr))
3648                 goto err_out;
3649
3650         memcpy(ndev->dev_addr, qdev->flash.mac_addr, ndev->addr_len);
3651         memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
3652
3653         /* Set up the default ring sizes. */
3654         qdev->tx_ring_size = NUM_TX_RING_ENTRIES;
3655         qdev->rx_ring_size = NUM_RX_RING_ENTRIES;
3656
3657         /* Set up the coalescing parameters. */
3658         qdev->rx_coalesce_usecs = DFLT_COALESCE_WAIT;
3659         qdev->tx_coalesce_usecs = DFLT_COALESCE_WAIT;
3660         qdev->rx_max_coalesced_frames = DFLT_INTER_FRAME_WAIT;
3661         qdev->tx_max_coalesced_frames = DFLT_INTER_FRAME_WAIT;
3662
3663         /*
3664          * Set up the operating parameters.
3665          */
3666         qdev->rx_csum = 1;
3667
3668         qdev->q_workqueue = create_workqueue(ndev->name);
3669         qdev->workqueue = create_singlethread_workqueue(ndev->name);
3670         INIT_DELAYED_WORK(&qdev->asic_reset_work, ql_asic_reset_work);
3671         INIT_DELAYED_WORK(&qdev->mpi_reset_work, ql_mpi_reset_work);
3672         INIT_DELAYED_WORK(&qdev->mpi_work, ql_mpi_work);
3673
3674         if (!cards_found) {
3675                 dev_info(&pdev->dev, "%s\n", DRV_STRING);
3676                 dev_info(&pdev->dev, "Driver name: %s, Version: %s.\n",
3677                          DRV_NAME, DRV_VERSION);
3678         }
3679         return 0;
3680 err_out:
3681         ql_release_all(pdev);
3682         pci_disable_device(pdev);
3683         return err;
3684 }
3685
3686
3687 static const struct net_device_ops qlge_netdev_ops = {
3688         .ndo_open               = qlge_open,
3689         .ndo_stop               = qlge_close,
3690         .ndo_start_xmit         = qlge_send,
3691         .ndo_change_mtu         = qlge_change_mtu,
3692         .ndo_get_stats          = qlge_get_stats,
3693         .ndo_set_multicast_list = qlge_set_multicast_list,
3694         .ndo_set_mac_address    = qlge_set_mac_address,
3695         .ndo_validate_addr      = eth_validate_addr,
3696         .ndo_tx_timeout         = qlge_tx_timeout,
3697         .ndo_vlan_rx_register   = ql_vlan_rx_register,
3698         .ndo_vlan_rx_add_vid    = ql_vlan_rx_add_vid,
3699         .ndo_vlan_rx_kill_vid   = ql_vlan_rx_kill_vid,
3700 };
3701
3702 static int __devinit qlge_probe(struct pci_dev *pdev,
3703                                 const struct pci_device_id *pci_entry)
3704 {
3705         struct net_device *ndev = NULL;
3706         struct ql_adapter *qdev = NULL;
3707         static int cards_found = 0;
3708         int err = 0;
3709
3710         ndev = alloc_etherdev(sizeof(struct ql_adapter));
3711         if (!ndev)
3712                 return -ENOMEM;
3713
3714         err = ql_init_device(pdev, ndev, cards_found);
3715         if (err < 0) {
3716                 free_netdev(ndev);
3717                 return err;
3718         }
3719
3720         qdev = netdev_priv(ndev);
3721         SET_NETDEV_DEV(ndev, &pdev->dev);
3722         ndev->features = (0
3723                           | NETIF_F_IP_CSUM
3724                           | NETIF_F_SG
3725                           | NETIF_F_TSO
3726                           | NETIF_F_TSO6
3727                           | NETIF_F_TSO_ECN
3728                           | NETIF_F_HW_VLAN_TX
3729                           | NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_FILTER);
3730
3731         if (test_bit(QL_DMA64, &qdev->flags))
3732                 ndev->features |= NETIF_F_HIGHDMA;
3733
3734         /*
3735          * Set up net_device structure.
3736          */
3737         ndev->tx_queue_len = qdev->tx_ring_size;
3738         ndev->irq = pdev->irq;
3739
3740         ndev->netdev_ops = &qlge_netdev_ops;
3741         SET_ETHTOOL_OPS(ndev, &qlge_ethtool_ops);
3742         ndev->watchdog_timeo = 10 * HZ;
3743
3744         err = register_netdev(ndev);
3745         if (err) {
3746                 dev_err(&pdev->dev, "net device registration failed.\n");
3747                 ql_release_all(pdev);
3748                 pci_disable_device(pdev);
3749                 return err;
3750         }
3751         netif_carrier_off(ndev);
3752         netif_stop_queue(ndev);
3753         ql_display_dev_info(ndev);
3754         cards_found++;
3755         return 0;
3756 }
3757
3758 static void __devexit qlge_remove(struct pci_dev *pdev)
3759 {
3760         struct net_device *ndev = pci_get_drvdata(pdev);
3761         unregister_netdev(ndev);
3762         ql_release_all(pdev);
3763         pci_disable_device(pdev);
3764         free_netdev(ndev);
3765 }
3766
3767 /*
3768  * This callback is called by the PCI subsystem whenever
3769  * a PCI bus error is detected.
3770  */
3771 static pci_ers_result_t qlge_io_error_detected(struct pci_dev *pdev,
3772                                                enum pci_channel_state state)
3773 {
3774         struct net_device *ndev = pci_get_drvdata(pdev);
3775         struct ql_adapter *qdev = netdev_priv(ndev);
3776
3777         if (netif_running(ndev))
3778                 ql_adapter_down(qdev);
3779
3780         pci_disable_device(pdev);
3781
3782         /* Request a slot reset. */
3783         return PCI_ERS_RESULT_NEED_RESET;
3784 }
3785
3786 /*
3787  * This callback is called after the PCI buss has been reset.
3788  * Basically, this tries to restart the card from scratch.
3789  * This is a shortened version of the device probe/discovery code,
3790  * it resembles the first-half of the () routine.
3791  */
3792 static pci_ers_result_t qlge_io_slot_reset(struct pci_dev *pdev)
3793 {
3794         struct net_device *ndev = pci_get_drvdata(pdev);
3795         struct ql_adapter *qdev = netdev_priv(ndev);
3796
3797         if (pci_enable_device(pdev)) {
3798                 QPRINTK(qdev, IFUP, ERR,
3799                         "Cannot re-enable PCI device after reset.\n");
3800                 return PCI_ERS_RESULT_DISCONNECT;
3801         }
3802
3803         pci_set_master(pdev);
3804
3805         netif_carrier_off(ndev);
3806         netif_stop_queue(ndev);
3807         ql_adapter_reset(qdev);
3808
3809         /* Make sure the EEPROM is good */
3810         memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
3811
3812         if (!is_valid_ether_addr(ndev->perm_addr)) {
3813                 QPRINTK(qdev, IFUP, ERR, "After reset, invalid MAC address.\n");
3814                 return PCI_ERS_RESULT_DISCONNECT;
3815         }
3816
3817         return PCI_ERS_RESULT_RECOVERED;
3818 }
3819
3820 static void qlge_io_resume(struct pci_dev *pdev)
3821 {
3822         struct net_device *ndev = pci_get_drvdata(pdev);
3823         struct ql_adapter *qdev = netdev_priv(ndev);
3824
3825         pci_set_master(pdev);
3826
3827         if (netif_running(ndev)) {
3828                 if (ql_adapter_up(qdev)) {
3829                         QPRINTK(qdev, IFUP, ERR,
3830                                 "Device initialization failed after reset.\n");
3831                         return;
3832                 }
3833         }
3834
3835         netif_device_attach(ndev);
3836 }
3837
3838 static struct pci_error_handlers qlge_err_handler = {
3839         .error_detected = qlge_io_error_detected,
3840         .slot_reset = qlge_io_slot_reset,
3841         .resume = qlge_io_resume,
3842 };
3843
3844 static int qlge_suspend(struct pci_dev *pdev, pm_message_t state)
3845 {
3846         struct net_device *ndev = pci_get_drvdata(pdev);
3847         struct ql_adapter *qdev = netdev_priv(ndev);
3848         int err, i;
3849
3850         netif_device_detach(ndev);
3851
3852         if (netif_running(ndev)) {
3853                 err = ql_adapter_down(qdev);
3854                 if (!err)
3855                         return err;
3856         }
3857
3858         for (i = qdev->rss_ring_first_cq_id; i < qdev->rx_ring_count; i++)
3859                 netif_napi_del(&qdev->rx_ring[i].napi);
3860
3861         err = pci_save_state(pdev);
3862         if (err)
3863                 return err;
3864
3865         pci_disable_device(pdev);
3866
3867         pci_set_power_state(pdev, pci_choose_state(pdev, state));
3868
3869         return 0;
3870 }
3871
3872 #ifdef CONFIG_PM
3873 static int qlge_resume(struct pci_dev *pdev)
3874 {
3875         struct net_device *ndev = pci_get_drvdata(pdev);
3876         struct ql_adapter *qdev = netdev_priv(ndev);
3877         int err;
3878
3879         pci_set_power_state(pdev, PCI_D0);
3880         pci_restore_state(pdev);
3881         err = pci_enable_device(pdev);
3882         if (err) {
3883                 QPRINTK(qdev, IFUP, ERR, "Cannot enable PCI device from suspend\n");
3884                 return err;
3885         }
3886         pci_set_master(pdev);
3887
3888         pci_enable_wake(pdev, PCI_D3hot, 0);
3889         pci_enable_wake(pdev, PCI_D3cold, 0);
3890
3891         if (netif_running(ndev)) {
3892                 err = ql_adapter_up(qdev);
3893                 if (err)
3894                         return err;
3895         }
3896
3897         netif_device_attach(ndev);
3898
3899         return 0;
3900 }
3901 #endif /* CONFIG_PM */
3902
3903 static void qlge_shutdown(struct pci_dev *pdev)
3904 {
3905         qlge_suspend(pdev, PMSG_SUSPEND);
3906 }
3907
3908 static struct pci_driver qlge_driver = {
3909         .name = DRV_NAME,
3910         .id_table = qlge_pci_tbl,
3911         .probe = qlge_probe,
3912         .remove = __devexit_p(qlge_remove),
3913 #ifdef CONFIG_PM
3914         .suspend = qlge_suspend,
3915         .resume = qlge_resume,
3916 #endif
3917         .shutdown = qlge_shutdown,
3918         .err_handler = &qlge_err_handler
3919 };
3920
3921 static int __init qlge_init_module(void)
3922 {
3923         return pci_register_driver(&qlge_driver);
3924 }
3925
3926 static void __exit qlge_exit(void)
3927 {
3928         pci_unregister_driver(&qlge_driver);
3929 }
3930
3931 module_init(qlge_init_module);
3932 module_exit(qlge_exit);