2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/firmware.h>
28 #include <linux/pci-aspm.h>
29 #include <linux/prefetch.h>
31 #include <asm/system.h>
35 #define RTL8169_VERSION "2.3LK-NAPI"
36 #define MODULENAME "r8169"
37 #define PFX MODULENAME ": "
39 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
40 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
41 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
42 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
43 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
46 #define assert(expr) \
48 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
49 #expr,__FILE__,__func__,__LINE__); \
51 #define dprintk(fmt, args...) \
52 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
54 #define assert(expr) do {} while (0)
55 #define dprintk(fmt, args...) do {} while (0)
56 #endif /* RTL8169_DEBUG */
58 #define R8169_MSG_DEFAULT \
59 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
61 #define TX_BUFFS_AVAIL(tp) \
62 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
64 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
65 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
66 static const int multicast_filter_limit = 32;
68 /* MAC address length */
69 #define MAC_ADDR_LEN 6
71 #define MAX_READ_REQUEST_SHIFT 12
72 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
73 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
74 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
75 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
76 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
78 #define R8169_REGS_SIZE 256
79 #define R8169_NAPI_WEIGHT 64
80 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
81 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
82 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
83 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
84 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
86 #define RTL8169_TX_TIMEOUT (6*HZ)
87 #define RTL8169_PHY_TIMEOUT (10*HZ)
89 #define RTL_EEPROM_SIG cpu_to_le32(0x8129)
90 #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
91 #define RTL_EEPROM_SIG_ADDR 0x0000
93 /* write/read MMIO register */
94 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
95 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
96 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
97 #define RTL_R8(reg) readb (ioaddr + (reg))
98 #define RTL_R16(reg) readw (ioaddr + (reg))
99 #define RTL_R32(reg) readl (ioaddr + (reg))
102 RTL_GIGA_MAC_VER_01 = 0,
135 RTL_GIGA_MAC_NONE = 0xff,
138 enum rtl_tx_desc_version {
143 #define JUMBO_1K ETH_DATA_LEN
144 #define JUMBO_4K (4*1024 - ETH_HLEN - 2)
145 #define JUMBO_6K (6*1024 - ETH_HLEN - 2)
146 #define JUMBO_7K (7*1024 - ETH_HLEN - 2)
147 #define JUMBO_9K (9*1024 - ETH_HLEN - 2)
149 #define _R(NAME,TD,FW,SZ,B) { \
157 static const struct {
159 enum rtl_tx_desc_version txd_version;
163 } rtl_chip_infos[] = {
165 [RTL_GIGA_MAC_VER_01] =
166 _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K, true),
167 [RTL_GIGA_MAC_VER_02] =
168 _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K, true),
169 [RTL_GIGA_MAC_VER_03] =
170 _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K, true),
171 [RTL_GIGA_MAC_VER_04] =
172 _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K, true),
173 [RTL_GIGA_MAC_VER_05] =
174 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
175 [RTL_GIGA_MAC_VER_06] =
176 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
178 [RTL_GIGA_MAC_VER_07] =
179 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
180 [RTL_GIGA_MAC_VER_08] =
181 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
182 [RTL_GIGA_MAC_VER_09] =
183 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
184 [RTL_GIGA_MAC_VER_10] =
185 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
186 [RTL_GIGA_MAC_VER_11] =
187 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
188 [RTL_GIGA_MAC_VER_12] =
189 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
190 [RTL_GIGA_MAC_VER_13] =
191 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
192 [RTL_GIGA_MAC_VER_14] =
193 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
194 [RTL_GIGA_MAC_VER_15] =
195 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
196 [RTL_GIGA_MAC_VER_16] =
197 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
198 [RTL_GIGA_MAC_VER_17] =
199 _R("RTL8168b/8111b", RTL_TD_1, NULL, JUMBO_4K, false),
200 [RTL_GIGA_MAC_VER_18] =
201 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
202 [RTL_GIGA_MAC_VER_19] =
203 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
204 [RTL_GIGA_MAC_VER_20] =
205 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
206 [RTL_GIGA_MAC_VER_21] =
207 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
208 [RTL_GIGA_MAC_VER_22] =
209 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
210 [RTL_GIGA_MAC_VER_23] =
211 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
212 [RTL_GIGA_MAC_VER_24] =
213 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
214 [RTL_GIGA_MAC_VER_25] =
215 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1,
217 [RTL_GIGA_MAC_VER_26] =
218 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2,
220 [RTL_GIGA_MAC_VER_27] =
221 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
222 [RTL_GIGA_MAC_VER_28] =
223 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
224 [RTL_GIGA_MAC_VER_29] =
225 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
227 [RTL_GIGA_MAC_VER_30] =
228 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
230 [RTL_GIGA_MAC_VER_31] =
231 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
232 [RTL_GIGA_MAC_VER_32] =
233 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1,
235 [RTL_GIGA_MAC_VER_33] =
236 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2,
247 static void rtl_hw_start_8169(struct net_device *);
248 static void rtl_hw_start_8168(struct net_device *);
249 static void rtl_hw_start_8101(struct net_device *);
251 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
252 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
253 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
254 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
255 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
256 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
257 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
258 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
259 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
260 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
261 { PCI_VENDOR_ID_LINKSYS, 0x1032,
262 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
264 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
268 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
270 static int rx_buf_sz = 16383;
277 MAC0 = 0, /* Ethernet hardware address. */
279 MAR0 = 8, /* Multicast filter. */
280 CounterAddrLow = 0x10,
281 CounterAddrHigh = 0x14,
282 TxDescStartAddrLow = 0x20,
283 TxDescStartAddrHigh = 0x24,
284 TxHDescStartAddrLow = 0x28,
285 TxHDescStartAddrHigh = 0x2c,
295 #define RTL_RX_CONFIG_MASK 0xff7e1880u
311 RxDescAddrLow = 0xe4,
312 RxDescAddrHigh = 0xe8,
313 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
315 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
317 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
319 #define TxPacketMax (8064 >> 7)
322 FuncEventMask = 0xf4,
323 FuncPresetState = 0xf8,
324 FuncForceEvent = 0xfc,
327 enum rtl8110_registers {
333 enum rtl8168_8101_registers {
336 #define CSIAR_FLAG 0x80000000
337 #define CSIAR_WRITE_CMD 0x80000000
338 #define CSIAR_BYTE_ENABLE 0x0f
339 #define CSIAR_BYTE_ENABLE_SHIFT 12
340 #define CSIAR_ADDR_MASK 0x0fff
343 #define EPHYAR_FLAG 0x80000000
344 #define EPHYAR_WRITE_CMD 0x80000000
345 #define EPHYAR_REG_MASK 0x1f
346 #define EPHYAR_REG_SHIFT 16
347 #define EPHYAR_DATA_MASK 0xffff
349 #define PM_SWITCH (1 << 6)
351 #define FIX_NAK_1 (1 << 4)
352 #define FIX_NAK_2 (1 << 3)
355 #define EN_NDP (1 << 3)
356 #define EN_OOB_RESET (1 << 2)
358 #define EFUSEAR_FLAG 0x80000000
359 #define EFUSEAR_WRITE_CMD 0x80000000
360 #define EFUSEAR_READ_CMD 0x00000000
361 #define EFUSEAR_REG_MASK 0x03ff
362 #define EFUSEAR_REG_SHIFT 8
363 #define EFUSEAR_DATA_MASK 0xff
366 enum rtl8168_registers {
369 #define ERIAR_FLAG 0x80000000
370 #define ERIAR_WRITE_CMD 0x80000000
371 #define ERIAR_READ_CMD 0x00000000
372 #define ERIAR_ADDR_BYTE_ALIGN 4
373 #define ERIAR_EXGMAC 0
376 #define ERIAR_TYPE_SHIFT 16
377 #define ERIAR_BYTEEN 0x0f
378 #define ERIAR_BYTEEN_SHIFT 12
379 EPHY_RXER_NUM = 0x7c,
380 OCPDR = 0xb0, /* OCP GPHY access */
381 #define OCPDR_WRITE_CMD 0x80000000
382 #define OCPDR_READ_CMD 0x00000000
383 #define OCPDR_REG_MASK 0x7f
384 #define OCPDR_GPHY_REG_SHIFT 16
385 #define OCPDR_DATA_MASK 0xffff
387 #define OCPAR_FLAG 0x80000000
388 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
389 #define OCPAR_GPHY_READ_CMD 0x0000f060
390 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
391 MISC = 0xf0, /* 8168e only. */
392 #define TXPLA_RST (1 << 29)
395 enum rtl_register_content {
396 /* InterruptStatusBits */
400 TxDescUnavail = 0x0080,
423 /* TXPoll register p.5 */
424 HPQ = 0x80, /* Poll cmd on the high prio queue */
425 NPQ = 0x40, /* Poll cmd on the low prio queue */
426 FSWInt = 0x01, /* Forced software interrupt */
430 Cfg9346_Unlock = 0xc0,
435 AcceptBroadcast = 0x08,
436 AcceptMulticast = 0x04,
438 AcceptAllPhys = 0x01,
445 TxInterFrameGapShift = 24,
446 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
448 /* Config1 register p.24 */
451 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
452 Speed_down = (1 << 4),
456 PMEnable = (1 << 0), /* Power Management Enable */
458 /* Config2 register p. 25 */
459 PCI_Clock_66MHz = 0x01,
460 PCI_Clock_33MHz = 0x00,
462 /* Config3 register p.25 */
463 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
464 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
465 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
466 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
468 /* Config4 register */
469 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
471 /* Config5 register p.27 */
472 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
473 MWF = (1 << 5), /* Accept Multicast wakeup frame */
474 UWF = (1 << 4), /* Accept Unicast wakeup frame */
476 LanWake = (1 << 1), /* LanWake enable/disable */
477 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
480 TBIReset = 0x80000000,
481 TBILoopback = 0x40000000,
482 TBINwEnable = 0x20000000,
483 TBINwRestart = 0x10000000,
484 TBILinkOk = 0x02000000,
485 TBINwComplete = 0x01000000,
488 EnableBist = (1 << 15), // 8168 8101
489 Mac_dbgo_oe = (1 << 14), // 8168 8101
490 Normal_mode = (1 << 13), // unused
491 Force_half_dup = (1 << 12), // 8168 8101
492 Force_rxflow_en = (1 << 11), // 8168 8101
493 Force_txflow_en = (1 << 10), // 8168 8101
494 Cxpl_dbg_sel = (1 << 9), // 8168 8101
495 ASF = (1 << 8), // 8168 8101
496 PktCntrDisable = (1 << 7), // 8168 8101
497 Mac_dbgo_sel = 0x001c, // 8168
502 INTT_0 = 0x0000, // 8168
503 INTT_1 = 0x0001, // 8168
504 INTT_2 = 0x0002, // 8168
505 INTT_3 = 0x0003, // 8168
507 /* rtl8169_PHYstatus */
518 TBILinkOK = 0x02000000,
520 /* DumpCounterCommand */
525 /* First doubleword. */
526 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
527 RingEnd = (1 << 30), /* End of descriptor ring */
528 FirstFrag = (1 << 29), /* First segment of a packet */
529 LastFrag = (1 << 28), /* Final segment of a packet */
533 enum rtl_tx_desc_bit {
534 /* First doubleword. */
535 TD_LSO = (1 << 27), /* Large Send Offload */
536 #define TD_MSS_MAX 0x07ffu /* MSS value */
538 /* Second doubleword. */
539 TxVlanTag = (1 << 17), /* Add VLAN tag */
542 /* 8169, 8168b and 810x except 8102e. */
543 enum rtl_tx_desc_bit_0 {
544 /* First doubleword. */
545 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
546 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
547 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
548 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
551 /* 8102e, 8168c and beyond. */
552 enum rtl_tx_desc_bit_1 {
553 /* Second doubleword. */
554 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
555 TD1_IP_CS = (1 << 29), /* Calculate IP checksum */
556 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
557 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
560 static const struct rtl_tx_desc_info {
567 } tx_desc_info [] = {
570 .udp = TD0_IP_CS | TD0_UDP_CS,
571 .tcp = TD0_IP_CS | TD0_TCP_CS
573 .mss_shift = TD0_MSS_SHIFT,
578 .udp = TD1_IP_CS | TD1_UDP_CS,
579 .tcp = TD1_IP_CS | TD1_TCP_CS
581 .mss_shift = TD1_MSS_SHIFT,
586 enum rtl_rx_desc_bit {
588 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
589 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
591 #define RxProtoUDP (PID1)
592 #define RxProtoTCP (PID0)
593 #define RxProtoIP (PID1 | PID0)
594 #define RxProtoMask RxProtoIP
596 IPFail = (1 << 16), /* IP checksum failed */
597 UDPFail = (1 << 15), /* UDP/IP checksum failed */
598 TCPFail = (1 << 14), /* TCP/IP checksum failed */
599 RxVlanTag = (1 << 16), /* VLAN tag available */
602 #define RsvdMask 0x3fffc000
619 u8 __pad[sizeof(void *) - sizeof(u32)];
623 RTL_FEATURE_WOL = (1 << 0),
624 RTL_FEATURE_MSI = (1 << 1),
625 RTL_FEATURE_GMII = (1 << 2),
628 struct rtl8169_counters {
635 __le32 tx_one_collision;
636 __le32 tx_multi_collision;
644 struct rtl8169_private {
645 void __iomem *mmio_addr; /* memory map physical address */
646 struct pci_dev *pci_dev;
647 struct net_device *dev;
648 struct napi_struct napi;
653 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
654 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
657 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
658 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
659 dma_addr_t TxPhyAddr;
660 dma_addr_t RxPhyAddr;
661 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
662 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
663 struct timer_list timer;
670 void (*write)(void __iomem *, int, int);
671 int (*read)(void __iomem *, int);
674 struct pll_power_ops {
675 void (*down)(struct rtl8169_private *);
676 void (*up)(struct rtl8169_private *);
680 void (*enable)(struct rtl8169_private *);
681 void (*disable)(struct rtl8169_private *);
684 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
685 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
686 void (*phy_reset_enable)(struct rtl8169_private *tp);
687 void (*hw_start)(struct net_device *);
688 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
689 unsigned int (*link_ok)(void __iomem *);
690 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
692 struct delayed_work task;
695 struct mii_if_info mii;
696 struct rtl8169_counters counters;
700 const struct firmware *fw;
701 #define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN);
704 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
705 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
706 module_param(use_dac, int, 0);
707 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
708 module_param_named(debug, debug.msg_enable, int, 0);
709 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
710 MODULE_LICENSE("GPL");
711 MODULE_VERSION(RTL8169_VERSION);
712 MODULE_FIRMWARE(FIRMWARE_8168D_1);
713 MODULE_FIRMWARE(FIRMWARE_8168D_2);
714 MODULE_FIRMWARE(FIRMWARE_8168E_1);
715 MODULE_FIRMWARE(FIRMWARE_8168E_2);
716 MODULE_FIRMWARE(FIRMWARE_8105E_1);
718 static int rtl8169_open(struct net_device *dev);
719 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
720 struct net_device *dev);
721 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
722 static int rtl8169_init_ring(struct net_device *dev);
723 static void rtl_hw_start(struct net_device *dev);
724 static int rtl8169_close(struct net_device *dev);
725 static void rtl_set_rx_mode(struct net_device *dev);
726 static void rtl8169_tx_timeout(struct net_device *dev);
727 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
728 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
729 void __iomem *, u32 budget);
730 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
731 static void rtl8169_down(struct net_device *dev);
732 static void rtl8169_rx_clear(struct rtl8169_private *tp);
733 static int rtl8169_poll(struct napi_struct *napi, int budget);
735 static const unsigned int rtl8169_rx_config =
736 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
738 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
740 struct net_device *dev = pci_get_drvdata(pdev);
741 struct rtl8169_private *tp = netdev_priv(dev);
742 int cap = tp->pcie_cap;
747 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
748 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
749 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
753 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
755 void __iomem *ioaddr = tp->mmio_addr;
758 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
759 for (i = 0; i < 20; i++) {
761 if (RTL_R32(OCPAR) & OCPAR_FLAG)
764 return RTL_R32(OCPDR);
767 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
769 void __iomem *ioaddr = tp->mmio_addr;
772 RTL_W32(OCPDR, data);
773 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
774 for (i = 0; i < 20; i++) {
776 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
781 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
783 void __iomem *ioaddr = tp->mmio_addr;
787 RTL_W32(ERIAR, 0x800010e8);
789 for (i = 0; i < 5; i++) {
791 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
795 ocp_write(tp, 0x1, 0x30, 0x00000001);
798 #define OOB_CMD_RESET 0x00
799 #define OOB_CMD_DRIVER_START 0x05
800 #define OOB_CMD_DRIVER_STOP 0x06
802 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
804 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
807 static void rtl8168_driver_start(struct rtl8169_private *tp)
812 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
814 reg = rtl8168_get_ocp_reg(tp);
816 for (i = 0; i < 10; i++) {
818 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
823 static void rtl8168_driver_stop(struct rtl8169_private *tp)
828 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
830 reg = rtl8168_get_ocp_reg(tp);
832 for (i = 0; i < 10; i++) {
834 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
839 static int r8168dp_check_dash(struct rtl8169_private *tp)
841 u16 reg = rtl8168_get_ocp_reg(tp);
843 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
846 static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
850 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
852 for (i = 20; i > 0; i--) {
854 * Check if the RTL8169 has completed writing to the specified
857 if (!(RTL_R32(PHYAR) & 0x80000000))
862 * According to hardware specs a 20us delay is required after write
863 * complete indication, but before sending next command.
868 static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
872 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
874 for (i = 20; i > 0; i--) {
876 * Check if the RTL8169 has completed retrieving data from
877 * the specified MII register.
879 if (RTL_R32(PHYAR) & 0x80000000) {
880 value = RTL_R32(PHYAR) & 0xffff;
886 * According to hardware specs a 20us delay is required after read
887 * complete indication, but before sending next command.
894 static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
898 RTL_W32(OCPDR, data |
899 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
900 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
901 RTL_W32(EPHY_RXER_NUM, 0);
903 for (i = 0; i < 100; i++) {
905 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
910 static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
912 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
913 (value & OCPDR_DATA_MASK));
916 static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
920 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
923 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
924 RTL_W32(EPHY_RXER_NUM, 0);
926 for (i = 0; i < 100; i++) {
928 if (RTL_R32(OCPAR) & OCPAR_FLAG)
932 return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
935 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
937 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
939 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
942 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
944 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
947 static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
949 r8168dp_2_mdio_start(ioaddr);
951 r8169_mdio_write(ioaddr, reg_addr, value);
953 r8168dp_2_mdio_stop(ioaddr);
956 static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
960 r8168dp_2_mdio_start(ioaddr);
962 value = r8169_mdio_read(ioaddr, reg_addr);
964 r8168dp_2_mdio_stop(ioaddr);
969 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
971 tp->mdio_ops.write(tp->mmio_addr, location, val);
974 static int rtl_readphy(struct rtl8169_private *tp, int location)
976 return tp->mdio_ops.read(tp->mmio_addr, location);
979 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
981 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
984 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
988 val = rtl_readphy(tp, reg_addr);
989 rtl_writephy(tp, reg_addr, (val | p) & ~m);
992 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
995 struct rtl8169_private *tp = netdev_priv(dev);
997 rtl_writephy(tp, location, val);
1000 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1002 struct rtl8169_private *tp = netdev_priv(dev);
1004 return rtl_readphy(tp, location);
1007 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
1011 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1012 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1014 for (i = 0; i < 100; i++) {
1015 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
1021 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
1026 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1028 for (i = 0; i < 100; i++) {
1029 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
1030 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
1039 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
1043 RTL_W32(CSIDR, value);
1044 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
1045 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1047 for (i = 0; i < 100; i++) {
1048 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
1054 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
1059 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
1060 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1062 for (i = 0; i < 100; i++) {
1063 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
1064 value = RTL_R32(CSIDR);
1073 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
1078 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1080 for (i = 0; i < 300; i++) {
1081 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
1082 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
1091 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1093 void __iomem *ioaddr = tp->mmio_addr;
1095 RTL_W16(IntrMask, 0x0000);
1096 RTL_W16(IntrStatus, tp->intr_event);
1100 static void rtl8169_asic_down(struct rtl8169_private *tp)
1102 void __iomem *ioaddr = tp->mmio_addr;
1104 RTL_W8(ChipCmd, 0x00);
1105 rtl8169_irq_mask_and_ack(tp);
1109 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1111 void __iomem *ioaddr = tp->mmio_addr;
1113 return RTL_R32(TBICSR) & TBIReset;
1116 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1118 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1121 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1123 return RTL_R32(TBICSR) & TBILinkOk;
1126 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1128 return RTL_R8(PHYstatus) & LinkStatus;
1131 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1133 void __iomem *ioaddr = tp->mmio_addr;
1135 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1138 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1142 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1143 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1146 static void __rtl8169_check_link_status(struct net_device *dev,
1147 struct rtl8169_private *tp,
1148 void __iomem *ioaddr, bool pm)
1150 unsigned long flags;
1152 spin_lock_irqsave(&tp->lock, flags);
1153 if (tp->link_ok(ioaddr)) {
1154 /* This is to cancel a scheduled suspend if there's one. */
1156 pm_request_resume(&tp->pci_dev->dev);
1157 netif_carrier_on(dev);
1158 if (net_ratelimit())
1159 netif_info(tp, ifup, dev, "link up\n");
1161 netif_carrier_off(dev);
1162 netif_info(tp, ifdown, dev, "link down\n");
1164 pm_schedule_suspend(&tp->pci_dev->dev, 5000);
1166 spin_unlock_irqrestore(&tp->lock, flags);
1169 static void rtl8169_check_link_status(struct net_device *dev,
1170 struct rtl8169_private *tp,
1171 void __iomem *ioaddr)
1173 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1176 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1178 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1180 void __iomem *ioaddr = tp->mmio_addr;
1184 options = RTL_R8(Config1);
1185 if (!(options & PMEnable))
1188 options = RTL_R8(Config3);
1189 if (options & LinkUp)
1190 wolopts |= WAKE_PHY;
1191 if (options & MagicPacket)
1192 wolopts |= WAKE_MAGIC;
1194 options = RTL_R8(Config5);
1196 wolopts |= WAKE_UCAST;
1198 wolopts |= WAKE_BCAST;
1200 wolopts |= WAKE_MCAST;
1205 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1207 struct rtl8169_private *tp = netdev_priv(dev);
1209 spin_lock_irq(&tp->lock);
1211 wol->supported = WAKE_ANY;
1212 wol->wolopts = __rtl8169_get_wol(tp);
1214 spin_unlock_irq(&tp->lock);
1217 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1219 void __iomem *ioaddr = tp->mmio_addr;
1221 static const struct {
1226 { WAKE_ANY, Config1, PMEnable },
1227 { WAKE_PHY, Config3, LinkUp },
1228 { WAKE_MAGIC, Config3, MagicPacket },
1229 { WAKE_UCAST, Config5, UWF },
1230 { WAKE_BCAST, Config5, BWF },
1231 { WAKE_MCAST, Config5, MWF },
1232 { WAKE_ANY, Config5, LanWake }
1235 RTL_W8(Cfg9346, Cfg9346_Unlock);
1237 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1238 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1239 if (wolopts & cfg[i].opt)
1240 options |= cfg[i].mask;
1241 RTL_W8(cfg[i].reg, options);
1244 RTL_W8(Cfg9346, Cfg9346_Lock);
1247 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1249 struct rtl8169_private *tp = netdev_priv(dev);
1251 spin_lock_irq(&tp->lock);
1254 tp->features |= RTL_FEATURE_WOL;
1256 tp->features &= ~RTL_FEATURE_WOL;
1257 __rtl8169_set_wol(tp, wol->wolopts);
1258 spin_unlock_irq(&tp->lock);
1260 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1265 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1267 return rtl_chip_infos[tp->mac_version].fw_name;
1270 static void rtl8169_get_drvinfo(struct net_device *dev,
1271 struct ethtool_drvinfo *info)
1273 struct rtl8169_private *tp = netdev_priv(dev);
1275 strcpy(info->driver, MODULENAME);
1276 strcpy(info->version, RTL8169_VERSION);
1277 strcpy(info->bus_info, pci_name(tp->pci_dev));
1278 strncpy(info->fw_version, IS_ERR_OR_NULL(tp->fw) ? "N/A" :
1279 rtl_lookup_firmware_name(tp), sizeof(info->fw_version) - 1);
1282 static int rtl8169_get_regs_len(struct net_device *dev)
1284 return R8169_REGS_SIZE;
1287 static int rtl8169_set_speed_tbi(struct net_device *dev,
1288 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1290 struct rtl8169_private *tp = netdev_priv(dev);
1291 void __iomem *ioaddr = tp->mmio_addr;
1295 reg = RTL_R32(TBICSR);
1296 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1297 (duplex == DUPLEX_FULL)) {
1298 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1299 } else if (autoneg == AUTONEG_ENABLE)
1300 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1302 netif_warn(tp, link, dev,
1303 "incorrect speed setting refused in TBI mode\n");
1310 static int rtl8169_set_speed_xmii(struct net_device *dev,
1311 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1313 struct rtl8169_private *tp = netdev_priv(dev);
1314 int giga_ctrl, bmcr;
1317 rtl_writephy(tp, 0x1f, 0x0000);
1319 if (autoneg == AUTONEG_ENABLE) {
1322 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1323 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1324 ADVERTISE_100HALF | ADVERTISE_100FULL);
1326 if (adv & ADVERTISED_10baseT_Half)
1327 auto_nego |= ADVERTISE_10HALF;
1328 if (adv & ADVERTISED_10baseT_Full)
1329 auto_nego |= ADVERTISE_10FULL;
1330 if (adv & ADVERTISED_100baseT_Half)
1331 auto_nego |= ADVERTISE_100HALF;
1332 if (adv & ADVERTISED_100baseT_Full)
1333 auto_nego |= ADVERTISE_100FULL;
1335 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1337 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1338 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1340 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1341 if (tp->mii.supports_gmii) {
1342 if (adv & ADVERTISED_1000baseT_Half)
1343 giga_ctrl |= ADVERTISE_1000HALF;
1344 if (adv & ADVERTISED_1000baseT_Full)
1345 giga_ctrl |= ADVERTISE_1000FULL;
1346 } else if (adv & (ADVERTISED_1000baseT_Half |
1347 ADVERTISED_1000baseT_Full)) {
1348 netif_info(tp, link, dev,
1349 "PHY does not support 1000Mbps\n");
1353 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1355 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1356 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1360 if (speed == SPEED_10)
1362 else if (speed == SPEED_100)
1363 bmcr = BMCR_SPEED100;
1367 if (duplex == DUPLEX_FULL)
1368 bmcr |= BMCR_FULLDPLX;
1371 rtl_writephy(tp, MII_BMCR, bmcr);
1373 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1374 tp->mac_version == RTL_GIGA_MAC_VER_03) {
1375 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1376 rtl_writephy(tp, 0x17, 0x2138);
1377 rtl_writephy(tp, 0x0e, 0x0260);
1379 rtl_writephy(tp, 0x17, 0x2108);
1380 rtl_writephy(tp, 0x0e, 0x0000);
1389 static int rtl8169_set_speed(struct net_device *dev,
1390 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1392 struct rtl8169_private *tp = netdev_priv(dev);
1395 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1399 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1400 (advertising & ADVERTISED_1000baseT_Full)) {
1401 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1407 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1409 struct rtl8169_private *tp = netdev_priv(dev);
1410 unsigned long flags;
1413 del_timer_sync(&tp->timer);
1415 spin_lock_irqsave(&tp->lock, flags);
1416 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
1417 cmd->duplex, cmd->advertising);
1418 spin_unlock_irqrestore(&tp->lock, flags);
1423 static u32 rtl8169_fix_features(struct net_device *dev, u32 features)
1425 struct rtl8169_private *tp = netdev_priv(dev);
1427 if (dev->mtu > TD_MSS_MAX)
1428 features &= ~NETIF_F_ALL_TSO;
1430 if (dev->mtu > JUMBO_1K &&
1431 !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1432 features &= ~NETIF_F_IP_CSUM;
1437 static int rtl8169_set_features(struct net_device *dev, u32 features)
1439 struct rtl8169_private *tp = netdev_priv(dev);
1440 void __iomem *ioaddr = tp->mmio_addr;
1441 unsigned long flags;
1443 spin_lock_irqsave(&tp->lock, flags);
1445 if (features & NETIF_F_RXCSUM)
1446 tp->cp_cmd |= RxChkSum;
1448 tp->cp_cmd &= ~RxChkSum;
1450 if (dev->features & NETIF_F_HW_VLAN_RX)
1451 tp->cp_cmd |= RxVlan;
1453 tp->cp_cmd &= ~RxVlan;
1455 RTL_W16(CPlusCmd, tp->cp_cmd);
1458 spin_unlock_irqrestore(&tp->lock, flags);
1463 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1464 struct sk_buff *skb)
1466 return (vlan_tx_tag_present(skb)) ?
1467 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1470 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1472 u32 opts2 = le32_to_cpu(desc->opts2);
1474 if (opts2 & RxVlanTag)
1475 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
1480 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1482 struct rtl8169_private *tp = netdev_priv(dev);
1483 void __iomem *ioaddr = tp->mmio_addr;
1487 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1488 cmd->port = PORT_FIBRE;
1489 cmd->transceiver = XCVR_INTERNAL;
1491 status = RTL_R32(TBICSR);
1492 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1493 cmd->autoneg = !!(status & TBINwEnable);
1495 ethtool_cmd_speed_set(cmd, SPEED_1000);
1496 cmd->duplex = DUPLEX_FULL; /* Always set */
1501 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1503 struct rtl8169_private *tp = netdev_priv(dev);
1505 return mii_ethtool_gset(&tp->mii, cmd);
1508 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1510 struct rtl8169_private *tp = netdev_priv(dev);
1511 unsigned long flags;
1514 spin_lock_irqsave(&tp->lock, flags);
1516 rc = tp->get_settings(dev, cmd);
1518 spin_unlock_irqrestore(&tp->lock, flags);
1522 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1525 struct rtl8169_private *tp = netdev_priv(dev);
1526 unsigned long flags;
1528 if (regs->len > R8169_REGS_SIZE)
1529 regs->len = R8169_REGS_SIZE;
1531 spin_lock_irqsave(&tp->lock, flags);
1532 memcpy_fromio(p, tp->mmio_addr, regs->len);
1533 spin_unlock_irqrestore(&tp->lock, flags);
1536 static u32 rtl8169_get_msglevel(struct net_device *dev)
1538 struct rtl8169_private *tp = netdev_priv(dev);
1540 return tp->msg_enable;
1543 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1545 struct rtl8169_private *tp = netdev_priv(dev);
1547 tp->msg_enable = value;
1550 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1557 "tx_single_collisions",
1558 "tx_multi_collisions",
1566 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1570 return ARRAY_SIZE(rtl8169_gstrings);
1576 static void rtl8169_update_counters(struct net_device *dev)
1578 struct rtl8169_private *tp = netdev_priv(dev);
1579 void __iomem *ioaddr = tp->mmio_addr;
1580 struct device *d = &tp->pci_dev->dev;
1581 struct rtl8169_counters *counters;
1587 * Some chips are unable to dump tally counters when the receiver
1590 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1593 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1597 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1598 cmd = (u64)paddr & DMA_BIT_MASK(32);
1599 RTL_W32(CounterAddrLow, cmd);
1600 RTL_W32(CounterAddrLow, cmd | CounterDump);
1603 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1604 memcpy(&tp->counters, counters, sizeof(*counters));
1610 RTL_W32(CounterAddrLow, 0);
1611 RTL_W32(CounterAddrHigh, 0);
1613 dma_free_coherent(d, sizeof(*counters), counters, paddr);
1616 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1617 struct ethtool_stats *stats, u64 *data)
1619 struct rtl8169_private *tp = netdev_priv(dev);
1623 rtl8169_update_counters(dev);
1625 data[0] = le64_to_cpu(tp->counters.tx_packets);
1626 data[1] = le64_to_cpu(tp->counters.rx_packets);
1627 data[2] = le64_to_cpu(tp->counters.tx_errors);
1628 data[3] = le32_to_cpu(tp->counters.rx_errors);
1629 data[4] = le16_to_cpu(tp->counters.rx_missed);
1630 data[5] = le16_to_cpu(tp->counters.align_errors);
1631 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1632 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1633 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1634 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1635 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1636 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1637 data[12] = le16_to_cpu(tp->counters.tx_underun);
1640 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1644 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1649 static const struct ethtool_ops rtl8169_ethtool_ops = {
1650 .get_drvinfo = rtl8169_get_drvinfo,
1651 .get_regs_len = rtl8169_get_regs_len,
1652 .get_link = ethtool_op_get_link,
1653 .get_settings = rtl8169_get_settings,
1654 .set_settings = rtl8169_set_settings,
1655 .get_msglevel = rtl8169_get_msglevel,
1656 .set_msglevel = rtl8169_set_msglevel,
1657 .get_regs = rtl8169_get_regs,
1658 .get_wol = rtl8169_get_wol,
1659 .set_wol = rtl8169_set_wol,
1660 .get_strings = rtl8169_get_strings,
1661 .get_sset_count = rtl8169_get_sset_count,
1662 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1665 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1666 struct net_device *dev, u8 default_version)
1668 void __iomem *ioaddr = tp->mmio_addr;
1670 * The driver currently handles the 8168Bf and the 8168Be identically
1671 * but they can be identified more specifically through the test below
1674 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1676 * Same thing for the 8101Eb and the 8101Ec:
1678 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1680 static const struct rtl_mac_info {
1686 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
1687 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
1688 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
1691 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
1692 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
1693 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
1695 /* 8168DP family. */
1696 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
1697 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
1698 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
1701 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
1702 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
1703 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
1704 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
1705 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1706 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
1707 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
1708 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
1709 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
1712 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1713 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1714 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1715 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1718 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
1719 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
1720 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
1721 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
1722 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1723 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1724 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1725 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1726 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1727 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
1728 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
1729 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
1730 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
1731 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1732 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
1733 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1734 /* FIXME: where did these entries come from ? -- FR */
1735 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1736 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1739 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1740 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1741 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1742 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1743 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1744 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1747 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
1749 const struct rtl_mac_info *p = mac_info;
1752 reg = RTL_R32(TxConfig);
1753 while ((reg & p->mask) != p->val)
1755 tp->mac_version = p->mac_version;
1757 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
1758 netif_notice(tp, probe, dev,
1759 "unknown MAC, using family default\n");
1760 tp->mac_version = default_version;
1764 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1766 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1774 static void rtl_writephy_batch(struct rtl8169_private *tp,
1775 const struct phy_reg *regs, int len)
1778 rtl_writephy(tp, regs->reg, regs->val);
1783 #define PHY_READ 0x00000000
1784 #define PHY_DATA_OR 0x10000000
1785 #define PHY_DATA_AND 0x20000000
1786 #define PHY_BJMPN 0x30000000
1787 #define PHY_READ_EFUSE 0x40000000
1788 #define PHY_READ_MAC_BYTE 0x50000000
1789 #define PHY_WRITE_MAC_BYTE 0x60000000
1790 #define PHY_CLEAR_READCOUNT 0x70000000
1791 #define PHY_WRITE 0x80000000
1792 #define PHY_READCOUNT_EQ_SKIP 0x90000000
1793 #define PHY_COMP_EQ_SKIPN 0xa0000000
1794 #define PHY_COMP_NEQ_SKIPN 0xb0000000
1795 #define PHY_WRITE_PREVIOUS 0xc0000000
1796 #define PHY_SKIPN 0xd0000000
1797 #define PHY_DELAY_MS 0xe0000000
1798 #define PHY_WRITE_ERI_WORD 0xf0000000
1801 rtl_phy_write_fw(struct rtl8169_private *tp, const struct firmware *fw)
1803 __le32 *phytable = (__le32 *)fw->data;
1804 struct net_device *dev = tp->dev;
1805 size_t index, fw_size = fw->size / sizeof(*phytable);
1808 if (fw->size % sizeof(*phytable)) {
1809 netif_err(tp, probe, dev, "odd sized firmware %zd\n", fw->size);
1813 for (index = 0; index < fw_size; index++) {
1814 u32 action = le32_to_cpu(phytable[index]);
1815 u32 regno = (action & 0x0fff0000) >> 16;
1817 switch(action & 0xf0000000) {
1821 case PHY_READ_EFUSE:
1822 case PHY_CLEAR_READCOUNT:
1824 case PHY_WRITE_PREVIOUS:
1829 if (regno > index) {
1830 netif_err(tp, probe, tp->dev,
1831 "Out of range of firmware\n");
1835 case PHY_READCOUNT_EQ_SKIP:
1836 if (index + 2 >= fw_size) {
1837 netif_err(tp, probe, tp->dev,
1838 "Out of range of firmware\n");
1842 case PHY_COMP_EQ_SKIPN:
1843 case PHY_COMP_NEQ_SKIPN:
1845 if (index + 1 + regno >= fw_size) {
1846 netif_err(tp, probe, tp->dev,
1847 "Out of range of firmware\n");
1852 case PHY_READ_MAC_BYTE:
1853 case PHY_WRITE_MAC_BYTE:
1854 case PHY_WRITE_ERI_WORD:
1856 netif_err(tp, probe, tp->dev,
1857 "Invalid action 0x%08x\n", action);
1865 for (index = 0; index < fw_size; ) {
1866 u32 action = le32_to_cpu(phytable[index]);
1867 u32 data = action & 0x0000ffff;
1868 u32 regno = (action & 0x0fff0000) >> 16;
1873 switch(action & 0xf0000000) {
1875 predata = rtl_readphy(tp, regno);
1890 case PHY_READ_EFUSE:
1891 predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
1894 case PHY_CLEAR_READCOUNT:
1899 rtl_writephy(tp, regno, data);
1902 case PHY_READCOUNT_EQ_SKIP:
1903 index += (count == data) ? 2 : 1;
1905 case PHY_COMP_EQ_SKIPN:
1906 if (predata == data)
1910 case PHY_COMP_NEQ_SKIPN:
1911 if (predata != data)
1915 case PHY_WRITE_PREVIOUS:
1916 rtl_writephy(tp, regno, predata);
1927 case PHY_READ_MAC_BYTE:
1928 case PHY_WRITE_MAC_BYTE:
1929 case PHY_WRITE_ERI_WORD:
1936 static void rtl_release_firmware(struct rtl8169_private *tp)
1938 if (!IS_ERR_OR_NULL(tp->fw))
1939 release_firmware(tp->fw);
1940 tp->fw = RTL_FIRMWARE_UNKNOWN;
1943 static void rtl_apply_firmware(struct rtl8169_private *tp)
1945 const struct firmware *fw = tp->fw;
1947 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
1948 if (!IS_ERR_OR_NULL(fw))
1949 rtl_phy_write_fw(tp, fw);
1952 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
1954 if (rtl_readphy(tp, reg) != val)
1955 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
1957 rtl_apply_firmware(tp);
1960 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1962 static const struct phy_reg phy_reg_init[] = {
2024 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2027 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2029 static const struct phy_reg phy_reg_init[] = {
2035 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2038 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2040 struct pci_dev *pdev = tp->pci_dev;
2041 u16 vendor_id, device_id;
2043 pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
2044 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
2046 if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
2049 rtl_writephy(tp, 0x1f, 0x0001);
2050 rtl_writephy(tp, 0x10, 0xf01b);
2051 rtl_writephy(tp, 0x1f, 0x0000);
2054 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2056 static const struct phy_reg phy_reg_init[] = {
2096 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2098 rtl8169scd_hw_phy_config_quirk(tp);
2101 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2103 static const struct phy_reg phy_reg_init[] = {
2151 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2154 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2156 static const struct phy_reg phy_reg_init[] = {
2161 rtl_writephy(tp, 0x1f, 0x0001);
2162 rtl_patchphy(tp, 0x16, 1 << 0);
2164 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2167 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2169 static const struct phy_reg phy_reg_init[] = {
2175 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2178 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2180 static const struct phy_reg phy_reg_init[] = {
2188 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2191 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2193 static const struct phy_reg phy_reg_init[] = {
2199 rtl_writephy(tp, 0x1f, 0x0000);
2200 rtl_patchphy(tp, 0x14, 1 << 5);
2201 rtl_patchphy(tp, 0x0d, 1 << 5);
2203 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2206 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2208 static const struct phy_reg phy_reg_init[] = {
2228 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2230 rtl_patchphy(tp, 0x14, 1 << 5);
2231 rtl_patchphy(tp, 0x0d, 1 << 5);
2232 rtl_writephy(tp, 0x1f, 0x0000);
2235 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2237 static const struct phy_reg phy_reg_init[] = {
2255 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2257 rtl_patchphy(tp, 0x16, 1 << 0);
2258 rtl_patchphy(tp, 0x14, 1 << 5);
2259 rtl_patchphy(tp, 0x0d, 1 << 5);
2260 rtl_writephy(tp, 0x1f, 0x0000);
2263 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2265 static const struct phy_reg phy_reg_init[] = {
2277 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2279 rtl_patchphy(tp, 0x16, 1 << 0);
2280 rtl_patchphy(tp, 0x14, 1 << 5);
2281 rtl_patchphy(tp, 0x0d, 1 << 5);
2282 rtl_writephy(tp, 0x1f, 0x0000);
2285 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2287 rtl8168c_3_hw_phy_config(tp);
2290 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2292 static const struct phy_reg phy_reg_init_0[] = {
2293 /* Channel Estimation */
2314 * Enhance line driver power
2323 * Can not link to 1Gbps with bad cable
2324 * Decrease SNR threshold form 21.07dB to 19.04dB
2332 void __iomem *ioaddr = tp->mmio_addr;
2334 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2338 * Fine Tune Switching regulator parameter
2340 rtl_writephy(tp, 0x1f, 0x0002);
2341 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2342 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2344 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2345 static const struct phy_reg phy_reg_init[] = {
2355 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2357 val = rtl_readphy(tp, 0x0d);
2359 if ((val & 0x00ff) != 0x006c) {
2360 static const u32 set[] = {
2361 0x0065, 0x0066, 0x0067, 0x0068,
2362 0x0069, 0x006a, 0x006b, 0x006c
2366 rtl_writephy(tp, 0x1f, 0x0002);
2369 for (i = 0; i < ARRAY_SIZE(set); i++)
2370 rtl_writephy(tp, 0x0d, val | set[i]);
2373 static const struct phy_reg phy_reg_init[] = {
2381 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2384 /* RSET couple improve */
2385 rtl_writephy(tp, 0x1f, 0x0002);
2386 rtl_patchphy(tp, 0x0d, 0x0300);
2387 rtl_patchphy(tp, 0x0f, 0x0010);
2389 /* Fine tune PLL performance */
2390 rtl_writephy(tp, 0x1f, 0x0002);
2391 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2392 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2394 rtl_writephy(tp, 0x1f, 0x0005);
2395 rtl_writephy(tp, 0x05, 0x001b);
2397 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2399 rtl_writephy(tp, 0x1f, 0x0000);
2402 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2404 static const struct phy_reg phy_reg_init_0[] = {
2405 /* Channel Estimation */
2426 * Enhance line driver power
2435 * Can not link to 1Gbps with bad cable
2436 * Decrease SNR threshold form 21.07dB to 19.04dB
2444 void __iomem *ioaddr = tp->mmio_addr;
2446 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2448 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2449 static const struct phy_reg phy_reg_init[] = {
2460 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2462 val = rtl_readphy(tp, 0x0d);
2463 if ((val & 0x00ff) != 0x006c) {
2464 static const u32 set[] = {
2465 0x0065, 0x0066, 0x0067, 0x0068,
2466 0x0069, 0x006a, 0x006b, 0x006c
2470 rtl_writephy(tp, 0x1f, 0x0002);
2473 for (i = 0; i < ARRAY_SIZE(set); i++)
2474 rtl_writephy(tp, 0x0d, val | set[i]);
2477 static const struct phy_reg phy_reg_init[] = {
2485 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2488 /* Fine tune PLL performance */
2489 rtl_writephy(tp, 0x1f, 0x0002);
2490 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2491 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2493 /* Switching regulator Slew rate */
2494 rtl_writephy(tp, 0x1f, 0x0002);
2495 rtl_patchphy(tp, 0x0f, 0x0017);
2497 rtl_writephy(tp, 0x1f, 0x0005);
2498 rtl_writephy(tp, 0x05, 0x001b);
2500 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2502 rtl_writephy(tp, 0x1f, 0x0000);
2505 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2507 static const struct phy_reg phy_reg_init[] = {
2563 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2566 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2568 static const struct phy_reg phy_reg_init[] = {
2578 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2579 rtl_patchphy(tp, 0x0d, 1 << 5);
2582 static void rtl8168e_hw_phy_config(struct rtl8169_private *tp)
2584 static const struct phy_reg phy_reg_init[] = {
2585 /* Enable Delay cap */
2591 /* Channel estimation fine tune */
2600 /* Update PFM & 10M TX idle timer */
2612 rtl_apply_firmware(tp);
2614 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2616 /* DCO enable for 10M IDLE Power */
2617 rtl_writephy(tp, 0x1f, 0x0007);
2618 rtl_writephy(tp, 0x1e, 0x0023);
2619 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2620 rtl_writephy(tp, 0x1f, 0x0000);
2622 /* For impedance matching */
2623 rtl_writephy(tp, 0x1f, 0x0002);
2624 rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
2625 rtl_writephy(tp, 0x1f, 0x0000);
2627 /* PHY auto speed down */
2628 rtl_writephy(tp, 0x1f, 0x0007);
2629 rtl_writephy(tp, 0x1e, 0x002d);
2630 rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2631 rtl_writephy(tp, 0x1f, 0x0000);
2632 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2634 rtl_writephy(tp, 0x1f, 0x0005);
2635 rtl_writephy(tp, 0x05, 0x8b86);
2636 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2637 rtl_writephy(tp, 0x1f, 0x0000);
2639 rtl_writephy(tp, 0x1f, 0x0005);
2640 rtl_writephy(tp, 0x05, 0x8b85);
2641 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2642 rtl_writephy(tp, 0x1f, 0x0007);
2643 rtl_writephy(tp, 0x1e, 0x0020);
2644 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2645 rtl_writephy(tp, 0x1f, 0x0006);
2646 rtl_writephy(tp, 0x00, 0x5a00);
2647 rtl_writephy(tp, 0x1f, 0x0000);
2648 rtl_writephy(tp, 0x0d, 0x0007);
2649 rtl_writephy(tp, 0x0e, 0x003c);
2650 rtl_writephy(tp, 0x0d, 0x4007);
2651 rtl_writephy(tp, 0x0e, 0x0000);
2652 rtl_writephy(tp, 0x0d, 0x0000);
2655 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2657 static const struct phy_reg phy_reg_init[] = {
2664 rtl_writephy(tp, 0x1f, 0x0000);
2665 rtl_patchphy(tp, 0x11, 1 << 12);
2666 rtl_patchphy(tp, 0x19, 1 << 13);
2667 rtl_patchphy(tp, 0x10, 1 << 15);
2669 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2672 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
2674 static const struct phy_reg phy_reg_init[] = {
2688 /* Disable ALDPS before ram code */
2689 rtl_writephy(tp, 0x1f, 0x0000);
2690 rtl_writephy(tp, 0x18, 0x0310);
2693 rtl_apply_firmware(tp);
2695 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2698 static void rtl_hw_phy_config(struct net_device *dev)
2700 struct rtl8169_private *tp = netdev_priv(dev);
2702 rtl8169_print_mac_version(tp);
2704 switch (tp->mac_version) {
2705 case RTL_GIGA_MAC_VER_01:
2707 case RTL_GIGA_MAC_VER_02:
2708 case RTL_GIGA_MAC_VER_03:
2709 rtl8169s_hw_phy_config(tp);
2711 case RTL_GIGA_MAC_VER_04:
2712 rtl8169sb_hw_phy_config(tp);
2714 case RTL_GIGA_MAC_VER_05:
2715 rtl8169scd_hw_phy_config(tp);
2717 case RTL_GIGA_MAC_VER_06:
2718 rtl8169sce_hw_phy_config(tp);
2720 case RTL_GIGA_MAC_VER_07:
2721 case RTL_GIGA_MAC_VER_08:
2722 case RTL_GIGA_MAC_VER_09:
2723 rtl8102e_hw_phy_config(tp);
2725 case RTL_GIGA_MAC_VER_11:
2726 rtl8168bb_hw_phy_config(tp);
2728 case RTL_GIGA_MAC_VER_12:
2729 rtl8168bef_hw_phy_config(tp);
2731 case RTL_GIGA_MAC_VER_17:
2732 rtl8168bef_hw_phy_config(tp);
2734 case RTL_GIGA_MAC_VER_18:
2735 rtl8168cp_1_hw_phy_config(tp);
2737 case RTL_GIGA_MAC_VER_19:
2738 rtl8168c_1_hw_phy_config(tp);
2740 case RTL_GIGA_MAC_VER_20:
2741 rtl8168c_2_hw_phy_config(tp);
2743 case RTL_GIGA_MAC_VER_21:
2744 rtl8168c_3_hw_phy_config(tp);
2746 case RTL_GIGA_MAC_VER_22:
2747 rtl8168c_4_hw_phy_config(tp);
2749 case RTL_GIGA_MAC_VER_23:
2750 case RTL_GIGA_MAC_VER_24:
2751 rtl8168cp_2_hw_phy_config(tp);
2753 case RTL_GIGA_MAC_VER_25:
2754 rtl8168d_1_hw_phy_config(tp);
2756 case RTL_GIGA_MAC_VER_26:
2757 rtl8168d_2_hw_phy_config(tp);
2759 case RTL_GIGA_MAC_VER_27:
2760 rtl8168d_3_hw_phy_config(tp);
2762 case RTL_GIGA_MAC_VER_28:
2763 rtl8168d_4_hw_phy_config(tp);
2765 case RTL_GIGA_MAC_VER_29:
2766 case RTL_GIGA_MAC_VER_30:
2767 rtl8105e_hw_phy_config(tp);
2769 case RTL_GIGA_MAC_VER_31:
2772 case RTL_GIGA_MAC_VER_32:
2773 case RTL_GIGA_MAC_VER_33:
2774 rtl8168e_hw_phy_config(tp);
2782 static void rtl8169_phy_timer(unsigned long __opaque)
2784 struct net_device *dev = (struct net_device *)__opaque;
2785 struct rtl8169_private *tp = netdev_priv(dev);
2786 struct timer_list *timer = &tp->timer;
2787 void __iomem *ioaddr = tp->mmio_addr;
2788 unsigned long timeout = RTL8169_PHY_TIMEOUT;
2790 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
2792 spin_lock_irq(&tp->lock);
2794 if (tp->phy_reset_pending(tp)) {
2796 * A busy loop could burn quite a few cycles on nowadays CPU.
2797 * Let's delay the execution of the timer for a few ticks.
2803 if (tp->link_ok(ioaddr))
2806 netif_warn(tp, link, dev, "PHY reset until link up\n");
2808 tp->phy_reset_enable(tp);
2811 mod_timer(timer, jiffies + timeout);
2813 spin_unlock_irq(&tp->lock);
2816 #ifdef CONFIG_NET_POLL_CONTROLLER
2818 * Polling 'interrupt' - used by things like netconsole to send skbs
2819 * without having to re-enable interrupts. It's not called while
2820 * the interrupt routine is executing.
2822 static void rtl8169_netpoll(struct net_device *dev)
2824 struct rtl8169_private *tp = netdev_priv(dev);
2825 struct pci_dev *pdev = tp->pci_dev;
2827 disable_irq(pdev->irq);
2828 rtl8169_interrupt(pdev->irq, dev);
2829 enable_irq(pdev->irq);
2833 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
2834 void __iomem *ioaddr)
2837 pci_release_regions(pdev);
2838 pci_clear_mwi(pdev);
2839 pci_disable_device(pdev);
2843 static void rtl8169_phy_reset(struct net_device *dev,
2844 struct rtl8169_private *tp)
2848 tp->phy_reset_enable(tp);
2849 for (i = 0; i < 100; i++) {
2850 if (!tp->phy_reset_pending(tp))
2854 netif_err(tp, link, dev, "PHY reset failed\n");
2857 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
2859 void __iomem *ioaddr = tp->mmio_addr;
2861 rtl_hw_phy_config(dev);
2863 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2864 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2868 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2870 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
2871 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
2873 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
2874 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2876 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
2877 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
2880 rtl8169_phy_reset(dev, tp);
2882 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
2883 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
2884 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
2885 (tp->mii.supports_gmii ?
2886 ADVERTISED_1000baseT_Half |
2887 ADVERTISED_1000baseT_Full : 0));
2889 if (RTL_R8(PHYstatus) & TBI_Enable)
2890 netif_info(tp, link, dev, "TBI auto-negotiating\n");
2893 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2895 void __iomem *ioaddr = tp->mmio_addr;
2899 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
2900 high = addr[4] | (addr[5] << 8);
2902 spin_lock_irq(&tp->lock);
2904 RTL_W8(Cfg9346, Cfg9346_Unlock);
2906 RTL_W32(MAC4, high);
2912 RTL_W8(Cfg9346, Cfg9346_Lock);
2914 spin_unlock_irq(&tp->lock);
2917 static int rtl_set_mac_address(struct net_device *dev, void *p)
2919 struct rtl8169_private *tp = netdev_priv(dev);
2920 struct sockaddr *addr = p;
2922 if (!is_valid_ether_addr(addr->sa_data))
2923 return -EADDRNOTAVAIL;
2925 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2927 rtl_rar_set(tp, dev->dev_addr);
2932 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2934 struct rtl8169_private *tp = netdev_priv(dev);
2935 struct mii_ioctl_data *data = if_mii(ifr);
2937 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
2940 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
2941 struct mii_ioctl_data *data, int cmd)
2945 data->phy_id = 32; /* Internal PHY */
2949 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
2953 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
2959 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2964 static const struct rtl_cfg_info {
2965 void (*hw_start)(struct net_device *);
2966 unsigned int region;
2972 } rtl_cfg_infos [] = {
2974 .hw_start = rtl_hw_start_8169,
2977 .intr_event = SYSErr | LinkChg | RxOverflow |
2978 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2979 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2980 .features = RTL_FEATURE_GMII,
2981 .default_ver = RTL_GIGA_MAC_VER_01,
2984 .hw_start = rtl_hw_start_8168,
2987 .intr_event = SYSErr | LinkChg | RxOverflow |
2988 TxErr | TxOK | RxOK | RxErr,
2989 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
2990 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
2991 .default_ver = RTL_GIGA_MAC_VER_11,
2994 .hw_start = rtl_hw_start_8101,
2997 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
2998 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2999 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
3000 .features = RTL_FEATURE_MSI,
3001 .default_ver = RTL_GIGA_MAC_VER_13,
3005 /* Cfg9346_Unlock assumed. */
3006 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
3007 const struct rtl_cfg_info *cfg)
3012 cfg2 = RTL_R8(Config2) & ~MSIEnable;
3013 if (cfg->features & RTL_FEATURE_MSI) {
3014 if (pci_enable_msi(pdev)) {
3015 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
3018 msi = RTL_FEATURE_MSI;
3021 RTL_W8(Config2, cfg2);
3025 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3027 if (tp->features & RTL_FEATURE_MSI) {
3028 pci_disable_msi(pdev);
3029 tp->features &= ~RTL_FEATURE_MSI;
3033 static const struct net_device_ops rtl8169_netdev_ops = {
3034 .ndo_open = rtl8169_open,
3035 .ndo_stop = rtl8169_close,
3036 .ndo_get_stats = rtl8169_get_stats,
3037 .ndo_start_xmit = rtl8169_start_xmit,
3038 .ndo_tx_timeout = rtl8169_tx_timeout,
3039 .ndo_validate_addr = eth_validate_addr,
3040 .ndo_change_mtu = rtl8169_change_mtu,
3041 .ndo_fix_features = rtl8169_fix_features,
3042 .ndo_set_features = rtl8169_set_features,
3043 .ndo_set_mac_address = rtl_set_mac_address,
3044 .ndo_do_ioctl = rtl8169_ioctl,
3045 .ndo_set_multicast_list = rtl_set_rx_mode,
3046 #ifdef CONFIG_NET_POLL_CONTROLLER
3047 .ndo_poll_controller = rtl8169_netpoll,
3052 static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
3054 struct mdio_ops *ops = &tp->mdio_ops;
3056 switch (tp->mac_version) {
3057 case RTL_GIGA_MAC_VER_27:
3058 ops->write = r8168dp_1_mdio_write;
3059 ops->read = r8168dp_1_mdio_read;
3061 case RTL_GIGA_MAC_VER_28:
3062 case RTL_GIGA_MAC_VER_31:
3063 ops->write = r8168dp_2_mdio_write;
3064 ops->read = r8168dp_2_mdio_read;
3067 ops->write = r8169_mdio_write;
3068 ops->read = r8169_mdio_read;
3073 static void r810x_phy_power_down(struct rtl8169_private *tp)
3075 rtl_writephy(tp, 0x1f, 0x0000);
3076 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3079 static void r810x_phy_power_up(struct rtl8169_private *tp)
3081 rtl_writephy(tp, 0x1f, 0x0000);
3082 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3085 static void r810x_pll_power_down(struct rtl8169_private *tp)
3087 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3088 rtl_writephy(tp, 0x1f, 0x0000);
3089 rtl_writephy(tp, MII_BMCR, 0x0000);
3093 r810x_phy_power_down(tp);
3096 static void r810x_pll_power_up(struct rtl8169_private *tp)
3098 r810x_phy_power_up(tp);
3101 static void r8168_phy_power_up(struct rtl8169_private *tp)
3103 rtl_writephy(tp, 0x1f, 0x0000);
3104 switch (tp->mac_version) {
3105 case RTL_GIGA_MAC_VER_11:
3106 case RTL_GIGA_MAC_VER_12:
3107 case RTL_GIGA_MAC_VER_17:
3108 case RTL_GIGA_MAC_VER_18:
3109 case RTL_GIGA_MAC_VER_19:
3110 case RTL_GIGA_MAC_VER_20:
3111 case RTL_GIGA_MAC_VER_21:
3112 case RTL_GIGA_MAC_VER_22:
3113 case RTL_GIGA_MAC_VER_23:
3114 case RTL_GIGA_MAC_VER_24:
3115 case RTL_GIGA_MAC_VER_25:
3116 case RTL_GIGA_MAC_VER_26:
3117 case RTL_GIGA_MAC_VER_27:
3118 case RTL_GIGA_MAC_VER_28:
3119 case RTL_GIGA_MAC_VER_31:
3120 rtl_writephy(tp, 0x0e, 0x0000);
3125 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3128 static void r8168_phy_power_down(struct rtl8169_private *tp)
3130 rtl_writephy(tp, 0x1f, 0x0000);
3131 switch (tp->mac_version) {
3132 case RTL_GIGA_MAC_VER_32:
3133 case RTL_GIGA_MAC_VER_33:
3134 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3137 case RTL_GIGA_MAC_VER_11:
3138 case RTL_GIGA_MAC_VER_12:
3139 case RTL_GIGA_MAC_VER_17:
3140 case RTL_GIGA_MAC_VER_18:
3141 case RTL_GIGA_MAC_VER_19:
3142 case RTL_GIGA_MAC_VER_20:
3143 case RTL_GIGA_MAC_VER_21:
3144 case RTL_GIGA_MAC_VER_22:
3145 case RTL_GIGA_MAC_VER_23:
3146 case RTL_GIGA_MAC_VER_24:
3147 case RTL_GIGA_MAC_VER_25:
3148 case RTL_GIGA_MAC_VER_26:
3149 case RTL_GIGA_MAC_VER_27:
3150 case RTL_GIGA_MAC_VER_28:
3151 case RTL_GIGA_MAC_VER_31:
3152 rtl_writephy(tp, 0x0e, 0x0200);
3154 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3159 static void r8168_pll_power_down(struct rtl8169_private *tp)
3161 void __iomem *ioaddr = tp->mmio_addr;
3163 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3164 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3165 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3166 r8168dp_check_dash(tp)) {
3170 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
3171 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
3172 (RTL_R16(CPlusCmd) & ASF)) {
3176 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3177 tp->mac_version == RTL_GIGA_MAC_VER_33)
3178 rtl_ephy_write(ioaddr, 0x19, 0xff64);
3180 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3181 rtl_writephy(tp, 0x1f, 0x0000);
3182 rtl_writephy(tp, MII_BMCR, 0x0000);
3184 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3185 tp->mac_version == RTL_GIGA_MAC_VER_33)
3186 RTL_W32(RxConfig, RTL_R32(RxConfig) | AcceptBroadcast |
3187 AcceptMulticast | AcceptMyPhys);
3191 r8168_phy_power_down(tp);
3193 switch (tp->mac_version) {
3194 case RTL_GIGA_MAC_VER_25:
3195 case RTL_GIGA_MAC_VER_26:
3196 case RTL_GIGA_MAC_VER_27:
3197 case RTL_GIGA_MAC_VER_28:
3198 case RTL_GIGA_MAC_VER_31:
3199 case RTL_GIGA_MAC_VER_32:
3200 case RTL_GIGA_MAC_VER_33:
3201 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3206 static void r8168_pll_power_up(struct rtl8169_private *tp)
3208 void __iomem *ioaddr = tp->mmio_addr;
3210 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3211 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3212 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3213 r8168dp_check_dash(tp)) {
3217 switch (tp->mac_version) {
3218 case RTL_GIGA_MAC_VER_25:
3219 case RTL_GIGA_MAC_VER_26:
3220 case RTL_GIGA_MAC_VER_27:
3221 case RTL_GIGA_MAC_VER_28:
3222 case RTL_GIGA_MAC_VER_31:
3223 case RTL_GIGA_MAC_VER_32:
3224 case RTL_GIGA_MAC_VER_33:
3225 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3229 r8168_phy_power_up(tp);
3232 static void rtl_generic_op(struct rtl8169_private *tp,
3233 void (*op)(struct rtl8169_private *))
3239 static void rtl_pll_power_down(struct rtl8169_private *tp)
3241 rtl_generic_op(tp, tp->pll_power_ops.down);
3244 static void rtl_pll_power_up(struct rtl8169_private *tp)
3246 rtl_generic_op(tp, tp->pll_power_ops.up);
3249 static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3251 struct pll_power_ops *ops = &tp->pll_power_ops;
3253 switch (tp->mac_version) {
3254 case RTL_GIGA_MAC_VER_07:
3255 case RTL_GIGA_MAC_VER_08:
3256 case RTL_GIGA_MAC_VER_09:
3257 case RTL_GIGA_MAC_VER_10:
3258 case RTL_GIGA_MAC_VER_16:
3259 case RTL_GIGA_MAC_VER_29:
3260 case RTL_GIGA_MAC_VER_30:
3261 ops->down = r810x_pll_power_down;
3262 ops->up = r810x_pll_power_up;
3265 case RTL_GIGA_MAC_VER_11:
3266 case RTL_GIGA_MAC_VER_12:
3267 case RTL_GIGA_MAC_VER_17:
3268 case RTL_GIGA_MAC_VER_18:
3269 case RTL_GIGA_MAC_VER_19:
3270 case RTL_GIGA_MAC_VER_20:
3271 case RTL_GIGA_MAC_VER_21:
3272 case RTL_GIGA_MAC_VER_22:
3273 case RTL_GIGA_MAC_VER_23:
3274 case RTL_GIGA_MAC_VER_24:
3275 case RTL_GIGA_MAC_VER_25:
3276 case RTL_GIGA_MAC_VER_26:
3277 case RTL_GIGA_MAC_VER_27:
3278 case RTL_GIGA_MAC_VER_28:
3279 case RTL_GIGA_MAC_VER_31:
3280 case RTL_GIGA_MAC_VER_32:
3281 case RTL_GIGA_MAC_VER_33:
3282 ops->down = r8168_pll_power_down;
3283 ops->up = r8168_pll_power_up;
3293 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
3295 rtl_generic_op(tp, tp->jumbo_ops.enable);
3298 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
3300 rtl_generic_op(tp, tp->jumbo_ops.disable);
3303 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
3305 void __iomem *ioaddr = tp->mmio_addr;
3307 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3308 RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
3309 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
3312 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
3314 void __iomem *ioaddr = tp->mmio_addr;
3316 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3317 RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
3318 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
3321 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
3323 void __iomem *ioaddr = tp->mmio_addr;
3325 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3328 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
3330 void __iomem *ioaddr = tp->mmio_addr;
3332 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3335 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
3337 void __iomem *ioaddr = tp->mmio_addr;
3338 struct pci_dev *pdev = tp->pci_dev;
3340 RTL_W8(MaxTxPacketSize, 0x3f);
3341 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3342 RTL_W8(Config4, RTL_R8(Config4) | 0x01);
3343 pci_write_config_byte(pdev, 0x79, 0x20);
3346 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
3348 void __iomem *ioaddr = tp->mmio_addr;
3349 struct pci_dev *pdev = tp->pci_dev;
3351 RTL_W8(MaxTxPacketSize, 0x0c);
3352 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3353 RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
3354 pci_write_config_byte(pdev, 0x79, 0x50);
3357 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
3359 rtl_tx_performance_tweak(tp->pci_dev,
3360 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3363 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
3365 rtl_tx_performance_tweak(tp->pci_dev,
3366 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3369 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
3371 void __iomem *ioaddr = tp->mmio_addr;
3373 r8168b_0_hw_jumbo_enable(tp);
3375 RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
3378 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
3380 void __iomem *ioaddr = tp->mmio_addr;
3382 r8168b_0_hw_jumbo_disable(tp);
3384 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
3387 static void __devinit rtl_init_jumbo_ops(struct rtl8169_private *tp)
3389 struct jumbo_ops *ops = &tp->jumbo_ops;
3391 switch (tp->mac_version) {
3392 case RTL_GIGA_MAC_VER_11:
3393 ops->disable = r8168b_0_hw_jumbo_disable;
3394 ops->enable = r8168b_0_hw_jumbo_enable;
3396 case RTL_GIGA_MAC_VER_12:
3397 case RTL_GIGA_MAC_VER_17:
3398 ops->disable = r8168b_1_hw_jumbo_disable;
3399 ops->enable = r8168b_1_hw_jumbo_enable;
3401 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
3402 case RTL_GIGA_MAC_VER_19:
3403 case RTL_GIGA_MAC_VER_20:
3404 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
3405 case RTL_GIGA_MAC_VER_22:
3406 case RTL_GIGA_MAC_VER_23:
3407 case RTL_GIGA_MAC_VER_24:
3408 case RTL_GIGA_MAC_VER_25:
3409 case RTL_GIGA_MAC_VER_26:
3410 ops->disable = r8168c_hw_jumbo_disable;
3411 ops->enable = r8168c_hw_jumbo_enable;
3413 case RTL_GIGA_MAC_VER_27:
3414 case RTL_GIGA_MAC_VER_28:
3415 ops->disable = r8168dp_hw_jumbo_disable;
3416 ops->enable = r8168dp_hw_jumbo_enable;
3418 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
3419 case RTL_GIGA_MAC_VER_32:
3420 case RTL_GIGA_MAC_VER_33:
3421 ops->disable = r8168e_hw_jumbo_disable;
3422 ops->enable = r8168e_hw_jumbo_enable;
3426 * No action needed for jumbo frames with 8169.
3427 * No jumbo for 810x at all.
3430 ops->disable = NULL;
3436 static void rtl_hw_reset(struct rtl8169_private *tp)
3438 void __iomem *ioaddr = tp->mmio_addr;
3441 /* Soft reset the chip. */
3442 RTL_W8(ChipCmd, CmdReset);
3444 /* Check that the chip has finished the reset. */
3445 for (i = 0; i < 100; i++) {
3446 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3448 msleep_interruptible(1);
3452 static int __devinit
3453 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3455 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
3456 const unsigned int region = cfg->region;
3457 struct rtl8169_private *tp;
3458 struct mii_if_info *mii;
3459 struct net_device *dev;
3460 void __iomem *ioaddr;
3464 if (netif_msg_drv(&debug)) {
3465 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
3466 MODULENAME, RTL8169_VERSION);
3469 dev = alloc_etherdev(sizeof (*tp));
3471 if (netif_msg_drv(&debug))
3472 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
3477 SET_NETDEV_DEV(dev, &pdev->dev);
3478 dev->netdev_ops = &rtl8169_netdev_ops;
3479 tp = netdev_priv(dev);
3482 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
3486 mii->mdio_read = rtl_mdio_read;
3487 mii->mdio_write = rtl_mdio_write;
3488 mii->phy_id_mask = 0x1f;
3489 mii->reg_num_mask = 0x1f;
3490 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3492 /* disable ASPM completely as that cause random device stop working
3493 * problems as well as full system hangs for some PCIe devices users */
3494 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3495 PCIE_LINK_STATE_CLKPM);
3497 /* enable device (incl. PCI PM wakeup and hotplug setup) */
3498 rc = pci_enable_device(pdev);
3500 netif_err(tp, probe, dev, "enable failure\n");
3501 goto err_out_free_dev_1;
3504 if (pci_set_mwi(pdev) < 0)
3505 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
3507 /* make sure PCI base addr 1 is MMIO */
3508 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
3509 netif_err(tp, probe, dev,
3510 "region #%d not an MMIO resource, aborting\n",
3516 /* check for weird/broken PCI region reporting */
3517 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
3518 netif_err(tp, probe, dev,
3519 "Invalid PCI region size(s), aborting\n");
3524 rc = pci_request_regions(pdev, MODULENAME);
3526 netif_err(tp, probe, dev, "could not request regions\n");
3530 tp->cp_cmd = RxChkSum;
3532 if ((sizeof(dma_addr_t) > 4) &&
3533 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
3534 tp->cp_cmd |= PCIDAC;
3535 dev->features |= NETIF_F_HIGHDMA;
3537 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3539 netif_err(tp, probe, dev, "DMA configuration failed\n");
3540 goto err_out_free_res_3;
3544 /* ioremap MMIO region */
3545 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
3547 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
3549 goto err_out_free_res_3;
3551 tp->mmio_addr = ioaddr;
3553 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3555 netif_info(tp, probe, dev, "no PCI Express capability\n");
3557 RTL_W16(IntrMask, 0x0000);
3561 RTL_W16(IntrStatus, 0xffff);
3563 pci_set_master(pdev);
3565 /* Identify chip attached to board */
3566 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
3569 * Pretend we are using VLANs; This bypasses a nasty bug where
3570 * Interrupts stop flowing on high load on 8110SCd controllers.
3572 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3573 tp->cp_cmd |= RxVlan;
3575 rtl_init_mdio_ops(tp);
3576 rtl_init_pll_power_ops(tp);
3577 rtl_init_jumbo_ops(tp);
3579 rtl8169_print_mac_version(tp);
3581 chipset = tp->mac_version;
3582 tp->txd_version = rtl_chip_infos[chipset].txd_version;
3584 RTL_W8(Cfg9346, Cfg9346_Unlock);
3585 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3586 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
3587 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3588 tp->features |= RTL_FEATURE_WOL;
3589 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3590 tp->features |= RTL_FEATURE_WOL;
3591 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
3592 RTL_W8(Cfg9346, Cfg9346_Lock);
3594 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3595 (RTL_R8(PHYstatus) & TBI_Enable)) {
3596 tp->set_speed = rtl8169_set_speed_tbi;
3597 tp->get_settings = rtl8169_gset_tbi;
3598 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3599 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3600 tp->link_ok = rtl8169_tbi_link_ok;
3601 tp->do_ioctl = rtl_tbi_ioctl;
3603 tp->set_speed = rtl8169_set_speed_xmii;
3604 tp->get_settings = rtl8169_gset_xmii;
3605 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3606 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3607 tp->link_ok = rtl8169_xmii_link_ok;
3608 tp->do_ioctl = rtl_xmii_ioctl;
3611 spin_lock_init(&tp->lock);
3613 /* Get MAC address */
3614 for (i = 0; i < MAC_ADDR_LEN; i++)
3615 dev->dev_addr[i] = RTL_R8(MAC0 + i);
3616 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3618 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
3619 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3620 dev->irq = pdev->irq;
3621 dev->base_addr = (unsigned long) ioaddr;
3623 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
3625 /* don't enable SG, IP_CSUM and TSO by default - it might not work
3626 * properly for all devices */
3627 dev->features |= NETIF_F_RXCSUM |
3628 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3630 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3631 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3632 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3635 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3636 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
3637 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
3639 tp->intr_mask = 0xffff;
3640 tp->hw_start = cfg->hw_start;
3641 tp->intr_event = cfg->intr_event;
3642 tp->napi_event = cfg->napi_event;
3644 tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
3645 ~(RxBOVF | RxFOVF) : ~0;
3647 init_timer(&tp->timer);
3648 tp->timer.data = (unsigned long) dev;
3649 tp->timer.function = rtl8169_phy_timer;
3651 tp->fw = RTL_FIRMWARE_UNKNOWN;
3653 rc = register_netdev(dev);
3657 pci_set_drvdata(pdev, dev);
3659 netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
3660 rtl_chip_infos[chipset].name, dev->base_addr, dev->dev_addr,
3661 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
3662 if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
3663 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
3664 "tx checksumming: %s]\n",
3665 rtl_chip_infos[chipset].jumbo_max,
3666 rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
3669 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3670 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3671 tp->mac_version == RTL_GIGA_MAC_VER_31) {
3672 rtl8168_driver_start(tp);
3675 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
3677 if (pci_dev_run_wake(pdev))
3678 pm_runtime_put_noidle(&pdev->dev);
3680 netif_carrier_off(dev);
3686 rtl_disable_msi(pdev, tp);
3689 pci_release_regions(pdev);
3691 pci_clear_mwi(pdev);
3692 pci_disable_device(pdev);
3698 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
3700 struct net_device *dev = pci_get_drvdata(pdev);
3701 struct rtl8169_private *tp = netdev_priv(dev);
3703 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3704 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3705 tp->mac_version == RTL_GIGA_MAC_VER_31) {
3706 rtl8168_driver_stop(tp);
3709 cancel_delayed_work_sync(&tp->task);
3711 unregister_netdev(dev);
3713 rtl_release_firmware(tp);
3715 if (pci_dev_run_wake(pdev))
3716 pm_runtime_get_noresume(&pdev->dev);
3718 /* restore original MAC address */
3719 rtl_rar_set(tp, dev->perm_addr);
3721 rtl_disable_msi(pdev, tp);
3722 rtl8169_release_board(pdev, dev, tp->mmio_addr);
3723 pci_set_drvdata(pdev, NULL);
3726 static void rtl_request_firmware(struct rtl8169_private *tp)
3728 /* Return early if the firmware is already loaded / cached. */
3729 if (IS_ERR(tp->fw)) {
3732 name = rtl_lookup_firmware_name(tp);
3736 rc = request_firmware(&tp->fw, name, &tp->pci_dev->dev);
3740 netif_warn(tp, ifup, tp->dev, "unable to load "
3741 "firmware patch %s (%d)\n", name, rc);
3747 static int rtl8169_open(struct net_device *dev)
3749 struct rtl8169_private *tp = netdev_priv(dev);
3750 void __iomem *ioaddr = tp->mmio_addr;
3751 struct pci_dev *pdev = tp->pci_dev;
3752 int retval = -ENOMEM;
3754 pm_runtime_get_sync(&pdev->dev);
3757 * Rx and Tx desscriptors needs 256 bytes alignment.
3758 * dma_alloc_coherent provides more.
3760 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
3761 &tp->TxPhyAddr, GFP_KERNEL);
3762 if (!tp->TxDescArray)
3763 goto err_pm_runtime_put;
3765 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
3766 &tp->RxPhyAddr, GFP_KERNEL);
3767 if (!tp->RxDescArray)
3770 retval = rtl8169_init_ring(dev);
3774 INIT_DELAYED_WORK(&tp->task, NULL);
3778 rtl_request_firmware(tp);
3780 retval = request_irq(dev->irq, rtl8169_interrupt,
3781 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
3784 goto err_release_fw_2;
3786 napi_enable(&tp->napi);
3788 rtl8169_init_phy(dev, tp);
3790 rtl8169_set_features(dev, dev->features);
3792 rtl_pll_power_up(tp);
3796 tp->saved_wolopts = 0;
3797 pm_runtime_put_noidle(&pdev->dev);
3799 rtl8169_check_link_status(dev, tp, ioaddr);
3804 rtl_release_firmware(tp);
3805 rtl8169_rx_clear(tp);
3807 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
3809 tp->RxDescArray = NULL;
3811 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
3813 tp->TxDescArray = NULL;
3815 pm_runtime_put_noidle(&pdev->dev);
3819 static void rtl8169_hw_reset(struct rtl8169_private *tp)
3821 void __iomem *ioaddr = tp->mmio_addr;
3823 /* Disable interrupts */
3824 rtl8169_irq_mask_and_ack(tp);
3826 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3827 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3828 tp->mac_version == RTL_GIGA_MAC_VER_31) {
3829 while (RTL_R8(TxPoll) & NPQ)
3834 /* Reset the chipset */
3835 RTL_W8(ChipCmd, CmdReset);
3841 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
3843 void __iomem *ioaddr = tp->mmio_addr;
3844 u32 cfg = rtl8169_rx_config;
3846 cfg |= (RTL_R32(RxConfig) & RTL_RX_CONFIG_MASK);
3847 RTL_W32(RxConfig, cfg);
3849 /* Set DMA burst size and Interframe Gap Time */
3850 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3851 (InterFrameGap << TxInterFrameGapShift));
3854 static void rtl_hw_start(struct net_device *dev)
3856 struct rtl8169_private *tp = netdev_priv(dev);
3862 netif_start_queue(dev);
3865 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3866 void __iomem *ioaddr)
3869 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3870 * register to be written before TxDescAddrLow to work.
3871 * Switching from MMIO to I/O access fixes the issue as well.
3873 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
3874 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
3875 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
3876 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
3879 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
3883 cmd = RTL_R16(CPlusCmd);
3884 RTL_W16(CPlusCmd, cmd);
3888 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
3890 /* Low hurts. Let's disable the filtering. */
3891 RTL_W16(RxMaxSize, rx_buf_sz + 1);
3894 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
3896 static const struct rtl_cfg2_info {
3901 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
3902 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
3903 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
3904 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3906 const struct rtl_cfg2_info *p = cfg2_info;
3910 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
3911 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
3912 if ((p->mac_version == mac_version) && (p->clk == clk)) {
3913 RTL_W32(0x7c, p->val);
3919 static void rtl_hw_start_8169(struct net_device *dev)
3921 struct rtl8169_private *tp = netdev_priv(dev);
3922 void __iomem *ioaddr = tp->mmio_addr;
3923 struct pci_dev *pdev = tp->pci_dev;
3925 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
3926 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
3927 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
3930 RTL_W8(Cfg9346, Cfg9346_Unlock);
3931 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
3932 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3933 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
3934 tp->mac_version == RTL_GIGA_MAC_VER_04)
3935 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3937 RTL_W8(EarlyTxThres, NoEarlyTx);
3939 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
3941 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
3942 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3943 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
3944 tp->mac_version == RTL_GIGA_MAC_VER_04)
3945 rtl_set_rx_tx_config_registers(tp);
3947 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3949 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3950 tp->mac_version == RTL_GIGA_MAC_VER_03) {
3951 dprintk("Set MAC Reg C+CR Offset 0xE0. "
3952 "Bit-3 and bit-14 MUST be 1\n");
3953 tp->cp_cmd |= (1 << 14);
3956 RTL_W16(CPlusCmd, tp->cp_cmd);
3958 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
3961 * Undocumented corner. Supposedly:
3962 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3964 RTL_W16(IntrMitigate, 0x0000);
3966 rtl_set_rx_tx_desc_registers(tp, ioaddr);
3968 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
3969 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
3970 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
3971 tp->mac_version != RTL_GIGA_MAC_VER_04) {
3972 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3973 rtl_set_rx_tx_config_registers(tp);
3976 RTL_W8(Cfg9346, Cfg9346_Lock);
3978 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3981 RTL_W32(RxMissed, 0);
3983 rtl_set_rx_mode(dev);
3985 /* no early-rx interrupts */
3986 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
3988 /* Enable all known interrupts by setting the interrupt mask. */
3989 RTL_W16(IntrMask, tp->intr_event);
3992 static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
3996 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
3997 rtl_csi_write(ioaddr, 0x070c, csi | bits);
4000 static void rtl_csi_access_enable_1(void __iomem *ioaddr)
4002 rtl_csi_access_enable(ioaddr, 0x17000000);
4005 static void rtl_csi_access_enable_2(void __iomem *ioaddr)
4007 rtl_csi_access_enable(ioaddr, 0x27000000);
4011 unsigned int offset;
4016 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
4021 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
4022 rtl_ephy_write(ioaddr, e->offset, w);
4027 static void rtl_disable_clock_request(struct pci_dev *pdev)
4029 struct net_device *dev = pci_get_drvdata(pdev);
4030 struct rtl8169_private *tp = netdev_priv(dev);
4031 int cap = tp->pcie_cap;
4036 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4037 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
4038 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4042 static void rtl_enable_clock_request(struct pci_dev *pdev)
4044 struct net_device *dev = pci_get_drvdata(pdev);
4045 struct rtl8169_private *tp = netdev_priv(dev);
4046 int cap = tp->pcie_cap;
4051 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4052 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
4053 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4057 #define R8168_CPCMD_QUIRK_MASK (\
4068 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
4070 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4072 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4074 rtl_tx_performance_tweak(pdev,
4075 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4078 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
4080 rtl_hw_start_8168bb(ioaddr, pdev);
4082 RTL_W8(MaxTxPacketSize, TxPacketMax);
4084 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4087 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
4089 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4091 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4093 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4095 rtl_disable_clock_request(pdev);
4097 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4100 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
4102 static const struct ephy_info e_info_8168cp[] = {
4103 { 0x01, 0, 0x0001 },
4104 { 0x02, 0x0800, 0x1000 },
4105 { 0x03, 0, 0x0042 },
4106 { 0x06, 0x0080, 0x0000 },
4110 rtl_csi_access_enable_2(ioaddr);
4112 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4114 __rtl_hw_start_8168cp(ioaddr, pdev);
4117 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
4119 rtl_csi_access_enable_2(ioaddr);
4121 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4123 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4125 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4128 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
4130 rtl_csi_access_enable_2(ioaddr);
4132 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4135 RTL_W8(DBG_REG, 0x20);
4137 RTL_W8(MaxTxPacketSize, TxPacketMax);
4139 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4141 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4144 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
4146 static const struct ephy_info e_info_8168c_1[] = {
4147 { 0x02, 0x0800, 0x1000 },
4148 { 0x03, 0, 0x0002 },
4149 { 0x06, 0x0080, 0x0000 }
4152 rtl_csi_access_enable_2(ioaddr);
4154 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4156 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4158 __rtl_hw_start_8168cp(ioaddr, pdev);
4161 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
4163 static const struct ephy_info e_info_8168c_2[] = {
4164 { 0x01, 0, 0x0001 },
4165 { 0x03, 0x0400, 0x0220 }
4168 rtl_csi_access_enable_2(ioaddr);
4170 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4172 __rtl_hw_start_8168cp(ioaddr, pdev);
4175 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
4177 rtl_hw_start_8168c_2(ioaddr, pdev);
4180 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
4182 rtl_csi_access_enable_2(ioaddr);
4184 __rtl_hw_start_8168cp(ioaddr, pdev);
4187 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
4189 rtl_csi_access_enable_2(ioaddr);
4191 rtl_disable_clock_request(pdev);
4193 RTL_W8(MaxTxPacketSize, TxPacketMax);
4195 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4197 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4200 static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev)
4202 rtl_csi_access_enable_1(ioaddr);
4204 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4206 RTL_W8(MaxTxPacketSize, TxPacketMax);
4208 rtl_disable_clock_request(pdev);
4211 static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
4213 static const struct ephy_info e_info_8168d_4[] = {
4215 { 0x19, 0x20, 0x50 },
4220 rtl_csi_access_enable_1(ioaddr);
4222 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4224 RTL_W8(MaxTxPacketSize, TxPacketMax);
4226 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4227 const struct ephy_info *e = e_info_8168d_4 + i;
4230 w = rtl_ephy_read(ioaddr, e->offset);
4231 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
4234 rtl_enable_clock_request(pdev);
4237 static void rtl_hw_start_8168e(void __iomem *ioaddr, struct pci_dev *pdev)
4239 static const struct ephy_info e_info_8168e[] = {
4240 { 0x00, 0x0200, 0x0100 },
4241 { 0x00, 0x0000, 0x0004 },
4242 { 0x06, 0x0002, 0x0001 },
4243 { 0x06, 0x0000, 0x0030 },
4244 { 0x07, 0x0000, 0x2000 },
4245 { 0x00, 0x0000, 0x0020 },
4246 { 0x03, 0x5800, 0x2000 },
4247 { 0x03, 0x0000, 0x0001 },
4248 { 0x01, 0x0800, 0x1000 },
4249 { 0x07, 0x0000, 0x4000 },
4250 { 0x1e, 0x0000, 0x2000 },
4251 { 0x19, 0xffff, 0xfe6c },
4252 { 0x0a, 0x0000, 0x0040 }
4255 rtl_csi_access_enable_2(ioaddr);
4257 rtl_ephy_init(ioaddr, e_info_8168e, ARRAY_SIZE(e_info_8168e));
4259 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4261 RTL_W8(MaxTxPacketSize, TxPacketMax);
4263 rtl_disable_clock_request(pdev);
4265 /* Reset tx FIFO pointer */
4266 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
4267 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
4269 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4272 static void rtl_hw_start_8168(struct net_device *dev)
4274 struct rtl8169_private *tp = netdev_priv(dev);
4275 void __iomem *ioaddr = tp->mmio_addr;
4276 struct pci_dev *pdev = tp->pci_dev;
4278 RTL_W8(Cfg9346, Cfg9346_Unlock);
4280 RTL_W8(MaxTxPacketSize, TxPacketMax);
4282 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4284 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
4286 RTL_W16(CPlusCmd, tp->cp_cmd);
4288 RTL_W16(IntrMitigate, 0x5151);
4290 /* Work around for RxFIFO overflow. */
4291 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
4292 tp->intr_event |= RxFIFOOver | PCSTimeout;
4293 tp->intr_event &= ~RxOverflow;
4296 rtl_set_rx_tx_desc_registers(tp, ioaddr);
4298 rtl_set_rx_mode(dev);
4300 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4301 (InterFrameGap << TxInterFrameGapShift));
4305 switch (tp->mac_version) {
4306 case RTL_GIGA_MAC_VER_11:
4307 rtl_hw_start_8168bb(ioaddr, pdev);
4310 case RTL_GIGA_MAC_VER_12:
4311 case RTL_GIGA_MAC_VER_17:
4312 rtl_hw_start_8168bef(ioaddr, pdev);
4315 case RTL_GIGA_MAC_VER_18:
4316 rtl_hw_start_8168cp_1(ioaddr, pdev);
4319 case RTL_GIGA_MAC_VER_19:
4320 rtl_hw_start_8168c_1(ioaddr, pdev);
4323 case RTL_GIGA_MAC_VER_20:
4324 rtl_hw_start_8168c_2(ioaddr, pdev);
4327 case RTL_GIGA_MAC_VER_21:
4328 rtl_hw_start_8168c_3(ioaddr, pdev);
4331 case RTL_GIGA_MAC_VER_22:
4332 rtl_hw_start_8168c_4(ioaddr, pdev);
4335 case RTL_GIGA_MAC_VER_23:
4336 rtl_hw_start_8168cp_2(ioaddr, pdev);
4339 case RTL_GIGA_MAC_VER_24:
4340 rtl_hw_start_8168cp_3(ioaddr, pdev);
4343 case RTL_GIGA_MAC_VER_25:
4344 case RTL_GIGA_MAC_VER_26:
4345 case RTL_GIGA_MAC_VER_27:
4346 rtl_hw_start_8168d(ioaddr, pdev);
4349 case RTL_GIGA_MAC_VER_28:
4350 rtl_hw_start_8168d_4(ioaddr, pdev);
4353 case RTL_GIGA_MAC_VER_31:
4354 rtl_hw_start_8168dp(ioaddr, pdev);
4357 case RTL_GIGA_MAC_VER_32:
4358 case RTL_GIGA_MAC_VER_33:
4359 rtl_hw_start_8168e(ioaddr, pdev);
4363 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
4364 dev->name, tp->mac_version);
4368 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4370 RTL_W8(Cfg9346, Cfg9346_Lock);
4372 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4374 RTL_W16(IntrMask, tp->intr_event);
4377 #define R810X_CPCMD_QUIRK_MASK (\
4388 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4390 static const struct ephy_info e_info_8102e_1[] = {
4391 { 0x01, 0, 0x6e65 },
4392 { 0x02, 0, 0x091f },
4393 { 0x03, 0, 0xc2f9 },
4394 { 0x06, 0, 0xafb5 },
4395 { 0x07, 0, 0x0e00 },
4396 { 0x19, 0, 0xec80 },
4397 { 0x01, 0, 0x2e65 },
4402 rtl_csi_access_enable_2(ioaddr);
4404 RTL_W8(DBG_REG, FIX_NAK_1);
4406 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4409 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
4410 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4412 cfg1 = RTL_R8(Config1);
4413 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
4414 RTL_W8(Config1, cfg1 & ~LEDS0);
4416 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
4419 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4421 rtl_csi_access_enable_2(ioaddr);
4423 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4425 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
4426 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4429 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
4431 rtl_hw_start_8102e_2(ioaddr, pdev);
4433 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
4436 static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4438 static const struct ephy_info e_info_8105e_1[] = {
4439 { 0x07, 0, 0x4000 },
4440 { 0x19, 0, 0x0200 },
4441 { 0x19, 0, 0x0020 },
4442 { 0x1e, 0, 0x2000 },
4443 { 0x03, 0, 0x0001 },
4444 { 0x19, 0, 0x0100 },
4445 { 0x19, 0, 0x0004 },
4449 /* Force LAN exit from ASPM if Rx/Tx are not idle */
4450 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
4452 /* Disable Early Tally Counter */
4453 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
4455 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4456 RTL_W8(DLLPR, RTL_R8(DLLPR) | PM_SWITCH);
4458 rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
4461 static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4463 rtl_hw_start_8105e_1(ioaddr, pdev);
4464 rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
4467 static void rtl_hw_start_8101(struct net_device *dev)
4469 struct rtl8169_private *tp = netdev_priv(dev);
4470 void __iomem *ioaddr = tp->mmio_addr;
4471 struct pci_dev *pdev = tp->pci_dev;
4473 if (tp->mac_version >= RTL_GIGA_MAC_VER_30) {
4474 tp->intr_event &= ~RxFIFOOver;
4475 tp->napi_event &= ~RxFIFOOver;
4478 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
4479 tp->mac_version == RTL_GIGA_MAC_VER_16) {
4480 int cap = tp->pcie_cap;
4483 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
4484 PCI_EXP_DEVCTL_NOSNOOP_EN);
4488 RTL_W8(Cfg9346, Cfg9346_Unlock);
4490 switch (tp->mac_version) {
4491 case RTL_GIGA_MAC_VER_07:
4492 rtl_hw_start_8102e_1(ioaddr, pdev);
4495 case RTL_GIGA_MAC_VER_08:
4496 rtl_hw_start_8102e_3(ioaddr, pdev);
4499 case RTL_GIGA_MAC_VER_09:
4500 rtl_hw_start_8102e_2(ioaddr, pdev);
4503 case RTL_GIGA_MAC_VER_29:
4504 rtl_hw_start_8105e_1(ioaddr, pdev);
4506 case RTL_GIGA_MAC_VER_30:
4507 rtl_hw_start_8105e_2(ioaddr, pdev);
4511 RTL_W8(Cfg9346, Cfg9346_Lock);
4513 RTL_W8(MaxTxPacketSize, TxPacketMax);
4515 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4517 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
4518 RTL_W16(CPlusCmd, tp->cp_cmd);
4520 RTL_W16(IntrMitigate, 0x0000);
4522 rtl_set_rx_tx_desc_registers(tp, ioaddr);
4524 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4525 rtl_set_rx_tx_config_registers(tp);
4529 rtl_set_rx_mode(dev);
4531 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
4533 RTL_W16(IntrMask, tp->intr_event);
4536 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
4538 struct rtl8169_private *tp = netdev_priv(dev);
4540 if (new_mtu < ETH_ZLEN ||
4541 new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
4544 if (new_mtu > ETH_DATA_LEN)
4545 rtl_hw_jumbo_enable(tp);
4547 rtl_hw_jumbo_disable(tp);
4550 netdev_update_features(dev);
4555 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
4557 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
4558 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
4561 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
4562 void **data_buff, struct RxDesc *desc)
4564 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
4569 rtl8169_make_unusable_by_asic(desc);
4572 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
4574 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
4576 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
4579 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
4582 desc->addr = cpu_to_le64(mapping);
4584 rtl8169_mark_to_asic(desc, rx_buf_sz);
4587 static inline void *rtl8169_align(void *data)
4589 return (void *)ALIGN((long)data, 16);
4592 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
4593 struct RxDesc *desc)
4597 struct device *d = &tp->pci_dev->dev;
4598 struct net_device *dev = tp->dev;
4599 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
4601 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
4605 if (rtl8169_align(data) != data) {
4607 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
4612 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
4614 if (unlikely(dma_mapping_error(d, mapping))) {
4615 if (net_ratelimit())
4616 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
4620 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
4628 static void rtl8169_rx_clear(struct rtl8169_private *tp)
4632 for (i = 0; i < NUM_RX_DESC; i++) {
4633 if (tp->Rx_databuff[i]) {
4634 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
4635 tp->RxDescArray + i);
4640 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
4642 desc->opts1 |= cpu_to_le32(RingEnd);
4645 static int rtl8169_rx_fill(struct rtl8169_private *tp)
4649 for (i = 0; i < NUM_RX_DESC; i++) {
4652 if (tp->Rx_databuff[i])
4655 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
4657 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
4660 tp->Rx_databuff[i] = data;
4663 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4667 rtl8169_rx_clear(tp);
4671 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4673 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
4676 static int rtl8169_init_ring(struct net_device *dev)
4678 struct rtl8169_private *tp = netdev_priv(dev);
4680 rtl8169_init_ring_indexes(tp);
4682 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
4683 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
4685 return rtl8169_rx_fill(tp);
4688 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
4689 struct TxDesc *desc)
4691 unsigned int len = tx_skb->len;
4693 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
4701 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4706 for (i = 0; i < n; i++) {
4707 unsigned int entry = (start + i) % NUM_TX_DESC;
4708 struct ring_info *tx_skb = tp->tx_skb + entry;
4709 unsigned int len = tx_skb->len;
4712 struct sk_buff *skb = tx_skb->skb;
4714 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4715 tp->TxDescArray + entry);
4717 tp->dev->stats.tx_dropped++;
4725 static void rtl8169_tx_clear(struct rtl8169_private *tp)
4727 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
4728 tp->cur_tx = tp->dirty_tx = 0;
4731 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
4733 struct rtl8169_private *tp = netdev_priv(dev);
4735 PREPARE_DELAYED_WORK(&tp->task, task);
4736 schedule_delayed_work(&tp->task, 4);
4739 static void rtl8169_wait_for_quiescence(struct net_device *dev)
4741 struct rtl8169_private *tp = netdev_priv(dev);
4742 void __iomem *ioaddr = tp->mmio_addr;
4744 synchronize_irq(dev->irq);
4746 /* Wait for any pending NAPI task to complete */
4747 napi_disable(&tp->napi);
4749 rtl8169_irq_mask_and_ack(tp);
4751 tp->intr_mask = 0xffff;
4752 RTL_W16(IntrMask, tp->intr_event);
4753 napi_enable(&tp->napi);
4756 static void rtl8169_reinit_task(struct work_struct *work)
4758 struct rtl8169_private *tp =
4759 container_of(work, struct rtl8169_private, task.work);
4760 struct net_device *dev = tp->dev;
4765 if (!netif_running(dev))
4768 rtl8169_wait_for_quiescence(dev);
4771 ret = rtl8169_open(dev);
4772 if (unlikely(ret < 0)) {
4773 if (net_ratelimit())
4774 netif_err(tp, drv, dev,
4775 "reinit failure (status = %d). Rescheduling\n",
4777 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4784 static void rtl8169_reset_task(struct work_struct *work)
4786 struct rtl8169_private *tp =
4787 container_of(work, struct rtl8169_private, task.work);
4788 struct net_device *dev = tp->dev;
4793 if (!netif_running(dev))
4796 rtl8169_wait_for_quiescence(dev);
4798 for (i = 0; i < NUM_RX_DESC; i++)
4799 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
4801 rtl8169_tx_clear(tp);
4803 rtl8169_init_ring_indexes(tp);
4805 netif_wake_queue(dev);
4806 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
4812 static void rtl8169_tx_timeout(struct net_device *dev)
4814 struct rtl8169_private *tp = netdev_priv(dev);
4816 rtl8169_hw_reset(tp);
4818 /* Let's wait a bit while any (async) irq lands on */
4819 rtl8169_schedule_work(dev, rtl8169_reset_task);
4822 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4825 struct skb_shared_info *info = skb_shinfo(skb);
4826 unsigned int cur_frag, entry;
4827 struct TxDesc * uninitialized_var(txd);
4828 struct device *d = &tp->pci_dev->dev;
4831 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4832 skb_frag_t *frag = info->frags + cur_frag;
4837 entry = (entry + 1) % NUM_TX_DESC;
4839 txd = tp->TxDescArray + entry;
4841 addr = ((void *) page_address(frag->page)) + frag->page_offset;
4842 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
4843 if (unlikely(dma_mapping_error(d, mapping))) {
4844 if (net_ratelimit())
4845 netif_err(tp, drv, tp->dev,
4846 "Failed to map TX fragments DMA!\n");
4850 /* Anti gcc 2.95.3 bugware (sic) */
4851 status = opts[0] | len |
4852 (RingEnd * !((entry + 1) % NUM_TX_DESC));
4854 txd->opts1 = cpu_to_le32(status);
4855 txd->opts2 = cpu_to_le32(opts[1]);
4856 txd->addr = cpu_to_le64(mapping);
4858 tp->tx_skb[entry].len = len;
4862 tp->tx_skb[entry].skb = skb;
4863 txd->opts1 |= cpu_to_le32(LastFrag);
4869 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4873 static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
4874 struct sk_buff *skb, u32 *opts)
4876 const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
4877 u32 mss = skb_shinfo(skb)->gso_size;
4878 int offset = info->opts_offset;
4882 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
4883 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4884 const struct iphdr *ip = ip_hdr(skb);
4886 if (ip->protocol == IPPROTO_TCP)
4887 opts[offset] |= info->checksum.tcp;
4888 else if (ip->protocol == IPPROTO_UDP)
4889 opts[offset] |= info->checksum.udp;
4895 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4896 struct net_device *dev)
4898 struct rtl8169_private *tp = netdev_priv(dev);
4899 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
4900 struct TxDesc *txd = tp->TxDescArray + entry;
4901 void __iomem *ioaddr = tp->mmio_addr;
4902 struct device *d = &tp->pci_dev->dev;
4908 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
4909 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
4913 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
4916 len = skb_headlen(skb);
4917 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
4918 if (unlikely(dma_mapping_error(d, mapping))) {
4919 if (net_ratelimit())
4920 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
4924 tp->tx_skb[entry].len = len;
4925 txd->addr = cpu_to_le64(mapping);
4927 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
4930 rtl8169_tso_csum(tp, skb, opts);
4932 frags = rtl8169_xmit_frags(tp, skb, opts);
4936 opts[0] |= FirstFrag;
4938 opts[0] |= FirstFrag | LastFrag;
4939 tp->tx_skb[entry].skb = skb;
4942 txd->opts2 = cpu_to_le32(opts[1]);
4946 /* Anti gcc 2.95.3 bugware (sic) */
4947 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4948 txd->opts1 = cpu_to_le32(status);
4950 tp->cur_tx += frags + 1;
4954 RTL_W8(TxPoll, NPQ);
4956 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
4957 netif_stop_queue(dev);
4959 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
4960 netif_wake_queue(dev);
4963 return NETDEV_TX_OK;
4966 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
4969 dev->stats.tx_dropped++;
4970 return NETDEV_TX_OK;
4973 netif_stop_queue(dev);
4974 dev->stats.tx_dropped++;
4975 return NETDEV_TX_BUSY;
4978 static void rtl8169_pcierr_interrupt(struct net_device *dev)
4980 struct rtl8169_private *tp = netdev_priv(dev);
4981 struct pci_dev *pdev = tp->pci_dev;
4982 u16 pci_status, pci_cmd;
4984 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4985 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
4987 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
4988 pci_cmd, pci_status);
4991 * The recovery sequence below admits a very elaborated explanation:
4992 * - it seems to work;
4993 * - I did not see what else could be done;
4994 * - it makes iop3xx happy.
4996 * Feel free to adjust to your needs.
4998 if (pdev->broken_parity_status)
4999 pci_cmd &= ~PCI_COMMAND_PARITY;
5001 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5003 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
5005 pci_write_config_word(pdev, PCI_STATUS,
5006 pci_status & (PCI_STATUS_DETECTED_PARITY |
5007 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5008 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5010 /* The infamous DAC f*ckup only happens at boot time */
5011 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
5012 void __iomem *ioaddr = tp->mmio_addr;
5014 netif_info(tp, intr, dev, "disabling PCI DAC\n");
5015 tp->cp_cmd &= ~PCIDAC;
5016 RTL_W16(CPlusCmd, tp->cp_cmd);
5017 dev->features &= ~NETIF_F_HIGHDMA;
5020 rtl8169_hw_reset(tp);
5022 rtl8169_schedule_work(dev, rtl8169_reinit_task);
5025 static void rtl8169_tx_interrupt(struct net_device *dev,
5026 struct rtl8169_private *tp,
5027 void __iomem *ioaddr)
5029 unsigned int dirty_tx, tx_left;
5031 dirty_tx = tp->dirty_tx;
5033 tx_left = tp->cur_tx - dirty_tx;
5035 while (tx_left > 0) {
5036 unsigned int entry = dirty_tx % NUM_TX_DESC;
5037 struct ring_info *tx_skb = tp->tx_skb + entry;
5041 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5042 if (status & DescOwn)
5045 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5046 tp->TxDescArray + entry);
5047 if (status & LastFrag) {
5048 dev->stats.tx_packets++;
5049 dev->stats.tx_bytes += tx_skb->skb->len;
5050 dev_kfree_skb(tx_skb->skb);
5057 if (tp->dirty_tx != dirty_tx) {
5058 tp->dirty_tx = dirty_tx;
5060 if (netif_queue_stopped(dev) &&
5061 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
5062 netif_wake_queue(dev);
5065 * 8168 hack: TxPoll requests are lost when the Tx packets are
5066 * too close. Let's kick an extra TxPoll request when a burst
5067 * of start_xmit activity is detected (if it is not detected,
5068 * it is slow enough). -- FR
5071 if (tp->cur_tx != dirty_tx)
5072 RTL_W8(TxPoll, NPQ);
5076 static inline int rtl8169_fragmented_frame(u32 status)
5078 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
5081 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
5083 u32 status = opts1 & RxProtoMask;
5085 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
5086 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
5087 skb->ip_summed = CHECKSUM_UNNECESSARY;
5089 skb_checksum_none_assert(skb);
5092 static struct sk_buff *rtl8169_try_rx_copy(void *data,
5093 struct rtl8169_private *tp,
5097 struct sk_buff *skb;
5098 struct device *d = &tp->pci_dev->dev;
5100 data = rtl8169_align(data);
5101 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
5103 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
5105 memcpy(skb->data, data, pkt_size);
5106 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
5111 static int rtl8169_rx_interrupt(struct net_device *dev,
5112 struct rtl8169_private *tp,
5113 void __iomem *ioaddr, u32 budget)
5115 unsigned int cur_rx, rx_left;
5118 cur_rx = tp->cur_rx;
5119 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
5120 rx_left = min(rx_left, budget);
5122 for (; rx_left > 0; rx_left--, cur_rx++) {
5123 unsigned int entry = cur_rx % NUM_RX_DESC;
5124 struct RxDesc *desc = tp->RxDescArray + entry;
5128 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
5130 if (status & DescOwn)
5132 if (unlikely(status & RxRES)) {
5133 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
5135 dev->stats.rx_errors++;
5136 if (status & (RxRWT | RxRUNT))
5137 dev->stats.rx_length_errors++;
5139 dev->stats.rx_crc_errors++;
5140 if (status & RxFOVF) {
5141 rtl8169_schedule_work(dev, rtl8169_reset_task);
5142 dev->stats.rx_fifo_errors++;
5144 rtl8169_mark_to_asic(desc, rx_buf_sz);
5146 struct sk_buff *skb;
5147 dma_addr_t addr = le64_to_cpu(desc->addr);
5148 int pkt_size = (status & 0x00003fff) - 4;
5151 * The driver does not support incoming fragmented
5152 * frames. They are seen as a symptom of over-mtu
5155 if (unlikely(rtl8169_fragmented_frame(status))) {
5156 dev->stats.rx_dropped++;
5157 dev->stats.rx_length_errors++;
5158 rtl8169_mark_to_asic(desc, rx_buf_sz);
5162 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
5163 tp, pkt_size, addr);
5164 rtl8169_mark_to_asic(desc, rx_buf_sz);
5166 dev->stats.rx_dropped++;
5170 rtl8169_rx_csum(skb, status);
5171 skb_put(skb, pkt_size);
5172 skb->protocol = eth_type_trans(skb, dev);
5174 rtl8169_rx_vlan_tag(desc, skb);
5176 napi_gro_receive(&tp->napi, skb);
5178 dev->stats.rx_bytes += pkt_size;
5179 dev->stats.rx_packets++;
5182 /* Work around for AMD plateform. */
5183 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
5184 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
5190 count = cur_rx - tp->cur_rx;
5191 tp->cur_rx = cur_rx;
5193 tp->dirty_rx += count;
5198 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
5200 struct net_device *dev = dev_instance;
5201 struct rtl8169_private *tp = netdev_priv(dev);
5202 void __iomem *ioaddr = tp->mmio_addr;
5206 /* loop handling interrupts until we have no new ones or
5207 * we hit a invalid/hotplug case.
5209 status = RTL_R16(IntrStatus);
5210 while (status && status != 0xffff) {
5211 status &= tp->intr_event;
5217 /* Handle all of the error cases first. These will reset
5218 * the chip, so just exit the loop.
5220 if (unlikely(!netif_running(dev))) {
5221 rtl8169_asic_down(tp);
5225 if (unlikely(status & RxFIFOOver)) {
5226 switch (tp->mac_version) {
5227 /* Work around for rx fifo overflow */
5228 case RTL_GIGA_MAC_VER_11:
5229 netif_stop_queue(dev);
5230 rtl8169_tx_timeout(dev);
5237 if (unlikely(status & SYSErr)) {
5238 rtl8169_pcierr_interrupt(dev);
5242 if (status & LinkChg)
5243 __rtl8169_check_link_status(dev, tp, ioaddr, true);
5245 /* We need to see the lastest version of tp->intr_mask to
5246 * avoid ignoring an MSI interrupt and having to wait for
5247 * another event which may never come.
5250 if (status & tp->intr_mask & tp->napi_event) {
5251 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
5252 tp->intr_mask = ~tp->napi_event;
5254 if (likely(napi_schedule_prep(&tp->napi)))
5255 __napi_schedule(&tp->napi);
5257 netif_info(tp, intr, dev,
5258 "interrupt %04x in poll\n", status);
5261 /* We only get a new MSI interrupt when all active irq
5262 * sources on the chip have been acknowledged. So, ack
5263 * everything we've seen and check if new sources have become
5264 * active to avoid blocking all interrupts from the chip.
5267 (status & RxFIFOOver) ? (status | RxOverflow) : status);
5268 status = RTL_R16(IntrStatus);
5271 return IRQ_RETVAL(handled);
5274 static int rtl8169_poll(struct napi_struct *napi, int budget)
5276 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5277 struct net_device *dev = tp->dev;
5278 void __iomem *ioaddr = tp->mmio_addr;
5281 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
5282 rtl8169_tx_interrupt(dev, tp, ioaddr);
5284 if (work_done < budget) {
5285 napi_complete(napi);
5287 /* We need for force the visibility of tp->intr_mask
5288 * for other CPUs, as we can loose an MSI interrupt
5289 * and potentially wait for a retransmit timeout if we don't.
5290 * The posted write to IntrMask is safe, as it will
5291 * eventually make it to the chip and we won't loose anything
5294 tp->intr_mask = 0xffff;
5296 RTL_W16(IntrMask, tp->intr_event);
5302 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
5304 struct rtl8169_private *tp = netdev_priv(dev);
5306 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5309 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
5310 RTL_W32(RxMissed, 0);
5313 static void rtl8169_down(struct net_device *dev)
5315 struct rtl8169_private *tp = netdev_priv(dev);
5316 void __iomem *ioaddr = tp->mmio_addr;
5318 del_timer_sync(&tp->timer);
5320 netif_stop_queue(dev);
5322 napi_disable(&tp->napi);
5324 spin_lock_irq(&tp->lock);
5326 rtl8169_asic_down(tp);
5328 * At this point device interrupts can not be enabled in any function,
5329 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
5330 * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
5332 rtl8169_rx_missed(dev, ioaddr);
5334 spin_unlock_irq(&tp->lock);
5336 synchronize_irq(dev->irq);
5338 /* Give a racing hard_start_xmit a few cycles to complete. */
5339 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
5341 rtl8169_tx_clear(tp);
5343 rtl8169_rx_clear(tp);
5345 rtl_pll_power_down(tp);
5348 static int rtl8169_close(struct net_device *dev)
5350 struct rtl8169_private *tp = netdev_priv(dev);
5351 struct pci_dev *pdev = tp->pci_dev;
5353 pm_runtime_get_sync(&pdev->dev);
5355 /* Update counters before going down */
5356 rtl8169_update_counters(dev);
5360 free_irq(dev->irq, dev);
5362 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5364 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5366 tp->TxDescArray = NULL;
5367 tp->RxDescArray = NULL;
5369 pm_runtime_put_sync(&pdev->dev);
5374 static void rtl_set_rx_mode(struct net_device *dev)
5376 struct rtl8169_private *tp = netdev_priv(dev);
5377 void __iomem *ioaddr = tp->mmio_addr;
5378 unsigned long flags;
5379 u32 mc_filter[2]; /* Multicast hash filter */
5383 if (dev->flags & IFF_PROMISC) {
5384 /* Unconditionally log net taps. */
5385 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
5387 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5389 mc_filter[1] = mc_filter[0] = 0xffffffff;
5390 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
5391 (dev->flags & IFF_ALLMULTI)) {
5392 /* Too many to filter perfectly -- accept all multicasts. */
5393 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5394 mc_filter[1] = mc_filter[0] = 0xffffffff;
5396 struct netdev_hw_addr *ha;
5398 rx_mode = AcceptBroadcast | AcceptMyPhys;
5399 mc_filter[1] = mc_filter[0] = 0;
5400 netdev_for_each_mc_addr(ha, dev) {
5401 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
5402 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5403 rx_mode |= AcceptMulticast;
5407 spin_lock_irqsave(&tp->lock, flags);
5409 tmp = rtl8169_rx_config | rx_mode |
5410 (RTL_R32(RxConfig) & RTL_RX_CONFIG_MASK);
5412 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
5413 u32 data = mc_filter[0];
5415 mc_filter[0] = swab32(mc_filter[1]);
5416 mc_filter[1] = swab32(data);
5419 RTL_W32(MAR0 + 4, mc_filter[1]);
5420 RTL_W32(MAR0 + 0, mc_filter[0]);
5422 RTL_W32(RxConfig, tmp);
5424 spin_unlock_irqrestore(&tp->lock, flags);
5428 * rtl8169_get_stats - Get rtl8169 read/write statistics
5429 * @dev: The Ethernet Device to get statistics for
5431 * Get TX/RX statistics for rtl8169
5433 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
5435 struct rtl8169_private *tp = netdev_priv(dev);
5436 void __iomem *ioaddr = tp->mmio_addr;
5437 unsigned long flags;
5439 if (netif_running(dev)) {
5440 spin_lock_irqsave(&tp->lock, flags);
5441 rtl8169_rx_missed(dev, ioaddr);
5442 spin_unlock_irqrestore(&tp->lock, flags);
5448 static void rtl8169_net_suspend(struct net_device *dev)
5450 struct rtl8169_private *tp = netdev_priv(dev);
5452 if (!netif_running(dev))
5455 rtl_pll_power_down(tp);
5457 netif_device_detach(dev);
5458 netif_stop_queue(dev);
5463 static int rtl8169_suspend(struct device *device)
5465 struct pci_dev *pdev = to_pci_dev(device);
5466 struct net_device *dev = pci_get_drvdata(pdev);
5468 rtl8169_net_suspend(dev);
5473 static void __rtl8169_resume(struct net_device *dev)
5475 struct rtl8169_private *tp = netdev_priv(dev);
5477 netif_device_attach(dev);
5479 rtl_pll_power_up(tp);
5481 rtl8169_schedule_work(dev, rtl8169_reset_task);
5484 static int rtl8169_resume(struct device *device)
5486 struct pci_dev *pdev = to_pci_dev(device);
5487 struct net_device *dev = pci_get_drvdata(pdev);
5488 struct rtl8169_private *tp = netdev_priv(dev);
5490 rtl8169_init_phy(dev, tp);
5492 if (netif_running(dev))
5493 __rtl8169_resume(dev);
5498 static int rtl8169_runtime_suspend(struct device *device)
5500 struct pci_dev *pdev = to_pci_dev(device);
5501 struct net_device *dev = pci_get_drvdata(pdev);
5502 struct rtl8169_private *tp = netdev_priv(dev);
5504 if (!tp->TxDescArray)
5507 spin_lock_irq(&tp->lock);
5508 tp->saved_wolopts = __rtl8169_get_wol(tp);
5509 __rtl8169_set_wol(tp, WAKE_ANY);
5510 spin_unlock_irq(&tp->lock);
5512 rtl8169_net_suspend(dev);
5517 static int rtl8169_runtime_resume(struct device *device)
5519 struct pci_dev *pdev = to_pci_dev(device);
5520 struct net_device *dev = pci_get_drvdata(pdev);
5521 struct rtl8169_private *tp = netdev_priv(dev);
5523 if (!tp->TxDescArray)
5526 spin_lock_irq(&tp->lock);
5527 __rtl8169_set_wol(tp, tp->saved_wolopts);
5528 tp->saved_wolopts = 0;
5529 spin_unlock_irq(&tp->lock);
5531 rtl8169_init_phy(dev, tp);
5533 __rtl8169_resume(dev);
5538 static int rtl8169_runtime_idle(struct device *device)
5540 struct pci_dev *pdev = to_pci_dev(device);
5541 struct net_device *dev = pci_get_drvdata(pdev);
5542 struct rtl8169_private *tp = netdev_priv(dev);
5544 return tp->TxDescArray ? -EBUSY : 0;
5547 static const struct dev_pm_ops rtl8169_pm_ops = {
5548 .suspend = rtl8169_suspend,
5549 .resume = rtl8169_resume,
5550 .freeze = rtl8169_suspend,
5551 .thaw = rtl8169_resume,
5552 .poweroff = rtl8169_suspend,
5553 .restore = rtl8169_resume,
5554 .runtime_suspend = rtl8169_runtime_suspend,
5555 .runtime_resume = rtl8169_runtime_resume,
5556 .runtime_idle = rtl8169_runtime_idle,
5559 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
5561 #else /* !CONFIG_PM */
5563 #define RTL8169_PM_OPS NULL
5565 #endif /* !CONFIG_PM */
5567 static void rtl_shutdown(struct pci_dev *pdev)
5569 struct net_device *dev = pci_get_drvdata(pdev);
5570 struct rtl8169_private *tp = netdev_priv(dev);
5571 void __iomem *ioaddr = tp->mmio_addr;
5573 rtl8169_net_suspend(dev);
5575 /* Restore original MAC address */
5576 rtl_rar_set(tp, dev->perm_addr);
5578 spin_lock_irq(&tp->lock);
5580 rtl8169_asic_down(tp);
5582 spin_unlock_irq(&tp->lock);
5584 if (system_state == SYSTEM_POWER_OFF) {
5585 /* WoL fails with 8168b when the receiver is disabled. */
5586 if ((tp->mac_version == RTL_GIGA_MAC_VER_11 ||
5587 tp->mac_version == RTL_GIGA_MAC_VER_12 ||
5588 tp->mac_version == RTL_GIGA_MAC_VER_17) &&
5589 (tp->features & RTL_FEATURE_WOL)) {
5590 pci_clear_master(pdev);
5592 RTL_W8(ChipCmd, CmdRxEnb);
5597 pci_wake_from_d3(pdev, true);
5598 pci_set_power_state(pdev, PCI_D3hot);
5602 static struct pci_driver rtl8169_pci_driver = {
5604 .id_table = rtl8169_pci_tbl,
5605 .probe = rtl8169_init_one,
5606 .remove = __devexit_p(rtl8169_remove_one),
5607 .shutdown = rtl_shutdown,
5608 .driver.pm = RTL8169_PM_OPS,
5611 static int __init rtl8169_init_module(void)
5613 return pci_register_driver(&rtl8169_pci_driver);
5616 static void __exit rtl8169_cleanup_module(void)
5618 pci_unregister_driver(&rtl8169_pci_driver);
5621 module_init(rtl8169_init_module);
5622 module_exit(rtl8169_cleanup_module);