drivers/net/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/mii.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/crc32.h>
  21 #include <linux/in.h>
  22 #include <linux/ip.h>
  23 #include <linux/tcp.h>
  24 #include <linux/init.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/firmware.h>
  28 #include <linux/pci-aspm.h>
  29
  30 #include <asm/system.h>
  31 #include <asm/io.h>
  32 #include <asm/irq.h>
  33
  34 #define RTL8169_VERSION "2.3LK-NAPI"
  35 #define MODULENAME "r8169"
  36 #define PFX MODULENAME ": "
  37
  38 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  39 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  40 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  41 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  42 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  43
  44 #ifdef RTL8169_DEBUG
  45 #define assert(expr) \
  46         if (!(expr)) {                                  \
  47                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  48                 #expr,__FILE__,__func__,__LINE__);              \
  49         }
  50 #define dprintk(fmt, args...) \
  51         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
  52 #else
  53 #define assert(expr) do {} while (0)
  54 #define dprintk(fmt, args...)   do {} while (0)
  55 #endif /* RTL8169_DEBUG */
  56
  57 #define R8169_MSG_DEFAULT \
  58         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  59
  60 #define TX_BUFFS_AVAIL(tp) \
  61         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
  62
  63 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  64    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  65 static const int multicast_filter_limit = 32;
  66
  67 /* MAC address length */
  68 #define MAC_ADDR_LEN    6
  69
  70 #define MAX_READ_REQUEST_SHIFT  12
  71 #define RX_FIFO_THRESH  7       /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
  72 #define RX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  73 #define TX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  74 #define SafeMtu         0x1c20  /* ... actually life sucks beyond ~7k */
  75 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  76
  77 #define R8169_REGS_SIZE         256
  78 #define R8169_NAPI_WEIGHT       64
  79 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  80 #define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
  81 #define RX_BUF_SIZE     1536    /* Rx Buffer size */
  82 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  83 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  84
  85 #define RTL8169_TX_TIMEOUT      (6*HZ)
  86 #define RTL8169_PHY_TIMEOUT     (10*HZ)
  87
  88 #define RTL_EEPROM_SIG          cpu_to_le32(0x8129)
  89 #define RTL_EEPROM_SIG_MASK     cpu_to_le32(0xffff)
  90 #define RTL_EEPROM_SIG_ADDR     0x0000
  91
  92 /* write/read MMIO register */
  93 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
  94 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
  95 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
  96 #define RTL_R8(reg)             readb (ioaddr + (reg))
  97 #define RTL_R16(reg)            readw (ioaddr + (reg))
  98 #define RTL_R32(reg)            readl (ioaddr + (reg))
  99
 100 enum mac_version {
 101         RTL_GIGA_MAC_NONE   = 0x00,
 102         RTL_GIGA_MAC_VER_01 = 0x01, // 8169
 103         RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
 104         RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
 105         RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
 106         RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
 107         RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
 108         RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
 109         RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
 110         RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
 111         RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
 112         RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
 113         RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
 114         RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
 115         RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
 116         RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
 117         RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
 118         RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
 119         RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
 120         RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
 121         RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
 122         RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
 123         RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
 124         RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
 125         RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
 126         RTL_GIGA_MAC_VER_25 = 0x19, // 8168D
 127         RTL_GIGA_MAC_VER_26 = 0x1a, // 8168D
 128         RTL_GIGA_MAC_VER_27 = 0x1b, // 8168DP
 129         RTL_GIGA_MAC_VER_28 = 0x1c, // 8168DP
 130         RTL_GIGA_MAC_VER_29 = 0x1d, // 8105E
 131         RTL_GIGA_MAC_VER_30 = 0x1e, // 8105E
 132         RTL_GIGA_MAC_VER_31 = 0x1f, // 8168DP
 133         RTL_GIGA_MAC_VER_32 = 0x20, // 8168E
 134         RTL_GIGA_MAC_VER_33 = 0x21, // 8168E
 135 };
 136
 137 #define _R(NAME,MAC,MASK) \
 138         { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
 139
 140 static const struct {
 141         const char *name;
 142         u8 mac_version;
 143         u32 RxConfigMask;       /* Clears the bits supported by this chip */
 144 } rtl_chip_info[] = {
 145         _R("RTL8169",           RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
 146         _R("RTL8169s",          RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
 147         _R("RTL8110s",          RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
 148         _R("RTL8169sb/8110sb",  RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
 149         _R("RTL8169sc/8110sc",  RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
 150         _R("RTL8169sc/8110sc",  RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
 151         _R("RTL8102e",          RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
 152         _R("RTL8102e",          RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
 153         _R("RTL8102e",          RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
 154         _R("RTL8101e",          RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
 155         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
 156         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
 157         _R("RTL8101e",          RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
 158         _R("RTL8100e",          RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
 159         _R("RTL8100e",          RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
 160         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
 161         _R("RTL8101e",          RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
 162         _R("RTL8168cp/8111cp",  RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
 163         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
 164         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E
 165         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E
 166         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E
 167         _R("RTL8168cp/8111cp",  RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E
 168         _R("RTL8168cp/8111cp",  RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E
 169         _R("RTL8168d/8111d",    RTL_GIGA_MAC_VER_25, 0xff7e1880), // PCI-E
 170         _R("RTL8168d/8111d",    RTL_GIGA_MAC_VER_26, 0xff7e1880), // PCI-E
 171         _R("RTL8168dp/8111dp",  RTL_GIGA_MAC_VER_27, 0xff7e1880), // PCI-E
 172         _R("RTL8168dp/8111dp",  RTL_GIGA_MAC_VER_28, 0xff7e1880), // PCI-E
 173         _R("RTL8105e",          RTL_GIGA_MAC_VER_29, 0xff7e1880), // PCI-E
 174         _R("RTL8105e",          RTL_GIGA_MAC_VER_30, 0xff7e1880), // PCI-E
 175         _R("RTL8168dp/8111dp",  RTL_GIGA_MAC_VER_31, 0xff7e1880), // PCI-E
 176         _R("RTL8168e/8111e",    RTL_GIGA_MAC_VER_32, 0xff7e1880), // PCI-E
 177         _R("RTL8168e/8111e",    RTL_GIGA_MAC_VER_33, 0xff7e1880)  // PCI-E
 178 };
 179 #undef _R
 180
 181 enum cfg_version {
 182         RTL_CFG_0 = 0x00,
 183         RTL_CFG_1,
 184         RTL_CFG_2
 185 };
 186
 187 static void rtl_hw_start_8169(struct net_device *);
 188 static void rtl_hw_start_8168(struct net_device *);
 189 static void rtl_hw_start_8101(struct net_device *);
 190
 191 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
 192         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 193         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 194         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 195         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 196         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 197         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 198         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
 199         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 200         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 201                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 202         { 0x0001,                               0x8168,
 203                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 204         {0,},
 205 };
 206
 207 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 208
 209 static int rx_buf_sz = 16383;
 210 static int use_dac;
 211 static struct {
 212         u32 msg_enable;
 213 } debug = { -1 };
 214
 215 enum rtl_registers {
 216         MAC0            = 0,    /* Ethernet hardware address. */
 217         MAC4            = 4,
 218         MAR0            = 8,    /* Multicast filter. */
 219         CounterAddrLow          = 0x10,
 220         CounterAddrHigh         = 0x14,
 221         TxDescStartAddrLow      = 0x20,
 222         TxDescStartAddrHigh     = 0x24,
 223         TxHDescStartAddrLow     = 0x28,
 224         TxHDescStartAddrHigh    = 0x2c,
 225         FLASH           = 0x30,
 226         ERSR            = 0x36,
 227         ChipCmd         = 0x37,
 228         TxPoll          = 0x38,
 229         IntrMask        = 0x3c,
 230         IntrStatus      = 0x3e,
 231         TxConfig        = 0x40,
 232         RxConfig        = 0x44,
 233         RxMissed        = 0x4c,
 234         Cfg9346         = 0x50,
 235         Config0         = 0x51,
 236         Config1         = 0x52,
 237         Config2         = 0x53,
 238         Config3         = 0x54,
 239         Config4         = 0x55,
 240         Config5         = 0x56,
 241         MultiIntr       = 0x5c,
 242         PHYAR           = 0x60,
 243         PHYstatus       = 0x6c,
 244         RxMaxSize       = 0xda,
 245         CPlusCmd        = 0xe0,
 246         IntrMitigate    = 0xe2,
 247         RxDescAddrLow   = 0xe4,
 248         RxDescAddrHigh  = 0xe8,
 249         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 250
 251 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 252
 253         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 254
 255 #define TxPacketMax     (8064 >> 7)
 256
 257         FuncEvent       = 0xf0,
 258         FuncEventMask   = 0xf4,
 259         FuncPresetState = 0xf8,
 260         FuncForceEvent  = 0xfc,
 261 };
 262
 263 enum rtl8110_registers {
 264         TBICSR                  = 0x64,
 265         TBI_ANAR                = 0x68,
 266         TBI_LPAR                = 0x6a,
 267 };
 268
 269 enum rtl8168_8101_registers {
 270         CSIDR                   = 0x64,
 271         CSIAR                   = 0x68,
 272 #define CSIAR_FLAG                      0x80000000
 273 #define CSIAR_WRITE_CMD                 0x80000000
 274 #define CSIAR_BYTE_ENABLE               0x0f
 275 #define CSIAR_BYTE_ENABLE_SHIFT         12
 276 #define CSIAR_ADDR_MASK                 0x0fff
 277         PMCH                    = 0x6f,
 278         EPHYAR                  = 0x80,
 279 #define EPHYAR_FLAG                     0x80000000
 280 #define EPHYAR_WRITE_CMD                0x80000000
 281 #define EPHYAR_REG_MASK                 0x1f
 282 #define EPHYAR_REG_SHIFT                16
 283 #define EPHYAR_DATA_MASK                0xffff
 284         DLLPR                   = 0xd0,
 285 #define PM_SWITCH                       (1 << 6)
 286         DBG_REG                 = 0xd1,
 287 #define FIX_NAK_1                       (1 << 4)
 288 #define FIX_NAK_2                       (1 << 3)
 289         TWSI                    = 0xd2,
 290         MCU                     = 0xd3,
 291 #define EN_NDP                          (1 << 3)
 292 #define EN_OOB_RESET                    (1 << 2)
 293         EFUSEAR                 = 0xdc,
 294 #define EFUSEAR_FLAG                    0x80000000
 295 #define EFUSEAR_WRITE_CMD               0x80000000
 296 #define EFUSEAR_READ_CMD                0x00000000
 297 #define EFUSEAR_REG_MASK                0x03ff
 298 #define EFUSEAR_REG_SHIFT               8
 299 #define EFUSEAR_DATA_MASK               0xff
 300 };
 301
 302 enum rtl8168_registers {
 303         ERIDR                   = 0x70,
 304         ERIAR                   = 0x74,
 305 #define ERIAR_FLAG                      0x80000000
 306 #define ERIAR_WRITE_CMD                 0x80000000
 307 #define ERIAR_READ_CMD                  0x00000000
 308 #define ERIAR_ADDR_BYTE_ALIGN           4
 309 #define ERIAR_EXGMAC                    0
 310 #define ERIAR_MSIX                      1
 311 #define ERIAR_ASF                       2
 312 #define ERIAR_TYPE_SHIFT                16
 313 #define ERIAR_BYTEEN                    0x0f
 314 #define ERIAR_BYTEEN_SHIFT              12
 315         EPHY_RXER_NUM           = 0x7c,
 316         OCPDR                   = 0xb0, /* OCP GPHY access */
 317 #define OCPDR_WRITE_CMD                 0x80000000
 318 #define OCPDR_READ_CMD                  0x00000000
 319 #define OCPDR_REG_MASK                  0x7f
 320 #define OCPDR_GPHY_REG_SHIFT            16
 321 #define OCPDR_DATA_MASK                 0xffff
 322         OCPAR                   = 0xb4,
 323 #define OCPAR_FLAG                      0x80000000
 324 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 325 #define OCPAR_GPHY_READ_CMD             0x0000f060
 326         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 327         MISC                    = 0xf0, /* 8168e only. */
 328         txpla_rst                       = (1 << 29)
 329 };
 330
 331 enum rtl_register_content {
 332         /* InterruptStatusBits */
 333         SYSErr          = 0x8000,
 334         PCSTimeout      = 0x4000,
 335         SWInt           = 0x0100,
 336         TxDescUnavail   = 0x0080,
 337         RxFIFOOver      = 0x0040,
 338         LinkChg         = 0x0020,
 339         RxOverflow      = 0x0010,
 340         TxErr           = 0x0008,
 341         TxOK            = 0x0004,
 342         RxErr           = 0x0002,
 343         RxOK            = 0x0001,
 344
 345         /* RxStatusDesc */
 346         RxFOVF  = (1 << 23),
 347         RxRWT   = (1 << 22),
 348         RxRES   = (1 << 21),
 349         RxRUNT  = (1 << 20),
 350         RxCRC   = (1 << 19),
 351
 352         /* ChipCmdBits */
 353         CmdReset        = 0x10,
 354         CmdRxEnb        = 0x08,
 355         CmdTxEnb        = 0x04,
 356         RxBufEmpty      = 0x01,
 357
 358         /* TXPoll register p.5 */
 359         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 360         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 361         FSWInt          = 0x01,         /* Forced software interrupt */
 362
 363         /* Cfg9346Bits */
 364         Cfg9346_Lock    = 0x00,
 365         Cfg9346_Unlock  = 0xc0,
 366
 367         /* rx_mode_bits */
 368         AcceptErr       = 0x20,
 369         AcceptRunt      = 0x10,
 370         AcceptBroadcast = 0x08,
 371         AcceptMulticast = 0x04,
 372         AcceptMyPhys    = 0x02,
 373         AcceptAllPhys   = 0x01,
 374
 375         /* RxConfigBits */
 376         RxCfgFIFOShift  = 13,
 377         RxCfgDMAShift   =  8,
 378
 379         /* TxConfigBits */
 380         TxInterFrameGapShift = 24,
 381         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 382
 383         /* Config1 register p.24 */
 384         LEDS1           = (1 << 7),
 385         LEDS0           = (1 << 6),
 386         MSIEnable       = (1 << 5),     /* Enable Message Signaled Interrupt */
 387         Speed_down      = (1 << 4),
 388         MEMMAP          = (1 << 3),
 389         IOMAP           = (1 << 2),
 390         VPD             = (1 << 1),
 391         PMEnable        = (1 << 0),     /* Power Management Enable */
 392
 393         /* Config2 register p. 25 */
 394         PCI_Clock_66MHz = 0x01,
 395         PCI_Clock_33MHz = 0x00,
 396
 397         /* Config3 register p.25 */
 398         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 399         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 400         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 401
 402         /* Config5 register p.27 */
 403         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 404         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 405         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 406         spi_en          = (1 << 3),
 407         LanWake         = (1 << 1),     /* LanWake enable/disable */
 408         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 409
 410         /* TBICSR p.28 */
 411         TBIReset        = 0x80000000,
 412         TBILoopback     = 0x40000000,
 413         TBINwEnable     = 0x20000000,
 414         TBINwRestart    = 0x10000000,
 415         TBILinkOk       = 0x02000000,
 416         TBINwComplete   = 0x01000000,
 417
 418         /* CPlusCmd p.31 */
 419         EnableBist      = (1 << 15),    // 8168 8101
 420         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 421         Normal_mode     = (1 << 13),    // unused
 422         Force_half_dup  = (1 << 12),    // 8168 8101
 423         Force_rxflow_en = (1 << 11),    // 8168 8101
 424         Force_txflow_en = (1 << 10),    // 8168 8101
 425         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 426         ASF             = (1 << 8),     // 8168 8101
 427         PktCntrDisable  = (1 << 7),     // 8168 8101
 428         Mac_dbgo_sel    = 0x001c,       // 8168
 429         RxVlan          = (1 << 6),
 430         RxChkSum        = (1 << 5),
 431         PCIDAC          = (1 << 4),
 432         PCIMulRW        = (1 << 3),
 433         INTT_0          = 0x0000,       // 8168
 434         INTT_1          = 0x0001,       // 8168
 435         INTT_2          = 0x0002,       // 8168
 436         INTT_3          = 0x0003,       // 8168
 437
 438         /* rtl8169_PHYstatus */
 439         TBI_Enable      = 0x80,
 440         TxFlowCtrl      = 0x40,
 441         RxFlowCtrl      = 0x20,
 442         _1000bpsF       = 0x10,
 443         _100bps         = 0x08,
 444         _10bps          = 0x04,
 445         LinkStatus      = 0x02,
 446         FullDup         = 0x01,
 447
 448         /* _TBICSRBit */
 449         TBILinkOK       = 0x02000000,
 450
 451         /* DumpCounterCommand */
 452         CounterDump     = 0x8,
 453 };
 454
 455 enum desc_status_bit {
 456         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 457         RingEnd         = (1 << 30), /* End of descriptor ring */
 458         FirstFrag       = (1 << 29), /* First segment of a packet */
 459         LastFrag        = (1 << 28), /* Final segment of a packet */
 460
 461         /* Tx private */
 462         LargeSend       = (1 << 27), /* TCP Large Send Offload (TSO) */
 463         MSSShift        = 16,        /* MSS value position */
 464         MSSMask         = 0xfff,     /* MSS value + LargeSend bit: 12 bits */
 465         IPCS            = (1 << 18), /* Calculate IP checksum */
 466         UDPCS           = (1 << 17), /* Calculate UDP/IP checksum */
 467         TCPCS           = (1 << 16), /* Calculate TCP/IP checksum */
 468         TxVlanTag       = (1 << 17), /* Add VLAN tag */
 469
 470         /* Rx private */
 471         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 472         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
 473
 474 #define RxProtoUDP      (PID1)
 475 #define RxProtoTCP      (PID0)
 476 #define RxProtoIP       (PID1 | PID0)
 477 #define RxProtoMask     RxProtoIP
 478
 479         IPFail          = (1 << 16), /* IP checksum failed */
 480         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 481         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 482         RxVlanTag       = (1 << 16), /* VLAN tag available */
 483 };
 484
 485 #define RsvdMask        0x3fffc000
 486
 487 struct TxDesc {
 488         __le32 opts1;
 489         __le32 opts2;
 490         __le64 addr;
 491 };
 492
 493 struct RxDesc {
 494         __le32 opts1;
 495         __le32 opts2;
 496         __le64 addr;
 497 };
 498
 499 struct ring_info {
 500         struct sk_buff  *skb;
 501         u32             len;
 502         u8              __pad[sizeof(void *) - sizeof(u32)];
 503 };
 504
 505 enum features {
 506         RTL_FEATURE_WOL         = (1 << 0),
 507         RTL_FEATURE_MSI         = (1 << 1),
 508         RTL_FEATURE_GMII        = (1 << 2),
 509 };
 510
 511 struct rtl8169_counters {
 512         __le64  tx_packets;
 513         __le64  rx_packets;
 514         __le64  tx_errors;
 515         __le32  rx_errors;
 516         __le16  rx_missed;
 517         __le16  align_errors;
 518         __le32  tx_one_collision;
 519         __le32  tx_multi_collision;
 520         __le64  rx_unicast;
 521         __le64  rx_broadcast;
 522         __le32  rx_multicast;
 523         __le16  tx_aborted;
 524         __le16  tx_underun;
 525 };
 526
 527 struct rtl8169_private {
 528         void __iomem *mmio_addr;        /* memory map physical address */
 529         struct pci_dev *pci_dev;        /* Index of PCI device */
 530         struct net_device *dev;
 531         struct napi_struct napi;
 532         spinlock_t lock;                /* spin lock flag */
 533         u32 msg_enable;
 534         int chipset;
 535         int mac_version;
 536         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 537         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 538         u32 dirty_rx;
 539         u32 dirty_tx;
 540         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 541         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 542         dma_addr_t TxPhyAddr;
 543         dma_addr_t RxPhyAddr;
 544         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 545         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 546         struct timer_list timer;
 547         u16 cp_cmd;
 548         u16 intr_event;
 549         u16 napi_event;
 550         u16 intr_mask;
 551         int phy_1000_ctrl_reg;
 552
 553         struct mdio_ops {
 554                 void (*write)(void __iomem *, int, int);
 555                 int (*read)(void __iomem *, int);
 556         } mdio_ops;
 557
 558         struct pll_power_ops {
 559                 void (*down)(struct rtl8169_private *);
 560                 void (*up)(struct rtl8169_private *);
 561         } pll_power_ops;
 562
 563         int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
 564         int (*get_settings)(struct net_device *, struct ethtool_cmd *);
 565         void (*phy_reset_enable)(struct rtl8169_private *tp);
 566         void (*hw_start)(struct net_device *);
 567         unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
 568         unsigned int (*link_ok)(void __iomem *);
 569         int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
 570         int pcie_cap;
 571         struct delayed_work task;
 572         unsigned features;
 573
 574         struct mii_if_info mii;
 575         struct rtl8169_counters counters;
 576         u32 saved_wolopts;
 577
 578         const struct firmware *fw;
 579 };
 580
 581 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 582 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 583 module_param(use_dac, int, 0);
 584 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 585 module_param_named(debug, debug.msg_enable, int, 0);
 586 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 587 MODULE_LICENSE("GPL");
 588 MODULE_VERSION(RTL8169_VERSION);
 589 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 590 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 591 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 592 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 593 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 594
 595 static int rtl8169_open(struct net_device *dev);
 596 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
 597                                       struct net_device *dev);
 598 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
 599 static int rtl8169_init_ring(struct net_device *dev);
 600 static void rtl_hw_start(struct net_device *dev);
 601 static int rtl8169_close(struct net_device *dev);
 602 static void rtl_set_rx_mode(struct net_device *dev);
 603 static void rtl8169_tx_timeout(struct net_device *dev);
 604 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
 605 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
 606                                 void __iomem *, u32 budget);
 607 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
 608 static void rtl8169_down(struct net_device *dev);
 609 static void rtl8169_rx_clear(struct rtl8169_private *tp);
 610 static int rtl8169_poll(struct napi_struct *napi, int budget);
 611
 612 static const unsigned int rtl8169_rx_config =
 613         (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
 614
 615 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
 616 {
 617         void __iomem *ioaddr = tp->mmio_addr;
 618         int i;
 619
 620         RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 621         for (i = 0; i < 20; i++) {
 622                 udelay(100);
 623                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
 624                         break;
 625         }
 626         return RTL_R32(OCPDR);
 627 }
 628
 629 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
 630 {
 631         void __iomem *ioaddr = tp->mmio_addr;
 632         int i;
 633
 634         RTL_W32(OCPDR, data);
 635         RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 636         for (i = 0; i < 20; i++) {
 637                 udelay(100);
 638                 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
 639                         break;
 640         }
 641 }
 642
 643 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
 644 {
 645         void __iomem *ioaddr = tp->mmio_addr;
 646         int i;
 647
 648         RTL_W8(ERIDR, cmd);
 649         RTL_W32(ERIAR, 0x800010e8);
 650         msleep(2);
 651         for (i = 0; i < 5; i++) {
 652                 udelay(100);
 653                 if (!(RTL_R32(ERIDR) & ERIAR_FLAG))
 654                         break;
 655         }
 656
 657         ocp_write(tp, 0x1, 0x30, 0x00000001);
 658 }
 659
 660 #define OOB_CMD_RESET           0x00
 661 #define OOB_CMD_DRIVER_START    0x05
 662 #define OOB_CMD_DRIVER_STOP     0x06
 663
 664 static void rtl8168_driver_start(struct rtl8169_private *tp)
 665 {
 666         int i;
 667         u32 reg;
 668
 669         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
 670
 671         if (tp->mac_version == RTL_GIGA_MAC_VER_31)
 672                 reg = 0xb8;
 673         else
 674                 reg = 0x10;
 675
 676         for (i = 0; i < 10; i++) {
 677                 msleep(10);
 678                 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
 679                         break;
 680         }
 681 }
 682
 683 static void rtl8168_driver_stop(struct rtl8169_private *tp)
 684 {
 685         int i;
 686         u32 reg;
 687
 688         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
 689
 690         if (tp->mac_version == RTL_GIGA_MAC_VER_31)
 691                 reg = 0xb8;
 692         else
 693                 reg = 0x10;
 694
 695         for (i = 0; i < 10; i++) {
 696                 msleep(10);
 697                 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
 698                         break;
 699         }
 700 }
 701
 702 static int r8168dp_check_dash(struct rtl8169_private *tp)
 703 {
 704         u32 reg;
 705
 706         if (tp->mac_version == RTL_GIGA_MAC_VER_31)
 707                 reg = 0xb8;
 708         else
 709                 reg = 0x10;
 710
 711         if (ocp_read(tp, 0xF, reg) & 0x00008000)
 712                 return 1;
 713         else
 714                 return 0;
 715 }
 716
 717 static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 718 {
 719         int i;
 720
 721         RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
 722
 723         for (i = 20; i > 0; i--) {
 724                 /*
 725                  * Check if the RTL8169 has completed writing to the specified
 726                  * MII register.
 727                  */
 728                 if (!(RTL_R32(PHYAR) & 0x80000000))
 729                         break;
 730                 udelay(25);
 731         }
 732         /*
 733          * According to hardware specs a 20us delay is required after write
 734          * complete indication, but before sending next command.
 735          */
 736         udelay(20);
 737 }
 738
 739 static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
 740 {
 741         int i, value = -1;
 742
 743         RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
 744
 745         for (i = 20; i > 0; i--) {
 746                 /*
 747                  * Check if the RTL8169 has completed retrieving data from
 748                  * the specified MII register.
 749                  */
 750                 if (RTL_R32(PHYAR) & 0x80000000) {
 751                         value = RTL_R32(PHYAR) & 0xffff;
 752                         break;
 753                 }
 754                 udelay(25);
 755         }
 756         /*
 757          * According to hardware specs a 20us delay is required after read
 758          * complete indication, but before sending next command.
 759          */
 760         udelay(20);
 761
 762         return value;
 763 }
 764
 765 static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
 766 {
 767         int i;
 768
 769         RTL_W32(OCPDR, data |
 770                 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
 771         RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
 772         RTL_W32(EPHY_RXER_NUM, 0);
 773
 774         for (i = 0; i < 100; i++) {
 775                 mdelay(1);
 776                 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
 777                         break;
 778         }
 779 }
 780
 781 static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 782 {
 783         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
 784                 (value & OCPDR_DATA_MASK));
 785 }
 786
 787 static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
 788 {
 789         int i;
 790
 791         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
 792
 793         mdelay(1);
 794         RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
 795         RTL_W32(EPHY_RXER_NUM, 0);
 796
 797         for (i = 0; i < 100; i++) {
 798                 mdelay(1);
 799                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
 800                         break;
 801         }
 802
 803         return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
 804 }
 805
 806 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
 807
 808 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
 809 {
 810         RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
 811 }
 812
 813 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
 814 {
 815         RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
 816 }
 817
 818 static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 819 {
 820         r8168dp_2_mdio_start(ioaddr);
 821
 822         r8169_mdio_write(ioaddr, reg_addr, value);
 823
 824         r8168dp_2_mdio_stop(ioaddr);
 825 }
 826
 827 static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
 828 {
 829         int value;
 830
 831         r8168dp_2_mdio_start(ioaddr);
 832
 833         value = r8169_mdio_read(ioaddr, reg_addr);
 834
 835         r8168dp_2_mdio_stop(ioaddr);
 836
 837         return value;
 838 }
 839
 840 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
 841 {
 842         tp->mdio_ops.write(tp->mmio_addr, location, val);
 843 }
 844
 845 static int rtl_readphy(struct rtl8169_private *tp, int location)
 846 {
 847         return tp->mdio_ops.read(tp->mmio_addr, location);
 848 }
 849
 850 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
 851 {
 852         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
 853 }
 854
 855 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
 856 {
 857         int val;
 858
 859         val = rtl_readphy(tp, reg_addr);
 860         rtl_writephy(tp, reg_addr, (val | p) & ~m);
 861 }
 862
 863 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
 864                            int val)
 865 {
 866         struct rtl8169_private *tp = netdev_priv(dev);
 867
 868         rtl_writephy(tp, location, val);
 869 }
 870
 871 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
 872 {
 873         struct rtl8169_private *tp = netdev_priv(dev);
 874
 875         return rtl_readphy(tp, location);
 876 }
 877
 878 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
 879 {
 880         unsigned int i;
 881
 882         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
 883                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
 884
 885         for (i = 0; i < 100; i++) {
 886                 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
 887                         break;
 888                 udelay(10);
 889         }
 890 }
 891
 892 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
 893 {
 894         u16 value = 0xffff;
 895         unsigned int i;
 896
 897         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
 898
 899         for (i = 0; i < 100; i++) {
 900                 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
 901                         value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
 902                         break;
 903                 }
 904                 udelay(10);
 905         }
 906
 907         return value;
 908 }
 909
 910 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
 911 {
 912         unsigned int i;
 913
 914         RTL_W32(CSIDR, value);
 915         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
 916                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
 917
 918         for (i = 0; i < 100; i++) {
 919                 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
 920                         break;
 921                 udelay(10);
 922         }
 923 }
 924
 925 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
 926 {
 927         u32 value = ~0x00;
 928         unsigned int i;
 929
 930         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
 931                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
 932
 933         for (i = 0; i < 100; i++) {
 934                 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
 935                         value = RTL_R32(CSIDR);
 936                         break;
 937                 }
 938                 udelay(10);
 939         }
 940
 941         return value;
 942 }
 943
 944 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
 945 {
 946         u8 value = 0xff;
 947         unsigned int i;
 948
 949         RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
 950
 951         for (i = 0; i < 300; i++) {
 952                 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
 953                         value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
 954                         break;
 955                 }
 956                 udelay(100);
 957         }
 958
 959         return value;
 960 }
 961
 962 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
 963 {
 964         RTL_W16(IntrMask, 0x0000);
 965
 966         RTL_W16(IntrStatus, 0xffff);
 967 }
 968
 969 static void rtl8169_asic_down(void __iomem *ioaddr)
 970 {
 971         RTL_W8(ChipCmd, 0x00);
 972         rtl8169_irq_mask_and_ack(ioaddr);
 973         RTL_R16(CPlusCmd);
 974 }
 975
 976 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
 977 {
 978         void __iomem *ioaddr = tp->mmio_addr;
 979
 980         return RTL_R32(TBICSR) & TBIReset;
 981 }
 982
 983 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
 984 {
 985         return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
 986 }
 987
 988 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
 989 {
 990         return RTL_R32(TBICSR) & TBILinkOk;
 991 }
 992
 993 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
 994 {
 995         return RTL_R8(PHYstatus) & LinkStatus;
 996 }
 997
 998 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
 999 {
1000         void __iomem *ioaddr = tp->mmio_addr;
1001
1002         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1003 }
1004
1005 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1006 {
1007         unsigned int val;
1008
1009         val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1010         rtl_writephy(tp, MII_BMCR, val & 0xffff);
1011 }
1012
1013 static void __rtl8169_check_link_status(struct net_device *dev,
1014                                       struct rtl8169_private *tp,
1015                                       void __iomem *ioaddr,
1016                                       bool pm)
1017 {
1018         unsigned long flags;
1019
1020         spin_lock_irqsave(&tp->lock, flags);
1021         if (tp->link_ok(ioaddr)) {
1022                 /* This is to cancel a scheduled suspend if there's one. */
1023                 if (pm)
1024                         pm_request_resume(&tp->pci_dev->dev);
1025                 netif_carrier_on(dev);
1026                 if (net_ratelimit())
1027                         netif_info(tp, ifup, dev, "link up\n");
1028         } else {
1029                 netif_carrier_off(dev);
1030                 netif_info(tp, ifdown, dev, "link down\n");
1031                 if (pm)
1032                         pm_schedule_suspend(&tp->pci_dev->dev, 100);
1033         }
1034         spin_unlock_irqrestore(&tp->lock, flags);
1035 }
1036
1037 static void rtl8169_check_link_status(struct net_device *dev,
1038                                       struct rtl8169_private *tp,
1039                                       void __iomem *ioaddr)
1040 {
1041         __rtl8169_check_link_status(dev, tp, ioaddr, false);
1042 }
1043
1044 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1045
1046 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1047 {
1048         void __iomem *ioaddr = tp->mmio_addr;
1049         u8 options;
1050         u32 wolopts = 0;
1051
1052         options = RTL_R8(Config1);
1053         if (!(options & PMEnable))
1054                 return 0;
1055
1056         options = RTL_R8(Config3);
1057         if (options & LinkUp)
1058                 wolopts |= WAKE_PHY;
1059         if (options & MagicPacket)
1060                 wolopts |= WAKE_MAGIC;
1061
1062         options = RTL_R8(Config5);
1063         if (options & UWF)
1064                 wolopts |= WAKE_UCAST;
1065         if (options & BWF)
1066                 wolopts |= WAKE_BCAST;
1067         if (options & MWF)
1068                 wolopts |= WAKE_MCAST;
1069
1070         return wolopts;
1071 }
1072
1073 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1074 {
1075         struct rtl8169_private *tp = netdev_priv(dev);
1076
1077         spin_lock_irq(&tp->lock);
1078
1079         wol->supported = WAKE_ANY;
1080         wol->wolopts = __rtl8169_get_wol(tp);
1081
1082         spin_unlock_irq(&tp->lock);
1083 }
1084
1085 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1086 {
1087         void __iomem *ioaddr = tp->mmio_addr;
1088         unsigned int i;
1089         static const struct {
1090                 u32 opt;
1091                 u16 reg;
1092                 u8  mask;
1093         } cfg[] = {
1094                 { WAKE_ANY,   Config1, PMEnable },
1095                 { WAKE_PHY,   Config3, LinkUp },
1096                 { WAKE_MAGIC, Config3, MagicPacket },
1097                 { WAKE_UCAST, Config5, UWF },
1098                 { WAKE_BCAST, Config5, BWF },
1099                 { WAKE_MCAST, Config5, MWF },
1100                 { WAKE_ANY,   Config5, LanWake }
1101         };
1102
1103         RTL_W8(Cfg9346, Cfg9346_Unlock);
1104
1105         for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1106                 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1107                 if (wolopts & cfg[i].opt)
1108                         options |= cfg[i].mask;
1109                 RTL_W8(cfg[i].reg, options);
1110         }
1111
1112         RTL_W8(Cfg9346, Cfg9346_Lock);
1113 }
1114
1115 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1116 {
1117         struct rtl8169_private *tp = netdev_priv(dev);
1118
1119         spin_lock_irq(&tp->lock);
1120
1121         if (wol->wolopts)
1122                 tp->features |= RTL_FEATURE_WOL;
1123         else
1124                 tp->features &= ~RTL_FEATURE_WOL;
1125         __rtl8169_set_wol(tp, wol->wolopts);
1126         spin_unlock_irq(&tp->lock);
1127
1128         device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1129
1130         return 0;
1131 }
1132
1133 static void rtl8169_get_drvinfo(struct net_device *dev,
1134                                 struct ethtool_drvinfo *info)
1135 {
1136         struct rtl8169_private *tp = netdev_priv(dev);
1137
1138         strcpy(info->driver, MODULENAME);
1139         strcpy(info->version, RTL8169_VERSION);
1140         strcpy(info->bus_info, pci_name(tp->pci_dev));
1141 }
1142
1143 static int rtl8169_get_regs_len(struct net_device *dev)
1144 {
1145         return R8169_REGS_SIZE;
1146 }
1147
1148 static int rtl8169_set_speed_tbi(struct net_device *dev,
1149                                  u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1150 {
1151         struct rtl8169_private *tp = netdev_priv(dev);
1152         void __iomem *ioaddr = tp->mmio_addr;
1153         int ret = 0;
1154         u32 reg;
1155
1156         reg = RTL_R32(TBICSR);
1157         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1158             (duplex == DUPLEX_FULL)) {
1159                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1160         } else if (autoneg == AUTONEG_ENABLE)
1161                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1162         else {
1163                 netif_warn(tp, link, dev,
1164                            "incorrect speed setting refused in TBI mode\n");
1165                 ret = -EOPNOTSUPP;
1166         }
1167
1168         return ret;
1169 }
1170
1171 static int rtl8169_set_speed_xmii(struct net_device *dev,
1172                                   u8 autoneg, u16 speed, u8 duplex, u32 adv)
1173 {
1174         struct rtl8169_private *tp = netdev_priv(dev);
1175         int giga_ctrl, bmcr;
1176         int rc = -EINVAL;
1177
1178         rtl_writephy(tp, 0x1f, 0x0000);
1179
1180         if (autoneg == AUTONEG_ENABLE) {
1181                 int auto_nego;
1182
1183                 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1184                 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1185                                 ADVERTISE_100HALF | ADVERTISE_100FULL);
1186
1187                 if (adv & ADVERTISED_10baseT_Half)
1188                         auto_nego |= ADVERTISE_10HALF;
1189                 if (adv & ADVERTISED_10baseT_Full)
1190                         auto_nego |= ADVERTISE_10FULL;
1191                 if (adv & ADVERTISED_100baseT_Half)
1192                         auto_nego |= ADVERTISE_100HALF;
1193                 if (adv & ADVERTISED_100baseT_Full)
1194                         auto_nego |= ADVERTISE_100FULL;
1195
1196                 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1197
1198                 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1199                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1200
1201                 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1202                 if ((tp->mac_version != RTL_GIGA_MAC_VER_07) &&
1203                     (tp->mac_version != RTL_GIGA_MAC_VER_08) &&
1204                     (tp->mac_version != RTL_GIGA_MAC_VER_09) &&
1205                     (tp->mac_version != RTL_GIGA_MAC_VER_10) &&
1206                     (tp->mac_version != RTL_GIGA_MAC_VER_13) &&
1207                     (tp->mac_version != RTL_GIGA_MAC_VER_14) &&
1208                     (tp->mac_version != RTL_GIGA_MAC_VER_15) &&
1209                     (tp->mac_version != RTL_GIGA_MAC_VER_16) &&
1210                     (tp->mac_version != RTL_GIGA_MAC_VER_29) &&
1211                     (tp->mac_version != RTL_GIGA_MAC_VER_30)) {
1212                         if (adv & ADVERTISED_1000baseT_Half)
1213                                 giga_ctrl |= ADVERTISE_1000HALF;
1214                         if (adv & ADVERTISED_1000baseT_Full)
1215                                 giga_ctrl |= ADVERTISE_1000FULL;
1216                 } else if (adv & (ADVERTISED_1000baseT_Half |
1217                                   ADVERTISED_1000baseT_Full)) {
1218                         netif_info(tp, link, dev,
1219                                    "PHY does not support 1000Mbps\n");
1220                         goto out;
1221                 }
1222
1223                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1224
1225                 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1226                 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1227         } else {
1228                 giga_ctrl = 0;
1229
1230                 if (speed == SPEED_10)
1231                         bmcr = 0;
1232                 else if (speed == SPEED_100)
1233                         bmcr = BMCR_SPEED100;
1234                 else
1235                         goto out;
1236
1237                 if (duplex == DUPLEX_FULL)
1238                         bmcr |= BMCR_FULLDPLX;
1239         }
1240
1241         tp->phy_1000_ctrl_reg = giga_ctrl;
1242
1243         rtl_writephy(tp, MII_BMCR, bmcr);
1244
1245         if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1246             (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
1247                 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1248                         rtl_writephy(tp, 0x17, 0x2138);
1249                         rtl_writephy(tp, 0x0e, 0x0260);
1250                 } else {
1251                         rtl_writephy(tp, 0x17, 0x2108);
1252                         rtl_writephy(tp, 0x0e, 0x0000);
1253                 }
1254         }
1255
1256         rc = 0;
1257 out:
1258         return rc;
1259 }
1260
1261 static int rtl8169_set_speed(struct net_device *dev,
1262                              u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1263 {
1264         struct rtl8169_private *tp = netdev_priv(dev);
1265         int ret;
1266
1267         ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1268
1269         if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1270                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1271
1272         return ret;
1273 }
1274
1275 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1276 {
1277         struct rtl8169_private *tp = netdev_priv(dev);
1278         unsigned long flags;
1279         int ret;
1280
1281         spin_lock_irqsave(&tp->lock, flags);
1282         ret = rtl8169_set_speed(dev,
1283                 cmd->autoneg, cmd->speed, cmd->duplex, cmd->advertising);
1284         spin_unlock_irqrestore(&tp->lock, flags);
1285
1286         return ret;
1287 }
1288
1289 static u32 rtl8169_fix_features(struct net_device *dev, u32 features)
1290 {
1291         if (dev->mtu > MSSMask)
1292                 features &= ~NETIF_F_ALL_TSO;
1293
1294         return features;
1295 }
1296
1297 static int rtl8169_set_features(struct net_device *dev, u32 features)
1298 {
1299         struct rtl8169_private *tp = netdev_priv(dev);
1300         void __iomem *ioaddr = tp->mmio_addr;
1301         unsigned long flags;
1302
1303         spin_lock_irqsave(&tp->lock, flags);
1304
1305         if (features & NETIF_F_RXCSUM)
1306                 tp->cp_cmd |= RxChkSum;
1307         else
1308                 tp->cp_cmd &= ~RxChkSum;
1309
1310         if (dev->features & NETIF_F_HW_VLAN_RX)
1311                 tp->cp_cmd |= RxVlan;
1312         else
1313                 tp->cp_cmd &= ~RxVlan;
1314
1315         RTL_W16(CPlusCmd, tp->cp_cmd);
1316         RTL_R16(CPlusCmd);
1317
1318         spin_unlock_irqrestore(&tp->lock, flags);
1319
1320         return 0;
1321 }
1322
1323 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1324                                       struct sk_buff *skb)
1325 {
1326         return (vlan_tx_tag_present(skb)) ?
1327                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1328 }
1329
1330 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1331 {
1332         u32 opts2 = le32_to_cpu(desc->opts2);
1333
1334         if (opts2 & RxVlanTag)
1335                 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
1336
1337         desc->opts2 = 0;
1338 }
1339
1340 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1341 {
1342         struct rtl8169_private *tp = netdev_priv(dev);
1343         void __iomem *ioaddr = tp->mmio_addr;
1344         u32 status;
1345
1346         cmd->supported =
1347                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1348         cmd->port = PORT_FIBRE;
1349         cmd->transceiver = XCVR_INTERNAL;
1350
1351         status = RTL_R32(TBICSR);
1352         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
1353         cmd->autoneg = !!(status & TBINwEnable);
1354
1355         cmd->speed = SPEED_1000;
1356         cmd->duplex = DUPLEX_FULL; /* Always set */
1357
1358         return 0;
1359 }
1360
1361 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1362 {
1363         struct rtl8169_private *tp = netdev_priv(dev);
1364
1365         return mii_ethtool_gset(&tp->mii, cmd);
1366 }
1367
1368 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1369 {
1370         struct rtl8169_private *tp = netdev_priv(dev);
1371         unsigned long flags;
1372         int rc;
1373
1374         spin_lock_irqsave(&tp->lock, flags);
1375
1376         rc = tp->get_settings(dev, cmd);
1377
1378         spin_unlock_irqrestore(&tp->lock, flags);
1379         return rc;
1380 }
1381
1382 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1383                              void *p)
1384 {
1385         struct rtl8169_private *tp = netdev_priv(dev);
1386         unsigned long flags;
1387
1388         if (regs->len > R8169_REGS_SIZE)
1389                 regs->len = R8169_REGS_SIZE;
1390
1391         spin_lock_irqsave(&tp->lock, flags);
1392         memcpy_fromio(p, tp->mmio_addr, regs->len);
1393         spin_unlock_irqrestore(&tp->lock, flags);
1394 }
1395
1396 static u32 rtl8169_get_msglevel(struct net_device *dev)
1397 {
1398         struct rtl8169_private *tp = netdev_priv(dev);
1399
1400         return tp->msg_enable;
1401 }
1402
1403 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1404 {
1405         struct rtl8169_private *tp = netdev_priv(dev);
1406
1407         tp->msg_enable = value;
1408 }
1409
1410 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1411         "tx_packets",
1412         "rx_packets",
1413         "tx_errors",
1414         "rx_errors",
1415         "rx_missed",
1416         "align_errors",
1417         "tx_single_collisions",
1418         "tx_multi_collisions",
1419         "unicast",
1420         "broadcast",
1421         "multicast",
1422         "tx_aborted",
1423         "tx_underrun",
1424 };
1425
1426 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1427 {
1428         switch (sset) {
1429         case ETH_SS_STATS:
1430                 return ARRAY_SIZE(rtl8169_gstrings);
1431         default:
1432                 return -EOPNOTSUPP;
1433         }
1434 }
1435
1436 static void rtl8169_update_counters(struct net_device *dev)
1437 {
1438         struct rtl8169_private *tp = netdev_priv(dev);
1439         void __iomem *ioaddr = tp->mmio_addr;
1440         struct rtl8169_counters *counters;
1441         dma_addr_t paddr;
1442         u32 cmd;
1443         int wait = 1000;
1444         struct device *d = &tp->pci_dev->dev;
1445
1446         /*
1447          * Some chips are unable to dump tally counters when the receiver
1448          * is disabled.
1449          */
1450         if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1451                 return;
1452
1453         counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1454         if (!counters)
1455                 return;
1456
1457         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1458         cmd = (u64)paddr & DMA_BIT_MASK(32);
1459         RTL_W32(CounterAddrLow, cmd);
1460         RTL_W32(CounterAddrLow, cmd | CounterDump);
1461
1462         while (wait--) {
1463                 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1464                         /* copy updated counters */
1465                         memcpy(&tp->counters, counters, sizeof(*counters));
1466                         break;
1467                 }
1468                 udelay(10);
1469         }
1470
1471         RTL_W32(CounterAddrLow, 0);
1472         RTL_W32(CounterAddrHigh, 0);
1473
1474         dma_free_coherent(d, sizeof(*counters), counters, paddr);
1475 }
1476
1477 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1478                                       struct ethtool_stats *stats, u64 *data)
1479 {
1480         struct rtl8169_private *tp = netdev_priv(dev);
1481
1482         ASSERT_RTNL();
1483
1484         rtl8169_update_counters(dev);
1485
1486         data[0] = le64_to_cpu(tp->counters.tx_packets);
1487         data[1] = le64_to_cpu(tp->counters.rx_packets);
1488         data[2] = le64_to_cpu(tp->counters.tx_errors);
1489         data[3] = le32_to_cpu(tp->counters.rx_errors);
1490         data[4] = le16_to_cpu(tp->counters.rx_missed);
1491         data[5] = le16_to_cpu(tp->counters.align_errors);
1492         data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1493         data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1494         data[8] = le64_to_cpu(tp->counters.rx_unicast);
1495         data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1496         data[10] = le32_to_cpu(tp->counters.rx_multicast);
1497         data[11] = le16_to_cpu(tp->counters.tx_aborted);
1498         data[12] = le16_to_cpu(tp->counters.tx_underun);
1499 }
1500
1501 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1502 {
1503         switch(stringset) {
1504         case ETH_SS_STATS:
1505                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1506                 break;
1507         }
1508 }
1509
1510 static const struct ethtool_ops rtl8169_ethtool_ops = {
1511         .get_drvinfo            = rtl8169_get_drvinfo,
1512         .get_regs_len           = rtl8169_get_regs_len,
1513         .get_link               = ethtool_op_get_link,
1514         .get_settings           = rtl8169_get_settings,
1515         .set_settings           = rtl8169_set_settings,
1516         .get_msglevel           = rtl8169_get_msglevel,
1517         .set_msglevel           = rtl8169_set_msglevel,
1518         .get_regs               = rtl8169_get_regs,
1519         .get_wol                = rtl8169_get_wol,
1520         .set_wol                = rtl8169_set_wol,
1521         .get_strings            = rtl8169_get_strings,
1522         .get_sset_count         = rtl8169_get_sset_count,
1523         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1524 };
1525
1526 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1527                                     void __iomem *ioaddr)
1528 {
1529         /*
1530          * The driver currently handles the 8168Bf and the 8168Be identically
1531          * but they can be identified more specifically through the test below
1532          * if needed:
1533          *
1534          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1535          *
1536          * Same thing for the 8101Eb and the 8101Ec:
1537          *
1538          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1539          */
1540         static const struct {
1541                 u32 mask;
1542                 u32 val;
1543                 int mac_version;
1544         } mac_info[] = {
1545                 /* 8168E family. */
1546                 { 0x7cf00000, 0x2c200000,       RTL_GIGA_MAC_VER_33 },
1547                 { 0x7cf00000, 0x2c100000,       RTL_GIGA_MAC_VER_32 },
1548                 { 0x7c800000, 0x2c000000,       RTL_GIGA_MAC_VER_33 },
1549
1550                 /* 8168D family. */
1551                 { 0x7cf00000, 0x28300000,       RTL_GIGA_MAC_VER_26 },
1552                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
1553                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
1554
1555                 /* 8168DP family. */
1556                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
1557                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
1558                 { 0x7cf00000, 0x28b00000,       RTL_GIGA_MAC_VER_31 },
1559
1560                 /* 8168C family. */
1561                 { 0x7cf00000, 0x3cb00000,       RTL_GIGA_MAC_VER_24 },
1562                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
1563                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
1564                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
1565                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
1566                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
1567                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
1568                 { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
1569                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
1570
1571                 /* 8168B family. */
1572                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
1573                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
1574                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
1575                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
1576
1577                 /* 8101 family. */
1578                 { 0x7cf00000, 0x40b00000,       RTL_GIGA_MAC_VER_30 },
1579                 { 0x7cf00000, 0x40a00000,       RTL_GIGA_MAC_VER_30 },
1580                 { 0x7cf00000, 0x40900000,       RTL_GIGA_MAC_VER_29 },
1581                 { 0x7c800000, 0x40800000,       RTL_GIGA_MAC_VER_30 },
1582                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
1583                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
1584                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
1585                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
1586                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
1587                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
1588                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
1589                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
1590                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
1591                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
1592                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
1593                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
1594                 /* FIXME: where did these entries come from ? -- FR */
1595                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
1596                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
1597
1598                 /* 8110 family. */
1599                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
1600                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
1601                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
1602                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
1603                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
1604                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
1605
1606                 /* Catch-all */
1607                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
1608         }, *p = mac_info;
1609         u32 reg;
1610
1611         reg = RTL_R32(TxConfig);
1612         while ((reg & p->mask) != p->val)
1613                 p++;
1614         tp->mac_version = p->mac_version;
1615 }
1616
1617 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1618 {
1619         dprintk("mac_version = 0x%02x\n", tp->mac_version);
1620 }
1621
1622 struct phy_reg {
1623         u16 reg;
1624         u16 val;
1625 };
1626
1627 static void rtl_writephy_batch(struct rtl8169_private *tp,
1628                                const struct phy_reg *regs, int len)
1629 {
1630         while (len-- > 0) {
1631                 rtl_writephy(tp, regs->reg, regs->val);
1632                 regs++;
1633         }
1634 }
1635
1636 #define PHY_READ                0x00000000
1637 #define PHY_DATA_OR             0x10000000
1638 #define PHY_DATA_AND            0x20000000
1639 #define PHY_BJMPN               0x30000000
1640 #define PHY_READ_EFUSE          0x40000000
1641 #define PHY_READ_MAC_BYTE       0x50000000
1642 #define PHY_WRITE_MAC_BYTE      0x60000000
1643 #define PHY_CLEAR_READCOUNT     0x70000000
1644 #define PHY_WRITE               0x80000000
1645 #define PHY_READCOUNT_EQ_SKIP   0x90000000
1646 #define PHY_COMP_EQ_SKIPN       0xa0000000
1647 #define PHY_COMP_NEQ_SKIPN      0xb0000000
1648 #define PHY_WRITE_PREVIOUS      0xc0000000
1649 #define PHY_SKIPN               0xd0000000
1650 #define PHY_DELAY_MS            0xe0000000
1651 #define PHY_WRITE_ERI_WORD      0xf0000000
1652
1653 static void
1654 rtl_phy_write_fw(struct rtl8169_private *tp, const struct firmware *fw)
1655 {
1656         __le32 *phytable = (__le32 *)fw->data;
1657         struct net_device *dev = tp->dev;
1658         size_t index, fw_size = fw->size / sizeof(*phytable);
1659         u32 predata, count;
1660
1661         if (fw->size % sizeof(*phytable)) {
1662                 netif_err(tp, probe, dev, "odd sized firmware %zd\n", fw->size);
1663                 return;
1664         }
1665
1666         for (index = 0; index < fw_size; index++) {
1667                 u32 action = le32_to_cpu(phytable[index]);
1668                 u32 regno = (action & 0x0fff0000) >> 16;
1669
1670                 switch(action & 0xf0000000) {
1671                 case PHY_READ:
1672                 case PHY_DATA_OR:
1673                 case PHY_DATA_AND:
1674                 case PHY_READ_EFUSE:
1675                 case PHY_CLEAR_READCOUNT:
1676                 case PHY_WRITE:
1677                 case PHY_WRITE_PREVIOUS:
1678                 case PHY_DELAY_MS:
1679                         break;
1680
1681                 case PHY_BJMPN:
1682                         if (regno > index) {
1683                                 netif_err(tp, probe, tp->dev,
1684                                         "Out of range of firmware\n");
1685                                 return;
1686                         }
1687                         break;
1688                 case PHY_READCOUNT_EQ_SKIP:
1689                         if (index + 2 >= fw_size) {
1690                                 netif_err(tp, probe, tp->dev,
1691                                         "Out of range of firmware\n");
1692                                 return;
1693                         }
1694                         break;
1695                 case PHY_COMP_EQ_SKIPN:
1696                 case PHY_COMP_NEQ_SKIPN:
1697                 case PHY_SKIPN:
1698                         if (index + 1 + regno >= fw_size) {
1699                                 netif_err(tp, probe, tp->dev,
1700                                         "Out of range of firmware\n");
1701                                 return;
1702                         }
1703                         break;
1704
1705                 case PHY_READ_MAC_BYTE:
1706                 case PHY_WRITE_MAC_BYTE:
1707                 case PHY_WRITE_ERI_WORD:
1708                 default:
1709                         netif_err(tp, probe, tp->dev,
1710                                   "Invalid action 0x%08x\n", action);
1711                         return;
1712                 }
1713         }
1714
1715         predata = 0;
1716         count = 0;
1717
1718         for (index = 0; index < fw_size; ) {
1719                 u32 action = le32_to_cpu(phytable[index]);
1720                 u32 data = action & 0x0000ffff;
1721                 u32 regno = (action & 0x0fff0000) >> 16;
1722
1723                 if (!action)
1724                         break;
1725
1726                 switch(action & 0xf0000000) {
1727                 case PHY_READ:
1728                         predata = rtl_readphy(tp, regno);
1729                         count++;
1730                         index++;
1731                         break;
1732                 case PHY_DATA_OR:
1733                         predata |= data;
1734                         index++;
1735                         break;
1736                 case PHY_DATA_AND:
1737                         predata &= data;
1738                         index++;
1739                         break;
1740                 case PHY_BJMPN:
1741                         index -= regno;
1742                         break;
1743                 case PHY_READ_EFUSE:
1744                         predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
1745                         index++;
1746                         break;
1747                 case PHY_CLEAR_READCOUNT:
1748                         count = 0;
1749                         index++;
1750                         break;
1751                 case PHY_WRITE:
1752                         rtl_writephy(tp, regno, data);
1753                         index++;
1754                         break;
1755                 case PHY_READCOUNT_EQ_SKIP:
1756                         if (count == data)
1757                                 index += 2;
1758                         else
1759                                 index += 1;
1760                         break;
1761                 case PHY_COMP_EQ_SKIPN:
1762                         if (predata == data)
1763                                 index += regno;
1764                         index++;
1765                         break;
1766                 case PHY_COMP_NEQ_SKIPN:
1767                         if (predata != data)
1768                                 index += regno;
1769                         index++;
1770                         break;
1771                 case PHY_WRITE_PREVIOUS:
1772                         rtl_writephy(tp, regno, predata);
1773                         index++;
1774                         break;
1775                 case PHY_SKIPN:
1776                         index += regno + 1;
1777                         break;
1778                 case PHY_DELAY_MS:
1779                         mdelay(data);
1780                         index++;
1781                         break;
1782
1783                 case PHY_READ_MAC_BYTE:
1784                 case PHY_WRITE_MAC_BYTE:
1785                 case PHY_WRITE_ERI_WORD:
1786                 default:
1787                         BUG();
1788                 }
1789         }
1790 }
1791
1792 static void rtl_release_firmware(struct rtl8169_private *tp)
1793 {
1794         release_firmware(tp->fw);
1795         tp->fw = NULL;
1796 }
1797
1798 static int rtl_apply_firmware(struct rtl8169_private *tp, const char *fw_name)
1799 {
1800         const struct firmware **fw = &tp->fw;
1801         int rc = !*fw;
1802
1803         if (rc) {
1804                 rc = request_firmware(fw, fw_name, &tp->pci_dev->dev);
1805                 if (rc < 0)
1806                         goto out;
1807         }
1808
1809         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
1810         rtl_phy_write_fw(tp, *fw);
1811 out:
1812         return rc;
1813 }
1814
1815 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1816 {
1817         static const struct phy_reg phy_reg_init[] = {
1818                 { 0x1f, 0x0001 },
1819                 { 0x06, 0x006e },
1820                 { 0x08, 0x0708 },
1821                 { 0x15, 0x4000 },
1822                 { 0x18, 0x65c7 },
1823
1824                 { 0x1f, 0x0001 },
1825                 { 0x03, 0x00a1 },
1826                 { 0x02, 0x0008 },
1827                 { 0x01, 0x0120 },
1828                 { 0x00, 0x1000 },
1829                 { 0x04, 0x0800 },
1830                 { 0x04, 0x0000 },
1831
1832                 { 0x03, 0xff41 },
1833                 { 0x02, 0xdf60 },
1834                 { 0x01, 0x0140 },
1835                 { 0x00, 0x0077 },
1836                 { 0x04, 0x7800 },
1837                 { 0x04, 0x7000 },
1838
1839                 { 0x03, 0x802f },
1840                 { 0x02, 0x4f02 },
1841                 { 0x01, 0x0409 },
1842                 { 0x00, 0xf0f9 },
1843                 { 0x04, 0x9800 },
1844                 { 0x04, 0x9000 },
1845
1846                 { 0x03, 0xdf01 },
1847                 { 0x02, 0xdf20 },
1848                 { 0x01, 0xff95 },
1849                 { 0x00, 0xba00 },
1850                 { 0x04, 0xa800 },
1851                 { 0x04, 0xa000 },
1852
1853                 { 0x03, 0xff41 },
1854                 { 0x02, 0xdf20 },
1855                 { 0x01, 0x0140 },
1856                 { 0x00, 0x00bb },
1857                 { 0x04, 0xb800 },
1858                 { 0x04, 0xb000 },
1859
1860                 { 0x03, 0xdf41 },
1861                 { 0x02, 0xdc60 },
1862                 { 0x01, 0x6340 },
1863                 { 0x00, 0x007d },
1864                 { 0x04, 0xd800 },
1865                 { 0x04, 0xd000 },
1866
1867                 { 0x03, 0xdf01 },
1868                 { 0x02, 0xdf20 },
1869                 { 0x01, 0x100a },
1870                 { 0x00, 0xa0ff },
1871                 { 0x04, 0xf800 },
1872                 { 0x04, 0xf000 },
1873
1874                 { 0x1f, 0x0000 },
1875                 { 0x0b, 0x0000 },
1876                 { 0x00, 0x9200 }
1877         };
1878
1879         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1880 }
1881
1882 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
1883 {
1884         static const struct phy_reg phy_reg_init[] = {
1885                 { 0x1f, 0x0002 },
1886                 { 0x01, 0x90d0 },
1887                 { 0x1f, 0x0000 }
1888         };
1889
1890         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1891 }
1892
1893 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
1894 {
1895         struct pci_dev *pdev = tp->pci_dev;
1896         u16 vendor_id, device_id;
1897
1898         pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
1899         pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
1900
1901         if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
1902                 return;
1903
1904         rtl_writephy(tp, 0x1f, 0x0001);
1905         rtl_writephy(tp, 0x10, 0xf01b);
1906         rtl_writephy(tp, 0x1f, 0x0000);
1907 }
1908
1909 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
1910 {
1911         static const struct phy_reg phy_reg_init[] = {
1912                 { 0x1f, 0x0001 },
1913                 { 0x04, 0x0000 },
1914                 { 0x03, 0x00a1 },
1915                 { 0x02, 0x0008 },
1916                 { 0x01, 0x0120 },
1917                 { 0x00, 0x1000 },
1918                 { 0x04, 0x0800 },
1919                 { 0x04, 0x9000 },
1920                 { 0x03, 0x802f },
1921                 { 0x02, 0x4f02 },
1922                 { 0x01, 0x0409 },
1923                 { 0x00, 0xf099 },
1924                 { 0x04, 0x9800 },
1925                 { 0x04, 0xa000 },
1926                 { 0x03, 0xdf01 },
1927                 { 0x02, 0xdf20 },
1928                 { 0x01, 0xff95 },
1929                 { 0x00, 0xba00 },
1930                 { 0x04, 0xa800 },
1931                 { 0x04, 0xf000 },
1932                 { 0x03, 0xdf01 },
1933                 { 0x02, 0xdf20 },
1934                 { 0x01, 0x101a },
1935                 { 0x00, 0xa0ff },
1936                 { 0x04, 0xf800 },
1937                 { 0x04, 0x0000 },
1938                 { 0x1f, 0x0000 },
1939
1940                 { 0x1f, 0x0001 },
1941                 { 0x10, 0xf41b },
1942                 { 0x14, 0xfb54 },
1943                 { 0x18, 0xf5c7 },
1944                 { 0x1f, 0x0000 },
1945
1946                 { 0x1f, 0x0001 },
1947                 { 0x17, 0x0cc0 },
1948                 { 0x1f, 0x0000 }
1949         };
1950
1951         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1952
1953         rtl8169scd_hw_phy_config_quirk(tp);
1954 }
1955
1956 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
1957 {
1958         static const struct phy_reg phy_reg_init[] = {
1959                 { 0x1f, 0x0001 },
1960                 { 0x04, 0x0000 },
1961                 { 0x03, 0x00a1 },
1962                 { 0x02, 0x0008 },
1963                 { 0x01, 0x0120 },
1964                 { 0x00, 0x1000 },
1965                 { 0x04, 0x0800 },
1966                 { 0x04, 0x9000 },
1967                 { 0x03, 0x802f },
1968                 { 0x02, 0x4f02 },
1969                 { 0x01, 0x0409 },
1970                 { 0x00, 0xf099 },
1971                 { 0x04, 0x9800 },
1972                 { 0x04, 0xa000 },
1973                 { 0x03, 0xdf01 },
1974                 { 0x02, 0xdf20 },
1975                 { 0x01, 0xff95 },
1976                 { 0x00, 0xba00 },
1977                 { 0x04, 0xa800 },
1978                 { 0x04, 0xf000 },
1979                 { 0x03, 0xdf01 },
1980                 { 0x02, 0xdf20 },
1981                 { 0x01, 0x101a },
1982                 { 0x00, 0xa0ff },
1983                 { 0x04, 0xf800 },
1984                 { 0x04, 0x0000 },
1985                 { 0x1f, 0x0000 },
1986
1987                 { 0x1f, 0x0001 },
1988                 { 0x0b, 0x8480 },
1989                 { 0x1f, 0x0000 },
1990
1991                 { 0x1f, 0x0001 },
1992                 { 0x18, 0x67c7 },
1993                 { 0x04, 0x2000 },
1994                 { 0x03, 0x002f },
1995                 { 0x02, 0x4360 },
1996                 { 0x01, 0x0109 },
1997                 { 0x00, 0x3022 },
1998                 { 0x04, 0x2800 },
1999                 { 0x1f, 0x0000 },
2000
2001                 { 0x1f, 0x0001 },
2002                 { 0x17, 0x0cc0 },
2003                 { 0x1f, 0x0000 }
2004         };
2005
2006         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2007 }
2008
2009 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2010 {
2011         static const struct phy_reg phy_reg_init[] = {
2012                 { 0x10, 0xf41b },
2013                 { 0x1f, 0x0000 }
2014         };
2015
2016         rtl_writephy(tp, 0x1f, 0x0001);
2017         rtl_patchphy(tp, 0x16, 1 << 0);
2018
2019         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2020 }
2021
2022 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2023 {
2024         static const struct phy_reg phy_reg_init[] = {
2025                 { 0x1f, 0x0001 },
2026                 { 0x10, 0xf41b },
2027                 { 0x1f, 0x0000 }
2028         };
2029
2030         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2031 }
2032
2033 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2034 {
2035         static const struct phy_reg phy_reg_init[] = {
2036                 { 0x1f, 0x0000 },
2037                 { 0x1d, 0x0f00 },
2038                 { 0x1f, 0x0002 },
2039                 { 0x0c, 0x1ec8 },
2040                 { 0x1f, 0x0000 }
2041         };
2042
2043         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2044 }
2045
2046 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2047 {
2048         static const struct phy_reg phy_reg_init[] = {
2049                 { 0x1f, 0x0001 },
2050                 { 0x1d, 0x3d98 },
2051                 { 0x1f, 0x0000 }
2052         };
2053
2054         rtl_writephy(tp, 0x1f, 0x0000);
2055         rtl_patchphy(tp, 0x14, 1 << 5);
2056         rtl_patchphy(tp, 0x0d, 1 << 5);
2057
2058         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2059 }
2060
2061 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2062 {
2063         static const struct phy_reg phy_reg_init[] = {
2064                 { 0x1f, 0x0001 },
2065                 { 0x12, 0x2300 },
2066                 { 0x1f, 0x0002 },
2067                 { 0x00, 0x88d4 },
2068                 { 0x01, 0x82b1 },
2069                 { 0x03, 0x7002 },
2070                 { 0x08, 0x9e30 },
2071                 { 0x09, 0x01f0 },
2072                 { 0x0a, 0x5500 },
2073                 { 0x0c, 0x00c8 },
2074                 { 0x1f, 0x0003 },
2075                 { 0x12, 0xc096 },
2076                 { 0x16, 0x000a },
2077                 { 0x1f, 0x0000 },
2078                 { 0x1f, 0x0000 },
2079                 { 0x09, 0x2000 },
2080                 { 0x09, 0x0000 }
2081         };
2082
2083         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2084
2085         rtl_patchphy(tp, 0x14, 1 << 5);
2086         rtl_patchphy(tp, 0x0d, 1 << 5);
2087         rtl_writephy(tp, 0x1f, 0x0000);
2088 }
2089
2090 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2091 {
2092         static const struct phy_reg phy_reg_init[] = {
2093                 { 0x1f, 0x0001 },
2094                 { 0x12, 0x2300 },
2095                 { 0x03, 0x802f },
2096                 { 0x02, 0x4f02 },
2097                 { 0x01, 0x0409 },
2098                 { 0x00, 0xf099 },
2099                 { 0x04, 0x9800 },
2100                 { 0x04, 0x9000 },
2101                 { 0x1d, 0x3d98 },
2102                 { 0x1f, 0x0002 },
2103                 { 0x0c, 0x7eb8 },
2104                 { 0x06, 0x0761 },
2105                 { 0x1f, 0x0003 },
2106                 { 0x16, 0x0f0a },
2107                 { 0x1f, 0x0000 }
2108         };
2109
2110         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2111
2112         rtl_patchphy(tp, 0x16, 1 << 0);
2113         rtl_patchphy(tp, 0x14, 1 << 5);
2114         rtl_patchphy(tp, 0x0d, 1 << 5);
2115         rtl_writephy(tp, 0x1f, 0x0000);
2116 }
2117
2118 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2119 {
2120         static const struct phy_reg phy_reg_init[] = {
2121                 { 0x1f, 0x0001 },
2122                 { 0x12, 0x2300 },
2123                 { 0x1d, 0x3d98 },
2124                 { 0x1f, 0x0002 },
2125                 { 0x0c, 0x7eb8 },
2126                 { 0x06, 0x5461 },
2127                 { 0x1f, 0x0003 },
2128                 { 0x16, 0x0f0a },
2129                 { 0x1f, 0x0000 }
2130         };
2131
2132         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2133
2134         rtl_patchphy(tp, 0x16, 1 << 0);
2135         rtl_patchphy(tp, 0x14, 1 << 5);
2136         rtl_patchphy(tp, 0x0d, 1 << 5);
2137         rtl_writephy(tp, 0x1f, 0x0000);
2138 }
2139
2140 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2141 {
2142         rtl8168c_3_hw_phy_config(tp);
2143 }
2144
2145 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2146 {
2147         static const struct phy_reg phy_reg_init_0[] = {
2148                 /* Channel Estimation */
2149                 { 0x1f, 0x0001 },
2150                 { 0x06, 0x4064 },
2151                 { 0x07, 0x2863 },
2152                 { 0x08, 0x059c },
2153                 { 0x09, 0x26b4 },
2154                 { 0x0a, 0x6a19 },
2155                 { 0x0b, 0xdcc8 },
2156                 { 0x10, 0xf06d },
2157                 { 0x14, 0x7f68 },
2158                 { 0x18, 0x7fd9 },
2159                 { 0x1c, 0xf0ff },
2160                 { 0x1d, 0x3d9c },
2161                 { 0x1f, 0x0003 },
2162                 { 0x12, 0xf49f },
2163                 { 0x13, 0x070b },
2164                 { 0x1a, 0x05ad },
2165                 { 0x14, 0x94c0 },
2166
2167                 /*
2168                  * Tx Error Issue
2169                  * enhance line driver power
2170                  */
2171                 { 0x1f, 0x0002 },
2172                 { 0x06, 0x5561 },
2173                 { 0x1f, 0x0005 },
2174                 { 0x05, 0x8332 },
2175                 { 0x06, 0x5561 },
2176
2177                 /*
2178                  * Can not link to 1Gbps with bad cable
2179                  * Decrease SNR threshold form 21.07dB to 19.04dB
2180                  */
2181                 { 0x1f, 0x0001 },
2182                 { 0x17, 0x0cc0 },
2183
2184                 { 0x1f, 0x0000 },
2185                 { 0x0d, 0xf880 }
2186         };
2187         void __iomem *ioaddr = tp->mmio_addr;
2188
2189         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2190
2191         /*
2192          * Rx Error Issue
2193          * Fine Tune Switching regulator parameter
2194          */
2195         rtl_writephy(tp, 0x1f, 0x0002);
2196         rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2197         rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2198
2199         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2200                 static const struct phy_reg phy_reg_init[] = {
2201                         { 0x1f, 0x0002 },
2202                         { 0x05, 0x669a },
2203                         { 0x1f, 0x0005 },
2204                         { 0x05, 0x8330 },
2205                         { 0x06, 0x669a },
2206                         { 0x1f, 0x0002 }
2207                 };
2208                 int val;
2209
2210                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2211
2212                 val = rtl_readphy(tp, 0x0d);
2213
2214                 if ((val & 0x00ff) != 0x006c) {
2215                         static const u32 set[] = {
2216                                 0x0065, 0x0066, 0x0067, 0x0068,
2217                                 0x0069, 0x006a, 0x006b, 0x006c
2218                         };
2219                         int i;
2220
2221                         rtl_writephy(tp, 0x1f, 0x0002);
2222
2223                         val &= 0xff00;
2224                         for (i = 0; i < ARRAY_SIZE(set); i++)
2225                                 rtl_writephy(tp, 0x0d, val | set[i]);
2226                 }
2227         } else {
2228                 static const struct phy_reg phy_reg_init[] = {
2229                         { 0x1f, 0x0002 },
2230                         { 0x05, 0x6662 },
2231                         { 0x1f, 0x0005 },
2232                         { 0x05, 0x8330 },
2233                         { 0x06, 0x6662 }
2234                 };
2235
2236                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2237         }
2238
2239         /* RSET couple improve */
2240         rtl_writephy(tp, 0x1f, 0x0002);
2241         rtl_patchphy(tp, 0x0d, 0x0300);
2242         rtl_patchphy(tp, 0x0f, 0x0010);
2243
2244         /* Fine tune PLL performance */
2245         rtl_writephy(tp, 0x1f, 0x0002);
2246         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2247         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2248
2249         rtl_writephy(tp, 0x1f, 0x0005);
2250         rtl_writephy(tp, 0x05, 0x001b);
2251         if ((rtl_readphy(tp, 0x06) != 0xbf00) ||
2252             (rtl_apply_firmware(tp, FIRMWARE_8168D_1) < 0)) {
2253                 netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n");
2254         }
2255
2256         rtl_writephy(tp, 0x1f, 0x0000);
2257 }
2258
2259 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2260 {
2261         static const struct phy_reg phy_reg_init_0[] = {
2262                 /* Channel Estimation */
2263                 { 0x1f, 0x0001 },
2264                 { 0x06, 0x4064 },
2265                 { 0x07, 0x2863 },
2266                 { 0x08, 0x059c },
2267                 { 0x09, 0x26b4 },
2268                 { 0x0a, 0x6a19 },
2269                 { 0x0b, 0xdcc8 },
2270                 { 0x10, 0xf06d },
2271                 { 0x14, 0x7f68 },
2272                 { 0x18, 0x7fd9 },
2273                 { 0x1c, 0xf0ff },
2274                 { 0x1d, 0x3d9c },
2275                 { 0x1f, 0x0003 },
2276                 { 0x12, 0xf49f },
2277                 { 0x13, 0x070b },
2278                 { 0x1a, 0x05ad },
2279                 { 0x14, 0x94c0 },
2280
2281                 /*
2282                  * Tx Error Issue
2283                  * enhance line driver power
2284                  */
2285                 { 0x1f, 0x0002 },
2286                 { 0x06, 0x5561 },
2287                 { 0x1f, 0x0005 },
2288                 { 0x05, 0x8332 },
2289                 { 0x06, 0x5561 },
2290
2291                 /*
2292                  * Can not link to 1Gbps with bad cable
2293                  * Decrease SNR threshold form 21.07dB to 19.04dB
2294                  */
2295                 { 0x1f, 0x0001 },
2296                 { 0x17, 0x0cc0 },
2297
2298                 { 0x1f, 0x0000 },
2299                 { 0x0d, 0xf880 }
2300         };
2301         void __iomem *ioaddr = tp->mmio_addr;
2302
2303         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2304
2305         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2306                 static const struct phy_reg phy_reg_init[] = {
2307                         { 0x1f, 0x0002 },
2308                         { 0x05, 0x669a },
2309                         { 0x1f, 0x0005 },
2310                         { 0x05, 0x8330 },
2311                         { 0x06, 0x669a },
2312
2313                         { 0x1f, 0x0002 }
2314                 };
2315                 int val;
2316
2317                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2318
2319                 val = rtl_readphy(tp, 0x0d);
2320                 if ((val & 0x00ff) != 0x006c) {
2321                         static const u32 set[] = {
2322                                 0x0065, 0x0066, 0x0067, 0x0068,
2323                                 0x0069, 0x006a, 0x006b, 0x006c
2324                         };
2325                         int i;
2326
2327                         rtl_writephy(tp, 0x1f, 0x0002);
2328
2329                         val &= 0xff00;
2330                         for (i = 0; i < ARRAY_SIZE(set); i++)
2331                                 rtl_writephy(tp, 0x0d, val | set[i]);
2332                 }
2333         } else {
2334                 static const struct phy_reg phy_reg_init[] = {
2335                         { 0x1f, 0x0002 },
2336                         { 0x05, 0x2642 },
2337                         { 0x1f, 0x0005 },
2338                         { 0x05, 0x8330 },
2339                         { 0x06, 0x2642 }
2340                 };
2341
2342                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2343         }
2344
2345         /* Fine tune PLL performance */
2346         rtl_writephy(tp, 0x1f, 0x0002);
2347         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2348         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2349
2350         /* Switching regulator Slew rate */
2351         rtl_writephy(tp, 0x1f, 0x0002);
2352         rtl_patchphy(tp, 0x0f, 0x0017);
2353
2354         rtl_writephy(tp, 0x1f, 0x0005);
2355         rtl_writephy(tp, 0x05, 0x001b);
2356         if ((rtl_readphy(tp, 0x06) != 0xb300) ||
2357             (rtl_apply_firmware(tp, FIRMWARE_8168D_2) < 0)) {
2358                 netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n");
2359         }
2360
2361         rtl_writephy(tp, 0x1f, 0x0000);
2362 }
2363
2364 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2365 {
2366         static const struct phy_reg phy_reg_init[] = {
2367                 { 0x1f, 0x0002 },
2368                 { 0x10, 0x0008 },
2369                 { 0x0d, 0x006c },
2370
2371                 { 0x1f, 0x0000 },
2372                 { 0x0d, 0xf880 },
2373
2374                 { 0x1f, 0x0001 },
2375                 { 0x17, 0x0cc0 },
2376
2377                 { 0x1f, 0x0001 },
2378                 { 0x0b, 0xa4d8 },
2379                 { 0x09, 0x281c },
2380                 { 0x07, 0x2883 },
2381                 { 0x0a, 0x6b35 },
2382                 { 0x1d, 0x3da4 },
2383                 { 0x1c, 0xeffd },
2384                 { 0x14, 0x7f52 },
2385                 { 0x18, 0x7fc6 },
2386                 { 0x08, 0x0601 },
2387                 { 0x06, 0x4063 },
2388                 { 0x10, 0xf074 },
2389                 { 0x1f, 0x0003 },
2390                 { 0x13, 0x0789 },
2391                 { 0x12, 0xf4bd },
2392                 { 0x1a, 0x04fd },
2393                 { 0x14, 0x84b0 },
2394                 { 0x1f, 0x0000 },
2395                 { 0x00, 0x9200 },
2396
2397                 { 0x1f, 0x0005 },
2398                 { 0x01, 0x0340 },
2399                 { 0x1f, 0x0001 },
2400                 { 0x04, 0x4000 },
2401                 { 0x03, 0x1d21 },
2402                 { 0x02, 0x0c32 },
2403                 { 0x01, 0x0200 },
2404                 { 0x00, 0x5554 },
2405                 { 0x04, 0x4800 },
2406                 { 0x04, 0x4000 },
2407                 { 0x04, 0xf000 },
2408                 { 0x03, 0xdf01 },
2409                 { 0x02, 0xdf20 },
2410                 { 0x01, 0x101a },
2411                 { 0x00, 0xa0ff },
2412                 { 0x04, 0xf800 },
2413                 { 0x04, 0xf000 },
2414                 { 0x1f, 0x0000 },
2415
2416                 { 0x1f, 0x0007 },
2417                 { 0x1e, 0x0023 },
2418                 { 0x16, 0x0000 },
2419                 { 0x1f, 0x0000 }
2420         };
2421
2422         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2423 }
2424
2425 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2426 {
2427         static const struct phy_reg phy_reg_init[] = {
2428                 { 0x1f, 0x0001 },
2429                 { 0x17, 0x0cc0 },
2430
2431                 { 0x1f, 0x0007 },
2432                 { 0x1e, 0x002d },
2433                 { 0x18, 0x0040 },
2434                 { 0x1f, 0x0000 }
2435         };
2436
2437         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2438         rtl_patchphy(tp, 0x0d, 1 << 5);
2439 }
2440
2441 static void rtl8168e_hw_phy_config(struct rtl8169_private *tp)
2442 {
2443         static const struct phy_reg phy_reg_init[] = {
2444                 /* Enable Delay cap */
2445                 { 0x1f, 0x0005 },
2446                 { 0x05, 0x8b80 },
2447                 { 0x06, 0xc896 },
2448                 { 0x1f, 0x0000 },
2449
2450                 /* Channel estimation fine tune */
2451                 { 0x1f, 0x0001 },
2452                 { 0x0b, 0x6c20 },
2453                 { 0x07, 0x2872 },
2454                 { 0x1c, 0xefff },
2455                 { 0x1f, 0x0003 },
2456                 { 0x14, 0x6420 },
2457                 { 0x1f, 0x0000 },
2458
2459                 /* Update PFM & 10M TX idle timer */
2460                 { 0x1f, 0x0007 },
2461                 { 0x1e, 0x002f },
2462                 { 0x15, 0x1919 },
2463                 { 0x1f, 0x0000 },
2464
2465                 { 0x1f, 0x0007 },
2466                 { 0x1e, 0x00ac },
2467                 { 0x18, 0x0006 },
2468                 { 0x1f, 0x0000 }
2469         };
2470
2471         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2472
2473         /* DCO enable for 10M IDLE Power */
2474         rtl_writephy(tp, 0x1f, 0x0007);
2475         rtl_writephy(tp, 0x1e, 0x0023);
2476         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2477         rtl_writephy(tp, 0x1f, 0x0000);
2478
2479         /* For impedance matching */
2480         rtl_writephy(tp, 0x1f, 0x0002);
2481         rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
2482         rtl_writephy(tp, 0x1F, 0x0000);
2483
2484         /* PHY auto speed down */
2485         rtl_writephy(tp, 0x1f, 0x0007);
2486         rtl_writephy(tp, 0x1e, 0x002d);
2487         rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2488         rtl_writephy(tp, 0x1f, 0x0000);
2489         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2490
2491         rtl_writephy(tp, 0x1f, 0x0005);
2492         rtl_writephy(tp, 0x05, 0x8b86);
2493         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2494         rtl_writephy(tp, 0x1f, 0x0000);
2495
2496         rtl_writephy(tp, 0x1f, 0x0005);
2497         rtl_writephy(tp, 0x05, 0x8b85);
2498         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2499         rtl_writephy(tp, 0x1f, 0x0007);
2500         rtl_writephy(tp, 0x1e, 0x0020);
2501         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2502         rtl_writephy(tp, 0x1f, 0x0006);
2503         rtl_writephy(tp, 0x00, 0x5a00);
2504         rtl_writephy(tp, 0x1f, 0x0000);
2505         rtl_writephy(tp, 0x0d, 0x0007);
2506         rtl_writephy(tp, 0x0e, 0x003c);
2507         rtl_writephy(tp, 0x0d, 0x4007);
2508         rtl_writephy(tp, 0x0e, 0x0000);
2509         rtl_writephy(tp, 0x0d, 0x0000);
2510 }
2511
2512 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
2513 {
2514         if (rtl_apply_firmware(tp, FIRMWARE_8168E_1) < 0)
2515                 netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n");
2516
2517         rtl8168e_hw_phy_config(tp);
2518 }
2519
2520 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
2521 {
2522         if (rtl_apply_firmware(tp, FIRMWARE_8168E_2) < 0)
2523                 netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n");
2524
2525         rtl8168e_hw_phy_config(tp);
2526 }
2527
2528 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2529 {
2530         static const struct phy_reg phy_reg_init[] = {
2531                 { 0x1f, 0x0003 },
2532                 { 0x08, 0x441d },
2533                 { 0x01, 0x9100 },
2534                 { 0x1f, 0x0000 }
2535         };
2536
2537         rtl_writephy(tp, 0x1f, 0x0000);
2538         rtl_patchphy(tp, 0x11, 1 << 12);
2539         rtl_patchphy(tp, 0x19, 1 << 13);
2540         rtl_patchphy(tp, 0x10, 1 << 15);
2541
2542         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2543 }
2544
2545 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
2546 {
2547         static const struct phy_reg phy_reg_init[] = {
2548                 { 0x1f, 0x0005 },
2549                 { 0x1a, 0x0000 },
2550                 { 0x1f, 0x0000 },
2551
2552                 { 0x1f, 0x0004 },
2553                 { 0x1c, 0x0000 },
2554                 { 0x1f, 0x0000 },
2555
2556                 { 0x1f, 0x0001 },
2557                 { 0x15, 0x7701 },
2558                 { 0x1f, 0x0000 }
2559         };
2560
2561         /* Disable ALDPS before ram code */
2562         rtl_writephy(tp, 0x1f, 0x0000);
2563         rtl_writephy(tp, 0x18, 0x0310);
2564         msleep(100);
2565
2566         if (rtl_apply_firmware(tp, FIRMWARE_8105E_1) < 0)
2567                 netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n");
2568
2569         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2570 }
2571
2572 static void rtl_hw_phy_config(struct net_device *dev)
2573 {
2574         struct rtl8169_private *tp = netdev_priv(dev);
2575
2576         rtl8169_print_mac_version(tp);
2577
2578         switch (tp->mac_version) {
2579         case RTL_GIGA_MAC_VER_01:
2580                 break;
2581         case RTL_GIGA_MAC_VER_02:
2582         case RTL_GIGA_MAC_VER_03:
2583                 rtl8169s_hw_phy_config(tp);
2584                 break;
2585         case RTL_GIGA_MAC_VER_04:
2586                 rtl8169sb_hw_phy_config(tp);
2587                 break;
2588         case RTL_GIGA_MAC_VER_05:
2589                 rtl8169scd_hw_phy_config(tp);
2590                 break;
2591         case RTL_GIGA_MAC_VER_06:
2592                 rtl8169sce_hw_phy_config(tp);
2593                 break;
2594         case RTL_GIGA_MAC_VER_07:
2595         case RTL_GIGA_MAC_VER_08:
2596         case RTL_GIGA_MAC_VER_09:
2597                 rtl8102e_hw_phy_config(tp);
2598                 break;
2599         case RTL_GIGA_MAC_VER_11:
2600                 rtl8168bb_hw_phy_config(tp);
2601                 break;
2602         case RTL_GIGA_MAC_VER_12:
2603                 rtl8168bef_hw_phy_config(tp);
2604                 break;
2605         case RTL_GIGA_MAC_VER_17:
2606                 rtl8168bef_hw_phy_config(tp);
2607                 break;
2608         case RTL_GIGA_MAC_VER_18:
2609                 rtl8168cp_1_hw_phy_config(tp);
2610                 break;
2611         case RTL_GIGA_MAC_VER_19:
2612                 rtl8168c_1_hw_phy_config(tp);
2613                 break;
2614         case RTL_GIGA_MAC_VER_20:
2615                 rtl8168c_2_hw_phy_config(tp);
2616                 break;
2617         case RTL_GIGA_MAC_VER_21:
2618                 rtl8168c_3_hw_phy_config(tp);
2619                 break;
2620         case RTL_GIGA_MAC_VER_22:
2621                 rtl8168c_4_hw_phy_config(tp);
2622                 break;
2623         case RTL_GIGA_MAC_VER_23:
2624         case RTL_GIGA_MAC_VER_24:
2625                 rtl8168cp_2_hw_phy_config(tp);
2626                 break;
2627         case RTL_GIGA_MAC_VER_25:
2628                 rtl8168d_1_hw_phy_config(tp);
2629                 break;
2630         case RTL_GIGA_MAC_VER_26:
2631                 rtl8168d_2_hw_phy_config(tp);
2632                 break;
2633         case RTL_GIGA_MAC_VER_27:
2634                 rtl8168d_3_hw_phy_config(tp);
2635                 break;
2636         case RTL_GIGA_MAC_VER_28:
2637                 rtl8168d_4_hw_phy_config(tp);
2638                 break;
2639         case RTL_GIGA_MAC_VER_29:
2640         case RTL_GIGA_MAC_VER_30:
2641                 rtl8105e_hw_phy_config(tp);
2642                 break;
2643         case RTL_GIGA_MAC_VER_32:
2644                 rtl8168e_1_hw_phy_config(tp);
2645                 break;
2646         case RTL_GIGA_MAC_VER_33:
2647                 rtl8168e_2_hw_phy_config(tp);
2648                 break;
2649
2650         default:
2651                 break;
2652         }
2653 }
2654
2655 static void rtl8169_phy_timer(unsigned long __opaque)
2656 {
2657         struct net_device *dev = (struct net_device *)__opaque;
2658         struct rtl8169_private *tp = netdev_priv(dev);
2659         struct timer_list *timer = &tp->timer;
2660         void __iomem *ioaddr = tp->mmio_addr;
2661         unsigned long timeout = RTL8169_PHY_TIMEOUT;
2662
2663         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
2664
2665         if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
2666                 return;
2667
2668         spin_lock_irq(&tp->lock);
2669
2670         if (tp->phy_reset_pending(tp)) {
2671                 /*
2672                  * A busy loop could burn quite a few cycles on nowadays CPU.
2673                  * Let's delay the execution of the timer for a few ticks.
2674                  */
2675                 timeout = HZ/10;
2676                 goto out_mod_timer;
2677         }
2678
2679         if (tp->link_ok(ioaddr))
2680                 goto out_unlock;
2681
2682         netif_warn(tp, link, dev, "PHY reset until link up\n");
2683
2684         tp->phy_reset_enable(tp);
2685
2686 out_mod_timer:
2687         mod_timer(timer, jiffies + timeout);
2688 out_unlock:
2689         spin_unlock_irq(&tp->lock);
2690 }
2691
2692 static inline void rtl8169_delete_timer(struct net_device *dev)
2693 {
2694         struct rtl8169_private *tp = netdev_priv(dev);
2695         struct timer_list *timer = &tp->timer;
2696
2697         if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
2698                 return;
2699
2700         del_timer_sync(timer);
2701 }
2702
2703 static inline void rtl8169_request_timer(struct net_device *dev)
2704 {
2705         struct rtl8169_private *tp = netdev_priv(dev);
2706         struct timer_list *timer = &tp->timer;
2707
2708         if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
2709                 return;
2710
2711         mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
2712 }
2713
2714 #ifdef CONFIG_NET_POLL_CONTROLLER
2715 /*
2716  * Polling 'interrupt' - used by things like netconsole to send skbs
2717  * without having to re-enable interrupts. It's not called while
2718  * the interrupt routine is executing.
2719  */
2720 static void rtl8169_netpoll(struct net_device *dev)
2721 {
2722         struct rtl8169_private *tp = netdev_priv(dev);
2723         struct pci_dev *pdev = tp->pci_dev;
2724
2725         disable_irq(pdev->irq);
2726         rtl8169_interrupt(pdev->irq, dev);
2727         enable_irq(pdev->irq);
2728 }
2729 #endif
2730
2731 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
2732                                   void __iomem *ioaddr)
2733 {
2734         iounmap(ioaddr);
2735         pci_release_regions(pdev);
2736         pci_clear_mwi(pdev);
2737         pci_disable_device(pdev);
2738         free_netdev(dev);
2739 }
2740
2741 static void rtl8169_phy_reset(struct net_device *dev,
2742                               struct rtl8169_private *tp)
2743 {
2744         unsigned int i;
2745
2746         tp->phy_reset_enable(tp);
2747         for (i = 0; i < 100; i++) {
2748                 if (!tp->phy_reset_pending(tp))
2749                         return;
2750                 msleep(1);
2751         }
2752         netif_err(tp, link, dev, "PHY reset failed\n");
2753 }
2754
2755 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
2756 {
2757         void __iomem *ioaddr = tp->mmio_addr;
2758
2759         rtl_hw_phy_config(dev);
2760
2761         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2762                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2763                 RTL_W8(0x82, 0x01);
2764         }
2765
2766         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2767
2768         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
2769                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
2770
2771         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
2772                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2773                 RTL_W8(0x82, 0x01);
2774                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
2775                 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
2776         }
2777
2778         rtl8169_phy_reset(dev, tp);
2779
2780         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
2781                 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
2782                 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
2783                 (tp->mii.supports_gmii ?
2784                         ADVERTISED_1000baseT_Half |
2785                         ADVERTISED_1000baseT_Full : 0));
2786
2787         if (RTL_R8(PHYstatus) & TBI_Enable)
2788                 netif_info(tp, link, dev, "TBI auto-negotiating\n");
2789 }
2790
2791 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2792 {
2793         void __iomem *ioaddr = tp->mmio_addr;
2794         u32 high;
2795         u32 low;
2796
2797         low  = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
2798         high = addr[4] | (addr[5] << 8);
2799
2800         spin_lock_irq(&tp->lock);
2801
2802         RTL_W8(Cfg9346, Cfg9346_Unlock);
2803
2804         RTL_W32(MAC4, high);
2805         RTL_R32(MAC4);
2806
2807         RTL_W32(MAC0, low);
2808         RTL_R32(MAC0);
2809
2810         RTL_W8(Cfg9346, Cfg9346_Lock);
2811
2812         spin_unlock_irq(&tp->lock);
2813 }
2814
2815 static int rtl_set_mac_address(struct net_device *dev, void *p)
2816 {
2817         struct rtl8169_private *tp = netdev_priv(dev);
2818         struct sockaddr *addr = p;
2819
2820         if (!is_valid_ether_addr(addr->sa_data))
2821                 return -EADDRNOTAVAIL;
2822
2823         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2824
2825         rtl_rar_set(tp, dev->dev_addr);
2826
2827         return 0;
2828 }
2829
2830 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2831 {
2832         struct rtl8169_private *tp = netdev_priv(dev);
2833         struct mii_ioctl_data *data = if_mii(ifr);
2834
2835         return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
2836 }
2837
2838 static int rtl_xmii_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2839 {
2840         switch (cmd) {
2841         case SIOCGMIIPHY:
2842                 data->phy_id = 32; /* Internal PHY */
2843                 return 0;
2844
2845         case SIOCGMIIREG:
2846                 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
2847                 return 0;
2848
2849         case SIOCSMIIREG:
2850                 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
2851                 return 0;
2852         }
2853         return -EOPNOTSUPP;
2854 }
2855
2856 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2857 {
2858         return -EOPNOTSUPP;
2859 }
2860
2861 static const struct rtl_cfg_info {
2862         void (*hw_start)(struct net_device *);
2863         unsigned int region;
2864         unsigned int align;
2865         u16 intr_event;
2866         u16 napi_event;
2867         unsigned features;
2868         u8 default_ver;
2869 } rtl_cfg_infos [] = {
2870         [RTL_CFG_0] = {
2871                 .hw_start       = rtl_hw_start_8169,
2872                 .region         = 1,
2873                 .align          = 0,
2874                 .intr_event     = SYSErr | LinkChg | RxOverflow |
2875                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2876                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2877                 .features       = RTL_FEATURE_GMII,
2878                 .default_ver    = RTL_GIGA_MAC_VER_01,
2879         },
2880         [RTL_CFG_1] = {
2881                 .hw_start       = rtl_hw_start_8168,
2882                 .region         = 2,
2883                 .align          = 8,
2884                 .intr_event     = SYSErr | LinkChg | RxOverflow |
2885                                   TxErr | TxOK | RxOK | RxErr,
2886                 .napi_event     = TxErr | TxOK | RxOK | RxOverflow,
2887                 .features       = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
2888                 .default_ver    = RTL_GIGA_MAC_VER_11,
2889         },
2890         [RTL_CFG_2] = {
2891                 .hw_start       = rtl_hw_start_8101,
2892                 .region         = 2,
2893                 .align          = 8,
2894                 .intr_event     = SYSErr | LinkChg | RxOverflow | PCSTimeout |
2895                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2896                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2897                 .features       = RTL_FEATURE_MSI,
2898                 .default_ver    = RTL_GIGA_MAC_VER_13,
2899         }
2900 };
2901
2902 /* Cfg9346_Unlock assumed. */
2903 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
2904                             const struct rtl_cfg_info *cfg)
2905 {
2906         unsigned msi = 0;
2907         u8 cfg2;
2908
2909         cfg2 = RTL_R8(Config2) & ~MSIEnable;
2910         if (cfg->features & RTL_FEATURE_MSI) {
2911                 if (pci_enable_msi(pdev)) {
2912                         dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
2913                 } else {
2914                         cfg2 |= MSIEnable;
2915                         msi = RTL_FEATURE_MSI;
2916                 }
2917         }
2918         RTL_W8(Config2, cfg2);
2919         return msi;
2920 }
2921
2922 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
2923 {
2924         if (tp->features & RTL_FEATURE_MSI) {
2925                 pci_disable_msi(pdev);
2926                 tp->features &= ~RTL_FEATURE_MSI;
2927         }
2928 }
2929
2930 static const struct net_device_ops rtl8169_netdev_ops = {
2931         .ndo_open               = rtl8169_open,
2932         .ndo_stop               = rtl8169_close,
2933         .ndo_get_stats          = rtl8169_get_stats,
2934         .ndo_start_xmit         = rtl8169_start_xmit,
2935         .ndo_tx_timeout         = rtl8169_tx_timeout,
2936         .ndo_validate_addr      = eth_validate_addr,
2937         .ndo_change_mtu         = rtl8169_change_mtu,
2938         .ndo_fix_features       = rtl8169_fix_features,
2939         .ndo_set_features       = rtl8169_set_features,
2940         .ndo_set_mac_address    = rtl_set_mac_address,
2941         .ndo_do_ioctl           = rtl8169_ioctl,
2942         .ndo_set_multicast_list = rtl_set_rx_mode,
2943 #ifdef CONFIG_NET_POLL_CONTROLLER
2944         .ndo_poll_controller    = rtl8169_netpoll,
2945 #endif
2946
2947 };
2948
2949 static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
2950 {
2951         struct mdio_ops *ops = &tp->mdio_ops;
2952
2953         switch (tp->mac_version) {
2954         case RTL_GIGA_MAC_VER_27:
2955                 ops->write      = r8168dp_1_mdio_write;
2956                 ops->read       = r8168dp_1_mdio_read;
2957                 break;
2958         case RTL_GIGA_MAC_VER_28:
2959         case RTL_GIGA_MAC_VER_31:
2960                 ops->write      = r8168dp_2_mdio_write;
2961                 ops->read       = r8168dp_2_mdio_read;
2962                 break;
2963         default:
2964                 ops->write      = r8169_mdio_write;
2965                 ops->read       = r8169_mdio_read;
2966                 break;
2967         }
2968 }
2969
2970 static void r810x_phy_power_down(struct rtl8169_private *tp)
2971 {
2972         rtl_writephy(tp, 0x1f, 0x0000);
2973         rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
2974 }
2975
2976 static void r810x_phy_power_up(struct rtl8169_private *tp)
2977 {
2978         rtl_writephy(tp, 0x1f, 0x0000);
2979         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
2980 }
2981
2982 static void r810x_pll_power_down(struct rtl8169_private *tp)
2983 {
2984         if (__rtl8169_get_wol(tp) & WAKE_ANY) {
2985                 rtl_writephy(tp, 0x1f, 0x0000);
2986                 rtl_writephy(tp, MII_BMCR, 0x0000);
2987                 return;
2988         }
2989
2990         r810x_phy_power_down(tp);
2991 }
2992
2993 static void r810x_pll_power_up(struct rtl8169_private *tp)
2994 {
2995         r810x_phy_power_up(tp);
2996 }
2997
2998 static void r8168_phy_power_up(struct rtl8169_private *tp)
2999 {
3000         rtl_writephy(tp, 0x1f, 0x0000);
3001         switch (tp->mac_version) {
3002         case RTL_GIGA_MAC_VER_11:
3003         case RTL_GIGA_MAC_VER_12:
3004         case RTL_GIGA_MAC_VER_17:
3005         case RTL_GIGA_MAC_VER_18:
3006         case RTL_GIGA_MAC_VER_19:
3007         case RTL_GIGA_MAC_VER_20:
3008         case RTL_GIGA_MAC_VER_21:
3009         case RTL_GIGA_MAC_VER_22:
3010         case RTL_GIGA_MAC_VER_23:
3011         case RTL_GIGA_MAC_VER_24:
3012         case RTL_GIGA_MAC_VER_25:
3013         case RTL_GIGA_MAC_VER_26:
3014         case RTL_GIGA_MAC_VER_27:
3015         case RTL_GIGA_MAC_VER_28:
3016         case RTL_GIGA_MAC_VER_31:
3017                 rtl_writephy(tp, 0x0e, 0x0000);
3018                 break;
3019         default:
3020                 break;
3021         }
3022         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3023 }
3024
3025 static void r8168_phy_power_down(struct rtl8169_private *tp)
3026 {
3027         rtl_writephy(tp, 0x1f, 0x0000);
3028         switch (tp->mac_version) {
3029         case RTL_GIGA_MAC_VER_32:
3030         case RTL_GIGA_MAC_VER_33:
3031                 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3032                 break;
3033
3034         case RTL_GIGA_MAC_VER_11:
3035         case RTL_GIGA_MAC_VER_12:
3036         case RTL_GIGA_MAC_VER_17:
3037         case RTL_GIGA_MAC_VER_18:
3038         case RTL_GIGA_MAC_VER_19:
3039         case RTL_GIGA_MAC_VER_20:
3040         case RTL_GIGA_MAC_VER_21:
3041         case RTL_GIGA_MAC_VER_22:
3042         case RTL_GIGA_MAC_VER_23:
3043         case RTL_GIGA_MAC_VER_24:
3044         case RTL_GIGA_MAC_VER_25:
3045         case RTL_GIGA_MAC_VER_26:
3046         case RTL_GIGA_MAC_VER_27:
3047         case RTL_GIGA_MAC_VER_28:
3048         case RTL_GIGA_MAC_VER_31:
3049                 rtl_writephy(tp, 0x0e, 0x0200);
3050         default:
3051                 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3052                 break;
3053         }
3054 }
3055
3056 static void r8168_pll_power_down(struct rtl8169_private *tp)
3057 {
3058         void __iomem *ioaddr = tp->mmio_addr;
3059
3060         if (((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
3061              (tp->mac_version == RTL_GIGA_MAC_VER_28) ||
3062              (tp->mac_version == RTL_GIGA_MAC_VER_31)) &&
3063             r8168dp_check_dash(tp)) {
3064                 return;
3065         }
3066
3067         if (((tp->mac_version == RTL_GIGA_MAC_VER_23) ||
3068              (tp->mac_version == RTL_GIGA_MAC_VER_24)) &&
3069             (RTL_R16(CPlusCmd) & ASF)) {
3070                 return;
3071         }
3072
3073         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3074             tp->mac_version == RTL_GIGA_MAC_VER_33)
3075                 rtl_ephy_write(ioaddr, 0x19, 0xff64);
3076
3077         if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3078                 rtl_writephy(tp, 0x1f, 0x0000);
3079                 rtl_writephy(tp, MII_BMCR, 0x0000);
3080
3081                 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3082                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3083                 return;
3084         }
3085
3086         r8168_phy_power_down(tp);
3087
3088         switch (tp->mac_version) {
3089         case RTL_GIGA_MAC_VER_25:
3090         case RTL_GIGA_MAC_VER_26:
3091         case RTL_GIGA_MAC_VER_27:
3092         case RTL_GIGA_MAC_VER_28:
3093         case RTL_GIGA_MAC_VER_31:
3094         case RTL_GIGA_MAC_VER_32:
3095         case RTL_GIGA_MAC_VER_33:
3096                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3097                 break;
3098         }
3099 }
3100
3101 static void r8168_pll_power_up(struct rtl8169_private *tp)
3102 {
3103         void __iomem *ioaddr = tp->mmio_addr;
3104
3105         if (((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
3106              (tp->mac_version == RTL_GIGA_MAC_VER_28) ||
3107              (tp->mac_version == RTL_GIGA_MAC_VER_31)) &&
3108             r8168dp_check_dash(tp)) {
3109                 return;
3110         }
3111
3112         switch (tp->mac_version) {
3113         case RTL_GIGA_MAC_VER_25:
3114         case RTL_GIGA_MAC_VER_26:
3115         case RTL_GIGA_MAC_VER_27:
3116         case RTL_GIGA_MAC_VER_28:
3117         case RTL_GIGA_MAC_VER_31:
3118         case RTL_GIGA_MAC_VER_32:
3119         case RTL_GIGA_MAC_VER_33:
3120                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3121                 break;
3122         }
3123
3124         r8168_phy_power_up(tp);
3125 }
3126
3127 static void rtl_pll_power_op(struct rtl8169_private *tp,
3128                              void (*op)(struct rtl8169_private *))
3129 {
3130         if (op)
3131                 op(tp);
3132 }
3133
3134 static void rtl_pll_power_down(struct rtl8169_private *tp)
3135 {
3136         rtl_pll_power_op(tp, tp->pll_power_ops.down);
3137 }
3138
3139 static void rtl_pll_power_up(struct rtl8169_private *tp)
3140 {
3141         rtl_pll_power_op(tp, tp->pll_power_ops.up);
3142 }
3143
3144 static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3145 {
3146         struct pll_power_ops *ops = &tp->pll_power_ops;
3147
3148         switch (tp->mac_version) {
3149         case RTL_GIGA_MAC_VER_07:
3150         case RTL_GIGA_MAC_VER_08:
3151         case RTL_GIGA_MAC_VER_09:
3152         case RTL_GIGA_MAC_VER_10:
3153         case RTL_GIGA_MAC_VER_16:
3154         case RTL_GIGA_MAC_VER_29:
3155         case RTL_GIGA_MAC_VER_30:
3156                 ops->down       = r810x_pll_power_down;
3157                 ops->up         = r810x_pll_power_up;
3158                 break;
3159
3160         case RTL_GIGA_MAC_VER_11:
3161         case RTL_GIGA_MAC_VER_12:
3162         case RTL_GIGA_MAC_VER_17:
3163         case RTL_GIGA_MAC_VER_18:
3164         case RTL_GIGA_MAC_VER_19:
3165         case RTL_GIGA_MAC_VER_20:
3166         case RTL_GIGA_MAC_VER_21:
3167         case RTL_GIGA_MAC_VER_22:
3168         case RTL_GIGA_MAC_VER_23:
3169         case RTL_GIGA_MAC_VER_24:
3170         case RTL_GIGA_MAC_VER_25:
3171         case RTL_GIGA_MAC_VER_26:
3172         case RTL_GIGA_MAC_VER_27:
3173         case RTL_GIGA_MAC_VER_28:
3174         case RTL_GIGA_MAC_VER_31:
3175         case RTL_GIGA_MAC_VER_32:
3176         case RTL_GIGA_MAC_VER_33:
3177                 ops->down       = r8168_pll_power_down;
3178                 ops->up         = r8168_pll_power_up;
3179                 break;
3180
3181         default:
3182                 ops->down       = NULL;
3183                 ops->up         = NULL;
3184                 break;
3185         }
3186 }
3187
3188 static int __devinit
3189 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3190 {
3191         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
3192         const unsigned int region = cfg->region;
3193         struct rtl8169_private *tp;
3194         struct mii_if_info *mii;
3195         struct net_device *dev;
3196         void __iomem *ioaddr;
3197         unsigned int i;
3198         int rc;
3199
3200         if (netif_msg_drv(&debug)) {
3201                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
3202                        MODULENAME, RTL8169_VERSION);
3203         }
3204
3205         dev = alloc_etherdev(sizeof (*tp));
3206         if (!dev) {
3207                 if (netif_msg_drv(&debug))
3208                         dev_err(&pdev->dev, "unable to alloc new ethernet\n");
3209                 rc = -ENOMEM;
3210                 goto out;
3211         }
3212
3213         SET_NETDEV_DEV(dev, &pdev->dev);
3214         dev->netdev_ops = &rtl8169_netdev_ops;
3215         tp = netdev_priv(dev);
3216         tp->dev = dev;
3217         tp->pci_dev = pdev;
3218         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
3219
3220         mii = &tp->mii;
3221         mii->dev = dev;
3222         mii->mdio_read = rtl_mdio_read;
3223         mii->mdio_write = rtl_mdio_write;
3224         mii->phy_id_mask = 0x1f;
3225         mii->reg_num_mask = 0x1f;
3226         mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3227
3228         /* disable ASPM completely as that cause random device stop working
3229          * problems as well as full system hangs for some PCIe devices users */
3230         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3231                                      PCIE_LINK_STATE_CLKPM);
3232
3233         /* enable device (incl. PCI PM wakeup and hotplug setup) */
3234         rc = pci_enable_device(pdev);
3235         if (rc < 0) {
3236                 netif_err(tp, probe, dev, "enable failure\n");
3237                 goto err_out_free_dev_1;
3238         }
3239
3240         if (pci_set_mwi(pdev) < 0)
3241                 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
3242
3243         /* make sure PCI base addr 1 is MMIO */
3244         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
3245                 netif_err(tp, probe, dev,
3246                           "region #%d not an MMIO resource, aborting\n",
3247                           region);
3248                 rc = -ENODEV;
3249                 goto err_out_mwi_2;
3250         }
3251
3252         /* check for weird/broken PCI region reporting */
3253         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
3254                 netif_err(tp, probe, dev,
3255                           "Invalid PCI region size(s), aborting\n");
3256                 rc = -ENODEV;
3257                 goto err_out_mwi_2;
3258         }
3259
3260         rc = pci_request_regions(pdev, MODULENAME);
3261         if (rc < 0) {
3262                 netif_err(tp, probe, dev, "could not request regions\n");
3263                 goto err_out_mwi_2;
3264         }
3265
3266         tp->cp_cmd = RxChkSum;
3267
3268         if ((sizeof(dma_addr_t) > 4) &&
3269             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
3270                 tp->cp_cmd |= PCIDAC;
3271                 dev->features |= NETIF_F_HIGHDMA;
3272         } else {
3273                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3274                 if (rc < 0) {
3275                         netif_err(tp, probe, dev, "DMA configuration failed\n");
3276                         goto err_out_free_res_3;
3277                 }
3278         }
3279
3280         /* ioremap MMIO region */
3281         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
3282         if (!ioaddr) {
3283                 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
3284                 rc = -EIO;
3285                 goto err_out_free_res_3;
3286         }
3287
3288         tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3289         if (!tp->pcie_cap)
3290                 netif_info(tp, probe, dev, "no PCI Express capability\n");
3291
3292         RTL_W16(IntrMask, 0x0000);
3293
3294         /* Soft reset the chip. */
3295         RTL_W8(ChipCmd, CmdReset);
3296
3297         /* Check that the chip has finished the reset. */
3298         for (i = 0; i < 100; i++) {
3299                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3300                         break;
3301                 msleep_interruptible(1);
3302         }
3303
3304         RTL_W16(IntrStatus, 0xffff);
3305
3306         pci_set_master(pdev);
3307
3308         /* Identify chip attached to board */
3309         rtl8169_get_mac_version(tp, ioaddr);
3310
3311         /*
3312          * Pretend we are using VLANs; This bypasses a nasty bug where
3313          * Interrupts stop flowing on high load on 8110SCd controllers.
3314          */
3315         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3316                 tp->cp_cmd |= RxVlan;
3317
3318         rtl_init_mdio_ops(tp);
3319         rtl_init_pll_power_ops(tp);
3320
3321         /* Use appropriate default if unknown */
3322         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
3323                 netif_notice(tp, probe, dev,
3324                              "unknown MAC, using family default\n");
3325                 tp->mac_version = cfg->default_ver;
3326         }
3327
3328         rtl8169_print_mac_version(tp);
3329
3330         for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
3331                 if (tp->mac_version == rtl_chip_info[i].mac_version)
3332                         break;
3333         }
3334         if (i == ARRAY_SIZE(rtl_chip_info)) {
3335                 dev_err(&pdev->dev,
3336                         "driver bug, MAC version not found in rtl_chip_info\n");
3337                 goto err_out_msi_4;
3338         }
3339         tp->chipset = i;
3340
3341         RTL_W8(Cfg9346, Cfg9346_Unlock);
3342         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3343         RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
3344         if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3345                 tp->features |= RTL_FEATURE_WOL;
3346         if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3347                 tp->features |= RTL_FEATURE_WOL;
3348         tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
3349         RTL_W8(Cfg9346, Cfg9346_Lock);
3350
3351         if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3352             (RTL_R8(PHYstatus) & TBI_Enable)) {
3353                 tp->set_speed = rtl8169_set_speed_tbi;
3354                 tp->get_settings = rtl8169_gset_tbi;
3355                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3356                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3357                 tp->link_ok = rtl8169_tbi_link_ok;
3358                 tp->do_ioctl = rtl_tbi_ioctl;
3359
3360                 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
3361         } else {
3362                 tp->set_speed = rtl8169_set_speed_xmii;
3363                 tp->get_settings = rtl8169_gset_xmii;
3364                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3365                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3366                 tp->link_ok = rtl8169_xmii_link_ok;
3367                 tp->do_ioctl = rtl_xmii_ioctl;
3368         }
3369
3370         spin_lock_init(&tp->lock);
3371
3372         tp->mmio_addr = ioaddr;
3373
3374         /* Get MAC address */
3375         for (i = 0; i < MAC_ADDR_LEN; i++)
3376                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
3377         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3378
3379         SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
3380         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3381         dev->irq = pdev->irq;
3382         dev->base_addr = (unsigned long) ioaddr;
3383
3384         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
3385
3386         /* don't enable SG, IP_CSUM and TSO by default - it might not work
3387          * properly for all devices */
3388         dev->features |= NETIF_F_RXCSUM |
3389                 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3390
3391         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3392                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3393         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3394                 NETIF_F_HIGHDMA;
3395
3396         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3397                 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
3398                 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
3399
3400         tp->intr_mask = 0xffff;
3401         tp->hw_start = cfg->hw_start;
3402         tp->intr_event = cfg->intr_event;
3403         tp->napi_event = cfg->napi_event;
3404
3405         init_timer(&tp->timer);
3406         tp->timer.data = (unsigned long) dev;
3407         tp->timer.function = rtl8169_phy_timer;
3408
3409         rc = register_netdev(dev);
3410         if (rc < 0)
3411                 goto err_out_msi_4;
3412
3413         pci_set_drvdata(pdev, dev);
3414
3415         netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
3416                    rtl_chip_info[tp->chipset].name,
3417                    dev->base_addr, dev->dev_addr,
3418                    (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
3419
3420         if ((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
3421             (tp->mac_version == RTL_GIGA_MAC_VER_28) ||
3422             (tp->mac_version == RTL_GIGA_MAC_VER_31)) {
3423                 rtl8168_driver_start(tp);
3424         }
3425
3426         device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
3427
3428         if (pci_dev_run_wake(pdev))
3429                 pm_runtime_put_noidle(&pdev->dev);
3430
3431         netif_carrier_off(dev);
3432
3433 out:
3434         return rc;
3435
3436 err_out_msi_4:
3437         rtl_disable_msi(pdev, tp);
3438         iounmap(ioaddr);
3439 err_out_free_res_3:
3440         pci_release_regions(pdev);
3441 err_out_mwi_2:
3442         pci_clear_mwi(pdev);
3443         pci_disable_device(pdev);
3444 err_out_free_dev_1:
3445         free_netdev(dev);
3446         goto out;
3447 }
3448
3449 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
3450 {
3451         struct net_device *dev = pci_get_drvdata(pdev);
3452         struct rtl8169_private *tp = netdev_priv(dev);
3453
3454         if ((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
3455             (tp->mac_version == RTL_GIGA_MAC_VER_28) ||
3456             (tp->mac_version == RTL_GIGA_MAC_VER_31)) {
3457                 rtl8168_driver_stop(tp);
3458         }
3459
3460         cancel_delayed_work_sync(&tp->task);
3461
3462         rtl_release_firmware(tp);
3463
3464         unregister_netdev(dev);
3465
3466         if (pci_dev_run_wake(pdev))
3467                 pm_runtime_get_noresume(&pdev->dev);
3468
3469         /* restore original MAC address */
3470         rtl_rar_set(tp, dev->perm_addr);
3471
3472         rtl_disable_msi(pdev, tp);
3473         rtl8169_release_board(pdev, dev, tp->mmio_addr);
3474         pci_set_drvdata(pdev, NULL);
3475 }
3476
3477 static int rtl8169_open(struct net_device *dev)
3478 {
3479         struct rtl8169_private *tp = netdev_priv(dev);
3480         void __iomem *ioaddr = tp->mmio_addr;
3481         struct pci_dev *pdev = tp->pci_dev;
3482         int retval = -ENOMEM;
3483
3484         pm_runtime_get_sync(&pdev->dev);
3485
3486         /*
3487          * Rx and Tx desscriptors needs 256 bytes alignment.
3488          * dma_alloc_coherent provides more.
3489          */
3490         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
3491                                              &tp->TxPhyAddr, GFP_KERNEL);
3492         if (!tp->TxDescArray)
3493                 goto err_pm_runtime_put;
3494
3495         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
3496                                              &tp->RxPhyAddr, GFP_KERNEL);
3497         if (!tp->RxDescArray)
3498                 goto err_free_tx_0;
3499
3500         retval = rtl8169_init_ring(dev);
3501         if (retval < 0)
3502                 goto err_free_rx_1;
3503
3504         INIT_DELAYED_WORK(&tp->task, NULL);
3505
3506         smp_mb();
3507
3508         retval = request_irq(dev->irq, rtl8169_interrupt,
3509                              (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
3510                              dev->name, dev);
3511         if (retval < 0)
3512                 goto err_release_ring_2;
3513
3514         napi_enable(&tp->napi);
3515
3516         rtl8169_init_phy(dev, tp);
3517
3518         rtl8169_set_features(dev, dev->features);
3519
3520         rtl_pll_power_up(tp);
3521
3522         rtl_hw_start(dev);
3523
3524         rtl8169_request_timer(dev);
3525
3526         tp->saved_wolopts = 0;
3527         pm_runtime_put_noidle(&pdev->dev);
3528
3529         rtl8169_check_link_status(dev, tp, ioaddr);
3530 out:
3531         return retval;
3532
3533 err_release_ring_2:
3534         rtl8169_rx_clear(tp);
3535 err_free_rx_1:
3536         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
3537                           tp->RxPhyAddr);
3538         tp->RxDescArray = NULL;
3539 err_free_tx_0:
3540         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
3541                           tp->TxPhyAddr);
3542         tp->TxDescArray = NULL;
3543 err_pm_runtime_put:
3544         pm_runtime_put_noidle(&pdev->dev);
3545         goto out;
3546 }
3547
3548 static void rtl8169_hw_reset(struct rtl8169_private *tp)
3549 {
3550         void __iomem *ioaddr = tp->mmio_addr;
3551
3552         /* Disable interrupts */
3553         rtl8169_irq_mask_and_ack(ioaddr);
3554
3555         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3556             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3557             tp->mac_version == RTL_GIGA_MAC_VER_31) {
3558                 while (RTL_R8(TxPoll) & NPQ)
3559                         udelay(20);
3560
3561         }
3562
3563         /* Reset the chipset */
3564         RTL_W8(ChipCmd, CmdReset);
3565
3566         /* PCI commit */
3567         RTL_R8(ChipCmd);
3568 }
3569
3570 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
3571 {
3572         void __iomem *ioaddr = tp->mmio_addr;
3573         u32 cfg = rtl8169_rx_config;
3574
3575         cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3576         RTL_W32(RxConfig, cfg);
3577
3578         /* Set DMA burst size and Interframe Gap Time */
3579         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3580                 (InterFrameGap << TxInterFrameGapShift));
3581 }
3582
3583 static void rtl_hw_start(struct net_device *dev)
3584 {
3585         struct rtl8169_private *tp = netdev_priv(dev);
3586         void __iomem *ioaddr = tp->mmio_addr;
3587         unsigned int i;
3588
3589         /* Soft reset the chip. */
3590         RTL_W8(ChipCmd, CmdReset);
3591
3592         /* Check that the chip has finished the reset. */
3593         for (i = 0; i < 100; i++) {
3594                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3595                         break;
3596                 msleep_interruptible(1);
3597         }
3598
3599         tp->hw_start(dev);
3600
3601         netif_start_queue(dev);
3602 }
3603
3604
3605 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3606                                          void __iomem *ioaddr)
3607 {
3608         /*
3609          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3610          * register to be written before TxDescAddrLow to work.
3611          * Switching from MMIO to I/O access fixes the issue as well.
3612          */
3613         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
3614         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
3615         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
3616         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
3617 }
3618
3619 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
3620 {
3621         u16 cmd;
3622
3623         cmd = RTL_R16(CPlusCmd);
3624         RTL_W16(CPlusCmd, cmd);
3625         return cmd;
3626 }
3627
3628 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
3629 {
3630         /* Low hurts. Let's disable the filtering. */
3631         RTL_W16(RxMaxSize, rx_buf_sz + 1);
3632 }
3633
3634 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
3635 {
3636         static const struct {
3637                 u32 mac_version;
3638                 u32 clk;
3639                 u32 val;
3640         } cfg2_info [] = {
3641                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
3642                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
3643                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
3644                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3645         }, *p = cfg2_info;
3646         unsigned int i;
3647         u32 clk;
3648
3649         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
3650         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
3651                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
3652                         RTL_W32(0x7c, p->val);
3653                         break;
3654                 }
3655         }
3656 }
3657
3658 static void rtl_hw_start_8169(struct net_device *dev)
3659 {
3660         struct rtl8169_private *tp = netdev_priv(dev);
3661         void __iomem *ioaddr = tp->mmio_addr;
3662         struct pci_dev *pdev = tp->pci_dev;
3663
3664         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
3665                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
3666                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
3667         }
3668
3669         RTL_W8(Cfg9346, Cfg9346_Unlock);
3670         if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3671             (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3672             (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3673             (tp->mac_version == RTL_GIGA_MAC_VER_04))
3674                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3675
3676         RTL_W8(EarlyTxThres, NoEarlyTx);
3677
3678         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
3679
3680         if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3681             (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3682             (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3683             (tp->mac_version == RTL_GIGA_MAC_VER_04))
3684                 rtl_set_rx_tx_config_registers(tp);
3685
3686         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3687
3688         if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3689             (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
3690                 dprintk("Set MAC Reg C+CR Offset 0xE0. "
3691                         "Bit-3 and bit-14 MUST be 1\n");
3692                 tp->cp_cmd |= (1 << 14);
3693         }
3694
3695         RTL_W16(CPlusCmd, tp->cp_cmd);
3696
3697         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
3698
3699         /*
3700          * Undocumented corner. Supposedly:
3701          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3702          */
3703         RTL_W16(IntrMitigate, 0x0000);
3704
3705         rtl_set_rx_tx_desc_registers(tp, ioaddr);
3706
3707         if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
3708             (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
3709             (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
3710             (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
3711                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3712                 rtl_set_rx_tx_config_registers(tp);
3713         }
3714
3715         RTL_W8(Cfg9346, Cfg9346_Lock);
3716
3717         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3718         RTL_R8(IntrMask);
3719
3720         RTL_W32(RxMissed, 0);
3721
3722         rtl_set_rx_mode(dev);
3723
3724         /* no early-rx interrupts */
3725         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
3726
3727         /* Enable all known interrupts by setting the interrupt mask. */
3728         RTL_W16(IntrMask, tp->intr_event);
3729 }
3730
3731 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
3732 {
3733         struct net_device *dev = pci_get_drvdata(pdev);
3734         struct rtl8169_private *tp = netdev_priv(dev);
3735         int cap = tp->pcie_cap;
3736
3737         if (cap) {
3738                 u16 ctl;
3739
3740                 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
3741                 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
3742                 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
3743         }
3744 }
3745
3746 static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
3747 {
3748         u32 csi;
3749
3750         csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
3751         rtl_csi_write(ioaddr, 0x070c, csi | bits);
3752 }
3753
3754 static void rtl_csi_access_enable_1(void __iomem *ioaddr)
3755 {
3756         rtl_csi_access_enable(ioaddr, 0x17000000);
3757 }
3758
3759 static void rtl_csi_access_enable_2(void __iomem *ioaddr)
3760 {
3761         rtl_csi_access_enable(ioaddr, 0x27000000);
3762 }
3763
3764 struct ephy_info {
3765         unsigned int offset;
3766         u16 mask;
3767         u16 bits;
3768 };
3769
3770 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
3771 {
3772         u16 w;
3773
3774         while (len-- > 0) {
3775                 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
3776                 rtl_ephy_write(ioaddr, e->offset, w);
3777                 e++;
3778         }
3779 }
3780
3781 static void rtl_disable_clock_request(struct pci_dev *pdev)
3782 {
3783         struct net_device *dev = pci_get_drvdata(pdev);
3784         struct rtl8169_private *tp = netdev_priv(dev);
3785         int cap = tp->pcie_cap;
3786
3787         if (cap) {
3788                 u16 ctl;
3789
3790                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3791                 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
3792                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3793         }
3794 }
3795
3796 static void rtl_enable_clock_request(struct pci_dev *pdev)
3797 {
3798         struct net_device *dev = pci_get_drvdata(pdev);
3799         struct rtl8169_private *tp = netdev_priv(dev);
3800         int cap = tp->pcie_cap;
3801
3802         if (cap) {
3803                 u16 ctl;
3804
3805                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3806                 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
3807                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3808         }
3809 }
3810
3811 #define R8168_CPCMD_QUIRK_MASK (\
3812         EnableBist | \
3813         Mac_dbgo_oe | \
3814         Force_half_dup | \
3815         Force_rxflow_en | \
3816         Force_txflow_en | \
3817         Cxpl_dbg_sel | \
3818         ASF | \
3819         PktCntrDisable | \
3820         Mac_dbgo_sel)
3821
3822 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
3823 {
3824         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3825
3826         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3827
3828         rtl_tx_performance_tweak(pdev,
3829                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3830 }
3831
3832 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
3833 {
3834         rtl_hw_start_8168bb(ioaddr, pdev);
3835
3836         RTL_W8(MaxTxPacketSize, TxPacketMax);
3837
3838         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
3839 }
3840
3841 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
3842 {
3843         RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
3844
3845         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3846
3847         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3848
3849         rtl_disable_clock_request(pdev);
3850
3851         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3852 }
3853
3854 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
3855 {
3856         static const struct ephy_info e_info_8168cp[] = {
3857                 { 0x01, 0,      0x0001 },
3858                 { 0x02, 0x0800, 0x1000 },
3859                 { 0x03, 0,      0x0042 },
3860                 { 0x06, 0x0080, 0x0000 },
3861                 { 0x07, 0,      0x2000 }
3862         };
3863
3864         rtl_csi_access_enable_2(ioaddr);
3865
3866         rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
3867
3868         __rtl_hw_start_8168cp(ioaddr, pdev);
3869 }
3870
3871 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
3872 {
3873         rtl_csi_access_enable_2(ioaddr);
3874
3875         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3876
3877         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3878
3879         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3880 }
3881
3882 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
3883 {
3884         rtl_csi_access_enable_2(ioaddr);
3885
3886         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3887
3888         /* Magic. */
3889         RTL_W8(DBG_REG, 0x20);
3890
3891         RTL_W8(MaxTxPacketSize, TxPacketMax);
3892
3893         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3894
3895         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3896 }
3897
3898 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
3899 {
3900         static const struct ephy_info e_info_8168c_1[] = {
3901                 { 0x02, 0x0800, 0x1000 },
3902                 { 0x03, 0,      0x0002 },
3903                 { 0x06, 0x0080, 0x0000 }
3904         };
3905
3906         rtl_csi_access_enable_2(ioaddr);
3907
3908         RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
3909
3910         rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
3911
3912         __rtl_hw_start_8168cp(ioaddr, pdev);
3913 }
3914
3915 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
3916 {
3917         static const struct ephy_info e_info_8168c_2[] = {
3918                 { 0x01, 0,      0x0001 },
3919                 { 0x03, 0x0400, 0x0220 }
3920         };
3921
3922         rtl_csi_access_enable_2(ioaddr);
3923
3924         rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
3925
3926         __rtl_hw_start_8168cp(ioaddr, pdev);
3927 }
3928
3929 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
3930 {
3931         rtl_hw_start_8168c_2(ioaddr, pdev);
3932 }
3933
3934 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
3935 {
3936         rtl_csi_access_enable_2(ioaddr);
3937
3938         __rtl_hw_start_8168cp(ioaddr, pdev);
3939 }
3940
3941 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
3942 {
3943         rtl_csi_access_enable_2(ioaddr);
3944
3945         rtl_disable_clock_request(pdev);
3946
3947         RTL_W8(MaxTxPacketSize, TxPacketMax);
3948
3949         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3950
3951         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3952 }
3953
3954 static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev)
3955 {
3956         rtl_csi_access_enable_1(ioaddr);
3957
3958         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3959
3960         RTL_W8(MaxTxPacketSize, TxPacketMax);
3961
3962         rtl_disable_clock_request(pdev);
3963 }
3964
3965 static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
3966 {
3967         static const struct ephy_info e_info_8168d_4[] = {
3968                 { 0x0b, ~0,     0x48 },
3969                 { 0x19, 0x20,   0x50 },
3970                 { 0x0c, ~0,     0x20 }
3971         };
3972         int i;
3973
3974         rtl_csi_access_enable_1(ioaddr);
3975
3976         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3977
3978         RTL_W8(MaxTxPacketSize, TxPacketMax);
3979
3980         for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
3981                 const struct ephy_info *e = e_info_8168d_4 + i;
3982                 u16 w;
3983
3984                 w = rtl_ephy_read(ioaddr, e->offset);
3985                 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
3986         }
3987
3988         rtl_enable_clock_request(pdev);
3989 }
3990
3991 static void rtl_hw_start_8168e(void __iomem *ioaddr, struct pci_dev *pdev)
3992 {
3993         static const struct ephy_info e_info_8168e[] = {
3994                 { 0x00, 0x0200, 0x0100 },
3995                 { 0x00, 0x0000, 0x0004 },
3996                 { 0x06, 0x0002, 0x0001 },
3997                 { 0x06, 0x0000, 0x0030 },
3998                 { 0x07, 0x0000, 0x2000 },
3999                 { 0x00, 0x0000, 0x0020 },
4000                 { 0x03, 0x5800, 0x2000 },
4001                 { 0x03, 0x0000, 0x0001 },
4002                 { 0x01, 0x0800, 0x1000 },
4003                 { 0x07, 0x0000, 0x4000 },
4004                 { 0x1e, 0x0000, 0x2000 },
4005                 { 0x19, 0xffff, 0xfe6c },
4006                 { 0x0a, 0x0000, 0x0040 }
4007         };
4008
4009         rtl_csi_access_enable_2(ioaddr);
4010
4011         rtl_ephy_init(ioaddr, e_info_8168e, ARRAY_SIZE(e_info_8168e));
4012
4013         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4014
4015         RTL_W8(MaxTxPacketSize, TxPacketMax);
4016
4017         rtl_disable_clock_request(pdev);
4018
4019         /* Reset tx FIFO pointer */
4020         RTL_W32(MISC, RTL_R32(MISC) | txpla_rst);
4021         RTL_W32(MISC, RTL_R32(MISC) & ~txpla_rst);
4022
4023         RTL_W8(Config5, RTL_R8(Config5) & ~spi_en);
4024 }
4025
4026 static void rtl_hw_start_8168(struct net_device *dev)
4027 {
4028         struct rtl8169_private *tp = netdev_priv(dev);
4029         void __iomem *ioaddr = tp->mmio_addr;
4030         struct pci_dev *pdev = tp->pci_dev;
4031
4032         RTL_W8(Cfg9346, Cfg9346_Unlock);
4033
4034         RTL_W8(MaxTxPacketSize, TxPacketMax);
4035
4036         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4037
4038         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
4039
4040         RTL_W16(CPlusCmd, tp->cp_cmd);
4041
4042         RTL_W16(IntrMitigate, 0x5151);
4043
4044         /* Work around for RxFIFO overflow. */
4045         if (tp->mac_version == RTL_GIGA_MAC_VER_11 ||
4046             tp->mac_version == RTL_GIGA_MAC_VER_22) {
4047                 tp->intr_event |= RxFIFOOver | PCSTimeout;
4048                 tp->intr_event &= ~RxOverflow;
4049         }
4050
4051         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4052
4053         rtl_set_rx_mode(dev);
4054
4055         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4056                 (InterFrameGap << TxInterFrameGapShift));
4057
4058         RTL_R8(IntrMask);
4059
4060         switch (tp->mac_version) {
4061         case RTL_GIGA_MAC_VER_11:
4062                 rtl_hw_start_8168bb(ioaddr, pdev);
4063                 break;
4064
4065         case RTL_GIGA_MAC_VER_12:
4066         case RTL_GIGA_MAC_VER_17:
4067                 rtl_hw_start_8168bef(ioaddr, pdev);
4068                 break;
4069
4070         case RTL_GIGA_MAC_VER_18:
4071                 rtl_hw_start_8168cp_1(ioaddr, pdev);
4072                 break;
4073
4074         case RTL_GIGA_MAC_VER_19:
4075                 rtl_hw_start_8168c_1(ioaddr, pdev);
4076                 break;
4077
4078         case RTL_GIGA_MAC_VER_20:
4079                 rtl_hw_start_8168c_2(ioaddr, pdev);
4080                 break;
4081
4082         case RTL_GIGA_MAC_VER_21:
4083                 rtl_hw_start_8168c_3(ioaddr, pdev);
4084                 break;
4085
4086         case RTL_GIGA_MAC_VER_22:
4087                 rtl_hw_start_8168c_4(ioaddr, pdev);
4088                 break;
4089
4090         case RTL_GIGA_MAC_VER_23:
4091                 rtl_hw_start_8168cp_2(ioaddr, pdev);
4092                 break;
4093
4094         case RTL_GIGA_MAC_VER_24:
4095                 rtl_hw_start_8168cp_3(ioaddr, pdev);
4096                 break;
4097
4098         case RTL_GIGA_MAC_VER_25:
4099         case RTL_GIGA_MAC_VER_26:
4100         case RTL_GIGA_MAC_VER_27:
4101                 rtl_hw_start_8168d(ioaddr, pdev);
4102                 break;
4103
4104         case RTL_GIGA_MAC_VER_28:
4105                 rtl_hw_start_8168d_4(ioaddr, pdev);
4106                 break;
4107         case RTL_GIGA_MAC_VER_31:
4108                 rtl_hw_start_8168dp(ioaddr, pdev);
4109                 break;
4110
4111         case RTL_GIGA_MAC_VER_32:
4112         case RTL_GIGA_MAC_VER_33:
4113                 rtl_hw_start_8168e(ioaddr, pdev);
4114                 break;
4115
4116         default:
4117                 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
4118                         dev->name, tp->mac_version);
4119                 break;
4120         }
4121
4122         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4123
4124         RTL_W8(Cfg9346, Cfg9346_Lock);
4125
4126         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4127
4128         RTL_W16(IntrMask, tp->intr_event);
4129 }
4130
4131 #define R810X_CPCMD_QUIRK_MASK (\
4132         EnableBist | \
4133         Mac_dbgo_oe | \
4134         Force_half_dup | \
4135         Force_rxflow_en | \
4136         Force_txflow_en | \
4137         Cxpl_dbg_sel | \
4138         ASF | \
4139         PktCntrDisable | \
4140         Mac_dbgo_sel)
4141
4142 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4143 {
4144         static const struct ephy_info e_info_8102e_1[] = {
4145                 { 0x01, 0, 0x6e65 },
4146                 { 0x02, 0, 0x091f },
4147                 { 0x03, 0, 0xc2f9 },
4148                 { 0x06, 0, 0xafb5 },
4149                 { 0x07, 0, 0x0e00 },
4150                 { 0x19, 0, 0xec80 },
4151                 { 0x01, 0, 0x2e65 },
4152                 { 0x01, 0, 0x6e65 }
4153         };
4154         u8 cfg1;
4155
4156         rtl_csi_access_enable_2(ioaddr);
4157
4158         RTL_W8(DBG_REG, FIX_NAK_1);
4159
4160         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4161
4162         RTL_W8(Config1,
4163                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
4164         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4165
4166         cfg1 = RTL_R8(Config1);
4167         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
4168                 RTL_W8(Config1, cfg1 & ~LEDS0);
4169
4170         rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
4171 }
4172
4173 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4174 {
4175         rtl_csi_access_enable_2(ioaddr);
4176
4177         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4178
4179         RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
4180         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4181 }
4182
4183 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
4184 {
4185         rtl_hw_start_8102e_2(ioaddr, pdev);
4186
4187         rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
4188 }
4189
4190 static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4191 {
4192         static const struct ephy_info e_info_8105e_1[] = {
4193                 { 0x07, 0, 0x4000 },
4194                 { 0x19, 0, 0x0200 },
4195                 { 0x19, 0, 0x0020 },
4196                 { 0x1e, 0, 0x2000 },
4197                 { 0x03, 0, 0x0001 },
4198                 { 0x19, 0, 0x0100 },
4199                 { 0x19, 0, 0x0004 },
4200                 { 0x0a, 0, 0x0020 }
4201         };
4202
4203         /* Force LAN exit from ASPM if Rx/Tx are not idel */
4204         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
4205
4206         /* disable Early Tally Counter */
4207         RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
4208
4209         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4210         RTL_W8(DLLPR, RTL_R8(DLLPR) | PM_SWITCH);
4211
4212         rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
4213 }
4214
4215 static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4216 {
4217         rtl_hw_start_8105e_1(ioaddr, pdev);
4218         rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
4219 }
4220
4221 static void rtl_hw_start_8101(struct net_device *dev)
4222 {
4223         struct rtl8169_private *tp = netdev_priv(dev);
4224         void __iomem *ioaddr = tp->mmio_addr;
4225         struct pci_dev *pdev = tp->pci_dev;
4226
4227         if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
4228             (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
4229                 int cap = tp->pcie_cap;
4230
4231                 if (cap) {
4232                         pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
4233                                               PCI_EXP_DEVCTL_NOSNOOP_EN);
4234                 }
4235         }
4236
4237         RTL_W8(Cfg9346, Cfg9346_Unlock);
4238
4239         switch (tp->mac_version) {
4240         case RTL_GIGA_MAC_VER_07:
4241                 rtl_hw_start_8102e_1(ioaddr, pdev);
4242                 break;
4243
4244         case RTL_GIGA_MAC_VER_08:
4245                 rtl_hw_start_8102e_3(ioaddr, pdev);
4246                 break;
4247
4248         case RTL_GIGA_MAC_VER_09:
4249                 rtl_hw_start_8102e_2(ioaddr, pdev);
4250                 break;
4251
4252         case RTL_GIGA_MAC_VER_29:
4253                 rtl_hw_start_8105e_1(ioaddr, pdev);
4254                 break;
4255         case RTL_GIGA_MAC_VER_30:
4256                 rtl_hw_start_8105e_2(ioaddr, pdev);
4257                 break;
4258         }
4259
4260         RTL_W8(Cfg9346, Cfg9346_Lock);
4261
4262         RTL_W8(MaxTxPacketSize, TxPacketMax);
4263
4264         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4265
4266         tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
4267         RTL_W16(CPlusCmd, tp->cp_cmd);
4268
4269         RTL_W16(IntrMitigate, 0x0000);
4270
4271         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4272
4273         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4274         rtl_set_rx_tx_config_registers(tp);
4275
4276         RTL_R8(IntrMask);
4277
4278         rtl_set_rx_mode(dev);
4279
4280         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
4281
4282         RTL_W16(IntrMask, tp->intr_event);
4283 }
4284
4285 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
4286 {
4287         if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
4288                 return -EINVAL;
4289
4290         dev->mtu = new_mtu;
4291         netdev_update_features(dev);
4292
4293         return 0;
4294 }
4295
4296 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
4297 {
4298         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
4299         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
4300 }
4301
4302 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
4303                                      void **data_buff, struct RxDesc *desc)
4304 {
4305         dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
4306                          DMA_FROM_DEVICE);
4307
4308         kfree(*data_buff);
4309         *data_buff = NULL;
4310         rtl8169_make_unusable_by_asic(desc);
4311 }
4312
4313 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
4314 {
4315         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
4316
4317         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
4318 }
4319
4320 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
4321                                        u32 rx_buf_sz)
4322 {
4323         desc->addr = cpu_to_le64(mapping);
4324         wmb();
4325         rtl8169_mark_to_asic(desc, rx_buf_sz);
4326 }
4327
4328 static inline void *rtl8169_align(void *data)
4329 {
4330         return (void *)ALIGN((long)data, 16);
4331 }
4332
4333 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
4334                                              struct RxDesc *desc)
4335 {
4336         void *data;
4337         dma_addr_t mapping;
4338         struct device *d = &tp->pci_dev->dev;
4339         struct net_device *dev = tp->dev;
4340         int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
4341
4342         data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
4343         if (!data)
4344                 return NULL;
4345
4346         if (rtl8169_align(data) != data) {
4347                 kfree(data);
4348                 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
4349                 if (!data)
4350                         return NULL;
4351         }
4352
4353         mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
4354                                  DMA_FROM_DEVICE);
4355         if (unlikely(dma_mapping_error(d, mapping))) {
4356                 if (net_ratelimit())
4357                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
4358                 goto err_out;
4359         }
4360
4361         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
4362         return data;
4363
4364 err_out:
4365         kfree(data);
4366         return NULL;
4367 }
4368
4369 static void rtl8169_rx_clear(struct rtl8169_private *tp)
4370 {
4371         unsigned int i;
4372
4373         for (i = 0; i < NUM_RX_DESC; i++) {
4374                 if (tp->Rx_databuff[i]) {
4375                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
4376                                             tp->RxDescArray + i);
4377                 }
4378         }
4379 }
4380
4381 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
4382 {
4383         desc->opts1 |= cpu_to_le32(RingEnd);
4384 }
4385
4386 static int rtl8169_rx_fill(struct rtl8169_private *tp)
4387 {
4388         unsigned int i;
4389
4390         for (i = 0; i < NUM_RX_DESC; i++) {
4391                 void *data;
4392
4393                 if (tp->Rx_databuff[i])
4394                         continue;
4395
4396                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
4397                 if (!data) {
4398                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
4399                         goto err_out;
4400                 }
4401                 tp->Rx_databuff[i] = data;
4402         }
4403
4404         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4405         return 0;
4406
4407 err_out:
4408         rtl8169_rx_clear(tp);
4409         return -ENOMEM;
4410 }
4411
4412 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4413 {
4414         tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
4415 }
4416
4417 static int rtl8169_init_ring(struct net_device *dev)
4418 {
4419         struct rtl8169_private *tp = netdev_priv(dev);
4420
4421         rtl8169_init_ring_indexes(tp);
4422
4423         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
4424         memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
4425
4426         return rtl8169_rx_fill(tp);
4427 }
4428
4429 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
4430                                  struct TxDesc *desc)
4431 {
4432         unsigned int len = tx_skb->len;
4433
4434         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
4435
4436         desc->opts1 = 0x00;
4437         desc->opts2 = 0x00;
4438         desc->addr = 0x00;
4439         tx_skb->len = 0;
4440 }
4441
4442 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4443                                    unsigned int n)
4444 {
4445         unsigned int i;
4446
4447         for (i = 0; i < n; i++) {
4448                 unsigned int entry = (start + i) % NUM_TX_DESC;
4449                 struct ring_info *tx_skb = tp->tx_skb + entry;
4450                 unsigned int len = tx_skb->len;
4451
4452                 if (len) {
4453                         struct sk_buff *skb = tx_skb->skb;
4454
4455                         rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4456                                              tp->TxDescArray + entry);
4457                         if (skb) {
4458                                 tp->dev->stats.tx_dropped++;
4459                                 dev_kfree_skb(skb);
4460                                 tx_skb->skb = NULL;
4461                         }
4462                 }
4463         }
4464 }
4465
4466 static void rtl8169_tx_clear(struct rtl8169_private *tp)
4467 {
4468         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
4469         tp->cur_tx = tp->dirty_tx = 0;
4470 }
4471
4472 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
4473 {
4474         struct rtl8169_private *tp = netdev_priv(dev);
4475
4476         PREPARE_DELAYED_WORK(&tp->task, task);
4477         schedule_delayed_work(&tp->task, 4);
4478 }
4479
4480 static void rtl8169_wait_for_quiescence(struct net_device *dev)
4481 {
4482         struct rtl8169_private *tp = netdev_priv(dev);
4483         void __iomem *ioaddr = tp->mmio_addr;
4484
4485         synchronize_irq(dev->irq);
4486
4487         /* Wait for any pending NAPI task to complete */
4488         napi_disable(&tp->napi);
4489
4490         rtl8169_irq_mask_and_ack(ioaddr);
4491
4492         tp->intr_mask = 0xffff;
4493         RTL_W16(IntrMask, tp->intr_event);
4494         napi_enable(&tp->napi);
4495 }
4496
4497 static void rtl8169_reinit_task(struct work_struct *work)
4498 {
4499         struct rtl8169_private *tp =
4500                 container_of(work, struct rtl8169_private, task.work);
4501         struct net_device *dev = tp->dev;
4502         int ret;
4503
4504         rtnl_lock();
4505
4506         if (!netif_running(dev))
4507                 goto out_unlock;
4508
4509         rtl8169_wait_for_quiescence(dev);
4510         rtl8169_close(dev);
4511
4512         ret = rtl8169_open(dev);
4513         if (unlikely(ret < 0)) {
4514                 if (net_ratelimit())
4515                         netif_err(tp, drv, dev,
4516                                   "reinit failure (status = %d). Rescheduling\n",
4517                                   ret);
4518                 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4519         }
4520
4521 out_unlock:
4522         rtnl_unlock();
4523 }
4524
4525 static void rtl8169_reset_task(struct work_struct *work)
4526 {
4527         struct rtl8169_private *tp =
4528                 container_of(work, struct rtl8169_private, task.work);
4529         struct net_device *dev = tp->dev;
4530
4531         rtnl_lock();
4532
4533         if (!netif_running(dev))
4534                 goto out_unlock;
4535
4536         rtl8169_wait_for_quiescence(dev);
4537
4538         rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
4539         rtl8169_tx_clear(tp);
4540
4541         if (tp->dirty_rx == tp->cur_rx) {
4542                 rtl8169_init_ring_indexes(tp);
4543                 rtl_hw_start(dev);
4544                 netif_wake_queue(dev);
4545                 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
4546         } else {
4547                 if (net_ratelimit())
4548                         netif_emerg(tp, intr, dev, "Rx buffers shortage\n");
4549                 rtl8169_schedule_work(dev, rtl8169_reset_task);
4550         }
4551
4552 out_unlock:
4553         rtnl_unlock();
4554 }
4555
4556 static void rtl8169_tx_timeout(struct net_device *dev)
4557 {
4558         struct rtl8169_private *tp = netdev_priv(dev);
4559
4560         rtl8169_hw_reset(tp);
4561
4562         /* Let's wait a bit while any (async) irq lands on */
4563         rtl8169_schedule_work(dev, rtl8169_reset_task);
4564 }
4565
4566 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4567                               u32 opts1)
4568 {
4569         struct skb_shared_info *info = skb_shinfo(skb);
4570         unsigned int cur_frag, entry;
4571         struct TxDesc * uninitialized_var(txd);
4572         struct device *d = &tp->pci_dev->dev;
4573
4574         entry = tp->cur_tx;
4575         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4576                 skb_frag_t *frag = info->frags + cur_frag;
4577                 dma_addr_t mapping;
4578                 u32 status, len;
4579                 void *addr;
4580
4581                 entry = (entry + 1) % NUM_TX_DESC;
4582
4583                 txd = tp->TxDescArray + entry;
4584                 len = frag->size;
4585                 addr = ((void *) page_address(frag->page)) + frag->page_offset;
4586                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
4587                 if (unlikely(dma_mapping_error(d, mapping))) {
4588                         if (net_ratelimit())
4589                                 netif_err(tp, drv, tp->dev,
4590                                           "Failed to map TX fragments DMA!\n");
4591                         goto err_out;
4592                 }
4593
4594                 /* anti gcc 2.95.3 bugware (sic) */
4595                 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4596
4597                 txd->opts1 = cpu_to_le32(status);
4598                 txd->addr = cpu_to_le64(mapping);
4599
4600                 tp->tx_skb[entry].len = len;
4601         }
4602
4603         if (cur_frag) {
4604                 tp->tx_skb[entry].skb = skb;
4605                 txd->opts1 |= cpu_to_le32(LastFrag);
4606         }
4607
4608         return cur_frag;
4609
4610 err_out:
4611         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4612         return -EIO;
4613 }
4614
4615 static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
4616 {
4617         u32 mss = skb_shinfo(skb)->gso_size;
4618
4619         if (mss)
4620                 return LargeSend | ((mss & MSSMask) << MSSShift);
4621
4622         if (skb->ip_summed == CHECKSUM_PARTIAL) {
4623                 const struct iphdr *ip = ip_hdr(skb);
4624
4625                 if (ip->protocol == IPPROTO_TCP)
4626                         return IPCS | TCPCS;
4627                 else if (ip->protocol == IPPROTO_UDP)
4628                         return IPCS | UDPCS;
4629                 WARN_ON(1);     /* we need a WARN() */
4630         }
4631         return 0;
4632 }
4633
4634 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4635                                       struct net_device *dev)
4636 {
4637         struct rtl8169_private *tp = netdev_priv(dev);
4638         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
4639         struct TxDesc *txd = tp->TxDescArray + entry;
4640         void __iomem *ioaddr = tp->mmio_addr;
4641         struct device *d = &tp->pci_dev->dev;
4642         dma_addr_t mapping;
4643         u32 status, len;
4644         u32 opts1;
4645         int frags;
4646
4647         if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
4648                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
4649                 goto err_stop_0;
4650         }
4651
4652         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
4653                 goto err_stop_0;
4654
4655         len = skb_headlen(skb);
4656         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
4657         if (unlikely(dma_mapping_error(d, mapping))) {
4658                 if (net_ratelimit())
4659                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
4660                 goto err_dma_0;
4661         }
4662
4663         tp->tx_skb[entry].len = len;
4664         txd->addr = cpu_to_le64(mapping);
4665         txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
4666
4667         opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
4668
4669         frags = rtl8169_xmit_frags(tp, skb, opts1);
4670         if (frags < 0)
4671                 goto err_dma_1;
4672         else if (frags)
4673                 opts1 |= FirstFrag;
4674         else {
4675                 opts1 |= FirstFrag | LastFrag;
4676                 tp->tx_skb[entry].skb = skb;
4677         }
4678
4679         wmb();
4680
4681         /* anti gcc 2.95.3 bugware (sic) */
4682         status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4683         txd->opts1 = cpu_to_le32(status);
4684
4685         tp->cur_tx += frags + 1;
4686
4687         wmb();
4688
4689         RTL_W8(TxPoll, NPQ);    /* set polling bit */
4690
4691         if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
4692                 netif_stop_queue(dev);
4693                 smp_rmb();
4694                 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
4695                         netif_wake_queue(dev);
4696         }
4697
4698         return NETDEV_TX_OK;
4699
4700 err_dma_1:
4701         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
4702 err_dma_0:
4703         dev_kfree_skb(skb);
4704         dev->stats.tx_dropped++;
4705         return NETDEV_TX_OK;
4706
4707 err_stop_0:
4708         netif_stop_queue(dev);
4709         dev->stats.tx_dropped++;
4710         return NETDEV_TX_BUSY;
4711 }
4712
4713 static void rtl8169_pcierr_interrupt(struct net_device *dev)
4714 {
4715         struct rtl8169_private *tp = netdev_priv(dev);
4716         struct pci_dev *pdev = tp->pci_dev;
4717         u16 pci_status, pci_cmd;
4718
4719         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4720         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
4721
4722         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
4723                   pci_cmd, pci_status);
4724
4725         /*
4726          * The recovery sequence below admits a very elaborated explanation:
4727          * - it seems to work;
4728          * - I did not see what else could be done;
4729          * - it makes iop3xx happy.
4730          *
4731          * Feel free to adjust to your needs.
4732          */
4733         if (pdev->broken_parity_status)
4734                 pci_cmd &= ~PCI_COMMAND_PARITY;
4735         else
4736                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
4737
4738         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
4739
4740         pci_write_config_word(pdev, PCI_STATUS,
4741                 pci_status & (PCI_STATUS_DETECTED_PARITY |
4742                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
4743                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
4744
4745         /* The infamous DAC f*ckup only happens at boot time */
4746         if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
4747                 void __iomem *ioaddr = tp->mmio_addr;
4748
4749                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
4750                 tp->cp_cmd &= ~PCIDAC;
4751                 RTL_W16(CPlusCmd, tp->cp_cmd);
4752                 dev->features &= ~NETIF_F_HIGHDMA;
4753         }
4754
4755         rtl8169_hw_reset(tp);
4756
4757         rtl8169_schedule_work(dev, rtl8169_reinit_task);
4758 }
4759
4760 static void rtl8169_tx_interrupt(struct net_device *dev,
4761                                  struct rtl8169_private *tp,
4762                                  void __iomem *ioaddr)
4763 {
4764         unsigned int dirty_tx, tx_left;
4765
4766         dirty_tx = tp->dirty_tx;
4767         smp_rmb();
4768         tx_left = tp->cur_tx - dirty_tx;
4769
4770         while (tx_left > 0) {
4771                 unsigned int entry = dirty_tx % NUM_TX_DESC;
4772                 struct ring_info *tx_skb = tp->tx_skb + entry;
4773                 u32 status;
4774
4775                 rmb();
4776                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4777                 if (status & DescOwn)
4778                         break;
4779
4780                 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4781                                      tp->TxDescArray + entry);
4782                 if (status & LastFrag) {
4783                         dev->stats.tx_packets++;
4784                         dev->stats.tx_bytes += tx_skb->skb->len;
4785                         dev_kfree_skb(tx_skb->skb);
4786                         tx_skb->skb = NULL;
4787                 }
4788                 dirty_tx++;
4789                 tx_left--;
4790         }
4791
4792         if (tp->dirty_tx != dirty_tx) {
4793                 tp->dirty_tx = dirty_tx;
4794                 smp_wmb();
4795                 if (netif_queue_stopped(dev) &&
4796                     (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
4797                         netif_wake_queue(dev);
4798                 }
4799                 /*
4800                  * 8168 hack: TxPoll requests are lost when the Tx packets are
4801                  * too close. Let's kick an extra TxPoll request when a burst
4802                  * of start_xmit activity is detected (if it is not detected,
4803                  * it is slow enough). -- FR
4804                  */
4805                 smp_rmb();
4806                 if (tp->cur_tx != dirty_tx)
4807                         RTL_W8(TxPoll, NPQ);
4808         }
4809 }
4810
4811 static inline int rtl8169_fragmented_frame(u32 status)
4812 {
4813         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4814 }
4815
4816 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
4817 {
4818         u32 status = opts1 & RxProtoMask;
4819
4820         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
4821             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
4822                 skb->ip_summed = CHECKSUM_UNNECESSARY;
4823         else
4824                 skb_checksum_none_assert(skb);
4825 }
4826
4827 static struct sk_buff *rtl8169_try_rx_copy(void *data,
4828                                            struct rtl8169_private *tp,
4829                                            int pkt_size,
4830                                            dma_addr_t addr)
4831 {
4832         struct sk_buff *skb;
4833         struct device *d = &tp->pci_dev->dev;
4834
4835         data = rtl8169_align(data);
4836         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
4837         prefetch(data);
4838         skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
4839         if (skb)
4840                 memcpy(skb->data, data, pkt_size);
4841         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
4842
4843         return skb;
4844 }
4845
4846 /*
4847  * Warning : rtl8169_rx_interrupt() might be called :
4848  * 1) from NAPI (softirq) context
4849  *      (polling = 1 : we should call netif_receive_skb())
4850  * 2) from process context (rtl8169_reset_task())
4851  *      (polling = 0 : we must call netif_rx() instead)
4852  */
4853 static int rtl8169_rx_interrupt(struct net_device *dev,
4854                                 struct rtl8169_private *tp,
4855                                 void __iomem *ioaddr, u32 budget)
4856 {
4857         unsigned int cur_rx, rx_left;
4858         unsigned int count;
4859         int polling = (budget != ~(u32)0) ? 1 : 0;
4860
4861         cur_rx = tp->cur_rx;
4862         rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
4863         rx_left = min(rx_left, budget);
4864
4865         for (; rx_left > 0; rx_left--, cur_rx++) {
4866                 unsigned int entry = cur_rx % NUM_RX_DESC;
4867                 struct RxDesc *desc = tp->RxDescArray + entry;
4868                 u32 status;
4869
4870                 rmb();
4871                 status = le32_to_cpu(desc->opts1);
4872
4873                 if (status & DescOwn)
4874                         break;
4875                 if (unlikely(status & RxRES)) {
4876                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
4877                                    status);
4878                         dev->stats.rx_errors++;
4879                         if (status & (RxRWT | RxRUNT))
4880                                 dev->stats.rx_length_errors++;
4881                         if (status & RxCRC)
4882                                 dev->stats.rx_crc_errors++;
4883                         if (status & RxFOVF) {
4884                                 rtl8169_schedule_work(dev, rtl8169_reset_task);
4885                                 dev->stats.rx_fifo_errors++;
4886                         }
4887                         rtl8169_mark_to_asic(desc, rx_buf_sz);
4888                 } else {
4889                         struct sk_buff *skb;
4890                         dma_addr_t addr = le64_to_cpu(desc->addr);
4891                         int pkt_size = (status & 0x00001FFF) - 4;
4892
4893                         /*
4894                          * The driver does not support incoming fragmented
4895                          * frames. They are seen as a symptom of over-mtu
4896                          * sized frames.
4897                          */
4898                         if (unlikely(rtl8169_fragmented_frame(status))) {
4899                                 dev->stats.rx_dropped++;
4900                                 dev->stats.rx_length_errors++;
4901                                 rtl8169_mark_to_asic(desc, rx_buf_sz);
4902                                 continue;
4903                         }
4904
4905                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
4906                                                   tp, pkt_size, addr);
4907                         rtl8169_mark_to_asic(desc, rx_buf_sz);
4908                         if (!skb) {
4909                                 dev->stats.rx_dropped++;
4910                                 continue;
4911                         }
4912
4913                         rtl8169_rx_csum(skb, status);
4914                         skb_put(skb, pkt_size);
4915                         skb->protocol = eth_type_trans(skb, dev);
4916
4917                         rtl8169_rx_vlan_tag(desc, skb);
4918
4919                         if (likely(polling))
4920                                 napi_gro_receive(&tp->napi, skb);
4921                         else
4922                                 netif_rx(skb);
4923
4924                         dev->stats.rx_bytes += pkt_size;
4925                         dev->stats.rx_packets++;
4926                 }
4927
4928                 /* Work around for AMD plateform. */
4929                 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
4930                     (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
4931                         desc->opts2 = 0;
4932                         cur_rx++;
4933                 }
4934         }
4935
4936         count = cur_rx - tp->cur_rx;
4937         tp->cur_rx = cur_rx;
4938
4939         tp->dirty_rx += count;
4940
4941         return count;
4942 }
4943
4944 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
4945 {
4946         struct net_device *dev = dev_instance;
4947         struct rtl8169_private *tp = netdev_priv(dev);
4948         void __iomem *ioaddr = tp->mmio_addr;
4949         int handled = 0;
4950         int status;
4951
4952         /* loop handling interrupts until we have no new ones or
4953          * we hit a invalid/hotplug case.
4954          */
4955         status = RTL_R16(IntrStatus);
4956         while (status && status != 0xffff) {
4957                 handled = 1;
4958
4959                 /* Handle all of the error cases first. These will reset
4960                  * the chip, so just exit the loop.
4961                  */
4962                 if (unlikely(!netif_running(dev))) {
4963                         rtl8169_asic_down(ioaddr);
4964                         break;
4965                 }
4966
4967                 if (unlikely(status & RxFIFOOver)) {
4968                         switch (tp->mac_version) {
4969                         /* Work around for rx fifo overflow */
4970                         case RTL_GIGA_MAC_VER_11:
4971                         case RTL_GIGA_MAC_VER_22:
4972                         case RTL_GIGA_MAC_VER_26:
4973                                 netif_stop_queue(dev);
4974                                 rtl8169_tx_timeout(dev);
4975                                 goto done;
4976                         /* Testers needed. */
4977                         case RTL_GIGA_MAC_VER_17:
4978                         case RTL_GIGA_MAC_VER_19:
4979                         case RTL_GIGA_MAC_VER_20:
4980                         case RTL_GIGA_MAC_VER_21:
4981                         case RTL_GIGA_MAC_VER_23:
4982                         case RTL_GIGA_MAC_VER_24:
4983                         case RTL_GIGA_MAC_VER_27:
4984                         case RTL_GIGA_MAC_VER_28:
4985                         case RTL_GIGA_MAC_VER_31:
4986                         /* Experimental science. Pktgen proof. */
4987                         case RTL_GIGA_MAC_VER_12:
4988                         case RTL_GIGA_MAC_VER_25:
4989                                 if (status == RxFIFOOver)
4990                                         goto done;
4991                                 break;
4992                         default:
4993                                 break;
4994                         }
4995                 }
4996
4997                 if (unlikely(status & SYSErr)) {
4998                         rtl8169_pcierr_interrupt(dev);
4999                         break;
5000                 }
5001
5002                 if (status & LinkChg)
5003                         __rtl8169_check_link_status(dev, tp, ioaddr, true);
5004
5005                 /* We need to see the lastest version of tp->intr_mask to
5006                  * avoid ignoring an MSI interrupt and having to wait for
5007                  * another event which may never come.
5008                  */
5009                 smp_rmb();
5010                 if (status & tp->intr_mask & tp->napi_event) {
5011                         RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
5012                         tp->intr_mask = ~tp->napi_event;
5013
5014                         if (likely(napi_schedule_prep(&tp->napi)))
5015                                 __napi_schedule(&tp->napi);
5016                         else
5017                                 netif_info(tp, intr, dev,
5018                                            "interrupt %04x in poll\n", status);
5019                 }
5020
5021                 /* We only get a new MSI interrupt when all active irq
5022                  * sources on the chip have been acknowledged. So, ack
5023                  * everything we've seen and check if new sources have become
5024                  * active to avoid blocking all interrupts from the chip.
5025                  */
5026                 RTL_W16(IntrStatus,
5027                         (status & RxFIFOOver) ? (status | RxOverflow) : status);
5028                 status = RTL_R16(IntrStatus);
5029         }
5030 done:
5031         return IRQ_RETVAL(handled);
5032 }
5033
5034 static int rtl8169_poll(struct napi_struct *napi, int budget)
5035 {
5036         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5037         struct net_device *dev = tp->dev;
5038         void __iomem *ioaddr = tp->mmio_addr;
5039         int work_done;
5040
5041         work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
5042         rtl8169_tx_interrupt(dev, tp, ioaddr);
5043
5044         if (work_done < budget) {
5045                 napi_complete(napi);
5046
5047                 /* We need for force the visibility of tp->intr_mask
5048                  * for other CPUs, as we can loose an MSI interrupt
5049                  * and potentially wait for a retransmit timeout if we don't.
5050                  * The posted write to IntrMask is safe, as it will
5051                  * eventually make it to the chip and we won't loose anything
5052                  * until it does.
5053                  */
5054                 tp->intr_mask = 0xffff;
5055                 wmb();
5056                 RTL_W16(IntrMask, tp->intr_event);
5057         }
5058
5059         return work_done;
5060 }
5061
5062 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
5063 {
5064         struct rtl8169_private *tp = netdev_priv(dev);
5065
5066         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5067                 return;
5068
5069         dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
5070         RTL_W32(RxMissed, 0);
5071 }
5072
5073 static void rtl8169_down(struct net_device *dev)
5074 {
5075         struct rtl8169_private *tp = netdev_priv(dev);
5076         void __iomem *ioaddr = tp->mmio_addr;
5077
5078         rtl8169_delete_timer(dev);
5079
5080         netif_stop_queue(dev);
5081
5082         napi_disable(&tp->napi);
5083
5084         spin_lock_irq(&tp->lock);
5085
5086         rtl8169_asic_down(ioaddr);
5087         /*
5088          * At this point device interrupts can not be enabled in any function,
5089          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
5090          * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
5091          */
5092         rtl8169_rx_missed(dev, ioaddr);
5093
5094         spin_unlock_irq(&tp->lock);
5095
5096         synchronize_irq(dev->irq);
5097
5098         /* Give a racing hard_start_xmit a few cycles to complete. */
5099         synchronize_sched();  /* FIXME: should this be synchronize_irq()? */
5100
5101         rtl8169_tx_clear(tp);
5102
5103         rtl8169_rx_clear(tp);
5104
5105         rtl_pll_power_down(tp);
5106 }
5107
5108 static int rtl8169_close(struct net_device *dev)
5109 {
5110         struct rtl8169_private *tp = netdev_priv(dev);
5111         struct pci_dev *pdev = tp->pci_dev;
5112
5113         pm_runtime_get_sync(&pdev->dev);
5114
5115         /* update counters before going down */
5116         rtl8169_update_counters(dev);
5117
5118         rtl8169_down(dev);
5119
5120         free_irq(dev->irq, dev);
5121
5122         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5123                           tp->RxPhyAddr);
5124         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5125                           tp->TxPhyAddr);
5126         tp->TxDescArray = NULL;
5127         tp->RxDescArray = NULL;
5128
5129         pm_runtime_put_sync(&pdev->dev);
5130
5131         return 0;
5132 }
5133
5134 static void rtl_set_rx_mode(struct net_device *dev)
5135 {
5136         struct rtl8169_private *tp = netdev_priv(dev);
5137         void __iomem *ioaddr = tp->mmio_addr;
5138         unsigned long flags;
5139         u32 mc_filter[2];       /* Multicast hash filter */
5140         int rx_mode;
5141         u32 tmp = 0;
5142
5143         if (dev->flags & IFF_PROMISC) {
5144                 /* Unconditionally log net taps. */
5145                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
5146                 rx_mode =
5147                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5148                     AcceptAllPhys;
5149                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5150         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
5151                    (dev->flags & IFF_ALLMULTI)) {
5152                 /* Too many to filter perfectly -- accept all multicasts. */
5153                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5154                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5155         } else {
5156                 struct netdev_hw_addr *ha;
5157
5158                 rx_mode = AcceptBroadcast | AcceptMyPhys;
5159                 mc_filter[1] = mc_filter[0] = 0;
5160                 netdev_for_each_mc_addr(ha, dev) {
5161                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
5162                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5163                         rx_mode |= AcceptMulticast;
5164                 }
5165         }
5166
5167         spin_lock_irqsave(&tp->lock, flags);
5168
5169         tmp = rtl8169_rx_config | rx_mode |
5170               (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
5171
5172         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
5173                 u32 data = mc_filter[0];
5174
5175                 mc_filter[0] = swab32(mc_filter[1]);
5176                 mc_filter[1] = swab32(data);
5177         }
5178
5179         RTL_W32(MAR0 + 4, mc_filter[1]);
5180         RTL_W32(MAR0 + 0, mc_filter[0]);
5181
5182         RTL_W32(RxConfig, tmp);
5183
5184         spin_unlock_irqrestore(&tp->lock, flags);
5185 }
5186
5187 /**
5188  *  rtl8169_get_stats - Get rtl8169 read/write statistics
5189  *  @dev: The Ethernet Device to get statistics for
5190  *
5191  *  Get TX/RX statistics for rtl8169
5192  */
5193 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
5194 {
5195         struct rtl8169_private *tp = netdev_priv(dev);
5196         void __iomem *ioaddr = tp->mmio_addr;
5197         unsigned long flags;
5198
5199         if (netif_running(dev)) {
5200                 spin_lock_irqsave(&tp->lock, flags);
5201                 rtl8169_rx_missed(dev, ioaddr);
5202                 spin_unlock_irqrestore(&tp->lock, flags);
5203         }
5204
5205         return &dev->stats;
5206 }
5207
5208 static void rtl8169_net_suspend(struct net_device *dev)
5209 {
5210         struct rtl8169_private *tp = netdev_priv(dev);
5211
5212         if (!netif_running(dev))
5213                 return;
5214
5215         rtl_pll_power_down(tp);
5216
5217         netif_device_detach(dev);
5218         netif_stop_queue(dev);
5219 }
5220
5221 #ifdef CONFIG_PM
5222
5223 static int rtl8169_suspend(struct device *device)
5224 {
5225         struct pci_dev *pdev = to_pci_dev(device);
5226         struct net_device *dev = pci_get_drvdata(pdev);
5227
5228         rtl8169_net_suspend(dev);
5229
5230         return 0;
5231 }
5232
5233 static void __rtl8169_resume(struct net_device *dev)
5234 {
5235         struct rtl8169_private *tp = netdev_priv(dev);
5236
5237         netif_device_attach(dev);
5238
5239         rtl_pll_power_up(tp);
5240
5241         rtl8169_schedule_work(dev, rtl8169_reset_task);
5242 }
5243
5244 static int rtl8169_resume(struct device *device)
5245 {
5246         struct pci_dev *pdev = to_pci_dev(device);
5247         struct net_device *dev = pci_get_drvdata(pdev);
5248         struct rtl8169_private *tp = netdev_priv(dev);
5249
5250         rtl8169_init_phy(dev, tp);
5251
5252         if (netif_running(dev))
5253                 __rtl8169_resume(dev);
5254
5255         return 0;
5256 }
5257
5258 static int rtl8169_runtime_suspend(struct device *device)
5259 {
5260         struct pci_dev *pdev = to_pci_dev(device);
5261         struct net_device *dev = pci_get_drvdata(pdev);
5262         struct rtl8169_private *tp = netdev_priv(dev);
5263
5264         if (!tp->TxDescArray)
5265                 return 0;
5266
5267         spin_lock_irq(&tp->lock);
5268         tp->saved_wolopts = __rtl8169_get_wol(tp);
5269         __rtl8169_set_wol(tp, WAKE_ANY);
5270         spin_unlock_irq(&tp->lock);
5271
5272         rtl8169_net_suspend(dev);
5273
5274         return 0;
5275 }
5276
5277 static int rtl8169_runtime_resume(struct device *device)
5278 {
5279         struct pci_dev *pdev = to_pci_dev(device);
5280         struct net_device *dev = pci_get_drvdata(pdev);
5281         struct rtl8169_private *tp = netdev_priv(dev);
5282
5283         if (!tp->TxDescArray)
5284                 return 0;
5285
5286         spin_lock_irq(&tp->lock);
5287         __rtl8169_set_wol(tp, tp->saved_wolopts);
5288         tp->saved_wolopts = 0;
5289         spin_unlock_irq(&tp->lock);
5290
5291         rtl8169_init_phy(dev, tp);
5292
5293         __rtl8169_resume(dev);
5294
5295         return 0;
5296 }
5297
5298 static int rtl8169_runtime_idle(struct device *device)
5299 {
5300         struct pci_dev *pdev = to_pci_dev(device);
5301         struct net_device *dev = pci_get_drvdata(pdev);
5302         struct rtl8169_private *tp = netdev_priv(dev);
5303
5304         return tp->TxDescArray ? -EBUSY : 0;
5305 }
5306
5307 static const struct dev_pm_ops rtl8169_pm_ops = {
5308         .suspend = rtl8169_suspend,
5309         .resume = rtl8169_resume,
5310         .freeze = rtl8169_suspend,
5311         .thaw = rtl8169_resume,
5312         .poweroff = rtl8169_suspend,
5313         .restore = rtl8169_resume,
5314         .runtime_suspend = rtl8169_runtime_suspend,
5315         .runtime_resume = rtl8169_runtime_resume,
5316         .runtime_idle = rtl8169_runtime_idle,
5317 };
5318
5319 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
5320
5321 #else /* !CONFIG_PM */
5322
5323 #define RTL8169_PM_OPS  NULL
5324
5325 #endif /* !CONFIG_PM */
5326
5327 static void rtl_shutdown(struct pci_dev *pdev)
5328 {
5329         struct net_device *dev = pci_get_drvdata(pdev);
5330         struct rtl8169_private *tp = netdev_priv(dev);
5331         void __iomem *ioaddr = tp->mmio_addr;
5332
5333         rtl8169_net_suspend(dev);
5334
5335         /* restore original MAC address */
5336         rtl_rar_set(tp, dev->perm_addr);
5337
5338         spin_lock_irq(&tp->lock);
5339
5340         rtl8169_asic_down(ioaddr);
5341
5342         spin_unlock_irq(&tp->lock);
5343
5344         if (system_state == SYSTEM_POWER_OFF) {
5345                 /* WoL fails with some 8168 when the receiver is disabled. */
5346                 if (tp->features & RTL_FEATURE_WOL) {
5347                         pci_clear_master(pdev);
5348
5349                         RTL_W8(ChipCmd, CmdRxEnb);
5350                         /* PCI commit */
5351                         RTL_R8(ChipCmd);
5352                 }
5353
5354                 pci_wake_from_d3(pdev, true);
5355                 pci_set_power_state(pdev, PCI_D3hot);
5356         }
5357 }
5358
5359 static struct pci_driver rtl8169_pci_driver = {
5360         .name           = MODULENAME,
5361         .id_table       = rtl8169_pci_tbl,
5362         .probe          = rtl8169_init_one,
5363         .remove         = __devexit_p(rtl8169_remove_one),
5364         .shutdown       = rtl_shutdown,
5365         .driver.pm      = RTL8169_PM_OPS,
5366 };
5367
5368 static int __init rtl8169_init_module(void)
5369 {
5370         return pci_register_driver(&rtl8169_pci_driver);
5371 }
5372
5373 static void __exit rtl8169_cleanup_module(void)
5374 {
5375         pci_unregister_driver(&rtl8169_pci_driver);
5376 }
5377
5378 module_init(rtl8169_init_module);
5379 module_exit(rtl8169_cleanup_module);