2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/firmware.h>
29 #include <linux/pci-aspm.h>
30 #include <linux/prefetch.h>
32 #include <asm/system.h>
36 #define RTL8169_VERSION "2.3LK-NAPI"
37 #define MODULENAME "r8169"
38 #define PFX MODULENAME ": "
40 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
41 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
42 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
43 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
44 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
45 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
48 #define assert(expr) \
50 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
51 #expr,__FILE__,__func__,__LINE__); \
53 #define dprintk(fmt, args...) \
54 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
56 #define assert(expr) do {} while (0)
57 #define dprintk(fmt, args...) do {} while (0)
58 #endif /* RTL8169_DEBUG */
60 #define R8169_MSG_DEFAULT \
61 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
63 #define TX_BUFFS_AVAIL(tp) \
64 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
66 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
67 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
68 static const int multicast_filter_limit = 32;
70 /* MAC address length */
71 #define MAC_ADDR_LEN 6
73 #define MAX_READ_REQUEST_SHIFT 12
74 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
75 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
76 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
78 #define R8169_REGS_SIZE 256
79 #define R8169_NAPI_WEIGHT 64
80 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
81 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
82 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
83 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
84 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
86 #define RTL8169_TX_TIMEOUT (6*HZ)
87 #define RTL8169_PHY_TIMEOUT (10*HZ)
89 #define RTL_EEPROM_SIG cpu_to_le32(0x8129)
90 #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
91 #define RTL_EEPROM_SIG_ADDR 0x0000
93 /* write/read MMIO register */
94 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
95 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
96 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
97 #define RTL_R8(reg) readb (ioaddr + (reg))
98 #define RTL_R16(reg) readw (ioaddr + (reg))
99 #define RTL_R32(reg) readl (ioaddr + (reg))
102 RTL_GIGA_MAC_VER_01 = 0,
136 RTL_GIGA_MAC_NONE = 0xff,
139 enum rtl_tx_desc_version {
144 #define _R(NAME,TD,FW) \
145 { .name = NAME, .txd_version = TD, .fw_name = FW }
147 static const struct {
149 enum rtl_tx_desc_version txd_version;
151 } rtl_chip_infos[] = {
153 [RTL_GIGA_MAC_VER_01] =
154 _R("RTL8169", RTL_TD_0, NULL),
155 [RTL_GIGA_MAC_VER_02] =
156 _R("RTL8169s", RTL_TD_0, NULL),
157 [RTL_GIGA_MAC_VER_03] =
158 _R("RTL8110s", RTL_TD_0, NULL),
159 [RTL_GIGA_MAC_VER_04] =
160 _R("RTL8169sb/8110sb", RTL_TD_0, NULL),
161 [RTL_GIGA_MAC_VER_05] =
162 _R("RTL8169sc/8110sc", RTL_TD_0, NULL),
163 [RTL_GIGA_MAC_VER_06] =
164 _R("RTL8169sc/8110sc", RTL_TD_0, NULL),
166 [RTL_GIGA_MAC_VER_07] =
167 _R("RTL8102e", RTL_TD_1, NULL),
168 [RTL_GIGA_MAC_VER_08] =
169 _R("RTL8102e", RTL_TD_1, NULL),
170 [RTL_GIGA_MAC_VER_09] =
171 _R("RTL8102e", RTL_TD_1, NULL),
172 [RTL_GIGA_MAC_VER_10] =
173 _R("RTL8101e", RTL_TD_0, NULL),
174 [RTL_GIGA_MAC_VER_11] =
175 _R("RTL8168b/8111b", RTL_TD_0, NULL),
176 [RTL_GIGA_MAC_VER_12] =
177 _R("RTL8168b/8111b", RTL_TD_0, NULL),
178 [RTL_GIGA_MAC_VER_13] =
179 _R("RTL8101e", RTL_TD_0, NULL),
180 [RTL_GIGA_MAC_VER_14] =
181 _R("RTL8100e", RTL_TD_0, NULL),
182 [RTL_GIGA_MAC_VER_15] =
183 _R("RTL8100e", RTL_TD_0, NULL),
184 [RTL_GIGA_MAC_VER_16] =
185 _R("RTL8101e", RTL_TD_0, NULL),
186 [RTL_GIGA_MAC_VER_17] =
187 _R("RTL8168b/8111b", RTL_TD_0, NULL),
188 [RTL_GIGA_MAC_VER_18] =
189 _R("RTL8168cp/8111cp", RTL_TD_1, NULL),
190 [RTL_GIGA_MAC_VER_19] =
191 _R("RTL8168c/8111c", RTL_TD_1, NULL),
192 [RTL_GIGA_MAC_VER_20] =
193 _R("RTL8168c/8111c", RTL_TD_1, NULL),
194 [RTL_GIGA_MAC_VER_21] =
195 _R("RTL8168c/8111c", RTL_TD_1, NULL),
196 [RTL_GIGA_MAC_VER_22] =
197 _R("RTL8168c/8111c", RTL_TD_1, NULL),
198 [RTL_GIGA_MAC_VER_23] =
199 _R("RTL8168cp/8111cp", RTL_TD_1, NULL),
200 [RTL_GIGA_MAC_VER_24] =
201 _R("RTL8168cp/8111cp", RTL_TD_1, NULL),
202 [RTL_GIGA_MAC_VER_25] =
203 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1),
204 [RTL_GIGA_MAC_VER_26] =
205 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2),
206 [RTL_GIGA_MAC_VER_27] =
207 _R("RTL8168dp/8111dp", RTL_TD_1, NULL),
208 [RTL_GIGA_MAC_VER_28] =
209 _R("RTL8168dp/8111dp", RTL_TD_1, NULL),
210 [RTL_GIGA_MAC_VER_29] =
211 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1),
212 [RTL_GIGA_MAC_VER_30] =
213 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1),
214 [RTL_GIGA_MAC_VER_31] =
215 _R("RTL8168dp/8111dp", RTL_TD_1, NULL),
216 [RTL_GIGA_MAC_VER_32] =
217 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1),
218 [RTL_GIGA_MAC_VER_33] =
219 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2),
220 [RTL_GIGA_MAC_VER_34] =
221 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3)
231 static void rtl_hw_start_8169(struct net_device *);
232 static void rtl_hw_start_8168(struct net_device *);
233 static void rtl_hw_start_8101(struct net_device *);
235 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
236 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
237 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
238 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
239 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
240 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
241 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
242 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
243 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
244 { PCI_VENDOR_ID_LINKSYS, 0x1032,
245 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
247 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
251 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
253 static int rx_buf_sz = 16383;
260 MAC0 = 0, /* Ethernet hardware address. */
262 MAR0 = 8, /* Multicast filter. */
263 CounterAddrLow = 0x10,
264 CounterAddrHigh = 0x14,
265 TxDescStartAddrLow = 0x20,
266 TxDescStartAddrHigh = 0x24,
267 TxHDescStartAddrLow = 0x28,
268 TxHDescStartAddrHigh = 0x2c,
277 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
278 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
281 #define RX128_INT_EN (1 << 15) /* 8111c and later */
282 #define RX_MULTI_EN (1 << 14) /* 8111c only */
283 #define RXCFG_FIFO_SHIFT 13
284 /* No threshold before first PCI xfer */
285 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
286 #define RXCFG_DMA_SHIFT 8
287 /* Unlimited maximum PCI burst. */
288 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
289 #define RTL_RX_CONFIG_MASK 0xff7e1880u
305 RxDescAddrLow = 0xe4,
306 RxDescAddrHigh = 0xe8,
307 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
309 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
311 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
313 #define TxPacketMax (8064 >> 7)
316 FuncEventMask = 0xf4,
317 FuncPresetState = 0xf8,
318 FuncForceEvent = 0xfc,
321 enum rtl8110_registers {
327 enum rtl8168_8101_registers {
330 #define CSIAR_FLAG 0x80000000
331 #define CSIAR_WRITE_CMD 0x80000000
332 #define CSIAR_BYTE_ENABLE 0x0f
333 #define CSIAR_BYTE_ENABLE_SHIFT 12
334 #define CSIAR_ADDR_MASK 0x0fff
337 #define EPHYAR_FLAG 0x80000000
338 #define EPHYAR_WRITE_CMD 0x80000000
339 #define EPHYAR_REG_MASK 0x1f
340 #define EPHYAR_REG_SHIFT 16
341 #define EPHYAR_DATA_MASK 0xffff
343 #define PFM_EN (1 << 6)
345 #define FIX_NAK_1 (1 << 4)
346 #define FIX_NAK_2 (1 << 3)
349 #define NOW_IS_OOB (1 << 7)
350 #define EN_NDP (1 << 3)
351 #define EN_OOB_RESET (1 << 2)
353 #define EFUSEAR_FLAG 0x80000000
354 #define EFUSEAR_WRITE_CMD 0x80000000
355 #define EFUSEAR_READ_CMD 0x00000000
356 #define EFUSEAR_REG_MASK 0x03ff
357 #define EFUSEAR_REG_SHIFT 8
358 #define EFUSEAR_DATA_MASK 0xff
361 enum rtl8168_registers {
366 #define ERIAR_FLAG 0x80000000
367 #define ERIAR_WRITE_CMD 0x80000000
368 #define ERIAR_READ_CMD 0x00000000
369 #define ERIAR_ADDR_BYTE_ALIGN 4
370 #define ERIAR_TYPE_SHIFT 16
371 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
372 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
373 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
374 #define ERIAR_MASK_SHIFT 12
375 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
376 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
377 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
378 EPHY_RXER_NUM = 0x7c,
379 OCPDR = 0xb0, /* OCP GPHY access */
380 #define OCPDR_WRITE_CMD 0x80000000
381 #define OCPDR_READ_CMD 0x00000000
382 #define OCPDR_REG_MASK 0x7f
383 #define OCPDR_GPHY_REG_SHIFT 16
384 #define OCPDR_DATA_MASK 0xffff
386 #define OCPAR_FLAG 0x80000000
387 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
388 #define OCPAR_GPHY_READ_CMD 0x0000f060
389 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
390 MISC = 0xf0, /* 8168e only. */
391 #define TXPLA_RST (1 << 29)
392 #define PWM_EN (1 << 22)
395 enum rtl_register_content {
396 /* InterruptStatusBits */
400 TxDescUnavail = 0x0080,
423 /* TXPoll register p.5 */
424 HPQ = 0x80, /* Poll cmd on the high prio queue */
425 NPQ = 0x40, /* Poll cmd on the low prio queue */
426 FSWInt = 0x01, /* Forced software interrupt */
430 Cfg9346_Unlock = 0xc0,
435 AcceptBroadcast = 0x08,
436 AcceptMulticast = 0x04,
438 AcceptAllPhys = 0x01,
441 TxInterFrameGapShift = 24,
442 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
444 /* Config1 register p.24 */
447 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
448 Speed_down = (1 << 4),
452 PMEnable = (1 << 0), /* Power Management Enable */
454 /* Config2 register p. 25 */
455 PCI_Clock_66MHz = 0x01,
456 PCI_Clock_33MHz = 0x00,
458 /* Config3 register p.25 */
459 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
460 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
461 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
463 /* Config5 register p.27 */
464 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
465 MWF = (1 << 5), /* Accept Multicast wakeup frame */
466 UWF = (1 << 4), /* Accept Unicast wakeup frame */
468 LanWake = (1 << 1), /* LanWake enable/disable */
469 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
472 TBIReset = 0x80000000,
473 TBILoopback = 0x40000000,
474 TBINwEnable = 0x20000000,
475 TBINwRestart = 0x10000000,
476 TBILinkOk = 0x02000000,
477 TBINwComplete = 0x01000000,
480 EnableBist = (1 << 15), // 8168 8101
481 Mac_dbgo_oe = (1 << 14), // 8168 8101
482 Normal_mode = (1 << 13), // unused
483 Force_half_dup = (1 << 12), // 8168 8101
484 Force_rxflow_en = (1 << 11), // 8168 8101
485 Force_txflow_en = (1 << 10), // 8168 8101
486 Cxpl_dbg_sel = (1 << 9), // 8168 8101
487 ASF = (1 << 8), // 8168 8101
488 PktCntrDisable = (1 << 7), // 8168 8101
489 Mac_dbgo_sel = 0x001c, // 8168
494 INTT_0 = 0x0000, // 8168
495 INTT_1 = 0x0001, // 8168
496 INTT_2 = 0x0002, // 8168
497 INTT_3 = 0x0003, // 8168
499 /* rtl8169_PHYstatus */
510 TBILinkOK = 0x02000000,
512 /* DumpCounterCommand */
517 /* First doubleword. */
518 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
519 RingEnd = (1 << 30), /* End of descriptor ring */
520 FirstFrag = (1 << 29), /* First segment of a packet */
521 LastFrag = (1 << 28), /* Final segment of a packet */
525 enum rtl_tx_desc_bit {
526 /* First doubleword. */
527 TD_LSO = (1 << 27), /* Large Send Offload */
528 #define TD_MSS_MAX 0x07ffu /* MSS value */
530 /* Second doubleword. */
531 TxVlanTag = (1 << 17), /* Add VLAN tag */
534 /* 8169, 8168b and 810x except 8102e. */
535 enum rtl_tx_desc_bit_0 {
536 /* First doubleword. */
537 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
538 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
539 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
540 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
543 /* 8102e, 8168c and beyond. */
544 enum rtl_tx_desc_bit_1 {
545 /* Second doubleword. */
546 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
547 TD1_IP_CS = (1 << 29), /* Calculate IP checksum */
548 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
549 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
552 static const struct rtl_tx_desc_info {
559 } tx_desc_info [] = {
562 .udp = TD0_IP_CS | TD0_UDP_CS,
563 .tcp = TD0_IP_CS | TD0_TCP_CS
565 .mss_shift = TD0_MSS_SHIFT,
570 .udp = TD1_IP_CS | TD1_UDP_CS,
571 .tcp = TD1_IP_CS | TD1_TCP_CS
573 .mss_shift = TD1_MSS_SHIFT,
578 enum rtl_rx_desc_bit {
580 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
581 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
583 #define RxProtoUDP (PID1)
584 #define RxProtoTCP (PID0)
585 #define RxProtoIP (PID1 | PID0)
586 #define RxProtoMask RxProtoIP
588 IPFail = (1 << 16), /* IP checksum failed */
589 UDPFail = (1 << 15), /* UDP/IP checksum failed */
590 TCPFail = (1 << 14), /* TCP/IP checksum failed */
591 RxVlanTag = (1 << 16), /* VLAN tag available */
594 #define RsvdMask 0x3fffc000
611 u8 __pad[sizeof(void *) - sizeof(u32)];
615 RTL_FEATURE_WOL = (1 << 0),
616 RTL_FEATURE_MSI = (1 << 1),
617 RTL_FEATURE_GMII = (1 << 2),
620 struct rtl8169_counters {
627 __le32 tx_one_collision;
628 __le32 tx_multi_collision;
636 struct rtl8169_private {
637 void __iomem *mmio_addr; /* memory map physical address */
638 struct pci_dev *pci_dev;
639 struct net_device *dev;
640 struct napi_struct napi;
645 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
646 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
649 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
650 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
651 dma_addr_t TxPhyAddr;
652 dma_addr_t RxPhyAddr;
653 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
654 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
655 struct timer_list timer;
662 void (*write)(void __iomem *, int, int);
663 int (*read)(void __iomem *, int);
666 struct pll_power_ops {
667 void (*down)(struct rtl8169_private *);
668 void (*up)(struct rtl8169_private *);
671 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
672 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
673 void (*phy_reset_enable)(struct rtl8169_private *tp);
674 void (*hw_start)(struct net_device *);
675 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
676 unsigned int (*link_ok)(void __iomem *);
677 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
678 struct delayed_work task;
681 struct mii_if_info mii;
682 struct rtl8169_counters counters;
686 const struct firmware *fw;
688 #define RTL_VER_SIZE 32
690 char version[RTL_VER_SIZE];
692 struct rtl_fw_phy_action {
697 #define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN);
700 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
701 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
702 module_param(use_dac, int, 0);
703 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
704 module_param_named(debug, debug.msg_enable, int, 0);
705 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
706 MODULE_LICENSE("GPL");
707 MODULE_VERSION(RTL8169_VERSION);
708 MODULE_FIRMWARE(FIRMWARE_8168D_1);
709 MODULE_FIRMWARE(FIRMWARE_8168D_2);
710 MODULE_FIRMWARE(FIRMWARE_8168E_1);
711 MODULE_FIRMWARE(FIRMWARE_8168E_2);
712 MODULE_FIRMWARE(FIRMWARE_8105E_1);
714 static int rtl8169_open(struct net_device *dev);
715 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
716 struct net_device *dev);
717 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
718 static int rtl8169_init_ring(struct net_device *dev);
719 static void rtl_hw_start(struct net_device *dev);
720 static int rtl8169_close(struct net_device *dev);
721 static void rtl_set_rx_mode(struct net_device *dev);
722 static void rtl8169_tx_timeout(struct net_device *dev);
723 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
724 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
725 void __iomem *, u32 budget);
726 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
727 static void rtl8169_down(struct net_device *dev);
728 static void rtl8169_rx_clear(struct rtl8169_private *tp);
729 static int rtl8169_poll(struct napi_struct *napi, int budget);
731 static const unsigned int rtl8169_rx_config = RX_FIFO_THRESH | RX_DMA_BURST;
733 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
735 void __iomem *ioaddr = tp->mmio_addr;
738 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
739 for (i = 0; i < 20; i++) {
741 if (RTL_R32(OCPAR) & OCPAR_FLAG)
744 return RTL_R32(OCPDR);
747 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
749 void __iomem *ioaddr = tp->mmio_addr;
752 RTL_W32(OCPDR, data);
753 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
754 for (i = 0; i < 20; i++) {
756 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
761 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
763 void __iomem *ioaddr = tp->mmio_addr;
767 RTL_W32(ERIAR, 0x800010e8);
769 for (i = 0; i < 5; i++) {
771 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
775 ocp_write(tp, 0x1, 0x30, 0x00000001);
778 #define OOB_CMD_RESET 0x00
779 #define OOB_CMD_DRIVER_START 0x05
780 #define OOB_CMD_DRIVER_STOP 0x06
782 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
784 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
787 static void rtl8168_driver_start(struct rtl8169_private *tp)
792 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
794 reg = rtl8168_get_ocp_reg(tp);
796 for (i = 0; i < 10; i++) {
798 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
803 static void rtl8168_driver_stop(struct rtl8169_private *tp)
808 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
810 reg = rtl8168_get_ocp_reg(tp);
812 for (i = 0; i < 10; i++) {
814 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
819 static int r8168dp_check_dash(struct rtl8169_private *tp)
821 u16 reg = rtl8168_get_ocp_reg(tp);
823 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
826 static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
830 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
832 for (i = 20; i > 0; i--) {
834 * Check if the RTL8169 has completed writing to the specified
837 if (!(RTL_R32(PHYAR) & 0x80000000))
842 * According to hardware specs a 20us delay is required after write
843 * complete indication, but before sending next command.
848 static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
852 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
854 for (i = 20; i > 0; i--) {
856 * Check if the RTL8169 has completed retrieving data from
857 * the specified MII register.
859 if (RTL_R32(PHYAR) & 0x80000000) {
860 value = RTL_R32(PHYAR) & 0xffff;
866 * According to hardware specs a 20us delay is required after read
867 * complete indication, but before sending next command.
874 static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
878 RTL_W32(OCPDR, data |
879 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
880 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
881 RTL_W32(EPHY_RXER_NUM, 0);
883 for (i = 0; i < 100; i++) {
885 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
890 static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
892 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
893 (value & OCPDR_DATA_MASK));
896 static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
900 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
903 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
904 RTL_W32(EPHY_RXER_NUM, 0);
906 for (i = 0; i < 100; i++) {
908 if (RTL_R32(OCPAR) & OCPAR_FLAG)
912 return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
915 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
917 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
919 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
922 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
924 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
927 static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
929 r8168dp_2_mdio_start(ioaddr);
931 r8169_mdio_write(ioaddr, reg_addr, value);
933 r8168dp_2_mdio_stop(ioaddr);
936 static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
940 r8168dp_2_mdio_start(ioaddr);
942 value = r8169_mdio_read(ioaddr, reg_addr);
944 r8168dp_2_mdio_stop(ioaddr);
949 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
951 tp->mdio_ops.write(tp->mmio_addr, location, val);
954 static int rtl_readphy(struct rtl8169_private *tp, int location)
956 return tp->mdio_ops.read(tp->mmio_addr, location);
959 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
961 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
964 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
968 val = rtl_readphy(tp, reg_addr);
969 rtl_writephy(tp, reg_addr, (val | p) & ~m);
972 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
975 struct rtl8169_private *tp = netdev_priv(dev);
977 rtl_writephy(tp, location, val);
980 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
982 struct rtl8169_private *tp = netdev_priv(dev);
984 return rtl_readphy(tp, location);
987 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
991 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
992 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
994 for (i = 0; i < 100; i++) {
995 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
1001 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
1006 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1008 for (i = 0; i < 100; i++) {
1009 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
1010 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
1019 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
1023 RTL_W32(CSIDR, value);
1024 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
1025 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1027 for (i = 0; i < 100; i++) {
1028 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
1034 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
1039 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
1040 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1042 for (i = 0; i < 100; i++) {
1043 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
1044 value = RTL_R32(CSIDR);
1054 void rtl_eri_write(void __iomem *ioaddr, int addr, u32 mask, u32 val, int type)
1058 BUG_ON((addr & 3) || (mask == 0));
1059 RTL_W32(ERIDR, val);
1060 RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1062 for (i = 0; i < 100; i++) {
1063 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
1069 static u32 rtl_eri_read(void __iomem *ioaddr, int addr, int type)
1074 RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1076 for (i = 0; i < 100; i++) {
1077 if (RTL_R32(ERIAR) & ERIAR_FLAG) {
1078 value = RTL_R32(ERIDR);
1088 rtl_w1w0_eri(void __iomem *ioaddr, int addr, u32 mask, u32 p, u32 m, int type)
1092 val = rtl_eri_read(ioaddr, addr, type);
1093 rtl_eri_write(ioaddr, addr, mask, (val & ~m) | p, type);
1096 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
1101 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1103 for (i = 0; i < 300; i++) {
1104 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
1105 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
1114 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
1116 RTL_W16(IntrMask, 0x0000);
1118 RTL_W16(IntrStatus, 0xffff);
1121 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1123 void __iomem *ioaddr = tp->mmio_addr;
1125 return RTL_R32(TBICSR) & TBIReset;
1128 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1130 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1133 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1135 return RTL_R32(TBICSR) & TBILinkOk;
1138 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1140 return RTL_R8(PHYstatus) & LinkStatus;
1143 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1145 void __iomem *ioaddr = tp->mmio_addr;
1147 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1150 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1154 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1155 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1158 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1160 void __iomem *ioaddr = tp->mmio_addr;
1161 struct net_device *dev = tp->dev;
1163 if (!netif_running(dev))
1166 if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
1167 if (RTL_R8(PHYstatus) & _1000bpsF) {
1168 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1169 0x00000011, ERIAR_EXGMAC);
1170 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1171 0x00000005, ERIAR_EXGMAC);
1172 } else if (RTL_R8(PHYstatus) & _100bps) {
1173 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1174 0x0000001f, ERIAR_EXGMAC);
1175 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1176 0x00000005, ERIAR_EXGMAC);
1178 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1179 0x0000001f, ERIAR_EXGMAC);
1180 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1181 0x0000003f, ERIAR_EXGMAC);
1183 /* Reset packet filter */
1184 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1186 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1191 static void __rtl8169_check_link_status(struct net_device *dev,
1192 struct rtl8169_private *tp,
1193 void __iomem *ioaddr, bool pm)
1195 unsigned long flags;
1197 spin_lock_irqsave(&tp->lock, flags);
1198 if (tp->link_ok(ioaddr)) {
1199 rtl_link_chg_patch(tp);
1200 /* This is to cancel a scheduled suspend if there's one. */
1202 pm_request_resume(&tp->pci_dev->dev);
1203 netif_carrier_on(dev);
1204 if (net_ratelimit())
1205 netif_info(tp, ifup, dev, "link up\n");
1207 netif_carrier_off(dev);
1208 netif_info(tp, ifdown, dev, "link down\n");
1210 pm_schedule_suspend(&tp->pci_dev->dev, 100);
1212 spin_unlock_irqrestore(&tp->lock, flags);
1215 static void rtl8169_check_link_status(struct net_device *dev,
1216 struct rtl8169_private *tp,
1217 void __iomem *ioaddr)
1219 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1222 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1224 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1226 void __iomem *ioaddr = tp->mmio_addr;
1230 options = RTL_R8(Config1);
1231 if (!(options & PMEnable))
1234 options = RTL_R8(Config3);
1235 if (options & LinkUp)
1236 wolopts |= WAKE_PHY;
1237 if (options & MagicPacket)
1238 wolopts |= WAKE_MAGIC;
1240 options = RTL_R8(Config5);
1242 wolopts |= WAKE_UCAST;
1244 wolopts |= WAKE_BCAST;
1246 wolopts |= WAKE_MCAST;
1251 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1253 struct rtl8169_private *tp = netdev_priv(dev);
1255 spin_lock_irq(&tp->lock);
1257 wol->supported = WAKE_ANY;
1258 wol->wolopts = __rtl8169_get_wol(tp);
1260 spin_unlock_irq(&tp->lock);
1263 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1265 void __iomem *ioaddr = tp->mmio_addr;
1267 static const struct {
1272 { WAKE_ANY, Config1, PMEnable },
1273 { WAKE_PHY, Config3, LinkUp },
1274 { WAKE_MAGIC, Config3, MagicPacket },
1275 { WAKE_UCAST, Config5, UWF },
1276 { WAKE_BCAST, Config5, BWF },
1277 { WAKE_MCAST, Config5, MWF },
1278 { WAKE_ANY, Config5, LanWake }
1281 RTL_W8(Cfg9346, Cfg9346_Unlock);
1283 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1284 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1285 if (wolopts & cfg[i].opt)
1286 options |= cfg[i].mask;
1287 RTL_W8(cfg[i].reg, options);
1290 RTL_W8(Cfg9346, Cfg9346_Lock);
1293 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1295 struct rtl8169_private *tp = netdev_priv(dev);
1297 spin_lock_irq(&tp->lock);
1300 tp->features |= RTL_FEATURE_WOL;
1302 tp->features &= ~RTL_FEATURE_WOL;
1303 __rtl8169_set_wol(tp, wol->wolopts);
1304 spin_unlock_irq(&tp->lock);
1306 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1311 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1313 return rtl_chip_infos[tp->mac_version].fw_name;
1316 static void rtl8169_get_drvinfo(struct net_device *dev,
1317 struct ethtool_drvinfo *info)
1319 struct rtl8169_private *tp = netdev_priv(dev);
1320 struct rtl_fw *rtl_fw = tp->rtl_fw;
1322 strcpy(info->driver, MODULENAME);
1323 strcpy(info->version, RTL8169_VERSION);
1324 strcpy(info->bus_info, pci_name(tp->pci_dev));
1325 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1326 strcpy(info->fw_version, IS_ERR_OR_NULL(rtl_fw) ? "N/A" :
1330 static int rtl8169_get_regs_len(struct net_device *dev)
1332 return R8169_REGS_SIZE;
1335 static int rtl8169_set_speed_tbi(struct net_device *dev,
1336 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1338 struct rtl8169_private *tp = netdev_priv(dev);
1339 void __iomem *ioaddr = tp->mmio_addr;
1343 reg = RTL_R32(TBICSR);
1344 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1345 (duplex == DUPLEX_FULL)) {
1346 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1347 } else if (autoneg == AUTONEG_ENABLE)
1348 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1350 netif_warn(tp, link, dev,
1351 "incorrect speed setting refused in TBI mode\n");
1358 static int rtl8169_set_speed_xmii(struct net_device *dev,
1359 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1361 struct rtl8169_private *tp = netdev_priv(dev);
1362 int giga_ctrl, bmcr;
1365 rtl_writephy(tp, 0x1f, 0x0000);
1367 if (autoneg == AUTONEG_ENABLE) {
1370 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1371 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1372 ADVERTISE_100HALF | ADVERTISE_100FULL);
1374 if (adv & ADVERTISED_10baseT_Half)
1375 auto_nego |= ADVERTISE_10HALF;
1376 if (adv & ADVERTISED_10baseT_Full)
1377 auto_nego |= ADVERTISE_10FULL;
1378 if (adv & ADVERTISED_100baseT_Half)
1379 auto_nego |= ADVERTISE_100HALF;
1380 if (adv & ADVERTISED_100baseT_Full)
1381 auto_nego |= ADVERTISE_100FULL;
1383 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1385 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1386 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1388 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1389 if (tp->mii.supports_gmii) {
1390 if (adv & ADVERTISED_1000baseT_Half)
1391 giga_ctrl |= ADVERTISE_1000HALF;
1392 if (adv & ADVERTISED_1000baseT_Full)
1393 giga_ctrl |= ADVERTISE_1000FULL;
1394 } else if (adv & (ADVERTISED_1000baseT_Half |
1395 ADVERTISED_1000baseT_Full)) {
1396 netif_info(tp, link, dev,
1397 "PHY does not support 1000Mbps\n");
1401 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1403 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1404 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1408 if (speed == SPEED_10)
1410 else if (speed == SPEED_100)
1411 bmcr = BMCR_SPEED100;
1415 if (duplex == DUPLEX_FULL)
1416 bmcr |= BMCR_FULLDPLX;
1419 rtl_writephy(tp, MII_BMCR, bmcr);
1421 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1422 tp->mac_version == RTL_GIGA_MAC_VER_03) {
1423 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1424 rtl_writephy(tp, 0x17, 0x2138);
1425 rtl_writephy(tp, 0x0e, 0x0260);
1427 rtl_writephy(tp, 0x17, 0x2108);
1428 rtl_writephy(tp, 0x0e, 0x0000);
1437 static int rtl8169_set_speed(struct net_device *dev,
1438 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1440 struct rtl8169_private *tp = netdev_priv(dev);
1443 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1447 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1448 (advertising & ADVERTISED_1000baseT_Full)) {
1449 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1455 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1457 struct rtl8169_private *tp = netdev_priv(dev);
1458 unsigned long flags;
1461 del_timer_sync(&tp->timer);
1463 spin_lock_irqsave(&tp->lock, flags);
1464 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
1465 cmd->duplex, cmd->advertising);
1466 spin_unlock_irqrestore(&tp->lock, flags);
1471 static u32 rtl8169_fix_features(struct net_device *dev, u32 features)
1473 if (dev->mtu > TD_MSS_MAX)
1474 features &= ~NETIF_F_ALL_TSO;
1479 static int rtl8169_set_features(struct net_device *dev, u32 features)
1481 struct rtl8169_private *tp = netdev_priv(dev);
1482 void __iomem *ioaddr = tp->mmio_addr;
1483 unsigned long flags;
1485 spin_lock_irqsave(&tp->lock, flags);
1487 if (features & NETIF_F_RXCSUM)
1488 tp->cp_cmd |= RxChkSum;
1490 tp->cp_cmd &= ~RxChkSum;
1492 if (dev->features & NETIF_F_HW_VLAN_RX)
1493 tp->cp_cmd |= RxVlan;
1495 tp->cp_cmd &= ~RxVlan;
1497 RTL_W16(CPlusCmd, tp->cp_cmd);
1500 spin_unlock_irqrestore(&tp->lock, flags);
1505 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1506 struct sk_buff *skb)
1508 return (vlan_tx_tag_present(skb)) ?
1509 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1512 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1514 u32 opts2 = le32_to_cpu(desc->opts2);
1516 if (opts2 & RxVlanTag)
1517 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
1522 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1524 struct rtl8169_private *tp = netdev_priv(dev);
1525 void __iomem *ioaddr = tp->mmio_addr;
1529 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1530 cmd->port = PORT_FIBRE;
1531 cmd->transceiver = XCVR_INTERNAL;
1533 status = RTL_R32(TBICSR);
1534 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1535 cmd->autoneg = !!(status & TBINwEnable);
1537 ethtool_cmd_speed_set(cmd, SPEED_1000);
1538 cmd->duplex = DUPLEX_FULL; /* Always set */
1543 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1545 struct rtl8169_private *tp = netdev_priv(dev);
1547 return mii_ethtool_gset(&tp->mii, cmd);
1550 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1552 struct rtl8169_private *tp = netdev_priv(dev);
1553 unsigned long flags;
1556 spin_lock_irqsave(&tp->lock, flags);
1558 rc = tp->get_settings(dev, cmd);
1560 spin_unlock_irqrestore(&tp->lock, flags);
1564 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1567 struct rtl8169_private *tp = netdev_priv(dev);
1568 unsigned long flags;
1570 if (regs->len > R8169_REGS_SIZE)
1571 regs->len = R8169_REGS_SIZE;
1573 spin_lock_irqsave(&tp->lock, flags);
1574 memcpy_fromio(p, tp->mmio_addr, regs->len);
1575 spin_unlock_irqrestore(&tp->lock, flags);
1578 static u32 rtl8169_get_msglevel(struct net_device *dev)
1580 struct rtl8169_private *tp = netdev_priv(dev);
1582 return tp->msg_enable;
1585 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1587 struct rtl8169_private *tp = netdev_priv(dev);
1589 tp->msg_enable = value;
1592 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1599 "tx_single_collisions",
1600 "tx_multi_collisions",
1608 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1612 return ARRAY_SIZE(rtl8169_gstrings);
1618 static void rtl8169_update_counters(struct net_device *dev)
1620 struct rtl8169_private *tp = netdev_priv(dev);
1621 void __iomem *ioaddr = tp->mmio_addr;
1622 struct device *d = &tp->pci_dev->dev;
1623 struct rtl8169_counters *counters;
1629 * Some chips are unable to dump tally counters when the receiver
1632 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1635 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1639 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1640 cmd = (u64)paddr & DMA_BIT_MASK(32);
1641 RTL_W32(CounterAddrLow, cmd);
1642 RTL_W32(CounterAddrLow, cmd | CounterDump);
1645 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1646 memcpy(&tp->counters, counters, sizeof(*counters));
1652 RTL_W32(CounterAddrLow, 0);
1653 RTL_W32(CounterAddrHigh, 0);
1655 dma_free_coherent(d, sizeof(*counters), counters, paddr);
1658 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1659 struct ethtool_stats *stats, u64 *data)
1661 struct rtl8169_private *tp = netdev_priv(dev);
1665 rtl8169_update_counters(dev);
1667 data[0] = le64_to_cpu(tp->counters.tx_packets);
1668 data[1] = le64_to_cpu(tp->counters.rx_packets);
1669 data[2] = le64_to_cpu(tp->counters.tx_errors);
1670 data[3] = le32_to_cpu(tp->counters.rx_errors);
1671 data[4] = le16_to_cpu(tp->counters.rx_missed);
1672 data[5] = le16_to_cpu(tp->counters.align_errors);
1673 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1674 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1675 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1676 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1677 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1678 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1679 data[12] = le16_to_cpu(tp->counters.tx_underun);
1682 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1686 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1691 static const struct ethtool_ops rtl8169_ethtool_ops = {
1692 .get_drvinfo = rtl8169_get_drvinfo,
1693 .get_regs_len = rtl8169_get_regs_len,
1694 .get_link = ethtool_op_get_link,
1695 .get_settings = rtl8169_get_settings,
1696 .set_settings = rtl8169_set_settings,
1697 .get_msglevel = rtl8169_get_msglevel,
1698 .set_msglevel = rtl8169_set_msglevel,
1699 .get_regs = rtl8169_get_regs,
1700 .get_wol = rtl8169_get_wol,
1701 .set_wol = rtl8169_set_wol,
1702 .get_strings = rtl8169_get_strings,
1703 .get_sset_count = rtl8169_get_sset_count,
1704 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1707 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1708 struct net_device *dev, u8 default_version)
1710 void __iomem *ioaddr = tp->mmio_addr;
1712 * The driver currently handles the 8168Bf and the 8168Be identically
1713 * but they can be identified more specifically through the test below
1716 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1718 * Same thing for the 8101Eb and the 8101Ec:
1720 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1722 static const struct rtl_mac_info {
1728 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
1729 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
1730 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
1731 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
1734 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
1735 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
1736 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
1738 /* 8168DP family. */
1739 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
1740 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
1741 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
1744 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
1745 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
1746 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
1747 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
1748 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1749 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
1750 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
1751 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
1752 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
1755 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1756 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1757 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1758 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1761 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
1762 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
1763 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
1764 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
1765 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1766 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1767 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1768 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1769 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1770 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
1771 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
1772 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
1773 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
1774 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1775 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
1776 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1777 /* FIXME: where did these entries come from ? -- FR */
1778 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1779 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1782 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1783 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1784 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1785 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1786 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1787 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1790 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
1792 const struct rtl_mac_info *p = mac_info;
1795 reg = RTL_R32(TxConfig);
1796 while ((reg & p->mask) != p->val)
1798 tp->mac_version = p->mac_version;
1800 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
1801 netif_notice(tp, probe, dev,
1802 "unknown MAC, using family default\n");
1803 tp->mac_version = default_version;
1807 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1809 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1817 static void rtl_writephy_batch(struct rtl8169_private *tp,
1818 const struct phy_reg *regs, int len)
1821 rtl_writephy(tp, regs->reg, regs->val);
1826 #define PHY_READ 0x00000000
1827 #define PHY_DATA_OR 0x10000000
1828 #define PHY_DATA_AND 0x20000000
1829 #define PHY_BJMPN 0x30000000
1830 #define PHY_READ_EFUSE 0x40000000
1831 #define PHY_READ_MAC_BYTE 0x50000000
1832 #define PHY_WRITE_MAC_BYTE 0x60000000
1833 #define PHY_CLEAR_READCOUNT 0x70000000
1834 #define PHY_WRITE 0x80000000
1835 #define PHY_READCOUNT_EQ_SKIP 0x90000000
1836 #define PHY_COMP_EQ_SKIPN 0xa0000000
1837 #define PHY_COMP_NEQ_SKIPN 0xb0000000
1838 #define PHY_WRITE_PREVIOUS 0xc0000000
1839 #define PHY_SKIPN 0xd0000000
1840 #define PHY_DELAY_MS 0xe0000000
1841 #define PHY_WRITE_ERI_WORD 0xf0000000
1845 char version[RTL_VER_SIZE];
1851 #define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
1853 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
1855 const struct firmware *fw = rtl_fw->fw;
1856 struct fw_info *fw_info = (struct fw_info *)fw->data;
1857 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
1858 char *version = rtl_fw->version;
1861 if (fw->size < FW_OPCODE_SIZE)
1864 if (!fw_info->magic) {
1865 size_t i, size, start;
1868 if (fw->size < sizeof(*fw_info))
1871 for (i = 0; i < fw->size; i++)
1872 checksum += fw->data[i];
1876 start = le32_to_cpu(fw_info->fw_start);
1877 if (start > fw->size)
1880 size = le32_to_cpu(fw_info->fw_len);
1881 if (size > (fw->size - start) / FW_OPCODE_SIZE)
1884 memcpy(version, fw_info->version, RTL_VER_SIZE);
1886 pa->code = (__le32 *)(fw->data + start);
1889 if (fw->size % FW_OPCODE_SIZE)
1892 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
1894 pa->code = (__le32 *)fw->data;
1895 pa->size = fw->size / FW_OPCODE_SIZE;
1897 version[RTL_VER_SIZE - 1] = 0;
1904 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
1905 struct rtl_fw_phy_action *pa)
1910 for (index = 0; index < pa->size; index++) {
1911 u32 action = le32_to_cpu(pa->code[index]);
1912 u32 regno = (action & 0x0fff0000) >> 16;
1914 switch(action & 0xf0000000) {
1918 case PHY_READ_EFUSE:
1919 case PHY_CLEAR_READCOUNT:
1921 case PHY_WRITE_PREVIOUS:
1926 if (regno > index) {
1927 netif_err(tp, ifup, tp->dev,
1928 "Out of range of firmware\n");
1932 case PHY_READCOUNT_EQ_SKIP:
1933 if (index + 2 >= pa->size) {
1934 netif_err(tp, ifup, tp->dev,
1935 "Out of range of firmware\n");
1939 case PHY_COMP_EQ_SKIPN:
1940 case PHY_COMP_NEQ_SKIPN:
1942 if (index + 1 + regno >= pa->size) {
1943 netif_err(tp, ifup, tp->dev,
1944 "Out of range of firmware\n");
1949 case PHY_READ_MAC_BYTE:
1950 case PHY_WRITE_MAC_BYTE:
1951 case PHY_WRITE_ERI_WORD:
1953 netif_err(tp, ifup, tp->dev,
1954 "Invalid action 0x%08x\n", action);
1963 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
1965 struct net_device *dev = tp->dev;
1968 if (!rtl_fw_format_ok(tp, rtl_fw)) {
1969 netif_err(tp, ifup, dev, "invalid firwmare\n");
1973 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
1979 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
1981 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
1985 predata = count = 0;
1987 for (index = 0; index < pa->size; ) {
1988 u32 action = le32_to_cpu(pa->code[index]);
1989 u32 data = action & 0x0000ffff;
1990 u32 regno = (action & 0x0fff0000) >> 16;
1995 switch(action & 0xf0000000) {
1997 predata = rtl_readphy(tp, regno);
2012 case PHY_READ_EFUSE:
2013 predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
2016 case PHY_CLEAR_READCOUNT:
2021 rtl_writephy(tp, regno, data);
2024 case PHY_READCOUNT_EQ_SKIP:
2025 index += (count == data) ? 2 : 1;
2027 case PHY_COMP_EQ_SKIPN:
2028 if (predata == data)
2032 case PHY_COMP_NEQ_SKIPN:
2033 if (predata != data)
2037 case PHY_WRITE_PREVIOUS:
2038 rtl_writephy(tp, regno, predata);
2049 case PHY_READ_MAC_BYTE:
2050 case PHY_WRITE_MAC_BYTE:
2051 case PHY_WRITE_ERI_WORD:
2058 static void rtl_release_firmware(struct rtl8169_private *tp)
2060 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2061 release_firmware(tp->rtl_fw->fw);
2064 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2067 static void rtl_apply_firmware(struct rtl8169_private *tp)
2069 struct rtl_fw *rtl_fw = tp->rtl_fw;
2071 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2072 if (!IS_ERR_OR_NULL(rtl_fw))
2073 rtl_phy_write_fw(tp, rtl_fw);
2076 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2078 if (rtl_readphy(tp, reg) != val)
2079 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2081 rtl_apply_firmware(tp);
2084 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2086 static const struct phy_reg phy_reg_init[] = {
2148 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2151 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2153 static const struct phy_reg phy_reg_init[] = {
2159 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2162 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2164 struct pci_dev *pdev = tp->pci_dev;
2165 u16 vendor_id, device_id;
2167 pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
2168 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
2170 if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
2173 rtl_writephy(tp, 0x1f, 0x0001);
2174 rtl_writephy(tp, 0x10, 0xf01b);
2175 rtl_writephy(tp, 0x1f, 0x0000);
2178 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2180 static const struct phy_reg phy_reg_init[] = {
2220 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2222 rtl8169scd_hw_phy_config_quirk(tp);
2225 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2227 static const struct phy_reg phy_reg_init[] = {
2275 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2278 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2280 static const struct phy_reg phy_reg_init[] = {
2285 rtl_writephy(tp, 0x1f, 0x0001);
2286 rtl_patchphy(tp, 0x16, 1 << 0);
2288 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2291 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2293 static const struct phy_reg phy_reg_init[] = {
2299 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2302 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2304 static const struct phy_reg phy_reg_init[] = {
2312 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2315 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2317 static const struct phy_reg phy_reg_init[] = {
2323 rtl_writephy(tp, 0x1f, 0x0000);
2324 rtl_patchphy(tp, 0x14, 1 << 5);
2325 rtl_patchphy(tp, 0x0d, 1 << 5);
2327 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2330 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2332 static const struct phy_reg phy_reg_init[] = {
2352 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2354 rtl_patchphy(tp, 0x14, 1 << 5);
2355 rtl_patchphy(tp, 0x0d, 1 << 5);
2356 rtl_writephy(tp, 0x1f, 0x0000);
2359 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2361 static const struct phy_reg phy_reg_init[] = {
2379 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2381 rtl_patchphy(tp, 0x16, 1 << 0);
2382 rtl_patchphy(tp, 0x14, 1 << 5);
2383 rtl_patchphy(tp, 0x0d, 1 << 5);
2384 rtl_writephy(tp, 0x1f, 0x0000);
2387 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2389 static const struct phy_reg phy_reg_init[] = {
2401 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2403 rtl_patchphy(tp, 0x16, 1 << 0);
2404 rtl_patchphy(tp, 0x14, 1 << 5);
2405 rtl_patchphy(tp, 0x0d, 1 << 5);
2406 rtl_writephy(tp, 0x1f, 0x0000);
2409 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2411 rtl8168c_3_hw_phy_config(tp);
2414 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2416 static const struct phy_reg phy_reg_init_0[] = {
2417 /* Channel Estimation */
2438 * Enhance line driver power
2447 * Can not link to 1Gbps with bad cable
2448 * Decrease SNR threshold form 21.07dB to 19.04dB
2456 void __iomem *ioaddr = tp->mmio_addr;
2458 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2462 * Fine Tune Switching regulator parameter
2464 rtl_writephy(tp, 0x1f, 0x0002);
2465 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2466 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2468 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2469 static const struct phy_reg phy_reg_init[] = {
2479 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2481 val = rtl_readphy(tp, 0x0d);
2483 if ((val & 0x00ff) != 0x006c) {
2484 static const u32 set[] = {
2485 0x0065, 0x0066, 0x0067, 0x0068,
2486 0x0069, 0x006a, 0x006b, 0x006c
2490 rtl_writephy(tp, 0x1f, 0x0002);
2493 for (i = 0; i < ARRAY_SIZE(set); i++)
2494 rtl_writephy(tp, 0x0d, val | set[i]);
2497 static const struct phy_reg phy_reg_init[] = {
2505 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2508 /* RSET couple improve */
2509 rtl_writephy(tp, 0x1f, 0x0002);
2510 rtl_patchphy(tp, 0x0d, 0x0300);
2511 rtl_patchphy(tp, 0x0f, 0x0010);
2513 /* Fine tune PLL performance */
2514 rtl_writephy(tp, 0x1f, 0x0002);
2515 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2516 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2518 rtl_writephy(tp, 0x1f, 0x0005);
2519 rtl_writephy(tp, 0x05, 0x001b);
2521 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2523 rtl_writephy(tp, 0x1f, 0x0000);
2526 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2528 static const struct phy_reg phy_reg_init_0[] = {
2529 /* Channel Estimation */
2550 * Enhance line driver power
2559 * Can not link to 1Gbps with bad cable
2560 * Decrease SNR threshold form 21.07dB to 19.04dB
2568 void __iomem *ioaddr = tp->mmio_addr;
2570 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2572 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2573 static const struct phy_reg phy_reg_init[] = {
2584 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2586 val = rtl_readphy(tp, 0x0d);
2587 if ((val & 0x00ff) != 0x006c) {
2588 static const u32 set[] = {
2589 0x0065, 0x0066, 0x0067, 0x0068,
2590 0x0069, 0x006a, 0x006b, 0x006c
2594 rtl_writephy(tp, 0x1f, 0x0002);
2597 for (i = 0; i < ARRAY_SIZE(set); i++)
2598 rtl_writephy(tp, 0x0d, val | set[i]);
2601 static const struct phy_reg phy_reg_init[] = {
2609 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2612 /* Fine tune PLL performance */
2613 rtl_writephy(tp, 0x1f, 0x0002);
2614 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2615 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2617 /* Switching regulator Slew rate */
2618 rtl_writephy(tp, 0x1f, 0x0002);
2619 rtl_patchphy(tp, 0x0f, 0x0017);
2621 rtl_writephy(tp, 0x1f, 0x0005);
2622 rtl_writephy(tp, 0x05, 0x001b);
2624 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2626 rtl_writephy(tp, 0x1f, 0x0000);
2629 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2631 static const struct phy_reg phy_reg_init[] = {
2687 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2690 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2692 static const struct phy_reg phy_reg_init[] = {
2702 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2703 rtl_patchphy(tp, 0x0d, 1 << 5);
2706 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
2708 static const struct phy_reg phy_reg_init[] = {
2709 /* Enable Delay cap */
2715 /* Channel estimation fine tune */
2724 /* Update PFM & 10M TX idle timer */
2736 rtl_apply_firmware(tp);
2738 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2740 /* DCO enable for 10M IDLE Power */
2741 rtl_writephy(tp, 0x1f, 0x0007);
2742 rtl_writephy(tp, 0x1e, 0x0023);
2743 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2744 rtl_writephy(tp, 0x1f, 0x0000);
2746 /* For impedance matching */
2747 rtl_writephy(tp, 0x1f, 0x0002);
2748 rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
2749 rtl_writephy(tp, 0x1f, 0x0000);
2751 /* PHY auto speed down */
2752 rtl_writephy(tp, 0x1f, 0x0007);
2753 rtl_writephy(tp, 0x1e, 0x002d);
2754 rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2755 rtl_writephy(tp, 0x1f, 0x0000);
2756 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2758 rtl_writephy(tp, 0x1f, 0x0005);
2759 rtl_writephy(tp, 0x05, 0x8b86);
2760 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2761 rtl_writephy(tp, 0x1f, 0x0000);
2763 rtl_writephy(tp, 0x1f, 0x0005);
2764 rtl_writephy(tp, 0x05, 0x8b85);
2765 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2766 rtl_writephy(tp, 0x1f, 0x0007);
2767 rtl_writephy(tp, 0x1e, 0x0020);
2768 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2769 rtl_writephy(tp, 0x1f, 0x0006);
2770 rtl_writephy(tp, 0x00, 0x5a00);
2771 rtl_writephy(tp, 0x1f, 0x0000);
2772 rtl_writephy(tp, 0x0d, 0x0007);
2773 rtl_writephy(tp, 0x0e, 0x003c);
2774 rtl_writephy(tp, 0x0d, 0x4007);
2775 rtl_writephy(tp, 0x0e, 0x0000);
2776 rtl_writephy(tp, 0x0d, 0x0000);
2779 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
2781 static const struct phy_reg phy_reg_init[] = {
2782 /* Enable Delay cap */
2791 /* Channel estimation fine tune */
2808 rtl_apply_firmware(tp);
2810 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2812 /* For 4-corner performance improve */
2813 rtl_writephy(tp, 0x1f, 0x0005);
2814 rtl_writephy(tp, 0x05, 0x8b80);
2815 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2816 rtl_writephy(tp, 0x1f, 0x0000);
2818 /* PHY auto speed down */
2819 rtl_writephy(tp, 0x1f, 0x0004);
2820 rtl_writephy(tp, 0x1f, 0x0007);
2821 rtl_writephy(tp, 0x1e, 0x002d);
2822 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
2823 rtl_writephy(tp, 0x1f, 0x0002);
2824 rtl_writephy(tp, 0x1f, 0x0000);
2825 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2827 /* improve 10M EEE waveform */
2828 rtl_writephy(tp, 0x1f, 0x0005);
2829 rtl_writephy(tp, 0x05, 0x8b86);
2830 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2831 rtl_writephy(tp, 0x1f, 0x0000);
2833 /* Improve 2-pair detection performance */
2834 rtl_writephy(tp, 0x1f, 0x0005);
2835 rtl_writephy(tp, 0x05, 0x8b85);
2836 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
2837 rtl_writephy(tp, 0x1f, 0x0000);
2840 rtl_w1w0_eri(tp->mmio_addr, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003,
2842 rtl_writephy(tp, 0x1f, 0x0005);
2843 rtl_writephy(tp, 0x05, 0x8b85);
2844 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2845 rtl_writephy(tp, 0x1f, 0x0004);
2846 rtl_writephy(tp, 0x1f, 0x0007);
2847 rtl_writephy(tp, 0x1e, 0x0020);
2848 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
2849 rtl_writephy(tp, 0x1f, 0x0002);
2850 rtl_writephy(tp, 0x1f, 0x0000);
2851 rtl_writephy(tp, 0x0d, 0x0007);
2852 rtl_writephy(tp, 0x0e, 0x003c);
2853 rtl_writephy(tp, 0x0d, 0x4007);
2854 rtl_writephy(tp, 0x0e, 0x0000);
2855 rtl_writephy(tp, 0x0d, 0x0000);
2858 rtl_writephy(tp, 0x1f, 0x0003);
2859 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
2860 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
2861 rtl_writephy(tp, 0x1f, 0x0000);
2864 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2866 static const struct phy_reg phy_reg_init[] = {
2873 rtl_writephy(tp, 0x1f, 0x0000);
2874 rtl_patchphy(tp, 0x11, 1 << 12);
2875 rtl_patchphy(tp, 0x19, 1 << 13);
2876 rtl_patchphy(tp, 0x10, 1 << 15);
2878 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2881 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
2883 static const struct phy_reg phy_reg_init[] = {
2897 /* Disable ALDPS before ram code */
2898 rtl_writephy(tp, 0x1f, 0x0000);
2899 rtl_writephy(tp, 0x18, 0x0310);
2902 rtl_apply_firmware(tp);
2904 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2907 static void rtl_hw_phy_config(struct net_device *dev)
2909 struct rtl8169_private *tp = netdev_priv(dev);
2911 rtl8169_print_mac_version(tp);
2913 switch (tp->mac_version) {
2914 case RTL_GIGA_MAC_VER_01:
2916 case RTL_GIGA_MAC_VER_02:
2917 case RTL_GIGA_MAC_VER_03:
2918 rtl8169s_hw_phy_config(tp);
2920 case RTL_GIGA_MAC_VER_04:
2921 rtl8169sb_hw_phy_config(tp);
2923 case RTL_GIGA_MAC_VER_05:
2924 rtl8169scd_hw_phy_config(tp);
2926 case RTL_GIGA_MAC_VER_06:
2927 rtl8169sce_hw_phy_config(tp);
2929 case RTL_GIGA_MAC_VER_07:
2930 case RTL_GIGA_MAC_VER_08:
2931 case RTL_GIGA_MAC_VER_09:
2932 rtl8102e_hw_phy_config(tp);
2934 case RTL_GIGA_MAC_VER_11:
2935 rtl8168bb_hw_phy_config(tp);
2937 case RTL_GIGA_MAC_VER_12:
2938 rtl8168bef_hw_phy_config(tp);
2940 case RTL_GIGA_MAC_VER_17:
2941 rtl8168bef_hw_phy_config(tp);
2943 case RTL_GIGA_MAC_VER_18:
2944 rtl8168cp_1_hw_phy_config(tp);
2946 case RTL_GIGA_MAC_VER_19:
2947 rtl8168c_1_hw_phy_config(tp);
2949 case RTL_GIGA_MAC_VER_20:
2950 rtl8168c_2_hw_phy_config(tp);
2952 case RTL_GIGA_MAC_VER_21:
2953 rtl8168c_3_hw_phy_config(tp);
2955 case RTL_GIGA_MAC_VER_22:
2956 rtl8168c_4_hw_phy_config(tp);
2958 case RTL_GIGA_MAC_VER_23:
2959 case RTL_GIGA_MAC_VER_24:
2960 rtl8168cp_2_hw_phy_config(tp);
2962 case RTL_GIGA_MAC_VER_25:
2963 rtl8168d_1_hw_phy_config(tp);
2965 case RTL_GIGA_MAC_VER_26:
2966 rtl8168d_2_hw_phy_config(tp);
2968 case RTL_GIGA_MAC_VER_27:
2969 rtl8168d_3_hw_phy_config(tp);
2971 case RTL_GIGA_MAC_VER_28:
2972 rtl8168d_4_hw_phy_config(tp);
2974 case RTL_GIGA_MAC_VER_29:
2975 case RTL_GIGA_MAC_VER_30:
2976 rtl8105e_hw_phy_config(tp);
2978 case RTL_GIGA_MAC_VER_31:
2981 case RTL_GIGA_MAC_VER_32:
2982 case RTL_GIGA_MAC_VER_33:
2983 rtl8168e_1_hw_phy_config(tp);
2985 case RTL_GIGA_MAC_VER_34:
2986 rtl8168e_2_hw_phy_config(tp);
2994 static void rtl8169_phy_timer(unsigned long __opaque)
2996 struct net_device *dev = (struct net_device *)__opaque;
2997 struct rtl8169_private *tp = netdev_priv(dev);
2998 struct timer_list *timer = &tp->timer;
2999 void __iomem *ioaddr = tp->mmio_addr;
3000 unsigned long timeout = RTL8169_PHY_TIMEOUT;
3002 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
3004 spin_lock_irq(&tp->lock);
3006 if (tp->phy_reset_pending(tp)) {
3008 * A busy loop could burn quite a few cycles on nowadays CPU.
3009 * Let's delay the execution of the timer for a few ticks.
3015 if (tp->link_ok(ioaddr))
3018 netif_warn(tp, link, dev, "PHY reset until link up\n");
3020 tp->phy_reset_enable(tp);
3023 mod_timer(timer, jiffies + timeout);
3025 spin_unlock_irq(&tp->lock);
3028 #ifdef CONFIG_NET_POLL_CONTROLLER
3030 * Polling 'interrupt' - used by things like netconsole to send skbs
3031 * without having to re-enable interrupts. It's not called while
3032 * the interrupt routine is executing.
3034 static void rtl8169_netpoll(struct net_device *dev)
3036 struct rtl8169_private *tp = netdev_priv(dev);
3037 struct pci_dev *pdev = tp->pci_dev;
3039 disable_irq(pdev->irq);
3040 rtl8169_interrupt(pdev->irq, dev);
3041 enable_irq(pdev->irq);
3045 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3046 void __iomem *ioaddr)
3049 pci_release_regions(pdev);
3050 pci_clear_mwi(pdev);
3051 pci_disable_device(pdev);
3055 static void rtl8169_phy_reset(struct net_device *dev,
3056 struct rtl8169_private *tp)
3060 tp->phy_reset_enable(tp);
3061 for (i = 0; i < 100; i++) {
3062 if (!tp->phy_reset_pending(tp))
3066 netif_err(tp, link, dev, "PHY reset failed\n");
3069 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3071 void __iomem *ioaddr = tp->mmio_addr;
3073 rtl_hw_phy_config(dev);
3075 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3076 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3080 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3082 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3083 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
3085 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
3086 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3088 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
3089 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
3092 rtl8169_phy_reset(dev, tp);
3094 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
3095 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3096 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3097 (tp->mii.supports_gmii ?
3098 ADVERTISED_1000baseT_Half |
3099 ADVERTISED_1000baseT_Full : 0));
3101 if (RTL_R8(PHYstatus) & TBI_Enable)
3102 netif_info(tp, link, dev, "TBI auto-negotiating\n");
3105 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3107 void __iomem *ioaddr = tp->mmio_addr;
3111 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
3112 high = addr[4] | (addr[5] << 8);
3114 spin_lock_irq(&tp->lock);
3116 RTL_W8(Cfg9346, Cfg9346_Unlock);
3118 RTL_W32(MAC4, high);
3124 RTL_W8(Cfg9346, Cfg9346_Lock);
3126 spin_unlock_irq(&tp->lock);
3129 static int rtl_set_mac_address(struct net_device *dev, void *p)
3131 struct rtl8169_private *tp = netdev_priv(dev);
3132 struct sockaddr *addr = p;
3134 if (!is_valid_ether_addr(addr->sa_data))
3135 return -EADDRNOTAVAIL;
3137 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3139 rtl_rar_set(tp, dev->dev_addr);
3144 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3146 struct rtl8169_private *tp = netdev_priv(dev);
3147 struct mii_ioctl_data *data = if_mii(ifr);
3149 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
3152 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
3153 struct mii_ioctl_data *data, int cmd)
3157 data->phy_id = 32; /* Internal PHY */
3161 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
3165 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
3171 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
3176 static const struct rtl_cfg_info {
3177 void (*hw_start)(struct net_device *);
3178 unsigned int region;
3184 } rtl_cfg_infos [] = {
3186 .hw_start = rtl_hw_start_8169,
3189 .intr_event = SYSErr | LinkChg | RxOverflow |
3190 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
3191 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
3192 .features = RTL_FEATURE_GMII,
3193 .default_ver = RTL_GIGA_MAC_VER_01,
3196 .hw_start = rtl_hw_start_8168,
3199 .intr_event = SYSErr | LinkChg | RxOverflow |
3200 TxErr | TxOK | RxOK | RxErr,
3201 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
3202 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
3203 .default_ver = RTL_GIGA_MAC_VER_11,
3206 .hw_start = rtl_hw_start_8101,
3209 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
3210 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
3211 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
3212 .features = RTL_FEATURE_MSI,
3213 .default_ver = RTL_GIGA_MAC_VER_13,
3217 /* Cfg9346_Unlock assumed. */
3218 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
3219 const struct rtl_cfg_info *cfg)
3224 cfg2 = RTL_R8(Config2) & ~MSIEnable;
3225 if (cfg->features & RTL_FEATURE_MSI) {
3226 if (pci_enable_msi(pdev)) {
3227 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
3230 msi = RTL_FEATURE_MSI;
3233 RTL_W8(Config2, cfg2);
3237 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3239 if (tp->features & RTL_FEATURE_MSI) {
3240 pci_disable_msi(pdev);
3241 tp->features &= ~RTL_FEATURE_MSI;
3245 static const struct net_device_ops rtl8169_netdev_ops = {
3246 .ndo_open = rtl8169_open,
3247 .ndo_stop = rtl8169_close,
3248 .ndo_get_stats = rtl8169_get_stats,
3249 .ndo_start_xmit = rtl8169_start_xmit,
3250 .ndo_tx_timeout = rtl8169_tx_timeout,
3251 .ndo_validate_addr = eth_validate_addr,
3252 .ndo_change_mtu = rtl8169_change_mtu,
3253 .ndo_fix_features = rtl8169_fix_features,
3254 .ndo_set_features = rtl8169_set_features,
3255 .ndo_set_mac_address = rtl_set_mac_address,
3256 .ndo_do_ioctl = rtl8169_ioctl,
3257 .ndo_set_multicast_list = rtl_set_rx_mode,
3258 #ifdef CONFIG_NET_POLL_CONTROLLER
3259 .ndo_poll_controller = rtl8169_netpoll,
3264 static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
3266 struct mdio_ops *ops = &tp->mdio_ops;
3268 switch (tp->mac_version) {
3269 case RTL_GIGA_MAC_VER_27:
3270 ops->write = r8168dp_1_mdio_write;
3271 ops->read = r8168dp_1_mdio_read;
3273 case RTL_GIGA_MAC_VER_28:
3274 case RTL_GIGA_MAC_VER_31:
3275 ops->write = r8168dp_2_mdio_write;
3276 ops->read = r8168dp_2_mdio_read;
3279 ops->write = r8169_mdio_write;
3280 ops->read = r8169_mdio_read;
3285 static void r810x_phy_power_down(struct rtl8169_private *tp)
3287 rtl_writephy(tp, 0x1f, 0x0000);
3288 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3291 static void r810x_phy_power_up(struct rtl8169_private *tp)
3293 rtl_writephy(tp, 0x1f, 0x0000);
3294 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3297 static void r810x_pll_power_down(struct rtl8169_private *tp)
3299 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3300 rtl_writephy(tp, 0x1f, 0x0000);
3301 rtl_writephy(tp, MII_BMCR, 0x0000);
3305 r810x_phy_power_down(tp);
3308 static void r810x_pll_power_up(struct rtl8169_private *tp)
3310 r810x_phy_power_up(tp);
3313 static void r8168_phy_power_up(struct rtl8169_private *tp)
3315 rtl_writephy(tp, 0x1f, 0x0000);
3316 switch (tp->mac_version) {
3317 case RTL_GIGA_MAC_VER_11:
3318 case RTL_GIGA_MAC_VER_12:
3319 case RTL_GIGA_MAC_VER_17:
3320 case RTL_GIGA_MAC_VER_18:
3321 case RTL_GIGA_MAC_VER_19:
3322 case RTL_GIGA_MAC_VER_20:
3323 case RTL_GIGA_MAC_VER_21:
3324 case RTL_GIGA_MAC_VER_22:
3325 case RTL_GIGA_MAC_VER_23:
3326 case RTL_GIGA_MAC_VER_24:
3327 case RTL_GIGA_MAC_VER_25:
3328 case RTL_GIGA_MAC_VER_26:
3329 case RTL_GIGA_MAC_VER_27:
3330 case RTL_GIGA_MAC_VER_28:
3331 case RTL_GIGA_MAC_VER_31:
3332 rtl_writephy(tp, 0x0e, 0x0000);
3337 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3340 static void r8168_phy_power_down(struct rtl8169_private *tp)
3342 rtl_writephy(tp, 0x1f, 0x0000);
3343 switch (tp->mac_version) {
3344 case RTL_GIGA_MAC_VER_32:
3345 case RTL_GIGA_MAC_VER_33:
3346 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3349 case RTL_GIGA_MAC_VER_11:
3350 case RTL_GIGA_MAC_VER_12:
3351 case RTL_GIGA_MAC_VER_17:
3352 case RTL_GIGA_MAC_VER_18:
3353 case RTL_GIGA_MAC_VER_19:
3354 case RTL_GIGA_MAC_VER_20:
3355 case RTL_GIGA_MAC_VER_21:
3356 case RTL_GIGA_MAC_VER_22:
3357 case RTL_GIGA_MAC_VER_23:
3358 case RTL_GIGA_MAC_VER_24:
3359 case RTL_GIGA_MAC_VER_25:
3360 case RTL_GIGA_MAC_VER_26:
3361 case RTL_GIGA_MAC_VER_27:
3362 case RTL_GIGA_MAC_VER_28:
3363 case RTL_GIGA_MAC_VER_31:
3364 rtl_writephy(tp, 0x0e, 0x0200);
3366 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3371 static void r8168_pll_power_down(struct rtl8169_private *tp)
3373 void __iomem *ioaddr = tp->mmio_addr;
3375 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3376 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3377 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3378 r8168dp_check_dash(tp)) {
3382 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
3383 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
3384 (RTL_R16(CPlusCmd) & ASF)) {
3388 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3389 tp->mac_version == RTL_GIGA_MAC_VER_33)
3390 rtl_ephy_write(ioaddr, 0x19, 0xff64);
3392 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3393 rtl_writephy(tp, 0x1f, 0x0000);
3394 rtl_writephy(tp, MII_BMCR, 0x0000);
3396 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3397 tp->mac_version == RTL_GIGA_MAC_VER_33)
3398 RTL_W32(RxConfig, RTL_R32(RxConfig) | AcceptBroadcast |
3399 AcceptMulticast | AcceptMyPhys);
3403 r8168_phy_power_down(tp);
3405 switch (tp->mac_version) {
3406 case RTL_GIGA_MAC_VER_25:
3407 case RTL_GIGA_MAC_VER_26:
3408 case RTL_GIGA_MAC_VER_27:
3409 case RTL_GIGA_MAC_VER_28:
3410 case RTL_GIGA_MAC_VER_31:
3411 case RTL_GIGA_MAC_VER_32:
3412 case RTL_GIGA_MAC_VER_33:
3413 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3418 static void r8168_pll_power_up(struct rtl8169_private *tp)
3420 void __iomem *ioaddr = tp->mmio_addr;
3422 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3423 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3424 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3425 r8168dp_check_dash(tp)) {
3429 switch (tp->mac_version) {
3430 case RTL_GIGA_MAC_VER_25:
3431 case RTL_GIGA_MAC_VER_26:
3432 case RTL_GIGA_MAC_VER_27:
3433 case RTL_GIGA_MAC_VER_28:
3434 case RTL_GIGA_MAC_VER_31:
3435 case RTL_GIGA_MAC_VER_32:
3436 case RTL_GIGA_MAC_VER_33:
3437 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3441 r8168_phy_power_up(tp);
3444 static void rtl_pll_power_op(struct rtl8169_private *tp,
3445 void (*op)(struct rtl8169_private *))
3451 static void rtl_pll_power_down(struct rtl8169_private *tp)
3453 rtl_pll_power_op(tp, tp->pll_power_ops.down);
3456 static void rtl_pll_power_up(struct rtl8169_private *tp)
3458 rtl_pll_power_op(tp, tp->pll_power_ops.up);
3461 static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3463 struct pll_power_ops *ops = &tp->pll_power_ops;
3465 switch (tp->mac_version) {
3466 case RTL_GIGA_MAC_VER_07:
3467 case RTL_GIGA_MAC_VER_08:
3468 case RTL_GIGA_MAC_VER_09:
3469 case RTL_GIGA_MAC_VER_10:
3470 case RTL_GIGA_MAC_VER_16:
3471 case RTL_GIGA_MAC_VER_29:
3472 case RTL_GIGA_MAC_VER_30:
3473 ops->down = r810x_pll_power_down;
3474 ops->up = r810x_pll_power_up;
3477 case RTL_GIGA_MAC_VER_11:
3478 case RTL_GIGA_MAC_VER_12:
3479 case RTL_GIGA_MAC_VER_17:
3480 case RTL_GIGA_MAC_VER_18:
3481 case RTL_GIGA_MAC_VER_19:
3482 case RTL_GIGA_MAC_VER_20:
3483 case RTL_GIGA_MAC_VER_21:
3484 case RTL_GIGA_MAC_VER_22:
3485 case RTL_GIGA_MAC_VER_23:
3486 case RTL_GIGA_MAC_VER_24:
3487 case RTL_GIGA_MAC_VER_25:
3488 case RTL_GIGA_MAC_VER_26:
3489 case RTL_GIGA_MAC_VER_27:
3490 case RTL_GIGA_MAC_VER_28:
3491 case RTL_GIGA_MAC_VER_31:
3492 case RTL_GIGA_MAC_VER_32:
3493 case RTL_GIGA_MAC_VER_33:
3494 case RTL_GIGA_MAC_VER_34:
3495 ops->down = r8168_pll_power_down;
3496 ops->up = r8168_pll_power_up;
3506 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3508 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
3511 static void rtl_hw_reset(struct rtl8169_private *tp)
3513 void __iomem *ioaddr = tp->mmio_addr;
3516 /* Soft reset the chip. */
3517 RTL_W8(ChipCmd, CmdReset);
3519 /* Check that the chip has finished the reset. */
3520 for (i = 0; i < 100; i++) {
3521 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3526 rtl8169_init_ring_indexes(tp);
3529 static int __devinit
3530 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3532 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
3533 const unsigned int region = cfg->region;
3534 struct rtl8169_private *tp;
3535 struct mii_if_info *mii;
3536 struct net_device *dev;
3537 void __iomem *ioaddr;
3541 if (netif_msg_drv(&debug)) {
3542 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
3543 MODULENAME, RTL8169_VERSION);
3546 dev = alloc_etherdev(sizeof (*tp));
3548 if (netif_msg_drv(&debug))
3549 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
3554 SET_NETDEV_DEV(dev, &pdev->dev);
3555 dev->netdev_ops = &rtl8169_netdev_ops;
3556 tp = netdev_priv(dev);
3559 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
3563 mii->mdio_read = rtl_mdio_read;
3564 mii->mdio_write = rtl_mdio_write;
3565 mii->phy_id_mask = 0x1f;
3566 mii->reg_num_mask = 0x1f;
3567 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3569 /* disable ASPM completely as that cause random device stop working
3570 * problems as well as full system hangs for some PCIe devices users */
3571 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3572 PCIE_LINK_STATE_CLKPM);
3574 /* enable device (incl. PCI PM wakeup and hotplug setup) */
3575 rc = pci_enable_device(pdev);
3577 netif_err(tp, probe, dev, "enable failure\n");
3578 goto err_out_free_dev_1;
3581 if (pci_set_mwi(pdev) < 0)
3582 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
3584 /* make sure PCI base addr 1 is MMIO */
3585 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
3586 netif_err(tp, probe, dev,
3587 "region #%d not an MMIO resource, aborting\n",
3593 /* check for weird/broken PCI region reporting */
3594 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
3595 netif_err(tp, probe, dev,
3596 "Invalid PCI region size(s), aborting\n");
3601 rc = pci_request_regions(pdev, MODULENAME);
3603 netif_err(tp, probe, dev, "could not request regions\n");
3607 tp->cp_cmd = RxChkSum;
3609 if ((sizeof(dma_addr_t) > 4) &&
3610 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
3611 tp->cp_cmd |= PCIDAC;
3612 dev->features |= NETIF_F_HIGHDMA;
3614 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3616 netif_err(tp, probe, dev, "DMA configuration failed\n");
3617 goto err_out_free_res_3;
3621 /* ioremap MMIO region */
3622 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
3624 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
3626 goto err_out_free_res_3;
3628 tp->mmio_addr = ioaddr;
3630 if (!pci_is_pcie(pdev))
3631 netif_info(tp, probe, dev, "not PCI Express\n");
3633 RTL_W16(IntrMask, 0x0000);
3637 RTL_W16(IntrStatus, 0xffff);
3639 pci_set_master(pdev);
3641 /* Identify chip attached to board */
3642 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
3645 * Pretend we are using VLANs; This bypasses a nasty bug where
3646 * Interrupts stop flowing on high load on 8110SCd controllers.
3648 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3649 tp->cp_cmd |= RxVlan;
3651 rtl_init_mdio_ops(tp);
3652 rtl_init_pll_power_ops(tp);
3654 rtl8169_print_mac_version(tp);
3656 chipset = tp->mac_version;
3657 tp->txd_version = rtl_chip_infos[chipset].txd_version;
3659 RTL_W8(Cfg9346, Cfg9346_Unlock);
3660 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3661 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
3662 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3663 tp->features |= RTL_FEATURE_WOL;
3664 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3665 tp->features |= RTL_FEATURE_WOL;
3666 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
3667 RTL_W8(Cfg9346, Cfg9346_Lock);
3669 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3670 (RTL_R8(PHYstatus) & TBI_Enable)) {
3671 tp->set_speed = rtl8169_set_speed_tbi;
3672 tp->get_settings = rtl8169_gset_tbi;
3673 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3674 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3675 tp->link_ok = rtl8169_tbi_link_ok;
3676 tp->do_ioctl = rtl_tbi_ioctl;
3678 tp->set_speed = rtl8169_set_speed_xmii;
3679 tp->get_settings = rtl8169_gset_xmii;
3680 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3681 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3682 tp->link_ok = rtl8169_xmii_link_ok;
3683 tp->do_ioctl = rtl_xmii_ioctl;
3686 spin_lock_init(&tp->lock);
3688 /* Get MAC address */
3689 for (i = 0; i < MAC_ADDR_LEN; i++)
3690 dev->dev_addr[i] = RTL_R8(MAC0 + i);
3691 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3693 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
3694 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3695 dev->irq = pdev->irq;
3696 dev->base_addr = (unsigned long) ioaddr;
3698 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
3700 /* don't enable SG, IP_CSUM and TSO by default - it might not work
3701 * properly for all devices */
3702 dev->features |= NETIF_F_RXCSUM |
3703 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3705 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3706 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3707 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3710 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3711 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
3712 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
3714 tp->intr_mask = 0xffff;
3715 tp->hw_start = cfg->hw_start;
3716 tp->intr_event = cfg->intr_event;
3717 tp->napi_event = cfg->napi_event;
3719 init_timer(&tp->timer);
3720 tp->timer.data = (unsigned long) dev;
3721 tp->timer.function = rtl8169_phy_timer;
3723 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
3725 rc = register_netdev(dev);
3729 pci_set_drvdata(pdev, dev);
3731 netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
3732 rtl_chip_infos[chipset].name, dev->base_addr, dev->dev_addr,
3733 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
3735 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3736 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3737 tp->mac_version == RTL_GIGA_MAC_VER_31) {
3738 rtl8168_driver_start(tp);
3741 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
3743 if (pci_dev_run_wake(pdev))
3744 pm_runtime_put_noidle(&pdev->dev);
3746 netif_carrier_off(dev);
3752 rtl_disable_msi(pdev, tp);
3755 pci_release_regions(pdev);
3757 pci_clear_mwi(pdev);
3758 pci_disable_device(pdev);
3764 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
3766 struct net_device *dev = pci_get_drvdata(pdev);
3767 struct rtl8169_private *tp = netdev_priv(dev);
3769 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3770 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3771 tp->mac_version == RTL_GIGA_MAC_VER_31) {
3772 rtl8168_driver_stop(tp);
3775 cancel_delayed_work_sync(&tp->task);
3777 unregister_netdev(dev);
3779 rtl_release_firmware(tp);
3781 if (pci_dev_run_wake(pdev))
3782 pm_runtime_get_noresume(&pdev->dev);
3784 /* restore original MAC address */
3785 rtl_rar_set(tp, dev->perm_addr);
3787 rtl_disable_msi(pdev, tp);
3788 rtl8169_release_board(pdev, dev, tp->mmio_addr);
3789 pci_set_drvdata(pdev, NULL);
3792 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
3794 struct rtl_fw *rtl_fw;
3798 name = rtl_lookup_firmware_name(tp);
3800 goto out_no_firmware;
3802 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
3806 rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
3810 rc = rtl_check_firmware(tp, rtl_fw);
3812 goto err_release_firmware;
3814 tp->rtl_fw = rtl_fw;
3818 err_release_firmware:
3819 release_firmware(rtl_fw->fw);
3823 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
3830 static void rtl_request_firmware(struct rtl8169_private *tp)
3832 if (IS_ERR(tp->rtl_fw))
3833 rtl_request_uncached_firmware(tp);
3836 static int rtl8169_open(struct net_device *dev)
3838 struct rtl8169_private *tp = netdev_priv(dev);
3839 void __iomem *ioaddr = tp->mmio_addr;
3840 struct pci_dev *pdev = tp->pci_dev;
3841 int retval = -ENOMEM;
3843 pm_runtime_get_sync(&pdev->dev);
3846 * Rx and Tx desscriptors needs 256 bytes alignment.
3847 * dma_alloc_coherent provides more.
3849 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
3850 &tp->TxPhyAddr, GFP_KERNEL);
3851 if (!tp->TxDescArray)
3852 goto err_pm_runtime_put;
3854 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
3855 &tp->RxPhyAddr, GFP_KERNEL);
3856 if (!tp->RxDescArray)
3859 retval = rtl8169_init_ring(dev);
3863 INIT_DELAYED_WORK(&tp->task, NULL);
3867 rtl_request_firmware(tp);
3869 retval = request_irq(dev->irq, rtl8169_interrupt,
3870 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
3873 goto err_release_fw_2;
3875 napi_enable(&tp->napi);
3877 rtl8169_init_phy(dev, tp);
3879 rtl8169_set_features(dev, dev->features);
3881 rtl_pll_power_up(tp);
3885 tp->saved_wolopts = 0;
3886 pm_runtime_put_noidle(&pdev->dev);
3888 rtl8169_check_link_status(dev, tp, ioaddr);
3893 rtl_release_firmware(tp);
3894 rtl8169_rx_clear(tp);
3896 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
3898 tp->RxDescArray = NULL;
3900 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
3902 tp->TxDescArray = NULL;
3904 pm_runtime_put_noidle(&pdev->dev);
3908 static void rtl_rx_close(struct rtl8169_private *tp)
3910 void __iomem *ioaddr = tp->mmio_addr;
3911 u32 rxcfg = RTL_R32(RxConfig);
3913 rxcfg &= ~(AcceptErr | AcceptRunt | AcceptBroadcast | AcceptMulticast |
3914 AcceptMyPhys | AcceptAllPhys);
3915 RTL_W32(RxConfig, rxcfg);
3918 static void rtl8169_hw_reset(struct rtl8169_private *tp)
3920 void __iomem *ioaddr = tp->mmio_addr;
3922 /* Disable interrupts */
3923 rtl8169_irq_mask_and_ack(ioaddr);
3927 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3928 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3929 tp->mac_version == RTL_GIGA_MAC_VER_31) {
3930 while (RTL_R8(TxPoll) & NPQ)
3932 } else if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
3933 while (!(RTL_R32(TxConfig) & TXCFG_EMPTY))
3936 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
3943 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
3945 void __iomem *ioaddr = tp->mmio_addr;
3946 u32 cfg = rtl8169_rx_config;
3948 cfg |= (RTL_R32(RxConfig) & RTL_RX_CONFIG_MASK);
3949 RTL_W32(RxConfig, cfg);
3951 /* Set DMA burst size and Interframe Gap Time */
3952 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3953 (InterFrameGap << TxInterFrameGapShift));
3956 static void rtl_hw_start(struct net_device *dev)
3958 struct rtl8169_private *tp = netdev_priv(dev);
3962 netif_start_queue(dev);
3965 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3966 void __iomem *ioaddr)
3969 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3970 * register to be written before TxDescAddrLow to work.
3971 * Switching from MMIO to I/O access fixes the issue as well.
3973 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
3974 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
3975 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
3976 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
3979 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
3983 cmd = RTL_R16(CPlusCmd);
3984 RTL_W16(CPlusCmd, cmd);
3988 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
3990 /* Low hurts. Let's disable the filtering. */
3991 RTL_W16(RxMaxSize, rx_buf_sz + 1);
3994 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
3996 static const struct rtl_cfg2_info {
4001 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4002 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4003 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4004 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
4006 const struct rtl_cfg2_info *p = cfg2_info;
4010 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
4011 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
4012 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4013 RTL_W32(0x7c, p->val);
4019 static void rtl_hw_start_8169(struct net_device *dev)
4021 struct rtl8169_private *tp = netdev_priv(dev);
4022 void __iomem *ioaddr = tp->mmio_addr;
4023 struct pci_dev *pdev = tp->pci_dev;
4025 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4026 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4027 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4030 RTL_W8(Cfg9346, Cfg9346_Unlock);
4031 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4032 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4033 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4034 tp->mac_version == RTL_GIGA_MAC_VER_04)
4035 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4037 RTL_W8(EarlyTxThres, NoEarlyTx);
4039 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4041 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4042 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4043 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4044 tp->mac_version == RTL_GIGA_MAC_VER_04)
4045 rtl_set_rx_tx_config_registers(tp);
4047 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
4049 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4050 tp->mac_version == RTL_GIGA_MAC_VER_03) {
4051 dprintk("Set MAC Reg C+CR Offset 0xE0. "
4052 "Bit-3 and bit-14 MUST be 1\n");
4053 tp->cp_cmd |= (1 << 14);
4056 RTL_W16(CPlusCmd, tp->cp_cmd);
4058 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
4061 * Undocumented corner. Supposedly:
4062 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4064 RTL_W16(IntrMitigate, 0x0000);
4066 rtl_set_rx_tx_desc_registers(tp, ioaddr);
4068 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
4069 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
4070 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
4071 tp->mac_version != RTL_GIGA_MAC_VER_04) {
4072 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4073 rtl_set_rx_tx_config_registers(tp);
4076 RTL_W8(Cfg9346, Cfg9346_Lock);
4078 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4081 RTL_W32(RxMissed, 0);
4083 rtl_set_rx_mode(dev);
4085 /* no early-rx interrupts */
4086 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4088 /* Enable all known interrupts by setting the interrupt mask. */
4089 RTL_W16(IntrMask, tp->intr_event);
4092 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
4094 int cap = pci_pcie_cap(pdev);
4099 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
4100 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
4101 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
4105 static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
4109 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
4110 rtl_csi_write(ioaddr, 0x070c, csi | bits);
4113 static void rtl_csi_access_enable_1(void __iomem *ioaddr)
4115 rtl_csi_access_enable(ioaddr, 0x17000000);
4118 static void rtl_csi_access_enable_2(void __iomem *ioaddr)
4120 rtl_csi_access_enable(ioaddr, 0x27000000);
4124 unsigned int offset;
4129 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
4134 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
4135 rtl_ephy_write(ioaddr, e->offset, w);
4140 static void rtl_disable_clock_request(struct pci_dev *pdev)
4142 int cap = pci_pcie_cap(pdev);
4147 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4148 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
4149 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4153 static void rtl_enable_clock_request(struct pci_dev *pdev)
4155 int cap = pci_pcie_cap(pdev);
4160 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4161 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
4162 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4166 #define R8168_CPCMD_QUIRK_MASK (\
4177 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
4179 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4181 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4183 rtl_tx_performance_tweak(pdev,
4184 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4187 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
4189 rtl_hw_start_8168bb(ioaddr, pdev);
4191 RTL_W8(MaxTxPacketSize, TxPacketMax);
4193 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4196 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
4198 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4200 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4202 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4204 rtl_disable_clock_request(pdev);
4206 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4209 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
4211 static const struct ephy_info e_info_8168cp[] = {
4212 { 0x01, 0, 0x0001 },
4213 { 0x02, 0x0800, 0x1000 },
4214 { 0x03, 0, 0x0042 },
4215 { 0x06, 0x0080, 0x0000 },
4219 rtl_csi_access_enable_2(ioaddr);
4221 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4223 __rtl_hw_start_8168cp(ioaddr, pdev);
4226 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
4228 rtl_csi_access_enable_2(ioaddr);
4230 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4232 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4234 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4237 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
4239 rtl_csi_access_enable_2(ioaddr);
4241 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4244 RTL_W8(DBG_REG, 0x20);
4246 RTL_W8(MaxTxPacketSize, TxPacketMax);
4248 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4250 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4253 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
4255 static const struct ephy_info e_info_8168c_1[] = {
4256 { 0x02, 0x0800, 0x1000 },
4257 { 0x03, 0, 0x0002 },
4258 { 0x06, 0x0080, 0x0000 }
4261 rtl_csi_access_enable_2(ioaddr);
4263 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4265 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4267 __rtl_hw_start_8168cp(ioaddr, pdev);
4270 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
4272 static const struct ephy_info e_info_8168c_2[] = {
4273 { 0x01, 0, 0x0001 },
4274 { 0x03, 0x0400, 0x0220 }
4277 rtl_csi_access_enable_2(ioaddr);
4279 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4281 __rtl_hw_start_8168cp(ioaddr, pdev);
4284 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
4286 rtl_hw_start_8168c_2(ioaddr, pdev);
4289 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
4291 rtl_csi_access_enable_2(ioaddr);
4293 __rtl_hw_start_8168cp(ioaddr, pdev);
4296 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
4298 rtl_csi_access_enable_2(ioaddr);
4300 rtl_disable_clock_request(pdev);
4302 RTL_W8(MaxTxPacketSize, TxPacketMax);
4304 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4306 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4309 static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev)
4311 rtl_csi_access_enable_1(ioaddr);
4313 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4315 RTL_W8(MaxTxPacketSize, TxPacketMax);
4317 rtl_disable_clock_request(pdev);
4320 static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
4322 static const struct ephy_info e_info_8168d_4[] = {
4324 { 0x19, 0x20, 0x50 },
4329 rtl_csi_access_enable_1(ioaddr);
4331 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4333 RTL_W8(MaxTxPacketSize, TxPacketMax);
4335 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4336 const struct ephy_info *e = e_info_8168d_4 + i;
4339 w = rtl_ephy_read(ioaddr, e->offset);
4340 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
4343 rtl_enable_clock_request(pdev);
4346 static void rtl_hw_start_8168e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4348 static const struct ephy_info e_info_8168e_1[] = {
4349 { 0x00, 0x0200, 0x0100 },
4350 { 0x00, 0x0000, 0x0004 },
4351 { 0x06, 0x0002, 0x0001 },
4352 { 0x06, 0x0000, 0x0030 },
4353 { 0x07, 0x0000, 0x2000 },
4354 { 0x00, 0x0000, 0x0020 },
4355 { 0x03, 0x5800, 0x2000 },
4356 { 0x03, 0x0000, 0x0001 },
4357 { 0x01, 0x0800, 0x1000 },
4358 { 0x07, 0x0000, 0x4000 },
4359 { 0x1e, 0x0000, 0x2000 },
4360 { 0x19, 0xffff, 0xfe6c },
4361 { 0x0a, 0x0000, 0x0040 }
4364 rtl_csi_access_enable_2(ioaddr);
4366 rtl_ephy_init(ioaddr, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
4368 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4370 RTL_W8(MaxTxPacketSize, TxPacketMax);
4372 rtl_disable_clock_request(pdev);
4374 /* Reset tx FIFO pointer */
4375 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
4376 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
4378 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4381 static void rtl_hw_start_8168e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4383 static const struct ephy_info e_info_8168e_2[] = {
4384 { 0x09, 0x0000, 0x0080 },
4385 { 0x19, 0x0000, 0x0224 }
4388 rtl_csi_access_enable_1(ioaddr);
4390 rtl_ephy_init(ioaddr, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
4392 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4394 rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4395 rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4396 rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4397 rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4398 rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4399 rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
4400 rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4401 rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4404 RTL_W8(MaxTxPacketSize, 0x27);
4406 rtl_disable_clock_request(pdev);
4408 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4409 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4411 /* Adjust EEE LED frequency */
4412 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4414 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4415 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4416 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4419 static void rtl_hw_start_8168(struct net_device *dev)
4421 struct rtl8169_private *tp = netdev_priv(dev);
4422 void __iomem *ioaddr = tp->mmio_addr;
4423 struct pci_dev *pdev = tp->pci_dev;
4425 RTL_W8(Cfg9346, Cfg9346_Unlock);
4427 RTL_W8(MaxTxPacketSize, TxPacketMax);
4429 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4431 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
4433 RTL_W16(CPlusCmd, tp->cp_cmd);
4435 RTL_W16(IntrMitigate, 0x5151);
4437 /* Work around for RxFIFO overflow. */
4438 if (tp->mac_version == RTL_GIGA_MAC_VER_11 ||
4439 tp->mac_version == RTL_GIGA_MAC_VER_22) {
4440 tp->intr_event |= RxFIFOOver | PCSTimeout;
4441 tp->intr_event &= ~RxOverflow;
4444 rtl_set_rx_tx_desc_registers(tp, ioaddr);
4446 rtl_set_rx_mode(dev);
4448 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4449 (InterFrameGap << TxInterFrameGapShift));
4453 switch (tp->mac_version) {
4454 case RTL_GIGA_MAC_VER_11:
4455 rtl_hw_start_8168bb(ioaddr, pdev);
4458 case RTL_GIGA_MAC_VER_12:
4459 case RTL_GIGA_MAC_VER_17:
4460 rtl_hw_start_8168bef(ioaddr, pdev);
4463 case RTL_GIGA_MAC_VER_18:
4464 rtl_hw_start_8168cp_1(ioaddr, pdev);
4467 case RTL_GIGA_MAC_VER_19:
4468 rtl_hw_start_8168c_1(ioaddr, pdev);
4471 case RTL_GIGA_MAC_VER_20:
4472 rtl_hw_start_8168c_2(ioaddr, pdev);
4475 case RTL_GIGA_MAC_VER_21:
4476 rtl_hw_start_8168c_3(ioaddr, pdev);
4479 case RTL_GIGA_MAC_VER_22:
4480 rtl_hw_start_8168c_4(ioaddr, pdev);
4483 case RTL_GIGA_MAC_VER_23:
4484 rtl_hw_start_8168cp_2(ioaddr, pdev);
4487 case RTL_GIGA_MAC_VER_24:
4488 rtl_hw_start_8168cp_3(ioaddr, pdev);
4491 case RTL_GIGA_MAC_VER_25:
4492 case RTL_GIGA_MAC_VER_26:
4493 case RTL_GIGA_MAC_VER_27:
4494 rtl_hw_start_8168d(ioaddr, pdev);
4497 case RTL_GIGA_MAC_VER_28:
4498 rtl_hw_start_8168d_4(ioaddr, pdev);
4501 case RTL_GIGA_MAC_VER_31:
4502 rtl_hw_start_8168dp(ioaddr, pdev);
4505 case RTL_GIGA_MAC_VER_32:
4506 case RTL_GIGA_MAC_VER_33:
4507 rtl_hw_start_8168e_1(ioaddr, pdev);
4509 case RTL_GIGA_MAC_VER_34:
4510 rtl_hw_start_8168e_2(ioaddr, pdev);
4514 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
4515 dev->name, tp->mac_version);
4519 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4521 RTL_W8(Cfg9346, Cfg9346_Lock);
4523 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4525 RTL_W16(IntrMask, tp->intr_event);
4528 #define R810X_CPCMD_QUIRK_MASK (\
4539 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4541 static const struct ephy_info e_info_8102e_1[] = {
4542 { 0x01, 0, 0x6e65 },
4543 { 0x02, 0, 0x091f },
4544 { 0x03, 0, 0xc2f9 },
4545 { 0x06, 0, 0xafb5 },
4546 { 0x07, 0, 0x0e00 },
4547 { 0x19, 0, 0xec80 },
4548 { 0x01, 0, 0x2e65 },
4553 rtl_csi_access_enable_2(ioaddr);
4555 RTL_W8(DBG_REG, FIX_NAK_1);
4557 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4560 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
4561 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4563 cfg1 = RTL_R8(Config1);
4564 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
4565 RTL_W8(Config1, cfg1 & ~LEDS0);
4567 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
4570 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4572 rtl_csi_access_enable_2(ioaddr);
4574 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4576 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
4577 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4580 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
4582 rtl_hw_start_8102e_2(ioaddr, pdev);
4584 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
4587 static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4589 static const struct ephy_info e_info_8105e_1[] = {
4590 { 0x07, 0, 0x4000 },
4591 { 0x19, 0, 0x0200 },
4592 { 0x19, 0, 0x0020 },
4593 { 0x1e, 0, 0x2000 },
4594 { 0x03, 0, 0x0001 },
4595 { 0x19, 0, 0x0100 },
4596 { 0x19, 0, 0x0004 },
4600 /* Force LAN exit from ASPM if Rx/Tx are not idle */
4601 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
4603 /* Disable Early Tally Counter */
4604 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
4606 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4607 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4609 rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
4612 static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4614 rtl_hw_start_8105e_1(ioaddr, pdev);
4615 rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
4618 static void rtl_hw_start_8101(struct net_device *dev)
4620 struct rtl8169_private *tp = netdev_priv(dev);
4621 void __iomem *ioaddr = tp->mmio_addr;
4622 struct pci_dev *pdev = tp->pci_dev;
4624 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
4625 tp->mac_version == RTL_GIGA_MAC_VER_16) {
4626 int cap = pci_pcie_cap(pdev);
4629 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
4630 PCI_EXP_DEVCTL_NOSNOOP_EN);
4634 RTL_W8(Cfg9346, Cfg9346_Unlock);
4636 switch (tp->mac_version) {
4637 case RTL_GIGA_MAC_VER_07:
4638 rtl_hw_start_8102e_1(ioaddr, pdev);
4641 case RTL_GIGA_MAC_VER_08:
4642 rtl_hw_start_8102e_3(ioaddr, pdev);
4645 case RTL_GIGA_MAC_VER_09:
4646 rtl_hw_start_8102e_2(ioaddr, pdev);
4649 case RTL_GIGA_MAC_VER_29:
4650 rtl_hw_start_8105e_1(ioaddr, pdev);
4652 case RTL_GIGA_MAC_VER_30:
4653 rtl_hw_start_8105e_2(ioaddr, pdev);
4657 RTL_W8(Cfg9346, Cfg9346_Lock);
4659 RTL_W8(MaxTxPacketSize, TxPacketMax);
4661 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4663 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
4664 RTL_W16(CPlusCmd, tp->cp_cmd);
4666 RTL_W16(IntrMitigate, 0x0000);
4668 rtl_set_rx_tx_desc_registers(tp, ioaddr);
4670 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4671 rtl_set_rx_tx_config_registers(tp);
4675 rtl_set_rx_mode(dev);
4677 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
4679 RTL_W16(IntrMask, tp->intr_event);
4682 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
4684 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
4688 netdev_update_features(dev);
4693 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
4695 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
4696 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
4699 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
4700 void **data_buff, struct RxDesc *desc)
4702 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
4707 rtl8169_make_unusable_by_asic(desc);
4710 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
4712 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
4714 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
4717 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
4720 desc->addr = cpu_to_le64(mapping);
4722 rtl8169_mark_to_asic(desc, rx_buf_sz);
4725 static inline void *rtl8169_align(void *data)
4727 return (void *)ALIGN((long)data, 16);
4730 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
4731 struct RxDesc *desc)
4735 struct device *d = &tp->pci_dev->dev;
4736 struct net_device *dev = tp->dev;
4737 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
4739 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
4743 if (rtl8169_align(data) != data) {
4745 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
4750 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
4752 if (unlikely(dma_mapping_error(d, mapping))) {
4753 if (net_ratelimit())
4754 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
4758 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
4766 static void rtl8169_rx_clear(struct rtl8169_private *tp)
4770 for (i = 0; i < NUM_RX_DESC; i++) {
4771 if (tp->Rx_databuff[i]) {
4772 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
4773 tp->RxDescArray + i);
4778 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
4780 desc->opts1 |= cpu_to_le32(RingEnd);
4783 static int rtl8169_rx_fill(struct rtl8169_private *tp)
4787 for (i = 0; i < NUM_RX_DESC; i++) {
4790 if (tp->Rx_databuff[i])
4793 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
4795 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
4798 tp->Rx_databuff[i] = data;
4801 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4805 rtl8169_rx_clear(tp);
4809 static int rtl8169_init_ring(struct net_device *dev)
4811 struct rtl8169_private *tp = netdev_priv(dev);
4813 rtl8169_init_ring_indexes(tp);
4815 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
4816 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
4818 return rtl8169_rx_fill(tp);
4821 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
4822 struct TxDesc *desc)
4824 unsigned int len = tx_skb->len;
4826 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
4834 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4839 for (i = 0; i < n; i++) {
4840 unsigned int entry = (start + i) % NUM_TX_DESC;
4841 struct ring_info *tx_skb = tp->tx_skb + entry;
4842 unsigned int len = tx_skb->len;
4845 struct sk_buff *skb = tx_skb->skb;
4847 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4848 tp->TxDescArray + entry);
4850 tp->dev->stats.tx_dropped++;
4858 static void rtl8169_tx_clear(struct rtl8169_private *tp)
4860 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
4861 tp->cur_tx = tp->dirty_tx = 0;
4864 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
4866 struct rtl8169_private *tp = netdev_priv(dev);
4868 PREPARE_DELAYED_WORK(&tp->task, task);
4869 schedule_delayed_work(&tp->task, 4);
4872 static void rtl8169_wait_for_quiescence(struct net_device *dev)
4874 struct rtl8169_private *tp = netdev_priv(dev);
4875 void __iomem *ioaddr = tp->mmio_addr;
4877 synchronize_irq(dev->irq);
4879 /* Wait for any pending NAPI task to complete */
4880 napi_disable(&tp->napi);
4882 rtl8169_irq_mask_and_ack(ioaddr);
4884 tp->intr_mask = 0xffff;
4885 RTL_W16(IntrMask, tp->intr_event);
4886 napi_enable(&tp->napi);
4889 static void rtl8169_reinit_task(struct work_struct *work)
4891 struct rtl8169_private *tp =
4892 container_of(work, struct rtl8169_private, task.work);
4893 struct net_device *dev = tp->dev;
4898 if (!netif_running(dev))
4901 rtl8169_wait_for_quiescence(dev);
4904 ret = rtl8169_open(dev);
4905 if (unlikely(ret < 0)) {
4906 if (net_ratelimit())
4907 netif_err(tp, drv, dev,
4908 "reinit failure (status = %d). Rescheduling\n",
4910 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4917 static void rtl8169_reset_task(struct work_struct *work)
4919 struct rtl8169_private *tp =
4920 container_of(work, struct rtl8169_private, task.work);
4921 struct net_device *dev = tp->dev;
4926 if (!netif_running(dev))
4929 rtl8169_wait_for_quiescence(dev);
4931 for (i = 0; i < NUM_RX_DESC; i++)
4932 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
4934 rtl8169_tx_clear(tp);
4936 rtl8169_hw_reset(tp);
4938 netif_wake_queue(dev);
4939 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
4945 static void rtl8169_tx_timeout(struct net_device *dev)
4947 struct rtl8169_private *tp = netdev_priv(dev);
4949 rtl8169_hw_reset(tp);
4951 /* Let's wait a bit while any (async) irq lands on */
4952 rtl8169_schedule_work(dev, rtl8169_reset_task);
4955 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4958 struct skb_shared_info *info = skb_shinfo(skb);
4959 unsigned int cur_frag, entry;
4960 struct TxDesc * uninitialized_var(txd);
4961 struct device *d = &tp->pci_dev->dev;
4964 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4965 skb_frag_t *frag = info->frags + cur_frag;
4970 entry = (entry + 1) % NUM_TX_DESC;
4972 txd = tp->TxDescArray + entry;
4974 addr = ((void *) page_address(frag->page)) + frag->page_offset;
4975 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
4976 if (unlikely(dma_mapping_error(d, mapping))) {
4977 if (net_ratelimit())
4978 netif_err(tp, drv, tp->dev,
4979 "Failed to map TX fragments DMA!\n");
4983 /* Anti gcc 2.95.3 bugware (sic) */
4984 status = opts[0] | len |
4985 (RingEnd * !((entry + 1) % NUM_TX_DESC));
4987 txd->opts1 = cpu_to_le32(status);
4988 txd->opts2 = cpu_to_le32(opts[1]);
4989 txd->addr = cpu_to_le64(mapping);
4991 tp->tx_skb[entry].len = len;
4995 tp->tx_skb[entry].skb = skb;
4996 txd->opts1 |= cpu_to_le32(LastFrag);
5002 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5006 static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
5007 struct sk_buff *skb, u32 *opts)
5009 const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
5010 u32 mss = skb_shinfo(skb)->gso_size;
5011 int offset = info->opts_offset;
5015 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
5016 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5017 const struct iphdr *ip = ip_hdr(skb);
5019 if (ip->protocol == IPPROTO_TCP)
5020 opts[offset] |= info->checksum.tcp;
5021 else if (ip->protocol == IPPROTO_UDP)
5022 opts[offset] |= info->checksum.udp;
5028 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5029 struct net_device *dev)
5031 struct rtl8169_private *tp = netdev_priv(dev);
5032 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
5033 struct TxDesc *txd = tp->TxDescArray + entry;
5034 void __iomem *ioaddr = tp->mmio_addr;
5035 struct device *d = &tp->pci_dev->dev;
5041 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
5042 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
5046 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
5049 len = skb_headlen(skb);
5050 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
5051 if (unlikely(dma_mapping_error(d, mapping))) {
5052 if (net_ratelimit())
5053 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
5057 tp->tx_skb[entry].len = len;
5058 txd->addr = cpu_to_le64(mapping);
5060 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
5063 rtl8169_tso_csum(tp, skb, opts);
5065 frags = rtl8169_xmit_frags(tp, skb, opts);
5069 opts[0] |= FirstFrag;
5071 opts[0] |= FirstFrag | LastFrag;
5072 tp->tx_skb[entry].skb = skb;
5075 txd->opts2 = cpu_to_le32(opts[1]);
5079 /* Anti gcc 2.95.3 bugware (sic) */
5080 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
5081 txd->opts1 = cpu_to_le32(status);
5083 tp->cur_tx += frags + 1;
5087 RTL_W8(TxPoll, NPQ);
5089 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
5090 netif_stop_queue(dev);
5092 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
5093 netif_wake_queue(dev);
5096 return NETDEV_TX_OK;
5099 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
5102 dev->stats.tx_dropped++;
5103 return NETDEV_TX_OK;
5106 netif_stop_queue(dev);
5107 dev->stats.tx_dropped++;
5108 return NETDEV_TX_BUSY;
5111 static void rtl8169_pcierr_interrupt(struct net_device *dev)
5113 struct rtl8169_private *tp = netdev_priv(dev);
5114 struct pci_dev *pdev = tp->pci_dev;
5115 u16 pci_status, pci_cmd;
5117 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5118 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5120 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5121 pci_cmd, pci_status);
5124 * The recovery sequence below admits a very elaborated explanation:
5125 * - it seems to work;
5126 * - I did not see what else could be done;
5127 * - it makes iop3xx happy.
5129 * Feel free to adjust to your needs.
5131 if (pdev->broken_parity_status)
5132 pci_cmd &= ~PCI_COMMAND_PARITY;
5134 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5136 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
5138 pci_write_config_word(pdev, PCI_STATUS,
5139 pci_status & (PCI_STATUS_DETECTED_PARITY |
5140 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5141 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5143 /* The infamous DAC f*ckup only happens at boot time */
5144 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
5145 void __iomem *ioaddr = tp->mmio_addr;
5147 netif_info(tp, intr, dev, "disabling PCI DAC\n");
5148 tp->cp_cmd &= ~PCIDAC;
5149 RTL_W16(CPlusCmd, tp->cp_cmd);
5150 dev->features &= ~NETIF_F_HIGHDMA;
5153 rtl8169_hw_reset(tp);
5155 rtl8169_schedule_work(dev, rtl8169_reinit_task);
5158 static void rtl8169_tx_interrupt(struct net_device *dev,
5159 struct rtl8169_private *tp,
5160 void __iomem *ioaddr)
5162 unsigned int dirty_tx, tx_left;
5164 dirty_tx = tp->dirty_tx;
5166 tx_left = tp->cur_tx - dirty_tx;
5168 while (tx_left > 0) {
5169 unsigned int entry = dirty_tx % NUM_TX_DESC;
5170 struct ring_info *tx_skb = tp->tx_skb + entry;
5174 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5175 if (status & DescOwn)
5178 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5179 tp->TxDescArray + entry);
5180 if (status & LastFrag) {
5181 dev->stats.tx_packets++;
5182 dev->stats.tx_bytes += tx_skb->skb->len;
5183 dev_kfree_skb(tx_skb->skb);
5190 if (tp->dirty_tx != dirty_tx) {
5191 tp->dirty_tx = dirty_tx;
5193 if (netif_queue_stopped(dev) &&
5194 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
5195 netif_wake_queue(dev);
5198 * 8168 hack: TxPoll requests are lost when the Tx packets are
5199 * too close. Let's kick an extra TxPoll request when a burst
5200 * of start_xmit activity is detected (if it is not detected,
5201 * it is slow enough). -- FR
5204 if (tp->cur_tx != dirty_tx)
5205 RTL_W8(TxPoll, NPQ);
5209 static inline int rtl8169_fragmented_frame(u32 status)
5211 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
5214 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
5216 u32 status = opts1 & RxProtoMask;
5218 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
5219 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
5220 skb->ip_summed = CHECKSUM_UNNECESSARY;
5222 skb_checksum_none_assert(skb);
5225 static struct sk_buff *rtl8169_try_rx_copy(void *data,
5226 struct rtl8169_private *tp,
5230 struct sk_buff *skb;
5231 struct device *d = &tp->pci_dev->dev;
5233 data = rtl8169_align(data);
5234 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
5236 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
5238 memcpy(skb->data, data, pkt_size);
5239 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
5244 static int rtl8169_rx_interrupt(struct net_device *dev,
5245 struct rtl8169_private *tp,
5246 void __iomem *ioaddr, u32 budget)
5248 unsigned int cur_rx, rx_left;
5251 cur_rx = tp->cur_rx;
5252 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
5253 rx_left = min(rx_left, budget);
5255 for (; rx_left > 0; rx_left--, cur_rx++) {
5256 unsigned int entry = cur_rx % NUM_RX_DESC;
5257 struct RxDesc *desc = tp->RxDescArray + entry;
5261 status = le32_to_cpu(desc->opts1);
5263 if (status & DescOwn)
5265 if (unlikely(status & RxRES)) {
5266 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
5268 dev->stats.rx_errors++;
5269 if (status & (RxRWT | RxRUNT))
5270 dev->stats.rx_length_errors++;
5272 dev->stats.rx_crc_errors++;
5273 if (status & RxFOVF) {
5274 rtl8169_schedule_work(dev, rtl8169_reset_task);
5275 dev->stats.rx_fifo_errors++;
5277 rtl8169_mark_to_asic(desc, rx_buf_sz);
5279 struct sk_buff *skb;
5280 dma_addr_t addr = le64_to_cpu(desc->addr);
5281 int pkt_size = (status & 0x00001FFF) - 4;
5284 * The driver does not support incoming fragmented
5285 * frames. They are seen as a symptom of over-mtu
5288 if (unlikely(rtl8169_fragmented_frame(status))) {
5289 dev->stats.rx_dropped++;
5290 dev->stats.rx_length_errors++;
5291 rtl8169_mark_to_asic(desc, rx_buf_sz);
5295 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
5296 tp, pkt_size, addr);
5297 rtl8169_mark_to_asic(desc, rx_buf_sz);
5299 dev->stats.rx_dropped++;
5303 rtl8169_rx_csum(skb, status);
5304 skb_put(skb, pkt_size);
5305 skb->protocol = eth_type_trans(skb, dev);
5307 rtl8169_rx_vlan_tag(desc, skb);
5309 napi_gro_receive(&tp->napi, skb);
5311 dev->stats.rx_bytes += pkt_size;
5312 dev->stats.rx_packets++;
5315 /* Work around for AMD plateform. */
5316 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
5317 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
5323 count = cur_rx - tp->cur_rx;
5324 tp->cur_rx = cur_rx;
5326 tp->dirty_rx += count;
5331 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
5333 struct net_device *dev = dev_instance;
5334 struct rtl8169_private *tp = netdev_priv(dev);
5335 void __iomem *ioaddr = tp->mmio_addr;
5339 /* loop handling interrupts until we have no new ones or
5340 * we hit a invalid/hotplug case.
5342 status = RTL_R16(IntrStatus);
5343 while (status && status != 0xffff) {
5346 /* Handle all of the error cases first. These will reset
5347 * the chip, so just exit the loop.
5349 if (unlikely(!netif_running(dev))) {
5350 rtl8169_hw_reset(tp);
5354 if (unlikely(status & RxFIFOOver)) {
5355 switch (tp->mac_version) {
5356 /* Work around for rx fifo overflow */
5357 case RTL_GIGA_MAC_VER_11:
5358 case RTL_GIGA_MAC_VER_22:
5359 case RTL_GIGA_MAC_VER_26:
5360 netif_stop_queue(dev);
5361 rtl8169_tx_timeout(dev);
5363 /* Testers needed. */
5364 case RTL_GIGA_MAC_VER_17:
5365 case RTL_GIGA_MAC_VER_19:
5366 case RTL_GIGA_MAC_VER_20:
5367 case RTL_GIGA_MAC_VER_21:
5368 case RTL_GIGA_MAC_VER_23:
5369 case RTL_GIGA_MAC_VER_24:
5370 case RTL_GIGA_MAC_VER_27:
5371 case RTL_GIGA_MAC_VER_28:
5372 case RTL_GIGA_MAC_VER_31:
5373 /* Experimental science. Pktgen proof. */
5374 case RTL_GIGA_MAC_VER_12:
5375 case RTL_GIGA_MAC_VER_25:
5376 if (status == RxFIFOOver)
5384 if (unlikely(status & SYSErr)) {
5385 rtl8169_pcierr_interrupt(dev);
5389 if (status & LinkChg)
5390 __rtl8169_check_link_status(dev, tp, ioaddr, true);
5392 /* We need to see the lastest version of tp->intr_mask to
5393 * avoid ignoring an MSI interrupt and having to wait for
5394 * another event which may never come.
5397 if (status & tp->intr_mask & tp->napi_event) {
5398 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
5399 tp->intr_mask = ~tp->napi_event;
5401 if (likely(napi_schedule_prep(&tp->napi)))
5402 __napi_schedule(&tp->napi);
5404 netif_info(tp, intr, dev,
5405 "interrupt %04x in poll\n", status);
5408 /* We only get a new MSI interrupt when all active irq
5409 * sources on the chip have been acknowledged. So, ack
5410 * everything we've seen and check if new sources have become
5411 * active to avoid blocking all interrupts from the chip.
5414 (status & RxFIFOOver) ? (status | RxOverflow) : status);
5415 status = RTL_R16(IntrStatus);
5418 return IRQ_RETVAL(handled);
5421 static int rtl8169_poll(struct napi_struct *napi, int budget)
5423 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5424 struct net_device *dev = tp->dev;
5425 void __iomem *ioaddr = tp->mmio_addr;
5428 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
5429 rtl8169_tx_interrupt(dev, tp, ioaddr);
5431 if (work_done < budget) {
5432 napi_complete(napi);
5434 /* We need for force the visibility of tp->intr_mask
5435 * for other CPUs, as we can loose an MSI interrupt
5436 * and potentially wait for a retransmit timeout if we don't.
5437 * The posted write to IntrMask is safe, as it will
5438 * eventually make it to the chip and we won't loose anything
5441 tp->intr_mask = 0xffff;
5443 RTL_W16(IntrMask, tp->intr_event);
5449 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
5451 struct rtl8169_private *tp = netdev_priv(dev);
5453 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5456 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
5457 RTL_W32(RxMissed, 0);
5460 static void rtl8169_down(struct net_device *dev)
5462 struct rtl8169_private *tp = netdev_priv(dev);
5463 void __iomem *ioaddr = tp->mmio_addr;
5465 del_timer_sync(&tp->timer);
5467 netif_stop_queue(dev);
5469 napi_disable(&tp->napi);
5471 spin_lock_irq(&tp->lock);
5473 rtl8169_hw_reset(tp);
5475 * At this point device interrupts can not be enabled in any function,
5476 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
5477 * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
5479 rtl8169_rx_missed(dev, ioaddr);
5481 spin_unlock_irq(&tp->lock);
5483 synchronize_irq(dev->irq);
5485 /* Give a racing hard_start_xmit a few cycles to complete. */
5486 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
5488 rtl8169_tx_clear(tp);
5490 rtl8169_rx_clear(tp);
5492 rtl_pll_power_down(tp);
5495 static int rtl8169_close(struct net_device *dev)
5497 struct rtl8169_private *tp = netdev_priv(dev);
5498 struct pci_dev *pdev = tp->pci_dev;
5500 pm_runtime_get_sync(&pdev->dev);
5502 /* Update counters before going down */
5503 rtl8169_update_counters(dev);
5507 free_irq(dev->irq, dev);
5509 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5511 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5513 tp->TxDescArray = NULL;
5514 tp->RxDescArray = NULL;
5516 pm_runtime_put_sync(&pdev->dev);
5521 static void rtl_set_rx_mode(struct net_device *dev)
5523 struct rtl8169_private *tp = netdev_priv(dev);
5524 void __iomem *ioaddr = tp->mmio_addr;
5525 unsigned long flags;
5526 u32 mc_filter[2]; /* Multicast hash filter */
5530 if (dev->flags & IFF_PROMISC) {
5531 /* Unconditionally log net taps. */
5532 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
5534 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5536 mc_filter[1] = mc_filter[0] = 0xffffffff;
5537 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
5538 (dev->flags & IFF_ALLMULTI)) {
5539 /* Too many to filter perfectly -- accept all multicasts. */
5540 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5541 mc_filter[1] = mc_filter[0] = 0xffffffff;
5543 struct netdev_hw_addr *ha;
5545 rx_mode = AcceptBroadcast | AcceptMyPhys;
5546 mc_filter[1] = mc_filter[0] = 0;
5547 netdev_for_each_mc_addr(ha, dev) {
5548 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
5549 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5550 rx_mode |= AcceptMulticast;
5554 spin_lock_irqsave(&tp->lock, flags);
5556 tmp = rtl8169_rx_config | rx_mode |
5557 (RTL_R32(RxConfig) & RTL_RX_CONFIG_MASK);
5559 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
5560 u32 data = mc_filter[0];
5562 mc_filter[0] = swab32(mc_filter[1]);
5563 mc_filter[1] = swab32(data);
5566 RTL_W32(MAR0 + 4, mc_filter[1]);
5567 RTL_W32(MAR0 + 0, mc_filter[0]);
5569 RTL_W32(RxConfig, tmp);
5571 spin_unlock_irqrestore(&tp->lock, flags);
5575 * rtl8169_get_stats - Get rtl8169 read/write statistics
5576 * @dev: The Ethernet Device to get statistics for
5578 * Get TX/RX statistics for rtl8169
5580 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
5582 struct rtl8169_private *tp = netdev_priv(dev);
5583 void __iomem *ioaddr = tp->mmio_addr;
5584 unsigned long flags;
5586 if (netif_running(dev)) {
5587 spin_lock_irqsave(&tp->lock, flags);
5588 rtl8169_rx_missed(dev, ioaddr);
5589 spin_unlock_irqrestore(&tp->lock, flags);
5595 static void rtl8169_net_suspend(struct net_device *dev)
5597 struct rtl8169_private *tp = netdev_priv(dev);
5599 if (!netif_running(dev))
5602 rtl_pll_power_down(tp);
5604 netif_device_detach(dev);
5605 netif_stop_queue(dev);
5610 static int rtl8169_suspend(struct device *device)
5612 struct pci_dev *pdev = to_pci_dev(device);
5613 struct net_device *dev = pci_get_drvdata(pdev);
5615 rtl8169_net_suspend(dev);
5620 static void __rtl8169_resume(struct net_device *dev)
5622 struct rtl8169_private *tp = netdev_priv(dev);
5624 netif_device_attach(dev);
5626 rtl_pll_power_up(tp);
5628 rtl8169_schedule_work(dev, rtl8169_reset_task);
5631 static int rtl8169_resume(struct device *device)
5633 struct pci_dev *pdev = to_pci_dev(device);
5634 struct net_device *dev = pci_get_drvdata(pdev);
5635 struct rtl8169_private *tp = netdev_priv(dev);
5637 rtl8169_init_phy(dev, tp);
5639 if (netif_running(dev))
5640 __rtl8169_resume(dev);
5645 static int rtl8169_runtime_suspend(struct device *device)
5647 struct pci_dev *pdev = to_pci_dev(device);
5648 struct net_device *dev = pci_get_drvdata(pdev);
5649 struct rtl8169_private *tp = netdev_priv(dev);
5651 if (!tp->TxDescArray)
5654 spin_lock_irq(&tp->lock);
5655 tp->saved_wolopts = __rtl8169_get_wol(tp);
5656 __rtl8169_set_wol(tp, WAKE_ANY);
5657 spin_unlock_irq(&tp->lock);
5659 rtl8169_net_suspend(dev);
5664 static int rtl8169_runtime_resume(struct device *device)
5666 struct pci_dev *pdev = to_pci_dev(device);
5667 struct net_device *dev = pci_get_drvdata(pdev);
5668 struct rtl8169_private *tp = netdev_priv(dev);
5670 if (!tp->TxDescArray)
5673 spin_lock_irq(&tp->lock);
5674 __rtl8169_set_wol(tp, tp->saved_wolopts);
5675 tp->saved_wolopts = 0;
5676 spin_unlock_irq(&tp->lock);
5678 rtl8169_init_phy(dev, tp);
5680 __rtl8169_resume(dev);
5685 static int rtl8169_runtime_idle(struct device *device)
5687 struct pci_dev *pdev = to_pci_dev(device);
5688 struct net_device *dev = pci_get_drvdata(pdev);
5689 struct rtl8169_private *tp = netdev_priv(dev);
5691 return tp->TxDescArray ? -EBUSY : 0;
5694 static const struct dev_pm_ops rtl8169_pm_ops = {
5695 .suspend = rtl8169_suspend,
5696 .resume = rtl8169_resume,
5697 .freeze = rtl8169_suspend,
5698 .thaw = rtl8169_resume,
5699 .poweroff = rtl8169_suspend,
5700 .restore = rtl8169_resume,
5701 .runtime_suspend = rtl8169_runtime_suspend,
5702 .runtime_resume = rtl8169_runtime_resume,
5703 .runtime_idle = rtl8169_runtime_idle,
5706 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
5708 #else /* !CONFIG_PM */
5710 #define RTL8169_PM_OPS NULL
5712 #endif /* !CONFIG_PM */
5714 static void rtl_shutdown(struct pci_dev *pdev)
5716 struct net_device *dev = pci_get_drvdata(pdev);
5717 struct rtl8169_private *tp = netdev_priv(dev);
5718 void __iomem *ioaddr = tp->mmio_addr;
5720 rtl8169_net_suspend(dev);
5722 /* Restore original MAC address */
5723 rtl_rar_set(tp, dev->perm_addr);
5725 spin_lock_irq(&tp->lock);
5727 rtl8169_hw_reset(tp);
5729 spin_unlock_irq(&tp->lock);
5731 if (system_state == SYSTEM_POWER_OFF) {
5732 /* WoL fails with some 8168 when the receiver is disabled. */
5733 if (tp->features & RTL_FEATURE_WOL) {
5734 pci_clear_master(pdev);
5736 RTL_W8(ChipCmd, CmdRxEnb);
5741 pci_wake_from_d3(pdev, true);
5742 pci_set_power_state(pdev, PCI_D3hot);
5746 static struct pci_driver rtl8169_pci_driver = {
5748 .id_table = rtl8169_pci_tbl,
5749 .probe = rtl8169_init_one,
5750 .remove = __devexit_p(rtl8169_remove_one),
5751 .shutdown = rtl_shutdown,
5752 .driver.pm = RTL8169_PM_OPS,
5755 static int __init rtl8169_init_module(void)
5757 return pci_register_driver(&rtl8169_pci_driver);
5760 static void __exit rtl8169_cleanup_module(void)
5762 pci_unregister_driver(&rtl8169_pci_driver);
5765 module_init(rtl8169_init_module);
5766 module_exit(rtl8169_cleanup_module);