drivers/net/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/mii.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/crc32.h>
  21 #include <linux/in.h>
  22 #include <linux/ip.h>
  23 #include <linux/tcp.h>
  24 #include <linux/init.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/firmware.h>
  28
  29 #include <asm/system.h>
  30 #include <asm/io.h>
  31 #include <asm/irq.h>
  32
  33 #define RTL8169_VERSION "2.3LK-NAPI"
  34 #define MODULENAME "r8169"
  35 #define PFX MODULENAME ": "
  36
  37 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  38 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  39 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  40
  41 #ifdef RTL8169_DEBUG
  42 #define assert(expr) \
  43         if (!(expr)) {                                  \
  44                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  45                 #expr,__FILE__,__func__,__LINE__);              \
  46         }
  47 #define dprintk(fmt, args...) \
  48         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
  49 #else
  50 #define assert(expr) do {} while (0)
  51 #define dprintk(fmt, args...)   do {} while (0)
  52 #endif /* RTL8169_DEBUG */
  53
  54 #define R8169_MSG_DEFAULT \
  55         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  56
  57 #define TX_BUFFS_AVAIL(tp) \
  58         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
  59
  60 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  61    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  62 static const int multicast_filter_limit = 32;
  63
  64 /* MAC address length */
  65 #define MAC_ADDR_LEN    6
  66
  67 #define MAX_READ_REQUEST_SHIFT  12
  68 #define RX_FIFO_THRESH  7       /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
  69 #define RX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  70 #define TX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  71 #define SafeMtu         0x1c20  /* ... actually life sucks beyond ~7k */
  72 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  73
  74 #define R8169_REGS_SIZE         256
  75 #define R8169_NAPI_WEIGHT       64
  76 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  77 #define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
  78 #define RX_BUF_SIZE     1536    /* Rx Buffer size */
  79 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  80 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  81
  82 #define RTL8169_TX_TIMEOUT      (6*HZ)
  83 #define RTL8169_PHY_TIMEOUT     (10*HZ)
  84
  85 #define RTL_EEPROM_SIG          cpu_to_le32(0x8129)
  86 #define RTL_EEPROM_SIG_MASK     cpu_to_le32(0xffff)
  87 #define RTL_EEPROM_SIG_ADDR     0x0000
  88
  89 /* write/read MMIO register */
  90 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
  91 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
  92 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
  93 #define RTL_R8(reg)             readb (ioaddr + (reg))
  94 #define RTL_R16(reg)            readw (ioaddr + (reg))
  95 #define RTL_R32(reg)            readl (ioaddr + (reg))
  96
  97 enum mac_version {
  98         RTL_GIGA_MAC_NONE   = 0x00,
  99         RTL_GIGA_MAC_VER_01 = 0x01, // 8169
 100         RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
 101         RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
 102         RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
 103         RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
 104         RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
 105         RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
 106         RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
 107         RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
 108         RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
 109         RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
 110         RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
 111         RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
 112         RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
 113         RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
 114         RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
 115         RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
 116         RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
 117         RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
 118         RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
 119         RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
 120         RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
 121         RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
 122         RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
 123         RTL_GIGA_MAC_VER_25 = 0x19, // 8168D
 124         RTL_GIGA_MAC_VER_26 = 0x1a, // 8168D
 125         RTL_GIGA_MAC_VER_27 = 0x1b, // 8168DP
 126         RTL_GIGA_MAC_VER_28 = 0x1c, // 8168DP
 127         RTL_GIGA_MAC_VER_29 = 0x1d, // 8105E
 128         RTL_GIGA_MAC_VER_30 = 0x1e, // 8105E
 129 };
 130
 131 #define _R(NAME,MAC,MASK) \
 132         { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
 133
 134 static const struct {
 135         const char *name;
 136         u8 mac_version;
 137         u32 RxConfigMask;       /* Clears the bits supported by this chip */
 138 } rtl_chip_info[] = {
 139         _R("RTL8169",           RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
 140         _R("RTL8169s",          RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
 141         _R("RTL8110s",          RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
 142         _R("RTL8169sb/8110sb",  RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
 143         _R("RTL8169sc/8110sc",  RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
 144         _R("RTL8169sc/8110sc",  RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
 145         _R("RTL8102e",          RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
 146         _R("RTL8102e",          RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
 147         _R("RTL8102e",          RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
 148         _R("RTL8101e",          RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
 149         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
 150         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
 151         _R("RTL8101e",          RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
 152         _R("RTL8100e",          RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
 153         _R("RTL8100e",          RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
 154         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
 155         _R("RTL8101e",          RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
 156         _R("RTL8168cp/8111cp",  RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
 157         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
 158         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E
 159         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E
 160         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E
 161         _R("RTL8168cp/8111cp",  RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E
 162         _R("RTL8168cp/8111cp",  RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E
 163         _R("RTL8168d/8111d",    RTL_GIGA_MAC_VER_25, 0xff7e1880), // PCI-E
 164         _R("RTL8168d/8111d",    RTL_GIGA_MAC_VER_26, 0xff7e1880), // PCI-E
 165         _R("RTL8168dp/8111dp",  RTL_GIGA_MAC_VER_27, 0xff7e1880), // PCI-E
 166         _R("RTL8168dp/8111dp",  RTL_GIGA_MAC_VER_28, 0xff7e1880), // PCI-E
 167         _R("RTL8105e",          RTL_GIGA_MAC_VER_29, 0xff7e1880), // PCI-E
 168         _R("RTL8105e",          RTL_GIGA_MAC_VER_30, 0xff7e1880)  // PCI-E
 169 };
 170 #undef _R
 171
 172 enum cfg_version {
 173         RTL_CFG_0 = 0x00,
 174         RTL_CFG_1,
 175         RTL_CFG_2
 176 };
 177
 178 static void rtl_hw_start_8169(struct net_device *);
 179 static void rtl_hw_start_8168(struct net_device *);
 180 static void rtl_hw_start_8101(struct net_device *);
 181
 182 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
 183         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 184         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 185         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 186         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 187         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 188         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 189         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
 190         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 191         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 192                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 193         { 0x0001,                               0x8168,
 194                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 195         {0,},
 196 };
 197
 198 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 199
 200 static int rx_buf_sz = 16383;
 201 static int use_dac;
 202 static struct {
 203         u32 msg_enable;
 204 } debug = { -1 };
 205
 206 enum rtl_registers {
 207         MAC0            = 0,    /* Ethernet hardware address. */
 208         MAC4            = 4,
 209         MAR0            = 8,    /* Multicast filter. */
 210         CounterAddrLow          = 0x10,
 211         CounterAddrHigh         = 0x14,
 212         TxDescStartAddrLow      = 0x20,
 213         TxDescStartAddrHigh     = 0x24,
 214         TxHDescStartAddrLow     = 0x28,
 215         TxHDescStartAddrHigh    = 0x2c,
 216         FLASH           = 0x30,
 217         ERSR            = 0x36,
 218         ChipCmd         = 0x37,
 219         TxPoll          = 0x38,
 220         IntrMask        = 0x3c,
 221         IntrStatus      = 0x3e,
 222         TxConfig        = 0x40,
 223         RxConfig        = 0x44,
 224         RxMissed        = 0x4c,
 225         Cfg9346         = 0x50,
 226         Config0         = 0x51,
 227         Config1         = 0x52,
 228         Config2         = 0x53,
 229         Config3         = 0x54,
 230         Config4         = 0x55,
 231         Config5         = 0x56,
 232         MultiIntr       = 0x5c,
 233         PHYAR           = 0x60,
 234         PHYstatus       = 0x6c,
 235         RxMaxSize       = 0xda,
 236         CPlusCmd        = 0xe0,
 237         IntrMitigate    = 0xe2,
 238         RxDescAddrLow   = 0xe4,
 239         RxDescAddrHigh  = 0xe8,
 240         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 241
 242 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 243
 244         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 245
 246 #define TxPacketMax     (8064 >> 7)
 247
 248         FuncEvent       = 0xf0,
 249         FuncEventMask   = 0xf4,
 250         FuncPresetState = 0xf8,
 251         FuncForceEvent  = 0xfc,
 252 };
 253
 254 enum rtl8110_registers {
 255         TBICSR                  = 0x64,
 256         TBI_ANAR                = 0x68,
 257         TBI_LPAR                = 0x6a,
 258 };
 259
 260 enum rtl8168_8101_registers {
 261         CSIDR                   = 0x64,
 262         CSIAR                   = 0x68,
 263 #define CSIAR_FLAG                      0x80000000
 264 #define CSIAR_WRITE_CMD                 0x80000000
 265 #define CSIAR_BYTE_ENABLE               0x0f
 266 #define CSIAR_BYTE_ENABLE_SHIFT         12
 267 #define CSIAR_ADDR_MASK                 0x0fff
 268         PMCH                    = 0x6f,
 269         EPHYAR                  = 0x80,
 270 #define EPHYAR_FLAG                     0x80000000
 271 #define EPHYAR_WRITE_CMD                0x80000000
 272 #define EPHYAR_REG_MASK                 0x1f
 273 #define EPHYAR_REG_SHIFT                16
 274 #define EPHYAR_DATA_MASK                0xffff
 275         DLLPR                   = 0xd0,
 276 #define PM_SWITCH                       (1 << 6)
 277         DBG_REG                 = 0xd1,
 278 #define FIX_NAK_1                       (1 << 4)
 279 #define FIX_NAK_2                       (1 << 3)
 280         TWSI                    = 0xd2,
 281         MCU                     = 0xd3,
 282 #define EN_NDP                          (1 << 3)
 283 #define EN_OOB_RESET                    (1 << 2)
 284         EFUSEAR                 = 0xdc,
 285 #define EFUSEAR_FLAG                    0x80000000
 286 #define EFUSEAR_WRITE_CMD               0x80000000
 287 #define EFUSEAR_READ_CMD                0x00000000
 288 #define EFUSEAR_REG_MASK                0x03ff
 289 #define EFUSEAR_REG_SHIFT               8
 290 #define EFUSEAR_DATA_MASK               0xff
 291 };
 292
 293 enum rtl8168_registers {
 294         ERIDR                   = 0x70,
 295         ERIAR                   = 0x74,
 296 #define ERIAR_FLAG                      0x80000000
 297 #define ERIAR_WRITE_CMD                 0x80000000
 298 #define ERIAR_READ_CMD                  0x00000000
 299 #define ERIAR_ADDR_BYTE_ALIGN           4
 300 #define ERIAR_EXGMAC                    0
 301 #define ERIAR_MSIX                      1
 302 #define ERIAR_ASF                       2
 303 #define ERIAR_TYPE_SHIFT                16
 304 #define ERIAR_BYTEEN                    0x0f
 305 #define ERIAR_BYTEEN_SHIFT              12
 306         EPHY_RXER_NUM           = 0x7c,
 307         OCPDR                   = 0xb0, /* OCP GPHY access */
 308 #define OCPDR_WRITE_CMD                 0x80000000
 309 #define OCPDR_READ_CMD                  0x00000000
 310 #define OCPDR_REG_MASK                  0x7f
 311 #define OCPDR_GPHY_REG_SHIFT            16
 312 #define OCPDR_DATA_MASK                 0xffff
 313         OCPAR                   = 0xb4,
 314 #define OCPAR_FLAG                      0x80000000
 315 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 316 #define OCPAR_GPHY_READ_CMD             0x0000f060
 317         RDSAR1                  = 0xd0  /* 8168c only. Undocumented on 8168dp */
 318 };
 319
 320 enum rtl_register_content {
 321         /* InterruptStatusBits */
 322         SYSErr          = 0x8000,
 323         PCSTimeout      = 0x4000,
 324         SWInt           = 0x0100,
 325         TxDescUnavail   = 0x0080,
 326         RxFIFOOver      = 0x0040,
 327         LinkChg         = 0x0020,
 328         RxOverflow      = 0x0010,
 329         TxErr           = 0x0008,
 330         TxOK            = 0x0004,
 331         RxErr           = 0x0002,
 332         RxOK            = 0x0001,
 333
 334         /* RxStatusDesc */
 335         RxFOVF  = (1 << 23),
 336         RxRWT   = (1 << 22),
 337         RxRES   = (1 << 21),
 338         RxRUNT  = (1 << 20),
 339         RxCRC   = (1 << 19),
 340
 341         /* ChipCmdBits */
 342         CmdReset        = 0x10,
 343         CmdRxEnb        = 0x08,
 344         CmdTxEnb        = 0x04,
 345         RxBufEmpty      = 0x01,
 346
 347         /* TXPoll register p.5 */
 348         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 349         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 350         FSWInt          = 0x01,         /* Forced software interrupt */
 351
 352         /* Cfg9346Bits */
 353         Cfg9346_Lock    = 0x00,
 354         Cfg9346_Unlock  = 0xc0,
 355
 356         /* rx_mode_bits */
 357         AcceptErr       = 0x20,
 358         AcceptRunt      = 0x10,
 359         AcceptBroadcast = 0x08,
 360         AcceptMulticast = 0x04,
 361         AcceptMyPhys    = 0x02,
 362         AcceptAllPhys   = 0x01,
 363
 364         /* RxConfigBits */
 365         RxCfgFIFOShift  = 13,
 366         RxCfgDMAShift   =  8,
 367
 368         /* TxConfigBits */
 369         TxInterFrameGapShift = 24,
 370         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 371
 372         /* Config1 register p.24 */
 373         LEDS1           = (1 << 7),
 374         LEDS0           = (1 << 6),
 375         MSIEnable       = (1 << 5),     /* Enable Message Signaled Interrupt */
 376         Speed_down      = (1 << 4),
 377         MEMMAP          = (1 << 3),
 378         IOMAP           = (1 << 2),
 379         VPD             = (1 << 1),
 380         PMEnable        = (1 << 0),     /* Power Management Enable */
 381
 382         /* Config2 register p. 25 */
 383         PCI_Clock_66MHz = 0x01,
 384         PCI_Clock_33MHz = 0x00,
 385
 386         /* Config3 register p.25 */
 387         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 388         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 389         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 390
 391         /* Config5 register p.27 */
 392         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 393         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 394         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 395         LanWake         = (1 << 1),     /* LanWake enable/disable */
 396         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 397
 398         /* TBICSR p.28 */
 399         TBIReset        = 0x80000000,
 400         TBILoopback     = 0x40000000,
 401         TBINwEnable     = 0x20000000,
 402         TBINwRestart    = 0x10000000,
 403         TBILinkOk       = 0x02000000,
 404         TBINwComplete   = 0x01000000,
 405
 406         /* CPlusCmd p.31 */
 407         EnableBist      = (1 << 15),    // 8168 8101
 408         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 409         Normal_mode     = (1 << 13),    // unused
 410         Force_half_dup  = (1 << 12),    // 8168 8101
 411         Force_rxflow_en = (1 << 11),    // 8168 8101
 412         Force_txflow_en = (1 << 10),    // 8168 8101
 413         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 414         ASF             = (1 << 8),     // 8168 8101
 415         PktCntrDisable  = (1 << 7),     // 8168 8101
 416         Mac_dbgo_sel    = 0x001c,       // 8168
 417         RxVlan          = (1 << 6),
 418         RxChkSum        = (1 << 5),
 419         PCIDAC          = (1 << 4),
 420         PCIMulRW        = (1 << 3),
 421         INTT_0          = 0x0000,       // 8168
 422         INTT_1          = 0x0001,       // 8168
 423         INTT_2          = 0x0002,       // 8168
 424         INTT_3          = 0x0003,       // 8168
 425
 426         /* rtl8169_PHYstatus */
 427         TBI_Enable      = 0x80,
 428         TxFlowCtrl      = 0x40,
 429         RxFlowCtrl      = 0x20,
 430         _1000bpsF       = 0x10,
 431         _100bps         = 0x08,
 432         _10bps          = 0x04,
 433         LinkStatus      = 0x02,
 434         FullDup         = 0x01,
 435
 436         /* _TBICSRBit */
 437         TBILinkOK       = 0x02000000,
 438
 439         /* DumpCounterCommand */
 440         CounterDump     = 0x8,
 441 };
 442
 443 enum desc_status_bit {
 444         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 445         RingEnd         = (1 << 30), /* End of descriptor ring */
 446         FirstFrag       = (1 << 29), /* First segment of a packet */
 447         LastFrag        = (1 << 28), /* Final segment of a packet */
 448
 449         /* Tx private */
 450         LargeSend       = (1 << 27), /* TCP Large Send Offload (TSO) */
 451         MSSShift        = 16,        /* MSS value position */
 452         MSSMask         = 0xfff,     /* MSS value + LargeSend bit: 12 bits */
 453         IPCS            = (1 << 18), /* Calculate IP checksum */
 454         UDPCS           = (1 << 17), /* Calculate UDP/IP checksum */
 455         TCPCS           = (1 << 16), /* Calculate TCP/IP checksum */
 456         TxVlanTag       = (1 << 17), /* Add VLAN tag */
 457
 458         /* Rx private */
 459         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 460         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
 461
 462 #define RxProtoUDP      (PID1)
 463 #define RxProtoTCP      (PID0)
 464 #define RxProtoIP       (PID1 | PID0)
 465 #define RxProtoMask     RxProtoIP
 466
 467         IPFail          = (1 << 16), /* IP checksum failed */
 468         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 469         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 470         RxVlanTag       = (1 << 16), /* VLAN tag available */
 471 };
 472
 473 #define RsvdMask        0x3fffc000
 474
 475 struct TxDesc {
 476         __le32 opts1;
 477         __le32 opts2;
 478         __le64 addr;
 479 };
 480
 481 struct RxDesc {
 482         __le32 opts1;
 483         __le32 opts2;
 484         __le64 addr;
 485 };
 486
 487 struct ring_info {
 488         struct sk_buff  *skb;
 489         u32             len;
 490         u8              __pad[sizeof(void *) - sizeof(u32)];
 491 };
 492
 493 enum features {
 494         RTL_FEATURE_WOL         = (1 << 0),
 495         RTL_FEATURE_MSI         = (1 << 1),
 496         RTL_FEATURE_GMII        = (1 << 2),
 497 };
 498
 499 struct rtl8169_counters {
 500         __le64  tx_packets;
 501         __le64  rx_packets;
 502         __le64  tx_errors;
 503         __le32  rx_errors;
 504         __le16  rx_missed;
 505         __le16  align_errors;
 506         __le32  tx_one_collision;
 507         __le32  tx_multi_collision;
 508         __le64  rx_unicast;
 509         __le64  rx_broadcast;
 510         __le32  rx_multicast;
 511         __le16  tx_aborted;
 512         __le16  tx_underun;
 513 };
 514
 515 struct rtl8169_private {
 516         void __iomem *mmio_addr;        /* memory map physical address */
 517         struct pci_dev *pci_dev;        /* Index of PCI device */
 518         struct net_device *dev;
 519         struct napi_struct napi;
 520         spinlock_t lock;                /* spin lock flag */
 521         u32 msg_enable;
 522         int chipset;
 523         int mac_version;
 524         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 525         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 526         u32 dirty_rx;
 527         u32 dirty_tx;
 528         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 529         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 530         dma_addr_t TxPhyAddr;
 531         dma_addr_t RxPhyAddr;
 532         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 533         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 534         struct timer_list timer;
 535         u16 cp_cmd;
 536         u16 intr_event;
 537         u16 napi_event;
 538         u16 intr_mask;
 539         int phy_1000_ctrl_reg;
 540 #ifdef CONFIG_R8169_VLAN
 541         struct vlan_group *vlgrp;
 542 #endif
 543
 544         struct mdio_ops {
 545                 void (*write)(void __iomem *, int, int);
 546                 int (*read)(void __iomem *, int);
 547         } mdio_ops;
 548
 549         struct pll_power_ops {
 550                 void (*down)(struct rtl8169_private *);
 551                 void (*up)(struct rtl8169_private *);
 552         } pll_power_ops;
 553
 554         int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
 555         int (*get_settings)(struct net_device *, struct ethtool_cmd *);
 556         void (*phy_reset_enable)(struct rtl8169_private *tp);
 557         void (*hw_start)(struct net_device *);
 558         unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
 559         unsigned int (*link_ok)(void __iomem *);
 560         int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
 561         int pcie_cap;
 562         struct delayed_work task;
 563         unsigned features;
 564
 565         struct mii_if_info mii;
 566         struct rtl8169_counters counters;
 567         u32 saved_wolopts;
 568
 569         const struct firmware *fw;
 570 };
 571
 572 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 573 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 574 module_param(use_dac, int, 0);
 575 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 576 module_param_named(debug, debug.msg_enable, int, 0);
 577 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 578 MODULE_LICENSE("GPL");
 579 MODULE_VERSION(RTL8169_VERSION);
 580 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 581 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 582 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 583
 584 static int rtl8169_open(struct net_device *dev);
 585 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
 586                                       struct net_device *dev);
 587 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
 588 static int rtl8169_init_ring(struct net_device *dev);
 589 static void rtl_hw_start(struct net_device *dev);
 590 static int rtl8169_close(struct net_device *dev);
 591 static void rtl_set_rx_mode(struct net_device *dev);
 592 static void rtl8169_tx_timeout(struct net_device *dev);
 593 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
 594 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
 595                                 void __iomem *, u32 budget);
 596 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
 597 static void rtl8169_down(struct net_device *dev);
 598 static void rtl8169_rx_clear(struct rtl8169_private *tp);
 599 static int rtl8169_poll(struct napi_struct *napi, int budget);
 600
 601 static const unsigned int rtl8169_rx_config =
 602         (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
 603
 604 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
 605 {
 606         void __iomem *ioaddr = tp->mmio_addr;
 607         int i;
 608
 609         RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 610         for (i = 0; i < 20; i++) {
 611                 udelay(100);
 612                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
 613                         break;
 614         }
 615         return RTL_R32(OCPDR);
 616 }
 617
 618 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
 619 {
 620         void __iomem *ioaddr = tp->mmio_addr;
 621         int i;
 622
 623         RTL_W32(OCPDR, data);
 624         RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 625         for (i = 0; i < 20; i++) {
 626                 udelay(100);
 627                 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
 628                         break;
 629         }
 630 }
 631
 632 static void rtl8168_oob_notify(void __iomem *ioaddr, u8 cmd)
 633 {
 634         int i;
 635
 636         RTL_W8(ERIDR, cmd);
 637         RTL_W32(ERIAR, 0x800010e8);
 638         msleep(2);
 639         for (i = 0; i < 5; i++) {
 640                 udelay(100);
 641                 if (!(RTL_R32(ERIDR) & ERIAR_FLAG))
 642                         break;
 643         }
 644
 645         ocp_write(ioaddr, 0x1, 0x30, 0x00000001);
 646 }
 647
 648 #define OOB_CMD_RESET           0x00
 649 #define OOB_CMD_DRIVER_START    0x05
 650 #define OOB_CMD_DRIVER_STOP     0x06
 651
 652 static void rtl8168_driver_start(struct rtl8169_private *tp)
 653 {
 654         int i;
 655
 656         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
 657
 658         for (i = 0; i < 10; i++) {
 659                 msleep(10);
 660                 if (ocp_read(tp, 0x0f, 0x0010) & 0x00000800)
 661                         break;
 662         }
 663 }
 664
 665 static void rtl8168_driver_stop(struct rtl8169_private *tp)
 666 {
 667         int i;
 668
 669         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
 670
 671         for (i = 0; i < 10; i++) {
 672                 msleep(10);
 673                 if ((ocp_read(tp, 0x0f, 0x0010) & 0x00000800) == 0)
 674                         break;
 675         }
 676 }
 677
 678
 679 static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 680 {
 681         int i;
 682
 683         RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
 684
 685         for (i = 20; i > 0; i--) {
 686                 /*
 687                  * Check if the RTL8169 has completed writing to the specified
 688                  * MII register.
 689                  */
 690                 if (!(RTL_R32(PHYAR) & 0x80000000))
 691                         break;
 692                 udelay(25);
 693         }
 694         /*
 695          * According to hardware specs a 20us delay is required after write
 696          * complete indication, but before sending next command.
 697          */
 698         udelay(20);
 699 }
 700
 701 static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
 702 {
 703         int i, value = -1;
 704
 705         RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
 706
 707         for (i = 20; i > 0; i--) {
 708                 /*
 709                  * Check if the RTL8169 has completed retrieving data from
 710                  * the specified MII register.
 711                  */
 712                 if (RTL_R32(PHYAR) & 0x80000000) {
 713                         value = RTL_R32(PHYAR) & 0xffff;
 714                         break;
 715                 }
 716                 udelay(25);
 717         }
 718         /*
 719          * According to hardware specs a 20us delay is required after read
 720          * complete indication, but before sending next command.
 721          */
 722         udelay(20);
 723
 724         return value;
 725 }
 726
 727 static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
 728 {
 729         int i;
 730
 731         RTL_W32(OCPDR, data |
 732                 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
 733         RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
 734         RTL_W32(EPHY_RXER_NUM, 0);
 735
 736         for (i = 0; i < 100; i++) {
 737                 mdelay(1);
 738                 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
 739                         break;
 740         }
 741 }
 742
 743 static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 744 {
 745         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
 746                 (value & OCPDR_DATA_MASK));
 747 }
 748
 749 static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
 750 {
 751         int i;
 752
 753         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
 754
 755         mdelay(1);
 756         RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
 757         RTL_W32(EPHY_RXER_NUM, 0);
 758
 759         for (i = 0; i < 100; i++) {
 760                 mdelay(1);
 761                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
 762                         break;
 763         }
 764
 765         return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
 766 }
 767
 768 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
 769
 770 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
 771 {
 772         RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
 773 }
 774
 775 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
 776 {
 777         RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
 778 }
 779
 780 static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 781 {
 782         r8168dp_2_mdio_start(ioaddr);
 783
 784         r8169_mdio_write(ioaddr, reg_addr, value);
 785
 786         r8168dp_2_mdio_stop(ioaddr);
 787 }
 788
 789 static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
 790 {
 791         int value;
 792
 793         r8168dp_2_mdio_start(ioaddr);
 794
 795         value = r8169_mdio_read(ioaddr, reg_addr);
 796
 797         r8168dp_2_mdio_stop(ioaddr);
 798
 799         return value;
 800 }
 801
 802 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
 803 {
 804         tp->mdio_ops.write(tp->mmio_addr, location, val);
 805 }
 806
 807 static int rtl_readphy(struct rtl8169_private *tp, int location)
 808 {
 809         return tp->mdio_ops.read(tp->mmio_addr, location);
 810 }
 811
 812 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
 813 {
 814         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
 815 }
 816
 817 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
 818 {
 819         int val;
 820
 821         val = rtl_readphy(tp, reg_addr);
 822         rtl_writephy(tp, reg_addr, (val | p) & ~m);
 823 }
 824
 825 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
 826                            int val)
 827 {
 828         struct rtl8169_private *tp = netdev_priv(dev);
 829
 830         rtl_writephy(tp, location, val);
 831 }
 832
 833 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
 834 {
 835         struct rtl8169_private *tp = netdev_priv(dev);
 836
 837         return rtl_readphy(tp, location);
 838 }
 839
 840 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
 841 {
 842         unsigned int i;
 843
 844         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
 845                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
 846
 847         for (i = 0; i < 100; i++) {
 848                 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
 849                         break;
 850                 udelay(10);
 851         }
 852 }
 853
 854 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
 855 {
 856         u16 value = 0xffff;
 857         unsigned int i;
 858
 859         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
 860
 861         for (i = 0; i < 100; i++) {
 862                 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
 863                         value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
 864                         break;
 865                 }
 866                 udelay(10);
 867         }
 868
 869         return value;
 870 }
 871
 872 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
 873 {
 874         unsigned int i;
 875
 876         RTL_W32(CSIDR, value);
 877         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
 878                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
 879
 880         for (i = 0; i < 100; i++) {
 881                 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
 882                         break;
 883                 udelay(10);
 884         }
 885 }
 886
 887 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
 888 {
 889         u32 value = ~0x00;
 890         unsigned int i;
 891
 892         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
 893                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
 894
 895         for (i = 0; i < 100; i++) {
 896                 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
 897                         value = RTL_R32(CSIDR);
 898                         break;
 899                 }
 900                 udelay(10);
 901         }
 902
 903         return value;
 904 }
 905
 906 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
 907 {
 908         u8 value = 0xff;
 909         unsigned int i;
 910
 911         RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
 912
 913         for (i = 0; i < 300; i++) {
 914                 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
 915                         value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
 916                         break;
 917                 }
 918                 udelay(100);
 919         }
 920
 921         return value;
 922 }
 923
 924 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
 925 {
 926         RTL_W16(IntrMask, 0x0000);
 927
 928         RTL_W16(IntrStatus, 0xffff);
 929 }
 930
 931 static void rtl8169_asic_down(void __iomem *ioaddr)
 932 {
 933         RTL_W8(ChipCmd, 0x00);
 934         rtl8169_irq_mask_and_ack(ioaddr);
 935         RTL_R16(CPlusCmd);
 936 }
 937
 938 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
 939 {
 940         void __iomem *ioaddr = tp->mmio_addr;
 941
 942         return RTL_R32(TBICSR) & TBIReset;
 943 }
 944
 945 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
 946 {
 947         return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
 948 }
 949
 950 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
 951 {
 952         return RTL_R32(TBICSR) & TBILinkOk;
 953 }
 954
 955 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
 956 {
 957         return RTL_R8(PHYstatus) & LinkStatus;
 958 }
 959
 960 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
 961 {
 962         void __iomem *ioaddr = tp->mmio_addr;
 963
 964         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
 965 }
 966
 967 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
 968 {
 969         unsigned int val;
 970
 971         val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
 972         rtl_writephy(tp, MII_BMCR, val & 0xffff);
 973 }
 974
 975 static void __rtl8169_check_link_status(struct net_device *dev,
 976                                       struct rtl8169_private *tp,
 977                                       void __iomem *ioaddr,
 978                                       bool pm)
 979 {
 980         unsigned long flags;
 981
 982         spin_lock_irqsave(&tp->lock, flags);
 983         if (tp->link_ok(ioaddr)) {
 984                 /* This is to cancel a scheduled suspend if there's one. */
 985                 if (pm)
 986                         pm_request_resume(&tp->pci_dev->dev);
 987                 netif_carrier_on(dev);
 988                 if (net_ratelimit())
 989                         netif_info(tp, ifup, dev, "link up\n");
 990         } else {
 991                 netif_carrier_off(dev);
 992                 netif_info(tp, ifdown, dev, "link down\n");
 993                 if (pm)
 994                         pm_schedule_suspend(&tp->pci_dev->dev, 100);
 995         }
 996         spin_unlock_irqrestore(&tp->lock, flags);
 997 }
 998
 999 static void rtl8169_check_link_status(struct net_device *dev,
1000                                       struct rtl8169_private *tp,
1001                                       void __iomem *ioaddr)
1002 {
1003         __rtl8169_check_link_status(dev, tp, ioaddr, false);
1004 }
1005
1006 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1007
1008 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1009 {
1010         void __iomem *ioaddr = tp->mmio_addr;
1011         u8 options;
1012         u32 wolopts = 0;
1013
1014         options = RTL_R8(Config1);
1015         if (!(options & PMEnable))
1016                 return 0;
1017
1018         options = RTL_R8(Config3);
1019         if (options & LinkUp)
1020                 wolopts |= WAKE_PHY;
1021         if (options & MagicPacket)
1022                 wolopts |= WAKE_MAGIC;
1023
1024         options = RTL_R8(Config5);
1025         if (options & UWF)
1026                 wolopts |= WAKE_UCAST;
1027         if (options & BWF)
1028                 wolopts |= WAKE_BCAST;
1029         if (options & MWF)
1030                 wolopts |= WAKE_MCAST;
1031
1032         return wolopts;
1033 }
1034
1035 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1036 {
1037         struct rtl8169_private *tp = netdev_priv(dev);
1038
1039         spin_lock_irq(&tp->lock);
1040
1041         wol->supported = WAKE_ANY;
1042         wol->wolopts = __rtl8169_get_wol(tp);
1043
1044         spin_unlock_irq(&tp->lock);
1045 }
1046
1047 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1048 {
1049         void __iomem *ioaddr = tp->mmio_addr;
1050         unsigned int i;
1051         static const struct {
1052                 u32 opt;
1053                 u16 reg;
1054                 u8  mask;
1055         } cfg[] = {
1056                 { WAKE_ANY,   Config1, PMEnable },
1057                 { WAKE_PHY,   Config3, LinkUp },
1058                 { WAKE_MAGIC, Config3, MagicPacket },
1059                 { WAKE_UCAST, Config5, UWF },
1060                 { WAKE_BCAST, Config5, BWF },
1061                 { WAKE_MCAST, Config5, MWF },
1062                 { WAKE_ANY,   Config5, LanWake }
1063         };
1064
1065         RTL_W8(Cfg9346, Cfg9346_Unlock);
1066
1067         for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1068                 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1069                 if (wolopts & cfg[i].opt)
1070                         options |= cfg[i].mask;
1071                 RTL_W8(cfg[i].reg, options);
1072         }
1073
1074         RTL_W8(Cfg9346, Cfg9346_Lock);
1075 }
1076
1077 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1078 {
1079         struct rtl8169_private *tp = netdev_priv(dev);
1080
1081         spin_lock_irq(&tp->lock);
1082
1083         if (wol->wolopts)
1084                 tp->features |= RTL_FEATURE_WOL;
1085         else
1086                 tp->features &= ~RTL_FEATURE_WOL;
1087         __rtl8169_set_wol(tp, wol->wolopts);
1088         spin_unlock_irq(&tp->lock);
1089
1090         device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1091
1092         return 0;
1093 }
1094
1095 static void rtl8169_get_drvinfo(struct net_device *dev,
1096                                 struct ethtool_drvinfo *info)
1097 {
1098         struct rtl8169_private *tp = netdev_priv(dev);
1099
1100         strcpy(info->driver, MODULENAME);
1101         strcpy(info->version, RTL8169_VERSION);
1102         strcpy(info->bus_info, pci_name(tp->pci_dev));
1103 }
1104
1105 static int rtl8169_get_regs_len(struct net_device *dev)
1106 {
1107         return R8169_REGS_SIZE;
1108 }
1109
1110 static int rtl8169_set_speed_tbi(struct net_device *dev,
1111                                  u8 autoneg, u16 speed, u8 duplex)
1112 {
1113         struct rtl8169_private *tp = netdev_priv(dev);
1114         void __iomem *ioaddr = tp->mmio_addr;
1115         int ret = 0;
1116         u32 reg;
1117
1118         reg = RTL_R32(TBICSR);
1119         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1120             (duplex == DUPLEX_FULL)) {
1121                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1122         } else if (autoneg == AUTONEG_ENABLE)
1123                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1124         else {
1125                 netif_warn(tp, link, dev,
1126                            "incorrect speed setting refused in TBI mode\n");
1127                 ret = -EOPNOTSUPP;
1128         }
1129
1130         return ret;
1131 }
1132
1133 static int rtl8169_set_speed_xmii(struct net_device *dev,
1134                                   u8 autoneg, u16 speed, u8 duplex)
1135 {
1136         struct rtl8169_private *tp = netdev_priv(dev);
1137         int giga_ctrl, bmcr;
1138
1139         rtl_writephy(tp, 0x1f, 0x0000);
1140
1141         if (autoneg == AUTONEG_ENABLE) {
1142                 int auto_nego;
1143
1144                 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1145                 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
1146                               ADVERTISE_100HALF | ADVERTISE_100FULL);
1147                 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1148
1149                 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1150                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1151
1152                 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1153                 if ((tp->mac_version != RTL_GIGA_MAC_VER_07) &&
1154                     (tp->mac_version != RTL_GIGA_MAC_VER_08) &&
1155                     (tp->mac_version != RTL_GIGA_MAC_VER_09) &&
1156                     (tp->mac_version != RTL_GIGA_MAC_VER_10) &&
1157                     (tp->mac_version != RTL_GIGA_MAC_VER_13) &&
1158                     (tp->mac_version != RTL_GIGA_MAC_VER_14) &&
1159                     (tp->mac_version != RTL_GIGA_MAC_VER_15) &&
1160                     (tp->mac_version != RTL_GIGA_MAC_VER_16) &&
1161                     (tp->mac_version != RTL_GIGA_MAC_VER_29) &&
1162                     (tp->mac_version != RTL_GIGA_MAC_VER_30)) {
1163                         giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
1164                 } else {
1165                         netif_info(tp, link, dev,
1166                                    "PHY does not support 1000Mbps\n");
1167                 }
1168
1169                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1170
1171                 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1172                 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1173         } else {
1174                 giga_ctrl = 0;
1175
1176                 if (speed == SPEED_10)
1177                         bmcr = 0;
1178                 else if (speed == SPEED_100)
1179                         bmcr = BMCR_SPEED100;
1180                 else
1181                         return -EINVAL;
1182
1183                 if (duplex == DUPLEX_FULL)
1184                         bmcr |= BMCR_FULLDPLX;
1185         }
1186
1187         tp->phy_1000_ctrl_reg = giga_ctrl;
1188
1189         rtl_writephy(tp, MII_BMCR, bmcr);
1190
1191         if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1192             (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
1193                 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1194                         rtl_writephy(tp, 0x17, 0x2138);
1195                         rtl_writephy(tp, 0x0e, 0x0260);
1196                 } else {
1197                         rtl_writephy(tp, 0x17, 0x2108);
1198                         rtl_writephy(tp, 0x0e, 0x0000);
1199                 }
1200         }
1201
1202         return 0;
1203 }
1204
1205 static int rtl8169_set_speed(struct net_device *dev,
1206                              u8 autoneg, u16 speed, u8 duplex)
1207 {
1208         struct rtl8169_private *tp = netdev_priv(dev);
1209         int ret;
1210
1211         ret = tp->set_speed(dev, autoneg, speed, duplex);
1212
1213         if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1214                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1215
1216         return ret;
1217 }
1218
1219 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1220 {
1221         struct rtl8169_private *tp = netdev_priv(dev);
1222         unsigned long flags;
1223         int ret;
1224
1225         spin_lock_irqsave(&tp->lock, flags);
1226         ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
1227         spin_unlock_irqrestore(&tp->lock, flags);
1228
1229         return ret;
1230 }
1231
1232 static u32 rtl8169_get_rx_csum(struct net_device *dev)
1233 {
1234         struct rtl8169_private *tp = netdev_priv(dev);
1235
1236         return tp->cp_cmd & RxChkSum;
1237 }
1238
1239 static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
1240 {
1241         struct rtl8169_private *tp = netdev_priv(dev);
1242         void __iomem *ioaddr = tp->mmio_addr;
1243         unsigned long flags;
1244
1245         spin_lock_irqsave(&tp->lock, flags);
1246
1247         if (data)
1248                 tp->cp_cmd |= RxChkSum;
1249         else
1250                 tp->cp_cmd &= ~RxChkSum;
1251
1252         RTL_W16(CPlusCmd, tp->cp_cmd);
1253         RTL_R16(CPlusCmd);
1254
1255         spin_unlock_irqrestore(&tp->lock, flags);
1256
1257         return 0;
1258 }
1259
1260 #ifdef CONFIG_R8169_VLAN
1261
1262 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1263                                       struct sk_buff *skb)
1264 {
1265         return (vlan_tx_tag_present(skb)) ?
1266                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1267 }
1268
1269 static void rtl8169_vlan_rx_register(struct net_device *dev,
1270                                      struct vlan_group *grp)
1271 {
1272         struct rtl8169_private *tp = netdev_priv(dev);
1273         void __iomem *ioaddr = tp->mmio_addr;
1274         unsigned long flags;
1275
1276         spin_lock_irqsave(&tp->lock, flags);
1277         tp->vlgrp = grp;
1278         /*
1279          * Do not disable RxVlan on 8110SCd.
1280          */
1281         if (tp->vlgrp || (tp->mac_version == RTL_GIGA_MAC_VER_05))
1282                 tp->cp_cmd |= RxVlan;
1283         else
1284                 tp->cp_cmd &= ~RxVlan;
1285         RTL_W16(CPlusCmd, tp->cp_cmd);
1286         RTL_R16(CPlusCmd);
1287         spin_unlock_irqrestore(&tp->lock, flags);
1288 }
1289
1290 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1291                                struct sk_buff *skb, int polling)
1292 {
1293         u32 opts2 = le32_to_cpu(desc->opts2);
1294         struct vlan_group *vlgrp = tp->vlgrp;
1295         int ret;
1296
1297         if (vlgrp && (opts2 & RxVlanTag)) {
1298                 u16 vtag = swab16(opts2 & 0xffff);
1299
1300                 if (likely(polling))
1301                         vlan_gro_receive(&tp->napi, vlgrp, vtag, skb);
1302                 else
1303                         __vlan_hwaccel_rx(skb, vlgrp, vtag, polling);
1304                 ret = 0;
1305         } else
1306                 ret = -1;
1307         desc->opts2 = 0;
1308         return ret;
1309 }
1310
1311 #else /* !CONFIG_R8169_VLAN */
1312
1313 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1314                                       struct sk_buff *skb)
1315 {
1316         return 0;
1317 }
1318
1319 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1320                                struct sk_buff *skb, int polling)
1321 {
1322         return -1;
1323 }
1324
1325 #endif
1326
1327 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1328 {
1329         struct rtl8169_private *tp = netdev_priv(dev);
1330         void __iomem *ioaddr = tp->mmio_addr;
1331         u32 status;
1332
1333         cmd->supported =
1334                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1335         cmd->port = PORT_FIBRE;
1336         cmd->transceiver = XCVR_INTERNAL;
1337
1338         status = RTL_R32(TBICSR);
1339         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
1340         cmd->autoneg = !!(status & TBINwEnable);
1341
1342         cmd->speed = SPEED_1000;
1343         cmd->duplex = DUPLEX_FULL; /* Always set */
1344
1345         return 0;
1346 }
1347
1348 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1349 {
1350         struct rtl8169_private *tp = netdev_priv(dev);
1351
1352         return mii_ethtool_gset(&tp->mii, cmd);
1353 }
1354
1355 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1356 {
1357         struct rtl8169_private *tp = netdev_priv(dev);
1358         unsigned long flags;
1359         int rc;
1360
1361         spin_lock_irqsave(&tp->lock, flags);
1362
1363         rc = tp->get_settings(dev, cmd);
1364
1365         spin_unlock_irqrestore(&tp->lock, flags);
1366         return rc;
1367 }
1368
1369 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1370                              void *p)
1371 {
1372         struct rtl8169_private *tp = netdev_priv(dev);
1373         unsigned long flags;
1374
1375         if (regs->len > R8169_REGS_SIZE)
1376                 regs->len = R8169_REGS_SIZE;
1377
1378         spin_lock_irqsave(&tp->lock, flags);
1379         memcpy_fromio(p, tp->mmio_addr, regs->len);
1380         spin_unlock_irqrestore(&tp->lock, flags);
1381 }
1382
1383 static u32 rtl8169_get_msglevel(struct net_device *dev)
1384 {
1385         struct rtl8169_private *tp = netdev_priv(dev);
1386
1387         return tp->msg_enable;
1388 }
1389
1390 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1391 {
1392         struct rtl8169_private *tp = netdev_priv(dev);
1393
1394         tp->msg_enable = value;
1395 }
1396
1397 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1398         "tx_packets",
1399         "rx_packets",
1400         "tx_errors",
1401         "rx_errors",
1402         "rx_missed",
1403         "align_errors",
1404         "tx_single_collisions",
1405         "tx_multi_collisions",
1406         "unicast",
1407         "broadcast",
1408         "multicast",
1409         "tx_aborted",
1410         "tx_underrun",
1411 };
1412
1413 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1414 {
1415         switch (sset) {
1416         case ETH_SS_STATS:
1417                 return ARRAY_SIZE(rtl8169_gstrings);
1418         default:
1419                 return -EOPNOTSUPP;
1420         }
1421 }
1422
1423 static void rtl8169_update_counters(struct net_device *dev)
1424 {
1425         struct rtl8169_private *tp = netdev_priv(dev);
1426         void __iomem *ioaddr = tp->mmio_addr;
1427         struct rtl8169_counters *counters;
1428         dma_addr_t paddr;
1429         u32 cmd;
1430         int wait = 1000;
1431         struct device *d = &tp->pci_dev->dev;
1432
1433         /*
1434          * Some chips are unable to dump tally counters when the receiver
1435          * is disabled.
1436          */
1437         if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1438                 return;
1439
1440         counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1441         if (!counters)
1442                 return;
1443
1444         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1445         cmd = (u64)paddr & DMA_BIT_MASK(32);
1446         RTL_W32(CounterAddrLow, cmd);
1447         RTL_W32(CounterAddrLow, cmd | CounterDump);
1448
1449         while (wait--) {
1450                 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1451                         /* copy updated counters */
1452                         memcpy(&tp->counters, counters, sizeof(*counters));
1453                         break;
1454                 }
1455                 udelay(10);
1456         }
1457
1458         RTL_W32(CounterAddrLow, 0);
1459         RTL_W32(CounterAddrHigh, 0);
1460
1461         dma_free_coherent(d, sizeof(*counters), counters, paddr);
1462 }
1463
1464 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1465                                       struct ethtool_stats *stats, u64 *data)
1466 {
1467         struct rtl8169_private *tp = netdev_priv(dev);
1468
1469         ASSERT_RTNL();
1470
1471         rtl8169_update_counters(dev);
1472
1473         data[0] = le64_to_cpu(tp->counters.tx_packets);
1474         data[1] = le64_to_cpu(tp->counters.rx_packets);
1475         data[2] = le64_to_cpu(tp->counters.tx_errors);
1476         data[3] = le32_to_cpu(tp->counters.rx_errors);
1477         data[4] = le16_to_cpu(tp->counters.rx_missed);
1478         data[5] = le16_to_cpu(tp->counters.align_errors);
1479         data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1480         data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1481         data[8] = le64_to_cpu(tp->counters.rx_unicast);
1482         data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1483         data[10] = le32_to_cpu(tp->counters.rx_multicast);
1484         data[11] = le16_to_cpu(tp->counters.tx_aborted);
1485         data[12] = le16_to_cpu(tp->counters.tx_underun);
1486 }
1487
1488 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1489 {
1490         switch(stringset) {
1491         case ETH_SS_STATS:
1492                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1493                 break;
1494         }
1495 }
1496
1497 static const struct ethtool_ops rtl8169_ethtool_ops = {
1498         .get_drvinfo            = rtl8169_get_drvinfo,
1499         .get_regs_len           = rtl8169_get_regs_len,
1500         .get_link               = ethtool_op_get_link,
1501         .get_settings           = rtl8169_get_settings,
1502         .set_settings           = rtl8169_set_settings,
1503         .get_msglevel           = rtl8169_get_msglevel,
1504         .set_msglevel           = rtl8169_set_msglevel,
1505         .get_rx_csum            = rtl8169_get_rx_csum,
1506         .set_rx_csum            = rtl8169_set_rx_csum,
1507         .set_tx_csum            = ethtool_op_set_tx_csum,
1508         .set_sg                 = ethtool_op_set_sg,
1509         .set_tso                = ethtool_op_set_tso,
1510         .get_regs               = rtl8169_get_regs,
1511         .get_wol                = rtl8169_get_wol,
1512         .set_wol                = rtl8169_set_wol,
1513         .get_strings            = rtl8169_get_strings,
1514         .get_sset_count         = rtl8169_get_sset_count,
1515         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1516 };
1517
1518 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1519                                     void __iomem *ioaddr)
1520 {
1521         /*
1522          * The driver currently handles the 8168Bf and the 8168Be identically
1523          * but they can be identified more specifically through the test below
1524          * if needed:
1525          *
1526          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1527          *
1528          * Same thing for the 8101Eb and the 8101Ec:
1529          *
1530          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1531          */
1532         static const struct {
1533                 u32 mask;
1534                 u32 val;
1535                 int mac_version;
1536         } mac_info[] = {
1537                 /* 8168D family. */
1538                 { 0x7cf00000, 0x28300000,       RTL_GIGA_MAC_VER_26 },
1539                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
1540                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
1541
1542                 /* 8168DP family. */
1543                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
1544                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
1545
1546                 /* 8168C family. */
1547                 { 0x7cf00000, 0x3cb00000,       RTL_GIGA_MAC_VER_24 },
1548                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
1549                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
1550                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
1551                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
1552                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
1553                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
1554                 { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
1555                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
1556
1557                 /* 8168B family. */
1558                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
1559                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
1560                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
1561                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
1562
1563                 /* 8101 family. */
1564                 { 0x7cf00000, 0x40a00000,       RTL_GIGA_MAC_VER_30 },
1565                 { 0x7cf00000, 0x40900000,       RTL_GIGA_MAC_VER_29 },
1566                 { 0x7c800000, 0x40800000,       RTL_GIGA_MAC_VER_30 },
1567                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
1568                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
1569                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
1570                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
1571                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
1572                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
1573                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
1574                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
1575                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
1576                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
1577                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
1578                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
1579                 /* FIXME: where did these entries come from ? -- FR */
1580                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
1581                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
1582
1583                 /* 8110 family. */
1584                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
1585                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
1586                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
1587                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
1588                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
1589                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
1590
1591                 /* Catch-all */
1592                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
1593         }, *p = mac_info;
1594         u32 reg;
1595
1596         reg = RTL_R32(TxConfig);
1597         while ((reg & p->mask) != p->val)
1598                 p++;
1599         tp->mac_version = p->mac_version;
1600 }
1601
1602 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1603 {
1604         dprintk("mac_version = 0x%02x\n", tp->mac_version);
1605 }
1606
1607 struct phy_reg {
1608         u16 reg;
1609         u16 val;
1610 };
1611
1612 static void rtl_writephy_batch(struct rtl8169_private *tp,
1613                                const struct phy_reg *regs, int len)
1614 {
1615         while (len-- > 0) {
1616                 rtl_writephy(tp, regs->reg, regs->val);
1617                 regs++;
1618         }
1619 }
1620
1621 #define PHY_READ                0x00000000
1622 #define PHY_DATA_OR             0x10000000
1623 #define PHY_DATA_AND            0x20000000
1624 #define PHY_BJMPN               0x30000000
1625 #define PHY_READ_EFUSE          0x40000000
1626 #define PHY_READ_MAC_BYTE       0x50000000
1627 #define PHY_WRITE_MAC_BYTE      0x60000000
1628 #define PHY_CLEAR_READCOUNT     0x70000000
1629 #define PHY_WRITE               0x80000000
1630 #define PHY_READCOUNT_EQ_SKIP   0x90000000
1631 #define PHY_COMP_EQ_SKIPN       0xa0000000
1632 #define PHY_COMP_NEQ_SKIPN      0xb0000000
1633 #define PHY_WRITE_PREVIOUS      0xc0000000
1634 #define PHY_SKIPN               0xd0000000
1635 #define PHY_DELAY_MS            0xe0000000
1636 #define PHY_WRITE_ERI_WORD      0xf0000000
1637
1638 static void
1639 rtl_phy_write_fw(struct rtl8169_private *tp, const struct firmware *fw)
1640 {
1641         __le32 *phytable = (__le32 *)fw->data;
1642         struct net_device *dev = tp->dev;
1643         size_t index, fw_size = fw->size / sizeof(*phytable);
1644         u32 predata, count;
1645
1646         if (fw->size % sizeof(*phytable)) {
1647                 netif_err(tp, probe, dev, "odd sized firmware %zd\n", fw->size);
1648                 return;
1649         }
1650
1651         for (index = 0; index < fw_size; index++) {
1652                 u32 action = le32_to_cpu(phytable[index]);
1653                 u32 regno = (action & 0x0fff0000) >> 16;
1654
1655                 switch(action & 0xf0000000) {
1656                 case PHY_READ:
1657                 case PHY_DATA_OR:
1658                 case PHY_DATA_AND:
1659                 case PHY_READ_EFUSE:
1660                 case PHY_CLEAR_READCOUNT:
1661                 case PHY_WRITE:
1662                 case PHY_WRITE_PREVIOUS:
1663                 case PHY_DELAY_MS:
1664                         break;
1665
1666                 case PHY_BJMPN:
1667                         if (regno > index) {
1668                                 netif_err(tp, probe, tp->dev,
1669                                         "Out of range of firmware\n");
1670                                 return;
1671                         }
1672                         break;
1673                 case PHY_READCOUNT_EQ_SKIP:
1674                         if (index + 2 >= fw_size) {
1675                                 netif_err(tp, probe, tp->dev,
1676                                         "Out of range of firmware\n");
1677                                 return;
1678                         }
1679                         break;
1680                 case PHY_COMP_EQ_SKIPN:
1681                 case PHY_COMP_NEQ_SKIPN:
1682                 case PHY_SKIPN:
1683                         if (index + 1 + regno >= fw_size) {
1684                                 netif_err(tp, probe, tp->dev,
1685                                         "Out of range of firmware\n");
1686                                 return;
1687                         }
1688                         break;
1689
1690                 case PHY_READ_MAC_BYTE:
1691                 case PHY_WRITE_MAC_BYTE:
1692                 case PHY_WRITE_ERI_WORD:
1693                 default:
1694                         netif_err(tp, probe, tp->dev,
1695                                   "Invalid action 0x%08x\n", action);
1696                         return;
1697                 }
1698         }
1699
1700         predata = 0;
1701         count = 0;
1702
1703         for (index = 0; index < fw_size; ) {
1704                 u32 action = le32_to_cpu(phytable[index]);
1705                 u32 data = action & 0x0000ffff;
1706                 u32 regno = (action & 0x0fff0000) >> 16;
1707
1708                 if (!action)
1709                         break;
1710
1711                 switch(action & 0xf0000000) {
1712                 case PHY_READ:
1713                         predata = rtl_readphy(tp, regno);
1714                         count++;
1715                         index++;
1716                         break;
1717                 case PHY_DATA_OR:
1718                         predata |= data;
1719                         index++;
1720                         break;
1721                 case PHY_DATA_AND:
1722                         predata &= data;
1723                         index++;
1724                         break;
1725                 case PHY_BJMPN:
1726                         index -= regno;
1727                         break;
1728                 case PHY_READ_EFUSE:
1729                         predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
1730                         index++;
1731                         break;
1732                 case PHY_CLEAR_READCOUNT:
1733                         count = 0;
1734                         index++;
1735                         break;
1736                 case PHY_WRITE:
1737                         rtl_writephy(tp, regno, data);
1738                         index++;
1739                         break;
1740                 case PHY_READCOUNT_EQ_SKIP:
1741                         if (count == data)
1742                                 index += 2;
1743                         else
1744                                 index += 1;
1745                         break;
1746                 case PHY_COMP_EQ_SKIPN:
1747                         if (predata == data)
1748                                 index += regno;
1749                         index++;
1750                         break;
1751                 case PHY_COMP_NEQ_SKIPN:
1752                         if (predata != data)
1753                                 index += regno;
1754                         index++;
1755                         break;
1756                 case PHY_WRITE_PREVIOUS:
1757                         rtl_writephy(tp, regno, predata);
1758                         index++;
1759                         break;
1760                 case PHY_SKIPN:
1761                         index += regno + 1;
1762                         break;
1763                 case PHY_DELAY_MS:
1764                         mdelay(data);
1765                         index++;
1766                         break;
1767
1768                 case PHY_READ_MAC_BYTE:
1769                 case PHY_WRITE_MAC_BYTE:
1770                 case PHY_WRITE_ERI_WORD:
1771                 default:
1772                         BUG();
1773                 }
1774         }
1775 }
1776
1777 static void rtl_release_firmware(struct rtl8169_private *tp)
1778 {
1779         release_firmware(tp->fw);
1780         tp->fw = NULL;
1781 }
1782
1783 static int rtl_apply_firmware(struct rtl8169_private *tp, const char *fw_name)
1784 {
1785         const struct firmware **fw = &tp->fw;
1786         int rc = !*fw;
1787
1788         if (rc) {
1789                 rc = request_firmware(fw, fw_name, &tp->pci_dev->dev);
1790                 if (rc < 0)
1791                         goto out;
1792         }
1793
1794         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
1795         rtl_phy_write_fw(tp, *fw);
1796 out:
1797         return rc;
1798 }
1799
1800 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1801 {
1802         static const struct phy_reg phy_reg_init[] = {
1803                 { 0x1f, 0x0001 },
1804                 { 0x06, 0x006e },
1805                 { 0x08, 0x0708 },
1806                 { 0x15, 0x4000 },
1807                 { 0x18, 0x65c7 },
1808
1809                 { 0x1f, 0x0001 },
1810                 { 0x03, 0x00a1 },
1811                 { 0x02, 0x0008 },
1812                 { 0x01, 0x0120 },
1813                 { 0x00, 0x1000 },
1814                 { 0x04, 0x0800 },
1815                 { 0x04, 0x0000 },
1816
1817                 { 0x03, 0xff41 },
1818                 { 0x02, 0xdf60 },
1819                 { 0x01, 0x0140 },
1820                 { 0x00, 0x0077 },
1821                 { 0x04, 0x7800 },
1822                 { 0x04, 0x7000 },
1823
1824                 { 0x03, 0x802f },
1825                 { 0x02, 0x4f02 },
1826                 { 0x01, 0x0409 },
1827                 { 0x00, 0xf0f9 },
1828                 { 0x04, 0x9800 },
1829                 { 0x04, 0x9000 },
1830
1831                 { 0x03, 0xdf01 },
1832                 { 0x02, 0xdf20 },
1833                 { 0x01, 0xff95 },
1834                 { 0x00, 0xba00 },
1835                 { 0x04, 0xa800 },
1836                 { 0x04, 0xa000 },
1837
1838                 { 0x03, 0xff41 },
1839                 { 0x02, 0xdf20 },
1840                 { 0x01, 0x0140 },
1841                 { 0x00, 0x00bb },
1842                 { 0x04, 0xb800 },
1843                 { 0x04, 0xb000 },
1844
1845                 { 0x03, 0xdf41 },
1846                 { 0x02, 0xdc60 },
1847                 { 0x01, 0x6340 },
1848                 { 0x00, 0x007d },
1849                 { 0x04, 0xd800 },
1850                 { 0x04, 0xd000 },
1851
1852                 { 0x03, 0xdf01 },
1853                 { 0x02, 0xdf20 },
1854                 { 0x01, 0x100a },
1855                 { 0x00, 0xa0ff },
1856                 { 0x04, 0xf800 },
1857                 { 0x04, 0xf000 },
1858
1859                 { 0x1f, 0x0000 },
1860                 { 0x0b, 0x0000 },
1861                 { 0x00, 0x9200 }
1862         };
1863
1864         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1865 }
1866
1867 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
1868 {
1869         static const struct phy_reg phy_reg_init[] = {
1870                 { 0x1f, 0x0002 },
1871                 { 0x01, 0x90d0 },
1872                 { 0x1f, 0x0000 }
1873         };
1874
1875         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1876 }
1877
1878 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
1879 {
1880         struct pci_dev *pdev = tp->pci_dev;
1881         u16 vendor_id, device_id;
1882
1883         pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
1884         pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
1885
1886         if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
1887                 return;
1888
1889         rtl_writephy(tp, 0x1f, 0x0001);
1890         rtl_writephy(tp, 0x10, 0xf01b);
1891         rtl_writephy(tp, 0x1f, 0x0000);
1892 }
1893
1894 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
1895 {
1896         static const struct phy_reg phy_reg_init[] = {
1897                 { 0x1f, 0x0001 },
1898                 { 0x04, 0x0000 },
1899                 { 0x03, 0x00a1 },
1900                 { 0x02, 0x0008 },
1901                 { 0x01, 0x0120 },
1902                 { 0x00, 0x1000 },
1903                 { 0x04, 0x0800 },
1904                 { 0x04, 0x9000 },
1905                 { 0x03, 0x802f },
1906                 { 0x02, 0x4f02 },
1907                 { 0x01, 0x0409 },
1908                 { 0x00, 0xf099 },
1909                 { 0x04, 0x9800 },
1910                 { 0x04, 0xa000 },
1911                 { 0x03, 0xdf01 },
1912                 { 0x02, 0xdf20 },
1913                 { 0x01, 0xff95 },
1914                 { 0x00, 0xba00 },
1915                 { 0x04, 0xa800 },
1916                 { 0x04, 0xf000 },
1917                 { 0x03, 0xdf01 },
1918                 { 0x02, 0xdf20 },
1919                 { 0x01, 0x101a },
1920                 { 0x00, 0xa0ff },
1921                 { 0x04, 0xf800 },
1922                 { 0x04, 0x0000 },
1923                 { 0x1f, 0x0000 },
1924
1925                 { 0x1f, 0x0001 },
1926                 { 0x10, 0xf41b },
1927                 { 0x14, 0xfb54 },
1928                 { 0x18, 0xf5c7 },
1929                 { 0x1f, 0x0000 },
1930
1931                 { 0x1f, 0x0001 },
1932                 { 0x17, 0x0cc0 },
1933                 { 0x1f, 0x0000 }
1934         };
1935
1936         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1937
1938         rtl8169scd_hw_phy_config_quirk(tp);
1939 }
1940
1941 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
1942 {
1943         static const struct phy_reg phy_reg_init[] = {
1944                 { 0x1f, 0x0001 },
1945                 { 0x04, 0x0000 },
1946                 { 0x03, 0x00a1 },
1947                 { 0x02, 0x0008 },
1948                 { 0x01, 0x0120 },
1949                 { 0x00, 0x1000 },
1950                 { 0x04, 0x0800 },
1951                 { 0x04, 0x9000 },
1952                 { 0x03, 0x802f },
1953                 { 0x02, 0x4f02 },
1954                 { 0x01, 0x0409 },
1955                 { 0x00, 0xf099 },
1956                 { 0x04, 0x9800 },
1957                 { 0x04, 0xa000 },
1958                 { 0x03, 0xdf01 },
1959                 { 0x02, 0xdf20 },
1960                 { 0x01, 0xff95 },
1961                 { 0x00, 0xba00 },
1962                 { 0x04, 0xa800 },
1963                 { 0x04, 0xf000 },
1964                 { 0x03, 0xdf01 },
1965                 { 0x02, 0xdf20 },
1966                 { 0x01, 0x101a },
1967                 { 0x00, 0xa0ff },
1968                 { 0x04, 0xf800 },
1969                 { 0x04, 0x0000 },
1970                 { 0x1f, 0x0000 },
1971
1972                 { 0x1f, 0x0001 },
1973                 { 0x0b, 0x8480 },
1974                 { 0x1f, 0x0000 },
1975
1976                 { 0x1f, 0x0001 },
1977                 { 0x18, 0x67c7 },
1978                 { 0x04, 0x2000 },
1979                 { 0x03, 0x002f },
1980                 { 0x02, 0x4360 },
1981                 { 0x01, 0x0109 },
1982                 { 0x00, 0x3022 },
1983                 { 0x04, 0x2800 },
1984                 { 0x1f, 0x0000 },
1985
1986                 { 0x1f, 0x0001 },
1987                 { 0x17, 0x0cc0 },
1988                 { 0x1f, 0x0000 }
1989         };
1990
1991         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1992 }
1993
1994 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
1995 {
1996         static const struct phy_reg phy_reg_init[] = {
1997                 { 0x10, 0xf41b },
1998                 { 0x1f, 0x0000 }
1999         };
2000
2001         rtl_writephy(tp, 0x1f, 0x0001);
2002         rtl_patchphy(tp, 0x16, 1 << 0);
2003
2004         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2005 }
2006
2007 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2008 {
2009         static const struct phy_reg phy_reg_init[] = {
2010                 { 0x1f, 0x0001 },
2011                 { 0x10, 0xf41b },
2012                 { 0x1f, 0x0000 }
2013         };
2014
2015         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2016 }
2017
2018 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2019 {
2020         static const struct phy_reg phy_reg_init[] = {
2021                 { 0x1f, 0x0000 },
2022                 { 0x1d, 0x0f00 },
2023                 { 0x1f, 0x0002 },
2024                 { 0x0c, 0x1ec8 },
2025                 { 0x1f, 0x0000 }
2026         };
2027
2028         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2029 }
2030
2031 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2032 {
2033         static const struct phy_reg phy_reg_init[] = {
2034                 { 0x1f, 0x0001 },
2035                 { 0x1d, 0x3d98 },
2036                 { 0x1f, 0x0000 }
2037         };
2038
2039         rtl_writephy(tp, 0x1f, 0x0000);
2040         rtl_patchphy(tp, 0x14, 1 << 5);
2041         rtl_patchphy(tp, 0x0d, 1 << 5);
2042
2043         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2044 }
2045
2046 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2047 {
2048         static const struct phy_reg phy_reg_init[] = {
2049                 { 0x1f, 0x0001 },
2050                 { 0x12, 0x2300 },
2051                 { 0x1f, 0x0002 },
2052                 { 0x00, 0x88d4 },
2053                 { 0x01, 0x82b1 },
2054                 { 0x03, 0x7002 },
2055                 { 0x08, 0x9e30 },
2056                 { 0x09, 0x01f0 },
2057                 { 0x0a, 0x5500 },
2058                 { 0x0c, 0x00c8 },
2059                 { 0x1f, 0x0003 },
2060                 { 0x12, 0xc096 },
2061                 { 0x16, 0x000a },
2062                 { 0x1f, 0x0000 },
2063                 { 0x1f, 0x0000 },
2064                 { 0x09, 0x2000 },
2065                 { 0x09, 0x0000 }
2066         };
2067
2068         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2069
2070         rtl_patchphy(tp, 0x14, 1 << 5);
2071         rtl_patchphy(tp, 0x0d, 1 << 5);
2072         rtl_writephy(tp, 0x1f, 0x0000);
2073 }
2074
2075 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2076 {
2077         static const struct phy_reg phy_reg_init[] = {
2078                 { 0x1f, 0x0001 },
2079                 { 0x12, 0x2300 },
2080                 { 0x03, 0x802f },
2081                 { 0x02, 0x4f02 },
2082                 { 0x01, 0x0409 },
2083                 { 0x00, 0xf099 },
2084                 { 0x04, 0x9800 },
2085                 { 0x04, 0x9000 },
2086                 { 0x1d, 0x3d98 },
2087                 { 0x1f, 0x0002 },
2088                 { 0x0c, 0x7eb8 },
2089                 { 0x06, 0x0761 },
2090                 { 0x1f, 0x0003 },
2091                 { 0x16, 0x0f0a },
2092                 { 0x1f, 0x0000 }
2093         };
2094
2095         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2096
2097         rtl_patchphy(tp, 0x16, 1 << 0);
2098         rtl_patchphy(tp, 0x14, 1 << 5);
2099         rtl_patchphy(tp, 0x0d, 1 << 5);
2100         rtl_writephy(tp, 0x1f, 0x0000);
2101 }
2102
2103 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2104 {
2105         static const struct phy_reg phy_reg_init[] = {
2106                 { 0x1f, 0x0001 },
2107                 { 0x12, 0x2300 },
2108                 { 0x1d, 0x3d98 },
2109                 { 0x1f, 0x0002 },
2110                 { 0x0c, 0x7eb8 },
2111                 { 0x06, 0x5461 },
2112                 { 0x1f, 0x0003 },
2113                 { 0x16, 0x0f0a },
2114                 { 0x1f, 0x0000 }
2115         };
2116
2117         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2118
2119         rtl_patchphy(tp, 0x16, 1 << 0);
2120         rtl_patchphy(tp, 0x14, 1 << 5);
2121         rtl_patchphy(tp, 0x0d, 1 << 5);
2122         rtl_writephy(tp, 0x1f, 0x0000);
2123 }
2124
2125 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2126 {
2127         rtl8168c_3_hw_phy_config(tp);
2128 }
2129
2130 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2131 {
2132         static const struct phy_reg phy_reg_init_0[] = {
2133                 /* Channel Estimation */
2134                 { 0x1f, 0x0001 },
2135                 { 0x06, 0x4064 },
2136                 { 0x07, 0x2863 },
2137                 { 0x08, 0x059c },
2138                 { 0x09, 0x26b4 },
2139                 { 0x0a, 0x6a19 },
2140                 { 0x0b, 0xdcc8 },
2141                 { 0x10, 0xf06d },
2142                 { 0x14, 0x7f68 },
2143                 { 0x18, 0x7fd9 },
2144                 { 0x1c, 0xf0ff },
2145                 { 0x1d, 0x3d9c },
2146                 { 0x1f, 0x0003 },
2147                 { 0x12, 0xf49f },
2148                 { 0x13, 0x070b },
2149                 { 0x1a, 0x05ad },
2150                 { 0x14, 0x94c0 },
2151
2152                 /*
2153                  * Tx Error Issue
2154                  * enhance line driver power
2155                  */
2156                 { 0x1f, 0x0002 },
2157                 { 0x06, 0x5561 },
2158                 { 0x1f, 0x0005 },
2159                 { 0x05, 0x8332 },
2160                 { 0x06, 0x5561 },
2161
2162                 /*
2163                  * Can not link to 1Gbps with bad cable
2164                  * Decrease SNR threshold form 21.07dB to 19.04dB
2165                  */
2166                 { 0x1f, 0x0001 },
2167                 { 0x17, 0x0cc0 },
2168
2169                 { 0x1f, 0x0000 },
2170                 { 0x0d, 0xf880 }
2171         };
2172         void __iomem *ioaddr = tp->mmio_addr;
2173
2174         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2175
2176         /*
2177          * Rx Error Issue
2178          * Fine Tune Switching regulator parameter
2179          */
2180         rtl_writephy(tp, 0x1f, 0x0002);
2181         rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2182         rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2183
2184         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2185                 static const struct phy_reg phy_reg_init[] = {
2186                         { 0x1f, 0x0002 },
2187                         { 0x05, 0x669a },
2188                         { 0x1f, 0x0005 },
2189                         { 0x05, 0x8330 },
2190                         { 0x06, 0x669a },
2191                         { 0x1f, 0x0002 }
2192                 };
2193                 int val;
2194
2195                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2196
2197                 val = rtl_readphy(tp, 0x0d);
2198
2199                 if ((val & 0x00ff) != 0x006c) {
2200                         static const u32 set[] = {
2201                                 0x0065, 0x0066, 0x0067, 0x0068,
2202                                 0x0069, 0x006a, 0x006b, 0x006c
2203                         };
2204                         int i;
2205
2206                         rtl_writephy(tp, 0x1f, 0x0002);
2207
2208                         val &= 0xff00;
2209                         for (i = 0; i < ARRAY_SIZE(set); i++)
2210                                 rtl_writephy(tp, 0x0d, val | set[i]);
2211                 }
2212         } else {
2213                 static const struct phy_reg phy_reg_init[] = {
2214                         { 0x1f, 0x0002 },
2215                         { 0x05, 0x6662 },
2216                         { 0x1f, 0x0005 },
2217                         { 0x05, 0x8330 },
2218                         { 0x06, 0x6662 }
2219                 };
2220
2221                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2222         }
2223
2224         /* RSET couple improve */
2225         rtl_writephy(tp, 0x1f, 0x0002);
2226         rtl_patchphy(tp, 0x0d, 0x0300);
2227         rtl_patchphy(tp, 0x0f, 0x0010);
2228
2229         /* Fine tune PLL performance */
2230         rtl_writephy(tp, 0x1f, 0x0002);
2231         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2232         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2233
2234         rtl_writephy(tp, 0x1f, 0x0005);
2235         rtl_writephy(tp, 0x05, 0x001b);
2236         if ((rtl_readphy(tp, 0x06) != 0xbf00) ||
2237             (rtl_apply_firmware(tp, FIRMWARE_8168D_1) < 0)) {
2238                 netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n");
2239         }
2240
2241         rtl_writephy(tp, 0x1f, 0x0000);
2242 }
2243
2244 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2245 {
2246         static const struct phy_reg phy_reg_init_0[] = {
2247                 /* Channel Estimation */
2248                 { 0x1f, 0x0001 },
2249                 { 0x06, 0x4064 },
2250                 { 0x07, 0x2863 },
2251                 { 0x08, 0x059c },
2252                 { 0x09, 0x26b4 },
2253                 { 0x0a, 0x6a19 },
2254                 { 0x0b, 0xdcc8 },
2255                 { 0x10, 0xf06d },
2256                 { 0x14, 0x7f68 },
2257                 { 0x18, 0x7fd9 },
2258                 { 0x1c, 0xf0ff },
2259                 { 0x1d, 0x3d9c },
2260                 { 0x1f, 0x0003 },
2261                 { 0x12, 0xf49f },
2262                 { 0x13, 0x070b },
2263                 { 0x1a, 0x05ad },
2264                 { 0x14, 0x94c0 },
2265
2266                 /*
2267                  * Tx Error Issue
2268                  * enhance line driver power
2269                  */
2270                 { 0x1f, 0x0002 },
2271                 { 0x06, 0x5561 },
2272                 { 0x1f, 0x0005 },
2273                 { 0x05, 0x8332 },
2274                 { 0x06, 0x5561 },
2275
2276                 /*
2277                  * Can not link to 1Gbps with bad cable
2278                  * Decrease SNR threshold form 21.07dB to 19.04dB
2279                  */
2280                 { 0x1f, 0x0001 },
2281                 { 0x17, 0x0cc0 },
2282
2283                 { 0x1f, 0x0000 },
2284                 { 0x0d, 0xf880 }
2285         };
2286         void __iomem *ioaddr = tp->mmio_addr;
2287
2288         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2289
2290         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2291                 static const struct phy_reg phy_reg_init[] = {
2292                         { 0x1f, 0x0002 },
2293                         { 0x05, 0x669a },
2294                         { 0x1f, 0x0005 },
2295                         { 0x05, 0x8330 },
2296                         { 0x06, 0x669a },
2297
2298                         { 0x1f, 0x0002 }
2299                 };
2300                 int val;
2301
2302                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2303
2304                 val = rtl_readphy(tp, 0x0d);
2305                 if ((val & 0x00ff) != 0x006c) {
2306                         static const u32 set[] = {
2307                                 0x0065, 0x0066, 0x0067, 0x0068,
2308                                 0x0069, 0x006a, 0x006b, 0x006c
2309                         };
2310                         int i;
2311
2312                         rtl_writephy(tp, 0x1f, 0x0002);
2313
2314                         val &= 0xff00;
2315                         for (i = 0; i < ARRAY_SIZE(set); i++)
2316                                 rtl_writephy(tp, 0x0d, val | set[i]);
2317                 }
2318         } else {
2319                 static const struct phy_reg phy_reg_init[] = {
2320                         { 0x1f, 0x0002 },
2321                         { 0x05, 0x2642 },
2322                         { 0x1f, 0x0005 },
2323                         { 0x05, 0x8330 },
2324                         { 0x06, 0x2642 }
2325                 };
2326
2327                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2328         }
2329
2330         /* Fine tune PLL performance */
2331         rtl_writephy(tp, 0x1f, 0x0002);
2332         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2333         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2334
2335         /* Switching regulator Slew rate */
2336         rtl_writephy(tp, 0x1f, 0x0002);
2337         rtl_patchphy(tp, 0x0f, 0x0017);
2338
2339         rtl_writephy(tp, 0x1f, 0x0005);
2340         rtl_writephy(tp, 0x05, 0x001b);
2341         if ((rtl_readphy(tp, 0x06) != 0xb300) ||
2342             (rtl_apply_firmware(tp, FIRMWARE_8168D_2) < 0)) {
2343                 netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n");
2344         }
2345
2346         rtl_writephy(tp, 0x1f, 0x0000);
2347 }
2348
2349 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2350 {
2351         static const struct phy_reg phy_reg_init[] = {
2352                 { 0x1f, 0x0002 },
2353                 { 0x10, 0x0008 },
2354                 { 0x0d, 0x006c },
2355
2356                 { 0x1f, 0x0000 },
2357                 { 0x0d, 0xf880 },
2358
2359                 { 0x1f, 0x0001 },
2360                 { 0x17, 0x0cc0 },
2361
2362                 { 0x1f, 0x0001 },
2363                 { 0x0b, 0xa4d8 },
2364                 { 0x09, 0x281c },
2365                 { 0x07, 0x2883 },
2366                 { 0x0a, 0x6b35 },
2367                 { 0x1d, 0x3da4 },
2368                 { 0x1c, 0xeffd },
2369                 { 0x14, 0x7f52 },
2370                 { 0x18, 0x7fc6 },
2371                 { 0x08, 0x0601 },
2372                 { 0x06, 0x4063 },
2373                 { 0x10, 0xf074 },
2374                 { 0x1f, 0x0003 },
2375                 { 0x13, 0x0789 },
2376                 { 0x12, 0xf4bd },
2377                 { 0x1a, 0x04fd },
2378                 { 0x14, 0x84b0 },
2379                 { 0x1f, 0x0000 },
2380                 { 0x00, 0x9200 },
2381
2382                 { 0x1f, 0x0005 },
2383                 { 0x01, 0x0340 },
2384                 { 0x1f, 0x0001 },
2385                 { 0x04, 0x4000 },
2386                 { 0x03, 0x1d21 },
2387                 { 0x02, 0x0c32 },
2388                 { 0x01, 0x0200 },
2389                 { 0x00, 0x5554 },
2390                 { 0x04, 0x4800 },
2391                 { 0x04, 0x4000 },
2392                 { 0x04, 0xf000 },
2393                 { 0x03, 0xdf01 },
2394                 { 0x02, 0xdf20 },
2395                 { 0x01, 0x101a },
2396                 { 0x00, 0xa0ff },
2397                 { 0x04, 0xf800 },
2398                 { 0x04, 0xf000 },
2399                 { 0x1f, 0x0000 },
2400
2401                 { 0x1f, 0x0007 },
2402                 { 0x1e, 0x0023 },
2403                 { 0x16, 0x0000 },
2404                 { 0x1f, 0x0000 }
2405         };
2406
2407         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2408 }
2409
2410 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2411 {
2412         static const struct phy_reg phy_reg_init[] = {
2413                 { 0x1f, 0x0001 },
2414                 { 0x17, 0x0cc0 },
2415
2416                 { 0x1f, 0x0007 },
2417                 { 0x1e, 0x002d },
2418                 { 0x18, 0x0040 },
2419                 { 0x1f, 0x0000 }
2420         };
2421
2422         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2423         rtl_patchphy(tp, 0x0d, 1 << 5);
2424 }
2425
2426 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2427 {
2428         static const struct phy_reg phy_reg_init[] = {
2429                 { 0x1f, 0x0003 },
2430                 { 0x08, 0x441d },
2431                 { 0x01, 0x9100 },
2432                 { 0x1f, 0x0000 }
2433         };
2434
2435         rtl_writephy(tp, 0x1f, 0x0000);
2436         rtl_patchphy(tp, 0x11, 1 << 12);
2437         rtl_patchphy(tp, 0x19, 1 << 13);
2438         rtl_patchphy(tp, 0x10, 1 << 15);
2439
2440         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2441 }
2442
2443 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
2444 {
2445         static const struct phy_reg phy_reg_init[] = {
2446                 { 0x1f, 0x0005 },
2447                 { 0x1a, 0x0000 },
2448                 { 0x1f, 0x0000 },
2449
2450                 { 0x1f, 0x0004 },
2451                 { 0x1c, 0x0000 },
2452                 { 0x1f, 0x0000 },
2453
2454                 { 0x1f, 0x0001 },
2455                 { 0x15, 0x7701 },
2456                 { 0x1f, 0x0000 }
2457         };
2458
2459         /* Disable ALDPS before ram code */
2460         rtl_writephy(tp, 0x1f, 0x0000);
2461         rtl_writephy(tp, 0x18, 0x0310);
2462         msleep(100);
2463
2464         if (rtl_apply_firmware(tp, FIRMWARE_8105E_1) < 0)
2465                 netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n");
2466
2467         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2468 }
2469
2470 static void rtl_hw_phy_config(struct net_device *dev)
2471 {
2472         struct rtl8169_private *tp = netdev_priv(dev);
2473
2474         rtl8169_print_mac_version(tp);
2475
2476         switch (tp->mac_version) {
2477         case RTL_GIGA_MAC_VER_01:
2478                 break;
2479         case RTL_GIGA_MAC_VER_02:
2480         case RTL_GIGA_MAC_VER_03:
2481                 rtl8169s_hw_phy_config(tp);
2482                 break;
2483         case RTL_GIGA_MAC_VER_04:
2484                 rtl8169sb_hw_phy_config(tp);
2485                 break;
2486         case RTL_GIGA_MAC_VER_05:
2487                 rtl8169scd_hw_phy_config(tp);
2488                 break;
2489         case RTL_GIGA_MAC_VER_06:
2490                 rtl8169sce_hw_phy_config(tp);
2491                 break;
2492         case RTL_GIGA_MAC_VER_07:
2493         case RTL_GIGA_MAC_VER_08:
2494         case RTL_GIGA_MAC_VER_09:
2495                 rtl8102e_hw_phy_config(tp);
2496                 break;
2497         case RTL_GIGA_MAC_VER_11:
2498                 rtl8168bb_hw_phy_config(tp);
2499                 break;
2500         case RTL_GIGA_MAC_VER_12:
2501                 rtl8168bef_hw_phy_config(tp);
2502                 break;
2503         case RTL_GIGA_MAC_VER_17:
2504                 rtl8168bef_hw_phy_config(tp);
2505                 break;
2506         case RTL_GIGA_MAC_VER_18:
2507                 rtl8168cp_1_hw_phy_config(tp);
2508                 break;
2509         case RTL_GIGA_MAC_VER_19:
2510                 rtl8168c_1_hw_phy_config(tp);
2511                 break;
2512         case RTL_GIGA_MAC_VER_20:
2513                 rtl8168c_2_hw_phy_config(tp);
2514                 break;
2515         case RTL_GIGA_MAC_VER_21:
2516                 rtl8168c_3_hw_phy_config(tp);
2517                 break;
2518         case RTL_GIGA_MAC_VER_22:
2519                 rtl8168c_4_hw_phy_config(tp);
2520                 break;
2521         case RTL_GIGA_MAC_VER_23:
2522         case RTL_GIGA_MAC_VER_24:
2523                 rtl8168cp_2_hw_phy_config(tp);
2524                 break;
2525         case RTL_GIGA_MAC_VER_25:
2526                 rtl8168d_1_hw_phy_config(tp);
2527                 break;
2528         case RTL_GIGA_MAC_VER_26:
2529                 rtl8168d_2_hw_phy_config(tp);
2530                 break;
2531         case RTL_GIGA_MAC_VER_27:
2532                 rtl8168d_3_hw_phy_config(tp);
2533                 break;
2534         case RTL_GIGA_MAC_VER_28:
2535                 rtl8168d_4_hw_phy_config(tp);
2536                 break;
2537         case RTL_GIGA_MAC_VER_29:
2538         case RTL_GIGA_MAC_VER_30:
2539                 rtl8105e_hw_phy_config(tp);
2540                 break;
2541
2542         default:
2543                 break;
2544         }
2545 }
2546
2547 static void rtl8169_phy_timer(unsigned long __opaque)
2548 {
2549         struct net_device *dev = (struct net_device *)__opaque;
2550         struct rtl8169_private *tp = netdev_priv(dev);
2551         struct timer_list *timer = &tp->timer;
2552         void __iomem *ioaddr = tp->mmio_addr;
2553         unsigned long timeout = RTL8169_PHY_TIMEOUT;
2554
2555         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
2556
2557         if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
2558                 return;
2559
2560         spin_lock_irq(&tp->lock);
2561
2562         if (tp->phy_reset_pending(tp)) {
2563                 /*
2564                  * A busy loop could burn quite a few cycles on nowadays CPU.
2565                  * Let's delay the execution of the timer for a few ticks.
2566                  */
2567                 timeout = HZ/10;
2568                 goto out_mod_timer;
2569         }
2570
2571         if (tp->link_ok(ioaddr))
2572                 goto out_unlock;
2573
2574         netif_warn(tp, link, dev, "PHY reset until link up\n");
2575
2576         tp->phy_reset_enable(tp);
2577
2578 out_mod_timer:
2579         mod_timer(timer, jiffies + timeout);
2580 out_unlock:
2581         spin_unlock_irq(&tp->lock);
2582 }
2583
2584 static inline void rtl8169_delete_timer(struct net_device *dev)
2585 {
2586         struct rtl8169_private *tp = netdev_priv(dev);
2587         struct timer_list *timer = &tp->timer;
2588
2589         if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
2590                 return;
2591
2592         del_timer_sync(timer);
2593 }
2594
2595 static inline void rtl8169_request_timer(struct net_device *dev)
2596 {
2597         struct rtl8169_private *tp = netdev_priv(dev);
2598         struct timer_list *timer = &tp->timer;
2599
2600         if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
2601                 return;
2602
2603         mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
2604 }
2605
2606 #ifdef CONFIG_NET_POLL_CONTROLLER
2607 /*
2608  * Polling 'interrupt' - used by things like netconsole to send skbs
2609  * without having to re-enable interrupts. It's not called while
2610  * the interrupt routine is executing.
2611  */
2612 static void rtl8169_netpoll(struct net_device *dev)
2613 {
2614         struct rtl8169_private *tp = netdev_priv(dev);
2615         struct pci_dev *pdev = tp->pci_dev;
2616
2617         disable_irq(pdev->irq);
2618         rtl8169_interrupt(pdev->irq, dev);
2619         enable_irq(pdev->irq);
2620 }
2621 #endif
2622
2623 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
2624                                   void __iomem *ioaddr)
2625 {
2626         iounmap(ioaddr);
2627         pci_release_regions(pdev);
2628         pci_clear_mwi(pdev);
2629         pci_disable_device(pdev);
2630         free_netdev(dev);
2631 }
2632
2633 static void rtl8169_phy_reset(struct net_device *dev,
2634                               struct rtl8169_private *tp)
2635 {
2636         unsigned int i;
2637
2638         tp->phy_reset_enable(tp);
2639         for (i = 0; i < 100; i++) {
2640                 if (!tp->phy_reset_pending(tp))
2641                         return;
2642                 msleep(1);
2643         }
2644         netif_err(tp, link, dev, "PHY reset failed\n");
2645 }
2646
2647 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
2648 {
2649         void __iomem *ioaddr = tp->mmio_addr;
2650
2651         rtl_hw_phy_config(dev);
2652
2653         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2654                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2655                 RTL_W8(0x82, 0x01);
2656         }
2657
2658         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2659
2660         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
2661                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
2662
2663         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
2664                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2665                 RTL_W8(0x82, 0x01);
2666                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
2667                 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
2668         }
2669
2670         rtl8169_phy_reset(dev, tp);
2671
2672         /*
2673          * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
2674          * only 8101. Don't panic.
2675          */
2676         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
2677
2678         if (RTL_R8(PHYstatus) & TBI_Enable)
2679                 netif_info(tp, link, dev, "TBI auto-negotiating\n");
2680 }
2681
2682 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2683 {
2684         void __iomem *ioaddr = tp->mmio_addr;
2685         u32 high;
2686         u32 low;
2687
2688         low  = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
2689         high = addr[4] | (addr[5] << 8);
2690
2691         spin_lock_irq(&tp->lock);
2692
2693         RTL_W8(Cfg9346, Cfg9346_Unlock);
2694
2695         RTL_W32(MAC4, high);
2696         RTL_R32(MAC4);
2697
2698         RTL_W32(MAC0, low);
2699         RTL_R32(MAC0);
2700
2701         RTL_W8(Cfg9346, Cfg9346_Lock);
2702
2703         spin_unlock_irq(&tp->lock);
2704 }
2705
2706 static int rtl_set_mac_address(struct net_device *dev, void *p)
2707 {
2708         struct rtl8169_private *tp = netdev_priv(dev);
2709         struct sockaddr *addr = p;
2710
2711         if (!is_valid_ether_addr(addr->sa_data))
2712                 return -EADDRNOTAVAIL;
2713
2714         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2715
2716         rtl_rar_set(tp, dev->dev_addr);
2717
2718         return 0;
2719 }
2720
2721 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2722 {
2723         struct rtl8169_private *tp = netdev_priv(dev);
2724         struct mii_ioctl_data *data = if_mii(ifr);
2725
2726         return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
2727 }
2728
2729 static int rtl_xmii_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2730 {
2731         switch (cmd) {
2732         case SIOCGMIIPHY:
2733                 data->phy_id = 32; /* Internal PHY */
2734                 return 0;
2735
2736         case SIOCGMIIREG:
2737                 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
2738                 return 0;
2739
2740         case SIOCSMIIREG:
2741                 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
2742                 return 0;
2743         }
2744         return -EOPNOTSUPP;
2745 }
2746
2747 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2748 {
2749         return -EOPNOTSUPP;
2750 }
2751
2752 static const struct rtl_cfg_info {
2753         void (*hw_start)(struct net_device *);
2754         unsigned int region;
2755         unsigned int align;
2756         u16 intr_event;
2757         u16 napi_event;
2758         unsigned features;
2759         u8 default_ver;
2760 } rtl_cfg_infos [] = {
2761         [RTL_CFG_0] = {
2762                 .hw_start       = rtl_hw_start_8169,
2763                 .region         = 1,
2764                 .align          = 0,
2765                 .intr_event     = SYSErr | LinkChg | RxOverflow |
2766                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2767                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2768                 .features       = RTL_FEATURE_GMII,
2769                 .default_ver    = RTL_GIGA_MAC_VER_01,
2770         },
2771         [RTL_CFG_1] = {
2772                 .hw_start       = rtl_hw_start_8168,
2773                 .region         = 2,
2774                 .align          = 8,
2775                 .intr_event     = SYSErr | LinkChg | RxOverflow |
2776                                   TxErr | TxOK | RxOK | RxErr,
2777                 .napi_event     = TxErr | TxOK | RxOK | RxOverflow,
2778                 .features       = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
2779                 .default_ver    = RTL_GIGA_MAC_VER_11,
2780         },
2781         [RTL_CFG_2] = {
2782                 .hw_start       = rtl_hw_start_8101,
2783                 .region         = 2,
2784                 .align          = 8,
2785                 .intr_event     = SYSErr | LinkChg | RxOverflow | PCSTimeout |
2786                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2787                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2788                 .features       = RTL_FEATURE_MSI,
2789                 .default_ver    = RTL_GIGA_MAC_VER_13,
2790         }
2791 };
2792
2793 /* Cfg9346_Unlock assumed. */
2794 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
2795                             const struct rtl_cfg_info *cfg)
2796 {
2797         unsigned msi = 0;
2798         u8 cfg2;
2799
2800         cfg2 = RTL_R8(Config2) & ~MSIEnable;
2801         if (cfg->features & RTL_FEATURE_MSI) {
2802                 if (pci_enable_msi(pdev)) {
2803                         dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
2804                 } else {
2805                         cfg2 |= MSIEnable;
2806                         msi = RTL_FEATURE_MSI;
2807                 }
2808         }
2809         RTL_W8(Config2, cfg2);
2810         return msi;
2811 }
2812
2813 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
2814 {
2815         if (tp->features & RTL_FEATURE_MSI) {
2816                 pci_disable_msi(pdev);
2817                 tp->features &= ~RTL_FEATURE_MSI;
2818         }
2819 }
2820
2821 static const struct net_device_ops rtl8169_netdev_ops = {
2822         .ndo_open               = rtl8169_open,
2823         .ndo_stop               = rtl8169_close,
2824         .ndo_get_stats          = rtl8169_get_stats,
2825         .ndo_start_xmit         = rtl8169_start_xmit,
2826         .ndo_tx_timeout         = rtl8169_tx_timeout,
2827         .ndo_validate_addr      = eth_validate_addr,
2828         .ndo_change_mtu         = rtl8169_change_mtu,
2829         .ndo_set_mac_address    = rtl_set_mac_address,
2830         .ndo_do_ioctl           = rtl8169_ioctl,
2831         .ndo_set_multicast_list = rtl_set_rx_mode,
2832 #ifdef CONFIG_R8169_VLAN
2833         .ndo_vlan_rx_register   = rtl8169_vlan_rx_register,
2834 #endif
2835 #ifdef CONFIG_NET_POLL_CONTROLLER
2836         .ndo_poll_controller    = rtl8169_netpoll,
2837 #endif
2838
2839 };
2840
2841 static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
2842 {
2843         struct mdio_ops *ops = &tp->mdio_ops;
2844
2845         switch (tp->mac_version) {
2846         case RTL_GIGA_MAC_VER_27:
2847                 ops->write      = r8168dp_1_mdio_write;
2848                 ops->read       = r8168dp_1_mdio_read;
2849                 break;
2850         case RTL_GIGA_MAC_VER_28:
2851                 ops->write      = r8168dp_2_mdio_write;
2852                 ops->read       = r8168dp_2_mdio_read;
2853                 break;
2854         default:
2855                 ops->write      = r8169_mdio_write;
2856                 ops->read       = r8169_mdio_read;
2857                 break;
2858         }
2859 }
2860
2861 static void r810x_phy_power_down(struct rtl8169_private *tp)
2862 {
2863         rtl_writephy(tp, 0x1f, 0x0000);
2864         rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
2865 }
2866
2867 static void r810x_phy_power_up(struct rtl8169_private *tp)
2868 {
2869         rtl_writephy(tp, 0x1f, 0x0000);
2870         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
2871 }
2872
2873 static void r810x_pll_power_down(struct rtl8169_private *tp)
2874 {
2875         if (__rtl8169_get_wol(tp) & WAKE_ANY) {
2876                 rtl_writephy(tp, 0x1f, 0x0000);
2877                 rtl_writephy(tp, MII_BMCR, 0x0000);
2878                 return;
2879         }
2880
2881         r810x_phy_power_down(tp);
2882 }
2883
2884 static void r810x_pll_power_up(struct rtl8169_private *tp)
2885 {
2886         r810x_phy_power_up(tp);
2887 }
2888
2889 static void r8168_phy_power_up(struct rtl8169_private *tp)
2890 {
2891         rtl_writephy(tp, 0x1f, 0x0000);
2892         rtl_writephy(tp, 0x0e, 0x0000);
2893         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
2894 }
2895
2896 static void r8168_phy_power_down(struct rtl8169_private *tp)
2897 {
2898         rtl_writephy(tp, 0x1f, 0x0000);
2899         rtl_writephy(tp, 0x0e, 0x0200);
2900         rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
2901 }
2902
2903 static void r8168_pll_power_down(struct rtl8169_private *tp)
2904 {
2905         void __iomem *ioaddr = tp->mmio_addr;
2906
2907         if (tp->mac_version == RTL_GIGA_MAC_VER_27)
2908                 return;
2909
2910         if (((tp->mac_version == RTL_GIGA_MAC_VER_23) ||
2911              (tp->mac_version == RTL_GIGA_MAC_VER_24)) &&
2912             (RTL_R16(CPlusCmd) & ASF)) {
2913                 return;
2914         }
2915
2916         if (__rtl8169_get_wol(tp) & WAKE_ANY) {
2917                 rtl_writephy(tp, 0x1f, 0x0000);
2918                 rtl_writephy(tp, MII_BMCR, 0x0000);
2919
2920                 RTL_W32(RxConfig, RTL_R32(RxConfig) |
2921                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
2922                 return;
2923         }
2924
2925         r8168_phy_power_down(tp);
2926
2927         switch (tp->mac_version) {
2928         case RTL_GIGA_MAC_VER_25:
2929         case RTL_GIGA_MAC_VER_26:
2930                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
2931                 break;
2932         }
2933 }
2934
2935 static void r8168_pll_power_up(struct rtl8169_private *tp)
2936 {
2937         void __iomem *ioaddr = tp->mmio_addr;
2938
2939         if (tp->mac_version == RTL_GIGA_MAC_VER_27)
2940                 return;
2941
2942         switch (tp->mac_version) {
2943         case RTL_GIGA_MAC_VER_25:
2944         case RTL_GIGA_MAC_VER_26:
2945                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
2946                 break;
2947         }
2948
2949         r8168_phy_power_up(tp);
2950 }
2951
2952 static void rtl_pll_power_op(struct rtl8169_private *tp,
2953                              void (*op)(struct rtl8169_private *))
2954 {
2955         if (op)
2956                 op(tp);
2957 }
2958
2959 static void rtl_pll_power_down(struct rtl8169_private *tp)
2960 {
2961         rtl_pll_power_op(tp, tp->pll_power_ops.down);
2962 }
2963
2964 static void rtl_pll_power_up(struct rtl8169_private *tp)
2965 {
2966         rtl_pll_power_op(tp, tp->pll_power_ops.up);
2967 }
2968
2969 static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
2970 {
2971         struct pll_power_ops *ops = &tp->pll_power_ops;
2972
2973         switch (tp->mac_version) {
2974         case RTL_GIGA_MAC_VER_07:
2975         case RTL_GIGA_MAC_VER_08:
2976         case RTL_GIGA_MAC_VER_09:
2977         case RTL_GIGA_MAC_VER_10:
2978         case RTL_GIGA_MAC_VER_16:
2979         case RTL_GIGA_MAC_VER_29:
2980         case RTL_GIGA_MAC_VER_30:
2981                 ops->down       = r810x_pll_power_down;
2982                 ops->up         = r810x_pll_power_up;
2983                 break;
2984
2985         case RTL_GIGA_MAC_VER_11:
2986         case RTL_GIGA_MAC_VER_12:
2987         case RTL_GIGA_MAC_VER_17:
2988         case RTL_GIGA_MAC_VER_18:
2989         case RTL_GIGA_MAC_VER_19:
2990         case RTL_GIGA_MAC_VER_20:
2991         case RTL_GIGA_MAC_VER_21:
2992         case RTL_GIGA_MAC_VER_22:
2993         case RTL_GIGA_MAC_VER_23:
2994         case RTL_GIGA_MAC_VER_24:
2995         case RTL_GIGA_MAC_VER_25:
2996         case RTL_GIGA_MAC_VER_26:
2997         case RTL_GIGA_MAC_VER_27:
2998         case RTL_GIGA_MAC_VER_28:
2999                 ops->down       = r8168_pll_power_down;
3000                 ops->up         = r8168_pll_power_up;
3001                 break;
3002
3003         default:
3004                 ops->down       = NULL;
3005                 ops->up         = NULL;
3006                 break;
3007         }
3008 }
3009
3010 static int __devinit
3011 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3012 {
3013         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
3014         const unsigned int region = cfg->region;
3015         struct rtl8169_private *tp;
3016         struct mii_if_info *mii;
3017         struct net_device *dev;
3018         void __iomem *ioaddr;
3019         unsigned int i;
3020         int rc;
3021
3022         if (netif_msg_drv(&debug)) {
3023                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
3024                        MODULENAME, RTL8169_VERSION);
3025         }
3026
3027         dev = alloc_etherdev(sizeof (*tp));
3028         if (!dev) {
3029                 if (netif_msg_drv(&debug))
3030                         dev_err(&pdev->dev, "unable to alloc new ethernet\n");
3031                 rc = -ENOMEM;
3032                 goto out;
3033         }
3034
3035         SET_NETDEV_DEV(dev, &pdev->dev);
3036         dev->netdev_ops = &rtl8169_netdev_ops;
3037         tp = netdev_priv(dev);
3038         tp->dev = dev;
3039         tp->pci_dev = pdev;
3040         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
3041
3042         mii = &tp->mii;
3043         mii->dev = dev;
3044         mii->mdio_read = rtl_mdio_read;
3045         mii->mdio_write = rtl_mdio_write;
3046         mii->phy_id_mask = 0x1f;
3047         mii->reg_num_mask = 0x1f;
3048         mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3049
3050         /* enable device (incl. PCI PM wakeup and hotplug setup) */
3051         rc = pci_enable_device(pdev);
3052         if (rc < 0) {
3053                 netif_err(tp, probe, dev, "enable failure\n");
3054                 goto err_out_free_dev_1;
3055         }
3056
3057         if (pci_set_mwi(pdev) < 0)
3058                 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
3059
3060         /* make sure PCI base addr 1 is MMIO */
3061         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
3062                 netif_err(tp, probe, dev,
3063                           "region #%d not an MMIO resource, aborting\n",
3064                           region);
3065                 rc = -ENODEV;
3066                 goto err_out_mwi_2;
3067         }
3068
3069         /* check for weird/broken PCI region reporting */
3070         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
3071                 netif_err(tp, probe, dev,
3072                           "Invalid PCI region size(s), aborting\n");
3073                 rc = -ENODEV;
3074                 goto err_out_mwi_2;
3075         }
3076
3077         rc = pci_request_regions(pdev, MODULENAME);
3078         if (rc < 0) {
3079                 netif_err(tp, probe, dev, "could not request regions\n");
3080                 goto err_out_mwi_2;
3081         }
3082
3083         tp->cp_cmd = PCIMulRW | RxChkSum;
3084
3085         if ((sizeof(dma_addr_t) > 4) &&
3086             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
3087                 tp->cp_cmd |= PCIDAC;
3088                 dev->features |= NETIF_F_HIGHDMA;
3089         } else {
3090                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3091                 if (rc < 0) {
3092                         netif_err(tp, probe, dev, "DMA configuration failed\n");
3093                         goto err_out_free_res_3;
3094                 }
3095         }
3096
3097         /* ioremap MMIO region */
3098         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
3099         if (!ioaddr) {
3100                 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
3101                 rc = -EIO;
3102                 goto err_out_free_res_3;
3103         }
3104
3105         tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3106         if (!tp->pcie_cap)
3107                 netif_info(tp, probe, dev, "no PCI Express capability\n");
3108
3109         RTL_W16(IntrMask, 0x0000);
3110
3111         /* Soft reset the chip. */
3112         RTL_W8(ChipCmd, CmdReset);
3113
3114         /* Check that the chip has finished the reset. */
3115         for (i = 0; i < 100; i++) {
3116                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3117                         break;
3118                 msleep_interruptible(1);
3119         }
3120
3121         RTL_W16(IntrStatus, 0xffff);
3122
3123         pci_set_master(pdev);
3124
3125         /* Identify chip attached to board */
3126         rtl8169_get_mac_version(tp, ioaddr);
3127
3128         rtl_init_mdio_ops(tp);
3129         rtl_init_pll_power_ops(tp);
3130
3131         /* Use appropriate default if unknown */
3132         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
3133                 netif_notice(tp, probe, dev,
3134                              "unknown MAC, using family default\n");
3135                 tp->mac_version = cfg->default_ver;
3136         }
3137
3138         rtl8169_print_mac_version(tp);
3139
3140         for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
3141                 if (tp->mac_version == rtl_chip_info[i].mac_version)
3142                         break;
3143         }
3144         if (i == ARRAY_SIZE(rtl_chip_info)) {
3145                 dev_err(&pdev->dev,
3146                         "driver bug, MAC version not found in rtl_chip_info\n");
3147                 goto err_out_msi_4;
3148         }
3149         tp->chipset = i;
3150
3151         RTL_W8(Cfg9346, Cfg9346_Unlock);
3152         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3153         RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
3154         if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3155                 tp->features |= RTL_FEATURE_WOL;
3156         if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3157                 tp->features |= RTL_FEATURE_WOL;
3158         tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
3159         RTL_W8(Cfg9346, Cfg9346_Lock);
3160
3161         if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3162             (RTL_R8(PHYstatus) & TBI_Enable)) {
3163                 tp->set_speed = rtl8169_set_speed_tbi;
3164                 tp->get_settings = rtl8169_gset_tbi;
3165                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3166                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3167                 tp->link_ok = rtl8169_tbi_link_ok;
3168                 tp->do_ioctl = rtl_tbi_ioctl;
3169
3170                 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
3171         } else {
3172                 tp->set_speed = rtl8169_set_speed_xmii;
3173                 tp->get_settings = rtl8169_gset_xmii;
3174                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3175                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3176                 tp->link_ok = rtl8169_xmii_link_ok;
3177                 tp->do_ioctl = rtl_xmii_ioctl;
3178         }
3179
3180         spin_lock_init(&tp->lock);
3181
3182         tp->mmio_addr = ioaddr;
3183
3184         /* Get MAC address */
3185         for (i = 0; i < MAC_ADDR_LEN; i++)
3186                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
3187         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3188
3189         SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
3190         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3191         dev->irq = pdev->irq;
3192         dev->base_addr = (unsigned long) ioaddr;
3193
3194         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
3195
3196 #ifdef CONFIG_R8169_VLAN
3197         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3198 #endif
3199         dev->features |= NETIF_F_GRO;
3200
3201         tp->intr_mask = 0xffff;
3202         tp->hw_start = cfg->hw_start;
3203         tp->intr_event = cfg->intr_event;
3204         tp->napi_event = cfg->napi_event;
3205
3206         init_timer(&tp->timer);
3207         tp->timer.data = (unsigned long) dev;
3208         tp->timer.function = rtl8169_phy_timer;
3209
3210         rc = register_netdev(dev);
3211         if (rc < 0)
3212                 goto err_out_msi_4;
3213
3214         pci_set_drvdata(pdev, dev);
3215
3216         netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
3217                    rtl_chip_info[tp->chipset].name,
3218                    dev->base_addr, dev->dev_addr,
3219                    (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
3220
3221         if ((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
3222             (tp->mac_version == RTL_GIGA_MAC_VER_28)) {
3223                 rtl8168_driver_start(tp);
3224         }
3225
3226         device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
3227
3228         if (pci_dev_run_wake(pdev))
3229                 pm_runtime_put_noidle(&pdev->dev);
3230
3231         netif_carrier_off(dev);
3232
3233 out:
3234         return rc;
3235
3236 err_out_msi_4:
3237         rtl_disable_msi(pdev, tp);
3238         iounmap(ioaddr);
3239 err_out_free_res_3:
3240         pci_release_regions(pdev);
3241 err_out_mwi_2:
3242         pci_clear_mwi(pdev);
3243         pci_disable_device(pdev);
3244 err_out_free_dev_1:
3245         free_netdev(dev);
3246         goto out;
3247 }
3248
3249 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
3250 {
3251         struct net_device *dev = pci_get_drvdata(pdev);
3252         struct rtl8169_private *tp = netdev_priv(dev);
3253
3254         if ((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
3255             (tp->mac_version == RTL_GIGA_MAC_VER_28)) {
3256                 rtl8168_driver_stop(tp);
3257         }
3258
3259         cancel_delayed_work_sync(&tp->task);
3260
3261         rtl_release_firmware(tp);
3262
3263         unregister_netdev(dev);
3264
3265         if (pci_dev_run_wake(pdev))
3266                 pm_runtime_get_noresume(&pdev->dev);
3267
3268         /* restore original MAC address */
3269         rtl_rar_set(tp, dev->perm_addr);
3270
3271         rtl_disable_msi(pdev, tp);
3272         rtl8169_release_board(pdev, dev, tp->mmio_addr);
3273         pci_set_drvdata(pdev, NULL);
3274 }
3275
3276 static int rtl8169_open(struct net_device *dev)
3277 {
3278         struct rtl8169_private *tp = netdev_priv(dev);
3279         void __iomem *ioaddr = tp->mmio_addr;
3280         struct pci_dev *pdev = tp->pci_dev;
3281         int retval = -ENOMEM;
3282
3283         pm_runtime_get_sync(&pdev->dev);
3284
3285         /*
3286          * Rx and Tx desscriptors needs 256 bytes alignment.
3287          * dma_alloc_coherent provides more.
3288          */
3289         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
3290                                              &tp->TxPhyAddr, GFP_KERNEL);
3291         if (!tp->TxDescArray)
3292                 goto err_pm_runtime_put;
3293
3294         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
3295                                              &tp->RxPhyAddr, GFP_KERNEL);
3296         if (!tp->RxDescArray)
3297                 goto err_free_tx_0;
3298
3299         retval = rtl8169_init_ring(dev);
3300         if (retval < 0)
3301                 goto err_free_rx_1;
3302
3303         INIT_DELAYED_WORK(&tp->task, NULL);
3304
3305         smp_mb();
3306
3307         retval = request_irq(dev->irq, rtl8169_interrupt,
3308                              (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
3309                              dev->name, dev);
3310         if (retval < 0)
3311                 goto err_release_ring_2;
3312
3313         napi_enable(&tp->napi);
3314
3315         rtl8169_init_phy(dev, tp);
3316
3317         /*
3318          * Pretend we are using VLANs; This bypasses a nasty bug where
3319          * Interrupts stop flowing on high load on 8110SCd controllers.
3320          */
3321         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3322                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | RxVlan);
3323
3324         rtl_pll_power_up(tp);
3325
3326         rtl_hw_start(dev);
3327
3328         rtl8169_request_timer(dev);
3329
3330         tp->saved_wolopts = 0;
3331         pm_runtime_put_noidle(&pdev->dev);
3332
3333         rtl8169_check_link_status(dev, tp, ioaddr);
3334 out:
3335         return retval;
3336
3337 err_release_ring_2:
3338         rtl8169_rx_clear(tp);
3339 err_free_rx_1:
3340         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
3341                           tp->RxPhyAddr);
3342         tp->RxDescArray = NULL;
3343 err_free_tx_0:
3344         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
3345                           tp->TxPhyAddr);
3346         tp->TxDescArray = NULL;
3347 err_pm_runtime_put:
3348         pm_runtime_put_noidle(&pdev->dev);
3349         goto out;
3350 }
3351
3352 static void rtl8169_hw_reset(struct rtl8169_private *tp)
3353 {
3354         void __iomem *ioaddr = tp->mmio_addr;
3355
3356         /* Disable interrupts */
3357         rtl8169_irq_mask_and_ack(ioaddr);
3358
3359         if (tp->mac_version == RTL_GIGA_MAC_VER_28) {
3360                 while (RTL_R8(TxPoll) & NPQ)
3361                         udelay(20);
3362
3363         }
3364
3365         /* Reset the chipset */
3366         RTL_W8(ChipCmd, CmdReset);
3367
3368         /* PCI commit */
3369         RTL_R8(ChipCmd);
3370 }
3371
3372 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
3373 {
3374         void __iomem *ioaddr = tp->mmio_addr;
3375         u32 cfg = rtl8169_rx_config;
3376
3377         cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3378         RTL_W32(RxConfig, cfg);
3379
3380         /* Set DMA burst size and Interframe Gap Time */
3381         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3382                 (InterFrameGap << TxInterFrameGapShift));
3383 }
3384
3385 static void rtl_hw_start(struct net_device *dev)
3386 {
3387         struct rtl8169_private *tp = netdev_priv(dev);
3388         void __iomem *ioaddr = tp->mmio_addr;
3389         unsigned int i;
3390
3391         /* Soft reset the chip. */
3392         RTL_W8(ChipCmd, CmdReset);
3393
3394         /* Check that the chip has finished the reset. */
3395         for (i = 0; i < 100; i++) {
3396                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3397                         break;
3398                 msleep_interruptible(1);
3399         }
3400
3401         tp->hw_start(dev);
3402
3403         netif_start_queue(dev);
3404 }
3405
3406
3407 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3408                                          void __iomem *ioaddr)
3409 {
3410         /*
3411          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3412          * register to be written before TxDescAddrLow to work.
3413          * Switching from MMIO to I/O access fixes the issue as well.
3414          */
3415         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
3416         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
3417         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
3418         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
3419 }
3420
3421 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
3422 {
3423         u16 cmd;
3424
3425         cmd = RTL_R16(CPlusCmd);
3426         RTL_W16(CPlusCmd, cmd);
3427         return cmd;
3428 }
3429
3430 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
3431 {
3432         /* Low hurts. Let's disable the filtering. */
3433         RTL_W16(RxMaxSize, rx_buf_sz + 1);
3434 }
3435
3436 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
3437 {
3438         static const struct {
3439                 u32 mac_version;
3440                 u32 clk;
3441                 u32 val;
3442         } cfg2_info [] = {
3443                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
3444                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
3445                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
3446                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3447         }, *p = cfg2_info;
3448         unsigned int i;
3449         u32 clk;
3450
3451         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
3452         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
3453                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
3454                         RTL_W32(0x7c, p->val);
3455                         break;
3456                 }
3457         }
3458 }
3459
3460 static void rtl_hw_start_8169(struct net_device *dev)
3461 {
3462         struct rtl8169_private *tp = netdev_priv(dev);
3463         void __iomem *ioaddr = tp->mmio_addr;
3464         struct pci_dev *pdev = tp->pci_dev;
3465
3466         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
3467                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
3468                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
3469         }
3470
3471         RTL_W8(Cfg9346, Cfg9346_Unlock);
3472         if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3473             (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3474             (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3475             (tp->mac_version == RTL_GIGA_MAC_VER_04))
3476                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3477
3478         RTL_W8(EarlyTxThres, NoEarlyTx);
3479
3480         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
3481
3482         if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3483             (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3484             (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3485             (tp->mac_version == RTL_GIGA_MAC_VER_04))
3486                 rtl_set_rx_tx_config_registers(tp);
3487
3488         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3489
3490         if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3491             (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
3492                 dprintk("Set MAC Reg C+CR Offset 0xE0. "
3493                         "Bit-3 and bit-14 MUST be 1\n");
3494                 tp->cp_cmd |= (1 << 14);
3495         }
3496
3497         RTL_W16(CPlusCmd, tp->cp_cmd);
3498
3499         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
3500
3501         /*
3502          * Undocumented corner. Supposedly:
3503          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3504          */
3505         RTL_W16(IntrMitigate, 0x0000);
3506
3507         rtl_set_rx_tx_desc_registers(tp, ioaddr);
3508
3509         if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
3510             (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
3511             (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
3512             (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
3513                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3514                 rtl_set_rx_tx_config_registers(tp);
3515         }
3516
3517         RTL_W8(Cfg9346, Cfg9346_Lock);
3518
3519         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3520         RTL_R8(IntrMask);
3521
3522         RTL_W32(RxMissed, 0);
3523
3524         rtl_set_rx_mode(dev);
3525
3526         /* no early-rx interrupts */
3527         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
3528
3529         /* Enable all known interrupts by setting the interrupt mask. */
3530         RTL_W16(IntrMask, tp->intr_event);
3531 }
3532
3533 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
3534 {
3535         struct net_device *dev = pci_get_drvdata(pdev);
3536         struct rtl8169_private *tp = netdev_priv(dev);
3537         int cap = tp->pcie_cap;
3538
3539         if (cap) {
3540                 u16 ctl;
3541
3542                 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
3543                 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
3544                 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
3545         }
3546 }
3547
3548 static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
3549 {
3550         u32 csi;
3551
3552         csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
3553         rtl_csi_write(ioaddr, 0x070c, csi | bits);
3554 }
3555
3556 static void rtl_csi_access_enable_1(void __iomem *ioaddr)
3557 {
3558         rtl_csi_access_enable(ioaddr, 0x17000000);
3559 }
3560
3561 static void rtl_csi_access_enable_2(void __iomem *ioaddr)
3562 {
3563         rtl_csi_access_enable(ioaddr, 0x27000000);
3564 }
3565
3566 struct ephy_info {
3567         unsigned int offset;
3568         u16 mask;
3569         u16 bits;
3570 };
3571
3572 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
3573 {
3574         u16 w;
3575
3576         while (len-- > 0) {
3577                 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
3578                 rtl_ephy_write(ioaddr, e->offset, w);
3579                 e++;
3580         }
3581 }
3582
3583 static void rtl_disable_clock_request(struct pci_dev *pdev)
3584 {
3585         struct net_device *dev = pci_get_drvdata(pdev);
3586         struct rtl8169_private *tp = netdev_priv(dev);
3587         int cap = tp->pcie_cap;
3588
3589         if (cap) {
3590                 u16 ctl;
3591
3592                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3593                 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
3594                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3595         }
3596 }
3597
3598 static void rtl_enable_clock_request(struct pci_dev *pdev)
3599 {
3600         struct net_device *dev = pci_get_drvdata(pdev);
3601         struct rtl8169_private *tp = netdev_priv(dev);
3602         int cap = tp->pcie_cap;
3603
3604         if (cap) {
3605                 u16 ctl;
3606
3607                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3608                 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
3609                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3610         }
3611 }
3612
3613 #define R8168_CPCMD_QUIRK_MASK (\
3614         EnableBist | \
3615         Mac_dbgo_oe | \
3616         Force_half_dup | \
3617         Force_rxflow_en | \
3618         Force_txflow_en | \
3619         Cxpl_dbg_sel | \
3620         ASF | \
3621         PktCntrDisable | \
3622         Mac_dbgo_sel)
3623
3624 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
3625 {
3626         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3627
3628         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3629
3630         rtl_tx_performance_tweak(pdev,
3631                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3632 }
3633
3634 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
3635 {
3636         rtl_hw_start_8168bb(ioaddr, pdev);
3637
3638         RTL_W8(MaxTxPacketSize, TxPacketMax);
3639
3640         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
3641 }
3642
3643 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
3644 {
3645         RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
3646
3647         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3648
3649         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3650
3651         rtl_disable_clock_request(pdev);
3652
3653         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3654 }
3655
3656 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
3657 {
3658         static const struct ephy_info e_info_8168cp[] = {
3659                 { 0x01, 0,      0x0001 },
3660                 { 0x02, 0x0800, 0x1000 },
3661                 { 0x03, 0,      0x0042 },
3662                 { 0x06, 0x0080, 0x0000 },
3663                 { 0x07, 0,      0x2000 }
3664         };
3665
3666         rtl_csi_access_enable_2(ioaddr);
3667
3668         rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
3669
3670         __rtl_hw_start_8168cp(ioaddr, pdev);
3671 }
3672
3673 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
3674 {
3675         rtl_csi_access_enable_2(ioaddr);
3676
3677         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3678
3679         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3680
3681         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3682 }
3683
3684 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
3685 {
3686         rtl_csi_access_enable_2(ioaddr);
3687
3688         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3689
3690         /* Magic. */
3691         RTL_W8(DBG_REG, 0x20);
3692
3693         RTL_W8(MaxTxPacketSize, TxPacketMax);
3694
3695         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3696
3697         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3698 }
3699
3700 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
3701 {
3702         static const struct ephy_info e_info_8168c_1[] = {
3703                 { 0x02, 0x0800, 0x1000 },
3704                 { 0x03, 0,      0x0002 },
3705                 { 0x06, 0x0080, 0x0000 }
3706         };
3707
3708         rtl_csi_access_enable_2(ioaddr);
3709
3710         RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
3711
3712         rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
3713
3714         __rtl_hw_start_8168cp(ioaddr, pdev);
3715 }
3716
3717 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
3718 {
3719         static const struct ephy_info e_info_8168c_2[] = {
3720                 { 0x01, 0,      0x0001 },
3721                 { 0x03, 0x0400, 0x0220 }
3722         };
3723
3724         rtl_csi_access_enable_2(ioaddr);
3725
3726         rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
3727
3728         __rtl_hw_start_8168cp(ioaddr, pdev);
3729 }
3730
3731 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
3732 {
3733         rtl_hw_start_8168c_2(ioaddr, pdev);
3734 }
3735
3736 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
3737 {
3738         rtl_csi_access_enable_2(ioaddr);
3739
3740         __rtl_hw_start_8168cp(ioaddr, pdev);
3741 }
3742
3743 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
3744 {
3745         rtl_csi_access_enable_2(ioaddr);
3746
3747         rtl_disable_clock_request(pdev);
3748
3749         RTL_W8(MaxTxPacketSize, TxPacketMax);
3750
3751         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3752
3753         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3754 }
3755
3756 static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
3757 {
3758         static const struct ephy_info e_info_8168d_4[] = {
3759                 { 0x0b, ~0,     0x48 },
3760                 { 0x19, 0x20,   0x50 },
3761                 { 0x0c, ~0,     0x20 }
3762         };
3763         int i;
3764
3765         rtl_csi_access_enable_1(ioaddr);
3766
3767         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3768
3769         RTL_W8(MaxTxPacketSize, TxPacketMax);
3770
3771         for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
3772                 const struct ephy_info *e = e_info_8168d_4 + i;
3773                 u16 w;
3774
3775                 w = rtl_ephy_read(ioaddr, e->offset);
3776                 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
3777         }
3778
3779         rtl_enable_clock_request(pdev);
3780 }
3781
3782 static void rtl_hw_start_8168(struct net_device *dev)
3783 {
3784         struct rtl8169_private *tp = netdev_priv(dev);
3785         void __iomem *ioaddr = tp->mmio_addr;
3786         struct pci_dev *pdev = tp->pci_dev;
3787
3788         RTL_W8(Cfg9346, Cfg9346_Unlock);
3789
3790         RTL_W8(MaxTxPacketSize, TxPacketMax);
3791
3792         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
3793
3794         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
3795
3796         RTL_W16(CPlusCmd, tp->cp_cmd);
3797
3798         RTL_W16(IntrMitigate, 0x5151);
3799
3800         /* Work around for RxFIFO overflow. */
3801         if (tp->mac_version == RTL_GIGA_MAC_VER_11 ||
3802             tp->mac_version == RTL_GIGA_MAC_VER_22) {
3803                 tp->intr_event |= RxFIFOOver | PCSTimeout;
3804                 tp->intr_event &= ~RxOverflow;
3805         }
3806
3807         rtl_set_rx_tx_desc_registers(tp, ioaddr);
3808
3809         rtl_set_rx_mode(dev);
3810
3811         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3812                 (InterFrameGap << TxInterFrameGapShift));
3813
3814         RTL_R8(IntrMask);
3815
3816         switch (tp->mac_version) {
3817         case RTL_GIGA_MAC_VER_11:
3818                 rtl_hw_start_8168bb(ioaddr, pdev);
3819         break;
3820
3821         case RTL_GIGA_MAC_VER_12:
3822         case RTL_GIGA_MAC_VER_17:
3823                 rtl_hw_start_8168bef(ioaddr, pdev);
3824         break;
3825
3826         case RTL_GIGA_MAC_VER_18:
3827                 rtl_hw_start_8168cp_1(ioaddr, pdev);
3828         break;
3829
3830         case RTL_GIGA_MAC_VER_19:
3831                 rtl_hw_start_8168c_1(ioaddr, pdev);
3832         break;
3833
3834         case RTL_GIGA_MAC_VER_20:
3835                 rtl_hw_start_8168c_2(ioaddr, pdev);
3836         break;
3837
3838         case RTL_GIGA_MAC_VER_21:
3839                 rtl_hw_start_8168c_3(ioaddr, pdev);
3840         break;
3841
3842         case RTL_GIGA_MAC_VER_22:
3843                 rtl_hw_start_8168c_4(ioaddr, pdev);
3844         break;
3845
3846         case RTL_GIGA_MAC_VER_23:
3847                 rtl_hw_start_8168cp_2(ioaddr, pdev);
3848         break;
3849
3850         case RTL_GIGA_MAC_VER_24:
3851                 rtl_hw_start_8168cp_3(ioaddr, pdev);
3852         break;
3853
3854         case RTL_GIGA_MAC_VER_25:
3855         case RTL_GIGA_MAC_VER_26:
3856         case RTL_GIGA_MAC_VER_27:
3857                 rtl_hw_start_8168d(ioaddr, pdev);
3858         break;
3859
3860         case RTL_GIGA_MAC_VER_28:
3861                 rtl_hw_start_8168d_4(ioaddr, pdev);
3862         break;
3863
3864         default:
3865                 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
3866                         dev->name, tp->mac_version);
3867         break;
3868         }
3869
3870         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3871
3872         RTL_W8(Cfg9346, Cfg9346_Lock);
3873
3874         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
3875
3876         RTL_W16(IntrMask, tp->intr_event);
3877 }
3878
3879 #define R810X_CPCMD_QUIRK_MASK (\
3880         EnableBist | \
3881         Mac_dbgo_oe | \
3882         Force_half_dup | \
3883         Force_rxflow_en | \
3884         Force_txflow_en | \
3885         Cxpl_dbg_sel | \
3886         ASF | \
3887         PktCntrDisable | \
3888         PCIDAC | \
3889         PCIMulRW)
3890
3891 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
3892 {
3893         static const struct ephy_info e_info_8102e_1[] = {
3894                 { 0x01, 0, 0x6e65 },
3895                 { 0x02, 0, 0x091f },
3896                 { 0x03, 0, 0xc2f9 },
3897                 { 0x06, 0, 0xafb5 },
3898                 { 0x07, 0, 0x0e00 },
3899                 { 0x19, 0, 0xec80 },
3900                 { 0x01, 0, 0x2e65 },
3901                 { 0x01, 0, 0x6e65 }
3902         };
3903         u8 cfg1;
3904
3905         rtl_csi_access_enable_2(ioaddr);
3906
3907         RTL_W8(DBG_REG, FIX_NAK_1);
3908
3909         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3910
3911         RTL_W8(Config1,
3912                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
3913         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3914
3915         cfg1 = RTL_R8(Config1);
3916         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
3917                 RTL_W8(Config1, cfg1 & ~LEDS0);
3918
3919         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3920
3921         rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
3922 }
3923
3924 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
3925 {
3926         rtl_csi_access_enable_2(ioaddr);
3927
3928         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3929
3930         RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
3931         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3932
3933         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3934 }
3935
3936 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
3937 {
3938         rtl_hw_start_8102e_2(ioaddr, pdev);
3939
3940         rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
3941 }
3942
3943 static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
3944 {
3945         static const struct ephy_info e_info_8105e_1[] = {
3946                 { 0x07, 0, 0x4000 },
3947                 { 0x19, 0, 0x0200 },
3948                 { 0x19, 0, 0x0020 },
3949                 { 0x1e, 0, 0x2000 },
3950                 { 0x03, 0, 0x0001 },
3951                 { 0x19, 0, 0x0100 },
3952                 { 0x19, 0, 0x0004 },
3953                 { 0x0a, 0, 0x0020 }
3954         };
3955
3956         /* Force LAN exit from ASPM if Rx/Tx are not idel */
3957         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
3958
3959         /* disable Early Tally Counter */
3960         RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
3961
3962         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
3963         RTL_W8(DLLPR, RTL_R8(DLLPR) | PM_SWITCH);
3964
3965         rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
3966 }
3967
3968 static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
3969 {
3970         rtl_hw_start_8105e_1(ioaddr, pdev);
3971         rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
3972 }
3973
3974 static void rtl_hw_start_8101(struct net_device *dev)
3975 {
3976         struct rtl8169_private *tp = netdev_priv(dev);
3977         void __iomem *ioaddr = tp->mmio_addr;
3978         struct pci_dev *pdev = tp->pci_dev;
3979
3980         if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
3981             (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
3982                 int cap = tp->pcie_cap;
3983
3984                 if (cap) {
3985                         pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
3986                                               PCI_EXP_DEVCTL_NOSNOOP_EN);
3987                 }
3988         }
3989
3990         switch (tp->mac_version) {
3991         case RTL_GIGA_MAC_VER_07:
3992                 rtl_hw_start_8102e_1(ioaddr, pdev);
3993                 break;
3994
3995         case RTL_GIGA_MAC_VER_08:
3996                 rtl_hw_start_8102e_3(ioaddr, pdev);
3997                 break;
3998
3999         case RTL_GIGA_MAC_VER_09:
4000                 rtl_hw_start_8102e_2(ioaddr, pdev);
4001                 break;
4002
4003         case RTL_GIGA_MAC_VER_29:
4004                 rtl_hw_start_8105e_1(ioaddr, pdev);
4005                 break;
4006         case RTL_GIGA_MAC_VER_30:
4007                 rtl_hw_start_8105e_2(ioaddr, pdev);
4008                 break;
4009         }
4010
4011         RTL_W8(Cfg9346, Cfg9346_Unlock);
4012
4013         RTL_W8(MaxTxPacketSize, TxPacketMax);
4014
4015         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4016
4017         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
4018
4019         RTL_W16(CPlusCmd, tp->cp_cmd);
4020
4021         RTL_W16(IntrMitigate, 0x0000);
4022
4023         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4024
4025         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4026         rtl_set_rx_tx_config_registers(tp);
4027
4028         RTL_W8(Cfg9346, Cfg9346_Lock);
4029
4030         RTL_R8(IntrMask);
4031
4032         rtl_set_rx_mode(dev);
4033
4034         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4035
4036         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
4037
4038         RTL_W16(IntrMask, tp->intr_event);
4039 }
4040
4041 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
4042 {
4043         if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
4044                 return -EINVAL;
4045
4046         dev->mtu = new_mtu;
4047         return 0;
4048 }
4049
4050 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
4051 {
4052         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
4053         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
4054 }
4055
4056 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
4057                                      void **data_buff, struct RxDesc *desc)
4058 {
4059         dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
4060                          DMA_FROM_DEVICE);
4061
4062         kfree(*data_buff);
4063         *data_buff = NULL;
4064         rtl8169_make_unusable_by_asic(desc);
4065 }
4066
4067 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
4068 {
4069         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
4070
4071         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
4072 }
4073
4074 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
4075                                        u32 rx_buf_sz)
4076 {
4077         desc->addr = cpu_to_le64(mapping);
4078         wmb();
4079         rtl8169_mark_to_asic(desc, rx_buf_sz);
4080 }
4081
4082 static inline void *rtl8169_align(void *data)
4083 {
4084         return (void *)ALIGN((long)data, 16);
4085 }
4086
4087 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
4088                                              struct RxDesc *desc)
4089 {
4090         void *data;
4091         dma_addr_t mapping;
4092         struct device *d = &tp->pci_dev->dev;
4093         struct net_device *dev = tp->dev;
4094         int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
4095
4096         data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
4097         if (!data)
4098                 return NULL;
4099
4100         if (rtl8169_align(data) != data) {
4101                 kfree(data);
4102                 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
4103                 if (!data)
4104                         return NULL;
4105         }
4106
4107         mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
4108                                  DMA_FROM_DEVICE);
4109         if (unlikely(dma_mapping_error(d, mapping))) {
4110                 if (net_ratelimit())
4111                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
4112                 goto err_out;
4113         }
4114
4115         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
4116         return data;
4117
4118 err_out:
4119         kfree(data);
4120         return NULL;
4121 }
4122
4123 static void rtl8169_rx_clear(struct rtl8169_private *tp)
4124 {
4125         unsigned int i;
4126
4127         for (i = 0; i < NUM_RX_DESC; i++) {
4128                 if (tp->Rx_databuff[i]) {
4129                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
4130                                             tp->RxDescArray + i);
4131                 }
4132         }
4133 }
4134
4135 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
4136 {
4137         desc->opts1 |= cpu_to_le32(RingEnd);
4138 }
4139
4140 static int rtl8169_rx_fill(struct rtl8169_private *tp)
4141 {
4142         unsigned int i;
4143
4144         for (i = 0; i < NUM_RX_DESC; i++) {
4145                 void *data;
4146
4147                 if (tp->Rx_databuff[i])
4148                         continue;
4149
4150                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
4151                 if (!data) {
4152                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
4153                         goto err_out;
4154                 }
4155                 tp->Rx_databuff[i] = data;
4156         }
4157
4158         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4159         return 0;
4160
4161 err_out:
4162         rtl8169_rx_clear(tp);
4163         return -ENOMEM;
4164 }
4165
4166 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4167 {
4168         tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
4169 }
4170
4171 static int rtl8169_init_ring(struct net_device *dev)
4172 {
4173         struct rtl8169_private *tp = netdev_priv(dev);
4174
4175         rtl8169_init_ring_indexes(tp);
4176
4177         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
4178         memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
4179
4180         return rtl8169_rx_fill(tp);
4181 }
4182
4183 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
4184                                  struct TxDesc *desc)
4185 {
4186         unsigned int len = tx_skb->len;
4187
4188         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
4189
4190         desc->opts1 = 0x00;
4191         desc->opts2 = 0x00;
4192         desc->addr = 0x00;
4193         tx_skb->len = 0;
4194 }
4195
4196 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4197                                    unsigned int n)
4198 {
4199         unsigned int i;
4200
4201         for (i = 0; i < n; i++) {
4202                 unsigned int entry = (start + i) % NUM_TX_DESC;
4203                 struct ring_info *tx_skb = tp->tx_skb + entry;
4204                 unsigned int len = tx_skb->len;
4205
4206                 if (len) {
4207                         struct sk_buff *skb = tx_skb->skb;
4208
4209                         rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4210                                              tp->TxDescArray + entry);
4211                         if (skb) {
4212                                 tp->dev->stats.tx_dropped++;
4213                                 dev_kfree_skb(skb);
4214                                 tx_skb->skb = NULL;
4215                         }
4216                 }
4217         }
4218 }
4219
4220 static void rtl8169_tx_clear(struct rtl8169_private *tp)
4221 {
4222         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
4223         tp->cur_tx = tp->dirty_tx = 0;
4224 }
4225
4226 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
4227 {
4228         struct rtl8169_private *tp = netdev_priv(dev);
4229
4230         PREPARE_DELAYED_WORK(&tp->task, task);
4231         schedule_delayed_work(&tp->task, 4);
4232 }
4233
4234 static void rtl8169_wait_for_quiescence(struct net_device *dev)
4235 {
4236         struct rtl8169_private *tp = netdev_priv(dev);
4237         void __iomem *ioaddr = tp->mmio_addr;
4238
4239         synchronize_irq(dev->irq);
4240
4241         /* Wait for any pending NAPI task to complete */
4242         napi_disable(&tp->napi);
4243
4244         rtl8169_irq_mask_and_ack(ioaddr);
4245
4246         tp->intr_mask = 0xffff;
4247         RTL_W16(IntrMask, tp->intr_event);
4248         napi_enable(&tp->napi);
4249 }
4250
4251 static void rtl8169_reinit_task(struct work_struct *work)
4252 {
4253         struct rtl8169_private *tp =
4254                 container_of(work, struct rtl8169_private, task.work);
4255         struct net_device *dev = tp->dev;
4256         int ret;
4257
4258         rtnl_lock();
4259
4260         if (!netif_running(dev))
4261                 goto out_unlock;
4262
4263         rtl8169_wait_for_quiescence(dev);
4264         rtl8169_close(dev);
4265
4266         ret = rtl8169_open(dev);
4267         if (unlikely(ret < 0)) {
4268                 if (net_ratelimit())
4269                         netif_err(tp, drv, dev,
4270                                   "reinit failure (status = %d). Rescheduling\n",
4271                                   ret);
4272                 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4273         }
4274
4275 out_unlock:
4276         rtnl_unlock();
4277 }
4278
4279 static void rtl8169_reset_task(struct work_struct *work)
4280 {
4281         struct rtl8169_private *tp =
4282                 container_of(work, struct rtl8169_private, task.work);
4283         struct net_device *dev = tp->dev;
4284
4285         rtnl_lock();
4286
4287         if (!netif_running(dev))
4288                 goto out_unlock;
4289
4290         rtl8169_wait_for_quiescence(dev);
4291
4292         rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
4293         rtl8169_tx_clear(tp);
4294
4295         if (tp->dirty_rx == tp->cur_rx) {
4296                 rtl8169_init_ring_indexes(tp);
4297                 rtl_hw_start(dev);
4298                 netif_wake_queue(dev);
4299                 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
4300         } else {
4301                 if (net_ratelimit())
4302                         netif_emerg(tp, intr, dev, "Rx buffers shortage\n");
4303                 rtl8169_schedule_work(dev, rtl8169_reset_task);
4304         }
4305
4306 out_unlock:
4307         rtnl_unlock();
4308 }
4309
4310 static void rtl8169_tx_timeout(struct net_device *dev)
4311 {
4312         struct rtl8169_private *tp = netdev_priv(dev);
4313
4314         rtl8169_hw_reset(tp);
4315
4316         /* Let's wait a bit while any (async) irq lands on */
4317         rtl8169_schedule_work(dev, rtl8169_reset_task);
4318 }
4319
4320 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4321                               u32 opts1)
4322 {
4323         struct skb_shared_info *info = skb_shinfo(skb);
4324         unsigned int cur_frag, entry;
4325         struct TxDesc * uninitialized_var(txd);
4326         struct device *d = &tp->pci_dev->dev;
4327
4328         entry = tp->cur_tx;
4329         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4330                 skb_frag_t *frag = info->frags + cur_frag;
4331                 dma_addr_t mapping;
4332                 u32 status, len;
4333                 void *addr;
4334
4335                 entry = (entry + 1) % NUM_TX_DESC;
4336
4337                 txd = tp->TxDescArray + entry;
4338                 len = frag->size;
4339                 addr = ((void *) page_address(frag->page)) + frag->page_offset;
4340                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
4341                 if (unlikely(dma_mapping_error(d, mapping))) {
4342                         if (net_ratelimit())
4343                                 netif_err(tp, drv, tp->dev,
4344                                           "Failed to map TX fragments DMA!\n");
4345                         goto err_out;
4346                 }
4347
4348                 /* anti gcc 2.95.3 bugware (sic) */
4349                 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4350
4351                 txd->opts1 = cpu_to_le32(status);
4352                 txd->addr = cpu_to_le64(mapping);
4353
4354                 tp->tx_skb[entry].len = len;
4355         }
4356
4357         if (cur_frag) {
4358                 tp->tx_skb[entry].skb = skb;
4359                 txd->opts1 |= cpu_to_le32(LastFrag);
4360         }
4361
4362         return cur_frag;
4363
4364 err_out:
4365         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4366         return -EIO;
4367 }
4368
4369 static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
4370 {
4371         if (dev->features & NETIF_F_TSO) {
4372                 u32 mss = skb_shinfo(skb)->gso_size;
4373
4374                 if (mss)
4375                         return LargeSend | ((mss & MSSMask) << MSSShift);
4376         }
4377         if (skb->ip_summed == CHECKSUM_PARTIAL) {
4378                 const struct iphdr *ip = ip_hdr(skb);
4379
4380                 if (ip->protocol == IPPROTO_TCP)
4381                         return IPCS | TCPCS;
4382                 else if (ip->protocol == IPPROTO_UDP)
4383                         return IPCS | UDPCS;
4384                 WARN_ON(1);     /* we need a WARN() */
4385         }
4386         return 0;
4387 }
4388
4389 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4390                                       struct net_device *dev)
4391 {
4392         struct rtl8169_private *tp = netdev_priv(dev);
4393         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
4394         struct TxDesc *txd = tp->TxDescArray + entry;
4395         void __iomem *ioaddr = tp->mmio_addr;
4396         struct device *d = &tp->pci_dev->dev;
4397         dma_addr_t mapping;
4398         u32 status, len;
4399         u32 opts1;
4400         int frags;
4401
4402         if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
4403                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
4404                 goto err_stop_0;
4405         }
4406
4407         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
4408                 goto err_stop_0;
4409
4410         len = skb_headlen(skb);
4411         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
4412         if (unlikely(dma_mapping_error(d, mapping))) {
4413                 if (net_ratelimit())
4414                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
4415                 goto err_dma_0;
4416         }
4417
4418         tp->tx_skb[entry].len = len;
4419         txd->addr = cpu_to_le64(mapping);
4420         txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
4421
4422         opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
4423
4424         frags = rtl8169_xmit_frags(tp, skb, opts1);
4425         if (frags < 0)
4426                 goto err_dma_1;
4427         else if (frags)
4428                 opts1 |= FirstFrag;
4429         else {
4430                 opts1 |= FirstFrag | LastFrag;
4431                 tp->tx_skb[entry].skb = skb;
4432         }
4433
4434         wmb();
4435
4436         /* anti gcc 2.95.3 bugware (sic) */
4437         status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4438         txd->opts1 = cpu_to_le32(status);
4439
4440         tp->cur_tx += frags + 1;
4441
4442         wmb();
4443
4444         RTL_W8(TxPoll, NPQ);    /* set polling bit */
4445
4446         if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
4447                 netif_stop_queue(dev);
4448                 smp_rmb();
4449                 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
4450                         netif_wake_queue(dev);
4451         }
4452
4453         return NETDEV_TX_OK;
4454
4455 err_dma_1:
4456         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
4457 err_dma_0:
4458         dev_kfree_skb(skb);
4459         dev->stats.tx_dropped++;
4460         return NETDEV_TX_OK;
4461
4462 err_stop_0:
4463         netif_stop_queue(dev);
4464         dev->stats.tx_dropped++;
4465         return NETDEV_TX_BUSY;
4466 }
4467
4468 static void rtl8169_pcierr_interrupt(struct net_device *dev)
4469 {
4470         struct rtl8169_private *tp = netdev_priv(dev);
4471         struct pci_dev *pdev = tp->pci_dev;
4472         u16 pci_status, pci_cmd;
4473
4474         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4475         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
4476
4477         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
4478                   pci_cmd, pci_status);
4479
4480         /*
4481          * The recovery sequence below admits a very elaborated explanation:
4482          * - it seems to work;
4483          * - I did not see what else could be done;
4484          * - it makes iop3xx happy.
4485          *
4486          * Feel free to adjust to your needs.
4487          */
4488         if (pdev->broken_parity_status)
4489                 pci_cmd &= ~PCI_COMMAND_PARITY;
4490         else
4491                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
4492
4493         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
4494
4495         pci_write_config_word(pdev, PCI_STATUS,
4496                 pci_status & (PCI_STATUS_DETECTED_PARITY |
4497                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
4498                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
4499
4500         /* The infamous DAC f*ckup only happens at boot time */
4501         if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
4502                 void __iomem *ioaddr = tp->mmio_addr;
4503
4504                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
4505                 tp->cp_cmd &= ~PCIDAC;
4506                 RTL_W16(CPlusCmd, tp->cp_cmd);
4507                 dev->features &= ~NETIF_F_HIGHDMA;
4508         }
4509
4510         rtl8169_hw_reset(tp);
4511
4512         rtl8169_schedule_work(dev, rtl8169_reinit_task);
4513 }
4514
4515 static void rtl8169_tx_interrupt(struct net_device *dev,
4516                                  struct rtl8169_private *tp,
4517                                  void __iomem *ioaddr)
4518 {
4519         unsigned int dirty_tx, tx_left;
4520
4521         dirty_tx = tp->dirty_tx;
4522         smp_rmb();
4523         tx_left = tp->cur_tx - dirty_tx;
4524
4525         while (tx_left > 0) {
4526                 unsigned int entry = dirty_tx % NUM_TX_DESC;
4527                 struct ring_info *tx_skb = tp->tx_skb + entry;
4528                 u32 status;
4529
4530                 rmb();
4531                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4532                 if (status & DescOwn)
4533                         break;
4534
4535                 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4536                                      tp->TxDescArray + entry);
4537                 if (status & LastFrag) {
4538                         dev->stats.tx_packets++;
4539                         dev->stats.tx_bytes += tx_skb->skb->len;
4540                         dev_kfree_skb(tx_skb->skb);
4541                         tx_skb->skb = NULL;
4542                 }
4543                 dirty_tx++;
4544                 tx_left--;
4545         }
4546
4547         if (tp->dirty_tx != dirty_tx) {
4548                 tp->dirty_tx = dirty_tx;
4549                 smp_wmb();
4550                 if (netif_queue_stopped(dev) &&
4551                     (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
4552                         netif_wake_queue(dev);
4553                 }
4554                 /*
4555                  * 8168 hack: TxPoll requests are lost when the Tx packets are
4556                  * too close. Let's kick an extra TxPoll request when a burst
4557                  * of start_xmit activity is detected (if it is not detected,
4558                  * it is slow enough). -- FR
4559                  */
4560                 smp_rmb();
4561                 if (tp->cur_tx != dirty_tx)
4562                         RTL_W8(TxPoll, NPQ);
4563         }
4564 }
4565
4566 static inline int rtl8169_fragmented_frame(u32 status)
4567 {
4568         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4569 }
4570
4571 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
4572 {
4573         u32 status = opts1 & RxProtoMask;
4574
4575         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
4576             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
4577                 skb->ip_summed = CHECKSUM_UNNECESSARY;
4578         else
4579                 skb_checksum_none_assert(skb);
4580 }
4581
4582 static struct sk_buff *rtl8169_try_rx_copy(void *data,
4583                                            struct rtl8169_private *tp,
4584                                            int pkt_size,
4585                                            dma_addr_t addr)
4586 {
4587         struct sk_buff *skb;
4588         struct device *d = &tp->pci_dev->dev;
4589
4590         data = rtl8169_align(data);
4591         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
4592         prefetch(data);
4593         skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
4594         if (skb)
4595                 memcpy(skb->data, data, pkt_size);
4596         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
4597
4598         return skb;
4599 }
4600
4601 /*
4602  * Warning : rtl8169_rx_interrupt() might be called :
4603  * 1) from NAPI (softirq) context
4604  *      (polling = 1 : we should call netif_receive_skb())
4605  * 2) from process context (rtl8169_reset_task())
4606  *      (polling = 0 : we must call netif_rx() instead)
4607  */
4608 static int rtl8169_rx_interrupt(struct net_device *dev,
4609                                 struct rtl8169_private *tp,
4610                                 void __iomem *ioaddr, u32 budget)
4611 {
4612         unsigned int cur_rx, rx_left;
4613         unsigned int count;
4614         int polling = (budget != ~(u32)0) ? 1 : 0;
4615
4616         cur_rx = tp->cur_rx;
4617         rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
4618         rx_left = min(rx_left, budget);
4619
4620         for (; rx_left > 0; rx_left--, cur_rx++) {
4621                 unsigned int entry = cur_rx % NUM_RX_DESC;
4622                 struct RxDesc *desc = tp->RxDescArray + entry;
4623                 u32 status;
4624
4625                 rmb();
4626                 status = le32_to_cpu(desc->opts1);
4627
4628                 if (status & DescOwn)
4629                         break;
4630                 if (unlikely(status & RxRES)) {
4631                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
4632                                    status);
4633                         dev->stats.rx_errors++;
4634                         if (status & (RxRWT | RxRUNT))
4635                                 dev->stats.rx_length_errors++;
4636                         if (status & RxCRC)
4637                                 dev->stats.rx_crc_errors++;
4638                         if (status & RxFOVF) {
4639                                 rtl8169_schedule_work(dev, rtl8169_reset_task);
4640                                 dev->stats.rx_fifo_errors++;
4641                         }
4642                         rtl8169_mark_to_asic(desc, rx_buf_sz);
4643                 } else {
4644                         struct sk_buff *skb;
4645                         dma_addr_t addr = le64_to_cpu(desc->addr);
4646                         int pkt_size = (status & 0x00001FFF) - 4;
4647
4648                         /*
4649                          * The driver does not support incoming fragmented
4650                          * frames. They are seen as a symptom of over-mtu
4651                          * sized frames.
4652                          */
4653                         if (unlikely(rtl8169_fragmented_frame(status))) {
4654                                 dev->stats.rx_dropped++;
4655                                 dev->stats.rx_length_errors++;
4656                                 rtl8169_mark_to_asic(desc, rx_buf_sz);
4657                                 continue;
4658                         }
4659
4660                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
4661                                                   tp, pkt_size, addr);
4662                         rtl8169_mark_to_asic(desc, rx_buf_sz);
4663                         if (!skb) {
4664                                 dev->stats.rx_dropped++;
4665                                 continue;
4666                         }
4667
4668                         rtl8169_rx_csum(skb, status);
4669                         skb_put(skb, pkt_size);
4670                         skb->protocol = eth_type_trans(skb, dev);
4671
4672                         if (rtl8169_rx_vlan_skb(tp, desc, skb, polling) < 0) {
4673                                 if (likely(polling))
4674                                         napi_gro_receive(&tp->napi, skb);
4675                                 else
4676                                         netif_rx(skb);
4677                         }
4678
4679                         dev->stats.rx_bytes += pkt_size;
4680                         dev->stats.rx_packets++;
4681                 }
4682
4683                 /* Work around for AMD plateform. */
4684                 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
4685                     (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
4686                         desc->opts2 = 0;
4687                         cur_rx++;
4688                 }
4689         }
4690
4691         count = cur_rx - tp->cur_rx;
4692         tp->cur_rx = cur_rx;
4693
4694         tp->dirty_rx += count;
4695
4696         return count;
4697 }
4698
4699 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
4700 {
4701         struct net_device *dev = dev_instance;
4702         struct rtl8169_private *tp = netdev_priv(dev);
4703         void __iomem *ioaddr = tp->mmio_addr;
4704         int handled = 0;
4705         int status;
4706
4707         /* loop handling interrupts until we have no new ones or
4708          * we hit a invalid/hotplug case.
4709          */
4710         status = RTL_R16(IntrStatus);
4711         while (status && status != 0xffff) {
4712                 handled = 1;
4713
4714                 /* Handle all of the error cases first. These will reset
4715                  * the chip, so just exit the loop.
4716                  */
4717                 if (unlikely(!netif_running(dev))) {
4718                         rtl8169_asic_down(ioaddr);
4719                         break;
4720                 }
4721
4722                 if (unlikely(status & RxFIFOOver)) {
4723                         switch (tp->mac_version) {
4724                         /* Work around for rx fifo overflow */
4725                         case RTL_GIGA_MAC_VER_11:
4726                         case RTL_GIGA_MAC_VER_22:
4727                         case RTL_GIGA_MAC_VER_26:
4728                                 netif_stop_queue(dev);
4729                                 rtl8169_tx_timeout(dev);
4730                                 goto done;
4731                         /* Testers needed. */
4732                         case RTL_GIGA_MAC_VER_17:
4733                         case RTL_GIGA_MAC_VER_19:
4734                         case RTL_GIGA_MAC_VER_20:
4735                         case RTL_GIGA_MAC_VER_21:
4736                         case RTL_GIGA_MAC_VER_23:
4737                         case RTL_GIGA_MAC_VER_24:
4738                         case RTL_GIGA_MAC_VER_27:
4739                         case RTL_GIGA_MAC_VER_28:
4740                         /* Experimental science. Pktgen proof. */
4741                         case RTL_GIGA_MAC_VER_12:
4742                         case RTL_GIGA_MAC_VER_25:
4743                                 if (status == RxFIFOOver)
4744                                         goto done;
4745                                 break;
4746                         default:
4747                                 break;
4748                         }
4749                 }
4750
4751                 if (unlikely(status & SYSErr)) {
4752                         rtl8169_pcierr_interrupt(dev);
4753                         break;
4754                 }
4755
4756                 if (status & LinkChg)
4757                         __rtl8169_check_link_status(dev, tp, ioaddr, true);
4758
4759                 /* We need to see the lastest version of tp->intr_mask to
4760                  * avoid ignoring an MSI interrupt and having to wait for
4761                  * another event which may never come.
4762                  */
4763                 smp_rmb();
4764                 if (status & tp->intr_mask & tp->napi_event) {
4765                         RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
4766                         tp->intr_mask = ~tp->napi_event;
4767
4768                         if (likely(napi_schedule_prep(&tp->napi)))
4769                                 __napi_schedule(&tp->napi);
4770                         else
4771                                 netif_info(tp, intr, dev,
4772                                            "interrupt %04x in poll\n", status);
4773                 }
4774
4775                 /* We only get a new MSI interrupt when all active irq
4776                  * sources on the chip have been acknowledged. So, ack
4777                  * everything we've seen and check if new sources have become
4778                  * active to avoid blocking all interrupts from the chip.
4779                  */
4780                 RTL_W16(IntrStatus,
4781                         (status & RxFIFOOver) ? (status | RxOverflow) : status);
4782                 status = RTL_R16(IntrStatus);
4783         }
4784 done:
4785         return IRQ_RETVAL(handled);
4786 }
4787
4788 static int rtl8169_poll(struct napi_struct *napi, int budget)
4789 {
4790         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4791         struct net_device *dev = tp->dev;
4792         void __iomem *ioaddr = tp->mmio_addr;
4793         int work_done;
4794
4795         work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
4796         rtl8169_tx_interrupt(dev, tp, ioaddr);
4797
4798         if (work_done < budget) {
4799                 napi_complete(napi);
4800
4801                 /* We need for force the visibility of tp->intr_mask
4802                  * for other CPUs, as we can loose an MSI interrupt
4803                  * and potentially wait for a retransmit timeout if we don't.
4804                  * The posted write to IntrMask is safe, as it will
4805                  * eventually make it to the chip and we won't loose anything
4806                  * until it does.
4807                  */
4808                 tp->intr_mask = 0xffff;
4809                 wmb();
4810                 RTL_W16(IntrMask, tp->intr_event);
4811         }
4812
4813         return work_done;
4814 }
4815
4816 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
4817 {
4818         struct rtl8169_private *tp = netdev_priv(dev);
4819
4820         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
4821                 return;
4822
4823         dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
4824         RTL_W32(RxMissed, 0);
4825 }
4826
4827 static void rtl8169_down(struct net_device *dev)
4828 {
4829         struct rtl8169_private *tp = netdev_priv(dev);
4830         void __iomem *ioaddr = tp->mmio_addr;
4831
4832         rtl8169_delete_timer(dev);
4833
4834         netif_stop_queue(dev);
4835
4836         napi_disable(&tp->napi);
4837
4838         spin_lock_irq(&tp->lock);
4839
4840         rtl8169_asic_down(ioaddr);
4841         /*
4842          * At this point device interrupts can not be enabled in any function,
4843          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
4844          * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
4845          */
4846         rtl8169_rx_missed(dev, ioaddr);
4847
4848         spin_unlock_irq(&tp->lock);
4849
4850         synchronize_irq(dev->irq);
4851
4852         /* Give a racing hard_start_xmit a few cycles to complete. */
4853         synchronize_sched();  /* FIXME: should this be synchronize_irq()? */
4854
4855         rtl8169_tx_clear(tp);
4856
4857         rtl8169_rx_clear(tp);
4858
4859         rtl_pll_power_down(tp);
4860 }
4861
4862 static int rtl8169_close(struct net_device *dev)
4863 {
4864         struct rtl8169_private *tp = netdev_priv(dev);
4865         struct pci_dev *pdev = tp->pci_dev;
4866
4867         pm_runtime_get_sync(&pdev->dev);
4868
4869         /* update counters before going down */
4870         rtl8169_update_counters(dev);
4871
4872         rtl8169_down(dev);
4873
4874         free_irq(dev->irq, dev);
4875
4876         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4877                           tp->RxPhyAddr);
4878         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4879                           tp->TxPhyAddr);
4880         tp->TxDescArray = NULL;
4881         tp->RxDescArray = NULL;
4882
4883         pm_runtime_put_sync(&pdev->dev);
4884
4885         return 0;
4886 }
4887
4888 static void rtl_set_rx_mode(struct net_device *dev)
4889 {
4890         struct rtl8169_private *tp = netdev_priv(dev);
4891         void __iomem *ioaddr = tp->mmio_addr;
4892         unsigned long flags;
4893         u32 mc_filter[2];       /* Multicast hash filter */
4894         int rx_mode;
4895         u32 tmp = 0;
4896
4897         if (dev->flags & IFF_PROMISC) {
4898                 /* Unconditionally log net taps. */
4899                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4900                 rx_mode =
4901                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4902                     AcceptAllPhys;
4903                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4904         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4905                    (dev->flags & IFF_ALLMULTI)) {
4906                 /* Too many to filter perfectly -- accept all multicasts. */
4907                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4908                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4909         } else {
4910                 struct netdev_hw_addr *ha;
4911
4912                 rx_mode = AcceptBroadcast | AcceptMyPhys;
4913                 mc_filter[1] = mc_filter[0] = 0;
4914                 netdev_for_each_mc_addr(ha, dev) {
4915                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4916                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4917                         rx_mode |= AcceptMulticast;
4918                 }
4919         }
4920
4921         spin_lock_irqsave(&tp->lock, flags);
4922
4923         tmp = rtl8169_rx_config | rx_mode |
4924               (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
4925
4926         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4927                 u32 data = mc_filter[0];
4928
4929                 mc_filter[0] = swab32(mc_filter[1]);
4930                 mc_filter[1] = swab32(data);
4931         }
4932
4933         RTL_W32(MAR0 + 4, mc_filter[1]);
4934         RTL_W32(MAR0 + 0, mc_filter[0]);
4935
4936         RTL_W32(RxConfig, tmp);
4937
4938         spin_unlock_irqrestore(&tp->lock, flags);
4939 }
4940
4941 /**
4942  *  rtl8169_get_stats - Get rtl8169 read/write statistics
4943  *  @dev: The Ethernet Device to get statistics for
4944  *
4945  *  Get TX/RX statistics for rtl8169
4946  */
4947 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
4948 {
4949         struct rtl8169_private *tp = netdev_priv(dev);
4950         void __iomem *ioaddr = tp->mmio_addr;
4951         unsigned long flags;
4952
4953         if (netif_running(dev)) {
4954                 spin_lock_irqsave(&tp->lock, flags);
4955                 rtl8169_rx_missed(dev, ioaddr);
4956                 spin_unlock_irqrestore(&tp->lock, flags);
4957         }
4958
4959         return &dev->stats;
4960 }
4961
4962 static void rtl8169_net_suspend(struct net_device *dev)
4963 {
4964         struct rtl8169_private *tp = netdev_priv(dev);
4965
4966         if (!netif_running(dev))
4967                 return;
4968
4969         rtl_pll_power_down(tp);
4970
4971         netif_device_detach(dev);
4972         netif_stop_queue(dev);
4973 }
4974
4975 #ifdef CONFIG_PM
4976
4977 static int rtl8169_suspend(struct device *device)
4978 {
4979         struct pci_dev *pdev = to_pci_dev(device);
4980         struct net_device *dev = pci_get_drvdata(pdev);
4981
4982         rtl8169_net_suspend(dev);
4983
4984         return 0;
4985 }
4986
4987 static void __rtl8169_resume(struct net_device *dev)
4988 {
4989         struct rtl8169_private *tp = netdev_priv(dev);
4990
4991         netif_device_attach(dev);
4992
4993         rtl_pll_power_up(tp);
4994
4995         rtl8169_schedule_work(dev, rtl8169_reset_task);
4996 }
4997
4998 static int rtl8169_resume(struct device *device)
4999 {
5000         struct pci_dev *pdev = to_pci_dev(device);
5001         struct net_device *dev = pci_get_drvdata(pdev);
5002         struct rtl8169_private *tp = netdev_priv(dev);
5003
5004         rtl8169_init_phy(dev, tp);
5005
5006         if (netif_running(dev))
5007                 __rtl8169_resume(dev);
5008
5009         return 0;
5010 }
5011
5012 static int rtl8169_runtime_suspend(struct device *device)
5013 {
5014         struct pci_dev *pdev = to_pci_dev(device);
5015         struct net_device *dev = pci_get_drvdata(pdev);
5016         struct rtl8169_private *tp = netdev_priv(dev);
5017
5018         if (!tp->TxDescArray)
5019                 return 0;
5020
5021         spin_lock_irq(&tp->lock);
5022         tp->saved_wolopts = __rtl8169_get_wol(tp);
5023         __rtl8169_set_wol(tp, WAKE_ANY);
5024         spin_unlock_irq(&tp->lock);
5025
5026         rtl8169_net_suspend(dev);
5027
5028         return 0;
5029 }
5030
5031 static int rtl8169_runtime_resume(struct device *device)
5032 {
5033         struct pci_dev *pdev = to_pci_dev(device);
5034         struct net_device *dev = pci_get_drvdata(pdev);
5035         struct rtl8169_private *tp = netdev_priv(dev);
5036
5037         if (!tp->TxDescArray)
5038                 return 0;
5039
5040         spin_lock_irq(&tp->lock);
5041         __rtl8169_set_wol(tp, tp->saved_wolopts);
5042         tp->saved_wolopts = 0;
5043         spin_unlock_irq(&tp->lock);
5044
5045         rtl8169_init_phy(dev, tp);
5046
5047         __rtl8169_resume(dev);
5048
5049         return 0;
5050 }
5051
5052 static int rtl8169_runtime_idle(struct device *device)
5053 {
5054         struct pci_dev *pdev = to_pci_dev(device);
5055         struct net_device *dev = pci_get_drvdata(pdev);
5056         struct rtl8169_private *tp = netdev_priv(dev);
5057
5058         return tp->TxDescArray ? -EBUSY : 0;
5059 }
5060
5061 static const struct dev_pm_ops rtl8169_pm_ops = {
5062         .suspend = rtl8169_suspend,
5063         .resume = rtl8169_resume,
5064         .freeze = rtl8169_suspend,
5065         .thaw = rtl8169_resume,
5066         .poweroff = rtl8169_suspend,
5067         .restore = rtl8169_resume,
5068         .runtime_suspend = rtl8169_runtime_suspend,
5069         .runtime_resume = rtl8169_runtime_resume,
5070         .runtime_idle = rtl8169_runtime_idle,
5071 };
5072
5073 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
5074
5075 #else /* !CONFIG_PM */
5076
5077 #define RTL8169_PM_OPS  NULL
5078
5079 #endif /* !CONFIG_PM */
5080
5081 static void rtl_shutdown(struct pci_dev *pdev)
5082 {
5083         struct net_device *dev = pci_get_drvdata(pdev);
5084         struct rtl8169_private *tp = netdev_priv(dev);
5085         void __iomem *ioaddr = tp->mmio_addr;
5086
5087         rtl8169_net_suspend(dev);
5088
5089         /* restore original MAC address */
5090         rtl_rar_set(tp, dev->perm_addr);
5091
5092         spin_lock_irq(&tp->lock);
5093
5094         rtl8169_asic_down(ioaddr);
5095
5096         spin_unlock_irq(&tp->lock);
5097
5098         if (system_state == SYSTEM_POWER_OFF) {
5099                 /* WoL fails with some 8168 when the receiver is disabled. */
5100                 if (tp->features & RTL_FEATURE_WOL) {
5101                         pci_clear_master(pdev);
5102
5103                         RTL_W8(ChipCmd, CmdRxEnb);
5104                         /* PCI commit */
5105                         RTL_R8(ChipCmd);
5106                 }
5107
5108                 pci_wake_from_d3(pdev, true);
5109                 pci_set_power_state(pdev, PCI_D3hot);
5110         }
5111 }
5112
5113 static struct pci_driver rtl8169_pci_driver = {
5114         .name           = MODULENAME,
5115         .id_table       = rtl8169_pci_tbl,
5116         .probe          = rtl8169_init_one,
5117         .remove         = __devexit_p(rtl8169_remove_one),
5118         .shutdown       = rtl_shutdown,
5119         .driver.pm      = RTL8169_PM_OPS,
5120 };
5121
5122 static int __init rtl8169_init_module(void)
5123 {
5124         return pci_register_driver(&rtl8169_pci_driver);
5125 }
5126
5127 static void __exit rtl8169_cleanup_module(void)
5128 {
5129         pci_unregister_driver(&rtl8169_pci_driver);
5130 }
5131
5132 module_init(rtl8169_init_module);
5133 module_exit(rtl8169_cleanup_module);