drivers/net/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/mii.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/crc32.h>
  21 #include <linux/in.h>
  22 #include <linux/ip.h>
  23 #include <linux/tcp.h>
  24 #include <linux/init.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/firmware.h>
  28
  29 #include <asm/system.h>
  30 #include <asm/io.h>
  31 #include <asm/irq.h>
  32
  33 #define RTL8169_VERSION "2.3LK-NAPI"
  34 #define MODULENAME "r8169"
  35 #define PFX MODULENAME ": "
  36
  37 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  38 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  39
  40 #ifdef RTL8169_DEBUG
  41 #define assert(expr) \
  42         if (!(expr)) {                                  \
  43                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  44                 #expr,__FILE__,__func__,__LINE__);              \
  45         }
  46 #define dprintk(fmt, args...) \
  47         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
  48 #else
  49 #define assert(expr) do {} while (0)
  50 #define dprintk(fmt, args...)   do {} while (0)
  51 #endif /* RTL8169_DEBUG */
  52
  53 #define R8169_MSG_DEFAULT \
  54         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  55
  56 #define TX_BUFFS_AVAIL(tp) \
  57         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
  58
  59 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  60    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  61 static const int multicast_filter_limit = 32;
  62
  63 /* MAC address length */
  64 #define MAC_ADDR_LEN    6
  65
  66 #define MAX_READ_REQUEST_SHIFT  12
  67 #define RX_FIFO_THRESH  7       /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
  68 #define RX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  69 #define TX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  70 #define EarlyTxThld     0x3F    /* 0x3F means NO early transmit */
  71 #define SafeMtu         0x1c20  /* ... actually life sucks beyond ~7k */
  72 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  73
  74 #define R8169_REGS_SIZE         256
  75 #define R8169_NAPI_WEIGHT       64
  76 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  77 #define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
  78 #define RX_BUF_SIZE     1536    /* Rx Buffer size */
  79 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  80 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  81
  82 #define RTL8169_TX_TIMEOUT      (6*HZ)
  83 #define RTL8169_PHY_TIMEOUT     (10*HZ)
  84
  85 #define RTL_EEPROM_SIG          cpu_to_le32(0x8129)
  86 #define RTL_EEPROM_SIG_MASK     cpu_to_le32(0xffff)
  87 #define RTL_EEPROM_SIG_ADDR     0x0000
  88
  89 /* write/read MMIO register */
  90 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
  91 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
  92 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
  93 #define RTL_R8(reg)             readb (ioaddr + (reg))
  94 #define RTL_R16(reg)            readw (ioaddr + (reg))
  95 #define RTL_R32(reg)            readl (ioaddr + (reg))
  96
  97 enum mac_version {
  98         RTL_GIGA_MAC_NONE   = 0x00,
  99         RTL_GIGA_MAC_VER_01 = 0x01, // 8169
 100         RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
 101         RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
 102         RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
 103         RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
 104         RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
 105         RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
 106         RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
 107         RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
 108         RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
 109         RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
 110         RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
 111         RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
 112         RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
 113         RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
 114         RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
 115         RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
 116         RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
 117         RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
 118         RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
 119         RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
 120         RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
 121         RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
 122         RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
 123         RTL_GIGA_MAC_VER_25 = 0x19, // 8168D
 124         RTL_GIGA_MAC_VER_26 = 0x1a, // 8168D
 125         RTL_GIGA_MAC_VER_27 = 0x1b  // 8168DP
 126 };
 127
 128 #define _R(NAME,MAC,MASK) \
 129         { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
 130
 131 static const struct {
 132         const char *name;
 133         u8 mac_version;
 134         u32 RxConfigMask;       /* Clears the bits supported by this chip */
 135 } rtl_chip_info[] = {
 136         _R("RTL8169",           RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
 137         _R("RTL8169s",          RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
 138         _R("RTL8110s",          RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
 139         _R("RTL8169sb/8110sb",  RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
 140         _R("RTL8169sc/8110sc",  RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
 141         _R("RTL8169sc/8110sc",  RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
 142         _R("RTL8102e",          RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
 143         _R("RTL8102e",          RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
 144         _R("RTL8102e",          RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
 145         _R("RTL8101e",          RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
 146         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
 147         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
 148         _R("RTL8101e",          RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
 149         _R("RTL8100e",          RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
 150         _R("RTL8100e",          RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
 151         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
 152         _R("RTL8101e",          RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
 153         _R("RTL8168cp/8111cp",  RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
 154         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
 155         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E
 156         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E
 157         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E
 158         _R("RTL8168cp/8111cp",  RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E
 159         _R("RTL8168cp/8111cp",  RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E
 160         _R("RTL8168d/8111d",    RTL_GIGA_MAC_VER_25, 0xff7e1880), // PCI-E
 161         _R("RTL8168d/8111d",    RTL_GIGA_MAC_VER_26, 0xff7e1880), // PCI-E
 162         _R("RTL8168dp/8111dp",  RTL_GIGA_MAC_VER_27, 0xff7e1880)  // PCI-E
 163 };
 164 #undef _R
 165
 166 enum cfg_version {
 167         RTL_CFG_0 = 0x00,
 168         RTL_CFG_1,
 169         RTL_CFG_2
 170 };
 171
 172 static void rtl_hw_start_8169(struct net_device *);
 173 static void rtl_hw_start_8168(struct net_device *);
 174 static void rtl_hw_start_8101(struct net_device *);
 175
 176 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
 177         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 178         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 179         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 180         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 181         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 182         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 183         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
 184         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 185         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 186                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 187         { 0x0001,                               0x8168,
 188                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 189         {0,},
 190 };
 191
 192 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 193
 194 static int rx_buf_sz = 16383;
 195 static int use_dac;
 196 static struct {
 197         u32 msg_enable;
 198 } debug = { -1 };
 199
 200 enum rtl_registers {
 201         MAC0            = 0,    /* Ethernet hardware address. */
 202         MAC4            = 4,
 203         MAR0            = 8,    /* Multicast filter. */
 204         CounterAddrLow          = 0x10,
 205         CounterAddrHigh         = 0x14,
 206         TxDescStartAddrLow      = 0x20,
 207         TxDescStartAddrHigh     = 0x24,
 208         TxHDescStartAddrLow     = 0x28,
 209         TxHDescStartAddrHigh    = 0x2c,
 210         FLASH           = 0x30,
 211         ERSR            = 0x36,
 212         ChipCmd         = 0x37,
 213         TxPoll          = 0x38,
 214         IntrMask        = 0x3c,
 215         IntrStatus      = 0x3e,
 216         TxConfig        = 0x40,
 217         RxConfig        = 0x44,
 218         RxMissed        = 0x4c,
 219         Cfg9346         = 0x50,
 220         Config0         = 0x51,
 221         Config1         = 0x52,
 222         Config2         = 0x53,
 223         Config3         = 0x54,
 224         Config4         = 0x55,
 225         Config5         = 0x56,
 226         MultiIntr       = 0x5c,
 227         PHYAR           = 0x60,
 228         PHYstatus       = 0x6c,
 229         RxMaxSize       = 0xda,
 230         CPlusCmd        = 0xe0,
 231         IntrMitigate    = 0xe2,
 232         RxDescAddrLow   = 0xe4,
 233         RxDescAddrHigh  = 0xe8,
 234         EarlyTxThres    = 0xec,
 235         FuncEvent       = 0xf0,
 236         FuncEventMask   = 0xf4,
 237         FuncPresetState = 0xf8,
 238         FuncForceEvent  = 0xfc,
 239 };
 240
 241 enum rtl8110_registers {
 242         TBICSR                  = 0x64,
 243         TBI_ANAR                = 0x68,
 244         TBI_LPAR                = 0x6a,
 245 };
 246
 247 enum rtl8168_8101_registers {
 248         CSIDR                   = 0x64,
 249         CSIAR                   = 0x68,
 250 #define CSIAR_FLAG                      0x80000000
 251 #define CSIAR_WRITE_CMD                 0x80000000
 252 #define CSIAR_BYTE_ENABLE               0x0f
 253 #define CSIAR_BYTE_ENABLE_SHIFT         12
 254 #define CSIAR_ADDR_MASK                 0x0fff
 255
 256         EPHYAR                  = 0x80,
 257 #define EPHYAR_FLAG                     0x80000000
 258 #define EPHYAR_WRITE_CMD                0x80000000
 259 #define EPHYAR_REG_MASK                 0x1f
 260 #define EPHYAR_REG_SHIFT                16
 261 #define EPHYAR_DATA_MASK                0xffff
 262         DBG_REG                 = 0xd1,
 263 #define FIX_NAK_1                       (1 << 4)
 264 #define FIX_NAK_2                       (1 << 3)
 265         EFUSEAR                 = 0xdc,
 266 #define EFUSEAR_FLAG                    0x80000000
 267 #define EFUSEAR_WRITE_CMD               0x80000000
 268 #define EFUSEAR_READ_CMD                0x00000000
 269 #define EFUSEAR_REG_MASK                0x03ff
 270 #define EFUSEAR_REG_SHIFT               8
 271 #define EFUSEAR_DATA_MASK               0xff
 272 };
 273
 274 enum rtl_register_content {
 275         /* InterruptStatusBits */
 276         SYSErr          = 0x8000,
 277         PCSTimeout      = 0x4000,
 278         SWInt           = 0x0100,
 279         TxDescUnavail   = 0x0080,
 280         RxFIFOOver      = 0x0040,
 281         LinkChg         = 0x0020,
 282         RxOverflow      = 0x0010,
 283         TxErr           = 0x0008,
 284         TxOK            = 0x0004,
 285         RxErr           = 0x0002,
 286         RxOK            = 0x0001,
 287
 288         /* RxStatusDesc */
 289         RxFOVF  = (1 << 23),
 290         RxRWT   = (1 << 22),
 291         RxRES   = (1 << 21),
 292         RxRUNT  = (1 << 20),
 293         RxCRC   = (1 << 19),
 294
 295         /* ChipCmdBits */
 296         CmdReset        = 0x10,
 297         CmdRxEnb        = 0x08,
 298         CmdTxEnb        = 0x04,
 299         RxBufEmpty      = 0x01,
 300
 301         /* TXPoll register p.5 */
 302         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 303         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 304         FSWInt          = 0x01,         /* Forced software interrupt */
 305
 306         /* Cfg9346Bits */
 307         Cfg9346_Lock    = 0x00,
 308         Cfg9346_Unlock  = 0xc0,
 309
 310         /* rx_mode_bits */
 311         AcceptErr       = 0x20,
 312         AcceptRunt      = 0x10,
 313         AcceptBroadcast = 0x08,
 314         AcceptMulticast = 0x04,
 315         AcceptMyPhys    = 0x02,
 316         AcceptAllPhys   = 0x01,
 317
 318         /* RxConfigBits */
 319         RxCfgFIFOShift  = 13,
 320         RxCfgDMAShift   =  8,
 321
 322         /* TxConfigBits */
 323         TxInterFrameGapShift = 24,
 324         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 325
 326         /* Config1 register p.24 */
 327         LEDS1           = (1 << 7),
 328         LEDS0           = (1 << 6),
 329         MSIEnable       = (1 << 5),     /* Enable Message Signaled Interrupt */
 330         Speed_down      = (1 << 4),
 331         MEMMAP          = (1 << 3),
 332         IOMAP           = (1 << 2),
 333         VPD             = (1 << 1),
 334         PMEnable        = (1 << 0),     /* Power Management Enable */
 335
 336         /* Config2 register p. 25 */
 337         PCI_Clock_66MHz = 0x01,
 338         PCI_Clock_33MHz = 0x00,
 339
 340         /* Config3 register p.25 */
 341         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 342         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 343         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 344
 345         /* Config5 register p.27 */
 346         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 347         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 348         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 349         LanWake         = (1 << 1),     /* LanWake enable/disable */
 350         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 351
 352         /* TBICSR p.28 */
 353         TBIReset        = 0x80000000,
 354         TBILoopback     = 0x40000000,
 355         TBINwEnable     = 0x20000000,
 356         TBINwRestart    = 0x10000000,
 357         TBILinkOk       = 0x02000000,
 358         TBINwComplete   = 0x01000000,
 359
 360         /* CPlusCmd p.31 */
 361         EnableBist      = (1 << 15),    // 8168 8101
 362         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 363         Normal_mode     = (1 << 13),    // unused
 364         Force_half_dup  = (1 << 12),    // 8168 8101
 365         Force_rxflow_en = (1 << 11),    // 8168 8101
 366         Force_txflow_en = (1 << 10),    // 8168 8101
 367         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 368         ASF             = (1 << 8),     // 8168 8101
 369         PktCntrDisable  = (1 << 7),     // 8168 8101
 370         Mac_dbgo_sel    = 0x001c,       // 8168
 371         RxVlan          = (1 << 6),
 372         RxChkSum        = (1 << 5),
 373         PCIDAC          = (1 << 4),
 374         PCIMulRW        = (1 << 3),
 375         INTT_0          = 0x0000,       // 8168
 376         INTT_1          = 0x0001,       // 8168
 377         INTT_2          = 0x0002,       // 8168
 378         INTT_3          = 0x0003,       // 8168
 379
 380         /* rtl8169_PHYstatus */
 381         TBI_Enable      = 0x80,
 382         TxFlowCtrl      = 0x40,
 383         RxFlowCtrl      = 0x20,
 384         _1000bpsF       = 0x10,
 385         _100bps         = 0x08,
 386         _10bps          = 0x04,
 387         LinkStatus      = 0x02,
 388         FullDup         = 0x01,
 389
 390         /* _TBICSRBit */
 391         TBILinkOK       = 0x02000000,
 392
 393         /* DumpCounterCommand */
 394         CounterDump     = 0x8,
 395 };
 396
 397 enum desc_status_bit {
 398         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 399         RingEnd         = (1 << 30), /* End of descriptor ring */
 400         FirstFrag       = (1 << 29), /* First segment of a packet */
 401         LastFrag        = (1 << 28), /* Final segment of a packet */
 402
 403         /* Tx private */
 404         LargeSend       = (1 << 27), /* TCP Large Send Offload (TSO) */
 405         MSSShift        = 16,        /* MSS value position */
 406         MSSMask         = 0xfff,     /* MSS value + LargeSend bit: 12 bits */
 407         IPCS            = (1 << 18), /* Calculate IP checksum */
 408         UDPCS           = (1 << 17), /* Calculate UDP/IP checksum */
 409         TCPCS           = (1 << 16), /* Calculate TCP/IP checksum */
 410         TxVlanTag       = (1 << 17), /* Add VLAN tag */
 411
 412         /* Rx private */
 413         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 414         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
 415
 416 #define RxProtoUDP      (PID1)
 417 #define RxProtoTCP      (PID0)
 418 #define RxProtoIP       (PID1 | PID0)
 419 #define RxProtoMask     RxProtoIP
 420
 421         IPFail          = (1 << 16), /* IP checksum failed */
 422         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 423         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 424         RxVlanTag       = (1 << 16), /* VLAN tag available */
 425 };
 426
 427 #define RsvdMask        0x3fffc000
 428
 429 struct TxDesc {
 430         __le32 opts1;
 431         __le32 opts2;
 432         __le64 addr;
 433 };
 434
 435 struct RxDesc {
 436         __le32 opts1;
 437         __le32 opts2;
 438         __le64 addr;
 439 };
 440
 441 struct ring_info {
 442         struct sk_buff  *skb;
 443         u32             len;
 444         u8              __pad[sizeof(void *) - sizeof(u32)];
 445 };
 446
 447 enum features {
 448         RTL_FEATURE_WOL         = (1 << 0),
 449         RTL_FEATURE_MSI         = (1 << 1),
 450         RTL_FEATURE_GMII        = (1 << 2),
 451 };
 452
 453 struct rtl8169_counters {
 454         __le64  tx_packets;
 455         __le64  rx_packets;
 456         __le64  tx_errors;
 457         __le32  rx_errors;
 458         __le16  rx_missed;
 459         __le16  align_errors;
 460         __le32  tx_one_collision;
 461         __le32  tx_multi_collision;
 462         __le64  rx_unicast;
 463         __le64  rx_broadcast;
 464         __le32  rx_multicast;
 465         __le16  tx_aborted;
 466         __le16  tx_underun;
 467 };
 468
 469 struct rtl8169_private {
 470         void __iomem *mmio_addr;        /* memory map physical address */
 471         struct pci_dev *pci_dev;        /* Index of PCI device */
 472         struct net_device *dev;
 473         struct napi_struct napi;
 474         spinlock_t lock;                /* spin lock flag */
 475         u32 msg_enable;
 476         int chipset;
 477         int mac_version;
 478         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 479         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 480         u32 dirty_rx;
 481         u32 dirty_tx;
 482         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 483         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 484         dma_addr_t TxPhyAddr;
 485         dma_addr_t RxPhyAddr;
 486         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 487         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 488         struct timer_list timer;
 489         u16 cp_cmd;
 490         u16 intr_event;
 491         u16 napi_event;
 492         u16 intr_mask;
 493         int phy_1000_ctrl_reg;
 494 #ifdef CONFIG_R8169_VLAN
 495         struct vlan_group *vlgrp;
 496 #endif
 497         int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
 498         int (*get_settings)(struct net_device *, struct ethtool_cmd *);
 499         void (*phy_reset_enable)(void __iomem *);
 500         void (*hw_start)(struct net_device *);
 501         unsigned int (*phy_reset_pending)(void __iomem *);
 502         unsigned int (*link_ok)(void __iomem *);
 503         int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
 504         int pcie_cap;
 505         struct delayed_work task;
 506         unsigned features;
 507
 508         struct mii_if_info mii;
 509         struct rtl8169_counters counters;
 510         u32 saved_wolopts;
 511 };
 512
 513 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 514 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 515 module_param(use_dac, int, 0);
 516 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 517 module_param_named(debug, debug.msg_enable, int, 0);
 518 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 519 MODULE_LICENSE("GPL");
 520 MODULE_VERSION(RTL8169_VERSION);
 521 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 522 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 523
 524 static int rtl8169_open(struct net_device *dev);
 525 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
 526                                       struct net_device *dev);
 527 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
 528 static int rtl8169_init_ring(struct net_device *dev);
 529 static void rtl_hw_start(struct net_device *dev);
 530 static int rtl8169_close(struct net_device *dev);
 531 static void rtl_set_rx_mode(struct net_device *dev);
 532 static void rtl8169_tx_timeout(struct net_device *dev);
 533 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
 534 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
 535                                 void __iomem *, u32 budget);
 536 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
 537 static void rtl8169_down(struct net_device *dev);
 538 static void rtl8169_rx_clear(struct rtl8169_private *tp);
 539 static int rtl8169_poll(struct napi_struct *napi, int budget);
 540
 541 static const unsigned int rtl8169_rx_config =
 542         (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
 543
 544 static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 545 {
 546         int i;
 547
 548         RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
 549
 550         for (i = 20; i > 0; i--) {
 551                 /*
 552                  * Check if the RTL8169 has completed writing to the specified
 553                  * MII register.
 554                  */
 555                 if (!(RTL_R32(PHYAR) & 0x80000000))
 556                         break;
 557                 udelay(25);
 558         }
 559         /*
 560          * According to hardware specs a 20us delay is required after write
 561          * complete indication, but before sending next command.
 562          */
 563         udelay(20);
 564 }
 565
 566 static int mdio_read(void __iomem *ioaddr, int reg_addr)
 567 {
 568         int i, value = -1;
 569
 570         RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
 571
 572         for (i = 20; i > 0; i--) {
 573                 /*
 574                  * Check if the RTL8169 has completed retrieving data from
 575                  * the specified MII register.
 576                  */
 577                 if (RTL_R32(PHYAR) & 0x80000000) {
 578                         value = RTL_R32(PHYAR) & 0xffff;
 579                         break;
 580                 }
 581                 udelay(25);
 582         }
 583         /*
 584          * According to hardware specs a 20us delay is required after read
 585          * complete indication, but before sending next command.
 586          */
 587         udelay(20);
 588
 589         return value;
 590 }
 591
 592 static void mdio_patch(void __iomem *ioaddr, int reg_addr, int value)
 593 {
 594         mdio_write(ioaddr, reg_addr, mdio_read(ioaddr, reg_addr) | value);
 595 }
 596
 597 static void mdio_plus_minus(void __iomem *ioaddr, int reg_addr, int p, int m)
 598 {
 599         int val;
 600
 601         val = mdio_read(ioaddr, reg_addr);
 602         mdio_write(ioaddr, reg_addr, (val | p) & ~m);
 603 }
 604
 605 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
 606                            int val)
 607 {
 608         struct rtl8169_private *tp = netdev_priv(dev);
 609         void __iomem *ioaddr = tp->mmio_addr;
 610
 611         mdio_write(ioaddr, location, val);
 612 }
 613
 614 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
 615 {
 616         struct rtl8169_private *tp = netdev_priv(dev);
 617         void __iomem *ioaddr = tp->mmio_addr;
 618
 619         return mdio_read(ioaddr, location);
 620 }
 621
 622 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
 623 {
 624         unsigned int i;
 625
 626         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
 627                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
 628
 629         for (i = 0; i < 100; i++) {
 630                 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
 631                         break;
 632                 udelay(10);
 633         }
 634 }
 635
 636 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
 637 {
 638         u16 value = 0xffff;
 639         unsigned int i;
 640
 641         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
 642
 643         for (i = 0; i < 100; i++) {
 644                 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
 645                         value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
 646                         break;
 647                 }
 648                 udelay(10);
 649         }
 650
 651         return value;
 652 }
 653
 654 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
 655 {
 656         unsigned int i;
 657
 658         RTL_W32(CSIDR, value);
 659         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
 660                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
 661
 662         for (i = 0; i < 100; i++) {
 663                 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
 664                         break;
 665                 udelay(10);
 666         }
 667 }
 668
 669 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
 670 {
 671         u32 value = ~0x00;
 672         unsigned int i;
 673
 674         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
 675                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
 676
 677         for (i = 0; i < 100; i++) {
 678                 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
 679                         value = RTL_R32(CSIDR);
 680                         break;
 681                 }
 682                 udelay(10);
 683         }
 684
 685         return value;
 686 }
 687
 688 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
 689 {
 690         u8 value = 0xff;
 691         unsigned int i;
 692
 693         RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
 694
 695         for (i = 0; i < 300; i++) {
 696                 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
 697                         value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
 698                         break;
 699                 }
 700                 udelay(100);
 701         }
 702
 703         return value;
 704 }
 705
 706 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
 707 {
 708         RTL_W16(IntrMask, 0x0000);
 709
 710         RTL_W16(IntrStatus, 0xffff);
 711 }
 712
 713 static void rtl8169_asic_down(void __iomem *ioaddr)
 714 {
 715         RTL_W8(ChipCmd, 0x00);
 716         rtl8169_irq_mask_and_ack(ioaddr);
 717         RTL_R16(CPlusCmd);
 718 }
 719
 720 static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
 721 {
 722         return RTL_R32(TBICSR) & TBIReset;
 723 }
 724
 725 static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
 726 {
 727         return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
 728 }
 729
 730 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
 731 {
 732         return RTL_R32(TBICSR) & TBILinkOk;
 733 }
 734
 735 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
 736 {
 737         return RTL_R8(PHYstatus) & LinkStatus;
 738 }
 739
 740 static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
 741 {
 742         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
 743 }
 744
 745 static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
 746 {
 747         unsigned int val;
 748
 749         val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
 750         mdio_write(ioaddr, MII_BMCR, val & 0xffff);
 751 }
 752
 753 static void __rtl8169_check_link_status(struct net_device *dev,
 754                                       struct rtl8169_private *tp,
 755                                       void __iomem *ioaddr,
 756                                       bool pm)
 757 {
 758         unsigned long flags;
 759
 760         spin_lock_irqsave(&tp->lock, flags);
 761         if (tp->link_ok(ioaddr)) {
 762                 /* This is to cancel a scheduled suspend if there's one. */
 763                 if (pm)
 764                         pm_request_resume(&tp->pci_dev->dev);
 765                 netif_carrier_on(dev);
 766                 netif_info(tp, ifup, dev, "link up\n");
 767         } else {
 768                 netif_carrier_off(dev);
 769                 netif_info(tp, ifdown, dev, "link down\n");
 770                 if (pm)
 771                         pm_schedule_suspend(&tp->pci_dev->dev, 100);
 772         }
 773         spin_unlock_irqrestore(&tp->lock, flags);
 774 }
 775
 776 static void rtl8169_check_link_status(struct net_device *dev,
 777                                       struct rtl8169_private *tp,
 778                                       void __iomem *ioaddr)
 779 {
 780         __rtl8169_check_link_status(dev, tp, ioaddr, false);
 781 }
 782
 783 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
 784
 785 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
 786 {
 787         void __iomem *ioaddr = tp->mmio_addr;
 788         u8 options;
 789         u32 wolopts = 0;
 790
 791         options = RTL_R8(Config1);
 792         if (!(options & PMEnable))
 793                 return 0;
 794
 795         options = RTL_R8(Config3);
 796         if (options & LinkUp)
 797                 wolopts |= WAKE_PHY;
 798         if (options & MagicPacket)
 799                 wolopts |= WAKE_MAGIC;
 800
 801         options = RTL_R8(Config5);
 802         if (options & UWF)
 803                 wolopts |= WAKE_UCAST;
 804         if (options & BWF)
 805                 wolopts |= WAKE_BCAST;
 806         if (options & MWF)
 807                 wolopts |= WAKE_MCAST;
 808
 809         return wolopts;
 810 }
 811
 812 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 813 {
 814         struct rtl8169_private *tp = netdev_priv(dev);
 815
 816         spin_lock_irq(&tp->lock);
 817
 818         wol->supported = WAKE_ANY;
 819         wol->wolopts = __rtl8169_get_wol(tp);
 820
 821         spin_unlock_irq(&tp->lock);
 822 }
 823
 824 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
 825 {
 826         void __iomem *ioaddr = tp->mmio_addr;
 827         unsigned int i;
 828         static const struct {
 829                 u32 opt;
 830                 u16 reg;
 831                 u8  mask;
 832         } cfg[] = {
 833                 { WAKE_ANY,   Config1, PMEnable },
 834                 { WAKE_PHY,   Config3, LinkUp },
 835                 { WAKE_MAGIC, Config3, MagicPacket },
 836                 { WAKE_UCAST, Config5, UWF },
 837                 { WAKE_BCAST, Config5, BWF },
 838                 { WAKE_MCAST, Config5, MWF },
 839                 { WAKE_ANY,   Config5, LanWake }
 840         };
 841
 842         RTL_W8(Cfg9346, Cfg9346_Unlock);
 843
 844         for (i = 0; i < ARRAY_SIZE(cfg); i++) {
 845                 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
 846                 if (wolopts & cfg[i].opt)
 847                         options |= cfg[i].mask;
 848                 RTL_W8(cfg[i].reg, options);
 849         }
 850
 851         RTL_W8(Cfg9346, Cfg9346_Lock);
 852 }
 853
 854 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 855 {
 856         struct rtl8169_private *tp = netdev_priv(dev);
 857
 858         spin_lock_irq(&tp->lock);
 859
 860         if (wol->wolopts)
 861                 tp->features |= RTL_FEATURE_WOL;
 862         else
 863                 tp->features &= ~RTL_FEATURE_WOL;
 864         __rtl8169_set_wol(tp, wol->wolopts);
 865         spin_unlock_irq(&tp->lock);
 866
 867         device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
 868
 869         return 0;
 870 }
 871
 872 static void rtl8169_get_drvinfo(struct net_device *dev,
 873                                 struct ethtool_drvinfo *info)
 874 {
 875         struct rtl8169_private *tp = netdev_priv(dev);
 876
 877         strcpy(info->driver, MODULENAME);
 878         strcpy(info->version, RTL8169_VERSION);
 879         strcpy(info->bus_info, pci_name(tp->pci_dev));
 880 }
 881
 882 static int rtl8169_get_regs_len(struct net_device *dev)
 883 {
 884         return R8169_REGS_SIZE;
 885 }
 886
 887 static int rtl8169_set_speed_tbi(struct net_device *dev,
 888                                  u8 autoneg, u16 speed, u8 duplex)
 889 {
 890         struct rtl8169_private *tp = netdev_priv(dev);
 891         void __iomem *ioaddr = tp->mmio_addr;
 892         int ret = 0;
 893         u32 reg;
 894
 895         reg = RTL_R32(TBICSR);
 896         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
 897             (duplex == DUPLEX_FULL)) {
 898                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
 899         } else if (autoneg == AUTONEG_ENABLE)
 900                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
 901         else {
 902                 netif_warn(tp, link, dev,
 903                            "incorrect speed setting refused in TBI mode\n");
 904                 ret = -EOPNOTSUPP;
 905         }
 906
 907         return ret;
 908 }
 909
 910 static int rtl8169_set_speed_xmii(struct net_device *dev,
 911                                   u8 autoneg, u16 speed, u8 duplex)
 912 {
 913         struct rtl8169_private *tp = netdev_priv(dev);
 914         void __iomem *ioaddr = tp->mmio_addr;
 915         int giga_ctrl, bmcr;
 916
 917         if (autoneg == AUTONEG_ENABLE) {
 918                 int auto_nego;
 919
 920                 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
 921                 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
 922                               ADVERTISE_100HALF | ADVERTISE_100FULL);
 923                 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
 924
 925                 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
 926                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
 927
 928                 /* The 8100e/8101e/8102e do Fast Ethernet only. */
 929                 if ((tp->mac_version != RTL_GIGA_MAC_VER_07) &&
 930                     (tp->mac_version != RTL_GIGA_MAC_VER_08) &&
 931                     (tp->mac_version != RTL_GIGA_MAC_VER_09) &&
 932                     (tp->mac_version != RTL_GIGA_MAC_VER_10) &&
 933                     (tp->mac_version != RTL_GIGA_MAC_VER_13) &&
 934                     (tp->mac_version != RTL_GIGA_MAC_VER_14) &&
 935                     (tp->mac_version != RTL_GIGA_MAC_VER_15) &&
 936                     (tp->mac_version != RTL_GIGA_MAC_VER_16)) {
 937                         giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
 938                 } else {
 939                         netif_info(tp, link, dev,
 940                                    "PHY does not support 1000Mbps\n");
 941                 }
 942
 943                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
 944
 945                 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
 946                     (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
 947                     (tp->mac_version >= RTL_GIGA_MAC_VER_17)) {
 948                         /*
 949                          * Wake up the PHY.
 950                          * Vendor specific (0x1f) and reserved (0x0e) MII
 951                          * registers.
 952                          */
 953                         mdio_write(ioaddr, 0x1f, 0x0000);
 954                         mdio_write(ioaddr, 0x0e, 0x0000);
 955                 }
 956
 957                 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
 958                 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
 959         } else {
 960                 giga_ctrl = 0;
 961
 962                 if (speed == SPEED_10)
 963                         bmcr = 0;
 964                 else if (speed == SPEED_100)
 965                         bmcr = BMCR_SPEED100;
 966                 else
 967                         return -EINVAL;
 968
 969                 if (duplex == DUPLEX_FULL)
 970                         bmcr |= BMCR_FULLDPLX;
 971
 972                 mdio_write(ioaddr, 0x1f, 0x0000);
 973         }
 974
 975         tp->phy_1000_ctrl_reg = giga_ctrl;
 976
 977         mdio_write(ioaddr, MII_BMCR, bmcr);
 978
 979         if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
 980             (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
 981                 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
 982                         mdio_write(ioaddr, 0x17, 0x2138);
 983                         mdio_write(ioaddr, 0x0e, 0x0260);
 984                 } else {
 985                         mdio_write(ioaddr, 0x17, 0x2108);
 986                         mdio_write(ioaddr, 0x0e, 0x0000);
 987                 }
 988         }
 989
 990         return 0;
 991 }
 992
 993 static int rtl8169_set_speed(struct net_device *dev,
 994                              u8 autoneg, u16 speed, u8 duplex)
 995 {
 996         struct rtl8169_private *tp = netdev_priv(dev);
 997         int ret;
 998
 999         ret = tp->set_speed(dev, autoneg, speed, duplex);
1000
1001         if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1002                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1003
1004         return ret;
1005 }
1006
1007 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1008 {
1009         struct rtl8169_private *tp = netdev_priv(dev);
1010         unsigned long flags;
1011         int ret;
1012
1013         spin_lock_irqsave(&tp->lock, flags);
1014         ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
1015         spin_unlock_irqrestore(&tp->lock, flags);
1016
1017         return ret;
1018 }
1019
1020 static u32 rtl8169_get_rx_csum(struct net_device *dev)
1021 {
1022         struct rtl8169_private *tp = netdev_priv(dev);
1023
1024         return tp->cp_cmd & RxChkSum;
1025 }
1026
1027 static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
1028 {
1029         struct rtl8169_private *tp = netdev_priv(dev);
1030         void __iomem *ioaddr = tp->mmio_addr;
1031         unsigned long flags;
1032
1033         spin_lock_irqsave(&tp->lock, flags);
1034
1035         if (data)
1036                 tp->cp_cmd |= RxChkSum;
1037         else
1038                 tp->cp_cmd &= ~RxChkSum;
1039
1040         RTL_W16(CPlusCmd, tp->cp_cmd);
1041         RTL_R16(CPlusCmd);
1042
1043         spin_unlock_irqrestore(&tp->lock, flags);
1044
1045         return 0;
1046 }
1047
1048 #ifdef CONFIG_R8169_VLAN
1049
1050 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1051                                       struct sk_buff *skb)
1052 {
1053         return (vlan_tx_tag_present(skb)) ?
1054                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1055 }
1056
1057 static void rtl8169_vlan_rx_register(struct net_device *dev,
1058                                      struct vlan_group *grp)
1059 {
1060         struct rtl8169_private *tp = netdev_priv(dev);
1061         void __iomem *ioaddr = tp->mmio_addr;
1062         unsigned long flags;
1063
1064         spin_lock_irqsave(&tp->lock, flags);
1065         tp->vlgrp = grp;
1066         /*
1067          * Do not disable RxVlan on 8110SCd.
1068          */
1069         if (tp->vlgrp || (tp->mac_version == RTL_GIGA_MAC_VER_05))
1070                 tp->cp_cmd |= RxVlan;
1071         else
1072                 tp->cp_cmd &= ~RxVlan;
1073         RTL_W16(CPlusCmd, tp->cp_cmd);
1074         RTL_R16(CPlusCmd);
1075         spin_unlock_irqrestore(&tp->lock, flags);
1076 }
1077
1078 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1079                                struct sk_buff *skb, int polling)
1080 {
1081         u32 opts2 = le32_to_cpu(desc->opts2);
1082         struct vlan_group *vlgrp = tp->vlgrp;
1083         int ret;
1084
1085         if (vlgrp && (opts2 & RxVlanTag)) {
1086                 u16 vtag = swab16(opts2 & 0xffff);
1087
1088                 if (likely(polling))
1089                         vlan_gro_receive(&tp->napi, vlgrp, vtag, skb);
1090                 else
1091                         __vlan_hwaccel_rx(skb, vlgrp, vtag, polling);
1092                 ret = 0;
1093         } else
1094                 ret = -1;
1095         desc->opts2 = 0;
1096         return ret;
1097 }
1098
1099 #else /* !CONFIG_R8169_VLAN */
1100
1101 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1102                                       struct sk_buff *skb)
1103 {
1104         return 0;
1105 }
1106
1107 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1108                                struct sk_buff *skb, int polling)
1109 {
1110         return -1;
1111 }
1112
1113 #endif
1114
1115 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1116 {
1117         struct rtl8169_private *tp = netdev_priv(dev);
1118         void __iomem *ioaddr = tp->mmio_addr;
1119         u32 status;
1120
1121         cmd->supported =
1122                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1123         cmd->port = PORT_FIBRE;
1124         cmd->transceiver = XCVR_INTERNAL;
1125
1126         status = RTL_R32(TBICSR);
1127         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
1128         cmd->autoneg = !!(status & TBINwEnable);
1129
1130         cmd->speed = SPEED_1000;
1131         cmd->duplex = DUPLEX_FULL; /* Always set */
1132
1133         return 0;
1134 }
1135
1136 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1137 {
1138         struct rtl8169_private *tp = netdev_priv(dev);
1139
1140         return mii_ethtool_gset(&tp->mii, cmd);
1141 }
1142
1143 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1144 {
1145         struct rtl8169_private *tp = netdev_priv(dev);
1146         unsigned long flags;
1147         int rc;
1148
1149         spin_lock_irqsave(&tp->lock, flags);
1150
1151         rc = tp->get_settings(dev, cmd);
1152
1153         spin_unlock_irqrestore(&tp->lock, flags);
1154         return rc;
1155 }
1156
1157 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1158                              void *p)
1159 {
1160         struct rtl8169_private *tp = netdev_priv(dev);
1161         unsigned long flags;
1162
1163         if (regs->len > R8169_REGS_SIZE)
1164                 regs->len = R8169_REGS_SIZE;
1165
1166         spin_lock_irqsave(&tp->lock, flags);
1167         memcpy_fromio(p, tp->mmio_addr, regs->len);
1168         spin_unlock_irqrestore(&tp->lock, flags);
1169 }
1170
1171 static u32 rtl8169_get_msglevel(struct net_device *dev)
1172 {
1173         struct rtl8169_private *tp = netdev_priv(dev);
1174
1175         return tp->msg_enable;
1176 }
1177
1178 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1179 {
1180         struct rtl8169_private *tp = netdev_priv(dev);
1181
1182         tp->msg_enable = value;
1183 }
1184
1185 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1186         "tx_packets",
1187         "rx_packets",
1188         "tx_errors",
1189         "rx_errors",
1190         "rx_missed",
1191         "align_errors",
1192         "tx_single_collisions",
1193         "tx_multi_collisions",
1194         "unicast",
1195         "broadcast",
1196         "multicast",
1197         "tx_aborted",
1198         "tx_underrun",
1199 };
1200
1201 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1202 {
1203         switch (sset) {
1204         case ETH_SS_STATS:
1205                 return ARRAY_SIZE(rtl8169_gstrings);
1206         default:
1207                 return -EOPNOTSUPP;
1208         }
1209 }
1210
1211 static void rtl8169_update_counters(struct net_device *dev)
1212 {
1213         struct rtl8169_private *tp = netdev_priv(dev);
1214         void __iomem *ioaddr = tp->mmio_addr;
1215         struct rtl8169_counters *counters;
1216         dma_addr_t paddr;
1217         u32 cmd;
1218         int wait = 1000;
1219         struct device *d = &tp->pci_dev->dev;
1220
1221         /*
1222          * Some chips are unable to dump tally counters when the receiver
1223          * is disabled.
1224          */
1225         if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1226                 return;
1227
1228         counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1229         if (!counters)
1230                 return;
1231
1232         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1233         cmd = (u64)paddr & DMA_BIT_MASK(32);
1234         RTL_W32(CounterAddrLow, cmd);
1235         RTL_W32(CounterAddrLow, cmd | CounterDump);
1236
1237         while (wait--) {
1238                 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1239                         /* copy updated counters */
1240                         memcpy(&tp->counters, counters, sizeof(*counters));
1241                         break;
1242                 }
1243                 udelay(10);
1244         }
1245
1246         RTL_W32(CounterAddrLow, 0);
1247         RTL_W32(CounterAddrHigh, 0);
1248
1249         dma_free_coherent(d, sizeof(*counters), counters, paddr);
1250 }
1251
1252 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1253                                       struct ethtool_stats *stats, u64 *data)
1254 {
1255         struct rtl8169_private *tp = netdev_priv(dev);
1256
1257         ASSERT_RTNL();
1258
1259         rtl8169_update_counters(dev);
1260
1261         data[0] = le64_to_cpu(tp->counters.tx_packets);
1262         data[1] = le64_to_cpu(tp->counters.rx_packets);
1263         data[2] = le64_to_cpu(tp->counters.tx_errors);
1264         data[3] = le32_to_cpu(tp->counters.rx_errors);
1265         data[4] = le16_to_cpu(tp->counters.rx_missed);
1266         data[5] = le16_to_cpu(tp->counters.align_errors);
1267         data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1268         data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1269         data[8] = le64_to_cpu(tp->counters.rx_unicast);
1270         data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1271         data[10] = le32_to_cpu(tp->counters.rx_multicast);
1272         data[11] = le16_to_cpu(tp->counters.tx_aborted);
1273         data[12] = le16_to_cpu(tp->counters.tx_underun);
1274 }
1275
1276 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1277 {
1278         switch(stringset) {
1279         case ETH_SS_STATS:
1280                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1281                 break;
1282         }
1283 }
1284
1285 static const struct ethtool_ops rtl8169_ethtool_ops = {
1286         .get_drvinfo            = rtl8169_get_drvinfo,
1287         .get_regs_len           = rtl8169_get_regs_len,
1288         .get_link               = ethtool_op_get_link,
1289         .get_settings           = rtl8169_get_settings,
1290         .set_settings           = rtl8169_set_settings,
1291         .get_msglevel           = rtl8169_get_msglevel,
1292         .set_msglevel           = rtl8169_set_msglevel,
1293         .get_rx_csum            = rtl8169_get_rx_csum,
1294         .set_rx_csum            = rtl8169_set_rx_csum,
1295         .set_tx_csum            = ethtool_op_set_tx_csum,
1296         .set_sg                 = ethtool_op_set_sg,
1297         .set_tso                = ethtool_op_set_tso,
1298         .get_regs               = rtl8169_get_regs,
1299         .get_wol                = rtl8169_get_wol,
1300         .set_wol                = rtl8169_set_wol,
1301         .get_strings            = rtl8169_get_strings,
1302         .get_sset_count         = rtl8169_get_sset_count,
1303         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1304 };
1305
1306 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1307                                     void __iomem *ioaddr)
1308 {
1309         /*
1310          * The driver currently handles the 8168Bf and the 8168Be identically
1311          * but they can be identified more specifically through the test below
1312          * if needed:
1313          *
1314          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1315          *
1316          * Same thing for the 8101Eb and the 8101Ec:
1317          *
1318          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1319          */
1320         static const struct {
1321                 u32 mask;
1322                 u32 val;
1323                 int mac_version;
1324         } mac_info[] = {
1325                 /* 8168D family. */
1326                 { 0x7cf00000, 0x28300000,       RTL_GIGA_MAC_VER_26 },
1327                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
1328                 { 0x7c800000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
1329                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
1330
1331                 /* 8168C family. */
1332                 { 0x7cf00000, 0x3cb00000,       RTL_GIGA_MAC_VER_24 },
1333                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
1334                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
1335                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
1336                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
1337                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
1338                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
1339                 { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
1340                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
1341
1342                 /* 8168B family. */
1343                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
1344                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
1345                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
1346                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
1347
1348                 /* 8101 family. */
1349                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
1350                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
1351                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
1352                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
1353                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
1354                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
1355                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
1356                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
1357                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
1358                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
1359                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
1360                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
1361                 /* FIXME: where did these entries come from ? -- FR */
1362                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
1363                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
1364
1365                 /* 8110 family. */
1366                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
1367                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
1368                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
1369                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
1370                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
1371                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
1372
1373                 /* Catch-all */
1374                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
1375         }, *p = mac_info;
1376         u32 reg;
1377
1378         reg = RTL_R32(TxConfig);
1379         while ((reg & p->mask) != p->val)
1380                 p++;
1381         tp->mac_version = p->mac_version;
1382 }
1383
1384 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1385 {
1386         dprintk("mac_version = 0x%02x\n", tp->mac_version);
1387 }
1388
1389 struct phy_reg {
1390         u16 reg;
1391         u16 val;
1392 };
1393
1394 static void rtl_phy_write(void __iomem *ioaddr, const struct phy_reg *regs, int len)
1395 {
1396         while (len-- > 0) {
1397                 mdio_write(ioaddr, regs->reg, regs->val);
1398                 regs++;
1399         }
1400 }
1401
1402 #define PHY_READ                0x00000000
1403 #define PHY_DATA_OR             0x10000000
1404 #define PHY_DATA_AND            0x20000000
1405 #define PHY_BJMPN               0x30000000
1406 #define PHY_READ_EFUSE          0x40000000
1407 #define PHY_READ_MAC_BYTE       0x50000000
1408 #define PHY_WRITE_MAC_BYTE      0x60000000
1409 #define PHY_CLEAR_READCOUNT     0x70000000
1410 #define PHY_WRITE               0x80000000
1411 #define PHY_READCOUNT_EQ_SKIP   0x90000000
1412 #define PHY_COMP_EQ_SKIPN       0xa0000000
1413 #define PHY_COMP_NEQ_SKIPN      0xb0000000
1414 #define PHY_WRITE_PREVIOUS      0xc0000000
1415 #define PHY_SKIPN               0xd0000000
1416 #define PHY_DELAY_MS            0xe0000000
1417 #define PHY_WRITE_ERI_WORD      0xf0000000
1418
1419 static void
1420 rtl_phy_write_fw(struct rtl8169_private *tp, const struct firmware *fw)
1421 {
1422         void __iomem *ioaddr = tp->mmio_addr;
1423         __le32 *phytable = (__le32 *)fw->data;
1424         struct net_device *dev = tp->dev;
1425         size_t i;
1426
1427         if (fw->size % sizeof(*phytable)) {
1428                 netif_err(tp, probe, dev, "odd sized firmware %zd\n", fw->size);
1429                 return;
1430         }
1431
1432         for (i = 0; i < fw->size / sizeof(*phytable); i++) {
1433                 u32 action = le32_to_cpu(phytable[i]);
1434
1435                 if (!action)
1436                         break;
1437
1438                 if ((action & 0xf0000000) != PHY_WRITE) {
1439                         netif_err(tp, probe, dev,
1440                                   "unknown action 0x%08x\n", action);
1441                         return;
1442                 }
1443         }
1444
1445         while (i-- != 0) {
1446                 u32 action = le32_to_cpu(*phytable);
1447                 u32 data = action & 0x0000ffff;
1448                 u32 reg = (action & 0x0fff0000) >> 16;
1449
1450                 switch(action & 0xf0000000) {
1451                 case PHY_WRITE:
1452                         mdio_write(ioaddr, reg, data);
1453                         phytable++;
1454                         break;
1455                 default:
1456                         BUG();
1457                 }
1458         }
1459 }
1460
1461 static void rtl8169s_hw_phy_config(void __iomem *ioaddr)
1462 {
1463         static const struct phy_reg phy_reg_init[] = {
1464                 { 0x1f, 0x0001 },
1465                 { 0x06, 0x006e },
1466                 { 0x08, 0x0708 },
1467                 { 0x15, 0x4000 },
1468                 { 0x18, 0x65c7 },
1469
1470                 { 0x1f, 0x0001 },
1471                 { 0x03, 0x00a1 },
1472                 { 0x02, 0x0008 },
1473                 { 0x01, 0x0120 },
1474                 { 0x00, 0x1000 },
1475                 { 0x04, 0x0800 },
1476                 { 0x04, 0x0000 },
1477
1478                 { 0x03, 0xff41 },
1479                 { 0x02, 0xdf60 },
1480                 { 0x01, 0x0140 },
1481                 { 0x00, 0x0077 },
1482                 { 0x04, 0x7800 },
1483                 { 0x04, 0x7000 },
1484
1485                 { 0x03, 0x802f },
1486                 { 0x02, 0x4f02 },
1487                 { 0x01, 0x0409 },
1488                 { 0x00, 0xf0f9 },
1489                 { 0x04, 0x9800 },
1490                 { 0x04, 0x9000 },
1491
1492                 { 0x03, 0xdf01 },
1493                 { 0x02, 0xdf20 },
1494                 { 0x01, 0xff95 },
1495                 { 0x00, 0xba00 },
1496                 { 0x04, 0xa800 },
1497                 { 0x04, 0xa000 },
1498
1499                 { 0x03, 0xff41 },
1500                 { 0x02, 0xdf20 },
1501                 { 0x01, 0x0140 },
1502                 { 0x00, 0x00bb },
1503                 { 0x04, 0xb800 },
1504                 { 0x04, 0xb000 },
1505
1506                 { 0x03, 0xdf41 },
1507                 { 0x02, 0xdc60 },
1508                 { 0x01, 0x6340 },
1509                 { 0x00, 0x007d },
1510                 { 0x04, 0xd800 },
1511                 { 0x04, 0xd000 },
1512
1513                 { 0x03, 0xdf01 },
1514                 { 0x02, 0xdf20 },
1515                 { 0x01, 0x100a },
1516                 { 0x00, 0xa0ff },
1517                 { 0x04, 0xf800 },
1518                 { 0x04, 0xf000 },
1519
1520                 { 0x1f, 0x0000 },
1521                 { 0x0b, 0x0000 },
1522                 { 0x00, 0x9200 }
1523         };
1524
1525         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1526 }
1527
1528 static void rtl8169sb_hw_phy_config(void __iomem *ioaddr)
1529 {
1530         static const struct phy_reg phy_reg_init[] = {
1531                 { 0x1f, 0x0002 },
1532                 { 0x01, 0x90d0 },
1533                 { 0x1f, 0x0000 }
1534         };
1535
1536         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1537 }
1538
1539 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp,
1540                                            void __iomem *ioaddr)
1541 {
1542         struct pci_dev *pdev = tp->pci_dev;
1543         u16 vendor_id, device_id;
1544
1545         pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
1546         pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
1547
1548         if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
1549                 return;
1550
1551         mdio_write(ioaddr, 0x1f, 0x0001);
1552         mdio_write(ioaddr, 0x10, 0xf01b);
1553         mdio_write(ioaddr, 0x1f, 0x0000);
1554 }
1555
1556 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp,
1557                                      void __iomem *ioaddr)
1558 {
1559         static const struct phy_reg phy_reg_init[] = {
1560                 { 0x1f, 0x0001 },
1561                 { 0x04, 0x0000 },
1562                 { 0x03, 0x00a1 },
1563                 { 0x02, 0x0008 },
1564                 { 0x01, 0x0120 },
1565                 { 0x00, 0x1000 },
1566                 { 0x04, 0x0800 },
1567                 { 0x04, 0x9000 },
1568                 { 0x03, 0x802f },
1569                 { 0x02, 0x4f02 },
1570                 { 0x01, 0x0409 },
1571                 { 0x00, 0xf099 },
1572                 { 0x04, 0x9800 },
1573                 { 0x04, 0xa000 },
1574                 { 0x03, 0xdf01 },
1575                 { 0x02, 0xdf20 },
1576                 { 0x01, 0xff95 },
1577                 { 0x00, 0xba00 },
1578                 { 0x04, 0xa800 },
1579                 { 0x04, 0xf000 },
1580                 { 0x03, 0xdf01 },
1581                 { 0x02, 0xdf20 },
1582                 { 0x01, 0x101a },
1583                 { 0x00, 0xa0ff },
1584                 { 0x04, 0xf800 },
1585                 { 0x04, 0x0000 },
1586                 { 0x1f, 0x0000 },
1587
1588                 { 0x1f, 0x0001 },
1589                 { 0x10, 0xf41b },
1590                 { 0x14, 0xfb54 },
1591                 { 0x18, 0xf5c7 },
1592                 { 0x1f, 0x0000 },
1593
1594                 { 0x1f, 0x0001 },
1595                 { 0x17, 0x0cc0 },
1596                 { 0x1f, 0x0000 }
1597         };
1598
1599         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1600
1601         rtl8169scd_hw_phy_config_quirk(tp, ioaddr);
1602 }
1603
1604 static void rtl8169sce_hw_phy_config(void __iomem *ioaddr)
1605 {
1606         static const struct phy_reg phy_reg_init[] = {
1607                 { 0x1f, 0x0001 },
1608                 { 0x04, 0x0000 },
1609                 { 0x03, 0x00a1 },
1610                 { 0x02, 0x0008 },
1611                 { 0x01, 0x0120 },
1612                 { 0x00, 0x1000 },
1613                 { 0x04, 0x0800 },
1614                 { 0x04, 0x9000 },
1615                 { 0x03, 0x802f },
1616                 { 0x02, 0x4f02 },
1617                 { 0x01, 0x0409 },
1618                 { 0x00, 0xf099 },
1619                 { 0x04, 0x9800 },
1620                 { 0x04, 0xa000 },
1621                 { 0x03, 0xdf01 },
1622                 { 0x02, 0xdf20 },
1623                 { 0x01, 0xff95 },
1624                 { 0x00, 0xba00 },
1625                 { 0x04, 0xa800 },
1626                 { 0x04, 0xf000 },
1627                 { 0x03, 0xdf01 },
1628                 { 0x02, 0xdf20 },
1629                 { 0x01, 0x101a },
1630                 { 0x00, 0xa0ff },
1631                 { 0x04, 0xf800 },
1632                 { 0x04, 0x0000 },
1633                 { 0x1f, 0x0000 },
1634
1635                 { 0x1f, 0x0001 },
1636                 { 0x0b, 0x8480 },
1637                 { 0x1f, 0x0000 },
1638
1639                 { 0x1f, 0x0001 },
1640                 { 0x18, 0x67c7 },
1641                 { 0x04, 0x2000 },
1642                 { 0x03, 0x002f },
1643                 { 0x02, 0x4360 },
1644                 { 0x01, 0x0109 },
1645                 { 0x00, 0x3022 },
1646                 { 0x04, 0x2800 },
1647                 { 0x1f, 0x0000 },
1648
1649                 { 0x1f, 0x0001 },
1650                 { 0x17, 0x0cc0 },
1651                 { 0x1f, 0x0000 }
1652         };
1653
1654         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1655 }
1656
1657 static void rtl8168bb_hw_phy_config(void __iomem *ioaddr)
1658 {
1659         static const struct phy_reg phy_reg_init[] = {
1660                 { 0x10, 0xf41b },
1661                 { 0x1f, 0x0000 }
1662         };
1663
1664         mdio_write(ioaddr, 0x1f, 0x0001);
1665         mdio_patch(ioaddr, 0x16, 1 << 0);
1666
1667         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1668 }
1669
1670 static void rtl8168bef_hw_phy_config(void __iomem *ioaddr)
1671 {
1672         static const struct phy_reg phy_reg_init[] = {
1673                 { 0x1f, 0x0001 },
1674                 { 0x10, 0xf41b },
1675                 { 0x1f, 0x0000 }
1676         };
1677
1678         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1679 }
1680
1681 static void rtl8168cp_1_hw_phy_config(void __iomem *ioaddr)
1682 {
1683         static const struct phy_reg phy_reg_init[] = {
1684                 { 0x1f, 0x0000 },
1685                 { 0x1d, 0x0f00 },
1686                 { 0x1f, 0x0002 },
1687                 { 0x0c, 0x1ec8 },
1688                 { 0x1f, 0x0000 }
1689         };
1690
1691         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1692 }
1693
1694 static void rtl8168cp_2_hw_phy_config(void __iomem *ioaddr)
1695 {
1696         static const struct phy_reg phy_reg_init[] = {
1697                 { 0x1f, 0x0001 },
1698                 { 0x1d, 0x3d98 },
1699                 { 0x1f, 0x0000 }
1700         };
1701
1702         mdio_write(ioaddr, 0x1f, 0x0000);
1703         mdio_patch(ioaddr, 0x14, 1 << 5);
1704         mdio_patch(ioaddr, 0x0d, 1 << 5);
1705
1706         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1707 }
1708
1709 static void rtl8168c_1_hw_phy_config(void __iomem *ioaddr)
1710 {
1711         static const struct phy_reg phy_reg_init[] = {
1712                 { 0x1f, 0x0001 },
1713                 { 0x12, 0x2300 },
1714                 { 0x1f, 0x0002 },
1715                 { 0x00, 0x88d4 },
1716                 { 0x01, 0x82b1 },
1717                 { 0x03, 0x7002 },
1718                 { 0x08, 0x9e30 },
1719                 { 0x09, 0x01f0 },
1720                 { 0x0a, 0x5500 },
1721                 { 0x0c, 0x00c8 },
1722                 { 0x1f, 0x0003 },
1723                 { 0x12, 0xc096 },
1724                 { 0x16, 0x000a },
1725                 { 0x1f, 0x0000 },
1726                 { 0x1f, 0x0000 },
1727                 { 0x09, 0x2000 },
1728                 { 0x09, 0x0000 }
1729         };
1730
1731         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1732
1733         mdio_patch(ioaddr, 0x14, 1 << 5);
1734         mdio_patch(ioaddr, 0x0d, 1 << 5);
1735         mdio_write(ioaddr, 0x1f, 0x0000);
1736 }
1737
1738 static void rtl8168c_2_hw_phy_config(void __iomem *ioaddr)
1739 {
1740         static const struct phy_reg phy_reg_init[] = {
1741                 { 0x1f, 0x0001 },
1742                 { 0x12, 0x2300 },
1743                 { 0x03, 0x802f },
1744                 { 0x02, 0x4f02 },
1745                 { 0x01, 0x0409 },
1746                 { 0x00, 0xf099 },
1747                 { 0x04, 0x9800 },
1748                 { 0x04, 0x9000 },
1749                 { 0x1d, 0x3d98 },
1750                 { 0x1f, 0x0002 },
1751                 { 0x0c, 0x7eb8 },
1752                 { 0x06, 0x0761 },
1753                 { 0x1f, 0x0003 },
1754                 { 0x16, 0x0f0a },
1755                 { 0x1f, 0x0000 }
1756         };
1757
1758         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1759
1760         mdio_patch(ioaddr, 0x16, 1 << 0);
1761         mdio_patch(ioaddr, 0x14, 1 << 5);
1762         mdio_patch(ioaddr, 0x0d, 1 << 5);
1763         mdio_write(ioaddr, 0x1f, 0x0000);
1764 }
1765
1766 static void rtl8168c_3_hw_phy_config(void __iomem *ioaddr)
1767 {
1768         static const struct phy_reg phy_reg_init[] = {
1769                 { 0x1f, 0x0001 },
1770                 { 0x12, 0x2300 },
1771                 { 0x1d, 0x3d98 },
1772                 { 0x1f, 0x0002 },
1773                 { 0x0c, 0x7eb8 },
1774                 { 0x06, 0x5461 },
1775                 { 0x1f, 0x0003 },
1776                 { 0x16, 0x0f0a },
1777                 { 0x1f, 0x0000 }
1778         };
1779
1780         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1781
1782         mdio_patch(ioaddr, 0x16, 1 << 0);
1783         mdio_patch(ioaddr, 0x14, 1 << 5);
1784         mdio_patch(ioaddr, 0x0d, 1 << 5);
1785         mdio_write(ioaddr, 0x1f, 0x0000);
1786 }
1787
1788 static void rtl8168c_4_hw_phy_config(void __iomem *ioaddr)
1789 {
1790         rtl8168c_3_hw_phy_config(ioaddr);
1791 }
1792
1793 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
1794 {
1795         static const struct phy_reg phy_reg_init_0[] = {
1796                 /* Channel Estimation */
1797                 { 0x1f, 0x0001 },
1798                 { 0x06, 0x4064 },
1799                 { 0x07, 0x2863 },
1800                 { 0x08, 0x059c },
1801                 { 0x09, 0x26b4 },
1802                 { 0x0a, 0x6a19 },
1803                 { 0x0b, 0xdcc8 },
1804                 { 0x10, 0xf06d },
1805                 { 0x14, 0x7f68 },
1806                 { 0x18, 0x7fd9 },
1807                 { 0x1c, 0xf0ff },
1808                 { 0x1d, 0x3d9c },
1809                 { 0x1f, 0x0003 },
1810                 { 0x12, 0xf49f },
1811                 { 0x13, 0x070b },
1812                 { 0x1a, 0x05ad },
1813                 { 0x14, 0x94c0 },
1814
1815                 /*
1816                  * Tx Error Issue
1817                  * enhance line driver power
1818                  */
1819                 { 0x1f, 0x0002 },
1820                 { 0x06, 0x5561 },
1821                 { 0x1f, 0x0005 },
1822                 { 0x05, 0x8332 },
1823                 { 0x06, 0x5561 },
1824
1825                 /*
1826                  * Can not link to 1Gbps with bad cable
1827                  * Decrease SNR threshold form 21.07dB to 19.04dB
1828                  */
1829                 { 0x1f, 0x0001 },
1830                 { 0x17, 0x0cc0 },
1831
1832                 { 0x1f, 0x0000 },
1833                 { 0x0d, 0xf880 }
1834         };
1835         void __iomem *ioaddr = tp->mmio_addr;
1836         const struct firmware *fw;
1837
1838         rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
1839
1840         /*
1841          * Rx Error Issue
1842          * Fine Tune Switching regulator parameter
1843          */
1844         mdio_write(ioaddr, 0x1f, 0x0002);
1845         mdio_plus_minus(ioaddr, 0x0b, 0x0010, 0x00ef);
1846         mdio_plus_minus(ioaddr, 0x0c, 0xa200, 0x5d00);
1847
1848         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
1849                 static const struct phy_reg phy_reg_init[] = {
1850                         { 0x1f, 0x0002 },
1851                         { 0x05, 0x669a },
1852                         { 0x1f, 0x0005 },
1853                         { 0x05, 0x8330 },
1854                         { 0x06, 0x669a },
1855                         { 0x1f, 0x0002 }
1856                 };
1857                 int val;
1858
1859                 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1860
1861                 val = mdio_read(ioaddr, 0x0d);
1862
1863                 if ((val & 0x00ff) != 0x006c) {
1864                         static const u32 set[] = {
1865                                 0x0065, 0x0066, 0x0067, 0x0068,
1866                                 0x0069, 0x006a, 0x006b, 0x006c
1867                         };
1868                         int i;
1869
1870                         mdio_write(ioaddr, 0x1f, 0x0002);
1871
1872                         val &= 0xff00;
1873                         for (i = 0; i < ARRAY_SIZE(set); i++)
1874                                 mdio_write(ioaddr, 0x0d, val | set[i]);
1875                 }
1876         } else {
1877                 static const struct phy_reg phy_reg_init[] = {
1878                         { 0x1f, 0x0002 },
1879                         { 0x05, 0x6662 },
1880                         { 0x1f, 0x0005 },
1881                         { 0x05, 0x8330 },
1882                         { 0x06, 0x6662 }
1883                 };
1884
1885                 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1886         }
1887
1888         /* RSET couple improve */
1889         mdio_write(ioaddr, 0x1f, 0x0002);
1890         mdio_patch(ioaddr, 0x0d, 0x0300);
1891         mdio_patch(ioaddr, 0x0f, 0x0010);
1892
1893         /* Fine tune PLL performance */
1894         mdio_write(ioaddr, 0x1f, 0x0002);
1895         mdio_plus_minus(ioaddr, 0x02, 0x0100, 0x0600);
1896         mdio_plus_minus(ioaddr, 0x03, 0x0000, 0xe000);
1897
1898         mdio_write(ioaddr, 0x1f, 0x0005);
1899         mdio_write(ioaddr, 0x05, 0x001b);
1900         if (mdio_read(ioaddr, 0x06) == 0xbf00 &&
1901             request_firmware(&fw, FIRMWARE_8168D_1, &tp->pci_dev->dev) == 0) {
1902                 rtl_phy_write_fw(tp, fw);
1903                 release_firmware(fw);
1904         } else {
1905                 netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n");
1906         }
1907
1908         mdio_write(ioaddr, 0x1f, 0x0000);
1909 }
1910
1911 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
1912 {
1913         static const struct phy_reg phy_reg_init_0[] = {
1914                 /* Channel Estimation */
1915                 { 0x1f, 0x0001 },
1916                 { 0x06, 0x4064 },
1917                 { 0x07, 0x2863 },
1918                 { 0x08, 0x059c },
1919                 { 0x09, 0x26b4 },
1920                 { 0x0a, 0x6a19 },
1921                 { 0x0b, 0xdcc8 },
1922                 { 0x10, 0xf06d },
1923                 { 0x14, 0x7f68 },
1924                 { 0x18, 0x7fd9 },
1925                 { 0x1c, 0xf0ff },
1926                 { 0x1d, 0x3d9c },
1927                 { 0x1f, 0x0003 },
1928                 { 0x12, 0xf49f },
1929                 { 0x13, 0x070b },
1930                 { 0x1a, 0x05ad },
1931                 { 0x14, 0x94c0 },
1932
1933                 /*
1934                  * Tx Error Issue
1935                  * enhance line driver power
1936                  */
1937                 { 0x1f, 0x0002 },
1938                 { 0x06, 0x5561 },
1939                 { 0x1f, 0x0005 },
1940                 { 0x05, 0x8332 },
1941                 { 0x06, 0x5561 },
1942
1943                 /*
1944                  * Can not link to 1Gbps with bad cable
1945                  * Decrease SNR threshold form 21.07dB to 19.04dB
1946                  */
1947                 { 0x1f, 0x0001 },
1948                 { 0x17, 0x0cc0 },
1949
1950                 { 0x1f, 0x0000 },
1951                 { 0x0d, 0xf880 }
1952         };
1953         void __iomem *ioaddr = tp->mmio_addr;
1954         const struct firmware *fw;
1955
1956         rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
1957
1958         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
1959                 static const struct phy_reg phy_reg_init[] = {
1960                         { 0x1f, 0x0002 },
1961                         { 0x05, 0x669a },
1962                         { 0x1f, 0x0005 },
1963                         { 0x05, 0x8330 },
1964                         { 0x06, 0x669a },
1965
1966                         { 0x1f, 0x0002 }
1967                 };
1968                 int val;
1969
1970                 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1971
1972                 val = mdio_read(ioaddr, 0x0d);
1973                 if ((val & 0x00ff) != 0x006c) {
1974                         static const u32 set[] = {
1975                                 0x0065, 0x0066, 0x0067, 0x0068,
1976                                 0x0069, 0x006a, 0x006b, 0x006c
1977                         };
1978                         int i;
1979
1980                         mdio_write(ioaddr, 0x1f, 0x0002);
1981
1982                         val &= 0xff00;
1983                         for (i = 0; i < ARRAY_SIZE(set); i++)
1984                                 mdio_write(ioaddr, 0x0d, val | set[i]);
1985                 }
1986         } else {
1987                 static const struct phy_reg phy_reg_init[] = {
1988                         { 0x1f, 0x0002 },
1989                         { 0x05, 0x2642 },
1990                         { 0x1f, 0x0005 },
1991                         { 0x05, 0x8330 },
1992                         { 0x06, 0x2642 }
1993                 };
1994
1995                 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1996         }
1997
1998         /* Fine tune PLL performance */
1999         mdio_write(ioaddr, 0x1f, 0x0002);
2000         mdio_plus_minus(ioaddr, 0x02, 0x0100, 0x0600);
2001         mdio_plus_minus(ioaddr, 0x03, 0x0000, 0xe000);
2002
2003         /* Switching regulator Slew rate */
2004         mdio_write(ioaddr, 0x1f, 0x0002);
2005         mdio_patch(ioaddr, 0x0f, 0x0017);
2006
2007         mdio_write(ioaddr, 0x1f, 0x0005);
2008         mdio_write(ioaddr, 0x05, 0x001b);
2009         if (mdio_read(ioaddr, 0x06) == 0xb300 &&
2010             request_firmware(&fw, FIRMWARE_8168D_2, &tp->pci_dev->dev) == 0) {
2011                 rtl_phy_write_fw(tp, fw);
2012                 release_firmware(fw);
2013         } else {
2014                 netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n");
2015         }
2016
2017         mdio_write(ioaddr, 0x1f, 0x0000);
2018 }
2019
2020 static void rtl8168d_3_hw_phy_config(void __iomem *ioaddr)
2021 {
2022         static const struct phy_reg phy_reg_init[] = {
2023                 { 0x1f, 0x0002 },
2024                 { 0x10, 0x0008 },
2025                 { 0x0d, 0x006c },
2026
2027                 { 0x1f, 0x0000 },
2028                 { 0x0d, 0xf880 },
2029
2030                 { 0x1f, 0x0001 },
2031                 { 0x17, 0x0cc0 },
2032
2033                 { 0x1f, 0x0001 },
2034                 { 0x0b, 0xa4d8 },
2035                 { 0x09, 0x281c },
2036                 { 0x07, 0x2883 },
2037                 { 0x0a, 0x6b35 },
2038                 { 0x1d, 0x3da4 },
2039                 { 0x1c, 0xeffd },
2040                 { 0x14, 0x7f52 },
2041                 { 0x18, 0x7fc6 },
2042                 { 0x08, 0x0601 },
2043                 { 0x06, 0x4063 },
2044                 { 0x10, 0xf074 },
2045                 { 0x1f, 0x0003 },
2046                 { 0x13, 0x0789 },
2047                 { 0x12, 0xf4bd },
2048                 { 0x1a, 0x04fd },
2049                 { 0x14, 0x84b0 },
2050                 { 0x1f, 0x0000 },
2051                 { 0x00, 0x9200 },
2052
2053                 { 0x1f, 0x0005 },
2054                 { 0x01, 0x0340 },
2055                 { 0x1f, 0x0001 },
2056                 { 0x04, 0x4000 },
2057                 { 0x03, 0x1d21 },
2058                 { 0x02, 0x0c32 },
2059                 { 0x01, 0x0200 },
2060                 { 0x00, 0x5554 },
2061                 { 0x04, 0x4800 },
2062                 { 0x04, 0x4000 },
2063                 { 0x04, 0xf000 },
2064                 { 0x03, 0xdf01 },
2065                 { 0x02, 0xdf20 },
2066                 { 0x01, 0x101a },
2067                 { 0x00, 0xa0ff },
2068                 { 0x04, 0xf800 },
2069                 { 0x04, 0xf000 },
2070                 { 0x1f, 0x0000 },
2071
2072                 { 0x1f, 0x0007 },
2073                 { 0x1e, 0x0023 },
2074                 { 0x16, 0x0000 },
2075                 { 0x1f, 0x0000 }
2076         };
2077
2078         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2079 }
2080
2081 static void rtl8102e_hw_phy_config(void __iomem *ioaddr)
2082 {
2083         static const struct phy_reg phy_reg_init[] = {
2084                 { 0x1f, 0x0003 },
2085                 { 0x08, 0x441d },
2086                 { 0x01, 0x9100 },
2087                 { 0x1f, 0x0000 }
2088         };
2089
2090         mdio_write(ioaddr, 0x1f, 0x0000);
2091         mdio_patch(ioaddr, 0x11, 1 << 12);
2092         mdio_patch(ioaddr, 0x19, 1 << 13);
2093         mdio_patch(ioaddr, 0x10, 1 << 15);
2094
2095         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2096 }
2097
2098 static void rtl_hw_phy_config(struct net_device *dev)
2099 {
2100         struct rtl8169_private *tp = netdev_priv(dev);
2101         void __iomem *ioaddr = tp->mmio_addr;
2102
2103         rtl8169_print_mac_version(tp);
2104
2105         switch (tp->mac_version) {
2106         case RTL_GIGA_MAC_VER_01:
2107                 break;
2108         case RTL_GIGA_MAC_VER_02:
2109         case RTL_GIGA_MAC_VER_03:
2110                 rtl8169s_hw_phy_config(ioaddr);
2111                 break;
2112         case RTL_GIGA_MAC_VER_04:
2113                 rtl8169sb_hw_phy_config(ioaddr);
2114                 break;
2115         case RTL_GIGA_MAC_VER_05:
2116                 rtl8169scd_hw_phy_config(tp, ioaddr);
2117                 break;
2118         case RTL_GIGA_MAC_VER_06:
2119                 rtl8169sce_hw_phy_config(ioaddr);
2120                 break;
2121         case RTL_GIGA_MAC_VER_07:
2122         case RTL_GIGA_MAC_VER_08:
2123         case RTL_GIGA_MAC_VER_09:
2124                 rtl8102e_hw_phy_config(ioaddr);
2125                 break;
2126         case RTL_GIGA_MAC_VER_11:
2127                 rtl8168bb_hw_phy_config(ioaddr);
2128                 break;
2129         case RTL_GIGA_MAC_VER_12:
2130                 rtl8168bef_hw_phy_config(ioaddr);
2131                 break;
2132         case RTL_GIGA_MAC_VER_17:
2133                 rtl8168bef_hw_phy_config(ioaddr);
2134                 break;
2135         case RTL_GIGA_MAC_VER_18:
2136                 rtl8168cp_1_hw_phy_config(ioaddr);
2137                 break;
2138         case RTL_GIGA_MAC_VER_19:
2139                 rtl8168c_1_hw_phy_config(ioaddr);
2140                 break;
2141         case RTL_GIGA_MAC_VER_20:
2142                 rtl8168c_2_hw_phy_config(ioaddr);
2143                 break;
2144         case RTL_GIGA_MAC_VER_21:
2145                 rtl8168c_3_hw_phy_config(ioaddr);
2146                 break;
2147         case RTL_GIGA_MAC_VER_22:
2148                 rtl8168c_4_hw_phy_config(ioaddr);
2149                 break;
2150         case RTL_GIGA_MAC_VER_23:
2151         case RTL_GIGA_MAC_VER_24:
2152                 rtl8168cp_2_hw_phy_config(ioaddr);
2153                 break;
2154         case RTL_GIGA_MAC_VER_25:
2155                 rtl8168d_1_hw_phy_config(tp);
2156                 break;
2157         case RTL_GIGA_MAC_VER_26:
2158                 rtl8168d_2_hw_phy_config(tp);
2159                 break;
2160         case RTL_GIGA_MAC_VER_27:
2161                 rtl8168d_3_hw_phy_config(ioaddr);
2162                 break;
2163
2164         default:
2165                 break;
2166         }
2167 }
2168
2169 static void rtl8169_phy_timer(unsigned long __opaque)
2170 {
2171         struct net_device *dev = (struct net_device *)__opaque;
2172         struct rtl8169_private *tp = netdev_priv(dev);
2173         struct timer_list *timer = &tp->timer;
2174         void __iomem *ioaddr = tp->mmio_addr;
2175         unsigned long timeout = RTL8169_PHY_TIMEOUT;
2176
2177         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
2178
2179         if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
2180                 return;
2181
2182         spin_lock_irq(&tp->lock);
2183
2184         if (tp->phy_reset_pending(ioaddr)) {
2185                 /*
2186                  * A busy loop could burn quite a few cycles on nowadays CPU.
2187                  * Let's delay the execution of the timer for a few ticks.
2188                  */
2189                 timeout = HZ/10;
2190                 goto out_mod_timer;
2191         }
2192
2193         if (tp->link_ok(ioaddr))
2194                 goto out_unlock;
2195
2196         netif_warn(tp, link, dev, "PHY reset until link up\n");
2197
2198         tp->phy_reset_enable(ioaddr);
2199
2200 out_mod_timer:
2201         mod_timer(timer, jiffies + timeout);
2202 out_unlock:
2203         spin_unlock_irq(&tp->lock);
2204 }
2205
2206 static inline void rtl8169_delete_timer(struct net_device *dev)
2207 {
2208         struct rtl8169_private *tp = netdev_priv(dev);
2209         struct timer_list *timer = &tp->timer;
2210
2211         if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
2212                 return;
2213
2214         del_timer_sync(timer);
2215 }
2216
2217 static inline void rtl8169_request_timer(struct net_device *dev)
2218 {
2219         struct rtl8169_private *tp = netdev_priv(dev);
2220         struct timer_list *timer = &tp->timer;
2221
2222         if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
2223                 return;
2224
2225         mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
2226 }
2227
2228 #ifdef CONFIG_NET_POLL_CONTROLLER
2229 /*
2230  * Polling 'interrupt' - used by things like netconsole to send skbs
2231  * without having to re-enable interrupts. It's not called while
2232  * the interrupt routine is executing.
2233  */
2234 static void rtl8169_netpoll(struct net_device *dev)
2235 {
2236         struct rtl8169_private *tp = netdev_priv(dev);
2237         struct pci_dev *pdev = tp->pci_dev;
2238
2239         disable_irq(pdev->irq);
2240         rtl8169_interrupt(pdev->irq, dev);
2241         enable_irq(pdev->irq);
2242 }
2243 #endif
2244
2245 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
2246                                   void __iomem *ioaddr)
2247 {
2248         iounmap(ioaddr);
2249         pci_release_regions(pdev);
2250         pci_clear_mwi(pdev);
2251         pci_disable_device(pdev);
2252         free_netdev(dev);
2253 }
2254
2255 static void rtl8169_phy_reset(struct net_device *dev,
2256                               struct rtl8169_private *tp)
2257 {
2258         void __iomem *ioaddr = tp->mmio_addr;
2259         unsigned int i;
2260
2261         tp->phy_reset_enable(ioaddr);
2262         for (i = 0; i < 100; i++) {
2263                 if (!tp->phy_reset_pending(ioaddr))
2264                         return;
2265                 msleep(1);
2266         }
2267         netif_err(tp, link, dev, "PHY reset failed\n");
2268 }
2269
2270 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
2271 {
2272         void __iomem *ioaddr = tp->mmio_addr;
2273
2274         rtl_hw_phy_config(dev);
2275
2276         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2277                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2278                 RTL_W8(0x82, 0x01);
2279         }
2280
2281         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2282
2283         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
2284                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
2285
2286         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
2287                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2288                 RTL_W8(0x82, 0x01);
2289                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
2290                 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
2291         }
2292
2293         rtl8169_phy_reset(dev, tp);
2294
2295         /*
2296          * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
2297          * only 8101. Don't panic.
2298          */
2299         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
2300
2301         if (RTL_R8(PHYstatus) & TBI_Enable)
2302                 netif_info(tp, link, dev, "TBI auto-negotiating\n");
2303 }
2304
2305 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2306 {
2307         void __iomem *ioaddr = tp->mmio_addr;
2308         u32 high;
2309         u32 low;
2310
2311         low  = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
2312         high = addr[4] | (addr[5] << 8);
2313
2314         spin_lock_irq(&tp->lock);
2315
2316         RTL_W8(Cfg9346, Cfg9346_Unlock);
2317
2318         RTL_W32(MAC4, high);
2319         RTL_R32(MAC4);
2320
2321         RTL_W32(MAC0, low);
2322         RTL_R32(MAC0);
2323
2324         RTL_W8(Cfg9346, Cfg9346_Lock);
2325
2326         spin_unlock_irq(&tp->lock);
2327 }
2328
2329 static int rtl_set_mac_address(struct net_device *dev, void *p)
2330 {
2331         struct rtl8169_private *tp = netdev_priv(dev);
2332         struct sockaddr *addr = p;
2333
2334         if (!is_valid_ether_addr(addr->sa_data))
2335                 return -EADDRNOTAVAIL;
2336
2337         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2338
2339         rtl_rar_set(tp, dev->dev_addr);
2340
2341         return 0;
2342 }
2343
2344 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2345 {
2346         struct rtl8169_private *tp = netdev_priv(dev);
2347         struct mii_ioctl_data *data = if_mii(ifr);
2348
2349         return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
2350 }
2351
2352 static int rtl_xmii_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2353 {
2354         switch (cmd) {
2355         case SIOCGMIIPHY:
2356                 data->phy_id = 32; /* Internal PHY */
2357                 return 0;
2358
2359         case SIOCGMIIREG:
2360                 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
2361                 return 0;
2362
2363         case SIOCSMIIREG:
2364                 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
2365                 return 0;
2366         }
2367         return -EOPNOTSUPP;
2368 }
2369
2370 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2371 {
2372         return -EOPNOTSUPP;
2373 }
2374
2375 static const struct rtl_cfg_info {
2376         void (*hw_start)(struct net_device *);
2377         unsigned int region;
2378         unsigned int align;
2379         u16 intr_event;
2380         u16 napi_event;
2381         unsigned features;
2382         u8 default_ver;
2383 } rtl_cfg_infos [] = {
2384         [RTL_CFG_0] = {
2385                 .hw_start       = rtl_hw_start_8169,
2386                 .region         = 1,
2387                 .align          = 0,
2388                 .intr_event     = SYSErr | LinkChg | RxOverflow |
2389                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2390                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2391                 .features       = RTL_FEATURE_GMII,
2392                 .default_ver    = RTL_GIGA_MAC_VER_01,
2393         },
2394         [RTL_CFG_1] = {
2395                 .hw_start       = rtl_hw_start_8168,
2396                 .region         = 2,
2397                 .align          = 8,
2398                 .intr_event     = SYSErr | LinkChg | RxOverflow |
2399                                   TxErr | TxOK | RxOK | RxErr,
2400                 .napi_event     = TxErr | TxOK | RxOK | RxOverflow,
2401                 .features       = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
2402                 .default_ver    = RTL_GIGA_MAC_VER_11,
2403         },
2404         [RTL_CFG_2] = {
2405                 .hw_start       = rtl_hw_start_8101,
2406                 .region         = 2,
2407                 .align          = 8,
2408                 .intr_event     = SYSErr | LinkChg | RxOverflow | PCSTimeout |
2409                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2410                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2411                 .features       = RTL_FEATURE_MSI,
2412                 .default_ver    = RTL_GIGA_MAC_VER_13,
2413         }
2414 };
2415
2416 /* Cfg9346_Unlock assumed. */
2417 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
2418                             const struct rtl_cfg_info *cfg)
2419 {
2420         unsigned msi = 0;
2421         u8 cfg2;
2422
2423         cfg2 = RTL_R8(Config2) & ~MSIEnable;
2424         if (cfg->features & RTL_FEATURE_MSI) {
2425                 if (pci_enable_msi(pdev)) {
2426                         dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
2427                 } else {
2428                         cfg2 |= MSIEnable;
2429                         msi = RTL_FEATURE_MSI;
2430                 }
2431         }
2432         RTL_W8(Config2, cfg2);
2433         return msi;
2434 }
2435
2436 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
2437 {
2438         if (tp->features & RTL_FEATURE_MSI) {
2439                 pci_disable_msi(pdev);
2440                 tp->features &= ~RTL_FEATURE_MSI;
2441         }
2442 }
2443
2444 static const struct net_device_ops rtl8169_netdev_ops = {
2445         .ndo_open               = rtl8169_open,
2446         .ndo_stop               = rtl8169_close,
2447         .ndo_get_stats          = rtl8169_get_stats,
2448         .ndo_start_xmit         = rtl8169_start_xmit,
2449         .ndo_tx_timeout         = rtl8169_tx_timeout,
2450         .ndo_validate_addr      = eth_validate_addr,
2451         .ndo_change_mtu         = rtl8169_change_mtu,
2452         .ndo_set_mac_address    = rtl_set_mac_address,
2453         .ndo_do_ioctl           = rtl8169_ioctl,
2454         .ndo_set_multicast_list = rtl_set_rx_mode,
2455 #ifdef CONFIG_R8169_VLAN
2456         .ndo_vlan_rx_register   = rtl8169_vlan_rx_register,
2457 #endif
2458 #ifdef CONFIG_NET_POLL_CONTROLLER
2459         .ndo_poll_controller    = rtl8169_netpoll,
2460 #endif
2461
2462 };
2463
2464 static int __devinit
2465 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2466 {
2467         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
2468         const unsigned int region = cfg->region;
2469         struct rtl8169_private *tp;
2470         struct mii_if_info *mii;
2471         struct net_device *dev;
2472         void __iomem *ioaddr;
2473         unsigned int i;
2474         int rc;
2475
2476         if (netif_msg_drv(&debug)) {
2477                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
2478                        MODULENAME, RTL8169_VERSION);
2479         }
2480
2481         dev = alloc_etherdev(sizeof (*tp));
2482         if (!dev) {
2483                 if (netif_msg_drv(&debug))
2484                         dev_err(&pdev->dev, "unable to alloc new ethernet\n");
2485                 rc = -ENOMEM;
2486                 goto out;
2487         }
2488
2489         SET_NETDEV_DEV(dev, &pdev->dev);
2490         dev->netdev_ops = &rtl8169_netdev_ops;
2491         tp = netdev_priv(dev);
2492         tp->dev = dev;
2493         tp->pci_dev = pdev;
2494         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
2495
2496         mii = &tp->mii;
2497         mii->dev = dev;
2498         mii->mdio_read = rtl_mdio_read;
2499         mii->mdio_write = rtl_mdio_write;
2500         mii->phy_id_mask = 0x1f;
2501         mii->reg_num_mask = 0x1f;
2502         mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
2503
2504         /* enable device (incl. PCI PM wakeup and hotplug setup) */
2505         rc = pci_enable_device(pdev);
2506         if (rc < 0) {
2507                 netif_err(tp, probe, dev, "enable failure\n");
2508                 goto err_out_free_dev_1;
2509         }
2510
2511         if (pci_set_mwi(pdev) < 0)
2512                 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
2513
2514         /* make sure PCI base addr 1 is MMIO */
2515         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
2516                 netif_err(tp, probe, dev,
2517                           "region #%d not an MMIO resource, aborting\n",
2518                           region);
2519                 rc = -ENODEV;
2520                 goto err_out_mwi_2;
2521         }
2522
2523         /* check for weird/broken PCI region reporting */
2524         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
2525                 netif_err(tp, probe, dev,
2526                           "Invalid PCI region size(s), aborting\n");
2527                 rc = -ENODEV;
2528                 goto err_out_mwi_2;
2529         }
2530
2531         rc = pci_request_regions(pdev, MODULENAME);
2532         if (rc < 0) {
2533                 netif_err(tp, probe, dev, "could not request regions\n");
2534                 goto err_out_mwi_2;
2535         }
2536
2537         tp->cp_cmd = PCIMulRW | RxChkSum;
2538
2539         if ((sizeof(dma_addr_t) > 4) &&
2540             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
2541                 tp->cp_cmd |= PCIDAC;
2542                 dev->features |= NETIF_F_HIGHDMA;
2543         } else {
2544                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2545                 if (rc < 0) {
2546                         netif_err(tp, probe, dev, "DMA configuration failed\n");
2547                         goto err_out_free_res_3;
2548                 }
2549         }
2550
2551         /* ioremap MMIO region */
2552         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
2553         if (!ioaddr) {
2554                 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
2555                 rc = -EIO;
2556                 goto err_out_free_res_3;
2557         }
2558
2559         tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2560         if (!tp->pcie_cap)
2561                 netif_info(tp, probe, dev, "no PCI Express capability\n");
2562
2563         RTL_W16(IntrMask, 0x0000);
2564
2565         /* Soft reset the chip. */
2566         RTL_W8(ChipCmd, CmdReset);
2567
2568         /* Check that the chip has finished the reset. */
2569         for (i = 0; i < 100; i++) {
2570                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
2571                         break;
2572                 msleep_interruptible(1);
2573         }
2574
2575         RTL_W16(IntrStatus, 0xffff);
2576
2577         pci_set_master(pdev);
2578
2579         /* Identify chip attached to board */
2580         rtl8169_get_mac_version(tp, ioaddr);
2581
2582         /* Use appropriate default if unknown */
2583         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2584                 netif_notice(tp, probe, dev,
2585                              "unknown MAC, using family default\n");
2586                 tp->mac_version = cfg->default_ver;
2587         }
2588
2589         rtl8169_print_mac_version(tp);
2590
2591         for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
2592                 if (tp->mac_version == rtl_chip_info[i].mac_version)
2593                         break;
2594         }
2595         if (i == ARRAY_SIZE(rtl_chip_info)) {
2596                 dev_err(&pdev->dev,
2597                         "driver bug, MAC version not found in rtl_chip_info\n");
2598                 goto err_out_msi_4;
2599         }
2600         tp->chipset = i;
2601
2602         RTL_W8(Cfg9346, Cfg9346_Unlock);
2603         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
2604         RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
2605         if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
2606                 tp->features |= RTL_FEATURE_WOL;
2607         if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
2608                 tp->features |= RTL_FEATURE_WOL;
2609         tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
2610         RTL_W8(Cfg9346, Cfg9346_Lock);
2611
2612         if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
2613             (RTL_R8(PHYstatus) & TBI_Enable)) {
2614                 tp->set_speed = rtl8169_set_speed_tbi;
2615                 tp->get_settings = rtl8169_gset_tbi;
2616                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
2617                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
2618                 tp->link_ok = rtl8169_tbi_link_ok;
2619                 tp->do_ioctl = rtl_tbi_ioctl;
2620
2621                 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
2622         } else {
2623                 tp->set_speed = rtl8169_set_speed_xmii;
2624                 tp->get_settings = rtl8169_gset_xmii;
2625                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
2626                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
2627                 tp->link_ok = rtl8169_xmii_link_ok;
2628                 tp->do_ioctl = rtl_xmii_ioctl;
2629         }
2630
2631         spin_lock_init(&tp->lock);
2632
2633         tp->mmio_addr = ioaddr;
2634
2635         /* Get MAC address */
2636         for (i = 0; i < MAC_ADDR_LEN; i++)
2637                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
2638         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
2639
2640         SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
2641         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
2642         dev->irq = pdev->irq;
2643         dev->base_addr = (unsigned long) ioaddr;
2644
2645         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
2646
2647 #ifdef CONFIG_R8169_VLAN
2648         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2649 #endif
2650         dev->features |= NETIF_F_GRO;
2651
2652         tp->intr_mask = 0xffff;
2653         tp->hw_start = cfg->hw_start;
2654         tp->intr_event = cfg->intr_event;
2655         tp->napi_event = cfg->napi_event;
2656
2657         init_timer(&tp->timer);
2658         tp->timer.data = (unsigned long) dev;
2659         tp->timer.function = rtl8169_phy_timer;
2660
2661         rc = register_netdev(dev);
2662         if (rc < 0)
2663                 goto err_out_msi_4;
2664
2665         pci_set_drvdata(pdev, dev);
2666
2667         netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
2668                    rtl_chip_info[tp->chipset].name,
2669                    dev->base_addr, dev->dev_addr,
2670                    (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
2671
2672         rtl8169_init_phy(dev, tp);
2673
2674         /*
2675          * Pretend we are using VLANs; This bypasses a nasty bug where
2676          * Interrupts stop flowing on high load on 8110SCd controllers.
2677          */
2678         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
2679                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | RxVlan);
2680
2681         device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
2682
2683         if (pci_dev_run_wake(pdev))
2684                 pm_runtime_put_noidle(&pdev->dev);
2685
2686 out:
2687         return rc;
2688
2689 err_out_msi_4:
2690         rtl_disable_msi(pdev, tp);
2691         iounmap(ioaddr);
2692 err_out_free_res_3:
2693         pci_release_regions(pdev);
2694 err_out_mwi_2:
2695         pci_clear_mwi(pdev);
2696         pci_disable_device(pdev);
2697 err_out_free_dev_1:
2698         free_netdev(dev);
2699         goto out;
2700 }
2701
2702 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
2703 {
2704         struct net_device *dev = pci_get_drvdata(pdev);
2705         struct rtl8169_private *tp = netdev_priv(dev);
2706
2707         cancel_delayed_work_sync(&tp->task);
2708
2709         unregister_netdev(dev);
2710
2711         if (pci_dev_run_wake(pdev))
2712                 pm_runtime_get_noresume(&pdev->dev);
2713
2714         /* restore original MAC address */
2715         rtl_rar_set(tp, dev->perm_addr);
2716
2717         rtl_disable_msi(pdev, tp);
2718         rtl8169_release_board(pdev, dev, tp->mmio_addr);
2719         pci_set_drvdata(pdev, NULL);
2720 }
2721
2722 static int rtl8169_open(struct net_device *dev)
2723 {
2724         struct rtl8169_private *tp = netdev_priv(dev);
2725         struct pci_dev *pdev = tp->pci_dev;
2726         int retval = -ENOMEM;
2727
2728         pm_runtime_get_sync(&pdev->dev);
2729
2730         /*
2731          * Rx and Tx desscriptors needs 256 bytes alignment.
2732          * dma_alloc_coherent provides more.
2733          */
2734         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
2735                                              &tp->TxPhyAddr, GFP_KERNEL);
2736         if (!tp->TxDescArray)
2737                 goto err_pm_runtime_put;
2738
2739         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
2740                                              &tp->RxPhyAddr, GFP_KERNEL);
2741         if (!tp->RxDescArray)
2742                 goto err_free_tx_0;
2743
2744         retval = rtl8169_init_ring(dev);
2745         if (retval < 0)
2746                 goto err_free_rx_1;
2747
2748         INIT_DELAYED_WORK(&tp->task, NULL);
2749
2750         smp_mb();
2751
2752         retval = request_irq(dev->irq, rtl8169_interrupt,
2753                              (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
2754                              dev->name, dev);
2755         if (retval < 0)
2756                 goto err_release_ring_2;
2757
2758         napi_enable(&tp->napi);
2759
2760         rtl_hw_start(dev);
2761
2762         rtl8169_request_timer(dev);
2763
2764         tp->saved_wolopts = 0;
2765         pm_runtime_put_noidle(&pdev->dev);
2766
2767         rtl8169_check_link_status(dev, tp, tp->mmio_addr);
2768 out:
2769         return retval;
2770
2771 err_release_ring_2:
2772         rtl8169_rx_clear(tp);
2773 err_free_rx_1:
2774         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
2775                           tp->RxPhyAddr);
2776         tp->RxDescArray = NULL;
2777 err_free_tx_0:
2778         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
2779                           tp->TxPhyAddr);
2780         tp->TxDescArray = NULL;
2781 err_pm_runtime_put:
2782         pm_runtime_put_noidle(&pdev->dev);
2783         goto out;
2784 }
2785
2786 static void rtl8169_hw_reset(void __iomem *ioaddr)
2787 {
2788         /* Disable interrupts */
2789         rtl8169_irq_mask_and_ack(ioaddr);
2790
2791         /* Reset the chipset */
2792         RTL_W8(ChipCmd, CmdReset);
2793
2794         /* PCI commit */
2795         RTL_R8(ChipCmd);
2796 }
2797
2798 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
2799 {
2800         void __iomem *ioaddr = tp->mmio_addr;
2801         u32 cfg = rtl8169_rx_config;
2802
2803         cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
2804         RTL_W32(RxConfig, cfg);
2805
2806         /* Set DMA burst size and Interframe Gap Time */
2807         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
2808                 (InterFrameGap << TxInterFrameGapShift));
2809 }
2810
2811 static void rtl_hw_start(struct net_device *dev)
2812 {
2813         struct rtl8169_private *tp = netdev_priv(dev);
2814         void __iomem *ioaddr = tp->mmio_addr;
2815         unsigned int i;
2816
2817         /* Soft reset the chip. */
2818         RTL_W8(ChipCmd, CmdReset);
2819
2820         /* Check that the chip has finished the reset. */
2821         for (i = 0; i < 100; i++) {
2822                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
2823                         break;
2824                 msleep_interruptible(1);
2825         }
2826
2827         tp->hw_start(dev);
2828
2829         netif_start_queue(dev);
2830 }
2831
2832
2833 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
2834                                          void __iomem *ioaddr)
2835 {
2836         /*
2837          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
2838          * register to be written before TxDescAddrLow to work.
2839          * Switching from MMIO to I/O access fixes the issue as well.
2840          */
2841         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
2842         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
2843         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
2844         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
2845 }
2846
2847 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
2848 {
2849         u16 cmd;
2850
2851         cmd = RTL_R16(CPlusCmd);
2852         RTL_W16(CPlusCmd, cmd);
2853         return cmd;
2854 }
2855
2856 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
2857 {
2858         /* Low hurts. Let's disable the filtering. */
2859         RTL_W16(RxMaxSize, rx_buf_sz + 1);
2860 }
2861
2862 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
2863 {
2864         static const struct {
2865                 u32 mac_version;
2866                 u32 clk;
2867                 u32 val;
2868         } cfg2_info [] = {
2869                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
2870                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
2871                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
2872                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
2873         }, *p = cfg2_info;
2874         unsigned int i;
2875         u32 clk;
2876
2877         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
2878         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
2879                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
2880                         RTL_W32(0x7c, p->val);
2881                         break;
2882                 }
2883         }
2884 }
2885
2886 static void rtl_hw_start_8169(struct net_device *dev)
2887 {
2888         struct rtl8169_private *tp = netdev_priv(dev);
2889         void __iomem *ioaddr = tp->mmio_addr;
2890         struct pci_dev *pdev = tp->pci_dev;
2891
2892         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
2893                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
2894                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
2895         }
2896
2897         RTL_W8(Cfg9346, Cfg9346_Unlock);
2898         if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2899             (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2900             (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2901             (tp->mac_version == RTL_GIGA_MAC_VER_04))
2902                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2903
2904         RTL_W8(EarlyTxThres, EarlyTxThld);
2905
2906         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
2907
2908         if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2909             (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2910             (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2911             (tp->mac_version == RTL_GIGA_MAC_VER_04))
2912                 rtl_set_rx_tx_config_registers(tp);
2913
2914         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2915
2916         if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2917             (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
2918                 dprintk("Set MAC Reg C+CR Offset 0xE0. "
2919                         "Bit-3 and bit-14 MUST be 1\n");
2920                 tp->cp_cmd |= (1 << 14);
2921         }
2922
2923         RTL_W16(CPlusCmd, tp->cp_cmd);
2924
2925         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
2926
2927         /*
2928          * Undocumented corner. Supposedly:
2929          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
2930          */
2931         RTL_W16(IntrMitigate, 0x0000);
2932
2933         rtl_set_rx_tx_desc_registers(tp, ioaddr);
2934
2935         if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
2936             (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
2937             (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
2938             (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
2939                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2940                 rtl_set_rx_tx_config_registers(tp);
2941         }
2942
2943         RTL_W8(Cfg9346, Cfg9346_Lock);
2944
2945         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
2946         RTL_R8(IntrMask);
2947
2948         RTL_W32(RxMissed, 0);
2949
2950         rtl_set_rx_mode(dev);
2951
2952         /* no early-rx interrupts */
2953         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
2954
2955         /* Enable all known interrupts by setting the interrupt mask. */
2956         RTL_W16(IntrMask, tp->intr_event);
2957 }
2958
2959 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
2960 {
2961         struct net_device *dev = pci_get_drvdata(pdev);
2962         struct rtl8169_private *tp = netdev_priv(dev);
2963         int cap = tp->pcie_cap;
2964
2965         if (cap) {
2966                 u16 ctl;
2967
2968                 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
2969                 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
2970                 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
2971         }
2972 }
2973
2974 static void rtl_csi_access_enable(void __iomem *ioaddr)
2975 {
2976         u32 csi;
2977
2978         csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
2979         rtl_csi_write(ioaddr, 0x070c, csi | 0x27000000);
2980 }
2981
2982 struct ephy_info {
2983         unsigned int offset;
2984         u16 mask;
2985         u16 bits;
2986 };
2987
2988 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
2989 {
2990         u16 w;
2991
2992         while (len-- > 0) {
2993                 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
2994                 rtl_ephy_write(ioaddr, e->offset, w);
2995                 e++;
2996         }
2997 }
2998
2999 static void rtl_disable_clock_request(struct pci_dev *pdev)
3000 {
3001         struct net_device *dev = pci_get_drvdata(pdev);
3002         struct rtl8169_private *tp = netdev_priv(dev);
3003         int cap = tp->pcie_cap;
3004
3005         if (cap) {
3006                 u16 ctl;
3007
3008                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3009                 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
3010                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3011         }
3012 }
3013
3014 #define R8168_CPCMD_QUIRK_MASK (\
3015         EnableBist | \
3016         Mac_dbgo_oe | \
3017         Force_half_dup | \
3018         Force_rxflow_en | \
3019         Force_txflow_en | \
3020         Cxpl_dbg_sel | \
3021         ASF | \
3022         PktCntrDisable | \
3023         Mac_dbgo_sel)
3024
3025 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
3026 {
3027         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3028
3029         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3030
3031         rtl_tx_performance_tweak(pdev,
3032                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3033 }
3034
3035 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
3036 {
3037         rtl_hw_start_8168bb(ioaddr, pdev);
3038
3039         RTL_W8(EarlyTxThres, EarlyTxThld);
3040
3041         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
3042 }
3043
3044 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
3045 {
3046         RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
3047
3048         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3049
3050         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3051
3052         rtl_disable_clock_request(pdev);
3053
3054         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3055 }
3056
3057 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
3058 {
3059         static const struct ephy_info e_info_8168cp[] = {
3060                 { 0x01, 0,      0x0001 },
3061                 { 0x02, 0x0800, 0x1000 },
3062                 { 0x03, 0,      0x0042 },
3063                 { 0x06, 0x0080, 0x0000 },
3064                 { 0x07, 0,      0x2000 }
3065         };
3066
3067         rtl_csi_access_enable(ioaddr);
3068
3069         rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
3070
3071         __rtl_hw_start_8168cp(ioaddr, pdev);
3072 }
3073
3074 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
3075 {
3076         rtl_csi_access_enable(ioaddr);
3077
3078         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3079
3080         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3081
3082         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3083 }
3084
3085 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
3086 {
3087         rtl_csi_access_enable(ioaddr);
3088
3089         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3090
3091         /* Magic. */
3092         RTL_W8(DBG_REG, 0x20);
3093
3094         RTL_W8(EarlyTxThres, EarlyTxThld);
3095
3096         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3097
3098         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3099 }
3100
3101 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
3102 {
3103         static const struct ephy_info e_info_8168c_1[] = {
3104                 { 0x02, 0x0800, 0x1000 },
3105                 { 0x03, 0,      0x0002 },
3106                 { 0x06, 0x0080, 0x0000 }
3107         };
3108
3109         rtl_csi_access_enable(ioaddr);
3110
3111         RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
3112
3113         rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
3114
3115         __rtl_hw_start_8168cp(ioaddr, pdev);
3116 }
3117
3118 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
3119 {
3120         static const struct ephy_info e_info_8168c_2[] = {
3121                 { 0x01, 0,      0x0001 },
3122                 { 0x03, 0x0400, 0x0220 }
3123         };
3124
3125         rtl_csi_access_enable(ioaddr);
3126
3127         rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
3128
3129         __rtl_hw_start_8168cp(ioaddr, pdev);
3130 }
3131
3132 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
3133 {
3134         rtl_hw_start_8168c_2(ioaddr, pdev);
3135 }
3136
3137 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
3138 {
3139         rtl_csi_access_enable(ioaddr);
3140
3141         __rtl_hw_start_8168cp(ioaddr, pdev);
3142 }
3143
3144 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
3145 {
3146         rtl_csi_access_enable(ioaddr);
3147
3148         rtl_disable_clock_request(pdev);
3149
3150         RTL_W8(EarlyTxThres, EarlyTxThld);
3151
3152         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3153
3154         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3155 }
3156
3157 static void rtl_hw_start_8168(struct net_device *dev)
3158 {
3159         struct rtl8169_private *tp = netdev_priv(dev);
3160         void __iomem *ioaddr = tp->mmio_addr;
3161         struct pci_dev *pdev = tp->pci_dev;
3162
3163         RTL_W8(Cfg9346, Cfg9346_Unlock);
3164
3165         RTL_W8(EarlyTxThres, EarlyTxThld);
3166
3167         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
3168
3169         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
3170
3171         RTL_W16(CPlusCmd, tp->cp_cmd);
3172
3173         RTL_W16(IntrMitigate, 0x5151);
3174
3175         /* Work around for RxFIFO overflow. */
3176         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
3177                 tp->intr_event |= RxFIFOOver | PCSTimeout;
3178                 tp->intr_event &= ~RxOverflow;
3179         }
3180
3181         rtl_set_rx_tx_desc_registers(tp, ioaddr);
3182
3183         rtl_set_rx_mode(dev);
3184
3185         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3186                 (InterFrameGap << TxInterFrameGapShift));
3187
3188         RTL_R8(IntrMask);
3189
3190         switch (tp->mac_version) {
3191         case RTL_GIGA_MAC_VER_11:
3192                 rtl_hw_start_8168bb(ioaddr, pdev);
3193         break;
3194
3195         case RTL_GIGA_MAC_VER_12:
3196         case RTL_GIGA_MAC_VER_17:
3197                 rtl_hw_start_8168bef(ioaddr, pdev);
3198         break;
3199
3200         case RTL_GIGA_MAC_VER_18:
3201                 rtl_hw_start_8168cp_1(ioaddr, pdev);
3202         break;
3203
3204         case RTL_GIGA_MAC_VER_19:
3205                 rtl_hw_start_8168c_1(ioaddr, pdev);
3206         break;
3207
3208         case RTL_GIGA_MAC_VER_20:
3209                 rtl_hw_start_8168c_2(ioaddr, pdev);
3210         break;
3211
3212         case RTL_GIGA_MAC_VER_21:
3213                 rtl_hw_start_8168c_3(ioaddr, pdev);
3214         break;
3215
3216         case RTL_GIGA_MAC_VER_22:
3217                 rtl_hw_start_8168c_4(ioaddr, pdev);
3218         break;
3219
3220         case RTL_GIGA_MAC_VER_23:
3221                 rtl_hw_start_8168cp_2(ioaddr, pdev);
3222         break;
3223
3224         case RTL_GIGA_MAC_VER_24:
3225                 rtl_hw_start_8168cp_3(ioaddr, pdev);
3226         break;
3227
3228         case RTL_GIGA_MAC_VER_25:
3229         case RTL_GIGA_MAC_VER_26:
3230         case RTL_GIGA_MAC_VER_27:
3231                 rtl_hw_start_8168d(ioaddr, pdev);
3232         break;
3233
3234         default:
3235                 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
3236                         dev->name, tp->mac_version);
3237         break;
3238         }
3239
3240         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3241
3242         RTL_W8(Cfg9346, Cfg9346_Lock);
3243
3244         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
3245
3246         RTL_W16(IntrMask, tp->intr_event);
3247 }
3248
3249 #define R810X_CPCMD_QUIRK_MASK (\
3250         EnableBist | \
3251         Mac_dbgo_oe | \
3252         Force_half_dup | \
3253         Force_rxflow_en | \
3254         Force_txflow_en | \
3255         Cxpl_dbg_sel | \
3256         ASF | \
3257         PktCntrDisable | \
3258         PCIDAC | \
3259         PCIMulRW)
3260
3261 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
3262 {
3263         static const struct ephy_info e_info_8102e_1[] = {
3264                 { 0x01, 0, 0x6e65 },
3265                 { 0x02, 0, 0x091f },
3266                 { 0x03, 0, 0xc2f9 },
3267                 { 0x06, 0, 0xafb5 },
3268                 { 0x07, 0, 0x0e00 },
3269                 { 0x19, 0, 0xec80 },
3270                 { 0x01, 0, 0x2e65 },
3271                 { 0x01, 0, 0x6e65 }
3272         };
3273         u8 cfg1;
3274
3275         rtl_csi_access_enable(ioaddr);
3276
3277         RTL_W8(DBG_REG, FIX_NAK_1);
3278
3279         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3280
3281         RTL_W8(Config1,
3282                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
3283         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3284
3285         cfg1 = RTL_R8(Config1);
3286         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
3287                 RTL_W8(Config1, cfg1 & ~LEDS0);
3288
3289         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3290
3291         rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
3292 }
3293
3294 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
3295 {
3296         rtl_csi_access_enable(ioaddr);
3297
3298         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3299
3300         RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
3301         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3302
3303         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3304 }
3305
3306 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
3307 {
3308         rtl_hw_start_8102e_2(ioaddr, pdev);
3309
3310         rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
3311 }
3312
3313 static void rtl_hw_start_8101(struct net_device *dev)
3314 {
3315         struct rtl8169_private *tp = netdev_priv(dev);
3316         void __iomem *ioaddr = tp->mmio_addr;
3317         struct pci_dev *pdev = tp->pci_dev;
3318
3319         if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
3320             (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
3321                 int cap = tp->pcie_cap;
3322
3323                 if (cap) {
3324                         pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
3325                                               PCI_EXP_DEVCTL_NOSNOOP_EN);
3326                 }
3327         }
3328
3329         switch (tp->mac_version) {
3330         case RTL_GIGA_MAC_VER_07:
3331                 rtl_hw_start_8102e_1(ioaddr, pdev);
3332                 break;
3333
3334         case RTL_GIGA_MAC_VER_08:
3335                 rtl_hw_start_8102e_3(ioaddr, pdev);
3336                 break;
3337
3338         case RTL_GIGA_MAC_VER_09:
3339                 rtl_hw_start_8102e_2(ioaddr, pdev);
3340                 break;
3341         }
3342
3343         RTL_W8(Cfg9346, Cfg9346_Unlock);
3344
3345         RTL_W8(EarlyTxThres, EarlyTxThld);
3346
3347         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
3348
3349         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3350
3351         RTL_W16(CPlusCmd, tp->cp_cmd);
3352
3353         RTL_W16(IntrMitigate, 0x0000);
3354
3355         rtl_set_rx_tx_desc_registers(tp, ioaddr);
3356
3357         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3358         rtl_set_rx_tx_config_registers(tp);
3359
3360         RTL_W8(Cfg9346, Cfg9346_Lock);
3361
3362         RTL_R8(IntrMask);
3363
3364         rtl_set_rx_mode(dev);
3365
3366         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3367
3368         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
3369
3370         RTL_W16(IntrMask, tp->intr_event);
3371 }
3372
3373 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
3374 {
3375         if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
3376                 return -EINVAL;
3377
3378         dev->mtu = new_mtu;
3379         return 0;
3380 }
3381
3382 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
3383 {
3384         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
3385         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
3386 }
3387
3388 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
3389                                      void **data_buff, struct RxDesc *desc)
3390 {
3391         dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
3392                          DMA_FROM_DEVICE);
3393
3394         kfree(*data_buff);
3395         *data_buff = NULL;
3396         rtl8169_make_unusable_by_asic(desc);
3397 }
3398
3399 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
3400 {
3401         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
3402
3403         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
3404 }
3405
3406 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
3407                                        u32 rx_buf_sz)
3408 {
3409         desc->addr = cpu_to_le64(mapping);
3410         wmb();
3411         rtl8169_mark_to_asic(desc, rx_buf_sz);
3412 }
3413
3414 static inline void *rtl8169_align(void *data)
3415 {
3416         return (void *)ALIGN((long)data, 16);
3417 }
3418
3419 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
3420                                              struct RxDesc *desc)
3421 {
3422         void *data;
3423         dma_addr_t mapping;
3424         struct device *d = &tp->pci_dev->dev;
3425         struct net_device *dev = tp->dev;
3426         int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
3427
3428         data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
3429         if (!data)
3430                 return NULL;
3431
3432         if (rtl8169_align(data) != data) {
3433                 kfree(data);
3434                 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
3435                 if (!data)
3436                         return NULL;
3437         }
3438
3439         mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
3440                                  DMA_FROM_DEVICE);
3441         if (unlikely(dma_mapping_error(d, mapping))) {
3442                 if (net_ratelimit())
3443                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
3444                 goto err_out;
3445         }
3446
3447         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
3448         return data;
3449
3450 err_out:
3451         kfree(data);
3452         return NULL;
3453 }
3454
3455 static void rtl8169_rx_clear(struct rtl8169_private *tp)
3456 {
3457         unsigned int i;
3458
3459         for (i = 0; i < NUM_RX_DESC; i++) {
3460                 if (tp->Rx_databuff[i]) {
3461                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
3462                                             tp->RxDescArray + i);
3463                 }
3464         }
3465 }
3466
3467 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
3468 {
3469         desc->opts1 |= cpu_to_le32(RingEnd);
3470 }
3471
3472 static int rtl8169_rx_fill(struct rtl8169_private *tp)
3473 {
3474         unsigned int i;
3475
3476         for (i = 0; i < NUM_RX_DESC; i++) {
3477                 void *data;
3478
3479                 if (tp->Rx_databuff[i])
3480                         continue;
3481
3482                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
3483                 if (!data) {
3484                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
3485                         goto err_out;
3486                 }
3487                 tp->Rx_databuff[i] = data;
3488         }
3489
3490         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
3491         return 0;
3492
3493 err_out:
3494         rtl8169_rx_clear(tp);
3495         return -ENOMEM;
3496 }
3497
3498 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3499 {
3500         tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
3501 }
3502
3503 static int rtl8169_init_ring(struct net_device *dev)
3504 {
3505         struct rtl8169_private *tp = netdev_priv(dev);
3506
3507         rtl8169_init_ring_indexes(tp);
3508
3509         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
3510         memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
3511
3512         return rtl8169_rx_fill(tp);
3513 }
3514
3515 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
3516                                  struct TxDesc *desc)
3517 {
3518         unsigned int len = tx_skb->len;
3519
3520         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
3521
3522         desc->opts1 = 0x00;
3523         desc->opts2 = 0x00;
3524         desc->addr = 0x00;
3525         tx_skb->len = 0;
3526 }
3527
3528 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
3529                                    unsigned int n)
3530 {
3531         unsigned int i;
3532
3533         for (i = 0; i < n; i++) {
3534                 unsigned int entry = (start + i) % NUM_TX_DESC;
3535                 struct ring_info *tx_skb = tp->tx_skb + entry;
3536                 unsigned int len = tx_skb->len;
3537
3538                 if (len) {
3539                         struct sk_buff *skb = tx_skb->skb;
3540
3541                         rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
3542                                              tp->TxDescArray + entry);
3543                         if (skb) {
3544                                 tp->dev->stats.tx_dropped++;
3545                                 dev_kfree_skb(skb);
3546                                 tx_skb->skb = NULL;
3547                         }
3548                 }
3549         }
3550 }
3551
3552 static void rtl8169_tx_clear(struct rtl8169_private *tp)
3553 {
3554         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
3555         tp->cur_tx = tp->dirty_tx = 0;
3556 }
3557
3558 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
3559 {
3560         struct rtl8169_private *tp = netdev_priv(dev);
3561
3562         PREPARE_DELAYED_WORK(&tp->task, task);
3563         schedule_delayed_work(&tp->task, 4);
3564 }
3565
3566 static void rtl8169_wait_for_quiescence(struct net_device *dev)
3567 {
3568         struct rtl8169_private *tp = netdev_priv(dev);
3569         void __iomem *ioaddr = tp->mmio_addr;
3570
3571         synchronize_irq(dev->irq);
3572
3573         /* Wait for any pending NAPI task to complete */
3574         napi_disable(&tp->napi);
3575
3576         rtl8169_irq_mask_and_ack(ioaddr);
3577
3578         tp->intr_mask = 0xffff;
3579         RTL_W16(IntrMask, tp->intr_event);
3580         napi_enable(&tp->napi);
3581 }
3582
3583 static void rtl8169_reinit_task(struct work_struct *work)
3584 {
3585         struct rtl8169_private *tp =
3586                 container_of(work, struct rtl8169_private, task.work);
3587         struct net_device *dev = tp->dev;
3588         int ret;
3589
3590         rtnl_lock();
3591
3592         if (!netif_running(dev))
3593                 goto out_unlock;
3594
3595         rtl8169_wait_for_quiescence(dev);
3596         rtl8169_close(dev);
3597
3598         ret = rtl8169_open(dev);
3599         if (unlikely(ret < 0)) {
3600                 if (net_ratelimit())
3601                         netif_err(tp, drv, dev,
3602                                   "reinit failure (status = %d). Rescheduling\n",
3603                                   ret);
3604                 rtl8169_schedule_work(dev, rtl8169_reinit_task);
3605         }
3606
3607 out_unlock:
3608         rtnl_unlock();
3609 }
3610
3611 static void rtl8169_reset_task(struct work_struct *work)
3612 {
3613         struct rtl8169_private *tp =
3614                 container_of(work, struct rtl8169_private, task.work);
3615         struct net_device *dev = tp->dev;
3616
3617         rtnl_lock();
3618
3619         if (!netif_running(dev))
3620                 goto out_unlock;
3621
3622         rtl8169_wait_for_quiescence(dev);
3623
3624         rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
3625         rtl8169_tx_clear(tp);
3626
3627         if (tp->dirty_rx == tp->cur_rx) {
3628                 rtl8169_init_ring_indexes(tp);
3629                 rtl_hw_start(dev);
3630                 netif_wake_queue(dev);
3631                 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
3632         } else {
3633                 if (net_ratelimit())
3634                         netif_emerg(tp, intr, dev, "Rx buffers shortage\n");
3635                 rtl8169_schedule_work(dev, rtl8169_reset_task);
3636         }
3637
3638 out_unlock:
3639         rtnl_unlock();
3640 }
3641
3642 static void rtl8169_tx_timeout(struct net_device *dev)
3643 {
3644         struct rtl8169_private *tp = netdev_priv(dev);
3645
3646         rtl8169_hw_reset(tp->mmio_addr);
3647
3648         /* Let's wait a bit while any (async) irq lands on */
3649         rtl8169_schedule_work(dev, rtl8169_reset_task);
3650 }
3651
3652 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
3653                               u32 opts1)
3654 {
3655         struct skb_shared_info *info = skb_shinfo(skb);
3656         unsigned int cur_frag, entry;
3657         struct TxDesc * uninitialized_var(txd);
3658         struct device *d = &tp->pci_dev->dev;
3659
3660         entry = tp->cur_tx;
3661         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
3662                 skb_frag_t *frag = info->frags + cur_frag;
3663                 dma_addr_t mapping;
3664                 u32 status, len;
3665                 void *addr;
3666
3667                 entry = (entry + 1) % NUM_TX_DESC;
3668
3669                 txd = tp->TxDescArray + entry;
3670                 len = frag->size;
3671                 addr = ((void *) page_address(frag->page)) + frag->page_offset;
3672                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
3673                 if (unlikely(dma_mapping_error(d, mapping))) {
3674                         if (net_ratelimit())
3675                                 netif_err(tp, drv, tp->dev,
3676                                           "Failed to map TX fragments DMA!\n");
3677                         goto err_out;
3678                 }
3679
3680                 /* anti gcc 2.95.3 bugware (sic) */
3681                 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
3682
3683                 txd->opts1 = cpu_to_le32(status);
3684                 txd->addr = cpu_to_le64(mapping);
3685
3686                 tp->tx_skb[entry].len = len;
3687         }
3688
3689         if (cur_frag) {
3690                 tp->tx_skb[entry].skb = skb;
3691                 txd->opts1 |= cpu_to_le32(LastFrag);
3692         }
3693
3694         return cur_frag;
3695
3696 err_out:
3697         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
3698         return -EIO;
3699 }
3700
3701 static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
3702 {
3703         if (dev->features & NETIF_F_TSO) {
3704                 u32 mss = skb_shinfo(skb)->gso_size;
3705
3706                 if (mss)
3707                         return LargeSend | ((mss & MSSMask) << MSSShift);
3708         }
3709         if (skb->ip_summed == CHECKSUM_PARTIAL) {
3710                 const struct iphdr *ip = ip_hdr(skb);
3711
3712                 if (ip->protocol == IPPROTO_TCP)
3713                         return IPCS | TCPCS;
3714                 else if (ip->protocol == IPPROTO_UDP)
3715                         return IPCS | UDPCS;
3716                 WARN_ON(1);     /* we need a WARN() */
3717         }
3718         return 0;
3719 }
3720
3721 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
3722                                       struct net_device *dev)
3723 {
3724         struct rtl8169_private *tp = netdev_priv(dev);
3725         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
3726         struct TxDesc *txd = tp->TxDescArray + entry;
3727         void __iomem *ioaddr = tp->mmio_addr;
3728         struct device *d = &tp->pci_dev->dev;
3729         dma_addr_t mapping;
3730         u32 status, len;
3731         u32 opts1;
3732         int frags;
3733
3734         if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
3735                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
3736                 goto err_stop_0;
3737         }
3738
3739         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3740                 goto err_stop_0;
3741
3742         len = skb_headlen(skb);
3743         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
3744         if (unlikely(dma_mapping_error(d, mapping))) {
3745                 if (net_ratelimit())
3746                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
3747                 goto err_dma_0;
3748         }
3749
3750         tp->tx_skb[entry].len = len;
3751         txd->addr = cpu_to_le64(mapping);
3752         txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
3753
3754         opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
3755
3756         frags = rtl8169_xmit_frags(tp, skb, opts1);
3757         if (frags < 0)
3758                 goto err_dma_1;
3759         else if (frags)
3760                 opts1 |= FirstFrag;
3761         else {
3762                 opts1 |= FirstFrag | LastFrag;
3763                 tp->tx_skb[entry].skb = skb;
3764         }
3765
3766         wmb();
3767
3768         /* anti gcc 2.95.3 bugware (sic) */
3769         status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
3770         txd->opts1 = cpu_to_le32(status);
3771
3772         tp->cur_tx += frags + 1;
3773
3774         wmb();
3775
3776         RTL_W8(TxPoll, NPQ);    /* set polling bit */
3777
3778         if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
3779                 netif_stop_queue(dev);
3780                 smp_rmb();
3781                 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
3782                         netif_wake_queue(dev);
3783         }
3784
3785         return NETDEV_TX_OK;
3786
3787 err_dma_1:
3788         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
3789 err_dma_0:
3790         dev_kfree_skb(skb);
3791         dev->stats.tx_dropped++;
3792         return NETDEV_TX_OK;
3793
3794 err_stop_0:
3795         netif_stop_queue(dev);
3796         dev->stats.tx_dropped++;
3797         return NETDEV_TX_BUSY;
3798 }
3799
3800 static void rtl8169_pcierr_interrupt(struct net_device *dev)
3801 {
3802         struct rtl8169_private *tp = netdev_priv(dev);
3803         struct pci_dev *pdev = tp->pci_dev;
3804         void __iomem *ioaddr = tp->mmio_addr;
3805         u16 pci_status, pci_cmd;
3806
3807         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
3808         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
3809
3810         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
3811                   pci_cmd, pci_status);
3812
3813         /*
3814          * The recovery sequence below admits a very elaborated explanation:
3815          * - it seems to work;
3816          * - I did not see what else could be done;
3817          * - it makes iop3xx happy.
3818          *
3819          * Feel free to adjust to your needs.
3820          */
3821         if (pdev->broken_parity_status)
3822                 pci_cmd &= ~PCI_COMMAND_PARITY;
3823         else
3824                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
3825
3826         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
3827
3828         pci_write_config_word(pdev, PCI_STATUS,
3829                 pci_status & (PCI_STATUS_DETECTED_PARITY |
3830                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
3831                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
3832
3833         /* The infamous DAC f*ckup only happens at boot time */
3834         if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
3835                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
3836                 tp->cp_cmd &= ~PCIDAC;
3837                 RTL_W16(CPlusCmd, tp->cp_cmd);
3838                 dev->features &= ~NETIF_F_HIGHDMA;
3839         }
3840
3841         rtl8169_hw_reset(ioaddr);
3842
3843         rtl8169_schedule_work(dev, rtl8169_reinit_task);
3844 }
3845
3846 static void rtl8169_tx_interrupt(struct net_device *dev,
3847                                  struct rtl8169_private *tp,
3848                                  void __iomem *ioaddr)
3849 {
3850         unsigned int dirty_tx, tx_left;
3851
3852         dirty_tx = tp->dirty_tx;
3853         smp_rmb();
3854         tx_left = tp->cur_tx - dirty_tx;
3855
3856         while (tx_left > 0) {
3857                 unsigned int entry = dirty_tx % NUM_TX_DESC;
3858                 struct ring_info *tx_skb = tp->tx_skb + entry;
3859                 u32 status;
3860
3861                 rmb();
3862                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
3863                 if (status & DescOwn)
3864                         break;
3865
3866                 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
3867                                      tp->TxDescArray + entry);
3868                 if (status & LastFrag) {
3869                         dev->stats.tx_packets++;
3870                         dev->stats.tx_bytes += tx_skb->skb->len;
3871                         dev_kfree_skb(tx_skb->skb);
3872                         tx_skb->skb = NULL;
3873                 }
3874                 dirty_tx++;
3875                 tx_left--;
3876         }
3877
3878         if (tp->dirty_tx != dirty_tx) {
3879                 tp->dirty_tx = dirty_tx;
3880                 smp_wmb();
3881                 if (netif_queue_stopped(dev) &&
3882                     (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
3883                         netif_wake_queue(dev);
3884                 }
3885                 /*
3886                  * 8168 hack: TxPoll requests are lost when the Tx packets are
3887                  * too close. Let's kick an extra TxPoll request when a burst
3888                  * of start_xmit activity is detected (if it is not detected,
3889                  * it is slow enough). -- FR
3890                  */
3891                 smp_rmb();
3892                 if (tp->cur_tx != dirty_tx)
3893                         RTL_W8(TxPoll, NPQ);
3894         }
3895 }
3896
3897 static inline int rtl8169_fragmented_frame(u32 status)
3898 {
3899         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
3900 }
3901
3902 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
3903 {
3904         u32 status = opts1 & RxProtoMask;
3905
3906         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
3907             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
3908                 skb->ip_summed = CHECKSUM_UNNECESSARY;
3909         else
3910                 skb_checksum_none_assert(skb);
3911 }
3912
3913 static struct sk_buff *rtl8169_try_rx_copy(void *data,
3914                                            struct rtl8169_private *tp,
3915                                            int pkt_size,
3916                                            dma_addr_t addr)
3917 {
3918         struct sk_buff *skb;
3919         struct device *d = &tp->pci_dev->dev;
3920
3921         data = rtl8169_align(data);
3922         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
3923         prefetch(data);
3924         skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
3925         if (skb)
3926                 memcpy(skb->data, data, pkt_size);
3927         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
3928
3929         return skb;
3930 }
3931
3932 /*
3933  * Warning : rtl8169_rx_interrupt() might be called :
3934  * 1) from NAPI (softirq) context
3935  *      (polling = 1 : we should call netif_receive_skb())
3936  * 2) from process context (rtl8169_reset_task())
3937  *      (polling = 0 : we must call netif_rx() instead)
3938  */
3939 static int rtl8169_rx_interrupt(struct net_device *dev,
3940                                 struct rtl8169_private *tp,
3941                                 void __iomem *ioaddr, u32 budget)
3942 {
3943         unsigned int cur_rx, rx_left;
3944         unsigned int count;
3945         int polling = (budget != ~(u32)0) ? 1 : 0;
3946
3947         cur_rx = tp->cur_rx;
3948         rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
3949         rx_left = min(rx_left, budget);
3950
3951         for (; rx_left > 0; rx_left--, cur_rx++) {
3952                 unsigned int entry = cur_rx % NUM_RX_DESC;
3953                 struct RxDesc *desc = tp->RxDescArray + entry;
3954                 u32 status;
3955
3956                 rmb();
3957                 status = le32_to_cpu(desc->opts1);
3958
3959                 if (status & DescOwn)
3960                         break;
3961                 if (unlikely(status & RxRES)) {
3962                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
3963                                    status);
3964                         dev->stats.rx_errors++;
3965                         if (status & (RxRWT | RxRUNT))
3966                                 dev->stats.rx_length_errors++;
3967                         if (status & RxCRC)
3968                                 dev->stats.rx_crc_errors++;
3969                         if (status & RxFOVF) {
3970                                 rtl8169_schedule_work(dev, rtl8169_reset_task);
3971                                 dev->stats.rx_fifo_errors++;
3972                         }
3973                         rtl8169_mark_to_asic(desc, rx_buf_sz);
3974                 } else {
3975                         struct sk_buff *skb;
3976                         dma_addr_t addr = le64_to_cpu(desc->addr);
3977                         int pkt_size = (status & 0x00001FFF) - 4;
3978
3979                         /*
3980                          * The driver does not support incoming fragmented
3981                          * frames. They are seen as a symptom of over-mtu
3982                          * sized frames.
3983                          */
3984                         if (unlikely(rtl8169_fragmented_frame(status))) {
3985                                 dev->stats.rx_dropped++;
3986                                 dev->stats.rx_length_errors++;
3987                                 rtl8169_mark_to_asic(desc, rx_buf_sz);
3988                                 continue;
3989                         }
3990
3991                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
3992                                                   tp, pkt_size, addr);
3993                         rtl8169_mark_to_asic(desc, rx_buf_sz);
3994                         if (!skb) {
3995                                 dev->stats.rx_dropped++;
3996                                 continue;
3997                         }
3998
3999                         rtl8169_rx_csum(skb, status);
4000                         skb_put(skb, pkt_size);
4001                         skb->protocol = eth_type_trans(skb, dev);
4002
4003                         if (rtl8169_rx_vlan_skb(tp, desc, skb, polling) < 0) {
4004                                 if (likely(polling))
4005                                         napi_gro_receive(&tp->napi, skb);
4006                                 else
4007                                         netif_rx(skb);
4008                         }
4009
4010                         dev->stats.rx_bytes += pkt_size;
4011                         dev->stats.rx_packets++;
4012                 }
4013
4014                 /* Work around for AMD plateform. */
4015                 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
4016                     (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
4017                         desc->opts2 = 0;
4018                         cur_rx++;
4019                 }
4020         }
4021
4022         count = cur_rx - tp->cur_rx;
4023         tp->cur_rx = cur_rx;
4024
4025         tp->dirty_rx += count;
4026
4027         return count;
4028 }
4029
4030 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
4031 {
4032         struct net_device *dev = dev_instance;
4033         struct rtl8169_private *tp = netdev_priv(dev);
4034         void __iomem *ioaddr = tp->mmio_addr;
4035         int handled = 0;
4036         int status;
4037
4038         /* loop handling interrupts until we have no new ones or
4039          * we hit a invalid/hotplug case.
4040          */
4041         status = RTL_R16(IntrStatus);
4042         while (status && status != 0xffff) {
4043                 handled = 1;
4044
4045                 /* Handle all of the error cases first. These will reset
4046                  * the chip, so just exit the loop.
4047                  */
4048                 if (unlikely(!netif_running(dev))) {
4049                         rtl8169_asic_down(ioaddr);
4050                         break;
4051                 }
4052
4053                 /* Work around for rx fifo overflow */
4054                 if (unlikely(status & RxFIFOOver) &&
4055                 (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
4056                         netif_stop_queue(dev);
4057                         rtl8169_tx_timeout(dev);
4058                         break;
4059                 }
4060
4061                 if (unlikely(status & SYSErr)) {
4062                         rtl8169_pcierr_interrupt(dev);
4063                         break;
4064                 }
4065
4066                 if (status & LinkChg)
4067                         __rtl8169_check_link_status(dev, tp, ioaddr, true);
4068
4069                 /* We need to see the lastest version of tp->intr_mask to
4070                  * avoid ignoring an MSI interrupt and having to wait for
4071                  * another event which may never come.
4072                  */
4073                 smp_rmb();
4074                 if (status & tp->intr_mask & tp->napi_event) {
4075                         RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
4076                         tp->intr_mask = ~tp->napi_event;
4077
4078                         if (likely(napi_schedule_prep(&tp->napi)))
4079                                 __napi_schedule(&tp->napi);
4080                         else
4081                                 netif_info(tp, intr, dev,
4082                                            "interrupt %04x in poll\n", status);
4083                 }
4084
4085                 /* We only get a new MSI interrupt when all active irq
4086                  * sources on the chip have been acknowledged. So, ack
4087                  * everything we've seen and check if new sources have become
4088                  * active to avoid blocking all interrupts from the chip.
4089                  */
4090                 RTL_W16(IntrStatus,
4091                         (status & RxFIFOOver) ? (status | RxOverflow) : status);
4092                 status = RTL_R16(IntrStatus);
4093         }
4094
4095         return IRQ_RETVAL(handled);
4096 }
4097
4098 static int rtl8169_poll(struct napi_struct *napi, int budget)
4099 {
4100         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4101         struct net_device *dev = tp->dev;
4102         void __iomem *ioaddr = tp->mmio_addr;
4103         int work_done;
4104
4105         work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
4106         rtl8169_tx_interrupt(dev, tp, ioaddr);
4107
4108         if (work_done < budget) {
4109                 napi_complete(napi);
4110
4111                 /* We need for force the visibility of tp->intr_mask
4112                  * for other CPUs, as we can loose an MSI interrupt
4113                  * and potentially wait for a retransmit timeout if we don't.
4114                  * The posted write to IntrMask is safe, as it will
4115                  * eventually make it to the chip and we won't loose anything
4116                  * until it does.
4117                  */
4118                 tp->intr_mask = 0xffff;
4119                 wmb();
4120                 RTL_W16(IntrMask, tp->intr_event);
4121         }
4122
4123         return work_done;
4124 }
4125
4126 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
4127 {
4128         struct rtl8169_private *tp = netdev_priv(dev);
4129
4130         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
4131                 return;
4132
4133         dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
4134         RTL_W32(RxMissed, 0);
4135 }
4136
4137 static void rtl8169_down(struct net_device *dev)
4138 {
4139         struct rtl8169_private *tp = netdev_priv(dev);
4140         void __iomem *ioaddr = tp->mmio_addr;
4141
4142         rtl8169_delete_timer(dev);
4143
4144         netif_stop_queue(dev);
4145
4146         napi_disable(&tp->napi);
4147
4148         spin_lock_irq(&tp->lock);
4149
4150         rtl8169_asic_down(ioaddr);
4151         /*
4152          * At this point device interrupts can not be enabled in any function,
4153          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
4154          * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
4155          */
4156         rtl8169_rx_missed(dev, ioaddr);
4157
4158         spin_unlock_irq(&tp->lock);
4159
4160         synchronize_irq(dev->irq);
4161
4162         /* Give a racing hard_start_xmit a few cycles to complete. */
4163         synchronize_sched();  /* FIXME: should this be synchronize_irq()? */
4164
4165         rtl8169_tx_clear(tp);
4166
4167         rtl8169_rx_clear(tp);
4168 }
4169
4170 static int rtl8169_close(struct net_device *dev)
4171 {
4172         struct rtl8169_private *tp = netdev_priv(dev);
4173         struct pci_dev *pdev = tp->pci_dev;
4174
4175         pm_runtime_get_sync(&pdev->dev);
4176
4177         /* update counters before going down */
4178         rtl8169_update_counters(dev);
4179
4180         rtl8169_down(dev);
4181
4182         free_irq(dev->irq, dev);
4183
4184         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4185                           tp->RxPhyAddr);
4186         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4187                           tp->TxPhyAddr);
4188         tp->TxDescArray = NULL;
4189         tp->RxDescArray = NULL;
4190
4191         pm_runtime_put_sync(&pdev->dev);
4192
4193         return 0;
4194 }
4195
4196 static void rtl_set_rx_mode(struct net_device *dev)
4197 {
4198         struct rtl8169_private *tp = netdev_priv(dev);
4199         void __iomem *ioaddr = tp->mmio_addr;
4200         unsigned long flags;
4201         u32 mc_filter[2];       /* Multicast hash filter */
4202         int rx_mode;
4203         u32 tmp = 0;
4204
4205         if (dev->flags & IFF_PROMISC) {
4206                 /* Unconditionally log net taps. */
4207                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4208                 rx_mode =
4209                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4210                     AcceptAllPhys;
4211                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4212         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4213                    (dev->flags & IFF_ALLMULTI)) {
4214                 /* Too many to filter perfectly -- accept all multicasts. */
4215                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4216                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4217         } else {
4218                 struct netdev_hw_addr *ha;
4219
4220                 rx_mode = AcceptBroadcast | AcceptMyPhys;
4221                 mc_filter[1] = mc_filter[0] = 0;
4222                 netdev_for_each_mc_addr(ha, dev) {
4223                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4224                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4225                         rx_mode |= AcceptMulticast;
4226                 }
4227         }
4228
4229         spin_lock_irqsave(&tp->lock, flags);
4230
4231         tmp = rtl8169_rx_config | rx_mode |
4232               (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
4233
4234         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4235                 u32 data = mc_filter[0];
4236
4237                 mc_filter[0] = swab32(mc_filter[1]);
4238                 mc_filter[1] = swab32(data);
4239         }
4240
4241         RTL_W32(MAR0 + 4, mc_filter[1]);
4242         RTL_W32(MAR0 + 0, mc_filter[0]);
4243
4244         RTL_W32(RxConfig, tmp);
4245
4246         spin_unlock_irqrestore(&tp->lock, flags);
4247 }
4248
4249 /**
4250  *  rtl8169_get_stats - Get rtl8169 read/write statistics
4251  *  @dev: The Ethernet Device to get statistics for
4252  *
4253  *  Get TX/RX statistics for rtl8169
4254  */
4255 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
4256 {
4257         struct rtl8169_private *tp = netdev_priv(dev);
4258         void __iomem *ioaddr = tp->mmio_addr;
4259         unsigned long flags;
4260
4261         if (netif_running(dev)) {
4262                 spin_lock_irqsave(&tp->lock, flags);
4263                 rtl8169_rx_missed(dev, ioaddr);
4264                 spin_unlock_irqrestore(&tp->lock, flags);
4265         }
4266
4267         return &dev->stats;
4268 }
4269
4270 static void rtl8169_net_suspend(struct net_device *dev)
4271 {
4272         if (!netif_running(dev))
4273                 return;
4274
4275         netif_device_detach(dev);
4276         netif_stop_queue(dev);
4277 }
4278
4279 #ifdef CONFIG_PM
4280
4281 static int rtl8169_suspend(struct device *device)
4282 {
4283         struct pci_dev *pdev = to_pci_dev(device);
4284         struct net_device *dev = pci_get_drvdata(pdev);
4285
4286         rtl8169_net_suspend(dev);
4287
4288         return 0;
4289 }
4290
4291 static void __rtl8169_resume(struct net_device *dev)
4292 {
4293         netif_device_attach(dev);
4294         rtl8169_schedule_work(dev, rtl8169_reset_task);
4295 }
4296
4297 static int rtl8169_resume(struct device *device)
4298 {
4299         struct pci_dev *pdev = to_pci_dev(device);
4300         struct net_device *dev = pci_get_drvdata(pdev);
4301         struct rtl8169_private *tp = netdev_priv(dev);
4302
4303         rtl8169_init_phy(dev, tp);
4304
4305         if (netif_running(dev))
4306                 __rtl8169_resume(dev);
4307
4308         return 0;
4309 }
4310
4311 static int rtl8169_runtime_suspend(struct device *device)
4312 {
4313         struct pci_dev *pdev = to_pci_dev(device);
4314         struct net_device *dev = pci_get_drvdata(pdev);
4315         struct rtl8169_private *tp = netdev_priv(dev);
4316
4317         if (!tp->TxDescArray)
4318                 return 0;
4319
4320         spin_lock_irq(&tp->lock);
4321         tp->saved_wolopts = __rtl8169_get_wol(tp);
4322         __rtl8169_set_wol(tp, WAKE_ANY);
4323         spin_unlock_irq(&tp->lock);
4324
4325         rtl8169_net_suspend(dev);
4326
4327         return 0;
4328 }
4329
4330 static int rtl8169_runtime_resume(struct device *device)
4331 {
4332         struct pci_dev *pdev = to_pci_dev(device);
4333         struct net_device *dev = pci_get_drvdata(pdev);
4334         struct rtl8169_private *tp = netdev_priv(dev);
4335
4336         if (!tp->TxDescArray)
4337                 return 0;
4338
4339         spin_lock_irq(&tp->lock);
4340         __rtl8169_set_wol(tp, tp->saved_wolopts);
4341         tp->saved_wolopts = 0;
4342         spin_unlock_irq(&tp->lock);
4343
4344         rtl8169_init_phy(dev, tp);
4345
4346         __rtl8169_resume(dev);
4347
4348         return 0;
4349 }
4350
4351 static int rtl8169_runtime_idle(struct device *device)
4352 {
4353         struct pci_dev *pdev = to_pci_dev(device);
4354         struct net_device *dev = pci_get_drvdata(pdev);
4355         struct rtl8169_private *tp = netdev_priv(dev);
4356
4357         return tp->TxDescArray ? -EBUSY : 0;
4358 }
4359
4360 static const struct dev_pm_ops rtl8169_pm_ops = {
4361         .suspend = rtl8169_suspend,
4362         .resume = rtl8169_resume,
4363         .freeze = rtl8169_suspend,
4364         .thaw = rtl8169_resume,
4365         .poweroff = rtl8169_suspend,
4366         .restore = rtl8169_resume,
4367         .runtime_suspend = rtl8169_runtime_suspend,
4368         .runtime_resume = rtl8169_runtime_resume,
4369         .runtime_idle = rtl8169_runtime_idle,
4370 };
4371
4372 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
4373
4374 #else /* !CONFIG_PM */
4375
4376 #define RTL8169_PM_OPS  NULL
4377
4378 #endif /* !CONFIG_PM */
4379
4380 static void rtl_shutdown(struct pci_dev *pdev)
4381 {
4382         struct net_device *dev = pci_get_drvdata(pdev);
4383         struct rtl8169_private *tp = netdev_priv(dev);
4384         void __iomem *ioaddr = tp->mmio_addr;
4385
4386         rtl8169_net_suspend(dev);
4387
4388         /* restore original MAC address */
4389         rtl_rar_set(tp, dev->perm_addr);
4390
4391         spin_lock_irq(&tp->lock);
4392
4393         rtl8169_asic_down(ioaddr);
4394
4395         spin_unlock_irq(&tp->lock);
4396
4397         if (system_state == SYSTEM_POWER_OFF) {
4398                 /* WoL fails with some 8168 when the receiver is disabled. */
4399                 if (tp->features & RTL_FEATURE_WOL) {
4400                         pci_clear_master(pdev);
4401
4402                         RTL_W8(ChipCmd, CmdRxEnb);
4403                         /* PCI commit */
4404                         RTL_R8(ChipCmd);
4405                 }
4406
4407                 pci_wake_from_d3(pdev, true);
4408                 pci_set_power_state(pdev, PCI_D3hot);
4409         }
4410 }
4411
4412 static struct pci_driver rtl8169_pci_driver = {
4413         .name           = MODULENAME,
4414         .id_table       = rtl8169_pci_tbl,
4415         .probe          = rtl8169_init_one,
4416         .remove         = __devexit_p(rtl8169_remove_one),
4417         .shutdown       = rtl_shutdown,
4418         .driver.pm      = RTL8169_PM_OPS,
4419 };
4420
4421 static int __init rtl8169_init_module(void)
4422 {
4423         return pci_register_driver(&rtl8169_pci_driver);
4424 }
4425
4426 static void __exit rtl8169_cleanup_module(void)
4427 {
4428         pci_unregister_driver(&rtl8169_pci_driver);
4429 }
4430
4431 module_init(rtl8169_init_module);
4432 module_exit(rtl8169_cleanup_module);