2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/firmware.h>
28 #include <linux/pci-aspm.h>
29 #include <linux/prefetch.h>
31 #include <asm/system.h>
35 #define RTL8169_VERSION "2.3LK-NAPI"
36 #define MODULENAME "r8169"
37 #define PFX MODULENAME ": "
39 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
40 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
41 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
42 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
43 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
46 #define assert(expr) \
48 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
49 #expr,__FILE__,__func__,__LINE__); \
51 #define dprintk(fmt, args...) \
52 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
54 #define assert(expr) do {} while (0)
55 #define dprintk(fmt, args...) do {} while (0)
56 #endif /* RTL8169_DEBUG */
58 #define R8169_MSG_DEFAULT \
59 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
61 #define TX_SLOTS_AVAIL(tp) \
62 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
64 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
65 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
66 (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
68 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
69 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
70 static const int multicast_filter_limit = 32;
72 /* MAC address length */
73 #define MAC_ADDR_LEN 6
75 #define MAX_READ_REQUEST_SHIFT 12
76 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
77 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
78 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
79 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
80 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
82 #define R8169_REGS_SIZE 256
83 #define R8169_NAPI_WEIGHT 64
84 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
85 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
86 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
87 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
88 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
90 #define RTL8169_TX_TIMEOUT (6*HZ)
91 #define RTL8169_PHY_TIMEOUT (10*HZ)
93 #define RTL_EEPROM_SIG cpu_to_le32(0x8129)
94 #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
95 #define RTL_EEPROM_SIG_ADDR 0x0000
97 /* write/read MMIO register */
98 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
99 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
100 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
101 #define RTL_R8(reg) readb (ioaddr + (reg))
102 #define RTL_R16(reg) readw (ioaddr + (reg))
103 #define RTL_R32(reg) readl (ioaddr + (reg))
106 RTL_GIGA_MAC_VER_01 = 0,
139 RTL_GIGA_MAC_NONE = 0xff,
142 enum rtl_tx_desc_version {
147 #define JUMBO_1K ETH_DATA_LEN
148 #define JUMBO_4K (4*1024 - ETH_HLEN - 2)
149 #define JUMBO_6K (6*1024 - ETH_HLEN - 2)
150 #define JUMBO_7K (7*1024 - ETH_HLEN - 2)
151 #define JUMBO_9K (9*1024 - ETH_HLEN - 2)
153 #define _R(NAME,TD,FW,SZ,B) { \
161 static const struct {
163 enum rtl_tx_desc_version txd_version;
167 } rtl_chip_infos[] = {
169 [RTL_GIGA_MAC_VER_01] =
170 _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K, true),
171 [RTL_GIGA_MAC_VER_02] =
172 _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K, true),
173 [RTL_GIGA_MAC_VER_03] =
174 _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K, true),
175 [RTL_GIGA_MAC_VER_04] =
176 _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K, true),
177 [RTL_GIGA_MAC_VER_05] =
178 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
179 [RTL_GIGA_MAC_VER_06] =
180 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
182 [RTL_GIGA_MAC_VER_07] =
183 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
184 [RTL_GIGA_MAC_VER_08] =
185 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
186 [RTL_GIGA_MAC_VER_09] =
187 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
188 [RTL_GIGA_MAC_VER_10] =
189 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
190 [RTL_GIGA_MAC_VER_11] =
191 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
192 [RTL_GIGA_MAC_VER_12] =
193 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
194 [RTL_GIGA_MAC_VER_13] =
195 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
196 [RTL_GIGA_MAC_VER_14] =
197 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
198 [RTL_GIGA_MAC_VER_15] =
199 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
200 [RTL_GIGA_MAC_VER_16] =
201 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
202 [RTL_GIGA_MAC_VER_17] =
203 _R("RTL8168b/8111b", RTL_TD_1, NULL, JUMBO_4K, false),
204 [RTL_GIGA_MAC_VER_18] =
205 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
206 [RTL_GIGA_MAC_VER_19] =
207 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
208 [RTL_GIGA_MAC_VER_20] =
209 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
210 [RTL_GIGA_MAC_VER_21] =
211 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
212 [RTL_GIGA_MAC_VER_22] =
213 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
214 [RTL_GIGA_MAC_VER_23] =
215 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
216 [RTL_GIGA_MAC_VER_24] =
217 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
218 [RTL_GIGA_MAC_VER_25] =
219 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1,
221 [RTL_GIGA_MAC_VER_26] =
222 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2,
224 [RTL_GIGA_MAC_VER_27] =
225 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
226 [RTL_GIGA_MAC_VER_28] =
227 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
228 [RTL_GIGA_MAC_VER_29] =
229 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
231 [RTL_GIGA_MAC_VER_30] =
232 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
234 [RTL_GIGA_MAC_VER_31] =
235 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
236 [RTL_GIGA_MAC_VER_32] =
237 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1,
239 [RTL_GIGA_MAC_VER_33] =
240 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2,
251 static void rtl_hw_start_8169(struct net_device *);
252 static void rtl_hw_start_8168(struct net_device *);
253 static void rtl_hw_start_8101(struct net_device *);
255 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
256 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
257 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
258 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
259 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
260 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
261 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
262 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
263 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
264 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
265 { PCI_VENDOR_ID_LINKSYS, 0x1032,
266 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
268 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
272 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
274 static int rx_buf_sz = 16383;
281 MAC0 = 0, /* Ethernet hardware address. */
283 MAR0 = 8, /* Multicast filter. */
284 CounterAddrLow = 0x10,
285 CounterAddrHigh = 0x14,
286 TxDescStartAddrLow = 0x20,
287 TxDescStartAddrHigh = 0x24,
288 TxHDescStartAddrLow = 0x28,
289 TxHDescStartAddrHigh = 0x2c,
299 #define RTL_RX_CONFIG_MASK 0xff7e1880u
306 #define PME_SIGNAL (1 << 5) /* 8168c and later */
317 RxDescAddrLow = 0xe4,
318 RxDescAddrHigh = 0xe8,
319 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
321 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
323 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
325 #define TxPacketMax (8064 >> 7)
328 FuncEventMask = 0xf4,
329 FuncPresetState = 0xf8,
330 FuncForceEvent = 0xfc,
333 enum rtl8110_registers {
339 enum rtl8168_8101_registers {
342 #define CSIAR_FLAG 0x80000000
343 #define CSIAR_WRITE_CMD 0x80000000
344 #define CSIAR_BYTE_ENABLE 0x0f
345 #define CSIAR_BYTE_ENABLE_SHIFT 12
346 #define CSIAR_ADDR_MASK 0x0fff
349 #define EPHYAR_FLAG 0x80000000
350 #define EPHYAR_WRITE_CMD 0x80000000
351 #define EPHYAR_REG_MASK 0x1f
352 #define EPHYAR_REG_SHIFT 16
353 #define EPHYAR_DATA_MASK 0xffff
355 #define PM_SWITCH (1 << 6)
357 #define FIX_NAK_1 (1 << 4)
358 #define FIX_NAK_2 (1 << 3)
361 #define EN_NDP (1 << 3)
362 #define EN_OOB_RESET (1 << 2)
364 #define EFUSEAR_FLAG 0x80000000
365 #define EFUSEAR_WRITE_CMD 0x80000000
366 #define EFUSEAR_READ_CMD 0x00000000
367 #define EFUSEAR_REG_MASK 0x03ff
368 #define EFUSEAR_REG_SHIFT 8
369 #define EFUSEAR_DATA_MASK 0xff
372 enum rtl8168_registers {
375 #define ERIAR_FLAG 0x80000000
376 #define ERIAR_WRITE_CMD 0x80000000
377 #define ERIAR_READ_CMD 0x00000000
378 #define ERIAR_ADDR_BYTE_ALIGN 4
379 #define ERIAR_EXGMAC 0
382 #define ERIAR_TYPE_SHIFT 16
383 #define ERIAR_BYTEEN 0x0f
384 #define ERIAR_BYTEEN_SHIFT 12
385 EPHY_RXER_NUM = 0x7c,
386 OCPDR = 0xb0, /* OCP GPHY access */
387 #define OCPDR_WRITE_CMD 0x80000000
388 #define OCPDR_READ_CMD 0x00000000
389 #define OCPDR_REG_MASK 0x7f
390 #define OCPDR_GPHY_REG_SHIFT 16
391 #define OCPDR_DATA_MASK 0xffff
393 #define OCPAR_FLAG 0x80000000
394 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
395 #define OCPAR_GPHY_READ_CMD 0x0000f060
396 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
397 MISC = 0xf0, /* 8168e only. */
398 #define TXPLA_RST (1 << 29)
401 enum rtl_register_content {
402 /* InterruptStatusBits */
406 TxDescUnavail = 0x0080,
429 /* TXPoll register p.5 */
430 HPQ = 0x80, /* Poll cmd on the high prio queue */
431 NPQ = 0x40, /* Poll cmd on the low prio queue */
432 FSWInt = 0x01, /* Forced software interrupt */
436 Cfg9346_Unlock = 0xc0,
441 AcceptBroadcast = 0x08,
442 AcceptMulticast = 0x04,
444 AcceptAllPhys = 0x01,
451 TxInterFrameGapShift = 24,
452 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
454 /* Config1 register p.24 */
457 Speed_down = (1 << 4),
461 PMEnable = (1 << 0), /* Power Management Enable */
463 /* Config2 register p. 25 */
464 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
465 PCI_Clock_66MHz = 0x01,
466 PCI_Clock_33MHz = 0x00,
468 /* Config3 register p.25 */
469 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
470 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
471 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
472 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
474 /* Config4 register */
475 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
477 /* Config5 register p.27 */
478 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
479 MWF = (1 << 5), /* Accept Multicast wakeup frame */
480 UWF = (1 << 4), /* Accept Unicast wakeup frame */
482 LanWake = (1 << 1), /* LanWake enable/disable */
483 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
486 TBIReset = 0x80000000,
487 TBILoopback = 0x40000000,
488 TBINwEnable = 0x20000000,
489 TBINwRestart = 0x10000000,
490 TBILinkOk = 0x02000000,
491 TBINwComplete = 0x01000000,
494 EnableBist = (1 << 15), // 8168 8101
495 Mac_dbgo_oe = (1 << 14), // 8168 8101
496 Normal_mode = (1 << 13), // unused
497 Force_half_dup = (1 << 12), // 8168 8101
498 Force_rxflow_en = (1 << 11), // 8168 8101
499 Force_txflow_en = (1 << 10), // 8168 8101
500 Cxpl_dbg_sel = (1 << 9), // 8168 8101
501 ASF = (1 << 8), // 8168 8101
502 PktCntrDisable = (1 << 7), // 8168 8101
503 Mac_dbgo_sel = 0x001c, // 8168
508 INTT_0 = 0x0000, // 8168
509 INTT_1 = 0x0001, // 8168
510 INTT_2 = 0x0002, // 8168
511 INTT_3 = 0x0003, // 8168
513 /* rtl8169_PHYstatus */
524 TBILinkOK = 0x02000000,
526 /* DumpCounterCommand */
531 /* First doubleword. */
532 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
533 RingEnd = (1 << 30), /* End of descriptor ring */
534 FirstFrag = (1 << 29), /* First segment of a packet */
535 LastFrag = (1 << 28), /* Final segment of a packet */
539 enum rtl_tx_desc_bit {
540 /* First doubleword. */
541 TD_LSO = (1 << 27), /* Large Send Offload */
542 #define TD_MSS_MAX 0x07ffu /* MSS value */
544 /* Second doubleword. */
545 TxVlanTag = (1 << 17), /* Add VLAN tag */
548 /* 8169, 8168b and 810x except 8102e. */
549 enum rtl_tx_desc_bit_0 {
550 /* First doubleword. */
551 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
552 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
553 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
554 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
557 /* 8102e, 8168c and beyond. */
558 enum rtl_tx_desc_bit_1 {
559 /* Second doubleword. */
560 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
561 TD1_IP_CS = (1 << 29), /* Calculate IP checksum */
562 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
563 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
566 static const struct rtl_tx_desc_info {
573 } tx_desc_info [] = {
576 .udp = TD0_IP_CS | TD0_UDP_CS,
577 .tcp = TD0_IP_CS | TD0_TCP_CS
579 .mss_shift = TD0_MSS_SHIFT,
584 .udp = TD1_IP_CS | TD1_UDP_CS,
585 .tcp = TD1_IP_CS | TD1_TCP_CS
587 .mss_shift = TD1_MSS_SHIFT,
592 enum rtl_rx_desc_bit {
594 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
595 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
597 #define RxProtoUDP (PID1)
598 #define RxProtoTCP (PID0)
599 #define RxProtoIP (PID1 | PID0)
600 #define RxProtoMask RxProtoIP
602 IPFail = (1 << 16), /* IP checksum failed */
603 UDPFail = (1 << 15), /* UDP/IP checksum failed */
604 TCPFail = (1 << 14), /* TCP/IP checksum failed */
605 RxVlanTag = (1 << 16), /* VLAN tag available */
608 #define RsvdMask 0x3fffc000
625 u8 __pad[sizeof(void *) - sizeof(u32)];
629 RTL_FEATURE_WOL = (1 << 0),
630 RTL_FEATURE_MSI = (1 << 1),
631 RTL_FEATURE_GMII = (1 << 2),
634 struct rtl8169_counters {
641 __le32 tx_one_collision;
642 __le32 tx_multi_collision;
650 struct rtl8169_private {
651 void __iomem *mmio_addr; /* memory map physical address */
652 struct pci_dev *pci_dev;
653 struct net_device *dev;
654 struct napi_struct napi;
659 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
660 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
663 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
664 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
665 dma_addr_t TxPhyAddr;
666 dma_addr_t RxPhyAddr;
667 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
668 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
669 struct timer_list timer;
676 void (*write)(void __iomem *, int, int);
677 int (*read)(void __iomem *, int);
680 struct pll_power_ops {
681 void (*down)(struct rtl8169_private *);
682 void (*up)(struct rtl8169_private *);
686 void (*enable)(struct rtl8169_private *);
687 void (*disable)(struct rtl8169_private *);
690 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
691 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
692 void (*phy_reset_enable)(struct rtl8169_private *tp);
693 void (*hw_start)(struct net_device *);
694 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
695 unsigned int (*link_ok)(void __iomem *);
696 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
698 struct delayed_work task;
701 struct mii_if_info mii;
702 struct rtl8169_counters counters;
706 const struct firmware *fw;
707 #define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN);
710 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
711 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
712 module_param(use_dac, int, 0);
713 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
714 module_param_named(debug, debug.msg_enable, int, 0);
715 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
716 MODULE_LICENSE("GPL");
717 MODULE_VERSION(RTL8169_VERSION);
718 MODULE_FIRMWARE(FIRMWARE_8168D_1);
719 MODULE_FIRMWARE(FIRMWARE_8168D_2);
720 MODULE_FIRMWARE(FIRMWARE_8168E_1);
721 MODULE_FIRMWARE(FIRMWARE_8168E_2);
722 MODULE_FIRMWARE(FIRMWARE_8105E_1);
724 static int rtl8169_open(struct net_device *dev);
725 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
726 struct net_device *dev);
727 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
728 static int rtl8169_init_ring(struct net_device *dev);
729 static void rtl_hw_start(struct net_device *dev);
730 static int rtl8169_close(struct net_device *dev);
731 static void rtl_set_rx_mode(struct net_device *dev);
732 static void rtl8169_tx_timeout(struct net_device *dev);
733 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
734 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
735 void __iomem *, u32 budget);
736 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
737 static void rtl8169_down(struct net_device *dev);
738 static void rtl8169_rx_clear(struct rtl8169_private *tp);
739 static int rtl8169_poll(struct napi_struct *napi, int budget);
741 static const unsigned int rtl8169_rx_config =
742 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
744 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
746 struct net_device *dev = pci_get_drvdata(pdev);
747 struct rtl8169_private *tp = netdev_priv(dev);
748 int cap = tp->pcie_cap;
753 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
754 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
755 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
759 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
761 void __iomem *ioaddr = tp->mmio_addr;
764 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
765 for (i = 0; i < 20; i++) {
767 if (RTL_R32(OCPAR) & OCPAR_FLAG)
770 return RTL_R32(OCPDR);
773 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
775 void __iomem *ioaddr = tp->mmio_addr;
778 RTL_W32(OCPDR, data);
779 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
780 for (i = 0; i < 20; i++) {
782 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
787 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
789 void __iomem *ioaddr = tp->mmio_addr;
793 RTL_W32(ERIAR, 0x800010e8);
795 for (i = 0; i < 5; i++) {
797 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
801 ocp_write(tp, 0x1, 0x30, 0x00000001);
804 #define OOB_CMD_RESET 0x00
805 #define OOB_CMD_DRIVER_START 0x05
806 #define OOB_CMD_DRIVER_STOP 0x06
808 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
810 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
813 static void rtl8168_driver_start(struct rtl8169_private *tp)
818 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
820 reg = rtl8168_get_ocp_reg(tp);
822 for (i = 0; i < 10; i++) {
824 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
829 static void rtl8168_driver_stop(struct rtl8169_private *tp)
834 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
836 reg = rtl8168_get_ocp_reg(tp);
838 for (i = 0; i < 10; i++) {
840 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
845 static int r8168dp_check_dash(struct rtl8169_private *tp)
847 u16 reg = rtl8168_get_ocp_reg(tp);
849 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
852 static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
856 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
858 for (i = 20; i > 0; i--) {
860 * Check if the RTL8169 has completed writing to the specified
863 if (!(RTL_R32(PHYAR) & 0x80000000))
868 * According to hardware specs a 20us delay is required after write
869 * complete indication, but before sending next command.
874 static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
878 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
880 for (i = 20; i > 0; i--) {
882 * Check if the RTL8169 has completed retrieving data from
883 * the specified MII register.
885 if (RTL_R32(PHYAR) & 0x80000000) {
886 value = RTL_R32(PHYAR) & 0xffff;
892 * According to hardware specs a 20us delay is required after read
893 * complete indication, but before sending next command.
900 static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
904 RTL_W32(OCPDR, data |
905 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
906 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
907 RTL_W32(EPHY_RXER_NUM, 0);
909 for (i = 0; i < 100; i++) {
911 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
916 static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
918 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
919 (value & OCPDR_DATA_MASK));
922 static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
926 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
929 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
930 RTL_W32(EPHY_RXER_NUM, 0);
932 for (i = 0; i < 100; i++) {
934 if (RTL_R32(OCPAR) & OCPAR_FLAG)
938 return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
941 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
943 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
945 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
948 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
950 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
953 static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
955 r8168dp_2_mdio_start(ioaddr);
957 r8169_mdio_write(ioaddr, reg_addr, value);
959 r8168dp_2_mdio_stop(ioaddr);
962 static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
966 r8168dp_2_mdio_start(ioaddr);
968 value = r8169_mdio_read(ioaddr, reg_addr);
970 r8168dp_2_mdio_stop(ioaddr);
975 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
977 tp->mdio_ops.write(tp->mmio_addr, location, val);
980 static int rtl_readphy(struct rtl8169_private *tp, int location)
982 return tp->mdio_ops.read(tp->mmio_addr, location);
985 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
987 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
990 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
994 val = rtl_readphy(tp, reg_addr);
995 rtl_writephy(tp, reg_addr, (val | p) & ~m);
998 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1001 struct rtl8169_private *tp = netdev_priv(dev);
1003 rtl_writephy(tp, location, val);
1006 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1008 struct rtl8169_private *tp = netdev_priv(dev);
1010 return rtl_readphy(tp, location);
1013 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
1017 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1018 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1020 for (i = 0; i < 100; i++) {
1021 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
1027 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
1032 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1034 for (i = 0; i < 100; i++) {
1035 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
1036 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
1045 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
1049 RTL_W32(CSIDR, value);
1050 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
1051 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1053 for (i = 0; i < 100; i++) {
1054 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
1060 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
1065 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
1066 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1068 for (i = 0; i < 100; i++) {
1069 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
1070 value = RTL_R32(CSIDR);
1079 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
1084 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1086 for (i = 0; i < 300; i++) {
1087 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
1088 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
1097 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1099 void __iomem *ioaddr = tp->mmio_addr;
1101 RTL_W16(IntrMask, 0x0000);
1102 RTL_W16(IntrStatus, tp->intr_event);
1106 static void rtl8169_asic_down(struct rtl8169_private *tp)
1108 void __iomem *ioaddr = tp->mmio_addr;
1110 RTL_W8(ChipCmd, 0x00);
1111 rtl8169_irq_mask_and_ack(tp);
1115 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1117 void __iomem *ioaddr = tp->mmio_addr;
1119 return RTL_R32(TBICSR) & TBIReset;
1122 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1124 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1127 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1129 return RTL_R32(TBICSR) & TBILinkOk;
1132 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1134 return RTL_R8(PHYstatus) & LinkStatus;
1137 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1139 void __iomem *ioaddr = tp->mmio_addr;
1141 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1144 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1148 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1149 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1152 static void __rtl8169_check_link_status(struct net_device *dev,
1153 struct rtl8169_private *tp,
1154 void __iomem *ioaddr, bool pm)
1156 unsigned long flags;
1158 spin_lock_irqsave(&tp->lock, flags);
1159 if (tp->link_ok(ioaddr)) {
1160 /* This is to cancel a scheduled suspend if there's one. */
1162 pm_request_resume(&tp->pci_dev->dev);
1163 netif_carrier_on(dev);
1164 if (net_ratelimit())
1165 netif_info(tp, ifup, dev, "link up\n");
1167 netif_carrier_off(dev);
1168 netif_info(tp, ifdown, dev, "link down\n");
1170 pm_schedule_suspend(&tp->pci_dev->dev, 5000);
1172 spin_unlock_irqrestore(&tp->lock, flags);
1175 static void rtl8169_check_link_status(struct net_device *dev,
1176 struct rtl8169_private *tp,
1177 void __iomem *ioaddr)
1179 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1182 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1184 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1186 void __iomem *ioaddr = tp->mmio_addr;
1190 options = RTL_R8(Config1);
1191 if (!(options & PMEnable))
1194 options = RTL_R8(Config3);
1195 if (options & LinkUp)
1196 wolopts |= WAKE_PHY;
1197 if (options & MagicPacket)
1198 wolopts |= WAKE_MAGIC;
1200 options = RTL_R8(Config5);
1202 wolopts |= WAKE_UCAST;
1204 wolopts |= WAKE_BCAST;
1206 wolopts |= WAKE_MCAST;
1211 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1213 struct rtl8169_private *tp = netdev_priv(dev);
1215 spin_lock_irq(&tp->lock);
1217 wol->supported = WAKE_ANY;
1218 wol->wolopts = __rtl8169_get_wol(tp);
1220 spin_unlock_irq(&tp->lock);
1223 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1225 void __iomem *ioaddr = tp->mmio_addr;
1227 static const struct {
1232 { WAKE_PHY, Config3, LinkUp },
1233 { WAKE_MAGIC, Config3, MagicPacket },
1234 { WAKE_UCAST, Config5, UWF },
1235 { WAKE_BCAST, Config5, BWF },
1236 { WAKE_MCAST, Config5, MWF },
1237 { WAKE_ANY, Config5, LanWake }
1241 RTL_W8(Cfg9346, Cfg9346_Unlock);
1243 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1244 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1245 if (wolopts & cfg[i].opt)
1246 options |= cfg[i].mask;
1247 RTL_W8(cfg[i].reg, options);
1250 switch (tp->mac_version) {
1251 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1252 options = RTL_R8(Config1) & ~PMEnable;
1254 options |= PMEnable;
1255 RTL_W8(Config1, options);
1258 options = RTL_R8(Config2) & ~PME_SIGNAL;
1260 options |= PME_SIGNAL;
1261 RTL_W8(Config2, options);
1265 RTL_W8(Cfg9346, Cfg9346_Lock);
1268 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1270 struct rtl8169_private *tp = netdev_priv(dev);
1272 spin_lock_irq(&tp->lock);
1275 tp->features |= RTL_FEATURE_WOL;
1277 tp->features &= ~RTL_FEATURE_WOL;
1278 __rtl8169_set_wol(tp, wol->wolopts);
1279 spin_unlock_irq(&tp->lock);
1281 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1286 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1288 return rtl_chip_infos[tp->mac_version].fw_name;
1291 static void rtl8169_get_drvinfo(struct net_device *dev,
1292 struct ethtool_drvinfo *info)
1294 struct rtl8169_private *tp = netdev_priv(dev);
1296 strcpy(info->driver, MODULENAME);
1297 strcpy(info->version, RTL8169_VERSION);
1298 strcpy(info->bus_info, pci_name(tp->pci_dev));
1299 strncpy(info->fw_version, IS_ERR_OR_NULL(tp->fw) ? "N/A" :
1300 rtl_lookup_firmware_name(tp), sizeof(info->fw_version) - 1);
1303 static int rtl8169_get_regs_len(struct net_device *dev)
1305 return R8169_REGS_SIZE;
1308 static int rtl8169_set_speed_tbi(struct net_device *dev,
1309 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1311 struct rtl8169_private *tp = netdev_priv(dev);
1312 void __iomem *ioaddr = tp->mmio_addr;
1316 reg = RTL_R32(TBICSR);
1317 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1318 (duplex == DUPLEX_FULL)) {
1319 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1320 } else if (autoneg == AUTONEG_ENABLE)
1321 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1323 netif_warn(tp, link, dev,
1324 "incorrect speed setting refused in TBI mode\n");
1331 static int rtl8169_set_speed_xmii(struct net_device *dev,
1332 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1334 struct rtl8169_private *tp = netdev_priv(dev);
1335 int giga_ctrl, bmcr;
1338 rtl_writephy(tp, 0x1f, 0x0000);
1340 if (autoneg == AUTONEG_ENABLE) {
1343 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1344 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1345 ADVERTISE_100HALF | ADVERTISE_100FULL);
1347 if (adv & ADVERTISED_10baseT_Half)
1348 auto_nego |= ADVERTISE_10HALF;
1349 if (adv & ADVERTISED_10baseT_Full)
1350 auto_nego |= ADVERTISE_10FULL;
1351 if (adv & ADVERTISED_100baseT_Half)
1352 auto_nego |= ADVERTISE_100HALF;
1353 if (adv & ADVERTISED_100baseT_Full)
1354 auto_nego |= ADVERTISE_100FULL;
1356 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1358 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1359 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1361 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1362 if (tp->mii.supports_gmii) {
1363 if (adv & ADVERTISED_1000baseT_Half)
1364 giga_ctrl |= ADVERTISE_1000HALF;
1365 if (adv & ADVERTISED_1000baseT_Full)
1366 giga_ctrl |= ADVERTISE_1000FULL;
1367 } else if (adv & (ADVERTISED_1000baseT_Half |
1368 ADVERTISED_1000baseT_Full)) {
1369 netif_info(tp, link, dev,
1370 "PHY does not support 1000Mbps\n");
1374 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1376 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1377 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1381 if (speed == SPEED_10)
1383 else if (speed == SPEED_100)
1384 bmcr = BMCR_SPEED100;
1388 if (duplex == DUPLEX_FULL)
1389 bmcr |= BMCR_FULLDPLX;
1392 rtl_writephy(tp, MII_BMCR, bmcr);
1394 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1395 tp->mac_version == RTL_GIGA_MAC_VER_03) {
1396 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1397 rtl_writephy(tp, 0x17, 0x2138);
1398 rtl_writephy(tp, 0x0e, 0x0260);
1400 rtl_writephy(tp, 0x17, 0x2108);
1401 rtl_writephy(tp, 0x0e, 0x0000);
1410 static int rtl8169_set_speed(struct net_device *dev,
1411 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1413 struct rtl8169_private *tp = netdev_priv(dev);
1416 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1420 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1421 (advertising & ADVERTISED_1000baseT_Full)) {
1422 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1428 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1430 struct rtl8169_private *tp = netdev_priv(dev);
1431 unsigned long flags;
1434 del_timer_sync(&tp->timer);
1436 spin_lock_irqsave(&tp->lock, flags);
1437 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
1438 cmd->duplex, cmd->advertising);
1439 spin_unlock_irqrestore(&tp->lock, flags);
1444 static u32 rtl8169_fix_features(struct net_device *dev, u32 features)
1446 struct rtl8169_private *tp = netdev_priv(dev);
1448 if (dev->mtu > TD_MSS_MAX)
1449 features &= ~NETIF_F_ALL_TSO;
1451 if (dev->mtu > JUMBO_1K &&
1452 !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1453 features &= ~NETIF_F_IP_CSUM;
1458 static int rtl8169_set_features(struct net_device *dev, u32 features)
1460 struct rtl8169_private *tp = netdev_priv(dev);
1461 void __iomem *ioaddr = tp->mmio_addr;
1462 unsigned long flags;
1464 spin_lock_irqsave(&tp->lock, flags);
1466 if (features & NETIF_F_RXCSUM)
1467 tp->cp_cmd |= RxChkSum;
1469 tp->cp_cmd &= ~RxChkSum;
1471 if (dev->features & NETIF_F_HW_VLAN_RX)
1472 tp->cp_cmd |= RxVlan;
1474 tp->cp_cmd &= ~RxVlan;
1476 RTL_W16(CPlusCmd, tp->cp_cmd);
1479 spin_unlock_irqrestore(&tp->lock, flags);
1484 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1485 struct sk_buff *skb)
1487 return (vlan_tx_tag_present(skb)) ?
1488 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1491 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1493 u32 opts2 = le32_to_cpu(desc->opts2);
1495 if (opts2 & RxVlanTag)
1496 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
1501 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1503 struct rtl8169_private *tp = netdev_priv(dev);
1504 void __iomem *ioaddr = tp->mmio_addr;
1508 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1509 cmd->port = PORT_FIBRE;
1510 cmd->transceiver = XCVR_INTERNAL;
1512 status = RTL_R32(TBICSR);
1513 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1514 cmd->autoneg = !!(status & TBINwEnable);
1516 ethtool_cmd_speed_set(cmd, SPEED_1000);
1517 cmd->duplex = DUPLEX_FULL; /* Always set */
1522 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1524 struct rtl8169_private *tp = netdev_priv(dev);
1526 return mii_ethtool_gset(&tp->mii, cmd);
1529 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1531 struct rtl8169_private *tp = netdev_priv(dev);
1532 unsigned long flags;
1535 spin_lock_irqsave(&tp->lock, flags);
1537 rc = tp->get_settings(dev, cmd);
1539 spin_unlock_irqrestore(&tp->lock, flags);
1543 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1546 struct rtl8169_private *tp = netdev_priv(dev);
1547 unsigned long flags;
1549 if (regs->len > R8169_REGS_SIZE)
1550 regs->len = R8169_REGS_SIZE;
1552 spin_lock_irqsave(&tp->lock, flags);
1553 memcpy_fromio(p, tp->mmio_addr, regs->len);
1554 spin_unlock_irqrestore(&tp->lock, flags);
1557 static u32 rtl8169_get_msglevel(struct net_device *dev)
1559 struct rtl8169_private *tp = netdev_priv(dev);
1561 return tp->msg_enable;
1564 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1566 struct rtl8169_private *tp = netdev_priv(dev);
1568 tp->msg_enable = value;
1571 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1578 "tx_single_collisions",
1579 "tx_multi_collisions",
1587 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1591 return ARRAY_SIZE(rtl8169_gstrings);
1597 static void rtl8169_update_counters(struct net_device *dev)
1599 struct rtl8169_private *tp = netdev_priv(dev);
1600 void __iomem *ioaddr = tp->mmio_addr;
1601 struct device *d = &tp->pci_dev->dev;
1602 struct rtl8169_counters *counters;
1608 * Some chips are unable to dump tally counters when the receiver
1611 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1614 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1618 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1619 cmd = (u64)paddr & DMA_BIT_MASK(32);
1620 RTL_W32(CounterAddrLow, cmd);
1621 RTL_W32(CounterAddrLow, cmd | CounterDump);
1624 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1625 memcpy(&tp->counters, counters, sizeof(*counters));
1631 RTL_W32(CounterAddrLow, 0);
1632 RTL_W32(CounterAddrHigh, 0);
1634 dma_free_coherent(d, sizeof(*counters), counters, paddr);
1637 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1638 struct ethtool_stats *stats, u64 *data)
1640 struct rtl8169_private *tp = netdev_priv(dev);
1644 rtl8169_update_counters(dev);
1646 data[0] = le64_to_cpu(tp->counters.tx_packets);
1647 data[1] = le64_to_cpu(tp->counters.rx_packets);
1648 data[2] = le64_to_cpu(tp->counters.tx_errors);
1649 data[3] = le32_to_cpu(tp->counters.rx_errors);
1650 data[4] = le16_to_cpu(tp->counters.rx_missed);
1651 data[5] = le16_to_cpu(tp->counters.align_errors);
1652 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1653 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1654 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1655 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1656 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1657 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1658 data[12] = le16_to_cpu(tp->counters.tx_underun);
1661 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1665 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1670 static const struct ethtool_ops rtl8169_ethtool_ops = {
1671 .get_drvinfo = rtl8169_get_drvinfo,
1672 .get_regs_len = rtl8169_get_regs_len,
1673 .get_link = ethtool_op_get_link,
1674 .get_settings = rtl8169_get_settings,
1675 .set_settings = rtl8169_set_settings,
1676 .get_msglevel = rtl8169_get_msglevel,
1677 .set_msglevel = rtl8169_set_msglevel,
1678 .get_regs = rtl8169_get_regs,
1679 .get_wol = rtl8169_get_wol,
1680 .set_wol = rtl8169_set_wol,
1681 .get_strings = rtl8169_get_strings,
1682 .get_sset_count = rtl8169_get_sset_count,
1683 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1686 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1687 struct net_device *dev, u8 default_version)
1689 void __iomem *ioaddr = tp->mmio_addr;
1691 * The driver currently handles the 8168Bf and the 8168Be identically
1692 * but they can be identified more specifically through the test below
1695 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1697 * Same thing for the 8101Eb and the 8101Ec:
1699 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1701 static const struct rtl_mac_info {
1707 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
1708 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
1709 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
1712 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
1713 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
1714 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
1716 /* 8168DP family. */
1717 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
1718 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
1719 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
1722 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
1723 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
1724 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
1725 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
1726 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1727 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
1728 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
1729 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
1730 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
1733 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1734 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1735 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1736 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1739 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
1740 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
1741 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
1742 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
1743 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1744 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1745 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1746 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1747 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1748 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
1749 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
1750 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
1751 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
1752 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1753 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
1754 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1755 /* FIXME: where did these entries come from ? -- FR */
1756 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1757 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1760 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1761 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1762 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1763 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1764 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1765 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1768 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
1770 const struct rtl_mac_info *p = mac_info;
1773 reg = RTL_R32(TxConfig);
1774 while ((reg & p->mask) != p->val)
1776 tp->mac_version = p->mac_version;
1778 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
1779 netif_notice(tp, probe, dev,
1780 "unknown MAC, using family default\n");
1781 tp->mac_version = default_version;
1785 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1787 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1795 static void rtl_writephy_batch(struct rtl8169_private *tp,
1796 const struct phy_reg *regs, int len)
1799 rtl_writephy(tp, regs->reg, regs->val);
1804 #define PHY_READ 0x00000000
1805 #define PHY_DATA_OR 0x10000000
1806 #define PHY_DATA_AND 0x20000000
1807 #define PHY_BJMPN 0x30000000
1808 #define PHY_READ_EFUSE 0x40000000
1809 #define PHY_READ_MAC_BYTE 0x50000000
1810 #define PHY_WRITE_MAC_BYTE 0x60000000
1811 #define PHY_CLEAR_READCOUNT 0x70000000
1812 #define PHY_WRITE 0x80000000
1813 #define PHY_READCOUNT_EQ_SKIP 0x90000000
1814 #define PHY_COMP_EQ_SKIPN 0xa0000000
1815 #define PHY_COMP_NEQ_SKIPN 0xb0000000
1816 #define PHY_WRITE_PREVIOUS 0xc0000000
1817 #define PHY_SKIPN 0xd0000000
1818 #define PHY_DELAY_MS 0xe0000000
1819 #define PHY_WRITE_ERI_WORD 0xf0000000
1822 rtl_phy_write_fw(struct rtl8169_private *tp, const struct firmware *fw)
1824 __le32 *phytable = (__le32 *)fw->data;
1825 struct net_device *dev = tp->dev;
1826 size_t index, fw_size = fw->size / sizeof(*phytable);
1829 if (fw->size % sizeof(*phytable)) {
1830 netif_err(tp, probe, dev, "odd sized firmware %zd\n", fw->size);
1834 for (index = 0; index < fw_size; index++) {
1835 u32 action = le32_to_cpu(phytable[index]);
1836 u32 regno = (action & 0x0fff0000) >> 16;
1838 switch(action & 0xf0000000) {
1842 case PHY_READ_EFUSE:
1843 case PHY_CLEAR_READCOUNT:
1845 case PHY_WRITE_PREVIOUS:
1850 if (regno > index) {
1851 netif_err(tp, probe, tp->dev,
1852 "Out of range of firmware\n");
1856 case PHY_READCOUNT_EQ_SKIP:
1857 if (index + 2 >= fw_size) {
1858 netif_err(tp, probe, tp->dev,
1859 "Out of range of firmware\n");
1863 case PHY_COMP_EQ_SKIPN:
1864 case PHY_COMP_NEQ_SKIPN:
1866 if (index + 1 + regno >= fw_size) {
1867 netif_err(tp, probe, tp->dev,
1868 "Out of range of firmware\n");
1873 case PHY_READ_MAC_BYTE:
1874 case PHY_WRITE_MAC_BYTE:
1875 case PHY_WRITE_ERI_WORD:
1877 netif_err(tp, probe, tp->dev,
1878 "Invalid action 0x%08x\n", action);
1886 for (index = 0; index < fw_size; ) {
1887 u32 action = le32_to_cpu(phytable[index]);
1888 u32 data = action & 0x0000ffff;
1889 u32 regno = (action & 0x0fff0000) >> 16;
1894 switch(action & 0xf0000000) {
1896 predata = rtl_readphy(tp, regno);
1911 case PHY_READ_EFUSE:
1912 predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
1915 case PHY_CLEAR_READCOUNT:
1920 rtl_writephy(tp, regno, data);
1923 case PHY_READCOUNT_EQ_SKIP:
1924 index += (count == data) ? 2 : 1;
1926 case PHY_COMP_EQ_SKIPN:
1927 if (predata == data)
1931 case PHY_COMP_NEQ_SKIPN:
1932 if (predata != data)
1936 case PHY_WRITE_PREVIOUS:
1937 rtl_writephy(tp, regno, predata);
1948 case PHY_READ_MAC_BYTE:
1949 case PHY_WRITE_MAC_BYTE:
1950 case PHY_WRITE_ERI_WORD:
1957 static void rtl_release_firmware(struct rtl8169_private *tp)
1959 if (!IS_ERR_OR_NULL(tp->fw))
1960 release_firmware(tp->fw);
1961 tp->fw = RTL_FIRMWARE_UNKNOWN;
1964 static void rtl_apply_firmware(struct rtl8169_private *tp)
1966 const struct firmware *fw = tp->fw;
1968 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
1969 if (!IS_ERR_OR_NULL(fw))
1970 rtl_phy_write_fw(tp, fw);
1973 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
1975 if (rtl_readphy(tp, reg) != val)
1976 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
1978 rtl_apply_firmware(tp);
1981 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1983 static const struct phy_reg phy_reg_init[] = {
2045 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2048 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2050 static const struct phy_reg phy_reg_init[] = {
2056 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2059 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2061 struct pci_dev *pdev = tp->pci_dev;
2062 u16 vendor_id, device_id;
2064 pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
2065 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
2067 if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
2070 rtl_writephy(tp, 0x1f, 0x0001);
2071 rtl_writephy(tp, 0x10, 0xf01b);
2072 rtl_writephy(tp, 0x1f, 0x0000);
2075 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2077 static const struct phy_reg phy_reg_init[] = {
2117 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2119 rtl8169scd_hw_phy_config_quirk(tp);
2122 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2124 static const struct phy_reg phy_reg_init[] = {
2172 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2175 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2177 static const struct phy_reg phy_reg_init[] = {
2182 rtl_writephy(tp, 0x1f, 0x0001);
2183 rtl_patchphy(tp, 0x16, 1 << 0);
2185 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2188 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2190 static const struct phy_reg phy_reg_init[] = {
2196 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2199 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2201 static const struct phy_reg phy_reg_init[] = {
2209 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2212 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2214 static const struct phy_reg phy_reg_init[] = {
2220 rtl_writephy(tp, 0x1f, 0x0000);
2221 rtl_patchphy(tp, 0x14, 1 << 5);
2222 rtl_patchphy(tp, 0x0d, 1 << 5);
2224 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2227 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2229 static const struct phy_reg phy_reg_init[] = {
2249 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2251 rtl_patchphy(tp, 0x14, 1 << 5);
2252 rtl_patchphy(tp, 0x0d, 1 << 5);
2253 rtl_writephy(tp, 0x1f, 0x0000);
2256 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2258 static const struct phy_reg phy_reg_init[] = {
2276 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2278 rtl_patchphy(tp, 0x16, 1 << 0);
2279 rtl_patchphy(tp, 0x14, 1 << 5);
2280 rtl_patchphy(tp, 0x0d, 1 << 5);
2281 rtl_writephy(tp, 0x1f, 0x0000);
2284 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2286 static const struct phy_reg phy_reg_init[] = {
2298 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2300 rtl_patchphy(tp, 0x16, 1 << 0);
2301 rtl_patchphy(tp, 0x14, 1 << 5);
2302 rtl_patchphy(tp, 0x0d, 1 << 5);
2303 rtl_writephy(tp, 0x1f, 0x0000);
2306 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2308 rtl8168c_3_hw_phy_config(tp);
2311 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2313 static const struct phy_reg phy_reg_init_0[] = {
2314 /* Channel Estimation */
2335 * Enhance line driver power
2344 * Can not link to 1Gbps with bad cable
2345 * Decrease SNR threshold form 21.07dB to 19.04dB
2353 void __iomem *ioaddr = tp->mmio_addr;
2355 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2359 * Fine Tune Switching regulator parameter
2361 rtl_writephy(tp, 0x1f, 0x0002);
2362 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2363 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2365 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2366 static const struct phy_reg phy_reg_init[] = {
2376 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2378 val = rtl_readphy(tp, 0x0d);
2380 if ((val & 0x00ff) != 0x006c) {
2381 static const u32 set[] = {
2382 0x0065, 0x0066, 0x0067, 0x0068,
2383 0x0069, 0x006a, 0x006b, 0x006c
2387 rtl_writephy(tp, 0x1f, 0x0002);
2390 for (i = 0; i < ARRAY_SIZE(set); i++)
2391 rtl_writephy(tp, 0x0d, val | set[i]);
2394 static const struct phy_reg phy_reg_init[] = {
2402 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2405 /* RSET couple improve */
2406 rtl_writephy(tp, 0x1f, 0x0002);
2407 rtl_patchphy(tp, 0x0d, 0x0300);
2408 rtl_patchphy(tp, 0x0f, 0x0010);
2410 /* Fine tune PLL performance */
2411 rtl_writephy(tp, 0x1f, 0x0002);
2412 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2413 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2415 rtl_writephy(tp, 0x1f, 0x0005);
2416 rtl_writephy(tp, 0x05, 0x001b);
2418 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2420 rtl_writephy(tp, 0x1f, 0x0000);
2423 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2425 static const struct phy_reg phy_reg_init_0[] = {
2426 /* Channel Estimation */
2447 * Enhance line driver power
2456 * Can not link to 1Gbps with bad cable
2457 * Decrease SNR threshold form 21.07dB to 19.04dB
2465 void __iomem *ioaddr = tp->mmio_addr;
2467 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2469 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2470 static const struct phy_reg phy_reg_init[] = {
2481 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2483 val = rtl_readphy(tp, 0x0d);
2484 if ((val & 0x00ff) != 0x006c) {
2485 static const u32 set[] = {
2486 0x0065, 0x0066, 0x0067, 0x0068,
2487 0x0069, 0x006a, 0x006b, 0x006c
2491 rtl_writephy(tp, 0x1f, 0x0002);
2494 for (i = 0; i < ARRAY_SIZE(set); i++)
2495 rtl_writephy(tp, 0x0d, val | set[i]);
2498 static const struct phy_reg phy_reg_init[] = {
2506 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2509 /* Fine tune PLL performance */
2510 rtl_writephy(tp, 0x1f, 0x0002);
2511 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2512 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2514 /* Switching regulator Slew rate */
2515 rtl_writephy(tp, 0x1f, 0x0002);
2516 rtl_patchphy(tp, 0x0f, 0x0017);
2518 rtl_writephy(tp, 0x1f, 0x0005);
2519 rtl_writephy(tp, 0x05, 0x001b);
2521 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2523 rtl_writephy(tp, 0x1f, 0x0000);
2526 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2528 static const struct phy_reg phy_reg_init[] = {
2584 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2587 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2589 static const struct phy_reg phy_reg_init[] = {
2599 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2600 rtl_patchphy(tp, 0x0d, 1 << 5);
2603 static void rtl8168e_hw_phy_config(struct rtl8169_private *tp)
2605 static const struct phy_reg phy_reg_init[] = {
2606 /* Enable Delay cap */
2612 /* Channel estimation fine tune */
2621 /* Update PFM & 10M TX idle timer */
2633 rtl_apply_firmware(tp);
2635 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2637 /* DCO enable for 10M IDLE Power */
2638 rtl_writephy(tp, 0x1f, 0x0007);
2639 rtl_writephy(tp, 0x1e, 0x0023);
2640 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2641 rtl_writephy(tp, 0x1f, 0x0000);
2643 /* For impedance matching */
2644 rtl_writephy(tp, 0x1f, 0x0002);
2645 rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
2646 rtl_writephy(tp, 0x1f, 0x0000);
2648 /* PHY auto speed down */
2649 rtl_writephy(tp, 0x1f, 0x0007);
2650 rtl_writephy(tp, 0x1e, 0x002d);
2651 rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2652 rtl_writephy(tp, 0x1f, 0x0000);
2653 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2655 rtl_writephy(tp, 0x1f, 0x0005);
2656 rtl_writephy(tp, 0x05, 0x8b86);
2657 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2658 rtl_writephy(tp, 0x1f, 0x0000);
2660 rtl_writephy(tp, 0x1f, 0x0005);
2661 rtl_writephy(tp, 0x05, 0x8b85);
2662 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2663 rtl_writephy(tp, 0x1f, 0x0007);
2664 rtl_writephy(tp, 0x1e, 0x0020);
2665 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2666 rtl_writephy(tp, 0x1f, 0x0006);
2667 rtl_writephy(tp, 0x00, 0x5a00);
2668 rtl_writephy(tp, 0x1f, 0x0000);
2669 rtl_writephy(tp, 0x0d, 0x0007);
2670 rtl_writephy(tp, 0x0e, 0x003c);
2671 rtl_writephy(tp, 0x0d, 0x4007);
2672 rtl_writephy(tp, 0x0e, 0x0000);
2673 rtl_writephy(tp, 0x0d, 0x0000);
2676 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2678 static const struct phy_reg phy_reg_init[] = {
2685 rtl_writephy(tp, 0x1f, 0x0000);
2686 rtl_patchphy(tp, 0x11, 1 << 12);
2687 rtl_patchphy(tp, 0x19, 1 << 13);
2688 rtl_patchphy(tp, 0x10, 1 << 15);
2690 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2693 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
2695 static const struct phy_reg phy_reg_init[] = {
2709 /* Disable ALDPS before ram code */
2710 rtl_writephy(tp, 0x1f, 0x0000);
2711 rtl_writephy(tp, 0x18, 0x0310);
2714 rtl_apply_firmware(tp);
2716 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2719 static void rtl_hw_phy_config(struct net_device *dev)
2721 struct rtl8169_private *tp = netdev_priv(dev);
2723 rtl8169_print_mac_version(tp);
2725 switch (tp->mac_version) {
2726 case RTL_GIGA_MAC_VER_01:
2728 case RTL_GIGA_MAC_VER_02:
2729 case RTL_GIGA_MAC_VER_03:
2730 rtl8169s_hw_phy_config(tp);
2732 case RTL_GIGA_MAC_VER_04:
2733 rtl8169sb_hw_phy_config(tp);
2735 case RTL_GIGA_MAC_VER_05:
2736 rtl8169scd_hw_phy_config(tp);
2738 case RTL_GIGA_MAC_VER_06:
2739 rtl8169sce_hw_phy_config(tp);
2741 case RTL_GIGA_MAC_VER_07:
2742 case RTL_GIGA_MAC_VER_08:
2743 case RTL_GIGA_MAC_VER_09:
2744 rtl8102e_hw_phy_config(tp);
2746 case RTL_GIGA_MAC_VER_11:
2747 rtl8168bb_hw_phy_config(tp);
2749 case RTL_GIGA_MAC_VER_12:
2750 rtl8168bef_hw_phy_config(tp);
2752 case RTL_GIGA_MAC_VER_17:
2753 rtl8168bef_hw_phy_config(tp);
2755 case RTL_GIGA_MAC_VER_18:
2756 rtl8168cp_1_hw_phy_config(tp);
2758 case RTL_GIGA_MAC_VER_19:
2759 rtl8168c_1_hw_phy_config(tp);
2761 case RTL_GIGA_MAC_VER_20:
2762 rtl8168c_2_hw_phy_config(tp);
2764 case RTL_GIGA_MAC_VER_21:
2765 rtl8168c_3_hw_phy_config(tp);
2767 case RTL_GIGA_MAC_VER_22:
2768 rtl8168c_4_hw_phy_config(tp);
2770 case RTL_GIGA_MAC_VER_23:
2771 case RTL_GIGA_MAC_VER_24:
2772 rtl8168cp_2_hw_phy_config(tp);
2774 case RTL_GIGA_MAC_VER_25:
2775 rtl8168d_1_hw_phy_config(tp);
2777 case RTL_GIGA_MAC_VER_26:
2778 rtl8168d_2_hw_phy_config(tp);
2780 case RTL_GIGA_MAC_VER_27:
2781 rtl8168d_3_hw_phy_config(tp);
2783 case RTL_GIGA_MAC_VER_28:
2784 rtl8168d_4_hw_phy_config(tp);
2786 case RTL_GIGA_MAC_VER_29:
2787 case RTL_GIGA_MAC_VER_30:
2788 rtl8105e_hw_phy_config(tp);
2790 case RTL_GIGA_MAC_VER_31:
2793 case RTL_GIGA_MAC_VER_32:
2794 case RTL_GIGA_MAC_VER_33:
2795 rtl8168e_hw_phy_config(tp);
2803 static void rtl8169_phy_timer(unsigned long __opaque)
2805 struct net_device *dev = (struct net_device *)__opaque;
2806 struct rtl8169_private *tp = netdev_priv(dev);
2807 struct timer_list *timer = &tp->timer;
2808 void __iomem *ioaddr = tp->mmio_addr;
2809 unsigned long timeout = RTL8169_PHY_TIMEOUT;
2811 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
2813 spin_lock_irq(&tp->lock);
2815 if (tp->phy_reset_pending(tp)) {
2817 * A busy loop could burn quite a few cycles on nowadays CPU.
2818 * Let's delay the execution of the timer for a few ticks.
2824 if (tp->link_ok(ioaddr))
2827 netif_warn(tp, link, dev, "PHY reset until link up\n");
2829 tp->phy_reset_enable(tp);
2832 mod_timer(timer, jiffies + timeout);
2834 spin_unlock_irq(&tp->lock);
2837 #ifdef CONFIG_NET_POLL_CONTROLLER
2839 * Polling 'interrupt' - used by things like netconsole to send skbs
2840 * without having to re-enable interrupts. It's not called while
2841 * the interrupt routine is executing.
2843 static void rtl8169_netpoll(struct net_device *dev)
2845 struct rtl8169_private *tp = netdev_priv(dev);
2846 struct pci_dev *pdev = tp->pci_dev;
2848 disable_irq(pdev->irq);
2849 rtl8169_interrupt(pdev->irq, dev);
2850 enable_irq(pdev->irq);
2854 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
2855 void __iomem *ioaddr)
2858 pci_release_regions(pdev);
2859 pci_clear_mwi(pdev);
2860 pci_disable_device(pdev);
2864 static void rtl8169_phy_reset(struct net_device *dev,
2865 struct rtl8169_private *tp)
2869 tp->phy_reset_enable(tp);
2870 for (i = 0; i < 100; i++) {
2871 if (!tp->phy_reset_pending(tp))
2875 netif_err(tp, link, dev, "PHY reset failed\n");
2878 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
2880 void __iomem *ioaddr = tp->mmio_addr;
2882 rtl_hw_phy_config(dev);
2884 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2885 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2889 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2891 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
2892 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
2894 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
2895 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2897 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
2898 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
2901 rtl8169_phy_reset(dev, tp);
2903 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
2904 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
2905 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
2906 (tp->mii.supports_gmii ?
2907 ADVERTISED_1000baseT_Half |
2908 ADVERTISED_1000baseT_Full : 0));
2910 if (RTL_R8(PHYstatus) & TBI_Enable)
2911 netif_info(tp, link, dev, "TBI auto-negotiating\n");
2914 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2916 void __iomem *ioaddr = tp->mmio_addr;
2920 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
2921 high = addr[4] | (addr[5] << 8);
2923 spin_lock_irq(&tp->lock);
2925 RTL_W8(Cfg9346, Cfg9346_Unlock);
2927 RTL_W32(MAC4, high);
2933 RTL_W8(Cfg9346, Cfg9346_Lock);
2935 spin_unlock_irq(&tp->lock);
2938 static int rtl_set_mac_address(struct net_device *dev, void *p)
2940 struct rtl8169_private *tp = netdev_priv(dev);
2941 struct sockaddr *addr = p;
2943 if (!is_valid_ether_addr(addr->sa_data))
2944 return -EADDRNOTAVAIL;
2946 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2948 rtl_rar_set(tp, dev->dev_addr);
2953 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2955 struct rtl8169_private *tp = netdev_priv(dev);
2956 struct mii_ioctl_data *data = if_mii(ifr);
2958 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
2961 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
2962 struct mii_ioctl_data *data, int cmd)
2966 data->phy_id = 32; /* Internal PHY */
2970 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
2974 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
2980 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2985 static const struct rtl_cfg_info {
2986 void (*hw_start)(struct net_device *);
2987 unsigned int region;
2993 } rtl_cfg_infos [] = {
2995 .hw_start = rtl_hw_start_8169,
2998 .intr_event = SYSErr | LinkChg | RxOverflow |
2999 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
3000 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
3001 .features = RTL_FEATURE_GMII,
3002 .default_ver = RTL_GIGA_MAC_VER_01,
3005 .hw_start = rtl_hw_start_8168,
3008 .intr_event = SYSErr | LinkChg | RxOverflow |
3009 TxErr | TxOK | RxOK | RxErr,
3010 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
3011 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
3012 .default_ver = RTL_GIGA_MAC_VER_11,
3015 .hw_start = rtl_hw_start_8101,
3018 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
3019 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
3020 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
3021 .features = RTL_FEATURE_MSI,
3022 .default_ver = RTL_GIGA_MAC_VER_13,
3026 /* Cfg9346_Unlock assumed. */
3027 static unsigned rtl_try_msi(struct rtl8169_private *tp,
3028 const struct rtl_cfg_info *cfg)
3030 void __iomem *ioaddr = tp->mmio_addr;
3034 cfg2 = RTL_R8(Config2) & ~MSIEnable;
3035 if (cfg->features & RTL_FEATURE_MSI) {
3036 if (pci_enable_msi(tp->pci_dev)) {
3037 netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
3040 msi = RTL_FEATURE_MSI;
3043 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3044 RTL_W8(Config2, cfg2);
3048 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3050 if (tp->features & RTL_FEATURE_MSI) {
3051 pci_disable_msi(pdev);
3052 tp->features &= ~RTL_FEATURE_MSI;
3056 static const struct net_device_ops rtl8169_netdev_ops = {
3057 .ndo_open = rtl8169_open,
3058 .ndo_stop = rtl8169_close,
3059 .ndo_get_stats = rtl8169_get_stats,
3060 .ndo_start_xmit = rtl8169_start_xmit,
3061 .ndo_tx_timeout = rtl8169_tx_timeout,
3062 .ndo_validate_addr = eth_validate_addr,
3063 .ndo_change_mtu = rtl8169_change_mtu,
3064 .ndo_fix_features = rtl8169_fix_features,
3065 .ndo_set_features = rtl8169_set_features,
3066 .ndo_set_mac_address = rtl_set_mac_address,
3067 .ndo_do_ioctl = rtl8169_ioctl,
3068 .ndo_set_multicast_list = rtl_set_rx_mode,
3069 #ifdef CONFIG_NET_POLL_CONTROLLER
3070 .ndo_poll_controller = rtl8169_netpoll,
3075 static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
3077 struct mdio_ops *ops = &tp->mdio_ops;
3079 switch (tp->mac_version) {
3080 case RTL_GIGA_MAC_VER_27:
3081 ops->write = r8168dp_1_mdio_write;
3082 ops->read = r8168dp_1_mdio_read;
3084 case RTL_GIGA_MAC_VER_28:
3085 case RTL_GIGA_MAC_VER_31:
3086 ops->write = r8168dp_2_mdio_write;
3087 ops->read = r8168dp_2_mdio_read;
3090 ops->write = r8169_mdio_write;
3091 ops->read = r8169_mdio_read;
3096 static void r810x_phy_power_down(struct rtl8169_private *tp)
3098 rtl_writephy(tp, 0x1f, 0x0000);
3099 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3102 static void r810x_phy_power_up(struct rtl8169_private *tp)
3104 rtl_writephy(tp, 0x1f, 0x0000);
3105 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3108 static void r810x_pll_power_down(struct rtl8169_private *tp)
3110 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3111 rtl_writephy(tp, 0x1f, 0x0000);
3112 rtl_writephy(tp, MII_BMCR, 0x0000);
3116 r810x_phy_power_down(tp);
3119 static void r810x_pll_power_up(struct rtl8169_private *tp)
3121 r810x_phy_power_up(tp);
3124 static void r8168_phy_power_up(struct rtl8169_private *tp)
3126 rtl_writephy(tp, 0x1f, 0x0000);
3127 switch (tp->mac_version) {
3128 case RTL_GIGA_MAC_VER_11:
3129 case RTL_GIGA_MAC_VER_12:
3130 case RTL_GIGA_MAC_VER_17:
3131 case RTL_GIGA_MAC_VER_18:
3132 case RTL_GIGA_MAC_VER_19:
3133 case RTL_GIGA_MAC_VER_20:
3134 case RTL_GIGA_MAC_VER_21:
3135 case RTL_GIGA_MAC_VER_22:
3136 case RTL_GIGA_MAC_VER_23:
3137 case RTL_GIGA_MAC_VER_24:
3138 case RTL_GIGA_MAC_VER_25:
3139 case RTL_GIGA_MAC_VER_26:
3140 case RTL_GIGA_MAC_VER_27:
3141 case RTL_GIGA_MAC_VER_28:
3142 case RTL_GIGA_MAC_VER_31:
3143 rtl_writephy(tp, 0x0e, 0x0000);
3148 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3151 static void r8168_phy_power_down(struct rtl8169_private *tp)
3153 rtl_writephy(tp, 0x1f, 0x0000);
3154 switch (tp->mac_version) {
3155 case RTL_GIGA_MAC_VER_32:
3156 case RTL_GIGA_MAC_VER_33:
3157 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3160 case RTL_GIGA_MAC_VER_11:
3161 case RTL_GIGA_MAC_VER_12:
3162 case RTL_GIGA_MAC_VER_17:
3163 case RTL_GIGA_MAC_VER_18:
3164 case RTL_GIGA_MAC_VER_19:
3165 case RTL_GIGA_MAC_VER_20:
3166 case RTL_GIGA_MAC_VER_21:
3167 case RTL_GIGA_MAC_VER_22:
3168 case RTL_GIGA_MAC_VER_23:
3169 case RTL_GIGA_MAC_VER_24:
3170 case RTL_GIGA_MAC_VER_25:
3171 case RTL_GIGA_MAC_VER_26:
3172 case RTL_GIGA_MAC_VER_27:
3173 case RTL_GIGA_MAC_VER_28:
3174 case RTL_GIGA_MAC_VER_31:
3175 rtl_writephy(tp, 0x0e, 0x0200);
3177 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3182 static void r8168_pll_power_down(struct rtl8169_private *tp)
3184 void __iomem *ioaddr = tp->mmio_addr;
3186 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3187 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3188 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3189 r8168dp_check_dash(tp)) {
3193 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
3194 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
3195 (RTL_R16(CPlusCmd) & ASF)) {
3199 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3200 tp->mac_version == RTL_GIGA_MAC_VER_33)
3201 rtl_ephy_write(ioaddr, 0x19, 0xff64);
3203 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3204 rtl_writephy(tp, 0x1f, 0x0000);
3205 rtl_writephy(tp, MII_BMCR, 0x0000);
3207 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3208 tp->mac_version == RTL_GIGA_MAC_VER_33)
3209 RTL_W32(RxConfig, RTL_R32(RxConfig) | AcceptBroadcast |
3210 AcceptMulticast | AcceptMyPhys);
3214 r8168_phy_power_down(tp);
3216 switch (tp->mac_version) {
3217 case RTL_GIGA_MAC_VER_25:
3218 case RTL_GIGA_MAC_VER_26:
3219 case RTL_GIGA_MAC_VER_27:
3220 case RTL_GIGA_MAC_VER_28:
3221 case RTL_GIGA_MAC_VER_31:
3222 case RTL_GIGA_MAC_VER_32:
3223 case RTL_GIGA_MAC_VER_33:
3224 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3229 static void r8168_pll_power_up(struct rtl8169_private *tp)
3231 void __iomem *ioaddr = tp->mmio_addr;
3233 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3234 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3235 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3236 r8168dp_check_dash(tp)) {
3240 switch (tp->mac_version) {
3241 case RTL_GIGA_MAC_VER_25:
3242 case RTL_GIGA_MAC_VER_26:
3243 case RTL_GIGA_MAC_VER_27:
3244 case RTL_GIGA_MAC_VER_28:
3245 case RTL_GIGA_MAC_VER_31:
3246 case RTL_GIGA_MAC_VER_32:
3247 case RTL_GIGA_MAC_VER_33:
3248 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3252 r8168_phy_power_up(tp);
3255 static void rtl_generic_op(struct rtl8169_private *tp,
3256 void (*op)(struct rtl8169_private *))
3262 static void rtl_pll_power_down(struct rtl8169_private *tp)
3264 rtl_generic_op(tp, tp->pll_power_ops.down);
3267 static void rtl_pll_power_up(struct rtl8169_private *tp)
3269 rtl_generic_op(tp, tp->pll_power_ops.up);
3272 static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3274 struct pll_power_ops *ops = &tp->pll_power_ops;
3276 switch (tp->mac_version) {
3277 case RTL_GIGA_MAC_VER_07:
3278 case RTL_GIGA_MAC_VER_08:
3279 case RTL_GIGA_MAC_VER_09:
3280 case RTL_GIGA_MAC_VER_10:
3281 case RTL_GIGA_MAC_VER_16:
3282 case RTL_GIGA_MAC_VER_29:
3283 case RTL_GIGA_MAC_VER_30:
3284 ops->down = r810x_pll_power_down;
3285 ops->up = r810x_pll_power_up;
3288 case RTL_GIGA_MAC_VER_11:
3289 case RTL_GIGA_MAC_VER_12:
3290 case RTL_GIGA_MAC_VER_17:
3291 case RTL_GIGA_MAC_VER_18:
3292 case RTL_GIGA_MAC_VER_19:
3293 case RTL_GIGA_MAC_VER_20:
3294 case RTL_GIGA_MAC_VER_21:
3295 case RTL_GIGA_MAC_VER_22:
3296 case RTL_GIGA_MAC_VER_23:
3297 case RTL_GIGA_MAC_VER_24:
3298 case RTL_GIGA_MAC_VER_25:
3299 case RTL_GIGA_MAC_VER_26:
3300 case RTL_GIGA_MAC_VER_27:
3301 case RTL_GIGA_MAC_VER_28:
3302 case RTL_GIGA_MAC_VER_31:
3303 case RTL_GIGA_MAC_VER_32:
3304 case RTL_GIGA_MAC_VER_33:
3305 ops->down = r8168_pll_power_down;
3306 ops->up = r8168_pll_power_up;
3316 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
3318 rtl_generic_op(tp, tp->jumbo_ops.enable);
3321 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
3323 rtl_generic_op(tp, tp->jumbo_ops.disable);
3326 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
3328 void __iomem *ioaddr = tp->mmio_addr;
3330 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3331 RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
3332 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
3335 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
3337 void __iomem *ioaddr = tp->mmio_addr;
3339 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3340 RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
3341 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
3344 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
3346 void __iomem *ioaddr = tp->mmio_addr;
3348 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3351 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
3353 void __iomem *ioaddr = tp->mmio_addr;
3355 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3358 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
3360 void __iomem *ioaddr = tp->mmio_addr;
3361 struct pci_dev *pdev = tp->pci_dev;
3363 RTL_W8(MaxTxPacketSize, 0x3f);
3364 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3365 RTL_W8(Config4, RTL_R8(Config4) | 0x01);
3366 pci_write_config_byte(pdev, 0x79, 0x20);
3369 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
3371 void __iomem *ioaddr = tp->mmio_addr;
3372 struct pci_dev *pdev = tp->pci_dev;
3374 RTL_W8(MaxTxPacketSize, 0x0c);
3375 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3376 RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
3377 pci_write_config_byte(pdev, 0x79, 0x50);
3380 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
3382 rtl_tx_performance_tweak(tp->pci_dev,
3383 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3386 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
3388 rtl_tx_performance_tweak(tp->pci_dev,
3389 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3392 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
3394 void __iomem *ioaddr = tp->mmio_addr;
3396 r8168b_0_hw_jumbo_enable(tp);
3398 RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
3401 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
3403 void __iomem *ioaddr = tp->mmio_addr;
3405 r8168b_0_hw_jumbo_disable(tp);
3407 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
3410 static void __devinit rtl_init_jumbo_ops(struct rtl8169_private *tp)
3412 struct jumbo_ops *ops = &tp->jumbo_ops;
3414 switch (tp->mac_version) {
3415 case RTL_GIGA_MAC_VER_11:
3416 ops->disable = r8168b_0_hw_jumbo_disable;
3417 ops->enable = r8168b_0_hw_jumbo_enable;
3419 case RTL_GIGA_MAC_VER_12:
3420 case RTL_GIGA_MAC_VER_17:
3421 ops->disable = r8168b_1_hw_jumbo_disable;
3422 ops->enable = r8168b_1_hw_jumbo_enable;
3424 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
3425 case RTL_GIGA_MAC_VER_19:
3426 case RTL_GIGA_MAC_VER_20:
3427 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
3428 case RTL_GIGA_MAC_VER_22:
3429 case RTL_GIGA_MAC_VER_23:
3430 case RTL_GIGA_MAC_VER_24:
3431 case RTL_GIGA_MAC_VER_25:
3432 case RTL_GIGA_MAC_VER_26:
3433 ops->disable = r8168c_hw_jumbo_disable;
3434 ops->enable = r8168c_hw_jumbo_enable;
3436 case RTL_GIGA_MAC_VER_27:
3437 case RTL_GIGA_MAC_VER_28:
3438 ops->disable = r8168dp_hw_jumbo_disable;
3439 ops->enable = r8168dp_hw_jumbo_enable;
3441 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
3442 case RTL_GIGA_MAC_VER_32:
3443 case RTL_GIGA_MAC_VER_33:
3444 ops->disable = r8168e_hw_jumbo_disable;
3445 ops->enable = r8168e_hw_jumbo_enable;
3449 * No action needed for jumbo frames with 8169.
3450 * No jumbo for 810x at all.
3453 ops->disable = NULL;
3459 static void rtl_hw_reset(struct rtl8169_private *tp)
3461 void __iomem *ioaddr = tp->mmio_addr;
3464 /* Soft reset the chip. */
3465 RTL_W8(ChipCmd, CmdReset);
3467 /* Check that the chip has finished the reset. */
3468 for (i = 0; i < 100; i++) {
3469 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3471 msleep_interruptible(1);
3475 static int __devinit
3476 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3478 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
3479 const unsigned int region = cfg->region;
3480 struct rtl8169_private *tp;
3481 struct mii_if_info *mii;
3482 struct net_device *dev;
3483 void __iomem *ioaddr;
3487 if (netif_msg_drv(&debug)) {
3488 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
3489 MODULENAME, RTL8169_VERSION);
3492 dev = alloc_etherdev(sizeof (*tp));
3494 if (netif_msg_drv(&debug))
3495 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
3500 SET_NETDEV_DEV(dev, &pdev->dev);
3501 dev->netdev_ops = &rtl8169_netdev_ops;
3502 tp = netdev_priv(dev);
3505 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
3509 mii->mdio_read = rtl_mdio_read;
3510 mii->mdio_write = rtl_mdio_write;
3511 mii->phy_id_mask = 0x1f;
3512 mii->reg_num_mask = 0x1f;
3513 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3515 /* disable ASPM completely as that cause random device stop working
3516 * problems as well as full system hangs for some PCIe devices users */
3517 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3518 PCIE_LINK_STATE_CLKPM);
3520 /* enable device (incl. PCI PM wakeup and hotplug setup) */
3521 rc = pci_enable_device(pdev);
3523 netif_err(tp, probe, dev, "enable failure\n");
3524 goto err_out_free_dev_1;
3527 if (pci_set_mwi(pdev) < 0)
3528 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
3530 /* make sure PCI base addr 1 is MMIO */
3531 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
3532 netif_err(tp, probe, dev,
3533 "region #%d not an MMIO resource, aborting\n",
3539 /* check for weird/broken PCI region reporting */
3540 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
3541 netif_err(tp, probe, dev,
3542 "Invalid PCI region size(s), aborting\n");
3547 rc = pci_request_regions(pdev, MODULENAME);
3549 netif_err(tp, probe, dev, "could not request regions\n");
3553 tp->cp_cmd = RxChkSum;
3555 if ((sizeof(dma_addr_t) > 4) &&
3556 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
3557 tp->cp_cmd |= PCIDAC;
3558 dev->features |= NETIF_F_HIGHDMA;
3560 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3562 netif_err(tp, probe, dev, "DMA configuration failed\n");
3563 goto err_out_free_res_3;
3567 /* ioremap MMIO region */
3568 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
3570 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
3572 goto err_out_free_res_3;
3574 tp->mmio_addr = ioaddr;
3576 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3578 netif_info(tp, probe, dev, "no PCI Express capability\n");
3580 RTL_W16(IntrMask, 0x0000);
3584 RTL_W16(IntrStatus, 0xffff);
3586 pci_set_master(pdev);
3588 /* Identify chip attached to board */
3589 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
3592 * Pretend we are using VLANs; This bypasses a nasty bug where
3593 * Interrupts stop flowing on high load on 8110SCd controllers.
3595 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3596 tp->cp_cmd |= RxVlan;
3598 rtl_init_mdio_ops(tp);
3599 rtl_init_pll_power_ops(tp);
3600 rtl_init_jumbo_ops(tp);
3602 rtl8169_print_mac_version(tp);
3604 chipset = tp->mac_version;
3605 tp->txd_version = rtl_chip_infos[chipset].txd_version;
3607 RTL_W8(Cfg9346, Cfg9346_Unlock);
3608 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3609 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
3610 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3611 tp->features |= RTL_FEATURE_WOL;
3612 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3613 tp->features |= RTL_FEATURE_WOL;
3614 tp->features |= rtl_try_msi(tp, cfg);
3615 RTL_W8(Cfg9346, Cfg9346_Lock);
3617 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3618 (RTL_R8(PHYstatus) & TBI_Enable)) {
3619 tp->set_speed = rtl8169_set_speed_tbi;
3620 tp->get_settings = rtl8169_gset_tbi;
3621 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3622 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3623 tp->link_ok = rtl8169_tbi_link_ok;
3624 tp->do_ioctl = rtl_tbi_ioctl;
3626 tp->set_speed = rtl8169_set_speed_xmii;
3627 tp->get_settings = rtl8169_gset_xmii;
3628 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3629 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3630 tp->link_ok = rtl8169_xmii_link_ok;
3631 tp->do_ioctl = rtl_xmii_ioctl;
3634 spin_lock_init(&tp->lock);
3636 /* Get MAC address */
3637 for (i = 0; i < MAC_ADDR_LEN; i++)
3638 dev->dev_addr[i] = RTL_R8(MAC0 + i);
3639 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3641 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
3642 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3643 dev->irq = pdev->irq;
3644 dev->base_addr = (unsigned long) ioaddr;
3646 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
3648 /* don't enable SG, IP_CSUM and TSO by default - it might not work
3649 * properly for all devices */
3650 dev->features |= NETIF_F_RXCSUM |
3651 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3653 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3654 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3655 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3658 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3659 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
3660 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
3662 tp->intr_mask = 0xffff;
3663 tp->hw_start = cfg->hw_start;
3664 tp->intr_event = cfg->intr_event;
3665 tp->napi_event = cfg->napi_event;
3667 tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
3668 ~(RxBOVF | RxFOVF) : ~0;
3670 init_timer(&tp->timer);
3671 tp->timer.data = (unsigned long) dev;
3672 tp->timer.function = rtl8169_phy_timer;
3674 tp->fw = RTL_FIRMWARE_UNKNOWN;
3676 rc = register_netdev(dev);
3680 pci_set_drvdata(pdev, dev);
3682 netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
3683 rtl_chip_infos[chipset].name, dev->base_addr, dev->dev_addr,
3684 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
3685 if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
3686 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
3687 "tx checksumming: %s]\n",
3688 rtl_chip_infos[chipset].jumbo_max,
3689 rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
3692 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3693 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3694 tp->mac_version == RTL_GIGA_MAC_VER_31) {
3695 rtl8168_driver_start(tp);
3698 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
3700 if (pci_dev_run_wake(pdev))
3701 pm_runtime_put_noidle(&pdev->dev);
3703 netif_carrier_off(dev);
3709 rtl_disable_msi(pdev, tp);
3712 pci_release_regions(pdev);
3714 pci_clear_mwi(pdev);
3715 pci_disable_device(pdev);
3721 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
3723 struct net_device *dev = pci_get_drvdata(pdev);
3724 struct rtl8169_private *tp = netdev_priv(dev);
3726 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3727 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3728 tp->mac_version == RTL_GIGA_MAC_VER_31) {
3729 rtl8168_driver_stop(tp);
3732 cancel_delayed_work_sync(&tp->task);
3734 unregister_netdev(dev);
3736 rtl_release_firmware(tp);
3738 if (pci_dev_run_wake(pdev))
3739 pm_runtime_get_noresume(&pdev->dev);
3741 /* restore original MAC address */
3742 rtl_rar_set(tp, dev->perm_addr);
3744 rtl_disable_msi(pdev, tp);
3745 rtl8169_release_board(pdev, dev, tp->mmio_addr);
3746 pci_set_drvdata(pdev, NULL);
3749 static void rtl_request_firmware(struct rtl8169_private *tp)
3751 /* Return early if the firmware is already loaded / cached. */
3752 if (IS_ERR(tp->fw)) {
3755 name = rtl_lookup_firmware_name(tp);
3759 rc = request_firmware(&tp->fw, name, &tp->pci_dev->dev);
3763 netif_warn(tp, ifup, tp->dev, "unable to load "
3764 "firmware patch %s (%d)\n", name, rc);
3770 static int rtl8169_open(struct net_device *dev)
3772 struct rtl8169_private *tp = netdev_priv(dev);
3773 void __iomem *ioaddr = tp->mmio_addr;
3774 struct pci_dev *pdev = tp->pci_dev;
3775 int retval = -ENOMEM;
3777 pm_runtime_get_sync(&pdev->dev);
3780 * Rx and Tx desscriptors needs 256 bytes alignment.
3781 * dma_alloc_coherent provides more.
3783 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
3784 &tp->TxPhyAddr, GFP_KERNEL);
3785 if (!tp->TxDescArray)
3786 goto err_pm_runtime_put;
3788 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
3789 &tp->RxPhyAddr, GFP_KERNEL);
3790 if (!tp->RxDescArray)
3793 retval = rtl8169_init_ring(dev);
3797 INIT_DELAYED_WORK(&tp->task, NULL);
3801 rtl_request_firmware(tp);
3803 retval = request_irq(dev->irq, rtl8169_interrupt,
3804 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
3807 goto err_release_fw_2;
3809 napi_enable(&tp->napi);
3811 rtl8169_init_phy(dev, tp);
3813 rtl8169_set_features(dev, dev->features);
3815 rtl_pll_power_up(tp);
3819 tp->saved_wolopts = 0;
3820 pm_runtime_put_noidle(&pdev->dev);
3822 rtl8169_check_link_status(dev, tp, ioaddr);
3827 rtl_release_firmware(tp);
3828 rtl8169_rx_clear(tp);
3830 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
3832 tp->RxDescArray = NULL;
3834 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
3836 tp->TxDescArray = NULL;
3838 pm_runtime_put_noidle(&pdev->dev);
3842 static void rtl8169_hw_reset(struct rtl8169_private *tp)
3844 void __iomem *ioaddr = tp->mmio_addr;
3846 /* Disable interrupts */
3847 rtl8169_irq_mask_and_ack(tp);
3849 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3850 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3851 tp->mac_version == RTL_GIGA_MAC_VER_31) {
3852 while (RTL_R8(TxPoll) & NPQ)
3857 /* Reset the chipset */
3858 RTL_W8(ChipCmd, CmdReset);
3864 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
3866 void __iomem *ioaddr = tp->mmio_addr;
3867 u32 cfg = rtl8169_rx_config;
3869 cfg |= (RTL_R32(RxConfig) & RTL_RX_CONFIG_MASK);
3870 RTL_W32(RxConfig, cfg);
3872 /* Set DMA burst size and Interframe Gap Time */
3873 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3874 (InterFrameGap << TxInterFrameGapShift));
3877 static void rtl_hw_start(struct net_device *dev)
3879 struct rtl8169_private *tp = netdev_priv(dev);
3885 netif_start_queue(dev);
3888 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3889 void __iomem *ioaddr)
3892 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3893 * register to be written before TxDescAddrLow to work.
3894 * Switching from MMIO to I/O access fixes the issue as well.
3896 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
3897 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
3898 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
3899 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
3902 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
3906 cmd = RTL_R16(CPlusCmd);
3907 RTL_W16(CPlusCmd, cmd);
3911 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
3913 /* Low hurts. Let's disable the filtering. */
3914 RTL_W16(RxMaxSize, rx_buf_sz + 1);
3917 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
3919 static const struct rtl_cfg2_info {
3924 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
3925 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
3926 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
3927 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3929 const struct rtl_cfg2_info *p = cfg2_info;
3933 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
3934 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
3935 if ((p->mac_version == mac_version) && (p->clk == clk)) {
3936 RTL_W32(0x7c, p->val);
3942 static void rtl_hw_start_8169(struct net_device *dev)
3944 struct rtl8169_private *tp = netdev_priv(dev);
3945 void __iomem *ioaddr = tp->mmio_addr;
3946 struct pci_dev *pdev = tp->pci_dev;
3948 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
3949 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
3950 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
3953 RTL_W8(Cfg9346, Cfg9346_Unlock);
3954 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
3955 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3956 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
3957 tp->mac_version == RTL_GIGA_MAC_VER_04)
3958 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3960 RTL_W8(EarlyTxThres, NoEarlyTx);
3962 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
3964 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
3965 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3966 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
3967 tp->mac_version == RTL_GIGA_MAC_VER_04)
3968 rtl_set_rx_tx_config_registers(tp);
3970 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3972 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3973 tp->mac_version == RTL_GIGA_MAC_VER_03) {
3974 dprintk("Set MAC Reg C+CR Offset 0xE0. "
3975 "Bit-3 and bit-14 MUST be 1\n");
3976 tp->cp_cmd |= (1 << 14);
3979 RTL_W16(CPlusCmd, tp->cp_cmd);
3981 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
3984 * Undocumented corner. Supposedly:
3985 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3987 RTL_W16(IntrMitigate, 0x0000);
3989 rtl_set_rx_tx_desc_registers(tp, ioaddr);
3991 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
3992 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
3993 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
3994 tp->mac_version != RTL_GIGA_MAC_VER_04) {
3995 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3996 rtl_set_rx_tx_config_registers(tp);
3999 RTL_W8(Cfg9346, Cfg9346_Lock);
4001 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4004 RTL_W32(RxMissed, 0);
4006 rtl_set_rx_mode(dev);
4008 /* no early-rx interrupts */
4009 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4011 /* Enable all known interrupts by setting the interrupt mask. */
4012 RTL_W16(IntrMask, tp->intr_event);
4015 static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
4019 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
4020 rtl_csi_write(ioaddr, 0x070c, csi | bits);
4023 static void rtl_csi_access_enable_1(void __iomem *ioaddr)
4025 rtl_csi_access_enable(ioaddr, 0x17000000);
4028 static void rtl_csi_access_enable_2(void __iomem *ioaddr)
4030 rtl_csi_access_enable(ioaddr, 0x27000000);
4034 unsigned int offset;
4039 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
4044 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
4045 rtl_ephy_write(ioaddr, e->offset, w);
4050 static void rtl_disable_clock_request(struct pci_dev *pdev)
4052 struct net_device *dev = pci_get_drvdata(pdev);
4053 struct rtl8169_private *tp = netdev_priv(dev);
4054 int cap = tp->pcie_cap;
4059 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4060 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
4061 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4065 static void rtl_enable_clock_request(struct pci_dev *pdev)
4067 struct net_device *dev = pci_get_drvdata(pdev);
4068 struct rtl8169_private *tp = netdev_priv(dev);
4069 int cap = tp->pcie_cap;
4074 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4075 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
4076 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4080 #define R8168_CPCMD_QUIRK_MASK (\
4091 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
4093 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4095 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4097 rtl_tx_performance_tweak(pdev,
4098 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4101 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
4103 rtl_hw_start_8168bb(ioaddr, pdev);
4105 RTL_W8(MaxTxPacketSize, TxPacketMax);
4107 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4110 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
4112 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4114 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4116 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4118 rtl_disable_clock_request(pdev);
4120 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4123 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
4125 static const struct ephy_info e_info_8168cp[] = {
4126 { 0x01, 0, 0x0001 },
4127 { 0x02, 0x0800, 0x1000 },
4128 { 0x03, 0, 0x0042 },
4129 { 0x06, 0x0080, 0x0000 },
4133 rtl_csi_access_enable_2(ioaddr);
4135 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4137 __rtl_hw_start_8168cp(ioaddr, pdev);
4140 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
4142 rtl_csi_access_enable_2(ioaddr);
4144 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4146 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4148 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4151 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
4153 rtl_csi_access_enable_2(ioaddr);
4155 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4158 RTL_W8(DBG_REG, 0x20);
4160 RTL_W8(MaxTxPacketSize, TxPacketMax);
4162 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4164 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4167 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
4169 static const struct ephy_info e_info_8168c_1[] = {
4170 { 0x02, 0x0800, 0x1000 },
4171 { 0x03, 0, 0x0002 },
4172 { 0x06, 0x0080, 0x0000 }
4175 rtl_csi_access_enable_2(ioaddr);
4177 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4179 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4181 __rtl_hw_start_8168cp(ioaddr, pdev);
4184 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
4186 static const struct ephy_info e_info_8168c_2[] = {
4187 { 0x01, 0, 0x0001 },
4188 { 0x03, 0x0400, 0x0220 }
4191 rtl_csi_access_enable_2(ioaddr);
4193 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4195 __rtl_hw_start_8168cp(ioaddr, pdev);
4198 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
4200 rtl_hw_start_8168c_2(ioaddr, pdev);
4203 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
4205 rtl_csi_access_enable_2(ioaddr);
4207 __rtl_hw_start_8168cp(ioaddr, pdev);
4210 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
4212 rtl_csi_access_enable_2(ioaddr);
4214 rtl_disable_clock_request(pdev);
4216 RTL_W8(MaxTxPacketSize, TxPacketMax);
4218 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4220 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4223 static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev)
4225 rtl_csi_access_enable_1(ioaddr);
4227 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4229 RTL_W8(MaxTxPacketSize, TxPacketMax);
4231 rtl_disable_clock_request(pdev);
4234 static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
4236 static const struct ephy_info e_info_8168d_4[] = {
4238 { 0x19, 0x20, 0x50 },
4243 rtl_csi_access_enable_1(ioaddr);
4245 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4247 RTL_W8(MaxTxPacketSize, TxPacketMax);
4249 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4250 const struct ephy_info *e = e_info_8168d_4 + i;
4253 w = rtl_ephy_read(ioaddr, e->offset);
4254 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
4257 rtl_enable_clock_request(pdev);
4260 static void rtl_hw_start_8168e(void __iomem *ioaddr, struct pci_dev *pdev)
4262 static const struct ephy_info e_info_8168e[] = {
4263 { 0x00, 0x0200, 0x0100 },
4264 { 0x00, 0x0000, 0x0004 },
4265 { 0x06, 0x0002, 0x0001 },
4266 { 0x06, 0x0000, 0x0030 },
4267 { 0x07, 0x0000, 0x2000 },
4268 { 0x00, 0x0000, 0x0020 },
4269 { 0x03, 0x5800, 0x2000 },
4270 { 0x03, 0x0000, 0x0001 },
4271 { 0x01, 0x0800, 0x1000 },
4272 { 0x07, 0x0000, 0x4000 },
4273 { 0x1e, 0x0000, 0x2000 },
4274 { 0x19, 0xffff, 0xfe6c },
4275 { 0x0a, 0x0000, 0x0040 }
4278 rtl_csi_access_enable_2(ioaddr);
4280 rtl_ephy_init(ioaddr, e_info_8168e, ARRAY_SIZE(e_info_8168e));
4282 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4284 RTL_W8(MaxTxPacketSize, TxPacketMax);
4286 rtl_disable_clock_request(pdev);
4288 /* Reset tx FIFO pointer */
4289 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
4290 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
4292 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4295 static void rtl_hw_start_8168(struct net_device *dev)
4297 struct rtl8169_private *tp = netdev_priv(dev);
4298 void __iomem *ioaddr = tp->mmio_addr;
4299 struct pci_dev *pdev = tp->pci_dev;
4301 RTL_W8(Cfg9346, Cfg9346_Unlock);
4303 RTL_W8(MaxTxPacketSize, TxPacketMax);
4305 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4307 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
4309 RTL_W16(CPlusCmd, tp->cp_cmd);
4311 RTL_W16(IntrMitigate, 0x5151);
4313 /* Work around for RxFIFO overflow. */
4314 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
4315 tp->intr_event |= RxFIFOOver | PCSTimeout;
4316 tp->intr_event &= ~RxOverflow;
4319 rtl_set_rx_tx_desc_registers(tp, ioaddr);
4321 rtl_set_rx_mode(dev);
4323 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4324 (InterFrameGap << TxInterFrameGapShift));
4328 switch (tp->mac_version) {
4329 case RTL_GIGA_MAC_VER_11:
4330 rtl_hw_start_8168bb(ioaddr, pdev);
4333 case RTL_GIGA_MAC_VER_12:
4334 case RTL_GIGA_MAC_VER_17:
4335 rtl_hw_start_8168bef(ioaddr, pdev);
4338 case RTL_GIGA_MAC_VER_18:
4339 rtl_hw_start_8168cp_1(ioaddr, pdev);
4342 case RTL_GIGA_MAC_VER_19:
4343 rtl_hw_start_8168c_1(ioaddr, pdev);
4346 case RTL_GIGA_MAC_VER_20:
4347 rtl_hw_start_8168c_2(ioaddr, pdev);
4350 case RTL_GIGA_MAC_VER_21:
4351 rtl_hw_start_8168c_3(ioaddr, pdev);
4354 case RTL_GIGA_MAC_VER_22:
4355 rtl_hw_start_8168c_4(ioaddr, pdev);
4358 case RTL_GIGA_MAC_VER_23:
4359 rtl_hw_start_8168cp_2(ioaddr, pdev);
4362 case RTL_GIGA_MAC_VER_24:
4363 rtl_hw_start_8168cp_3(ioaddr, pdev);
4366 case RTL_GIGA_MAC_VER_25:
4367 case RTL_GIGA_MAC_VER_26:
4368 case RTL_GIGA_MAC_VER_27:
4369 rtl_hw_start_8168d(ioaddr, pdev);
4372 case RTL_GIGA_MAC_VER_28:
4373 rtl_hw_start_8168d_4(ioaddr, pdev);
4376 case RTL_GIGA_MAC_VER_31:
4377 rtl_hw_start_8168dp(ioaddr, pdev);
4380 case RTL_GIGA_MAC_VER_32:
4381 case RTL_GIGA_MAC_VER_33:
4382 rtl_hw_start_8168e(ioaddr, pdev);
4386 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
4387 dev->name, tp->mac_version);
4391 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4393 RTL_W8(Cfg9346, Cfg9346_Lock);
4395 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4397 RTL_W16(IntrMask, tp->intr_event);
4400 #define R810X_CPCMD_QUIRK_MASK (\
4411 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4413 static const struct ephy_info e_info_8102e_1[] = {
4414 { 0x01, 0, 0x6e65 },
4415 { 0x02, 0, 0x091f },
4416 { 0x03, 0, 0xc2f9 },
4417 { 0x06, 0, 0xafb5 },
4418 { 0x07, 0, 0x0e00 },
4419 { 0x19, 0, 0xec80 },
4420 { 0x01, 0, 0x2e65 },
4425 rtl_csi_access_enable_2(ioaddr);
4427 RTL_W8(DBG_REG, FIX_NAK_1);
4429 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4432 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
4433 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4435 cfg1 = RTL_R8(Config1);
4436 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
4437 RTL_W8(Config1, cfg1 & ~LEDS0);
4439 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
4442 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4444 rtl_csi_access_enable_2(ioaddr);
4446 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4448 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
4449 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4452 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
4454 rtl_hw_start_8102e_2(ioaddr, pdev);
4456 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
4459 static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4461 static const struct ephy_info e_info_8105e_1[] = {
4462 { 0x07, 0, 0x4000 },
4463 { 0x19, 0, 0x0200 },
4464 { 0x19, 0, 0x0020 },
4465 { 0x1e, 0, 0x2000 },
4466 { 0x03, 0, 0x0001 },
4467 { 0x19, 0, 0x0100 },
4468 { 0x19, 0, 0x0004 },
4472 /* Force LAN exit from ASPM if Rx/Tx are not idle */
4473 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
4475 /* Disable Early Tally Counter */
4476 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
4478 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4479 RTL_W8(DLLPR, RTL_R8(DLLPR) | PM_SWITCH);
4481 rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
4484 static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4486 rtl_hw_start_8105e_1(ioaddr, pdev);
4487 rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
4490 static void rtl_hw_start_8101(struct net_device *dev)
4492 struct rtl8169_private *tp = netdev_priv(dev);
4493 void __iomem *ioaddr = tp->mmio_addr;
4494 struct pci_dev *pdev = tp->pci_dev;
4496 if (tp->mac_version >= RTL_GIGA_MAC_VER_30) {
4497 tp->intr_event &= ~RxFIFOOver;
4498 tp->napi_event &= ~RxFIFOOver;
4501 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
4502 tp->mac_version == RTL_GIGA_MAC_VER_16) {
4503 int cap = tp->pcie_cap;
4506 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
4507 PCI_EXP_DEVCTL_NOSNOOP_EN);
4511 RTL_W8(Cfg9346, Cfg9346_Unlock);
4513 switch (tp->mac_version) {
4514 case RTL_GIGA_MAC_VER_07:
4515 rtl_hw_start_8102e_1(ioaddr, pdev);
4518 case RTL_GIGA_MAC_VER_08:
4519 rtl_hw_start_8102e_3(ioaddr, pdev);
4522 case RTL_GIGA_MAC_VER_09:
4523 rtl_hw_start_8102e_2(ioaddr, pdev);
4526 case RTL_GIGA_MAC_VER_29:
4527 rtl_hw_start_8105e_1(ioaddr, pdev);
4529 case RTL_GIGA_MAC_VER_30:
4530 rtl_hw_start_8105e_2(ioaddr, pdev);
4534 RTL_W8(Cfg9346, Cfg9346_Lock);
4536 RTL_W8(MaxTxPacketSize, TxPacketMax);
4538 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4540 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
4541 RTL_W16(CPlusCmd, tp->cp_cmd);
4543 RTL_W16(IntrMitigate, 0x0000);
4545 rtl_set_rx_tx_desc_registers(tp, ioaddr);
4547 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4548 rtl_set_rx_tx_config_registers(tp);
4552 rtl_set_rx_mode(dev);
4554 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
4556 RTL_W16(IntrMask, tp->intr_event);
4559 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
4561 struct rtl8169_private *tp = netdev_priv(dev);
4563 if (new_mtu < ETH_ZLEN ||
4564 new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
4567 if (new_mtu > ETH_DATA_LEN)
4568 rtl_hw_jumbo_enable(tp);
4570 rtl_hw_jumbo_disable(tp);
4573 netdev_update_features(dev);
4578 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
4580 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
4581 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
4584 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
4585 void **data_buff, struct RxDesc *desc)
4587 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
4592 rtl8169_make_unusable_by_asic(desc);
4595 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
4597 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
4599 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
4602 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
4605 desc->addr = cpu_to_le64(mapping);
4607 rtl8169_mark_to_asic(desc, rx_buf_sz);
4610 static inline void *rtl8169_align(void *data)
4612 return (void *)ALIGN((long)data, 16);
4615 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
4616 struct RxDesc *desc)
4620 struct device *d = &tp->pci_dev->dev;
4621 struct net_device *dev = tp->dev;
4622 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
4624 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
4628 if (rtl8169_align(data) != data) {
4630 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
4635 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
4637 if (unlikely(dma_mapping_error(d, mapping))) {
4638 if (net_ratelimit())
4639 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
4643 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
4651 static void rtl8169_rx_clear(struct rtl8169_private *tp)
4655 for (i = 0; i < NUM_RX_DESC; i++) {
4656 if (tp->Rx_databuff[i]) {
4657 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
4658 tp->RxDescArray + i);
4663 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
4665 desc->opts1 |= cpu_to_le32(RingEnd);
4668 static int rtl8169_rx_fill(struct rtl8169_private *tp)
4672 for (i = 0; i < NUM_RX_DESC; i++) {
4675 if (tp->Rx_databuff[i])
4678 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
4680 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
4683 tp->Rx_databuff[i] = data;
4686 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4690 rtl8169_rx_clear(tp);
4694 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4696 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
4699 static int rtl8169_init_ring(struct net_device *dev)
4701 struct rtl8169_private *tp = netdev_priv(dev);
4703 rtl8169_init_ring_indexes(tp);
4705 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
4706 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
4708 return rtl8169_rx_fill(tp);
4711 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
4712 struct TxDesc *desc)
4714 unsigned int len = tx_skb->len;
4716 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
4724 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4729 for (i = 0; i < n; i++) {
4730 unsigned int entry = (start + i) % NUM_TX_DESC;
4731 struct ring_info *tx_skb = tp->tx_skb + entry;
4732 unsigned int len = tx_skb->len;
4735 struct sk_buff *skb = tx_skb->skb;
4737 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4738 tp->TxDescArray + entry);
4740 tp->dev->stats.tx_dropped++;
4748 static void rtl8169_tx_clear(struct rtl8169_private *tp)
4750 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
4751 tp->cur_tx = tp->dirty_tx = 0;
4754 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
4756 struct rtl8169_private *tp = netdev_priv(dev);
4758 PREPARE_DELAYED_WORK(&tp->task, task);
4759 schedule_delayed_work(&tp->task, 4);
4762 static void rtl8169_wait_for_quiescence(struct net_device *dev)
4764 struct rtl8169_private *tp = netdev_priv(dev);
4765 void __iomem *ioaddr = tp->mmio_addr;
4767 synchronize_irq(dev->irq);
4769 /* Wait for any pending NAPI task to complete */
4770 napi_disable(&tp->napi);
4772 rtl8169_irq_mask_and_ack(tp);
4774 tp->intr_mask = 0xffff;
4775 RTL_W16(IntrMask, tp->intr_event);
4776 napi_enable(&tp->napi);
4779 static void rtl8169_reinit_task(struct work_struct *work)
4781 struct rtl8169_private *tp =
4782 container_of(work, struct rtl8169_private, task.work);
4783 struct net_device *dev = tp->dev;
4788 if (!netif_running(dev))
4791 rtl8169_wait_for_quiescence(dev);
4794 ret = rtl8169_open(dev);
4795 if (unlikely(ret < 0)) {
4796 if (net_ratelimit())
4797 netif_err(tp, drv, dev,
4798 "reinit failure (status = %d). Rescheduling\n",
4800 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4807 static void rtl8169_reset_task(struct work_struct *work)
4809 struct rtl8169_private *tp =
4810 container_of(work, struct rtl8169_private, task.work);
4811 struct net_device *dev = tp->dev;
4816 if (!netif_running(dev))
4819 rtl8169_wait_for_quiescence(dev);
4821 for (i = 0; i < NUM_RX_DESC; i++)
4822 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
4824 rtl8169_tx_clear(tp);
4826 rtl8169_init_ring_indexes(tp);
4828 netif_wake_queue(dev);
4829 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
4835 static void rtl8169_tx_timeout(struct net_device *dev)
4837 struct rtl8169_private *tp = netdev_priv(dev);
4839 rtl8169_hw_reset(tp);
4841 /* Let's wait a bit while any (async) irq lands on */
4842 rtl8169_schedule_work(dev, rtl8169_reset_task);
4845 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4848 struct skb_shared_info *info = skb_shinfo(skb);
4849 unsigned int cur_frag, entry;
4850 struct TxDesc * uninitialized_var(txd);
4851 struct device *d = &tp->pci_dev->dev;
4854 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4855 skb_frag_t *frag = info->frags + cur_frag;
4860 entry = (entry + 1) % NUM_TX_DESC;
4862 txd = tp->TxDescArray + entry;
4864 addr = ((void *) page_address(frag->page)) + frag->page_offset;
4865 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
4866 if (unlikely(dma_mapping_error(d, mapping))) {
4867 if (net_ratelimit())
4868 netif_err(tp, drv, tp->dev,
4869 "Failed to map TX fragments DMA!\n");
4873 /* Anti gcc 2.95.3 bugware (sic) */
4874 status = opts[0] | len |
4875 (RingEnd * !((entry + 1) % NUM_TX_DESC));
4877 txd->opts1 = cpu_to_le32(status);
4878 txd->opts2 = cpu_to_le32(opts[1]);
4879 txd->addr = cpu_to_le64(mapping);
4881 tp->tx_skb[entry].len = len;
4885 tp->tx_skb[entry].skb = skb;
4886 txd->opts1 |= cpu_to_le32(LastFrag);
4892 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4896 static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
4897 struct sk_buff *skb, u32 *opts)
4899 const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
4900 u32 mss = skb_shinfo(skb)->gso_size;
4901 int offset = info->opts_offset;
4905 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
4906 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4907 const struct iphdr *ip = ip_hdr(skb);
4909 if (ip->protocol == IPPROTO_TCP)
4910 opts[offset] |= info->checksum.tcp;
4911 else if (ip->protocol == IPPROTO_UDP)
4912 opts[offset] |= info->checksum.udp;
4918 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4919 struct net_device *dev)
4921 struct rtl8169_private *tp = netdev_priv(dev);
4922 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
4923 struct TxDesc *txd = tp->TxDescArray + entry;
4924 void __iomem *ioaddr = tp->mmio_addr;
4925 struct device *d = &tp->pci_dev->dev;
4931 if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
4932 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
4936 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
4939 len = skb_headlen(skb);
4940 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
4941 if (unlikely(dma_mapping_error(d, mapping))) {
4942 if (net_ratelimit())
4943 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
4947 tp->tx_skb[entry].len = len;
4948 txd->addr = cpu_to_le64(mapping);
4950 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
4953 rtl8169_tso_csum(tp, skb, opts);
4955 frags = rtl8169_xmit_frags(tp, skb, opts);
4959 opts[0] |= FirstFrag;
4961 opts[0] |= FirstFrag | LastFrag;
4962 tp->tx_skb[entry].skb = skb;
4965 txd->opts2 = cpu_to_le32(opts[1]);
4969 /* Anti gcc 2.95.3 bugware (sic) */
4970 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4971 txd->opts1 = cpu_to_le32(status);
4973 tp->cur_tx += frags + 1;
4977 RTL_W8(TxPoll, NPQ);
4979 if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
4980 netif_stop_queue(dev);
4982 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
4983 netif_wake_queue(dev);
4986 return NETDEV_TX_OK;
4989 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
4992 dev->stats.tx_dropped++;
4993 return NETDEV_TX_OK;
4996 netif_stop_queue(dev);
4997 dev->stats.tx_dropped++;
4998 return NETDEV_TX_BUSY;
5001 static void rtl8169_pcierr_interrupt(struct net_device *dev)
5003 struct rtl8169_private *tp = netdev_priv(dev);
5004 struct pci_dev *pdev = tp->pci_dev;
5005 u16 pci_status, pci_cmd;
5007 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5008 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5010 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5011 pci_cmd, pci_status);
5014 * The recovery sequence below admits a very elaborated explanation:
5015 * - it seems to work;
5016 * - I did not see what else could be done;
5017 * - it makes iop3xx happy.
5019 * Feel free to adjust to your needs.
5021 if (pdev->broken_parity_status)
5022 pci_cmd &= ~PCI_COMMAND_PARITY;
5024 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5026 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
5028 pci_write_config_word(pdev, PCI_STATUS,
5029 pci_status & (PCI_STATUS_DETECTED_PARITY |
5030 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5031 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5033 /* The infamous DAC f*ckup only happens at boot time */
5034 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
5035 void __iomem *ioaddr = tp->mmio_addr;
5037 netif_info(tp, intr, dev, "disabling PCI DAC\n");
5038 tp->cp_cmd &= ~PCIDAC;
5039 RTL_W16(CPlusCmd, tp->cp_cmd);
5040 dev->features &= ~NETIF_F_HIGHDMA;
5043 rtl8169_hw_reset(tp);
5045 rtl8169_schedule_work(dev, rtl8169_reinit_task);
5048 static void rtl8169_tx_interrupt(struct net_device *dev,
5049 struct rtl8169_private *tp,
5050 void __iomem *ioaddr)
5052 unsigned int dirty_tx, tx_left;
5054 dirty_tx = tp->dirty_tx;
5056 tx_left = tp->cur_tx - dirty_tx;
5058 while (tx_left > 0) {
5059 unsigned int entry = dirty_tx % NUM_TX_DESC;
5060 struct ring_info *tx_skb = tp->tx_skb + entry;
5064 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5065 if (status & DescOwn)
5068 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5069 tp->TxDescArray + entry);
5070 if (status & LastFrag) {
5071 dev->stats.tx_packets++;
5072 dev->stats.tx_bytes += tx_skb->skb->len;
5073 dev_kfree_skb(tx_skb->skb);
5080 if (tp->dirty_tx != dirty_tx) {
5081 tp->dirty_tx = dirty_tx;
5083 if (netif_queue_stopped(dev) &&
5084 TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
5085 netif_wake_queue(dev);
5088 * 8168 hack: TxPoll requests are lost when the Tx packets are
5089 * too close. Let's kick an extra TxPoll request when a burst
5090 * of start_xmit activity is detected (if it is not detected,
5091 * it is slow enough). -- FR
5093 if (tp->cur_tx != dirty_tx)
5094 RTL_W8(TxPoll, NPQ);
5098 static inline int rtl8169_fragmented_frame(u32 status)
5100 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
5103 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
5105 u32 status = opts1 & RxProtoMask;
5107 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
5108 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
5109 skb->ip_summed = CHECKSUM_UNNECESSARY;
5111 skb_checksum_none_assert(skb);
5114 static struct sk_buff *rtl8169_try_rx_copy(void *data,
5115 struct rtl8169_private *tp,
5119 struct sk_buff *skb;
5120 struct device *d = &tp->pci_dev->dev;
5122 data = rtl8169_align(data);
5123 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
5125 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
5127 memcpy(skb->data, data, pkt_size);
5128 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
5133 static int rtl8169_rx_interrupt(struct net_device *dev,
5134 struct rtl8169_private *tp,
5135 void __iomem *ioaddr, u32 budget)
5137 unsigned int cur_rx, rx_left;
5140 cur_rx = tp->cur_rx;
5141 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
5142 rx_left = min(rx_left, budget);
5144 for (; rx_left > 0; rx_left--, cur_rx++) {
5145 unsigned int entry = cur_rx % NUM_RX_DESC;
5146 struct RxDesc *desc = tp->RxDescArray + entry;
5150 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
5152 if (status & DescOwn)
5154 if (unlikely(status & RxRES)) {
5155 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
5157 dev->stats.rx_errors++;
5158 if (status & (RxRWT | RxRUNT))
5159 dev->stats.rx_length_errors++;
5161 dev->stats.rx_crc_errors++;
5162 if (status & RxFOVF) {
5163 rtl8169_schedule_work(dev, rtl8169_reset_task);
5164 dev->stats.rx_fifo_errors++;
5166 rtl8169_mark_to_asic(desc, rx_buf_sz);
5168 struct sk_buff *skb;
5169 dma_addr_t addr = le64_to_cpu(desc->addr);
5170 int pkt_size = (status & 0x00003fff) - 4;
5173 * The driver does not support incoming fragmented
5174 * frames. They are seen as a symptom of over-mtu
5177 if (unlikely(rtl8169_fragmented_frame(status))) {
5178 dev->stats.rx_dropped++;
5179 dev->stats.rx_length_errors++;
5180 rtl8169_mark_to_asic(desc, rx_buf_sz);
5184 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
5185 tp, pkt_size, addr);
5186 rtl8169_mark_to_asic(desc, rx_buf_sz);
5188 dev->stats.rx_dropped++;
5192 rtl8169_rx_csum(skb, status);
5193 skb_put(skb, pkt_size);
5194 skb->protocol = eth_type_trans(skb, dev);
5196 rtl8169_rx_vlan_tag(desc, skb);
5198 napi_gro_receive(&tp->napi, skb);
5200 dev->stats.rx_bytes += pkt_size;
5201 dev->stats.rx_packets++;
5204 /* Work around for AMD plateform. */
5205 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
5206 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
5212 count = cur_rx - tp->cur_rx;
5213 tp->cur_rx = cur_rx;
5215 tp->dirty_rx += count;
5220 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
5222 struct net_device *dev = dev_instance;
5223 struct rtl8169_private *tp = netdev_priv(dev);
5224 void __iomem *ioaddr = tp->mmio_addr;
5228 /* loop handling interrupts until we have no new ones or
5229 * we hit a invalid/hotplug case.
5231 status = RTL_R16(IntrStatus);
5232 while (status && status != 0xffff) {
5233 status &= tp->intr_event;
5239 /* Handle all of the error cases first. These will reset
5240 * the chip, so just exit the loop.
5242 if (unlikely(!netif_running(dev))) {
5243 rtl8169_asic_down(tp);
5247 if (unlikely(status & RxFIFOOver)) {
5248 switch (tp->mac_version) {
5249 /* Work around for rx fifo overflow */
5250 case RTL_GIGA_MAC_VER_11:
5251 netif_stop_queue(dev);
5252 rtl8169_tx_timeout(dev);
5259 if (unlikely(status & SYSErr)) {
5260 rtl8169_pcierr_interrupt(dev);
5264 if (status & LinkChg)
5265 __rtl8169_check_link_status(dev, tp, ioaddr, true);
5267 /* We need to see the lastest version of tp->intr_mask to
5268 * avoid ignoring an MSI interrupt and having to wait for
5269 * another event which may never come.
5272 if (status & tp->intr_mask & tp->napi_event) {
5273 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
5274 tp->intr_mask = ~tp->napi_event;
5276 if (likely(napi_schedule_prep(&tp->napi)))
5277 __napi_schedule(&tp->napi);
5279 netif_info(tp, intr, dev,
5280 "interrupt %04x in poll\n", status);
5283 /* We only get a new MSI interrupt when all active irq
5284 * sources on the chip have been acknowledged. So, ack
5285 * everything we've seen and check if new sources have become
5286 * active to avoid blocking all interrupts from the chip.
5289 (status & RxFIFOOver) ? (status | RxOverflow) : status);
5290 status = RTL_R16(IntrStatus);
5293 return IRQ_RETVAL(handled);
5296 static int rtl8169_poll(struct napi_struct *napi, int budget)
5298 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5299 struct net_device *dev = tp->dev;
5300 void __iomem *ioaddr = tp->mmio_addr;
5303 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
5304 rtl8169_tx_interrupt(dev, tp, ioaddr);
5306 if (work_done < budget) {
5307 napi_complete(napi);
5309 /* We need for force the visibility of tp->intr_mask
5310 * for other CPUs, as we can loose an MSI interrupt
5311 * and potentially wait for a retransmit timeout if we don't.
5312 * The posted write to IntrMask is safe, as it will
5313 * eventually make it to the chip and we won't loose anything
5316 tp->intr_mask = 0xffff;
5318 RTL_W16(IntrMask, tp->intr_event);
5324 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
5326 struct rtl8169_private *tp = netdev_priv(dev);
5328 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5331 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
5332 RTL_W32(RxMissed, 0);
5335 static void rtl8169_down(struct net_device *dev)
5337 struct rtl8169_private *tp = netdev_priv(dev);
5338 void __iomem *ioaddr = tp->mmio_addr;
5340 del_timer_sync(&tp->timer);
5342 netif_stop_queue(dev);
5344 napi_disable(&tp->napi);
5346 spin_lock_irq(&tp->lock);
5348 rtl8169_asic_down(tp);
5350 * At this point device interrupts can not be enabled in any function,
5351 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
5352 * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
5354 rtl8169_rx_missed(dev, ioaddr);
5356 spin_unlock_irq(&tp->lock);
5358 synchronize_irq(dev->irq);
5360 /* Give a racing hard_start_xmit a few cycles to complete. */
5361 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
5363 rtl8169_tx_clear(tp);
5365 rtl8169_rx_clear(tp);
5367 rtl_pll_power_down(tp);
5370 static int rtl8169_close(struct net_device *dev)
5372 struct rtl8169_private *tp = netdev_priv(dev);
5373 struct pci_dev *pdev = tp->pci_dev;
5375 pm_runtime_get_sync(&pdev->dev);
5377 /* Update counters before going down */
5378 rtl8169_update_counters(dev);
5382 free_irq(dev->irq, dev);
5384 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5386 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5388 tp->TxDescArray = NULL;
5389 tp->RxDescArray = NULL;
5391 pm_runtime_put_sync(&pdev->dev);
5396 static void rtl_set_rx_mode(struct net_device *dev)
5398 struct rtl8169_private *tp = netdev_priv(dev);
5399 void __iomem *ioaddr = tp->mmio_addr;
5400 unsigned long flags;
5401 u32 mc_filter[2]; /* Multicast hash filter */
5405 if (dev->flags & IFF_PROMISC) {
5406 /* Unconditionally log net taps. */
5407 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
5409 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5411 mc_filter[1] = mc_filter[0] = 0xffffffff;
5412 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
5413 (dev->flags & IFF_ALLMULTI)) {
5414 /* Too many to filter perfectly -- accept all multicasts. */
5415 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5416 mc_filter[1] = mc_filter[0] = 0xffffffff;
5418 struct netdev_hw_addr *ha;
5420 rx_mode = AcceptBroadcast | AcceptMyPhys;
5421 mc_filter[1] = mc_filter[0] = 0;
5422 netdev_for_each_mc_addr(ha, dev) {
5423 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
5424 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5425 rx_mode |= AcceptMulticast;
5429 spin_lock_irqsave(&tp->lock, flags);
5431 tmp = rtl8169_rx_config | rx_mode |
5432 (RTL_R32(RxConfig) & RTL_RX_CONFIG_MASK);
5434 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
5435 u32 data = mc_filter[0];
5437 mc_filter[0] = swab32(mc_filter[1]);
5438 mc_filter[1] = swab32(data);
5441 RTL_W32(MAR0 + 4, mc_filter[1]);
5442 RTL_W32(MAR0 + 0, mc_filter[0]);
5444 RTL_W32(RxConfig, tmp);
5446 spin_unlock_irqrestore(&tp->lock, flags);
5450 * rtl8169_get_stats - Get rtl8169 read/write statistics
5451 * @dev: The Ethernet Device to get statistics for
5453 * Get TX/RX statistics for rtl8169
5455 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
5457 struct rtl8169_private *tp = netdev_priv(dev);
5458 void __iomem *ioaddr = tp->mmio_addr;
5459 unsigned long flags;
5461 if (netif_running(dev)) {
5462 spin_lock_irqsave(&tp->lock, flags);
5463 rtl8169_rx_missed(dev, ioaddr);
5464 spin_unlock_irqrestore(&tp->lock, flags);
5470 static void rtl8169_net_suspend(struct net_device *dev)
5472 struct rtl8169_private *tp = netdev_priv(dev);
5474 if (!netif_running(dev))
5477 rtl_pll_power_down(tp);
5479 netif_device_detach(dev);
5480 netif_stop_queue(dev);
5485 static int rtl8169_suspend(struct device *device)
5487 struct pci_dev *pdev = to_pci_dev(device);
5488 struct net_device *dev = pci_get_drvdata(pdev);
5490 rtl8169_net_suspend(dev);
5495 static void __rtl8169_resume(struct net_device *dev)
5497 struct rtl8169_private *tp = netdev_priv(dev);
5499 netif_device_attach(dev);
5501 rtl_pll_power_up(tp);
5503 rtl8169_schedule_work(dev, rtl8169_reset_task);
5506 static int rtl8169_resume(struct device *device)
5508 struct pci_dev *pdev = to_pci_dev(device);
5509 struct net_device *dev = pci_get_drvdata(pdev);
5510 struct rtl8169_private *tp = netdev_priv(dev);
5512 rtl8169_init_phy(dev, tp);
5514 if (netif_running(dev))
5515 __rtl8169_resume(dev);
5520 static int rtl8169_runtime_suspend(struct device *device)
5522 struct pci_dev *pdev = to_pci_dev(device);
5523 struct net_device *dev = pci_get_drvdata(pdev);
5524 struct rtl8169_private *tp = netdev_priv(dev);
5526 if (!tp->TxDescArray)
5529 spin_lock_irq(&tp->lock);
5530 tp->saved_wolopts = __rtl8169_get_wol(tp);
5531 __rtl8169_set_wol(tp, WAKE_ANY);
5532 spin_unlock_irq(&tp->lock);
5534 rtl8169_net_suspend(dev);
5539 static int rtl8169_runtime_resume(struct device *device)
5541 struct pci_dev *pdev = to_pci_dev(device);
5542 struct net_device *dev = pci_get_drvdata(pdev);
5543 struct rtl8169_private *tp = netdev_priv(dev);
5545 if (!tp->TxDescArray)
5548 spin_lock_irq(&tp->lock);
5549 __rtl8169_set_wol(tp, tp->saved_wolopts);
5550 tp->saved_wolopts = 0;
5551 spin_unlock_irq(&tp->lock);
5553 rtl8169_init_phy(dev, tp);
5555 __rtl8169_resume(dev);
5560 static int rtl8169_runtime_idle(struct device *device)
5562 struct pci_dev *pdev = to_pci_dev(device);
5563 struct net_device *dev = pci_get_drvdata(pdev);
5564 struct rtl8169_private *tp = netdev_priv(dev);
5566 return tp->TxDescArray ? -EBUSY : 0;
5569 static const struct dev_pm_ops rtl8169_pm_ops = {
5570 .suspend = rtl8169_suspend,
5571 .resume = rtl8169_resume,
5572 .freeze = rtl8169_suspend,
5573 .thaw = rtl8169_resume,
5574 .poweroff = rtl8169_suspend,
5575 .restore = rtl8169_resume,
5576 .runtime_suspend = rtl8169_runtime_suspend,
5577 .runtime_resume = rtl8169_runtime_resume,
5578 .runtime_idle = rtl8169_runtime_idle,
5581 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
5583 #else /* !CONFIG_PM */
5585 #define RTL8169_PM_OPS NULL
5587 #endif /* !CONFIG_PM */
5589 static void rtl_shutdown(struct pci_dev *pdev)
5591 struct net_device *dev = pci_get_drvdata(pdev);
5592 struct rtl8169_private *tp = netdev_priv(dev);
5593 void __iomem *ioaddr = tp->mmio_addr;
5594 struct device *d = &pdev->dev;
5596 pm_runtime_get_sync(d);
5598 rtl8169_net_suspend(dev);
5600 /* Restore original MAC address */
5601 rtl_rar_set(tp, dev->perm_addr);
5603 spin_lock_irq(&tp->lock);
5605 rtl8169_asic_down(tp);
5607 spin_unlock_irq(&tp->lock);
5609 if (system_state == SYSTEM_POWER_OFF) {
5610 /* WoL fails with 8168b when the receiver is disabled. */
5611 if ((tp->mac_version == RTL_GIGA_MAC_VER_11 ||
5612 tp->mac_version == RTL_GIGA_MAC_VER_12 ||
5613 tp->mac_version == RTL_GIGA_MAC_VER_17) &&
5614 (tp->features & RTL_FEATURE_WOL)) {
5615 pci_clear_master(pdev);
5617 RTL_W8(ChipCmd, CmdRxEnb);
5622 pci_wake_from_d3(pdev, true);
5623 pci_set_power_state(pdev, PCI_D3hot);
5626 pm_runtime_put_noidle(d);
5629 static struct pci_driver rtl8169_pci_driver = {
5631 .id_table = rtl8169_pci_tbl,
5632 .probe = rtl8169_init_one,
5633 .remove = __devexit_p(rtl8169_remove_one),
5634 .shutdown = rtl_shutdown,
5635 .driver.pm = RTL8169_PM_OPS,
5638 static int __init rtl8169_init_module(void)
5640 return pci_register_driver(&rtl8169_pci_driver);
5643 static void __exit rtl8169_cleanup_module(void)
5645 pci_unregister_driver(&rtl8169_pci_driver);
5648 module_init(rtl8169_init_module);
5649 module_exit(rtl8169_cleanup_module);