drivers/net/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/mii.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/crc32.h>
  21 #include <linux/in.h>
  22 #include <linux/ip.h>
  23 #include <linux/tcp.h>
  24 #include <linux/init.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/firmware.h>
  28 #include <linux/pci-aspm.h>
  29 #include <linux/prefetch.h>
  30
  31 #include <asm/system.h>
  32 #include <asm/io.h>
  33 #include <asm/irq.h>
  34
  35 #define RTL8169_VERSION "2.3LK-NAPI"
  36 #define MODULENAME "r8169"
  37 #define PFX MODULENAME ": "
  38
  39 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  40 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  41 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  42 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  43 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  44
  45 #ifdef RTL8169_DEBUG
  46 #define assert(expr) \
  47         if (!(expr)) {                                  \
  48                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  49                 #expr,__FILE__,__func__,__LINE__);              \
  50         }
  51 #define dprintk(fmt, args...) \
  52         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
  53 #else
  54 #define assert(expr) do {} while (0)
  55 #define dprintk(fmt, args...)   do {} while (0)
  56 #endif /* RTL8169_DEBUG */
  57
  58 #define R8169_MSG_DEFAULT \
  59         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  60
  61 #define TX_SLOTS_AVAIL(tp) \
  62         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
  63
  64 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
  65 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
  66         (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
  67
  68 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  69    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  70 static const int multicast_filter_limit = 32;
  71
  72 /* MAC address length */
  73 #define MAC_ADDR_LEN    6
  74
  75 #define MAX_READ_REQUEST_SHIFT  12
  76 #define RX_FIFO_THRESH  7       /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
  77 #define RX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  78 #define TX_DMA_BURST    7       /* Maximum PCI burst, '7' is unlimited */
  79 #define SafeMtu         0x1c20  /* ... actually life sucks beyond ~7k */
  80 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  81
  82 #define R8169_REGS_SIZE         256
  83 #define R8169_NAPI_WEIGHT       64
  84 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  85 #define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
  86 #define RX_BUF_SIZE     1536    /* Rx Buffer size */
  87 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  88 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  89
  90 #define RTL8169_TX_TIMEOUT      (6*HZ)
  91 #define RTL8169_PHY_TIMEOUT     (10*HZ)
  92
  93 #define RTL_EEPROM_SIG          cpu_to_le32(0x8129)
  94 #define RTL_EEPROM_SIG_MASK     cpu_to_le32(0xffff)
  95 #define RTL_EEPROM_SIG_ADDR     0x0000
  96
  97 /* write/read MMIO register */
  98 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
  99 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
 100 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
 101 #define RTL_R8(reg)             readb (ioaddr + (reg))
 102 #define RTL_R16(reg)            readw (ioaddr + (reg))
 103 #define RTL_R32(reg)            readl (ioaddr + (reg))
 104
 105 enum mac_version {
 106         RTL_GIGA_MAC_VER_01 = 0,
 107         RTL_GIGA_MAC_VER_02,
 108         RTL_GIGA_MAC_VER_03,
 109         RTL_GIGA_MAC_VER_04,
 110         RTL_GIGA_MAC_VER_05,
 111         RTL_GIGA_MAC_VER_06,
 112         RTL_GIGA_MAC_VER_07,
 113         RTL_GIGA_MAC_VER_08,
 114         RTL_GIGA_MAC_VER_09,
 115         RTL_GIGA_MAC_VER_10,
 116         RTL_GIGA_MAC_VER_11,
 117         RTL_GIGA_MAC_VER_12,
 118         RTL_GIGA_MAC_VER_13,
 119         RTL_GIGA_MAC_VER_14,
 120         RTL_GIGA_MAC_VER_15,
 121         RTL_GIGA_MAC_VER_16,
 122         RTL_GIGA_MAC_VER_17,
 123         RTL_GIGA_MAC_VER_18,
 124         RTL_GIGA_MAC_VER_19,
 125         RTL_GIGA_MAC_VER_20,
 126         RTL_GIGA_MAC_VER_21,
 127         RTL_GIGA_MAC_VER_22,
 128         RTL_GIGA_MAC_VER_23,
 129         RTL_GIGA_MAC_VER_24,
 130         RTL_GIGA_MAC_VER_25,
 131         RTL_GIGA_MAC_VER_26,
 132         RTL_GIGA_MAC_VER_27,
 133         RTL_GIGA_MAC_VER_28,
 134         RTL_GIGA_MAC_VER_29,
 135         RTL_GIGA_MAC_VER_30,
 136         RTL_GIGA_MAC_VER_31,
 137         RTL_GIGA_MAC_VER_32,
 138         RTL_GIGA_MAC_VER_33,
 139         RTL_GIGA_MAC_NONE   = 0xff,
 140 };
 141
 142 enum rtl_tx_desc_version {
 143         RTL_TD_0        = 0,
 144         RTL_TD_1        = 1,
 145 };
 146
 147 #define JUMBO_1K        ETH_DATA_LEN
 148 #define JUMBO_4K        (4*1024 - ETH_HLEN - 2)
 149 #define JUMBO_6K        (6*1024 - ETH_HLEN - 2)
 150 #define JUMBO_7K        (7*1024 - ETH_HLEN - 2)
 151 #define JUMBO_9K        (9*1024 - ETH_HLEN - 2)
 152
 153 #define _R(NAME,TD,FW,SZ,B) {   \
 154         .name = NAME,           \
 155         .txd_version = TD,      \
 156         .fw_name = FW,          \
 157         .jumbo_max = SZ,        \
 158         .jumbo_tx_csum = B      \
 159 }
 160
 161 static const struct {
 162         const char *name;
 163         enum rtl_tx_desc_version txd_version;
 164         const char *fw_name;
 165         u16 jumbo_max;
 166         bool jumbo_tx_csum;
 167 } rtl_chip_infos[] = {
 168         /* PCI devices. */
 169         [RTL_GIGA_MAC_VER_01] =
 170                 _R("RTL8169",           RTL_TD_0, NULL, JUMBO_7K, true),
 171         [RTL_GIGA_MAC_VER_02] =
 172                 _R("RTL8169s",          RTL_TD_0, NULL, JUMBO_7K, true),
 173         [RTL_GIGA_MAC_VER_03] =
 174                 _R("RTL8110s",          RTL_TD_0, NULL, JUMBO_7K, true),
 175         [RTL_GIGA_MAC_VER_04] =
 176                 _R("RTL8169sb/8110sb",  RTL_TD_0, NULL, JUMBO_7K, true),
 177         [RTL_GIGA_MAC_VER_05] =
 178                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 179         [RTL_GIGA_MAC_VER_06] =
 180                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 181         /* PCI-E devices. */
 182         [RTL_GIGA_MAC_VER_07] =
 183                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 184         [RTL_GIGA_MAC_VER_08] =
 185                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 186         [RTL_GIGA_MAC_VER_09] =
 187                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 188         [RTL_GIGA_MAC_VER_10] =
 189                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 190         [RTL_GIGA_MAC_VER_11] =
 191                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 192         [RTL_GIGA_MAC_VER_12] =
 193                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 194         [RTL_GIGA_MAC_VER_13] =
 195                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 196         [RTL_GIGA_MAC_VER_14] =
 197                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 198         [RTL_GIGA_MAC_VER_15] =
 199                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 200         [RTL_GIGA_MAC_VER_16] =
 201                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 202         [RTL_GIGA_MAC_VER_17] =
 203                 _R("RTL8168b/8111b",    RTL_TD_1, NULL, JUMBO_4K, false),
 204         [RTL_GIGA_MAC_VER_18] =
 205                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 206         [RTL_GIGA_MAC_VER_19] =
 207                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 208         [RTL_GIGA_MAC_VER_20] =
 209                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 210         [RTL_GIGA_MAC_VER_21] =
 211                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 212         [RTL_GIGA_MAC_VER_22] =
 213                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 214         [RTL_GIGA_MAC_VER_23] =
 215                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 216         [RTL_GIGA_MAC_VER_24] =
 217                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 218         [RTL_GIGA_MAC_VER_25] =
 219                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_1,
 220                                                         JUMBO_9K, false),
 221         [RTL_GIGA_MAC_VER_26] =
 222                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_2,
 223                                                         JUMBO_9K, false),
 224         [RTL_GIGA_MAC_VER_27] =
 225                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 226         [RTL_GIGA_MAC_VER_28] =
 227                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 228         [RTL_GIGA_MAC_VER_29] =
 229                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 230                                                         JUMBO_1K, true),
 231         [RTL_GIGA_MAC_VER_30] =
 232                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 233                                                         JUMBO_1K, true),
 234         [RTL_GIGA_MAC_VER_31] =
 235                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 236         [RTL_GIGA_MAC_VER_32] =
 237                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_1,
 238                                                         JUMBO_9K, false),
 239         [RTL_GIGA_MAC_VER_33] =
 240                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_2,
 241                                                         JUMBO_9K, false)
 242 };
 243 #undef _R
 244
 245 enum cfg_version {
 246         RTL_CFG_0 = 0x00,
 247         RTL_CFG_1,
 248         RTL_CFG_2
 249 };
 250
 251 static void rtl_hw_start_8169(struct net_device *);
 252 static void rtl_hw_start_8168(struct net_device *);
 253 static void rtl_hw_start_8101(struct net_device *);
 254
 255 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
 256         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 257         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 258         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 259         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 260         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 261         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 262         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4302), 0, 0, RTL_CFG_0 },
 263         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
 264         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 265         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 266                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 267         { 0x0001,                               0x8168,
 268                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 269         {0,},
 270 };
 271
 272 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 273
 274 static int rx_buf_sz = 16383;
 275 static int use_dac;
 276 static struct {
 277         u32 msg_enable;
 278 } debug = { -1 };
 279
 280 enum rtl_registers {
 281         MAC0            = 0,    /* Ethernet hardware address. */
 282         MAC4            = 4,
 283         MAR0            = 8,    /* Multicast filter. */
 284         CounterAddrLow          = 0x10,
 285         CounterAddrHigh         = 0x14,
 286         TxDescStartAddrLow      = 0x20,
 287         TxDescStartAddrHigh     = 0x24,
 288         TxHDescStartAddrLow     = 0x28,
 289         TxHDescStartAddrHigh    = 0x2c,
 290         FLASH           = 0x30,
 291         ERSR            = 0x36,
 292         ChipCmd         = 0x37,
 293         TxPoll          = 0x38,
 294         IntrMask        = 0x3c,
 295         IntrStatus      = 0x3e,
 296         TxConfig        = 0x40,
 297         RxConfig        = 0x44,
 298
 299 #define RTL_RX_CONFIG_MASK              0xff7e1880u
 300
 301         RxMissed        = 0x4c,
 302         Cfg9346         = 0x50,
 303         Config0         = 0x51,
 304         Config1         = 0x52,
 305         Config2         = 0x53,
 306 #define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
 307
 308         Config3         = 0x54,
 309         Config4         = 0x55,
 310         Config5         = 0x56,
 311         MultiIntr       = 0x5c,
 312         PHYAR           = 0x60,
 313         PHYstatus       = 0x6c,
 314         RxMaxSize       = 0xda,
 315         CPlusCmd        = 0xe0,
 316         IntrMitigate    = 0xe2,
 317         RxDescAddrLow   = 0xe4,
 318         RxDescAddrHigh  = 0xe8,
 319         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 320
 321 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 322
 323         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 324
 325 #define TxPacketMax     (8064 >> 7)
 326
 327         FuncEvent       = 0xf0,
 328         FuncEventMask   = 0xf4,
 329         FuncPresetState = 0xf8,
 330         FuncForceEvent  = 0xfc,
 331 };
 332
 333 enum rtl8110_registers {
 334         TBICSR                  = 0x64,
 335         TBI_ANAR                = 0x68,
 336         TBI_LPAR                = 0x6a,
 337 };
 338
 339 enum rtl8168_8101_registers {
 340         CSIDR                   = 0x64,
 341         CSIAR                   = 0x68,
 342 #define CSIAR_FLAG                      0x80000000
 343 #define CSIAR_WRITE_CMD                 0x80000000
 344 #define CSIAR_BYTE_ENABLE               0x0f
 345 #define CSIAR_BYTE_ENABLE_SHIFT         12
 346 #define CSIAR_ADDR_MASK                 0x0fff
 347         PMCH                    = 0x6f,
 348         EPHYAR                  = 0x80,
 349 #define EPHYAR_FLAG                     0x80000000
 350 #define EPHYAR_WRITE_CMD                0x80000000
 351 #define EPHYAR_REG_MASK                 0x1f
 352 #define EPHYAR_REG_SHIFT                16
 353 #define EPHYAR_DATA_MASK                0xffff
 354         DLLPR                   = 0xd0,
 355 #define PM_SWITCH                       (1 << 6)
 356         DBG_REG                 = 0xd1,
 357 #define FIX_NAK_1                       (1 << 4)
 358 #define FIX_NAK_2                       (1 << 3)
 359         TWSI                    = 0xd2,
 360         MCU                     = 0xd3,
 361 #define EN_NDP                          (1 << 3)
 362 #define EN_OOB_RESET                    (1 << 2)
 363         EFUSEAR                 = 0xdc,
 364 #define EFUSEAR_FLAG                    0x80000000
 365 #define EFUSEAR_WRITE_CMD               0x80000000
 366 #define EFUSEAR_READ_CMD                0x00000000
 367 #define EFUSEAR_REG_MASK                0x03ff
 368 #define EFUSEAR_REG_SHIFT               8
 369 #define EFUSEAR_DATA_MASK               0xff
 370 };
 371
 372 enum rtl8168_registers {
 373         ERIDR                   = 0x70,
 374         ERIAR                   = 0x74,
 375 #define ERIAR_FLAG                      0x80000000
 376 #define ERIAR_WRITE_CMD                 0x80000000
 377 #define ERIAR_READ_CMD                  0x00000000
 378 #define ERIAR_ADDR_BYTE_ALIGN           4
 379 #define ERIAR_EXGMAC                    0
 380 #define ERIAR_MSIX                      1
 381 #define ERIAR_ASF                       2
 382 #define ERIAR_TYPE_SHIFT                16
 383 #define ERIAR_BYTEEN                    0x0f
 384 #define ERIAR_BYTEEN_SHIFT              12
 385         EPHY_RXER_NUM           = 0x7c,
 386         OCPDR                   = 0xb0, /* OCP GPHY access */
 387 #define OCPDR_WRITE_CMD                 0x80000000
 388 #define OCPDR_READ_CMD                  0x00000000
 389 #define OCPDR_REG_MASK                  0x7f
 390 #define OCPDR_GPHY_REG_SHIFT            16
 391 #define OCPDR_DATA_MASK                 0xffff
 392         OCPAR                   = 0xb4,
 393 #define OCPAR_FLAG                      0x80000000
 394 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 395 #define OCPAR_GPHY_READ_CMD             0x0000f060
 396         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 397         MISC                    = 0xf0, /* 8168e only. */
 398 #define TXPLA_RST                       (1 << 29)
 399 };
 400
 401 enum rtl_register_content {
 402         /* InterruptStatusBits */
 403         SYSErr          = 0x8000,
 404         PCSTimeout      = 0x4000,
 405         SWInt           = 0x0100,
 406         TxDescUnavail   = 0x0080,
 407         RxFIFOOver      = 0x0040,
 408         LinkChg         = 0x0020,
 409         RxOverflow      = 0x0010,
 410         TxErr           = 0x0008,
 411         TxOK            = 0x0004,
 412         RxErr           = 0x0002,
 413         RxOK            = 0x0001,
 414
 415         /* RxStatusDesc */
 416         RxBOVF  = (1 << 24),
 417         RxFOVF  = (1 << 23),
 418         RxRWT   = (1 << 22),
 419         RxRES   = (1 << 21),
 420         RxRUNT  = (1 << 20),
 421         RxCRC   = (1 << 19),
 422
 423         /* ChipCmdBits */
 424         CmdReset        = 0x10,
 425         CmdRxEnb        = 0x08,
 426         CmdTxEnb        = 0x04,
 427         RxBufEmpty      = 0x01,
 428
 429         /* TXPoll register p.5 */
 430         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 431         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 432         FSWInt          = 0x01,         /* Forced software interrupt */
 433
 434         /* Cfg9346Bits */
 435         Cfg9346_Lock    = 0x00,
 436         Cfg9346_Unlock  = 0xc0,
 437
 438         /* rx_mode_bits */
 439         AcceptErr       = 0x20,
 440         AcceptRunt      = 0x10,
 441         AcceptBroadcast = 0x08,
 442         AcceptMulticast = 0x04,
 443         AcceptMyPhys    = 0x02,
 444         AcceptAllPhys   = 0x01,
 445
 446         /* RxConfigBits */
 447         RxCfgFIFOShift  = 13,
 448         RxCfgDMAShift   =  8,
 449
 450         /* TxConfigBits */
 451         TxInterFrameGapShift = 24,
 452         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 453
 454         /* Config1 register p.24 */
 455         LEDS1           = (1 << 7),
 456         LEDS0           = (1 << 6),
 457         Speed_down      = (1 << 4),
 458         MEMMAP          = (1 << 3),
 459         IOMAP           = (1 << 2),
 460         VPD             = (1 << 1),
 461         PMEnable        = (1 << 0),     /* Power Management Enable */
 462
 463         /* Config2 register p. 25 */
 464         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 465         PCI_Clock_66MHz = 0x01,
 466         PCI_Clock_33MHz = 0x00,
 467
 468         /* Config3 register p.25 */
 469         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 470         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 471         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 472         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 473
 474         /* Config4 register */
 475         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 476
 477         /* Config5 register p.27 */
 478         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 479         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 480         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 481         Spi_en          = (1 << 3),
 482         LanWake         = (1 << 1),     /* LanWake enable/disable */
 483         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 484
 485         /* TBICSR p.28 */
 486         TBIReset        = 0x80000000,
 487         TBILoopback     = 0x40000000,
 488         TBINwEnable     = 0x20000000,
 489         TBINwRestart    = 0x10000000,
 490         TBILinkOk       = 0x02000000,
 491         TBINwComplete   = 0x01000000,
 492
 493         /* CPlusCmd p.31 */
 494         EnableBist      = (1 << 15),    // 8168 8101
 495         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 496         Normal_mode     = (1 << 13),    // unused
 497         Force_half_dup  = (1 << 12),    // 8168 8101
 498         Force_rxflow_en = (1 << 11),    // 8168 8101
 499         Force_txflow_en = (1 << 10),    // 8168 8101
 500         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 501         ASF             = (1 << 8),     // 8168 8101
 502         PktCntrDisable  = (1 << 7),     // 8168 8101
 503         Mac_dbgo_sel    = 0x001c,       // 8168
 504         RxVlan          = (1 << 6),
 505         RxChkSum        = (1 << 5),
 506         PCIDAC          = (1 << 4),
 507         PCIMulRW        = (1 << 3),
 508         INTT_0          = 0x0000,       // 8168
 509         INTT_1          = 0x0001,       // 8168
 510         INTT_2          = 0x0002,       // 8168
 511         INTT_3          = 0x0003,       // 8168
 512
 513         /* rtl8169_PHYstatus */
 514         TBI_Enable      = 0x80,
 515         TxFlowCtrl      = 0x40,
 516         RxFlowCtrl      = 0x20,
 517         _1000bpsF       = 0x10,
 518         _100bps         = 0x08,
 519         _10bps          = 0x04,
 520         LinkStatus      = 0x02,
 521         FullDup         = 0x01,
 522
 523         /* _TBICSRBit */
 524         TBILinkOK       = 0x02000000,
 525
 526         /* DumpCounterCommand */
 527         CounterDump     = 0x8,
 528 };
 529
 530 enum rtl_desc_bit {
 531         /* First doubleword. */
 532         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 533         RingEnd         = (1 << 30), /* End of descriptor ring */
 534         FirstFrag       = (1 << 29), /* First segment of a packet */
 535         LastFrag        = (1 << 28), /* Final segment of a packet */
 536 };
 537
 538 /* Generic case. */
 539 enum rtl_tx_desc_bit {
 540         /* First doubleword. */
 541         TD_LSO          = (1 << 27),            /* Large Send Offload */
 542 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 543
 544         /* Second doubleword. */
 545         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 546 };
 547
 548 /* 8169, 8168b and 810x except 8102e. */
 549 enum rtl_tx_desc_bit_0 {
 550         /* First doubleword. */
 551 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 552         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 553         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 554         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 555 };
 556
 557 /* 8102e, 8168c and beyond. */
 558 enum rtl_tx_desc_bit_1 {
 559         /* Second doubleword. */
 560 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 561         TD1_IP_CS       = (1 << 29),            /* Calculate IP checksum */
 562         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 563         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 564 };
 565
 566 static const struct rtl_tx_desc_info {
 567         struct {
 568                 u32 udp;
 569                 u32 tcp;
 570         } checksum;
 571         u16 mss_shift;
 572         u16 opts_offset;
 573 } tx_desc_info [] = {
 574         [RTL_TD_0] = {
 575                 .checksum = {
 576                         .udp    = TD0_IP_CS | TD0_UDP_CS,
 577                         .tcp    = TD0_IP_CS | TD0_TCP_CS
 578                 },
 579                 .mss_shift      = TD0_MSS_SHIFT,
 580                 .opts_offset    = 0
 581         },
 582         [RTL_TD_1] = {
 583                 .checksum = {
 584                         .udp    = TD1_IP_CS | TD1_UDP_CS,
 585                         .tcp    = TD1_IP_CS | TD1_TCP_CS
 586                 },
 587                 .mss_shift      = TD1_MSS_SHIFT,
 588                 .opts_offset    = 1
 589         }
 590 };
 591
 592 enum rtl_rx_desc_bit {
 593         /* Rx private */
 594         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 595         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
 596
 597 #define RxProtoUDP      (PID1)
 598 #define RxProtoTCP      (PID0)
 599 #define RxProtoIP       (PID1 | PID0)
 600 #define RxProtoMask     RxProtoIP
 601
 602         IPFail          = (1 << 16), /* IP checksum failed */
 603         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 604         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 605         RxVlanTag       = (1 << 16), /* VLAN tag available */
 606 };
 607
 608 #define RsvdMask        0x3fffc000
 609
 610 struct TxDesc {
 611         __le32 opts1;
 612         __le32 opts2;
 613         __le64 addr;
 614 };
 615
 616 struct RxDesc {
 617         __le32 opts1;
 618         __le32 opts2;
 619         __le64 addr;
 620 };
 621
 622 struct ring_info {
 623         struct sk_buff  *skb;
 624         u32             len;
 625         u8              __pad[sizeof(void *) - sizeof(u32)];
 626 };
 627
 628 enum features {
 629         RTL_FEATURE_WOL         = (1 << 0),
 630         RTL_FEATURE_MSI         = (1 << 1),
 631         RTL_FEATURE_GMII        = (1 << 2),
 632 };
 633
 634 struct rtl8169_counters {
 635         __le64  tx_packets;
 636         __le64  rx_packets;
 637         __le64  tx_errors;
 638         __le32  rx_errors;
 639         __le16  rx_missed;
 640         __le16  align_errors;
 641         __le32  tx_one_collision;
 642         __le32  tx_multi_collision;
 643         __le64  rx_unicast;
 644         __le64  rx_broadcast;
 645         __le32  rx_multicast;
 646         __le16  tx_aborted;
 647         __le16  tx_underun;
 648 };
 649
 650 struct rtl8169_private {
 651         void __iomem *mmio_addr;        /* memory map physical address */
 652         struct pci_dev *pci_dev;
 653         struct net_device *dev;
 654         struct napi_struct napi;
 655         spinlock_t lock;
 656         u32 msg_enable;
 657         u16 txd_version;
 658         u16 mac_version;
 659         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 660         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 661         u32 dirty_rx;
 662         u32 dirty_tx;
 663         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 664         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 665         dma_addr_t TxPhyAddr;
 666         dma_addr_t RxPhyAddr;
 667         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 668         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 669         struct timer_list timer;
 670         u16 cp_cmd;
 671         u16 intr_event;
 672         u16 napi_event;
 673         u16 intr_mask;
 674
 675         struct mdio_ops {
 676                 void (*write)(void __iomem *, int, int);
 677                 int (*read)(void __iomem *, int);
 678         } mdio_ops;
 679
 680         struct pll_power_ops {
 681                 void (*down)(struct rtl8169_private *);
 682                 void (*up)(struct rtl8169_private *);
 683         } pll_power_ops;
 684
 685         struct jumbo_ops {
 686                 void (*enable)(struct rtl8169_private *);
 687                 void (*disable)(struct rtl8169_private *);
 688         } jumbo_ops;
 689
 690         int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
 691         int (*get_settings)(struct net_device *, struct ethtool_cmd *);
 692         void (*phy_reset_enable)(struct rtl8169_private *tp);
 693         void (*hw_start)(struct net_device *);
 694         unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
 695         unsigned int (*link_ok)(void __iomem *);
 696         int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
 697         int pcie_cap;
 698         struct delayed_work task;
 699         unsigned features;
 700
 701         struct mii_if_info mii;
 702         struct rtl8169_counters counters;
 703         u32 saved_wolopts;
 704         u32 opts1_mask;
 705
 706         const struct firmware *fw;
 707 #define RTL_FIRMWARE_UNKNOWN    ERR_PTR(-EAGAIN);
 708 };
 709
 710 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 711 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 712 module_param(use_dac, int, 0);
 713 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 714 module_param_named(debug, debug.msg_enable, int, 0);
 715 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 716 MODULE_LICENSE("GPL");
 717 MODULE_VERSION(RTL8169_VERSION);
 718 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 719 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 720 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 721 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 722 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 723
 724 static int rtl8169_open(struct net_device *dev);
 725 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
 726                                       struct net_device *dev);
 727 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
 728 static int rtl8169_init_ring(struct net_device *dev);
 729 static void rtl_hw_start(struct net_device *dev);
 730 static int rtl8169_close(struct net_device *dev);
 731 static void rtl_set_rx_mode(struct net_device *dev);
 732 static void rtl8169_tx_timeout(struct net_device *dev);
 733 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
 734 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
 735                                 void __iomem *, u32 budget);
 736 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
 737 static void rtl8169_down(struct net_device *dev);
 738 static void rtl8169_rx_clear(struct rtl8169_private *tp);
 739 static int rtl8169_poll(struct napi_struct *napi, int budget);
 740
 741 static const unsigned int rtl8169_rx_config =
 742         (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
 743
 744 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
 745 {
 746         struct net_device *dev = pci_get_drvdata(pdev);
 747         struct rtl8169_private *tp = netdev_priv(dev);
 748         int cap = tp->pcie_cap;
 749
 750         if (cap) {
 751                 u16 ctl;
 752
 753                 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
 754                 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
 755                 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
 756         }
 757 }
 758
 759 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
 760 {
 761         void __iomem *ioaddr = tp->mmio_addr;
 762         int i;
 763
 764         RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 765         for (i = 0; i < 20; i++) {
 766                 udelay(100);
 767                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
 768                         break;
 769         }
 770         return RTL_R32(OCPDR);
 771 }
 772
 773 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
 774 {
 775         void __iomem *ioaddr = tp->mmio_addr;
 776         int i;
 777
 778         RTL_W32(OCPDR, data);
 779         RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 780         for (i = 0; i < 20; i++) {
 781                 udelay(100);
 782                 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
 783                         break;
 784         }
 785 }
 786
 787 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
 788 {
 789         void __iomem *ioaddr = tp->mmio_addr;
 790         int i;
 791
 792         RTL_W8(ERIDR, cmd);
 793         RTL_W32(ERIAR, 0x800010e8);
 794         msleep(2);
 795         for (i = 0; i < 5; i++) {
 796                 udelay(100);
 797                 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
 798                         break;
 799         }
 800
 801         ocp_write(tp, 0x1, 0x30, 0x00000001);
 802 }
 803
 804 #define OOB_CMD_RESET           0x00
 805 #define OOB_CMD_DRIVER_START    0x05
 806 #define OOB_CMD_DRIVER_STOP     0x06
 807
 808 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
 809 {
 810         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
 811 }
 812
 813 static void rtl8168_driver_start(struct rtl8169_private *tp)
 814 {
 815         u16 reg;
 816         int i;
 817
 818         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
 819
 820         reg = rtl8168_get_ocp_reg(tp);
 821
 822         for (i = 0; i < 10; i++) {
 823                 msleep(10);
 824                 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
 825                         break;
 826         }
 827 }
 828
 829 static void rtl8168_driver_stop(struct rtl8169_private *tp)
 830 {
 831         u16 reg;
 832         int i;
 833
 834         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
 835
 836         reg = rtl8168_get_ocp_reg(tp);
 837
 838         for (i = 0; i < 10; i++) {
 839                 msleep(10);
 840                 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
 841                         break;
 842         }
 843 }
 844
 845 static int r8168dp_check_dash(struct rtl8169_private *tp)
 846 {
 847         u16 reg = rtl8168_get_ocp_reg(tp);
 848
 849         return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
 850 }
 851
 852 static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 853 {
 854         int i;
 855
 856         RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
 857
 858         for (i = 20; i > 0; i--) {
 859                 /*
 860                  * Check if the RTL8169 has completed writing to the specified
 861                  * MII register.
 862                  */
 863                 if (!(RTL_R32(PHYAR) & 0x80000000))
 864                         break;
 865                 udelay(25);
 866         }
 867         /*
 868          * According to hardware specs a 20us delay is required after write
 869          * complete indication, but before sending next command.
 870          */
 871         udelay(20);
 872 }
 873
 874 static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
 875 {
 876         int i, value = -1;
 877
 878         RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
 879
 880         for (i = 20; i > 0; i--) {
 881                 /*
 882                  * Check if the RTL8169 has completed retrieving data from
 883                  * the specified MII register.
 884                  */
 885                 if (RTL_R32(PHYAR) & 0x80000000) {
 886                         value = RTL_R32(PHYAR) & 0xffff;
 887                         break;
 888                 }
 889                 udelay(25);
 890         }
 891         /*
 892          * According to hardware specs a 20us delay is required after read
 893          * complete indication, but before sending next command.
 894          */
 895         udelay(20);
 896
 897         return value;
 898 }
 899
 900 static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
 901 {
 902         int i;
 903
 904         RTL_W32(OCPDR, data |
 905                 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
 906         RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
 907         RTL_W32(EPHY_RXER_NUM, 0);
 908
 909         for (i = 0; i < 100; i++) {
 910                 mdelay(1);
 911                 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
 912                         break;
 913         }
 914 }
 915
 916 static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 917 {
 918         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
 919                 (value & OCPDR_DATA_MASK));
 920 }
 921
 922 static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
 923 {
 924         int i;
 925
 926         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
 927
 928         mdelay(1);
 929         RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
 930         RTL_W32(EPHY_RXER_NUM, 0);
 931
 932         for (i = 0; i < 100; i++) {
 933                 mdelay(1);
 934                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
 935                         break;
 936         }
 937
 938         return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
 939 }
 940
 941 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
 942
 943 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
 944 {
 945         RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
 946 }
 947
 948 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
 949 {
 950         RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
 951 }
 952
 953 static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 954 {
 955         r8168dp_2_mdio_start(ioaddr);
 956
 957         r8169_mdio_write(ioaddr, reg_addr, value);
 958
 959         r8168dp_2_mdio_stop(ioaddr);
 960 }
 961
 962 static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
 963 {
 964         int value;
 965
 966         r8168dp_2_mdio_start(ioaddr);
 967
 968         value = r8169_mdio_read(ioaddr, reg_addr);
 969
 970         r8168dp_2_mdio_stop(ioaddr);
 971
 972         return value;
 973 }
 974
 975 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
 976 {
 977         tp->mdio_ops.write(tp->mmio_addr, location, val);
 978 }
 979
 980 static int rtl_readphy(struct rtl8169_private *tp, int location)
 981 {
 982         return tp->mdio_ops.read(tp->mmio_addr, location);
 983 }
 984
 985 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
 986 {
 987         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
 988 }
 989
 990 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
 991 {
 992         int val;
 993
 994         val = rtl_readphy(tp, reg_addr);
 995         rtl_writephy(tp, reg_addr, (val | p) & ~m);
 996 }
 997
 998 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
 999                            int val)
1000 {
1001         struct rtl8169_private *tp = netdev_priv(dev);
1002
1003         rtl_writephy(tp, location, val);
1004 }
1005
1006 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1007 {
1008         struct rtl8169_private *tp = netdev_priv(dev);
1009
1010         return rtl_readphy(tp, location);
1011 }
1012
1013 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
1014 {
1015         unsigned int i;
1016
1017         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1018                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1019
1020         for (i = 0; i < 100; i++) {
1021                 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
1022                         break;
1023                 udelay(10);
1024         }
1025 }
1026
1027 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
1028 {
1029         u16 value = 0xffff;
1030         unsigned int i;
1031
1032         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1033
1034         for (i = 0; i < 100; i++) {
1035                 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
1036                         value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
1037                         break;
1038                 }
1039                 udelay(10);
1040         }
1041
1042         return value;
1043 }
1044
1045 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
1046 {
1047         unsigned int i;
1048
1049         RTL_W32(CSIDR, value);
1050         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
1051                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1052
1053         for (i = 0; i < 100; i++) {
1054                 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
1055                         break;
1056                 udelay(10);
1057         }
1058 }
1059
1060 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
1061 {
1062         u32 value = ~0x00;
1063         unsigned int i;
1064
1065         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
1066                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1067
1068         for (i = 0; i < 100; i++) {
1069                 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
1070                         value = RTL_R32(CSIDR);
1071                         break;
1072                 }
1073                 udelay(10);
1074         }
1075
1076         return value;
1077 }
1078
1079 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
1080 {
1081         u8 value = 0xff;
1082         unsigned int i;
1083
1084         RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1085
1086         for (i = 0; i < 300; i++) {
1087                 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
1088                         value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
1089                         break;
1090                 }
1091                 udelay(100);
1092         }
1093
1094         return value;
1095 }
1096
1097 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1098 {
1099         void __iomem *ioaddr = tp->mmio_addr;
1100
1101         RTL_W16(IntrMask, 0x0000);
1102         RTL_W16(IntrStatus, tp->intr_event);
1103         RTL_R8(ChipCmd);
1104 }
1105
1106 static void rtl8169_asic_down(struct rtl8169_private *tp)
1107 {
1108         void __iomem *ioaddr = tp->mmio_addr;
1109
1110         RTL_W8(ChipCmd, 0x00);
1111         rtl8169_irq_mask_and_ack(tp);
1112         RTL_R16(CPlusCmd);
1113 }
1114
1115 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1116 {
1117         void __iomem *ioaddr = tp->mmio_addr;
1118
1119         return RTL_R32(TBICSR) & TBIReset;
1120 }
1121
1122 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1123 {
1124         return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1125 }
1126
1127 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1128 {
1129         return RTL_R32(TBICSR) & TBILinkOk;
1130 }
1131
1132 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1133 {
1134         return RTL_R8(PHYstatus) & LinkStatus;
1135 }
1136
1137 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1138 {
1139         void __iomem *ioaddr = tp->mmio_addr;
1140
1141         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1142 }
1143
1144 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1145 {
1146         unsigned int val;
1147
1148         val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1149         rtl_writephy(tp, MII_BMCR, val & 0xffff);
1150 }
1151
1152 static void __rtl8169_check_link_status(struct net_device *dev,
1153                                         struct rtl8169_private *tp,
1154                                         void __iomem *ioaddr, bool pm)
1155 {
1156         unsigned long flags;
1157
1158         spin_lock_irqsave(&tp->lock, flags);
1159         if (tp->link_ok(ioaddr)) {
1160                 /* This is to cancel a scheduled suspend if there's one. */
1161                 if (pm)
1162                         pm_request_resume(&tp->pci_dev->dev);
1163                 netif_carrier_on(dev);
1164                 if (net_ratelimit())
1165                         netif_info(tp, ifup, dev, "link up\n");
1166         } else {
1167                 netif_carrier_off(dev);
1168                 netif_info(tp, ifdown, dev, "link down\n");
1169                 if (pm)
1170                         pm_schedule_suspend(&tp->pci_dev->dev, 5000);
1171         }
1172         spin_unlock_irqrestore(&tp->lock, flags);
1173 }
1174
1175 static void rtl8169_check_link_status(struct net_device *dev,
1176                                       struct rtl8169_private *tp,
1177                                       void __iomem *ioaddr)
1178 {
1179         __rtl8169_check_link_status(dev, tp, ioaddr, false);
1180 }
1181
1182 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1183
1184 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1185 {
1186         void __iomem *ioaddr = tp->mmio_addr;
1187         u8 options;
1188         u32 wolopts = 0;
1189
1190         options = RTL_R8(Config1);
1191         if (!(options & PMEnable))
1192                 return 0;
1193
1194         options = RTL_R8(Config3);
1195         if (options & LinkUp)
1196                 wolopts |= WAKE_PHY;
1197         if (options & MagicPacket)
1198                 wolopts |= WAKE_MAGIC;
1199
1200         options = RTL_R8(Config5);
1201         if (options & UWF)
1202                 wolopts |= WAKE_UCAST;
1203         if (options & BWF)
1204                 wolopts |= WAKE_BCAST;
1205         if (options & MWF)
1206                 wolopts |= WAKE_MCAST;
1207
1208         return wolopts;
1209 }
1210
1211 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1212 {
1213         struct rtl8169_private *tp = netdev_priv(dev);
1214
1215         spin_lock_irq(&tp->lock);
1216
1217         wol->supported = WAKE_ANY;
1218         wol->wolopts = __rtl8169_get_wol(tp);
1219
1220         spin_unlock_irq(&tp->lock);
1221 }
1222
1223 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1224 {
1225         void __iomem *ioaddr = tp->mmio_addr;
1226         unsigned int i;
1227         static const struct {
1228                 u32 opt;
1229                 u16 reg;
1230                 u8  mask;
1231         } cfg[] = {
1232                 { WAKE_PHY,   Config3, LinkUp },
1233                 { WAKE_MAGIC, Config3, MagicPacket },
1234                 { WAKE_UCAST, Config5, UWF },
1235                 { WAKE_BCAST, Config5, BWF },
1236                 { WAKE_MCAST, Config5, MWF },
1237                 { WAKE_ANY,   Config5, LanWake }
1238         };
1239         u8 options;
1240
1241         RTL_W8(Cfg9346, Cfg9346_Unlock);
1242
1243         for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1244                 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1245                 if (wolopts & cfg[i].opt)
1246                         options |= cfg[i].mask;
1247                 RTL_W8(cfg[i].reg, options);
1248         }
1249
1250         switch (tp->mac_version) {
1251         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1252                 options = RTL_R8(Config1) & ~PMEnable;
1253                 if (wolopts)
1254                         options |= PMEnable;
1255                 RTL_W8(Config1, options);
1256                 break;
1257         default:
1258                 options = RTL_R8(Config2) & ~PME_SIGNAL;
1259                 if (wolopts)
1260                         options |= PME_SIGNAL;
1261                 RTL_W8(Config2, options);
1262                 break;
1263         }
1264
1265         RTL_W8(Cfg9346, Cfg9346_Lock);
1266 }
1267
1268 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1269 {
1270         struct rtl8169_private *tp = netdev_priv(dev);
1271
1272         spin_lock_irq(&tp->lock);
1273
1274         if (wol->wolopts)
1275                 tp->features |= RTL_FEATURE_WOL;
1276         else
1277                 tp->features &= ~RTL_FEATURE_WOL;
1278         __rtl8169_set_wol(tp, wol->wolopts);
1279         spin_unlock_irq(&tp->lock);
1280
1281         device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1282
1283         return 0;
1284 }
1285
1286 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1287 {
1288         return rtl_chip_infos[tp->mac_version].fw_name;
1289 }
1290
1291 static void rtl8169_get_drvinfo(struct net_device *dev,
1292                                 struct ethtool_drvinfo *info)
1293 {
1294         struct rtl8169_private *tp = netdev_priv(dev);
1295
1296         strcpy(info->driver, MODULENAME);
1297         strcpy(info->version, RTL8169_VERSION);
1298         strcpy(info->bus_info, pci_name(tp->pci_dev));
1299         strncpy(info->fw_version, IS_ERR_OR_NULL(tp->fw) ? "N/A" :
1300                 rtl_lookup_firmware_name(tp), sizeof(info->fw_version) - 1);
1301 }
1302
1303 static int rtl8169_get_regs_len(struct net_device *dev)
1304 {
1305         return R8169_REGS_SIZE;
1306 }
1307
1308 static int rtl8169_set_speed_tbi(struct net_device *dev,
1309                                  u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1310 {
1311         struct rtl8169_private *tp = netdev_priv(dev);
1312         void __iomem *ioaddr = tp->mmio_addr;
1313         int ret = 0;
1314         u32 reg;
1315
1316         reg = RTL_R32(TBICSR);
1317         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1318             (duplex == DUPLEX_FULL)) {
1319                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1320         } else if (autoneg == AUTONEG_ENABLE)
1321                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1322         else {
1323                 netif_warn(tp, link, dev,
1324                            "incorrect speed setting refused in TBI mode\n");
1325                 ret = -EOPNOTSUPP;
1326         }
1327
1328         return ret;
1329 }
1330
1331 static int rtl8169_set_speed_xmii(struct net_device *dev,
1332                                   u8 autoneg, u16 speed, u8 duplex, u32 adv)
1333 {
1334         struct rtl8169_private *tp = netdev_priv(dev);
1335         int giga_ctrl, bmcr;
1336         int rc = -EINVAL;
1337
1338         rtl_writephy(tp, 0x1f, 0x0000);
1339
1340         if (autoneg == AUTONEG_ENABLE) {
1341                 int auto_nego;
1342
1343                 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1344                 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1345                                 ADVERTISE_100HALF | ADVERTISE_100FULL);
1346
1347                 if (adv & ADVERTISED_10baseT_Half)
1348                         auto_nego |= ADVERTISE_10HALF;
1349                 if (adv & ADVERTISED_10baseT_Full)
1350                         auto_nego |= ADVERTISE_10FULL;
1351                 if (adv & ADVERTISED_100baseT_Half)
1352                         auto_nego |= ADVERTISE_100HALF;
1353                 if (adv & ADVERTISED_100baseT_Full)
1354                         auto_nego |= ADVERTISE_100FULL;
1355
1356                 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1357
1358                 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1359                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1360
1361                 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1362                 if (tp->mii.supports_gmii) {
1363                         if (adv & ADVERTISED_1000baseT_Half)
1364                                 giga_ctrl |= ADVERTISE_1000HALF;
1365                         if (adv & ADVERTISED_1000baseT_Full)
1366                                 giga_ctrl |= ADVERTISE_1000FULL;
1367                 } else if (adv & (ADVERTISED_1000baseT_Half |
1368                                   ADVERTISED_1000baseT_Full)) {
1369                         netif_info(tp, link, dev,
1370                                    "PHY does not support 1000Mbps\n");
1371                         goto out;
1372                 }
1373
1374                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1375
1376                 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1377                 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1378         } else {
1379                 giga_ctrl = 0;
1380
1381                 if (speed == SPEED_10)
1382                         bmcr = 0;
1383                 else if (speed == SPEED_100)
1384                         bmcr = BMCR_SPEED100;
1385                 else
1386                         goto out;
1387
1388                 if (duplex == DUPLEX_FULL)
1389                         bmcr |= BMCR_FULLDPLX;
1390         }
1391
1392         rtl_writephy(tp, MII_BMCR, bmcr);
1393
1394         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1395             tp->mac_version == RTL_GIGA_MAC_VER_03) {
1396                 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1397                         rtl_writephy(tp, 0x17, 0x2138);
1398                         rtl_writephy(tp, 0x0e, 0x0260);
1399                 } else {
1400                         rtl_writephy(tp, 0x17, 0x2108);
1401                         rtl_writephy(tp, 0x0e, 0x0000);
1402                 }
1403         }
1404
1405         rc = 0;
1406 out:
1407         return rc;
1408 }
1409
1410 static int rtl8169_set_speed(struct net_device *dev,
1411                              u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1412 {
1413         struct rtl8169_private *tp = netdev_priv(dev);
1414         int ret;
1415
1416         ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1417         if (ret < 0)
1418                 goto out;
1419
1420         if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1421             (advertising & ADVERTISED_1000baseT_Full)) {
1422                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1423         }
1424 out:
1425         return ret;
1426 }
1427
1428 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1429 {
1430         struct rtl8169_private *tp = netdev_priv(dev);
1431         unsigned long flags;
1432         int ret;
1433
1434         del_timer_sync(&tp->timer);
1435
1436         spin_lock_irqsave(&tp->lock, flags);
1437         ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
1438                                 cmd->duplex, cmd->advertising);
1439         spin_unlock_irqrestore(&tp->lock, flags);
1440
1441         return ret;
1442 }
1443
1444 static u32 rtl8169_fix_features(struct net_device *dev, u32 features)
1445 {
1446         struct rtl8169_private *tp = netdev_priv(dev);
1447
1448         if (dev->mtu > TD_MSS_MAX)
1449                 features &= ~NETIF_F_ALL_TSO;
1450
1451         if (dev->mtu > JUMBO_1K &&
1452             !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1453                 features &= ~NETIF_F_IP_CSUM;
1454
1455         return features;
1456 }
1457
1458 static int rtl8169_set_features(struct net_device *dev, u32 features)
1459 {
1460         struct rtl8169_private *tp = netdev_priv(dev);
1461         void __iomem *ioaddr = tp->mmio_addr;
1462         unsigned long flags;
1463
1464         spin_lock_irqsave(&tp->lock, flags);
1465
1466         if (features & NETIF_F_RXCSUM)
1467                 tp->cp_cmd |= RxChkSum;
1468         else
1469                 tp->cp_cmd &= ~RxChkSum;
1470
1471         if (dev->features & NETIF_F_HW_VLAN_RX)
1472                 tp->cp_cmd |= RxVlan;
1473         else
1474                 tp->cp_cmd &= ~RxVlan;
1475
1476         RTL_W16(CPlusCmd, tp->cp_cmd);
1477         RTL_R16(CPlusCmd);
1478
1479         spin_unlock_irqrestore(&tp->lock, flags);
1480
1481         return 0;
1482 }
1483
1484 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1485                                       struct sk_buff *skb)
1486 {
1487         return (vlan_tx_tag_present(skb)) ?
1488                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1489 }
1490
1491 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1492 {
1493         u32 opts2 = le32_to_cpu(desc->opts2);
1494
1495         if (opts2 & RxVlanTag)
1496                 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
1497
1498         desc->opts2 = 0;
1499 }
1500
1501 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1502 {
1503         struct rtl8169_private *tp = netdev_priv(dev);
1504         void __iomem *ioaddr = tp->mmio_addr;
1505         u32 status;
1506
1507         cmd->supported =
1508                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1509         cmd->port = PORT_FIBRE;
1510         cmd->transceiver = XCVR_INTERNAL;
1511
1512         status = RTL_R32(TBICSR);
1513         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
1514         cmd->autoneg = !!(status & TBINwEnable);
1515
1516         ethtool_cmd_speed_set(cmd, SPEED_1000);
1517         cmd->duplex = DUPLEX_FULL; /* Always set */
1518
1519         return 0;
1520 }
1521
1522 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1523 {
1524         struct rtl8169_private *tp = netdev_priv(dev);
1525
1526         return mii_ethtool_gset(&tp->mii, cmd);
1527 }
1528
1529 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1530 {
1531         struct rtl8169_private *tp = netdev_priv(dev);
1532         unsigned long flags;
1533         int rc;
1534
1535         spin_lock_irqsave(&tp->lock, flags);
1536
1537         rc = tp->get_settings(dev, cmd);
1538
1539         spin_unlock_irqrestore(&tp->lock, flags);
1540         return rc;
1541 }
1542
1543 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1544                              void *p)
1545 {
1546         struct rtl8169_private *tp = netdev_priv(dev);
1547         unsigned long flags;
1548
1549         if (regs->len > R8169_REGS_SIZE)
1550                 regs->len = R8169_REGS_SIZE;
1551
1552         spin_lock_irqsave(&tp->lock, flags);
1553         memcpy_fromio(p, tp->mmio_addr, regs->len);
1554         spin_unlock_irqrestore(&tp->lock, flags);
1555 }
1556
1557 static u32 rtl8169_get_msglevel(struct net_device *dev)
1558 {
1559         struct rtl8169_private *tp = netdev_priv(dev);
1560
1561         return tp->msg_enable;
1562 }
1563
1564 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1565 {
1566         struct rtl8169_private *tp = netdev_priv(dev);
1567
1568         tp->msg_enable = value;
1569 }
1570
1571 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1572         "tx_packets",
1573         "rx_packets",
1574         "tx_errors",
1575         "rx_errors",
1576         "rx_missed",
1577         "align_errors",
1578         "tx_single_collisions",
1579         "tx_multi_collisions",
1580         "unicast",
1581         "broadcast",
1582         "multicast",
1583         "tx_aborted",
1584         "tx_underrun",
1585 };
1586
1587 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1588 {
1589         switch (sset) {
1590         case ETH_SS_STATS:
1591                 return ARRAY_SIZE(rtl8169_gstrings);
1592         default:
1593                 return -EOPNOTSUPP;
1594         }
1595 }
1596
1597 static void rtl8169_update_counters(struct net_device *dev)
1598 {
1599         struct rtl8169_private *tp = netdev_priv(dev);
1600         void __iomem *ioaddr = tp->mmio_addr;
1601         struct device *d = &tp->pci_dev->dev;
1602         struct rtl8169_counters *counters;
1603         dma_addr_t paddr;
1604         u32 cmd;
1605         int wait = 1000;
1606
1607         /*
1608          * Some chips are unable to dump tally counters when the receiver
1609          * is disabled.
1610          */
1611         if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1612                 return;
1613
1614         counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1615         if (!counters)
1616                 return;
1617
1618         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1619         cmd = (u64)paddr & DMA_BIT_MASK(32);
1620         RTL_W32(CounterAddrLow, cmd);
1621         RTL_W32(CounterAddrLow, cmd | CounterDump);
1622
1623         while (wait--) {
1624                 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1625                         memcpy(&tp->counters, counters, sizeof(*counters));
1626                         break;
1627                 }
1628                 udelay(10);
1629         }
1630
1631         RTL_W32(CounterAddrLow, 0);
1632         RTL_W32(CounterAddrHigh, 0);
1633
1634         dma_free_coherent(d, sizeof(*counters), counters, paddr);
1635 }
1636
1637 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1638                                       struct ethtool_stats *stats, u64 *data)
1639 {
1640         struct rtl8169_private *tp = netdev_priv(dev);
1641
1642         ASSERT_RTNL();
1643
1644         rtl8169_update_counters(dev);
1645
1646         data[0] = le64_to_cpu(tp->counters.tx_packets);
1647         data[1] = le64_to_cpu(tp->counters.rx_packets);
1648         data[2] = le64_to_cpu(tp->counters.tx_errors);
1649         data[3] = le32_to_cpu(tp->counters.rx_errors);
1650         data[4] = le16_to_cpu(tp->counters.rx_missed);
1651         data[5] = le16_to_cpu(tp->counters.align_errors);
1652         data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1653         data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1654         data[8] = le64_to_cpu(tp->counters.rx_unicast);
1655         data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1656         data[10] = le32_to_cpu(tp->counters.rx_multicast);
1657         data[11] = le16_to_cpu(tp->counters.tx_aborted);
1658         data[12] = le16_to_cpu(tp->counters.tx_underun);
1659 }
1660
1661 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1662 {
1663         switch(stringset) {
1664         case ETH_SS_STATS:
1665                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1666                 break;
1667         }
1668 }
1669
1670 static const struct ethtool_ops rtl8169_ethtool_ops = {
1671         .get_drvinfo            = rtl8169_get_drvinfo,
1672         .get_regs_len           = rtl8169_get_regs_len,
1673         .get_link               = ethtool_op_get_link,
1674         .get_settings           = rtl8169_get_settings,
1675         .set_settings           = rtl8169_set_settings,
1676         .get_msglevel           = rtl8169_get_msglevel,
1677         .set_msglevel           = rtl8169_set_msglevel,
1678         .get_regs               = rtl8169_get_regs,
1679         .get_wol                = rtl8169_get_wol,
1680         .set_wol                = rtl8169_set_wol,
1681         .get_strings            = rtl8169_get_strings,
1682         .get_sset_count         = rtl8169_get_sset_count,
1683         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1684 };
1685
1686 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1687                                     struct net_device *dev, u8 default_version)
1688 {
1689         void __iomem *ioaddr = tp->mmio_addr;
1690         /*
1691          * The driver currently handles the 8168Bf and the 8168Be identically
1692          * but they can be identified more specifically through the test below
1693          * if needed:
1694          *
1695          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1696          *
1697          * Same thing for the 8101Eb and the 8101Ec:
1698          *
1699          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1700          */
1701         static const struct rtl_mac_info {
1702                 u32 mask;
1703                 u32 val;
1704                 int mac_version;
1705         } mac_info[] = {
1706                 /* 8168E family. */
1707                 { 0x7cf00000, 0x2c200000,       RTL_GIGA_MAC_VER_33 },
1708                 { 0x7cf00000, 0x2c100000,       RTL_GIGA_MAC_VER_32 },
1709                 { 0x7c800000, 0x2c000000,       RTL_GIGA_MAC_VER_33 },
1710
1711                 /* 8168D family. */
1712                 { 0x7cf00000, 0x28300000,       RTL_GIGA_MAC_VER_26 },
1713                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
1714                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
1715
1716                 /* 8168DP family. */
1717                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
1718                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
1719                 { 0x7cf00000, 0x28b00000,       RTL_GIGA_MAC_VER_31 },
1720
1721                 /* 8168C family. */
1722                 { 0x7cf00000, 0x3cb00000,       RTL_GIGA_MAC_VER_24 },
1723                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
1724                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
1725                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
1726                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
1727                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
1728                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
1729                 { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
1730                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
1731
1732                 /* 8168B family. */
1733                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
1734                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
1735                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
1736                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
1737
1738                 /* 8101 family. */
1739                 { 0x7cf00000, 0x40b00000,       RTL_GIGA_MAC_VER_30 },
1740                 { 0x7cf00000, 0x40a00000,       RTL_GIGA_MAC_VER_30 },
1741                 { 0x7cf00000, 0x40900000,       RTL_GIGA_MAC_VER_29 },
1742                 { 0x7c800000, 0x40800000,       RTL_GIGA_MAC_VER_30 },
1743                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
1744                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
1745                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
1746                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
1747                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
1748                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
1749                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
1750                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
1751                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
1752                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
1753                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
1754                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
1755                 /* FIXME: where did these entries come from ? -- FR */
1756                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
1757                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
1758
1759                 /* 8110 family. */
1760                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
1761                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
1762                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
1763                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
1764                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
1765                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
1766
1767                 /* Catch-all */
1768                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
1769         };
1770         const struct rtl_mac_info *p = mac_info;
1771         u32 reg;
1772
1773         reg = RTL_R32(TxConfig);
1774         while ((reg & p->mask) != p->val)
1775                 p++;
1776         tp->mac_version = p->mac_version;
1777
1778         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
1779                 netif_notice(tp, probe, dev,
1780                              "unknown MAC, using family default\n");
1781                 tp->mac_version = default_version;
1782         }
1783 }
1784
1785 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1786 {
1787         dprintk("mac_version = 0x%02x\n", tp->mac_version);
1788 }
1789
1790 struct phy_reg {
1791         u16 reg;
1792         u16 val;
1793 };
1794
1795 static void rtl_writephy_batch(struct rtl8169_private *tp,
1796                                const struct phy_reg *regs, int len)
1797 {
1798         while (len-- > 0) {
1799                 rtl_writephy(tp, regs->reg, regs->val);
1800                 regs++;
1801         }
1802 }
1803
1804 #define PHY_READ                0x00000000
1805 #define PHY_DATA_OR             0x10000000
1806 #define PHY_DATA_AND            0x20000000
1807 #define PHY_BJMPN               0x30000000
1808 #define PHY_READ_EFUSE          0x40000000
1809 #define PHY_READ_MAC_BYTE       0x50000000
1810 #define PHY_WRITE_MAC_BYTE      0x60000000
1811 #define PHY_CLEAR_READCOUNT     0x70000000
1812 #define PHY_WRITE               0x80000000
1813 #define PHY_READCOUNT_EQ_SKIP   0x90000000
1814 #define PHY_COMP_EQ_SKIPN       0xa0000000
1815 #define PHY_COMP_NEQ_SKIPN      0xb0000000
1816 #define PHY_WRITE_PREVIOUS      0xc0000000
1817 #define PHY_SKIPN               0xd0000000
1818 #define PHY_DELAY_MS            0xe0000000
1819 #define PHY_WRITE_ERI_WORD      0xf0000000
1820
1821 static void
1822 rtl_phy_write_fw(struct rtl8169_private *tp, const struct firmware *fw)
1823 {
1824         __le32 *phytable = (__le32 *)fw->data;
1825         struct net_device *dev = tp->dev;
1826         size_t index, fw_size = fw->size / sizeof(*phytable);
1827         u32 predata, count;
1828
1829         if (fw->size % sizeof(*phytable)) {
1830                 netif_err(tp, probe, dev, "odd sized firmware %zd\n", fw->size);
1831                 return;
1832         }
1833
1834         for (index = 0; index < fw_size; index++) {
1835                 u32 action = le32_to_cpu(phytable[index]);
1836                 u32 regno = (action & 0x0fff0000) >> 16;
1837
1838                 switch(action & 0xf0000000) {
1839                 case PHY_READ:
1840                 case PHY_DATA_OR:
1841                 case PHY_DATA_AND:
1842                 case PHY_READ_EFUSE:
1843                 case PHY_CLEAR_READCOUNT:
1844                 case PHY_WRITE:
1845                 case PHY_WRITE_PREVIOUS:
1846                 case PHY_DELAY_MS:
1847                         break;
1848
1849                 case PHY_BJMPN:
1850                         if (regno > index) {
1851                                 netif_err(tp, probe, tp->dev,
1852                                           "Out of range of firmware\n");
1853                                 return;
1854                         }
1855                         break;
1856                 case PHY_READCOUNT_EQ_SKIP:
1857                         if (index + 2 >= fw_size) {
1858                                 netif_err(tp, probe, tp->dev,
1859                                           "Out of range of firmware\n");
1860                                 return;
1861                         }
1862                         break;
1863                 case PHY_COMP_EQ_SKIPN:
1864                 case PHY_COMP_NEQ_SKIPN:
1865                 case PHY_SKIPN:
1866                         if (index + 1 + regno >= fw_size) {
1867                                 netif_err(tp, probe, tp->dev,
1868                                           "Out of range of firmware\n");
1869                                 return;
1870                         }
1871                         break;
1872
1873                 case PHY_READ_MAC_BYTE:
1874                 case PHY_WRITE_MAC_BYTE:
1875                 case PHY_WRITE_ERI_WORD:
1876                 default:
1877                         netif_err(tp, probe, tp->dev,
1878                                   "Invalid action 0x%08x\n", action);
1879                         return;
1880                 }
1881         }
1882
1883         predata = 0;
1884         count = 0;
1885
1886         for (index = 0; index < fw_size; ) {
1887                 u32 action = le32_to_cpu(phytable[index]);
1888                 u32 data = action & 0x0000ffff;
1889                 u32 regno = (action & 0x0fff0000) >> 16;
1890
1891                 if (!action)
1892                         break;
1893
1894                 switch(action & 0xf0000000) {
1895                 case PHY_READ:
1896                         predata = rtl_readphy(tp, regno);
1897                         count++;
1898                         index++;
1899                         break;
1900                 case PHY_DATA_OR:
1901                         predata |= data;
1902                         index++;
1903                         break;
1904                 case PHY_DATA_AND:
1905                         predata &= data;
1906                         index++;
1907                         break;
1908                 case PHY_BJMPN:
1909                         index -= regno;
1910                         break;
1911                 case PHY_READ_EFUSE:
1912                         predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
1913                         index++;
1914                         break;
1915                 case PHY_CLEAR_READCOUNT:
1916                         count = 0;
1917                         index++;
1918                         break;
1919                 case PHY_WRITE:
1920                         rtl_writephy(tp, regno, data);
1921                         index++;
1922                         break;
1923                 case PHY_READCOUNT_EQ_SKIP:
1924                         index += (count == data) ? 2 : 1;
1925                         break;
1926                 case PHY_COMP_EQ_SKIPN:
1927                         if (predata == data)
1928                                 index += regno;
1929                         index++;
1930                         break;
1931                 case PHY_COMP_NEQ_SKIPN:
1932                         if (predata != data)
1933                                 index += regno;
1934                         index++;
1935                         break;
1936                 case PHY_WRITE_PREVIOUS:
1937                         rtl_writephy(tp, regno, predata);
1938                         index++;
1939                         break;
1940                 case PHY_SKIPN:
1941                         index += regno + 1;
1942                         break;
1943                 case PHY_DELAY_MS:
1944                         mdelay(data);
1945                         index++;
1946                         break;
1947
1948                 case PHY_READ_MAC_BYTE:
1949                 case PHY_WRITE_MAC_BYTE:
1950                 case PHY_WRITE_ERI_WORD:
1951                 default:
1952                         BUG();
1953                 }
1954         }
1955 }
1956
1957 static void rtl_release_firmware(struct rtl8169_private *tp)
1958 {
1959         if (!IS_ERR_OR_NULL(tp->fw))
1960                 release_firmware(tp->fw);
1961         tp->fw = RTL_FIRMWARE_UNKNOWN;
1962 }
1963
1964 static void rtl_apply_firmware(struct rtl8169_private *tp)
1965 {
1966         const struct firmware *fw = tp->fw;
1967
1968         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
1969         if (!IS_ERR_OR_NULL(fw))
1970                 rtl_phy_write_fw(tp, fw);
1971 }
1972
1973 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
1974 {
1975         if (rtl_readphy(tp, reg) != val)
1976                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
1977         else
1978                 rtl_apply_firmware(tp);
1979 }
1980
1981 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1982 {
1983         static const struct phy_reg phy_reg_init[] = {
1984                 { 0x1f, 0x0001 },
1985                 { 0x06, 0x006e },
1986                 { 0x08, 0x0708 },
1987                 { 0x15, 0x4000 },
1988                 { 0x18, 0x65c7 },
1989
1990                 { 0x1f, 0x0001 },
1991                 { 0x03, 0x00a1 },
1992                 { 0x02, 0x0008 },
1993                 { 0x01, 0x0120 },
1994                 { 0x00, 0x1000 },
1995                 { 0x04, 0x0800 },
1996                 { 0x04, 0x0000 },
1997
1998                 { 0x03, 0xff41 },
1999                 { 0x02, 0xdf60 },
2000                 { 0x01, 0x0140 },
2001                 { 0x00, 0x0077 },
2002                 { 0x04, 0x7800 },
2003                 { 0x04, 0x7000 },
2004
2005                 { 0x03, 0x802f },
2006                 { 0x02, 0x4f02 },
2007                 { 0x01, 0x0409 },
2008                 { 0x00, 0xf0f9 },
2009                 { 0x04, 0x9800 },
2010                 { 0x04, 0x9000 },
2011
2012                 { 0x03, 0xdf01 },
2013                 { 0x02, 0xdf20 },
2014                 { 0x01, 0xff95 },
2015                 { 0x00, 0xba00 },
2016                 { 0x04, 0xa800 },
2017                 { 0x04, 0xa000 },
2018
2019                 { 0x03, 0xff41 },
2020                 { 0x02, 0xdf20 },
2021                 { 0x01, 0x0140 },
2022                 { 0x00, 0x00bb },
2023                 { 0x04, 0xb800 },
2024                 { 0x04, 0xb000 },
2025
2026                 { 0x03, 0xdf41 },
2027                 { 0x02, 0xdc60 },
2028                 { 0x01, 0x6340 },
2029                 { 0x00, 0x007d },
2030                 { 0x04, 0xd800 },
2031                 { 0x04, 0xd000 },
2032
2033                 { 0x03, 0xdf01 },
2034                 { 0x02, 0xdf20 },
2035                 { 0x01, 0x100a },
2036                 { 0x00, 0xa0ff },
2037                 { 0x04, 0xf800 },
2038                 { 0x04, 0xf000 },
2039
2040                 { 0x1f, 0x0000 },
2041                 { 0x0b, 0x0000 },
2042                 { 0x00, 0x9200 }
2043         };
2044
2045         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2046 }
2047
2048 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2049 {
2050         static const struct phy_reg phy_reg_init[] = {
2051                 { 0x1f, 0x0002 },
2052                 { 0x01, 0x90d0 },
2053                 { 0x1f, 0x0000 }
2054         };
2055
2056         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2057 }
2058
2059 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2060 {
2061         struct pci_dev *pdev = tp->pci_dev;
2062         u16 vendor_id, device_id;
2063
2064         pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
2065         pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
2066
2067         if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
2068                 return;
2069
2070         rtl_writephy(tp, 0x1f, 0x0001);
2071         rtl_writephy(tp, 0x10, 0xf01b);
2072         rtl_writephy(tp, 0x1f, 0x0000);
2073 }
2074
2075 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2076 {
2077         static const struct phy_reg phy_reg_init[] = {
2078                 { 0x1f, 0x0001 },
2079                 { 0x04, 0x0000 },
2080                 { 0x03, 0x00a1 },
2081                 { 0x02, 0x0008 },
2082                 { 0x01, 0x0120 },
2083                 { 0x00, 0x1000 },
2084                 { 0x04, 0x0800 },
2085                 { 0x04, 0x9000 },
2086                 { 0x03, 0x802f },
2087                 { 0x02, 0x4f02 },
2088                 { 0x01, 0x0409 },
2089                 { 0x00, 0xf099 },
2090                 { 0x04, 0x9800 },
2091                 { 0x04, 0xa000 },
2092                 { 0x03, 0xdf01 },
2093                 { 0x02, 0xdf20 },
2094                 { 0x01, 0xff95 },
2095                 { 0x00, 0xba00 },
2096                 { 0x04, 0xa800 },
2097                 { 0x04, 0xf000 },
2098                 { 0x03, 0xdf01 },
2099                 { 0x02, 0xdf20 },
2100                 { 0x01, 0x101a },
2101                 { 0x00, 0xa0ff },
2102                 { 0x04, 0xf800 },
2103                 { 0x04, 0x0000 },
2104                 { 0x1f, 0x0000 },
2105
2106                 { 0x1f, 0x0001 },
2107                 { 0x10, 0xf41b },
2108                 { 0x14, 0xfb54 },
2109                 { 0x18, 0xf5c7 },
2110                 { 0x1f, 0x0000 },
2111
2112                 { 0x1f, 0x0001 },
2113                 { 0x17, 0x0cc0 },
2114                 { 0x1f, 0x0000 }
2115         };
2116
2117         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2118
2119         rtl8169scd_hw_phy_config_quirk(tp);
2120 }
2121
2122 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2123 {
2124         static const struct phy_reg phy_reg_init[] = {
2125                 { 0x1f, 0x0001 },
2126                 { 0x04, 0x0000 },
2127                 { 0x03, 0x00a1 },
2128                 { 0x02, 0x0008 },
2129                 { 0x01, 0x0120 },
2130                 { 0x00, 0x1000 },
2131                 { 0x04, 0x0800 },
2132                 { 0x04, 0x9000 },
2133                 { 0x03, 0x802f },
2134                 { 0x02, 0x4f02 },
2135                 { 0x01, 0x0409 },
2136                 { 0x00, 0xf099 },
2137                 { 0x04, 0x9800 },
2138                 { 0x04, 0xa000 },
2139                 { 0x03, 0xdf01 },
2140                 { 0x02, 0xdf20 },
2141                 { 0x01, 0xff95 },
2142                 { 0x00, 0xba00 },
2143                 { 0x04, 0xa800 },
2144                 { 0x04, 0xf000 },
2145                 { 0x03, 0xdf01 },
2146                 { 0x02, 0xdf20 },
2147                 { 0x01, 0x101a },
2148                 { 0x00, 0xa0ff },
2149                 { 0x04, 0xf800 },
2150                 { 0x04, 0x0000 },
2151                 { 0x1f, 0x0000 },
2152
2153                 { 0x1f, 0x0001 },
2154                 { 0x0b, 0x8480 },
2155                 { 0x1f, 0x0000 },
2156
2157                 { 0x1f, 0x0001 },
2158                 { 0x18, 0x67c7 },
2159                 { 0x04, 0x2000 },
2160                 { 0x03, 0x002f },
2161                 { 0x02, 0x4360 },
2162                 { 0x01, 0x0109 },
2163                 { 0x00, 0x3022 },
2164                 { 0x04, 0x2800 },
2165                 { 0x1f, 0x0000 },
2166
2167                 { 0x1f, 0x0001 },
2168                 { 0x17, 0x0cc0 },
2169                 { 0x1f, 0x0000 }
2170         };
2171
2172         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2173 }
2174
2175 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2176 {
2177         static const struct phy_reg phy_reg_init[] = {
2178                 { 0x10, 0xf41b },
2179                 { 0x1f, 0x0000 }
2180         };
2181
2182         rtl_writephy(tp, 0x1f, 0x0001);
2183         rtl_patchphy(tp, 0x16, 1 << 0);
2184
2185         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2186 }
2187
2188 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2189 {
2190         static const struct phy_reg phy_reg_init[] = {
2191                 { 0x1f, 0x0001 },
2192                 { 0x10, 0xf41b },
2193                 { 0x1f, 0x0000 }
2194         };
2195
2196         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2197 }
2198
2199 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2200 {
2201         static const struct phy_reg phy_reg_init[] = {
2202                 { 0x1f, 0x0000 },
2203                 { 0x1d, 0x0f00 },
2204                 { 0x1f, 0x0002 },
2205                 { 0x0c, 0x1ec8 },
2206                 { 0x1f, 0x0000 }
2207         };
2208
2209         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2210 }
2211
2212 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2213 {
2214         static const struct phy_reg phy_reg_init[] = {
2215                 { 0x1f, 0x0001 },
2216                 { 0x1d, 0x3d98 },
2217                 { 0x1f, 0x0000 }
2218         };
2219
2220         rtl_writephy(tp, 0x1f, 0x0000);
2221         rtl_patchphy(tp, 0x14, 1 << 5);
2222         rtl_patchphy(tp, 0x0d, 1 << 5);
2223
2224         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2225 }
2226
2227 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2228 {
2229         static const struct phy_reg phy_reg_init[] = {
2230                 { 0x1f, 0x0001 },
2231                 { 0x12, 0x2300 },
2232                 { 0x1f, 0x0002 },
2233                 { 0x00, 0x88d4 },
2234                 { 0x01, 0x82b1 },
2235                 { 0x03, 0x7002 },
2236                 { 0x08, 0x9e30 },
2237                 { 0x09, 0x01f0 },
2238                 { 0x0a, 0x5500 },
2239                 { 0x0c, 0x00c8 },
2240                 { 0x1f, 0x0003 },
2241                 { 0x12, 0xc096 },
2242                 { 0x16, 0x000a },
2243                 { 0x1f, 0x0000 },
2244                 { 0x1f, 0x0000 },
2245                 { 0x09, 0x2000 },
2246                 { 0x09, 0x0000 }
2247         };
2248
2249         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2250
2251         rtl_patchphy(tp, 0x14, 1 << 5);
2252         rtl_patchphy(tp, 0x0d, 1 << 5);
2253         rtl_writephy(tp, 0x1f, 0x0000);
2254 }
2255
2256 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2257 {
2258         static const struct phy_reg phy_reg_init[] = {
2259                 { 0x1f, 0x0001 },
2260                 { 0x12, 0x2300 },
2261                 { 0x03, 0x802f },
2262                 { 0x02, 0x4f02 },
2263                 { 0x01, 0x0409 },
2264                 { 0x00, 0xf099 },
2265                 { 0x04, 0x9800 },
2266                 { 0x04, 0x9000 },
2267                 { 0x1d, 0x3d98 },
2268                 { 0x1f, 0x0002 },
2269                 { 0x0c, 0x7eb8 },
2270                 { 0x06, 0x0761 },
2271                 { 0x1f, 0x0003 },
2272                 { 0x16, 0x0f0a },
2273                 { 0x1f, 0x0000 }
2274         };
2275
2276         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2277
2278         rtl_patchphy(tp, 0x16, 1 << 0);
2279         rtl_patchphy(tp, 0x14, 1 << 5);
2280         rtl_patchphy(tp, 0x0d, 1 << 5);
2281         rtl_writephy(tp, 0x1f, 0x0000);
2282 }
2283
2284 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2285 {
2286         static const struct phy_reg phy_reg_init[] = {
2287                 { 0x1f, 0x0001 },
2288                 { 0x12, 0x2300 },
2289                 { 0x1d, 0x3d98 },
2290                 { 0x1f, 0x0002 },
2291                 { 0x0c, 0x7eb8 },
2292                 { 0x06, 0x5461 },
2293                 { 0x1f, 0x0003 },
2294                 { 0x16, 0x0f0a },
2295                 { 0x1f, 0x0000 }
2296         };
2297
2298         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2299
2300         rtl_patchphy(tp, 0x16, 1 << 0);
2301         rtl_patchphy(tp, 0x14, 1 << 5);
2302         rtl_patchphy(tp, 0x0d, 1 << 5);
2303         rtl_writephy(tp, 0x1f, 0x0000);
2304 }
2305
2306 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2307 {
2308         rtl8168c_3_hw_phy_config(tp);
2309 }
2310
2311 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2312 {
2313         static const struct phy_reg phy_reg_init_0[] = {
2314                 /* Channel Estimation */
2315                 { 0x1f, 0x0001 },
2316                 { 0x06, 0x4064 },
2317                 { 0x07, 0x2863 },
2318                 { 0x08, 0x059c },
2319                 { 0x09, 0x26b4 },
2320                 { 0x0a, 0x6a19 },
2321                 { 0x0b, 0xdcc8 },
2322                 { 0x10, 0xf06d },
2323                 { 0x14, 0x7f68 },
2324                 { 0x18, 0x7fd9 },
2325                 { 0x1c, 0xf0ff },
2326                 { 0x1d, 0x3d9c },
2327                 { 0x1f, 0x0003 },
2328                 { 0x12, 0xf49f },
2329                 { 0x13, 0x070b },
2330                 { 0x1a, 0x05ad },
2331                 { 0x14, 0x94c0 },
2332
2333                 /*
2334                  * Tx Error Issue
2335                  * Enhance line driver power
2336                  */
2337                 { 0x1f, 0x0002 },
2338                 { 0x06, 0x5561 },
2339                 { 0x1f, 0x0005 },
2340                 { 0x05, 0x8332 },
2341                 { 0x06, 0x5561 },
2342
2343                 /*
2344                  * Can not link to 1Gbps with bad cable
2345                  * Decrease SNR threshold form 21.07dB to 19.04dB
2346                  */
2347                 { 0x1f, 0x0001 },
2348                 { 0x17, 0x0cc0 },
2349
2350                 { 0x1f, 0x0000 },
2351                 { 0x0d, 0xf880 }
2352         };
2353         void __iomem *ioaddr = tp->mmio_addr;
2354
2355         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2356
2357         /*
2358          * Rx Error Issue
2359          * Fine Tune Switching regulator parameter
2360          */
2361         rtl_writephy(tp, 0x1f, 0x0002);
2362         rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2363         rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2364
2365         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2366                 static const struct phy_reg phy_reg_init[] = {
2367                         { 0x1f, 0x0002 },
2368                         { 0x05, 0x669a },
2369                         { 0x1f, 0x0005 },
2370                         { 0x05, 0x8330 },
2371                         { 0x06, 0x669a },
2372                         { 0x1f, 0x0002 }
2373                 };
2374                 int val;
2375
2376                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2377
2378                 val = rtl_readphy(tp, 0x0d);
2379
2380                 if ((val & 0x00ff) != 0x006c) {
2381                         static const u32 set[] = {
2382                                 0x0065, 0x0066, 0x0067, 0x0068,
2383                                 0x0069, 0x006a, 0x006b, 0x006c
2384                         };
2385                         int i;
2386
2387                         rtl_writephy(tp, 0x1f, 0x0002);
2388
2389                         val &= 0xff00;
2390                         for (i = 0; i < ARRAY_SIZE(set); i++)
2391                                 rtl_writephy(tp, 0x0d, val | set[i]);
2392                 }
2393         } else {
2394                 static const struct phy_reg phy_reg_init[] = {
2395                         { 0x1f, 0x0002 },
2396                         { 0x05, 0x6662 },
2397                         { 0x1f, 0x0005 },
2398                         { 0x05, 0x8330 },
2399                         { 0x06, 0x6662 }
2400                 };
2401
2402                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2403         }
2404
2405         /* RSET couple improve */
2406         rtl_writephy(tp, 0x1f, 0x0002);
2407         rtl_patchphy(tp, 0x0d, 0x0300);
2408         rtl_patchphy(tp, 0x0f, 0x0010);
2409
2410         /* Fine tune PLL performance */
2411         rtl_writephy(tp, 0x1f, 0x0002);
2412         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2413         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2414
2415         rtl_writephy(tp, 0x1f, 0x0005);
2416         rtl_writephy(tp, 0x05, 0x001b);
2417
2418         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2419
2420         rtl_writephy(tp, 0x1f, 0x0000);
2421 }
2422
2423 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2424 {
2425         static const struct phy_reg phy_reg_init_0[] = {
2426                 /* Channel Estimation */
2427                 { 0x1f, 0x0001 },
2428                 { 0x06, 0x4064 },
2429                 { 0x07, 0x2863 },
2430                 { 0x08, 0x059c },
2431                 { 0x09, 0x26b4 },
2432                 { 0x0a, 0x6a19 },
2433                 { 0x0b, 0xdcc8 },
2434                 { 0x10, 0xf06d },
2435                 { 0x14, 0x7f68 },
2436                 { 0x18, 0x7fd9 },
2437                 { 0x1c, 0xf0ff },
2438                 { 0x1d, 0x3d9c },
2439                 { 0x1f, 0x0003 },
2440                 { 0x12, 0xf49f },
2441                 { 0x13, 0x070b },
2442                 { 0x1a, 0x05ad },
2443                 { 0x14, 0x94c0 },
2444
2445                 /*
2446                  * Tx Error Issue
2447                  * Enhance line driver power
2448                  */
2449                 { 0x1f, 0x0002 },
2450                 { 0x06, 0x5561 },
2451                 { 0x1f, 0x0005 },
2452                 { 0x05, 0x8332 },
2453                 { 0x06, 0x5561 },
2454
2455                 /*
2456                  * Can not link to 1Gbps with bad cable
2457                  * Decrease SNR threshold form 21.07dB to 19.04dB
2458                  */
2459                 { 0x1f, 0x0001 },
2460                 { 0x17, 0x0cc0 },
2461
2462                 { 0x1f, 0x0000 },
2463                 { 0x0d, 0xf880 }
2464         };
2465         void __iomem *ioaddr = tp->mmio_addr;
2466
2467         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2468
2469         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2470                 static const struct phy_reg phy_reg_init[] = {
2471                         { 0x1f, 0x0002 },
2472                         { 0x05, 0x669a },
2473                         { 0x1f, 0x0005 },
2474                         { 0x05, 0x8330 },
2475                         { 0x06, 0x669a },
2476
2477                         { 0x1f, 0x0002 }
2478                 };
2479                 int val;
2480
2481                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2482
2483                 val = rtl_readphy(tp, 0x0d);
2484                 if ((val & 0x00ff) != 0x006c) {
2485                         static const u32 set[] = {
2486                                 0x0065, 0x0066, 0x0067, 0x0068,
2487                                 0x0069, 0x006a, 0x006b, 0x006c
2488                         };
2489                         int i;
2490
2491                         rtl_writephy(tp, 0x1f, 0x0002);
2492
2493                         val &= 0xff00;
2494                         for (i = 0; i < ARRAY_SIZE(set); i++)
2495                                 rtl_writephy(tp, 0x0d, val | set[i]);
2496                 }
2497         } else {
2498                 static const struct phy_reg phy_reg_init[] = {
2499                         { 0x1f, 0x0002 },
2500                         { 0x05, 0x2642 },
2501                         { 0x1f, 0x0005 },
2502                         { 0x05, 0x8330 },
2503                         { 0x06, 0x2642 }
2504                 };
2505
2506                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2507         }
2508
2509         /* Fine tune PLL performance */
2510         rtl_writephy(tp, 0x1f, 0x0002);
2511         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2512         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2513
2514         /* Switching regulator Slew rate */
2515         rtl_writephy(tp, 0x1f, 0x0002);
2516         rtl_patchphy(tp, 0x0f, 0x0017);
2517
2518         rtl_writephy(tp, 0x1f, 0x0005);
2519         rtl_writephy(tp, 0x05, 0x001b);
2520
2521         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2522
2523         rtl_writephy(tp, 0x1f, 0x0000);
2524 }
2525
2526 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2527 {
2528         static const struct phy_reg phy_reg_init[] = {
2529                 { 0x1f, 0x0002 },
2530                 { 0x10, 0x0008 },
2531                 { 0x0d, 0x006c },
2532
2533                 { 0x1f, 0x0000 },
2534                 { 0x0d, 0xf880 },
2535
2536                 { 0x1f, 0x0001 },
2537                 { 0x17, 0x0cc0 },
2538
2539                 { 0x1f, 0x0001 },
2540                 { 0x0b, 0xa4d8 },
2541                 { 0x09, 0x281c },
2542                 { 0x07, 0x2883 },
2543                 { 0x0a, 0x6b35 },
2544                 { 0x1d, 0x3da4 },
2545                 { 0x1c, 0xeffd },
2546                 { 0x14, 0x7f52 },
2547                 { 0x18, 0x7fc6 },
2548                 { 0x08, 0x0601 },
2549                 { 0x06, 0x4063 },
2550                 { 0x10, 0xf074 },
2551                 { 0x1f, 0x0003 },
2552                 { 0x13, 0x0789 },
2553                 { 0x12, 0xf4bd },
2554                 { 0x1a, 0x04fd },
2555                 { 0x14, 0x84b0 },
2556                 { 0x1f, 0x0000 },
2557                 { 0x00, 0x9200 },
2558
2559                 { 0x1f, 0x0005 },
2560                 { 0x01, 0x0340 },
2561                 { 0x1f, 0x0001 },
2562                 { 0x04, 0x4000 },
2563                 { 0x03, 0x1d21 },
2564                 { 0x02, 0x0c32 },
2565                 { 0x01, 0x0200 },
2566                 { 0x00, 0x5554 },
2567                 { 0x04, 0x4800 },
2568                 { 0x04, 0x4000 },
2569                 { 0x04, 0xf000 },
2570                 { 0x03, 0xdf01 },
2571                 { 0x02, 0xdf20 },
2572                 { 0x01, 0x101a },
2573                 { 0x00, 0xa0ff },
2574                 { 0x04, 0xf800 },
2575                 { 0x04, 0xf000 },
2576                 { 0x1f, 0x0000 },
2577
2578                 { 0x1f, 0x0007 },
2579                 { 0x1e, 0x0023 },
2580                 { 0x16, 0x0000 },
2581                 { 0x1f, 0x0000 }
2582         };
2583
2584         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2585 }
2586
2587 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2588 {
2589         static const struct phy_reg phy_reg_init[] = {
2590                 { 0x1f, 0x0001 },
2591                 { 0x17, 0x0cc0 },
2592
2593                 { 0x1f, 0x0007 },
2594                 { 0x1e, 0x002d },
2595                 { 0x18, 0x0040 },
2596                 { 0x1f, 0x0000 }
2597         };
2598
2599         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2600         rtl_patchphy(tp, 0x0d, 1 << 5);
2601 }
2602
2603 static void rtl8168e_hw_phy_config(struct rtl8169_private *tp)
2604 {
2605         static const struct phy_reg phy_reg_init[] = {
2606                 /* Enable Delay cap */
2607                 { 0x1f, 0x0005 },
2608                 { 0x05, 0x8b80 },
2609                 { 0x06, 0xc896 },
2610                 { 0x1f, 0x0000 },
2611
2612                 /* Channel estimation fine tune */
2613                 { 0x1f, 0x0001 },
2614                 { 0x0b, 0x6c20 },
2615                 { 0x07, 0x2872 },
2616                 { 0x1c, 0xefff },
2617                 { 0x1f, 0x0003 },
2618                 { 0x14, 0x6420 },
2619                 { 0x1f, 0x0000 },
2620
2621                 /* Update PFM & 10M TX idle timer */
2622                 { 0x1f, 0x0007 },
2623                 { 0x1e, 0x002f },
2624                 { 0x15, 0x1919 },
2625                 { 0x1f, 0x0000 },
2626
2627                 { 0x1f, 0x0007 },
2628                 { 0x1e, 0x00ac },
2629                 { 0x18, 0x0006 },
2630                 { 0x1f, 0x0000 }
2631         };
2632
2633         rtl_apply_firmware(tp);
2634
2635         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2636
2637         /* DCO enable for 10M IDLE Power */
2638         rtl_writephy(tp, 0x1f, 0x0007);
2639         rtl_writephy(tp, 0x1e, 0x0023);
2640         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2641         rtl_writephy(tp, 0x1f, 0x0000);
2642
2643         /* For impedance matching */
2644         rtl_writephy(tp, 0x1f, 0x0002);
2645         rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
2646         rtl_writephy(tp, 0x1f, 0x0000);
2647
2648         /* PHY auto speed down */
2649         rtl_writephy(tp, 0x1f, 0x0007);
2650         rtl_writephy(tp, 0x1e, 0x002d);
2651         rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2652         rtl_writephy(tp, 0x1f, 0x0000);
2653         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2654
2655         rtl_writephy(tp, 0x1f, 0x0005);
2656         rtl_writephy(tp, 0x05, 0x8b86);
2657         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2658         rtl_writephy(tp, 0x1f, 0x0000);
2659
2660         rtl_writephy(tp, 0x1f, 0x0005);
2661         rtl_writephy(tp, 0x05, 0x8b85);
2662         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2663         rtl_writephy(tp, 0x1f, 0x0007);
2664         rtl_writephy(tp, 0x1e, 0x0020);
2665         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2666         rtl_writephy(tp, 0x1f, 0x0006);
2667         rtl_writephy(tp, 0x00, 0x5a00);
2668         rtl_writephy(tp, 0x1f, 0x0000);
2669         rtl_writephy(tp, 0x0d, 0x0007);
2670         rtl_writephy(tp, 0x0e, 0x003c);
2671         rtl_writephy(tp, 0x0d, 0x4007);
2672         rtl_writephy(tp, 0x0e, 0x0000);
2673         rtl_writephy(tp, 0x0d, 0x0000);
2674 }
2675
2676 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2677 {
2678         static const struct phy_reg phy_reg_init[] = {
2679                 { 0x1f, 0x0003 },
2680                 { 0x08, 0x441d },
2681                 { 0x01, 0x9100 },
2682                 { 0x1f, 0x0000 }
2683         };
2684
2685         rtl_writephy(tp, 0x1f, 0x0000);
2686         rtl_patchphy(tp, 0x11, 1 << 12);
2687         rtl_patchphy(tp, 0x19, 1 << 13);
2688         rtl_patchphy(tp, 0x10, 1 << 15);
2689
2690         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2691 }
2692
2693 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
2694 {
2695         static const struct phy_reg phy_reg_init[] = {
2696                 { 0x1f, 0x0005 },
2697                 { 0x1a, 0x0000 },
2698                 { 0x1f, 0x0000 },
2699
2700                 { 0x1f, 0x0004 },
2701                 { 0x1c, 0x0000 },
2702                 { 0x1f, 0x0000 },
2703
2704                 { 0x1f, 0x0001 },
2705                 { 0x15, 0x7701 },
2706                 { 0x1f, 0x0000 }
2707         };
2708
2709         /* Disable ALDPS before ram code */
2710         rtl_writephy(tp, 0x1f, 0x0000);
2711         rtl_writephy(tp, 0x18, 0x0310);
2712         msleep(100);
2713
2714         rtl_apply_firmware(tp);
2715
2716         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2717 }
2718
2719 static void rtl_hw_phy_config(struct net_device *dev)
2720 {
2721         struct rtl8169_private *tp = netdev_priv(dev);
2722
2723         rtl8169_print_mac_version(tp);
2724
2725         switch (tp->mac_version) {
2726         case RTL_GIGA_MAC_VER_01:
2727                 break;
2728         case RTL_GIGA_MAC_VER_02:
2729         case RTL_GIGA_MAC_VER_03:
2730                 rtl8169s_hw_phy_config(tp);
2731                 break;
2732         case RTL_GIGA_MAC_VER_04:
2733                 rtl8169sb_hw_phy_config(tp);
2734                 break;
2735         case RTL_GIGA_MAC_VER_05:
2736                 rtl8169scd_hw_phy_config(tp);
2737                 break;
2738         case RTL_GIGA_MAC_VER_06:
2739                 rtl8169sce_hw_phy_config(tp);
2740                 break;
2741         case RTL_GIGA_MAC_VER_07:
2742         case RTL_GIGA_MAC_VER_08:
2743         case RTL_GIGA_MAC_VER_09:
2744                 rtl8102e_hw_phy_config(tp);
2745                 break;
2746         case RTL_GIGA_MAC_VER_11:
2747                 rtl8168bb_hw_phy_config(tp);
2748                 break;
2749         case RTL_GIGA_MAC_VER_12:
2750                 rtl8168bef_hw_phy_config(tp);
2751                 break;
2752         case RTL_GIGA_MAC_VER_17:
2753                 rtl8168bef_hw_phy_config(tp);
2754                 break;
2755         case RTL_GIGA_MAC_VER_18:
2756                 rtl8168cp_1_hw_phy_config(tp);
2757                 break;
2758         case RTL_GIGA_MAC_VER_19:
2759                 rtl8168c_1_hw_phy_config(tp);
2760                 break;
2761         case RTL_GIGA_MAC_VER_20:
2762                 rtl8168c_2_hw_phy_config(tp);
2763                 break;
2764         case RTL_GIGA_MAC_VER_21:
2765                 rtl8168c_3_hw_phy_config(tp);
2766                 break;
2767         case RTL_GIGA_MAC_VER_22:
2768                 rtl8168c_4_hw_phy_config(tp);
2769                 break;
2770         case RTL_GIGA_MAC_VER_23:
2771         case RTL_GIGA_MAC_VER_24:
2772                 rtl8168cp_2_hw_phy_config(tp);
2773                 break;
2774         case RTL_GIGA_MAC_VER_25:
2775                 rtl8168d_1_hw_phy_config(tp);
2776                 break;
2777         case RTL_GIGA_MAC_VER_26:
2778                 rtl8168d_2_hw_phy_config(tp);
2779                 break;
2780         case RTL_GIGA_MAC_VER_27:
2781                 rtl8168d_3_hw_phy_config(tp);
2782                 break;
2783         case RTL_GIGA_MAC_VER_28:
2784                 rtl8168d_4_hw_phy_config(tp);
2785                 break;
2786         case RTL_GIGA_MAC_VER_29:
2787         case RTL_GIGA_MAC_VER_30:
2788                 rtl8105e_hw_phy_config(tp);
2789                 break;
2790         case RTL_GIGA_MAC_VER_31:
2791                 /* None. */
2792                 break;
2793         case RTL_GIGA_MAC_VER_32:
2794         case RTL_GIGA_MAC_VER_33:
2795                 rtl8168e_hw_phy_config(tp);
2796                 break;
2797
2798         default:
2799                 break;
2800         }
2801 }
2802
2803 static void rtl8169_phy_timer(unsigned long __opaque)
2804 {
2805         struct net_device *dev = (struct net_device *)__opaque;
2806         struct rtl8169_private *tp = netdev_priv(dev);
2807         struct timer_list *timer = &tp->timer;
2808         void __iomem *ioaddr = tp->mmio_addr;
2809         unsigned long timeout = RTL8169_PHY_TIMEOUT;
2810
2811         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
2812
2813         spin_lock_irq(&tp->lock);
2814
2815         if (tp->phy_reset_pending(tp)) {
2816                 /*
2817                  * A busy loop could burn quite a few cycles on nowadays CPU.
2818                  * Let's delay the execution of the timer for a few ticks.
2819                  */
2820                 timeout = HZ/10;
2821                 goto out_mod_timer;
2822         }
2823
2824         if (tp->link_ok(ioaddr))
2825                 goto out_unlock;
2826
2827         netif_warn(tp, link, dev, "PHY reset until link up\n");
2828
2829         tp->phy_reset_enable(tp);
2830
2831 out_mod_timer:
2832         mod_timer(timer, jiffies + timeout);
2833 out_unlock:
2834         spin_unlock_irq(&tp->lock);
2835 }
2836
2837 #ifdef CONFIG_NET_POLL_CONTROLLER
2838 /*
2839  * Polling 'interrupt' - used by things like netconsole to send skbs
2840  * without having to re-enable interrupts. It's not called while
2841  * the interrupt routine is executing.
2842  */
2843 static void rtl8169_netpoll(struct net_device *dev)
2844 {
2845         struct rtl8169_private *tp = netdev_priv(dev);
2846         struct pci_dev *pdev = tp->pci_dev;
2847
2848         disable_irq(pdev->irq);
2849         rtl8169_interrupt(pdev->irq, dev);
2850         enable_irq(pdev->irq);
2851 }
2852 #endif
2853
2854 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
2855                                   void __iomem *ioaddr)
2856 {
2857         iounmap(ioaddr);
2858         pci_release_regions(pdev);
2859         pci_clear_mwi(pdev);
2860         pci_disable_device(pdev);
2861         free_netdev(dev);
2862 }
2863
2864 static void rtl8169_phy_reset(struct net_device *dev,
2865                               struct rtl8169_private *tp)
2866 {
2867         unsigned int i;
2868
2869         tp->phy_reset_enable(tp);
2870         for (i = 0; i < 100; i++) {
2871                 if (!tp->phy_reset_pending(tp))
2872                         return;
2873                 msleep(1);
2874         }
2875         netif_err(tp, link, dev, "PHY reset failed\n");
2876 }
2877
2878 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
2879 {
2880         void __iomem *ioaddr = tp->mmio_addr;
2881
2882         rtl_hw_phy_config(dev);
2883
2884         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2885                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2886                 RTL_W8(0x82, 0x01);
2887         }
2888
2889         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2890
2891         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
2892                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
2893
2894         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
2895                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2896                 RTL_W8(0x82, 0x01);
2897                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
2898                 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
2899         }
2900
2901         rtl8169_phy_reset(dev, tp);
2902
2903         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
2904                           ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
2905                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
2906                           (tp->mii.supports_gmii ?
2907                            ADVERTISED_1000baseT_Half |
2908                            ADVERTISED_1000baseT_Full : 0));
2909
2910         if (RTL_R8(PHYstatus) & TBI_Enable)
2911                 netif_info(tp, link, dev, "TBI auto-negotiating\n");
2912 }
2913
2914 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2915 {
2916         void __iomem *ioaddr = tp->mmio_addr;
2917         u32 high;
2918         u32 low;
2919
2920         low  = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
2921         high = addr[4] | (addr[5] << 8);
2922
2923         spin_lock_irq(&tp->lock);
2924
2925         RTL_W8(Cfg9346, Cfg9346_Unlock);
2926
2927         RTL_W32(MAC4, high);
2928         RTL_R32(MAC4);
2929
2930         RTL_W32(MAC0, low);
2931         RTL_R32(MAC0);
2932
2933         RTL_W8(Cfg9346, Cfg9346_Lock);
2934
2935         spin_unlock_irq(&tp->lock);
2936 }
2937
2938 static int rtl_set_mac_address(struct net_device *dev, void *p)
2939 {
2940         struct rtl8169_private *tp = netdev_priv(dev);
2941         struct sockaddr *addr = p;
2942
2943         if (!is_valid_ether_addr(addr->sa_data))
2944                 return -EADDRNOTAVAIL;
2945
2946         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2947
2948         rtl_rar_set(tp, dev->dev_addr);
2949
2950         return 0;
2951 }
2952
2953 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2954 {
2955         struct rtl8169_private *tp = netdev_priv(dev);
2956         struct mii_ioctl_data *data = if_mii(ifr);
2957
2958         return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
2959 }
2960
2961 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
2962                           struct mii_ioctl_data *data, int cmd)
2963 {
2964         switch (cmd) {
2965         case SIOCGMIIPHY:
2966                 data->phy_id = 32; /* Internal PHY */
2967                 return 0;
2968
2969         case SIOCGMIIREG:
2970                 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
2971                 return 0;
2972
2973         case SIOCSMIIREG:
2974                 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
2975                 return 0;
2976         }
2977         return -EOPNOTSUPP;
2978 }
2979
2980 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2981 {
2982         return -EOPNOTSUPP;
2983 }
2984
2985 static const struct rtl_cfg_info {
2986         void (*hw_start)(struct net_device *);
2987         unsigned int region;
2988         unsigned int align;
2989         u16 intr_event;
2990         u16 napi_event;
2991         unsigned features;
2992         u8 default_ver;
2993 } rtl_cfg_infos [] = {
2994         [RTL_CFG_0] = {
2995                 .hw_start       = rtl_hw_start_8169,
2996                 .region         = 1,
2997                 .align          = 0,
2998                 .intr_event     = SYSErr | LinkChg | RxOverflow |
2999                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
3000                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
3001                 .features       = RTL_FEATURE_GMII,
3002                 .default_ver    = RTL_GIGA_MAC_VER_01,
3003         },
3004         [RTL_CFG_1] = {
3005                 .hw_start       = rtl_hw_start_8168,
3006                 .region         = 2,
3007                 .align          = 8,
3008                 .intr_event     = SYSErr | LinkChg | RxOverflow |
3009                                   TxErr | TxOK | RxOK | RxErr,
3010                 .napi_event     = TxErr | TxOK | RxOK | RxOverflow,
3011                 .features       = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
3012                 .default_ver    = RTL_GIGA_MAC_VER_11,
3013         },
3014         [RTL_CFG_2] = {
3015                 .hw_start       = rtl_hw_start_8101,
3016                 .region         = 2,
3017                 .align          = 8,
3018                 .intr_event     = SYSErr | LinkChg | RxOverflow | PCSTimeout |
3019                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
3020                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
3021                 .features       = RTL_FEATURE_MSI,
3022                 .default_ver    = RTL_GIGA_MAC_VER_13,
3023         }
3024 };
3025
3026 /* Cfg9346_Unlock assumed. */
3027 static unsigned rtl_try_msi(struct rtl8169_private *tp,
3028                             const struct rtl_cfg_info *cfg)
3029 {
3030         void __iomem *ioaddr = tp->mmio_addr;
3031         unsigned msi = 0;
3032         u8 cfg2;
3033
3034         cfg2 = RTL_R8(Config2) & ~MSIEnable;
3035         if (cfg->features & RTL_FEATURE_MSI) {
3036                 if (pci_enable_msi(tp->pci_dev)) {
3037                         netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
3038                 } else {
3039                         cfg2 |= MSIEnable;
3040                         msi = RTL_FEATURE_MSI;
3041                 }
3042         }
3043         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3044                 RTL_W8(Config2, cfg2);
3045         return msi;
3046 }
3047
3048 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3049 {
3050         if (tp->features & RTL_FEATURE_MSI) {
3051                 pci_disable_msi(pdev);
3052                 tp->features &= ~RTL_FEATURE_MSI;
3053         }
3054 }
3055
3056 static const struct net_device_ops rtl8169_netdev_ops = {
3057         .ndo_open               = rtl8169_open,
3058         .ndo_stop               = rtl8169_close,
3059         .ndo_get_stats          = rtl8169_get_stats,
3060         .ndo_start_xmit         = rtl8169_start_xmit,
3061         .ndo_tx_timeout         = rtl8169_tx_timeout,
3062         .ndo_validate_addr      = eth_validate_addr,
3063         .ndo_change_mtu         = rtl8169_change_mtu,
3064         .ndo_fix_features       = rtl8169_fix_features,
3065         .ndo_set_features       = rtl8169_set_features,
3066         .ndo_set_mac_address    = rtl_set_mac_address,
3067         .ndo_do_ioctl           = rtl8169_ioctl,
3068         .ndo_set_multicast_list = rtl_set_rx_mode,
3069 #ifdef CONFIG_NET_POLL_CONTROLLER
3070         .ndo_poll_controller    = rtl8169_netpoll,
3071 #endif
3072
3073 };
3074
3075 static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
3076 {
3077         struct mdio_ops *ops = &tp->mdio_ops;
3078
3079         switch (tp->mac_version) {
3080         case RTL_GIGA_MAC_VER_27:
3081                 ops->write      = r8168dp_1_mdio_write;
3082                 ops->read       = r8168dp_1_mdio_read;
3083                 break;
3084         case RTL_GIGA_MAC_VER_28:
3085         case RTL_GIGA_MAC_VER_31:
3086                 ops->write      = r8168dp_2_mdio_write;
3087                 ops->read       = r8168dp_2_mdio_read;
3088                 break;
3089         default:
3090                 ops->write      = r8169_mdio_write;
3091                 ops->read       = r8169_mdio_read;
3092                 break;
3093         }
3094 }
3095
3096 static void r810x_phy_power_down(struct rtl8169_private *tp)
3097 {
3098         rtl_writephy(tp, 0x1f, 0x0000);
3099         rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3100 }
3101
3102 static void r810x_phy_power_up(struct rtl8169_private *tp)
3103 {
3104         rtl_writephy(tp, 0x1f, 0x0000);
3105         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3106 }
3107
3108 static void r810x_pll_power_down(struct rtl8169_private *tp)
3109 {
3110         if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3111                 rtl_writephy(tp, 0x1f, 0x0000);
3112                 rtl_writephy(tp, MII_BMCR, 0x0000);
3113                 return;
3114         }
3115
3116         r810x_phy_power_down(tp);
3117 }
3118
3119 static void r810x_pll_power_up(struct rtl8169_private *tp)
3120 {
3121         r810x_phy_power_up(tp);
3122 }
3123
3124 static void r8168_phy_power_up(struct rtl8169_private *tp)
3125 {
3126         rtl_writephy(tp, 0x1f, 0x0000);
3127         switch (tp->mac_version) {
3128         case RTL_GIGA_MAC_VER_11:
3129         case RTL_GIGA_MAC_VER_12:
3130         case RTL_GIGA_MAC_VER_17:
3131         case RTL_GIGA_MAC_VER_18:
3132         case RTL_GIGA_MAC_VER_19:
3133         case RTL_GIGA_MAC_VER_20:
3134         case RTL_GIGA_MAC_VER_21:
3135         case RTL_GIGA_MAC_VER_22:
3136         case RTL_GIGA_MAC_VER_23:
3137         case RTL_GIGA_MAC_VER_24:
3138         case RTL_GIGA_MAC_VER_25:
3139         case RTL_GIGA_MAC_VER_26:
3140         case RTL_GIGA_MAC_VER_27:
3141         case RTL_GIGA_MAC_VER_28:
3142         case RTL_GIGA_MAC_VER_31:
3143                 rtl_writephy(tp, 0x0e, 0x0000);
3144                 break;
3145         default:
3146                 break;
3147         }
3148         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3149 }
3150
3151 static void r8168_phy_power_down(struct rtl8169_private *tp)
3152 {
3153         rtl_writephy(tp, 0x1f, 0x0000);
3154         switch (tp->mac_version) {
3155         case RTL_GIGA_MAC_VER_32:
3156         case RTL_GIGA_MAC_VER_33:
3157                 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3158                 break;
3159
3160         case RTL_GIGA_MAC_VER_11:
3161         case RTL_GIGA_MAC_VER_12:
3162         case RTL_GIGA_MAC_VER_17:
3163         case RTL_GIGA_MAC_VER_18:
3164         case RTL_GIGA_MAC_VER_19:
3165         case RTL_GIGA_MAC_VER_20:
3166         case RTL_GIGA_MAC_VER_21:
3167         case RTL_GIGA_MAC_VER_22:
3168         case RTL_GIGA_MAC_VER_23:
3169         case RTL_GIGA_MAC_VER_24:
3170         case RTL_GIGA_MAC_VER_25:
3171         case RTL_GIGA_MAC_VER_26:
3172         case RTL_GIGA_MAC_VER_27:
3173         case RTL_GIGA_MAC_VER_28:
3174         case RTL_GIGA_MAC_VER_31:
3175                 rtl_writephy(tp, 0x0e, 0x0200);
3176         default:
3177                 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3178                 break;
3179         }
3180 }
3181
3182 static void r8168_pll_power_down(struct rtl8169_private *tp)
3183 {
3184         void __iomem *ioaddr = tp->mmio_addr;
3185
3186         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3187              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3188              tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3189             r8168dp_check_dash(tp)) {
3190                 return;
3191         }
3192
3193         if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
3194              tp->mac_version == RTL_GIGA_MAC_VER_24) &&
3195             (RTL_R16(CPlusCmd) & ASF)) {
3196                 return;
3197         }
3198
3199         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3200             tp->mac_version == RTL_GIGA_MAC_VER_33)
3201                 rtl_ephy_write(ioaddr, 0x19, 0xff64);
3202
3203         if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3204                 rtl_writephy(tp, 0x1f, 0x0000);
3205                 rtl_writephy(tp, MII_BMCR, 0x0000);
3206
3207                 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3208                     tp->mac_version == RTL_GIGA_MAC_VER_33)
3209                         RTL_W32(RxConfig, RTL_R32(RxConfig) | AcceptBroadcast |
3210                                 AcceptMulticast | AcceptMyPhys);
3211                 return;
3212         }
3213
3214         r8168_phy_power_down(tp);
3215
3216         switch (tp->mac_version) {
3217         case RTL_GIGA_MAC_VER_25:
3218         case RTL_GIGA_MAC_VER_26:
3219         case RTL_GIGA_MAC_VER_27:
3220         case RTL_GIGA_MAC_VER_28:
3221         case RTL_GIGA_MAC_VER_31:
3222         case RTL_GIGA_MAC_VER_32:
3223         case RTL_GIGA_MAC_VER_33:
3224                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3225                 break;
3226         }
3227 }
3228
3229 static void r8168_pll_power_up(struct rtl8169_private *tp)
3230 {
3231         void __iomem *ioaddr = tp->mmio_addr;
3232
3233         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3234              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3235              tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3236             r8168dp_check_dash(tp)) {
3237                 return;
3238         }
3239
3240         switch (tp->mac_version) {
3241         case RTL_GIGA_MAC_VER_25:
3242         case RTL_GIGA_MAC_VER_26:
3243         case RTL_GIGA_MAC_VER_27:
3244         case RTL_GIGA_MAC_VER_28:
3245         case RTL_GIGA_MAC_VER_31:
3246         case RTL_GIGA_MAC_VER_32:
3247         case RTL_GIGA_MAC_VER_33:
3248                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3249                 break;
3250         }
3251
3252         r8168_phy_power_up(tp);
3253 }
3254
3255 static void rtl_generic_op(struct rtl8169_private *tp,
3256                            void (*op)(struct rtl8169_private *))
3257 {
3258         if (op)
3259                 op(tp);
3260 }
3261
3262 static void rtl_pll_power_down(struct rtl8169_private *tp)
3263 {
3264         rtl_generic_op(tp, tp->pll_power_ops.down);
3265 }
3266
3267 static void rtl_pll_power_up(struct rtl8169_private *tp)
3268 {
3269         rtl_generic_op(tp, tp->pll_power_ops.up);
3270 }
3271
3272 static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3273 {
3274         struct pll_power_ops *ops = &tp->pll_power_ops;
3275
3276         switch (tp->mac_version) {
3277         case RTL_GIGA_MAC_VER_07:
3278         case RTL_GIGA_MAC_VER_08:
3279         case RTL_GIGA_MAC_VER_09:
3280         case RTL_GIGA_MAC_VER_10:
3281         case RTL_GIGA_MAC_VER_16:
3282         case RTL_GIGA_MAC_VER_29:
3283         case RTL_GIGA_MAC_VER_30:
3284                 ops->down       = r810x_pll_power_down;
3285                 ops->up         = r810x_pll_power_up;
3286                 break;
3287
3288         case RTL_GIGA_MAC_VER_11:
3289         case RTL_GIGA_MAC_VER_12:
3290         case RTL_GIGA_MAC_VER_17:
3291         case RTL_GIGA_MAC_VER_18:
3292         case RTL_GIGA_MAC_VER_19:
3293         case RTL_GIGA_MAC_VER_20:
3294         case RTL_GIGA_MAC_VER_21:
3295         case RTL_GIGA_MAC_VER_22:
3296         case RTL_GIGA_MAC_VER_23:
3297         case RTL_GIGA_MAC_VER_24:
3298         case RTL_GIGA_MAC_VER_25:
3299         case RTL_GIGA_MAC_VER_26:
3300         case RTL_GIGA_MAC_VER_27:
3301         case RTL_GIGA_MAC_VER_28:
3302         case RTL_GIGA_MAC_VER_31:
3303         case RTL_GIGA_MAC_VER_32:
3304         case RTL_GIGA_MAC_VER_33:
3305                 ops->down       = r8168_pll_power_down;
3306                 ops->up         = r8168_pll_power_up;
3307                 break;
3308
3309         default:
3310                 ops->down       = NULL;
3311                 ops->up         = NULL;
3312                 break;
3313         }
3314 }
3315
3316 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
3317 {
3318         rtl_generic_op(tp, tp->jumbo_ops.enable);
3319 }
3320
3321 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
3322 {
3323         rtl_generic_op(tp, tp->jumbo_ops.disable);
3324 }
3325
3326 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
3327 {
3328         void __iomem *ioaddr = tp->mmio_addr;
3329
3330         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3331         RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
3332         rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
3333 }
3334
3335 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
3336 {
3337         void __iomem *ioaddr = tp->mmio_addr;
3338
3339         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3340         RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
3341         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
3342 }
3343
3344 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
3345 {
3346         void __iomem *ioaddr = tp->mmio_addr;
3347
3348         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3349 }
3350
3351 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
3352 {
3353         void __iomem *ioaddr = tp->mmio_addr;
3354
3355         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3356 }
3357
3358 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
3359 {
3360         void __iomem *ioaddr = tp->mmio_addr;
3361         struct pci_dev *pdev = tp->pci_dev;
3362
3363         RTL_W8(MaxTxPacketSize, 0x3f);
3364         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3365         RTL_W8(Config4, RTL_R8(Config4) | 0x01);
3366         pci_write_config_byte(pdev, 0x79, 0x20);
3367 }
3368
3369 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
3370 {
3371         void __iomem *ioaddr = tp->mmio_addr;
3372         struct pci_dev *pdev = tp->pci_dev;
3373
3374         RTL_W8(MaxTxPacketSize, 0x0c);
3375         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3376         RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
3377         pci_write_config_byte(pdev, 0x79, 0x50);
3378 }
3379
3380 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
3381 {
3382         rtl_tx_performance_tweak(tp->pci_dev,
3383                 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3384 }
3385
3386 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
3387 {
3388         rtl_tx_performance_tweak(tp->pci_dev,
3389                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3390 }
3391
3392 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
3393 {
3394         void __iomem *ioaddr = tp->mmio_addr;
3395
3396         r8168b_0_hw_jumbo_enable(tp);
3397
3398         RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
3399 }
3400
3401 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
3402 {
3403         void __iomem *ioaddr = tp->mmio_addr;
3404
3405         r8168b_0_hw_jumbo_disable(tp);
3406
3407         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
3408 }
3409
3410 static void __devinit rtl_init_jumbo_ops(struct rtl8169_private *tp)
3411 {
3412         struct jumbo_ops *ops = &tp->jumbo_ops;
3413
3414         switch (tp->mac_version) {
3415         case RTL_GIGA_MAC_VER_11:
3416                 ops->disable    = r8168b_0_hw_jumbo_disable;
3417                 ops->enable     = r8168b_0_hw_jumbo_enable;
3418                 break;
3419         case RTL_GIGA_MAC_VER_12:
3420         case RTL_GIGA_MAC_VER_17:
3421                 ops->disable    = r8168b_1_hw_jumbo_disable;
3422                 ops->enable     = r8168b_1_hw_jumbo_enable;
3423                 break;
3424         case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
3425         case RTL_GIGA_MAC_VER_19:
3426         case RTL_GIGA_MAC_VER_20:
3427         case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
3428         case RTL_GIGA_MAC_VER_22:
3429         case RTL_GIGA_MAC_VER_23:
3430         case RTL_GIGA_MAC_VER_24:
3431         case RTL_GIGA_MAC_VER_25:
3432         case RTL_GIGA_MAC_VER_26:
3433                 ops->disable    = r8168c_hw_jumbo_disable;
3434                 ops->enable     = r8168c_hw_jumbo_enable;
3435                 break;
3436         case RTL_GIGA_MAC_VER_27:
3437         case RTL_GIGA_MAC_VER_28:
3438                 ops->disable    = r8168dp_hw_jumbo_disable;
3439                 ops->enable     = r8168dp_hw_jumbo_enable;
3440                 break;
3441         case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
3442         case RTL_GIGA_MAC_VER_32:
3443         case RTL_GIGA_MAC_VER_33:
3444                 ops->disable    = r8168e_hw_jumbo_disable;
3445                 ops->enable     = r8168e_hw_jumbo_enable;
3446                 break;
3447
3448         /*
3449          * No action needed for jumbo frames with 8169.
3450          * No jumbo for 810x at all.
3451          */
3452         default:
3453                 ops->disable    = NULL;
3454                 ops->enable     = NULL;
3455                 break;
3456         }
3457 }
3458
3459 static void rtl_hw_reset(struct rtl8169_private *tp)
3460 {
3461         void __iomem *ioaddr = tp->mmio_addr;
3462         int i;
3463
3464         /* Soft reset the chip. */
3465         RTL_W8(ChipCmd, CmdReset);
3466
3467         /* Check that the chip has finished the reset. */
3468         for (i = 0; i < 100; i++) {
3469                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3470                         break;
3471                 msleep_interruptible(1);
3472         }
3473 }
3474
3475 static int __devinit
3476 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3477 {
3478         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
3479         const unsigned int region = cfg->region;
3480         struct rtl8169_private *tp;
3481         struct mii_if_info *mii;
3482         struct net_device *dev;
3483         void __iomem *ioaddr;
3484         int chipset, i;
3485         int rc;
3486
3487         if (netif_msg_drv(&debug)) {
3488                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
3489                        MODULENAME, RTL8169_VERSION);
3490         }
3491
3492         dev = alloc_etherdev(sizeof (*tp));
3493         if (!dev) {
3494                 if (netif_msg_drv(&debug))
3495                         dev_err(&pdev->dev, "unable to alloc new ethernet\n");
3496                 rc = -ENOMEM;
3497                 goto out;
3498         }
3499
3500         SET_NETDEV_DEV(dev, &pdev->dev);
3501         dev->netdev_ops = &rtl8169_netdev_ops;
3502         tp = netdev_priv(dev);
3503         tp->dev = dev;
3504         tp->pci_dev = pdev;
3505         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
3506
3507         mii = &tp->mii;
3508         mii->dev = dev;
3509         mii->mdio_read = rtl_mdio_read;
3510         mii->mdio_write = rtl_mdio_write;
3511         mii->phy_id_mask = 0x1f;
3512         mii->reg_num_mask = 0x1f;
3513         mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3514
3515         /* disable ASPM completely as that cause random device stop working
3516          * problems as well as full system hangs for some PCIe devices users */
3517         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3518                                      PCIE_LINK_STATE_CLKPM);
3519
3520         /* enable device (incl. PCI PM wakeup and hotplug setup) */
3521         rc = pci_enable_device(pdev);
3522         if (rc < 0) {
3523                 netif_err(tp, probe, dev, "enable failure\n");
3524                 goto err_out_free_dev_1;
3525         }
3526
3527         if (pci_set_mwi(pdev) < 0)
3528                 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
3529
3530         /* make sure PCI base addr 1 is MMIO */
3531         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
3532                 netif_err(tp, probe, dev,
3533                           "region #%d not an MMIO resource, aborting\n",
3534                           region);
3535                 rc = -ENODEV;
3536                 goto err_out_mwi_2;
3537         }
3538
3539         /* check for weird/broken PCI region reporting */
3540         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
3541                 netif_err(tp, probe, dev,
3542                           "Invalid PCI region size(s), aborting\n");
3543                 rc = -ENODEV;
3544                 goto err_out_mwi_2;
3545         }
3546
3547         rc = pci_request_regions(pdev, MODULENAME);
3548         if (rc < 0) {
3549                 netif_err(tp, probe, dev, "could not request regions\n");
3550                 goto err_out_mwi_2;
3551         }
3552
3553         tp->cp_cmd = RxChkSum;
3554
3555         if ((sizeof(dma_addr_t) > 4) &&
3556             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
3557                 tp->cp_cmd |= PCIDAC;
3558                 dev->features |= NETIF_F_HIGHDMA;
3559         } else {
3560                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3561                 if (rc < 0) {
3562                         netif_err(tp, probe, dev, "DMA configuration failed\n");
3563                         goto err_out_free_res_3;
3564                 }
3565         }
3566
3567         /* ioremap MMIO region */
3568         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
3569         if (!ioaddr) {
3570                 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
3571                 rc = -EIO;
3572                 goto err_out_free_res_3;
3573         }
3574         tp->mmio_addr = ioaddr;
3575
3576         tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3577         if (!tp->pcie_cap)
3578                 netif_info(tp, probe, dev, "no PCI Express capability\n");
3579
3580         RTL_W16(IntrMask, 0x0000);
3581
3582         rtl_hw_reset(tp);
3583
3584         RTL_W16(IntrStatus, 0xffff);
3585
3586         pci_set_master(pdev);
3587
3588         /* Identify chip attached to board */
3589         rtl8169_get_mac_version(tp, dev, cfg->default_ver);
3590
3591         /*
3592          * Pretend we are using VLANs; This bypasses a nasty bug where
3593          * Interrupts stop flowing on high load on 8110SCd controllers.
3594          */
3595         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3596                 tp->cp_cmd |= RxVlan;
3597
3598         rtl_init_mdio_ops(tp);
3599         rtl_init_pll_power_ops(tp);
3600         rtl_init_jumbo_ops(tp);
3601
3602         rtl8169_print_mac_version(tp);
3603
3604         chipset = tp->mac_version;
3605         tp->txd_version = rtl_chip_infos[chipset].txd_version;
3606
3607         RTL_W8(Cfg9346, Cfg9346_Unlock);
3608         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3609         RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
3610         if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3611                 tp->features |= RTL_FEATURE_WOL;
3612         if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3613                 tp->features |= RTL_FEATURE_WOL;
3614         tp->features |= rtl_try_msi(tp, cfg);
3615         RTL_W8(Cfg9346, Cfg9346_Lock);
3616
3617         if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3618             (RTL_R8(PHYstatus) & TBI_Enable)) {
3619                 tp->set_speed = rtl8169_set_speed_tbi;
3620                 tp->get_settings = rtl8169_gset_tbi;
3621                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3622                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3623                 tp->link_ok = rtl8169_tbi_link_ok;
3624                 tp->do_ioctl = rtl_tbi_ioctl;
3625         } else {
3626                 tp->set_speed = rtl8169_set_speed_xmii;
3627                 tp->get_settings = rtl8169_gset_xmii;
3628                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3629                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3630                 tp->link_ok = rtl8169_xmii_link_ok;
3631                 tp->do_ioctl = rtl_xmii_ioctl;
3632         }
3633
3634         spin_lock_init(&tp->lock);
3635
3636         /* Get MAC address */
3637         for (i = 0; i < MAC_ADDR_LEN; i++)
3638                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
3639         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3640
3641         SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
3642         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3643         dev->irq = pdev->irq;
3644         dev->base_addr = (unsigned long) ioaddr;
3645
3646         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
3647
3648         /* don't enable SG, IP_CSUM and TSO by default - it might not work
3649          * properly for all devices */
3650         dev->features |= NETIF_F_RXCSUM |
3651                 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3652
3653         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3654                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3655         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3656                 NETIF_F_HIGHDMA;
3657
3658         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3659                 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
3660                 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
3661
3662         tp->intr_mask = 0xffff;
3663         tp->hw_start = cfg->hw_start;
3664         tp->intr_event = cfg->intr_event;
3665         tp->napi_event = cfg->napi_event;
3666
3667         tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
3668                 ~(RxBOVF | RxFOVF) : ~0;
3669
3670         init_timer(&tp->timer);
3671         tp->timer.data = (unsigned long) dev;
3672         tp->timer.function = rtl8169_phy_timer;
3673
3674         tp->fw = RTL_FIRMWARE_UNKNOWN;
3675
3676         rc = register_netdev(dev);
3677         if (rc < 0)
3678                 goto err_out_msi_4;
3679
3680         pci_set_drvdata(pdev, dev);
3681
3682         netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
3683                    rtl_chip_infos[chipset].name, dev->base_addr, dev->dev_addr,
3684                    (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
3685         if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
3686                 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
3687                            "tx checksumming: %s]\n",
3688                            rtl_chip_infos[chipset].jumbo_max,
3689                            rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
3690         }
3691
3692         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3693             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3694             tp->mac_version == RTL_GIGA_MAC_VER_31) {
3695                 rtl8168_driver_start(tp);
3696         }
3697
3698         device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
3699
3700         if (pci_dev_run_wake(pdev))
3701                 pm_runtime_put_noidle(&pdev->dev);
3702
3703         netif_carrier_off(dev);
3704
3705 out:
3706         return rc;
3707
3708 err_out_msi_4:
3709         netif_napi_del(&tp->napi);
3710         rtl_disable_msi(pdev, tp);
3711         iounmap(ioaddr);
3712 err_out_free_res_3:
3713         pci_release_regions(pdev);
3714 err_out_mwi_2:
3715         pci_clear_mwi(pdev);
3716         pci_disable_device(pdev);
3717 err_out_free_dev_1:
3718         free_netdev(dev);
3719         goto out;
3720 }
3721
3722 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
3723 {
3724         struct net_device *dev = pci_get_drvdata(pdev);
3725         struct rtl8169_private *tp = netdev_priv(dev);
3726
3727         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3728             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3729             tp->mac_version == RTL_GIGA_MAC_VER_31) {
3730                 rtl8168_driver_stop(tp);
3731         }
3732
3733         cancel_delayed_work_sync(&tp->task);
3734
3735         netif_napi_del(&tp->napi);
3736
3737         unregister_netdev(dev);
3738
3739         rtl_release_firmware(tp);
3740
3741         if (pci_dev_run_wake(pdev))
3742                 pm_runtime_get_noresume(&pdev->dev);
3743
3744         /* restore original MAC address */
3745         rtl_rar_set(tp, dev->perm_addr);
3746
3747         rtl_disable_msi(pdev, tp);
3748         rtl8169_release_board(pdev, dev, tp->mmio_addr);
3749         pci_set_drvdata(pdev, NULL);
3750 }
3751
3752 static void rtl_request_firmware(struct rtl8169_private *tp)
3753 {
3754         /* Return early if the firmware is already loaded / cached. */
3755         if (IS_ERR(tp->fw)) {
3756                 const char *name;
3757
3758                 name = rtl_lookup_firmware_name(tp);
3759                 if (name) {
3760                         int rc;
3761
3762                         rc = request_firmware(&tp->fw, name, &tp->pci_dev->dev);
3763                         if (rc >= 0)
3764                                 return;
3765
3766                         netif_warn(tp, ifup, tp->dev, "unable to load "
3767                                 "firmware patch %s (%d)\n", name, rc);
3768                 }
3769                 tp->fw = NULL;
3770         }
3771 }
3772
3773 static int rtl8169_open(struct net_device *dev)
3774 {
3775         struct rtl8169_private *tp = netdev_priv(dev);
3776         void __iomem *ioaddr = tp->mmio_addr;
3777         struct pci_dev *pdev = tp->pci_dev;
3778         int retval = -ENOMEM;
3779
3780         pm_runtime_get_sync(&pdev->dev);
3781
3782         /*
3783          * Rx and Tx desscriptors needs 256 bytes alignment.
3784          * dma_alloc_coherent provides more.
3785          */
3786         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
3787                                              &tp->TxPhyAddr, GFP_KERNEL);
3788         if (!tp->TxDescArray)
3789                 goto err_pm_runtime_put;
3790
3791         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
3792                                              &tp->RxPhyAddr, GFP_KERNEL);
3793         if (!tp->RxDescArray)
3794                 goto err_free_tx_0;
3795
3796         retval = rtl8169_init_ring(dev);
3797         if (retval < 0)
3798                 goto err_free_rx_1;
3799
3800         INIT_DELAYED_WORK(&tp->task, NULL);
3801
3802         smp_mb();
3803
3804         rtl_request_firmware(tp);
3805
3806         retval = request_irq(dev->irq, rtl8169_interrupt,
3807                              (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
3808                              dev->name, dev);
3809         if (retval < 0)
3810                 goto err_release_fw_2;
3811
3812         napi_enable(&tp->napi);
3813
3814         rtl8169_init_phy(dev, tp);
3815
3816         rtl8169_set_features(dev, dev->features);
3817
3818         rtl_pll_power_up(tp);
3819
3820         rtl_hw_start(dev);
3821
3822         tp->saved_wolopts = 0;
3823         pm_runtime_put_noidle(&pdev->dev);
3824
3825         rtl8169_check_link_status(dev, tp, ioaddr);
3826 out:
3827         return retval;
3828
3829 err_release_fw_2:
3830         rtl_release_firmware(tp);
3831         rtl8169_rx_clear(tp);
3832 err_free_rx_1:
3833         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
3834                           tp->RxPhyAddr);
3835         tp->RxDescArray = NULL;
3836 err_free_tx_0:
3837         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
3838                           tp->TxPhyAddr);
3839         tp->TxDescArray = NULL;
3840 err_pm_runtime_put:
3841         pm_runtime_put_noidle(&pdev->dev);
3842         goto out;
3843 }
3844
3845 static void rtl8169_hw_reset(struct rtl8169_private *tp)
3846 {
3847         void __iomem *ioaddr = tp->mmio_addr;
3848
3849         /* Disable interrupts */
3850         rtl8169_irq_mask_and_ack(tp);
3851
3852         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3853             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3854             tp->mac_version == RTL_GIGA_MAC_VER_31) {
3855                 while (RTL_R8(TxPoll) & NPQ)
3856                         udelay(20);
3857
3858         }
3859
3860         /* Reset the chipset */
3861         RTL_W8(ChipCmd, CmdReset);
3862
3863         /* PCI commit */
3864         RTL_R8(ChipCmd);
3865 }
3866
3867 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
3868 {
3869         void __iomem *ioaddr = tp->mmio_addr;
3870         u32 cfg = rtl8169_rx_config;
3871
3872         cfg |= (RTL_R32(RxConfig) & RTL_RX_CONFIG_MASK);
3873         RTL_W32(RxConfig, cfg);
3874
3875         /* Set DMA burst size and Interframe Gap Time */
3876         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3877                 (InterFrameGap << TxInterFrameGapShift));
3878 }
3879
3880 static void rtl_hw_start(struct net_device *dev)
3881 {
3882         struct rtl8169_private *tp = netdev_priv(dev);
3883
3884         rtl_hw_reset(tp);
3885
3886         tp->hw_start(dev);
3887
3888         netif_start_queue(dev);
3889 }
3890
3891 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3892                                          void __iomem *ioaddr)
3893 {
3894         /*
3895          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3896          * register to be written before TxDescAddrLow to work.
3897          * Switching from MMIO to I/O access fixes the issue as well.
3898          */
3899         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
3900         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
3901         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
3902         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
3903 }
3904
3905 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
3906 {
3907         u16 cmd;
3908
3909         cmd = RTL_R16(CPlusCmd);
3910         RTL_W16(CPlusCmd, cmd);
3911         return cmd;
3912 }
3913
3914 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
3915 {
3916         /* Low hurts. Let's disable the filtering. */
3917         RTL_W16(RxMaxSize, rx_buf_sz + 1);
3918 }
3919
3920 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
3921 {
3922         static const struct rtl_cfg2_info {
3923                 u32 mac_version;
3924                 u32 clk;
3925                 u32 val;
3926         } cfg2_info [] = {
3927                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
3928                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
3929                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
3930                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3931         };
3932         const struct rtl_cfg2_info *p = cfg2_info;
3933         unsigned int i;
3934         u32 clk;
3935
3936         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
3937         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
3938                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
3939                         RTL_W32(0x7c, p->val);
3940                         break;
3941                 }
3942         }
3943 }
3944
3945 static void rtl_hw_start_8169(struct net_device *dev)
3946 {
3947         struct rtl8169_private *tp = netdev_priv(dev);
3948         void __iomem *ioaddr = tp->mmio_addr;
3949         struct pci_dev *pdev = tp->pci_dev;
3950
3951         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
3952                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
3953                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
3954         }
3955
3956         RTL_W8(Cfg9346, Cfg9346_Unlock);
3957         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
3958             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3959             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
3960             tp->mac_version == RTL_GIGA_MAC_VER_04)
3961                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3962
3963         RTL_W8(EarlyTxThres, NoEarlyTx);
3964
3965         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
3966
3967         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
3968             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3969             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
3970             tp->mac_version == RTL_GIGA_MAC_VER_04)
3971                 rtl_set_rx_tx_config_registers(tp);
3972
3973         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3974
3975         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3976             tp->mac_version == RTL_GIGA_MAC_VER_03) {
3977                 dprintk("Set MAC Reg C+CR Offset 0xE0. "
3978                         "Bit-3 and bit-14 MUST be 1\n");
3979                 tp->cp_cmd |= (1 << 14);
3980         }
3981
3982         RTL_W16(CPlusCmd, tp->cp_cmd);
3983
3984         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
3985
3986         /*
3987          * Undocumented corner. Supposedly:
3988          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3989          */
3990         RTL_W16(IntrMitigate, 0x0000);
3991
3992         rtl_set_rx_tx_desc_registers(tp, ioaddr);
3993
3994         if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
3995             tp->mac_version != RTL_GIGA_MAC_VER_02 &&
3996             tp->mac_version != RTL_GIGA_MAC_VER_03 &&
3997             tp->mac_version != RTL_GIGA_MAC_VER_04) {
3998                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3999                 rtl_set_rx_tx_config_registers(tp);
4000         }
4001
4002         RTL_W8(Cfg9346, Cfg9346_Lock);
4003
4004         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4005         RTL_R8(IntrMask);
4006
4007         RTL_W32(RxMissed, 0);
4008
4009         rtl_set_rx_mode(dev);
4010
4011         /* no early-rx interrupts */
4012         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4013
4014         /* Enable all known interrupts by setting the interrupt mask. */
4015         RTL_W16(IntrMask, tp->intr_event);
4016 }
4017
4018 static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
4019 {
4020         u32 csi;
4021
4022         csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
4023         rtl_csi_write(ioaddr, 0x070c, csi | bits);
4024 }
4025
4026 static void rtl_csi_access_enable_1(void __iomem *ioaddr)
4027 {
4028         rtl_csi_access_enable(ioaddr, 0x17000000);
4029 }
4030
4031 static void rtl_csi_access_enable_2(void __iomem *ioaddr)
4032 {
4033         rtl_csi_access_enable(ioaddr, 0x27000000);
4034 }
4035
4036 struct ephy_info {
4037         unsigned int offset;
4038         u16 mask;
4039         u16 bits;
4040 };
4041
4042 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
4043 {
4044         u16 w;
4045
4046         while (len-- > 0) {
4047                 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
4048                 rtl_ephy_write(ioaddr, e->offset, w);
4049                 e++;
4050         }
4051 }
4052
4053 static void rtl_disable_clock_request(struct pci_dev *pdev)
4054 {
4055         struct net_device *dev = pci_get_drvdata(pdev);
4056         struct rtl8169_private *tp = netdev_priv(dev);
4057         int cap = tp->pcie_cap;
4058
4059         if (cap) {
4060                 u16 ctl;
4061
4062                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4063                 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
4064                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4065         }
4066 }
4067
4068 static void rtl_enable_clock_request(struct pci_dev *pdev)
4069 {
4070         struct net_device *dev = pci_get_drvdata(pdev);
4071         struct rtl8169_private *tp = netdev_priv(dev);
4072         int cap = tp->pcie_cap;
4073
4074         if (cap) {
4075                 u16 ctl;
4076
4077                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4078                 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
4079                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4080         }
4081 }
4082
4083 #define R8168_CPCMD_QUIRK_MASK (\
4084         EnableBist | \
4085         Mac_dbgo_oe | \
4086         Force_half_dup | \
4087         Force_rxflow_en | \
4088         Force_txflow_en | \
4089         Cxpl_dbg_sel | \
4090         ASF | \
4091         PktCntrDisable | \
4092         Mac_dbgo_sel)
4093
4094 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
4095 {
4096         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4097
4098         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4099
4100         rtl_tx_performance_tweak(pdev,
4101                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4102 }
4103
4104 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
4105 {
4106         rtl_hw_start_8168bb(ioaddr, pdev);
4107
4108         RTL_W8(MaxTxPacketSize, TxPacketMax);
4109
4110         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4111 }
4112
4113 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
4114 {
4115         RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4116
4117         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4118
4119         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4120
4121         rtl_disable_clock_request(pdev);
4122
4123         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4124 }
4125
4126 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
4127 {
4128         static const struct ephy_info e_info_8168cp[] = {
4129                 { 0x01, 0,      0x0001 },
4130                 { 0x02, 0x0800, 0x1000 },
4131                 { 0x03, 0,      0x0042 },
4132                 { 0x06, 0x0080, 0x0000 },
4133                 { 0x07, 0,      0x2000 }
4134         };
4135
4136         rtl_csi_access_enable_2(ioaddr);
4137
4138         rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4139
4140         __rtl_hw_start_8168cp(ioaddr, pdev);
4141 }
4142
4143 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
4144 {
4145         rtl_csi_access_enable_2(ioaddr);
4146
4147         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4148
4149         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4150
4151         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4152 }
4153
4154 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
4155 {
4156         rtl_csi_access_enable_2(ioaddr);
4157
4158         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4159
4160         /* Magic. */
4161         RTL_W8(DBG_REG, 0x20);
4162
4163         RTL_W8(MaxTxPacketSize, TxPacketMax);
4164
4165         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4166
4167         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4168 }
4169
4170 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
4171 {
4172         static const struct ephy_info e_info_8168c_1[] = {
4173                 { 0x02, 0x0800, 0x1000 },
4174                 { 0x03, 0,      0x0002 },
4175                 { 0x06, 0x0080, 0x0000 }
4176         };
4177
4178         rtl_csi_access_enable_2(ioaddr);
4179
4180         RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4181
4182         rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4183
4184         __rtl_hw_start_8168cp(ioaddr, pdev);
4185 }
4186
4187 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
4188 {
4189         static const struct ephy_info e_info_8168c_2[] = {
4190                 { 0x01, 0,      0x0001 },
4191                 { 0x03, 0x0400, 0x0220 }
4192         };
4193
4194         rtl_csi_access_enable_2(ioaddr);
4195
4196         rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4197
4198         __rtl_hw_start_8168cp(ioaddr, pdev);
4199 }
4200
4201 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
4202 {
4203         rtl_hw_start_8168c_2(ioaddr, pdev);
4204 }
4205
4206 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
4207 {
4208         rtl_csi_access_enable_2(ioaddr);
4209
4210         __rtl_hw_start_8168cp(ioaddr, pdev);
4211 }
4212
4213 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
4214 {
4215         rtl_csi_access_enable_2(ioaddr);
4216
4217         rtl_disable_clock_request(pdev);
4218
4219         RTL_W8(MaxTxPacketSize, TxPacketMax);
4220
4221         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4222
4223         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4224 }
4225
4226 static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev)
4227 {
4228         rtl_csi_access_enable_1(ioaddr);
4229
4230         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4231
4232         RTL_W8(MaxTxPacketSize, TxPacketMax);
4233
4234         rtl_disable_clock_request(pdev);
4235 }
4236
4237 static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
4238 {
4239         static const struct ephy_info e_info_8168d_4[] = {
4240                 { 0x0b, ~0,     0x48 },
4241                 { 0x19, 0x20,   0x50 },
4242                 { 0x0c, ~0,     0x20 }
4243         };
4244         int i;
4245
4246         rtl_csi_access_enable_1(ioaddr);
4247
4248         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4249
4250         RTL_W8(MaxTxPacketSize, TxPacketMax);
4251
4252         for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4253                 const struct ephy_info *e = e_info_8168d_4 + i;
4254                 u16 w;
4255
4256                 w = rtl_ephy_read(ioaddr, e->offset);
4257                 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
4258         }
4259
4260         rtl_enable_clock_request(pdev);
4261 }
4262
4263 static void rtl_hw_start_8168e(void __iomem *ioaddr, struct pci_dev *pdev)
4264 {
4265         static const struct ephy_info e_info_8168e[] = {
4266                 { 0x00, 0x0200, 0x0100 },
4267                 { 0x00, 0x0000, 0x0004 },
4268                 { 0x06, 0x0002, 0x0001 },
4269                 { 0x06, 0x0000, 0x0030 },
4270                 { 0x07, 0x0000, 0x2000 },
4271                 { 0x00, 0x0000, 0x0020 },
4272                 { 0x03, 0x5800, 0x2000 },
4273                 { 0x03, 0x0000, 0x0001 },
4274                 { 0x01, 0x0800, 0x1000 },
4275                 { 0x07, 0x0000, 0x4000 },
4276                 { 0x1e, 0x0000, 0x2000 },
4277                 { 0x19, 0xffff, 0xfe6c },
4278                 { 0x0a, 0x0000, 0x0040 }
4279         };
4280
4281         rtl_csi_access_enable_2(ioaddr);
4282
4283         rtl_ephy_init(ioaddr, e_info_8168e, ARRAY_SIZE(e_info_8168e));
4284
4285         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4286
4287         RTL_W8(MaxTxPacketSize, TxPacketMax);
4288
4289         rtl_disable_clock_request(pdev);
4290
4291         /* Reset tx FIFO pointer */
4292         RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
4293         RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
4294
4295         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4296 }
4297
4298 static void rtl_hw_start_8168(struct net_device *dev)
4299 {
4300         struct rtl8169_private *tp = netdev_priv(dev);
4301         void __iomem *ioaddr = tp->mmio_addr;
4302         struct pci_dev *pdev = tp->pci_dev;
4303
4304         RTL_W8(Cfg9346, Cfg9346_Unlock);
4305
4306         RTL_W8(MaxTxPacketSize, TxPacketMax);
4307
4308         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4309
4310         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
4311
4312         RTL_W16(CPlusCmd, tp->cp_cmd);
4313
4314         RTL_W16(IntrMitigate, 0x5151);
4315
4316         /* Work around for RxFIFO overflow. */
4317         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
4318                 tp->intr_event |= RxFIFOOver | PCSTimeout;
4319                 tp->intr_event &= ~RxOverflow;
4320         }
4321
4322         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4323
4324         rtl_set_rx_mode(dev);
4325
4326         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4327                 (InterFrameGap << TxInterFrameGapShift));
4328
4329         RTL_R8(IntrMask);
4330
4331         switch (tp->mac_version) {
4332         case RTL_GIGA_MAC_VER_11:
4333                 rtl_hw_start_8168bb(ioaddr, pdev);
4334                 break;
4335
4336         case RTL_GIGA_MAC_VER_12:
4337         case RTL_GIGA_MAC_VER_17:
4338                 rtl_hw_start_8168bef(ioaddr, pdev);
4339                 break;
4340
4341         case RTL_GIGA_MAC_VER_18:
4342                 rtl_hw_start_8168cp_1(ioaddr, pdev);
4343                 break;
4344
4345         case RTL_GIGA_MAC_VER_19:
4346                 rtl_hw_start_8168c_1(ioaddr, pdev);
4347                 break;
4348
4349         case RTL_GIGA_MAC_VER_20:
4350                 rtl_hw_start_8168c_2(ioaddr, pdev);
4351                 break;
4352
4353         case RTL_GIGA_MAC_VER_21:
4354                 rtl_hw_start_8168c_3(ioaddr, pdev);
4355                 break;
4356
4357         case RTL_GIGA_MAC_VER_22:
4358                 rtl_hw_start_8168c_4(ioaddr, pdev);
4359                 break;
4360
4361         case RTL_GIGA_MAC_VER_23:
4362                 rtl_hw_start_8168cp_2(ioaddr, pdev);
4363                 break;
4364
4365         case RTL_GIGA_MAC_VER_24:
4366                 rtl_hw_start_8168cp_3(ioaddr, pdev);
4367                 break;
4368
4369         case RTL_GIGA_MAC_VER_25:
4370         case RTL_GIGA_MAC_VER_26:
4371         case RTL_GIGA_MAC_VER_27:
4372                 rtl_hw_start_8168d(ioaddr, pdev);
4373                 break;
4374
4375         case RTL_GIGA_MAC_VER_28:
4376                 rtl_hw_start_8168d_4(ioaddr, pdev);
4377                 break;
4378
4379         case RTL_GIGA_MAC_VER_31:
4380                 rtl_hw_start_8168dp(ioaddr, pdev);
4381                 break;
4382
4383         case RTL_GIGA_MAC_VER_32:
4384         case RTL_GIGA_MAC_VER_33:
4385                 rtl_hw_start_8168e(ioaddr, pdev);
4386                 break;
4387
4388         default:
4389                 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
4390                         dev->name, tp->mac_version);
4391                 break;
4392         }
4393
4394         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4395
4396         RTL_W8(Cfg9346, Cfg9346_Lock);
4397
4398         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4399
4400         RTL_W16(IntrMask, tp->intr_event);
4401 }
4402
4403 #define R810X_CPCMD_QUIRK_MASK (\
4404         EnableBist | \
4405         Mac_dbgo_oe | \
4406         Force_half_dup | \
4407         Force_rxflow_en | \
4408         Force_txflow_en | \
4409         Cxpl_dbg_sel | \
4410         ASF | \
4411         PktCntrDisable | \
4412         Mac_dbgo_sel)
4413
4414 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4415 {
4416         static const struct ephy_info e_info_8102e_1[] = {
4417                 { 0x01, 0, 0x6e65 },
4418                 { 0x02, 0, 0x091f },
4419                 { 0x03, 0, 0xc2f9 },
4420                 { 0x06, 0, 0xafb5 },
4421                 { 0x07, 0, 0x0e00 },
4422                 { 0x19, 0, 0xec80 },
4423                 { 0x01, 0, 0x2e65 },
4424                 { 0x01, 0, 0x6e65 }
4425         };
4426         u8 cfg1;
4427
4428         rtl_csi_access_enable_2(ioaddr);
4429
4430         RTL_W8(DBG_REG, FIX_NAK_1);
4431
4432         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4433
4434         RTL_W8(Config1,
4435                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
4436         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4437
4438         cfg1 = RTL_R8(Config1);
4439         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
4440                 RTL_W8(Config1, cfg1 & ~LEDS0);
4441
4442         rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
4443 }
4444
4445 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4446 {
4447         rtl_csi_access_enable_2(ioaddr);
4448
4449         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4450
4451         RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
4452         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4453 }
4454
4455 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
4456 {
4457         rtl_hw_start_8102e_2(ioaddr, pdev);
4458
4459         rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
4460 }
4461
4462 static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4463 {
4464         static const struct ephy_info e_info_8105e_1[] = {
4465                 { 0x07, 0, 0x4000 },
4466                 { 0x19, 0, 0x0200 },
4467                 { 0x19, 0, 0x0020 },
4468                 { 0x1e, 0, 0x2000 },
4469                 { 0x03, 0, 0x0001 },
4470                 { 0x19, 0, 0x0100 },
4471                 { 0x19, 0, 0x0004 },
4472                 { 0x0a, 0, 0x0020 }
4473         };
4474
4475         /* Force LAN exit from ASPM if Rx/Tx are not idle */
4476         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
4477
4478         /* Disable Early Tally Counter */
4479         RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
4480
4481         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4482         RTL_W8(DLLPR, RTL_R8(DLLPR) | PM_SWITCH);
4483
4484         rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
4485 }
4486
4487 static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4488 {
4489         rtl_hw_start_8105e_1(ioaddr, pdev);
4490         rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
4491 }
4492
4493 static void rtl_hw_start_8101(struct net_device *dev)
4494 {
4495         struct rtl8169_private *tp = netdev_priv(dev);
4496         void __iomem *ioaddr = tp->mmio_addr;
4497         struct pci_dev *pdev = tp->pci_dev;
4498
4499         if (tp->mac_version >= RTL_GIGA_MAC_VER_30) {
4500                 tp->intr_event &= ~RxFIFOOver;
4501                 tp->napi_event &= ~RxFIFOOver;
4502         }
4503
4504         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
4505             tp->mac_version == RTL_GIGA_MAC_VER_16) {
4506                 int cap = tp->pcie_cap;
4507
4508                 if (cap) {
4509                         pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
4510                                               PCI_EXP_DEVCTL_NOSNOOP_EN);
4511                 }
4512         }
4513
4514         RTL_W8(Cfg9346, Cfg9346_Unlock);
4515
4516         switch (tp->mac_version) {
4517         case RTL_GIGA_MAC_VER_07:
4518                 rtl_hw_start_8102e_1(ioaddr, pdev);
4519                 break;
4520
4521         case RTL_GIGA_MAC_VER_08:
4522                 rtl_hw_start_8102e_3(ioaddr, pdev);
4523                 break;
4524
4525         case RTL_GIGA_MAC_VER_09:
4526                 rtl_hw_start_8102e_2(ioaddr, pdev);
4527                 break;
4528
4529         case RTL_GIGA_MAC_VER_29:
4530                 rtl_hw_start_8105e_1(ioaddr, pdev);
4531                 break;
4532         case RTL_GIGA_MAC_VER_30:
4533                 rtl_hw_start_8105e_2(ioaddr, pdev);
4534                 break;
4535         }
4536
4537         RTL_W8(Cfg9346, Cfg9346_Lock);
4538
4539         RTL_W8(MaxTxPacketSize, TxPacketMax);
4540
4541         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4542
4543         tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
4544         RTL_W16(CPlusCmd, tp->cp_cmd);
4545
4546         RTL_W16(IntrMitigate, 0x0000);
4547
4548         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4549
4550         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4551         rtl_set_rx_tx_config_registers(tp);
4552
4553         RTL_R8(IntrMask);
4554
4555         rtl_set_rx_mode(dev);
4556
4557         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
4558
4559         RTL_W16(IntrMask, tp->intr_event);
4560 }
4561
4562 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
4563 {
4564         struct rtl8169_private *tp = netdev_priv(dev);
4565
4566         if (new_mtu < ETH_ZLEN ||
4567             new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
4568                 return -EINVAL;
4569
4570         if (new_mtu > ETH_DATA_LEN)
4571                 rtl_hw_jumbo_enable(tp);
4572         else
4573                 rtl_hw_jumbo_disable(tp);
4574
4575         dev->mtu = new_mtu;
4576         netdev_update_features(dev);
4577
4578         return 0;
4579 }
4580
4581 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
4582 {
4583         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
4584         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
4585 }
4586
4587 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
4588                                      void **data_buff, struct RxDesc *desc)
4589 {
4590         dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
4591                          DMA_FROM_DEVICE);
4592
4593         kfree(*data_buff);
4594         *data_buff = NULL;
4595         rtl8169_make_unusable_by_asic(desc);
4596 }
4597
4598 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
4599 {
4600         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
4601
4602         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
4603 }
4604
4605 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
4606                                        u32 rx_buf_sz)
4607 {
4608         desc->addr = cpu_to_le64(mapping);
4609         wmb();
4610         rtl8169_mark_to_asic(desc, rx_buf_sz);
4611 }
4612
4613 static inline void *rtl8169_align(void *data)
4614 {
4615         return (void *)ALIGN((long)data, 16);
4616 }
4617
4618 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
4619                                              struct RxDesc *desc)
4620 {
4621         void *data;
4622         dma_addr_t mapping;
4623         struct device *d = &tp->pci_dev->dev;
4624         struct net_device *dev = tp->dev;
4625         int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
4626
4627         data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
4628         if (!data)
4629                 return NULL;
4630
4631         if (rtl8169_align(data) != data) {
4632                 kfree(data);
4633                 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
4634                 if (!data)
4635                         return NULL;
4636         }
4637
4638         mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
4639                                  DMA_FROM_DEVICE);
4640         if (unlikely(dma_mapping_error(d, mapping))) {
4641                 if (net_ratelimit())
4642                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
4643                 goto err_out;
4644         }
4645
4646         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
4647         return data;
4648
4649 err_out:
4650         kfree(data);
4651         return NULL;
4652 }
4653
4654 static void rtl8169_rx_clear(struct rtl8169_private *tp)
4655 {
4656         unsigned int i;
4657
4658         for (i = 0; i < NUM_RX_DESC; i++) {
4659                 if (tp->Rx_databuff[i]) {
4660                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
4661                                             tp->RxDescArray + i);
4662                 }
4663         }
4664 }
4665
4666 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
4667 {
4668         desc->opts1 |= cpu_to_le32(RingEnd);
4669 }
4670
4671 static int rtl8169_rx_fill(struct rtl8169_private *tp)
4672 {
4673         unsigned int i;
4674
4675         for (i = 0; i < NUM_RX_DESC; i++) {
4676                 void *data;
4677
4678                 if (tp->Rx_databuff[i])
4679                         continue;
4680
4681                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
4682                 if (!data) {
4683                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
4684                         goto err_out;
4685                 }
4686                 tp->Rx_databuff[i] = data;
4687         }
4688
4689         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4690         return 0;
4691
4692 err_out:
4693         rtl8169_rx_clear(tp);
4694         return -ENOMEM;
4695 }
4696
4697 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4698 {
4699         tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
4700 }
4701
4702 static int rtl8169_init_ring(struct net_device *dev)
4703 {
4704         struct rtl8169_private *tp = netdev_priv(dev);
4705
4706         rtl8169_init_ring_indexes(tp);
4707
4708         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
4709         memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
4710
4711         return rtl8169_rx_fill(tp);
4712 }
4713
4714 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
4715                                  struct TxDesc *desc)
4716 {
4717         unsigned int len = tx_skb->len;
4718
4719         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
4720
4721         desc->opts1 = 0x00;
4722         desc->opts2 = 0x00;
4723         desc->addr = 0x00;
4724         tx_skb->len = 0;
4725 }
4726
4727 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4728                                    unsigned int n)
4729 {
4730         unsigned int i;
4731
4732         for (i = 0; i < n; i++) {
4733                 unsigned int entry = (start + i) % NUM_TX_DESC;
4734                 struct ring_info *tx_skb = tp->tx_skb + entry;
4735                 unsigned int len = tx_skb->len;
4736
4737                 if (len) {
4738                         struct sk_buff *skb = tx_skb->skb;
4739
4740                         rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4741                                              tp->TxDescArray + entry);
4742                         if (skb) {
4743                                 tp->dev->stats.tx_dropped++;
4744                                 dev_kfree_skb(skb);
4745                                 tx_skb->skb = NULL;
4746                         }
4747                 }
4748         }
4749 }
4750
4751 static void rtl8169_tx_clear(struct rtl8169_private *tp)
4752 {
4753         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
4754         tp->cur_tx = tp->dirty_tx = 0;
4755 }
4756
4757 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
4758 {
4759         struct rtl8169_private *tp = netdev_priv(dev);
4760
4761         PREPARE_DELAYED_WORK(&tp->task, task);
4762         schedule_delayed_work(&tp->task, 4);
4763 }
4764
4765 static void rtl8169_wait_for_quiescence(struct net_device *dev)
4766 {
4767         struct rtl8169_private *tp = netdev_priv(dev);
4768         void __iomem *ioaddr = tp->mmio_addr;
4769
4770         synchronize_irq(dev->irq);
4771
4772         /* Wait for any pending NAPI task to complete */
4773         napi_disable(&tp->napi);
4774
4775         rtl8169_irq_mask_and_ack(tp);
4776
4777         tp->intr_mask = 0xffff;
4778         RTL_W16(IntrMask, tp->intr_event);
4779         napi_enable(&tp->napi);
4780 }
4781
4782 static void rtl8169_reinit_task(struct work_struct *work)
4783 {
4784         struct rtl8169_private *tp =
4785                 container_of(work, struct rtl8169_private, task.work);
4786         struct net_device *dev = tp->dev;
4787         int ret;
4788
4789         rtnl_lock();
4790
4791         if (!netif_running(dev))
4792                 goto out_unlock;
4793
4794         rtl8169_wait_for_quiescence(dev);
4795         rtl8169_close(dev);
4796
4797         ret = rtl8169_open(dev);
4798         if (unlikely(ret < 0)) {
4799                 if (net_ratelimit())
4800                         netif_err(tp, drv, dev,
4801                                   "reinit failure (status = %d). Rescheduling\n",
4802                                   ret);
4803                 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4804         }
4805
4806 out_unlock:
4807         rtnl_unlock();
4808 }
4809
4810 static void rtl8169_reset_task(struct work_struct *work)
4811 {
4812         struct rtl8169_private *tp =
4813                 container_of(work, struct rtl8169_private, task.work);
4814         struct net_device *dev = tp->dev;
4815         int i;
4816
4817         rtnl_lock();
4818
4819         if (!netif_running(dev))
4820                 goto out_unlock;
4821
4822         rtl8169_wait_for_quiescence(dev);
4823
4824         for (i = 0; i < NUM_RX_DESC; i++)
4825                 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
4826
4827         rtl8169_tx_clear(tp);
4828
4829         rtl8169_init_ring_indexes(tp);
4830         rtl_hw_start(dev);
4831         netif_wake_queue(dev);
4832         rtl8169_check_link_status(dev, tp, tp->mmio_addr);
4833
4834 out_unlock:
4835         rtnl_unlock();
4836 }
4837
4838 static void rtl8169_tx_timeout(struct net_device *dev)
4839 {
4840         struct rtl8169_private *tp = netdev_priv(dev);
4841
4842         rtl8169_hw_reset(tp);
4843
4844         /* Let's wait a bit while any (async) irq lands on */
4845         rtl8169_schedule_work(dev, rtl8169_reset_task);
4846 }
4847
4848 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4849                               u32 *opts)
4850 {
4851         struct skb_shared_info *info = skb_shinfo(skb);
4852         unsigned int cur_frag, entry;
4853         struct TxDesc * uninitialized_var(txd);
4854         struct device *d = &tp->pci_dev->dev;
4855
4856         entry = tp->cur_tx;
4857         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4858                 skb_frag_t *frag = info->frags + cur_frag;
4859                 dma_addr_t mapping;
4860                 u32 status, len;
4861                 void *addr;
4862
4863                 entry = (entry + 1) % NUM_TX_DESC;
4864
4865                 txd = tp->TxDescArray + entry;
4866                 len = frag->size;
4867                 addr = ((void *) page_address(frag->page)) + frag->page_offset;
4868                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
4869                 if (unlikely(dma_mapping_error(d, mapping))) {
4870                         if (net_ratelimit())
4871                                 netif_err(tp, drv, tp->dev,
4872                                           "Failed to map TX fragments DMA!\n");
4873                         goto err_out;
4874                 }
4875
4876                 /* Anti gcc 2.95.3 bugware (sic) */
4877                 status = opts[0] | len |
4878                         (RingEnd * !((entry + 1) % NUM_TX_DESC));
4879
4880                 txd->opts1 = cpu_to_le32(status);
4881                 txd->opts2 = cpu_to_le32(opts[1]);
4882                 txd->addr = cpu_to_le64(mapping);
4883
4884                 tp->tx_skb[entry].len = len;
4885         }
4886
4887         if (cur_frag) {
4888                 tp->tx_skb[entry].skb = skb;
4889                 txd->opts1 |= cpu_to_le32(LastFrag);
4890         }
4891
4892         return cur_frag;
4893
4894 err_out:
4895         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4896         return -EIO;
4897 }
4898
4899 static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
4900                                     struct sk_buff *skb, u32 *opts)
4901 {
4902         const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
4903         u32 mss = skb_shinfo(skb)->gso_size;
4904         int offset = info->opts_offset;
4905
4906         if (mss) {
4907                 opts[0] |= TD_LSO;
4908                 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
4909         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4910                 const struct iphdr *ip = ip_hdr(skb);
4911
4912                 if (ip->protocol == IPPROTO_TCP)
4913                         opts[offset] |= info->checksum.tcp;
4914                 else if (ip->protocol == IPPROTO_UDP)
4915                         opts[offset] |= info->checksum.udp;
4916                 else
4917                         WARN_ON_ONCE(1);
4918         }
4919 }
4920
4921 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4922                                       struct net_device *dev)
4923 {
4924         struct rtl8169_private *tp = netdev_priv(dev);
4925         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
4926         struct TxDesc *txd = tp->TxDescArray + entry;
4927         void __iomem *ioaddr = tp->mmio_addr;
4928         struct device *d = &tp->pci_dev->dev;
4929         dma_addr_t mapping;
4930         u32 status, len;
4931         u32 opts[2];
4932         int frags;
4933
4934         if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
4935                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
4936                 goto err_stop_0;
4937         }
4938
4939         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
4940                 goto err_stop_0;
4941
4942         len = skb_headlen(skb);
4943         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
4944         if (unlikely(dma_mapping_error(d, mapping))) {
4945                 if (net_ratelimit())
4946                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
4947                 goto err_dma_0;
4948         }
4949
4950         tp->tx_skb[entry].len = len;
4951         txd->addr = cpu_to_le64(mapping);
4952
4953         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
4954         opts[0] = DescOwn;
4955
4956         rtl8169_tso_csum(tp, skb, opts);
4957
4958         frags = rtl8169_xmit_frags(tp, skb, opts);
4959         if (frags < 0)
4960                 goto err_dma_1;
4961         else if (frags)
4962                 opts[0] |= FirstFrag;
4963         else {
4964                 opts[0] |= FirstFrag | LastFrag;
4965                 tp->tx_skb[entry].skb = skb;
4966         }
4967
4968         txd->opts2 = cpu_to_le32(opts[1]);
4969
4970         wmb();
4971
4972         /* Anti gcc 2.95.3 bugware (sic) */
4973         status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4974         txd->opts1 = cpu_to_le32(status);
4975
4976         tp->cur_tx += frags + 1;
4977
4978         wmb();
4979
4980         RTL_W8(TxPoll, NPQ);
4981
4982         if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
4983                 netif_stop_queue(dev);
4984                 smp_mb();
4985                 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
4986                         netif_wake_queue(dev);
4987         }
4988
4989         return NETDEV_TX_OK;
4990
4991 err_dma_1:
4992         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
4993 err_dma_0:
4994         dev_kfree_skb(skb);
4995         dev->stats.tx_dropped++;
4996         return NETDEV_TX_OK;
4997
4998 err_stop_0:
4999         netif_stop_queue(dev);
5000         dev->stats.tx_dropped++;
5001         return NETDEV_TX_BUSY;
5002 }
5003
5004 static void rtl8169_pcierr_interrupt(struct net_device *dev)
5005 {
5006         struct rtl8169_private *tp = netdev_priv(dev);
5007         struct pci_dev *pdev = tp->pci_dev;
5008         u16 pci_status, pci_cmd;
5009
5010         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5011         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5012
5013         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5014                   pci_cmd, pci_status);
5015
5016         /*
5017          * The recovery sequence below admits a very elaborated explanation:
5018          * - it seems to work;
5019          * - I did not see what else could be done;
5020          * - it makes iop3xx happy.
5021          *
5022          * Feel free to adjust to your needs.
5023          */
5024         if (pdev->broken_parity_status)
5025                 pci_cmd &= ~PCI_COMMAND_PARITY;
5026         else
5027                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5028
5029         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
5030
5031         pci_write_config_word(pdev, PCI_STATUS,
5032                 pci_status & (PCI_STATUS_DETECTED_PARITY |
5033                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5034                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5035
5036         /* The infamous DAC f*ckup only happens at boot time */
5037         if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
5038                 void __iomem *ioaddr = tp->mmio_addr;
5039
5040                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
5041                 tp->cp_cmd &= ~PCIDAC;
5042                 RTL_W16(CPlusCmd, tp->cp_cmd);
5043                 dev->features &= ~NETIF_F_HIGHDMA;
5044         }
5045
5046         rtl8169_hw_reset(tp);
5047
5048         rtl8169_schedule_work(dev, rtl8169_reinit_task);
5049 }
5050
5051 static void rtl8169_tx_interrupt(struct net_device *dev,
5052                                  struct rtl8169_private *tp,
5053                                  void __iomem *ioaddr)
5054 {
5055         unsigned int dirty_tx, tx_left;
5056
5057         dirty_tx = tp->dirty_tx;
5058         smp_rmb();
5059         tx_left = tp->cur_tx - dirty_tx;
5060
5061         while (tx_left > 0) {
5062                 unsigned int entry = dirty_tx % NUM_TX_DESC;
5063                 struct ring_info *tx_skb = tp->tx_skb + entry;
5064                 u32 status;
5065
5066                 rmb();
5067                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5068                 if (status & DescOwn)
5069                         break;
5070
5071                 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5072                                      tp->TxDescArray + entry);
5073                 if (status & LastFrag) {
5074                         dev->stats.tx_packets++;
5075                         dev->stats.tx_bytes += tx_skb->skb->len;
5076                         dev_kfree_skb(tx_skb->skb);
5077                         tx_skb->skb = NULL;
5078                 }
5079                 dirty_tx++;
5080                 tx_left--;
5081         }
5082
5083         if (tp->dirty_tx != dirty_tx) {
5084                 tp->dirty_tx = dirty_tx;
5085                 smp_mb();
5086                 if (netif_queue_stopped(dev) &&
5087                     TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
5088                         netif_wake_queue(dev);
5089                 }
5090                 /*
5091                  * 8168 hack: TxPoll requests are lost when the Tx packets are
5092                  * too close. Let's kick an extra TxPoll request when a burst
5093                  * of start_xmit activity is detected (if it is not detected,
5094                  * it is slow enough). -- FR
5095                  */
5096                 if (tp->cur_tx != dirty_tx)
5097                         RTL_W8(TxPoll, NPQ);
5098         }
5099 }
5100
5101 static inline int rtl8169_fragmented_frame(u32 status)
5102 {
5103         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
5104 }
5105
5106 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
5107 {
5108         u32 status = opts1 & RxProtoMask;
5109
5110         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
5111             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
5112                 skb->ip_summed = CHECKSUM_UNNECESSARY;
5113         else
5114                 skb_checksum_none_assert(skb);
5115 }
5116
5117 static struct sk_buff *rtl8169_try_rx_copy(void *data,
5118                                            struct rtl8169_private *tp,
5119                                            int pkt_size,
5120                                            dma_addr_t addr)
5121 {
5122         struct sk_buff *skb;
5123         struct device *d = &tp->pci_dev->dev;
5124
5125         data = rtl8169_align(data);
5126         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
5127         prefetch(data);
5128         skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
5129         if (skb)
5130                 memcpy(skb->data, data, pkt_size);
5131         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
5132
5133         return skb;
5134 }
5135
5136 static int rtl8169_rx_interrupt(struct net_device *dev,
5137                                 struct rtl8169_private *tp,
5138                                 void __iomem *ioaddr, u32 budget)
5139 {
5140         unsigned int cur_rx, rx_left;
5141         unsigned int count;
5142
5143         cur_rx = tp->cur_rx;
5144         rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
5145         rx_left = min(rx_left, budget);
5146
5147         for (; rx_left > 0; rx_left--, cur_rx++) {
5148                 unsigned int entry = cur_rx % NUM_RX_DESC;
5149                 struct RxDesc *desc = tp->RxDescArray + entry;
5150                 u32 status;
5151
5152                 rmb();
5153                 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
5154
5155                 if (status & DescOwn)
5156                         break;
5157                 if (unlikely(status & RxRES)) {
5158                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
5159                                    status);
5160                         dev->stats.rx_errors++;
5161                         if (status & (RxRWT | RxRUNT))
5162                                 dev->stats.rx_length_errors++;
5163                         if (status & RxCRC)
5164                                 dev->stats.rx_crc_errors++;
5165                         if (status & RxFOVF) {
5166                                 rtl8169_schedule_work(dev, rtl8169_reset_task);
5167                                 dev->stats.rx_fifo_errors++;
5168                         }
5169                         rtl8169_mark_to_asic(desc, rx_buf_sz);
5170                 } else {
5171                         struct sk_buff *skb;
5172                         dma_addr_t addr = le64_to_cpu(desc->addr);
5173                         int pkt_size = (status & 0x00003fff) - 4;
5174
5175                         /*
5176                          * The driver does not support incoming fragmented
5177                          * frames. They are seen as a symptom of over-mtu
5178                          * sized frames.
5179                          */
5180                         if (unlikely(rtl8169_fragmented_frame(status))) {
5181                                 dev->stats.rx_dropped++;
5182                                 dev->stats.rx_length_errors++;
5183                                 rtl8169_mark_to_asic(desc, rx_buf_sz);
5184                                 continue;
5185                         }
5186
5187                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
5188                                                   tp, pkt_size, addr);
5189                         rtl8169_mark_to_asic(desc, rx_buf_sz);
5190                         if (!skb) {
5191                                 dev->stats.rx_dropped++;
5192                                 continue;
5193                         }
5194
5195                         rtl8169_rx_csum(skb, status);
5196                         skb_put(skb, pkt_size);
5197                         skb->protocol = eth_type_trans(skb, dev);
5198
5199                         rtl8169_rx_vlan_tag(desc, skb);
5200
5201                         napi_gro_receive(&tp->napi, skb);
5202
5203                         dev->stats.rx_bytes += pkt_size;
5204                         dev->stats.rx_packets++;
5205                 }
5206
5207                 /* Work around for AMD plateform. */
5208                 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
5209                     (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
5210                         desc->opts2 = 0;
5211                         cur_rx++;
5212                 }
5213         }
5214
5215         count = cur_rx - tp->cur_rx;
5216         tp->cur_rx = cur_rx;
5217
5218         tp->dirty_rx += count;
5219
5220         return count;
5221 }
5222
5223 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
5224 {
5225         struct net_device *dev = dev_instance;
5226         struct rtl8169_private *tp = netdev_priv(dev);
5227         void __iomem *ioaddr = tp->mmio_addr;
5228         int handled = 0;
5229         int status;
5230
5231         /* loop handling interrupts until we have no new ones or
5232          * we hit a invalid/hotplug case.
5233          */
5234         status = RTL_R16(IntrStatus);
5235         while (status && status != 0xffff) {
5236                 status &= tp->intr_event;
5237                 if (!status)
5238                         break;
5239
5240                 handled = 1;
5241
5242                 /* Handle all of the error cases first. These will reset
5243                  * the chip, so just exit the loop.
5244                  */
5245                 if (unlikely(!netif_running(dev))) {
5246                         rtl8169_asic_down(tp);
5247                         break;
5248                 }
5249
5250                 if (unlikely(status & RxFIFOOver)) {
5251                         switch (tp->mac_version) {
5252                         /* Work around for rx fifo overflow */
5253                         case RTL_GIGA_MAC_VER_11:
5254                                 netif_stop_queue(dev);
5255                                 rtl8169_tx_timeout(dev);
5256                                 goto done;
5257                         default:
5258                                 break;
5259                         }
5260                 }
5261
5262                 if (unlikely(status & SYSErr)) {
5263                         rtl8169_pcierr_interrupt(dev);
5264                         break;
5265                 }
5266
5267                 if (status & LinkChg)
5268                         __rtl8169_check_link_status(dev, tp, ioaddr, true);
5269
5270                 /* We need to see the lastest version of tp->intr_mask to
5271                  * avoid ignoring an MSI interrupt and having to wait for
5272                  * another event which may never come.
5273                  */
5274                 smp_rmb();
5275                 if (status & tp->intr_mask & tp->napi_event) {
5276                         RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
5277                         tp->intr_mask = ~tp->napi_event;
5278
5279                         if (likely(napi_schedule_prep(&tp->napi)))
5280                                 __napi_schedule(&tp->napi);
5281                         else
5282                                 netif_info(tp, intr, dev,
5283                                            "interrupt %04x in poll\n", status);
5284                 }
5285
5286                 /* We only get a new MSI interrupt when all active irq
5287                  * sources on the chip have been acknowledged. So, ack
5288                  * everything we've seen and check if new sources have become
5289                  * active to avoid blocking all interrupts from the chip.
5290                  */
5291                 RTL_W16(IntrStatus,
5292                         (status & RxFIFOOver) ? (status | RxOverflow) : status);
5293                 status = RTL_R16(IntrStatus);
5294         }
5295 done:
5296         return IRQ_RETVAL(handled);
5297 }
5298
5299 static int rtl8169_poll(struct napi_struct *napi, int budget)
5300 {
5301         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5302         struct net_device *dev = tp->dev;
5303         void __iomem *ioaddr = tp->mmio_addr;
5304         int work_done;
5305
5306         work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
5307         rtl8169_tx_interrupt(dev, tp, ioaddr);
5308
5309         if (work_done < budget) {
5310                 napi_complete(napi);
5311
5312                 /* We need for force the visibility of tp->intr_mask
5313                  * for other CPUs, as we can loose an MSI interrupt
5314                  * and potentially wait for a retransmit timeout if we don't.
5315                  * The posted write to IntrMask is safe, as it will
5316                  * eventually make it to the chip and we won't loose anything
5317                  * until it does.
5318                  */
5319                 tp->intr_mask = 0xffff;
5320                 wmb();
5321                 RTL_W16(IntrMask, tp->intr_event);
5322         }
5323
5324         return work_done;
5325 }
5326
5327 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
5328 {
5329         struct rtl8169_private *tp = netdev_priv(dev);
5330
5331         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5332                 return;
5333
5334         dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
5335         RTL_W32(RxMissed, 0);
5336 }
5337
5338 static void rtl8169_down(struct net_device *dev)
5339 {
5340         struct rtl8169_private *tp = netdev_priv(dev);
5341         void __iomem *ioaddr = tp->mmio_addr;
5342
5343         del_timer_sync(&tp->timer);
5344
5345         netif_stop_queue(dev);
5346
5347         napi_disable(&tp->napi);
5348
5349         spin_lock_irq(&tp->lock);
5350
5351         rtl8169_asic_down(tp);
5352         /*
5353          * At this point device interrupts can not be enabled in any function,
5354          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
5355          * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
5356          */
5357         rtl8169_rx_missed(dev, ioaddr);
5358
5359         spin_unlock_irq(&tp->lock);
5360
5361         synchronize_irq(dev->irq);
5362
5363         /* Give a racing hard_start_xmit a few cycles to complete. */
5364         synchronize_sched();  /* FIXME: should this be synchronize_irq()? */
5365
5366         rtl8169_tx_clear(tp);
5367
5368         rtl8169_rx_clear(tp);
5369
5370         rtl_pll_power_down(tp);
5371 }
5372
5373 static int rtl8169_close(struct net_device *dev)
5374 {
5375         struct rtl8169_private *tp = netdev_priv(dev);
5376         struct pci_dev *pdev = tp->pci_dev;
5377
5378         pm_runtime_get_sync(&pdev->dev);
5379
5380         /* Update counters before going down */
5381         rtl8169_update_counters(dev);
5382
5383         rtl8169_down(dev);
5384
5385         free_irq(dev->irq, dev);
5386
5387         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5388                           tp->RxPhyAddr);
5389         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5390                           tp->TxPhyAddr);
5391         tp->TxDescArray = NULL;
5392         tp->RxDescArray = NULL;
5393
5394         pm_runtime_put_sync(&pdev->dev);
5395
5396         return 0;
5397 }
5398
5399 static void rtl_set_rx_mode(struct net_device *dev)
5400 {
5401         struct rtl8169_private *tp = netdev_priv(dev);
5402         void __iomem *ioaddr = tp->mmio_addr;
5403         unsigned long flags;
5404         u32 mc_filter[2];       /* Multicast hash filter */
5405         int rx_mode;
5406         u32 tmp = 0;
5407
5408         if (dev->flags & IFF_PROMISC) {
5409                 /* Unconditionally log net taps. */
5410                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
5411                 rx_mode =
5412                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5413                     AcceptAllPhys;
5414                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5415         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
5416                    (dev->flags & IFF_ALLMULTI)) {
5417                 /* Too many to filter perfectly -- accept all multicasts. */
5418                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5419                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5420         } else {
5421                 struct netdev_hw_addr *ha;
5422
5423                 rx_mode = AcceptBroadcast | AcceptMyPhys;
5424                 mc_filter[1] = mc_filter[0] = 0;
5425                 netdev_for_each_mc_addr(ha, dev) {
5426                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
5427                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5428                         rx_mode |= AcceptMulticast;
5429                 }
5430         }
5431
5432         spin_lock_irqsave(&tp->lock, flags);
5433
5434         tmp = rtl8169_rx_config | rx_mode |
5435               (RTL_R32(RxConfig) & RTL_RX_CONFIG_MASK);
5436
5437         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
5438                 u32 data = mc_filter[0];
5439
5440                 mc_filter[0] = swab32(mc_filter[1]);
5441                 mc_filter[1] = swab32(data);
5442         }
5443
5444         RTL_W32(MAR0 + 4, mc_filter[1]);
5445         RTL_W32(MAR0 + 0, mc_filter[0]);
5446
5447         RTL_W32(RxConfig, tmp);
5448
5449         spin_unlock_irqrestore(&tp->lock, flags);
5450 }
5451
5452 /**
5453  *  rtl8169_get_stats - Get rtl8169 read/write statistics
5454  *  @dev: The Ethernet Device to get statistics for
5455  *
5456  *  Get TX/RX statistics for rtl8169
5457  */
5458 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
5459 {
5460         struct rtl8169_private *tp = netdev_priv(dev);
5461         void __iomem *ioaddr = tp->mmio_addr;
5462         unsigned long flags;
5463
5464         if (netif_running(dev)) {
5465                 spin_lock_irqsave(&tp->lock, flags);
5466                 rtl8169_rx_missed(dev, ioaddr);
5467                 spin_unlock_irqrestore(&tp->lock, flags);
5468         }
5469
5470         return &dev->stats;
5471 }
5472
5473 static void rtl8169_net_suspend(struct net_device *dev)
5474 {
5475         struct rtl8169_private *tp = netdev_priv(dev);
5476
5477         if (!netif_running(dev))
5478                 return;
5479
5480         rtl_pll_power_down(tp);
5481
5482         netif_device_detach(dev);
5483         netif_stop_queue(dev);
5484 }
5485
5486 #ifdef CONFIG_PM
5487
5488 static int rtl8169_suspend(struct device *device)
5489 {
5490         struct pci_dev *pdev = to_pci_dev(device);
5491         struct net_device *dev = pci_get_drvdata(pdev);
5492
5493         rtl8169_net_suspend(dev);
5494
5495         return 0;
5496 }
5497
5498 static void __rtl8169_resume(struct net_device *dev)
5499 {
5500         struct rtl8169_private *tp = netdev_priv(dev);
5501
5502         netif_device_attach(dev);
5503
5504         rtl_pll_power_up(tp);
5505
5506         rtl8169_schedule_work(dev, rtl8169_reset_task);
5507 }
5508
5509 static int rtl8169_resume(struct device *device)
5510 {
5511         struct pci_dev *pdev = to_pci_dev(device);
5512         struct net_device *dev = pci_get_drvdata(pdev);
5513         struct rtl8169_private *tp = netdev_priv(dev);
5514
5515         rtl8169_init_phy(dev, tp);
5516
5517         if (netif_running(dev))
5518                 __rtl8169_resume(dev);
5519
5520         return 0;
5521 }
5522
5523 static int rtl8169_runtime_suspend(struct device *device)
5524 {
5525         struct pci_dev *pdev = to_pci_dev(device);
5526         struct net_device *dev = pci_get_drvdata(pdev);
5527         struct rtl8169_private *tp = netdev_priv(dev);
5528
5529         if (!tp->TxDescArray)
5530                 return 0;
5531
5532         spin_lock_irq(&tp->lock);
5533         tp->saved_wolopts = __rtl8169_get_wol(tp);
5534         __rtl8169_set_wol(tp, WAKE_ANY);
5535         spin_unlock_irq(&tp->lock);
5536
5537         rtl8169_net_suspend(dev);
5538
5539         return 0;
5540 }
5541
5542 static int rtl8169_runtime_resume(struct device *device)
5543 {
5544         struct pci_dev *pdev = to_pci_dev(device);
5545         struct net_device *dev = pci_get_drvdata(pdev);
5546         struct rtl8169_private *tp = netdev_priv(dev);
5547
5548         if (!tp->TxDescArray)
5549                 return 0;
5550
5551         spin_lock_irq(&tp->lock);
5552         __rtl8169_set_wol(tp, tp->saved_wolopts);
5553         tp->saved_wolopts = 0;
5554         spin_unlock_irq(&tp->lock);
5555
5556         rtl8169_init_phy(dev, tp);
5557
5558         __rtl8169_resume(dev);
5559
5560         return 0;
5561 }
5562
5563 static int rtl8169_runtime_idle(struct device *device)
5564 {
5565         struct pci_dev *pdev = to_pci_dev(device);
5566         struct net_device *dev = pci_get_drvdata(pdev);
5567         struct rtl8169_private *tp = netdev_priv(dev);
5568
5569         return tp->TxDescArray ? -EBUSY : 0;
5570 }
5571
5572 static const struct dev_pm_ops rtl8169_pm_ops = {
5573         .suspend                = rtl8169_suspend,
5574         .resume                 = rtl8169_resume,
5575         .freeze                 = rtl8169_suspend,
5576         .thaw                   = rtl8169_resume,
5577         .poweroff               = rtl8169_suspend,
5578         .restore                = rtl8169_resume,
5579         .runtime_suspend        = rtl8169_runtime_suspend,
5580         .runtime_resume         = rtl8169_runtime_resume,
5581         .runtime_idle           = rtl8169_runtime_idle,
5582 };
5583
5584 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
5585
5586 #else /* !CONFIG_PM */
5587
5588 #define RTL8169_PM_OPS  NULL
5589
5590 #endif /* !CONFIG_PM */
5591
5592 static void rtl_shutdown(struct pci_dev *pdev)
5593 {
5594         struct net_device *dev = pci_get_drvdata(pdev);
5595         struct rtl8169_private *tp = netdev_priv(dev);
5596         void __iomem *ioaddr = tp->mmio_addr;
5597         struct device *d = &pdev->dev;
5598
5599         pm_runtime_get_sync(d);
5600
5601         rtl8169_net_suspend(dev);
5602
5603         /* Restore original MAC address */
5604         rtl_rar_set(tp, dev->perm_addr);
5605
5606         spin_lock_irq(&tp->lock);
5607
5608         rtl8169_asic_down(tp);
5609
5610         spin_unlock_irq(&tp->lock);
5611
5612         if (system_state == SYSTEM_POWER_OFF) {
5613                 /* WoL fails with 8168b when the receiver is disabled. */
5614                 if ((tp->mac_version == RTL_GIGA_MAC_VER_11 ||
5615                      tp->mac_version == RTL_GIGA_MAC_VER_12 ||
5616                      tp->mac_version == RTL_GIGA_MAC_VER_17) &&
5617                     (tp->features & RTL_FEATURE_WOL)) {
5618                         pci_clear_master(pdev);
5619
5620                         RTL_W8(ChipCmd, CmdRxEnb);
5621                         /* PCI commit */
5622                         RTL_R8(ChipCmd);
5623                 }
5624
5625                 pci_wake_from_d3(pdev, true);
5626                 pci_set_power_state(pdev, PCI_D3hot);
5627         }
5628
5629         pm_runtime_put_noidle(d);
5630 }
5631
5632 static struct pci_driver rtl8169_pci_driver = {
5633         .name           = MODULENAME,
5634         .id_table       = rtl8169_pci_tbl,
5635         .probe          = rtl8169_init_one,
5636         .remove         = __devexit_p(rtl8169_remove_one),
5637         .shutdown       = rtl_shutdown,
5638         .driver.pm      = RTL8169_PM_OPS,
5639 };
5640
5641 static int __init rtl8169_init_module(void)
5642 {
5643         return pci_register_driver(&rtl8169_pci_driver);
5644 }
5645
5646 static void __exit rtl8169_cleanup_module(void)
5647 {
5648         pci_unregister_driver(&rtl8169_pci_driver);
5649 }
5650
5651 module_init(rtl8169_init_module);
5652 module_exit(rtl8169_cleanup_module);