drivers/net/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/mii.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/crc32.h>
  21 #include <linux/in.h>
  22 #include <linux/ip.h>
  23 #include <linux/tcp.h>
  24 #include <linux/init.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/firmware.h>
  28 #include <linux/pci-aspm.h>
  29 #include <linux/prefetch.h>
  30
  31 #include <asm/system.h>
  32 #include <asm/io.h>
  33 #include <asm/irq.h>
  34
  35 #define RTL8169_VERSION "2.3LK-NAPI"
  36 #define MODULENAME "r8169"
  37 #define PFX MODULENAME ": "
  38
  39 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  40 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  41 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  42 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  43 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  44
  45 #ifdef RTL8169_DEBUG
  46 #define assert(expr) \
  47         if (!(expr)) {                                  \
  48                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  49                 #expr,__FILE__,__func__,__LINE__);              \
  50         }
  51 #define dprintk(fmt, args...) \
  52         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
  53 #else
  54 #define assert(expr) do {} while (0)
  55 #define dprintk(fmt, args...)   do {} while (0)
  56 #endif /* RTL8169_DEBUG */
  57
  58 #define R8169_MSG_DEFAULT \
  59         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  60
  61 #define TX_BUFFS_AVAIL(tp) \
  62         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
  63
  64 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  65    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  66 static const int multicast_filter_limit = 32;
  67
  68 /* MAC address length */
  69 #define MAC_ADDR_LEN    6
  70
  71 #define MAX_READ_REQUEST_SHIFT  12
  72 #define RX_FIFO_THRESH  7       /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
  73 #define RX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  74 #define TX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  75 #define SafeMtu         0x1c20  /* ... actually life sucks beyond ~7k */
  76 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  77
  78 #define R8169_REGS_SIZE         256
  79 #define R8169_NAPI_WEIGHT       64
  80 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  81 #define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
  82 #define RX_BUF_SIZE     1536    /* Rx Buffer size */
  83 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  84 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  85
  86 #define RTL8169_TX_TIMEOUT      (6*HZ)
  87 #define RTL8169_PHY_TIMEOUT     (10*HZ)
  88
  89 #define RTL_EEPROM_SIG          cpu_to_le32(0x8129)
  90 #define RTL_EEPROM_SIG_MASK     cpu_to_le32(0xffff)
  91 #define RTL_EEPROM_SIG_ADDR     0x0000
  92
  93 /* write/read MMIO register */
  94 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
  95 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
  96 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
  97 #define RTL_R8(reg)             readb (ioaddr + (reg))
  98 #define RTL_R16(reg)            readw (ioaddr + (reg))
  99 #define RTL_R32(reg)            readl (ioaddr + (reg))
 100
 101 enum mac_version {
 102         RTL_GIGA_MAC_VER_01 = 0,
 103         RTL_GIGA_MAC_VER_02,
 104         RTL_GIGA_MAC_VER_03,
 105         RTL_GIGA_MAC_VER_04,
 106         RTL_GIGA_MAC_VER_05,
 107         RTL_GIGA_MAC_VER_06,
 108         RTL_GIGA_MAC_VER_07,
 109         RTL_GIGA_MAC_VER_08,
 110         RTL_GIGA_MAC_VER_09,
 111         RTL_GIGA_MAC_VER_10,
 112         RTL_GIGA_MAC_VER_11,
 113         RTL_GIGA_MAC_VER_12,
 114         RTL_GIGA_MAC_VER_13,
 115         RTL_GIGA_MAC_VER_14,
 116         RTL_GIGA_MAC_VER_15,
 117         RTL_GIGA_MAC_VER_16,
 118         RTL_GIGA_MAC_VER_17,
 119         RTL_GIGA_MAC_VER_18,
 120         RTL_GIGA_MAC_VER_19,
 121         RTL_GIGA_MAC_VER_20,
 122         RTL_GIGA_MAC_VER_21,
 123         RTL_GIGA_MAC_VER_22,
 124         RTL_GIGA_MAC_VER_23,
 125         RTL_GIGA_MAC_VER_24,
 126         RTL_GIGA_MAC_VER_25,
 127         RTL_GIGA_MAC_VER_26,
 128         RTL_GIGA_MAC_VER_27,
 129         RTL_GIGA_MAC_VER_28,
 130         RTL_GIGA_MAC_VER_29,
 131         RTL_GIGA_MAC_VER_30,
 132         RTL_GIGA_MAC_VER_31,
 133         RTL_GIGA_MAC_VER_32,
 134         RTL_GIGA_MAC_VER_33,
 135         RTL_GIGA_MAC_NONE   = 0xff,
 136 };
 137
 138 enum rtl_tx_desc_version {
 139         RTL_TD_0        = 0,
 140         RTL_TD_1        = 1,
 141 };
 142
 143 #define JUMBO_1K        ETH_DATA_LEN
 144 #define JUMBO_4K        (4*1024 - ETH_HLEN - 2)
 145 #define JUMBO_6K        (6*1024 - ETH_HLEN - 2)
 146 #define JUMBO_7K        (7*1024 - ETH_HLEN - 2)
 147 #define JUMBO_9K        (9*1024 - ETH_HLEN - 2)
 148
 149 #define _R(NAME,TD,FW,SZ,B) {   \
 150         .name = NAME,           \
 151         .txd_version = TD,      \
 152         .fw_name = FW,          \
 153         .jumbo_max = SZ,        \
 154         .jumbo_tx_csum = B      \
 155 }
 156
 157 static const struct {
 158         const char *name;
 159         enum rtl_tx_desc_version txd_version;
 160         const char *fw_name;
 161         u16 jumbo_max;
 162         bool jumbo_tx_csum;
 163 } rtl_chip_infos[] = {
 164         /* PCI devices. */
 165         [RTL_GIGA_MAC_VER_01] =
 166                 _R("RTL8169",           RTL_TD_0, NULL, JUMBO_7K, true),
 167         [RTL_GIGA_MAC_VER_02] =
 168                 _R("RTL8169s",          RTL_TD_0, NULL, JUMBO_7K, true),
 169         [RTL_GIGA_MAC_VER_03] =
 170                 _R("RTL8110s",          RTL_TD_0, NULL, JUMBO_7K, true),
 171         [RTL_GIGA_MAC_VER_04] =
 172                 _R("RTL8169sb/8110sb",  RTL_TD_0, NULL, JUMBO_7K, true),
 173         [RTL_GIGA_MAC_VER_05] =
 174                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 175         [RTL_GIGA_MAC_VER_06] =
 176                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 177         /* PCI-E devices. */
 178         [RTL_GIGA_MAC_VER_07] =
 179                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 180         [RTL_GIGA_MAC_VER_08] =
 181                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 182         [RTL_GIGA_MAC_VER_09] =
 183                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 184         [RTL_GIGA_MAC_VER_10] =
 185                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 186         [RTL_GIGA_MAC_VER_11] =
 187                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 188         [RTL_GIGA_MAC_VER_12] =
 189                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 190         [RTL_GIGA_MAC_VER_13] =
 191                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 192         [RTL_GIGA_MAC_VER_14] =
 193                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 194         [RTL_GIGA_MAC_VER_15] =
 195                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 196         [RTL_GIGA_MAC_VER_16] =
 197                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 198         [RTL_GIGA_MAC_VER_17] =
 199                 _R("RTL8168b/8111b",    RTL_TD_1, NULL, JUMBO_4K, false),
 200         [RTL_GIGA_MAC_VER_18] =
 201                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 202         [RTL_GIGA_MAC_VER_19] =
 203                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 204         [RTL_GIGA_MAC_VER_20] =
 205                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 206         [RTL_GIGA_MAC_VER_21] =
 207                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 208         [RTL_GIGA_MAC_VER_22] =
 209                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 210         [RTL_GIGA_MAC_VER_23] =
 211                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 212         [RTL_GIGA_MAC_VER_24] =
 213                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 214         [RTL_GIGA_MAC_VER_25] =
 215                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_1,
 216                                                         JUMBO_9K, false),
 217         [RTL_GIGA_MAC_VER_26] =
 218                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_2,
 219                                                         JUMBO_9K, false),
 220         [RTL_GIGA_MAC_VER_27] =
 221                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 222         [RTL_GIGA_MAC_VER_28] =
 223                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 224         [RTL_GIGA_MAC_VER_29] =
 225                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 226                                                         JUMBO_1K, true),
 227         [RTL_GIGA_MAC_VER_30] =
 228                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 229                                                         JUMBO_1K, true),
 230         [RTL_GIGA_MAC_VER_31] =
 231                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 232         [RTL_GIGA_MAC_VER_32] =
 233                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_1,
 234                                                         JUMBO_9K, false),
 235         [RTL_GIGA_MAC_VER_33] =
 236                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_2,
 237                                                         JUMBO_9K, false)
 238 };
 239 #undef _R
 240
 241 enum cfg_version {
 242         RTL_CFG_0 = 0x00,
 243         RTL_CFG_1,
 244         RTL_CFG_2
 245 };
 246
 247 static void rtl_hw_start_8169(struct net_device *);
 248 static void rtl_hw_start_8168(struct net_device *);
 249 static void rtl_hw_start_8101(struct net_device *);
 250
 251 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
 252         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 253         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 254         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 255         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 256         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 257         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 258         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4302), 0, 0, RTL_CFG_0 },
 259         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
 260         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 261         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 262                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 263         { 0x0001,                               0x8168,
 264                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 265         {0,},
 266 };
 267
 268 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 269
 270 static int rx_buf_sz = 16383;
 271 static int use_dac;
 272 static struct {
 273         u32 msg_enable;
 274 } debug = { -1 };
 275
 276 enum rtl_registers {
 277         MAC0            = 0,    /* Ethernet hardware address. */
 278         MAC4            = 4,
 279         MAR0            = 8,    /* Multicast filter. */
 280         CounterAddrLow          = 0x10,
 281         CounterAddrHigh         = 0x14,
 282         TxDescStartAddrLow      = 0x20,
 283         TxDescStartAddrHigh     = 0x24,
 284         TxHDescStartAddrLow     = 0x28,
 285         TxHDescStartAddrHigh    = 0x2c,
 286         FLASH           = 0x30,
 287         ERSR            = 0x36,
 288         ChipCmd         = 0x37,
 289         TxPoll          = 0x38,
 290         IntrMask        = 0x3c,
 291         IntrStatus      = 0x3e,
 292         TxConfig        = 0x40,
 293         RxConfig        = 0x44,
 294
 295 #define RTL_RX_CONFIG_MASK              0xff7e1880u
 296
 297         RxMissed        = 0x4c,
 298         Cfg9346         = 0x50,
 299         Config0         = 0x51,
 300         Config1         = 0x52,
 301         Config2         = 0x53,
 302         Config3         = 0x54,
 303         Config4         = 0x55,
 304         Config5         = 0x56,
 305         MultiIntr       = 0x5c,
 306         PHYAR           = 0x60,
 307         PHYstatus       = 0x6c,
 308         RxMaxSize       = 0xda,
 309         CPlusCmd        = 0xe0,
 310         IntrMitigate    = 0xe2,
 311         RxDescAddrLow   = 0xe4,
 312         RxDescAddrHigh  = 0xe8,
 313         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 314
 315 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 316
 317         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 318
 319 #define TxPacketMax     (8064 >> 7)
 320
 321         FuncEvent       = 0xf0,
 322         FuncEventMask   = 0xf4,
 323         FuncPresetState = 0xf8,
 324         FuncForceEvent  = 0xfc,
 325 };
 326
 327 enum rtl8110_registers {
 328         TBICSR                  = 0x64,
 329         TBI_ANAR                = 0x68,
 330         TBI_LPAR                = 0x6a,
 331 };
 332
 333 enum rtl8168_8101_registers {
 334         CSIDR                   = 0x64,
 335         CSIAR                   = 0x68,
 336 #define CSIAR_FLAG                      0x80000000
 337 #define CSIAR_WRITE_CMD                 0x80000000
 338 #define CSIAR_BYTE_ENABLE               0x0f
 339 #define CSIAR_BYTE_ENABLE_SHIFT         12
 340 #define CSIAR_ADDR_MASK                 0x0fff
 341         PMCH                    = 0x6f,
 342         EPHYAR                  = 0x80,
 343 #define EPHYAR_FLAG                     0x80000000
 344 #define EPHYAR_WRITE_CMD                0x80000000
 345 #define EPHYAR_REG_MASK                 0x1f
 346 #define EPHYAR_REG_SHIFT                16
 347 #define EPHYAR_DATA_MASK                0xffff
 348         DLLPR                   = 0xd0,
 349 #define PM_SWITCH                       (1 << 6)
 350         DBG_REG                 = 0xd1,
 351 #define FIX_NAK_1                       (1 << 4)
 352 #define FIX_NAK_2                       (1 << 3)
 353         TWSI                    = 0xd2,
 354         MCU                     = 0xd3,
 355 #define EN_NDP                          (1 << 3)
 356 #define EN_OOB_RESET                    (1 << 2)
 357         EFUSEAR                 = 0xdc,
 358 #define EFUSEAR_FLAG                    0x80000000
 359 #define EFUSEAR_WRITE_CMD               0x80000000
 360 #define EFUSEAR_READ_CMD                0x00000000
 361 #define EFUSEAR_REG_MASK                0x03ff
 362 #define EFUSEAR_REG_SHIFT               8
 363 #define EFUSEAR_DATA_MASK               0xff
 364 };
 365
 366 enum rtl8168_registers {
 367         ERIDR                   = 0x70,
 368         ERIAR                   = 0x74,
 369 #define ERIAR_FLAG                      0x80000000
 370 #define ERIAR_WRITE_CMD                 0x80000000
 371 #define ERIAR_READ_CMD                  0x00000000
 372 #define ERIAR_ADDR_BYTE_ALIGN           4
 373 #define ERIAR_EXGMAC                    0
 374 #define ERIAR_MSIX                      1
 375 #define ERIAR_ASF                       2
 376 #define ERIAR_TYPE_SHIFT                16
 377 #define ERIAR_BYTEEN                    0x0f
 378 #define ERIAR_BYTEEN_SHIFT              12
 379         EPHY_RXER_NUM           = 0x7c,
 380         OCPDR                   = 0xb0, /* OCP GPHY access */
 381 #define OCPDR_WRITE_CMD                 0x80000000
 382 #define OCPDR_READ_CMD                  0x00000000
 383 #define OCPDR_REG_MASK                  0x7f
 384 #define OCPDR_GPHY_REG_SHIFT            16
 385 #define OCPDR_DATA_MASK                 0xffff
 386         OCPAR                   = 0xb4,
 387 #define OCPAR_FLAG                      0x80000000
 388 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 389 #define OCPAR_GPHY_READ_CMD             0x0000f060
 390         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 391         MISC                    = 0xf0, /* 8168e only. */
 392 #define TXPLA_RST                       (1 << 29)
 393 };
 394
 395 enum rtl_register_content {
 396         /* InterruptStatusBits */
 397         SYSErr          = 0x8000,
 398         PCSTimeout      = 0x4000,
 399         SWInt           = 0x0100,
 400         TxDescUnavail   = 0x0080,
 401         RxFIFOOver      = 0x0040,
 402         LinkChg         = 0x0020,
 403         RxOverflow      = 0x0010,
 404         TxErr           = 0x0008,
 405         TxOK            = 0x0004,
 406         RxErr           = 0x0002,
 407         RxOK            = 0x0001,
 408
 409         /* RxStatusDesc */
 410         RxBOVF  = (1 << 24),
 411         RxFOVF  = (1 << 23),
 412         RxRWT   = (1 << 22),
 413         RxRES   = (1 << 21),
 414         RxRUNT  = (1 << 20),
 415         RxCRC   = (1 << 19),
 416
 417         /* ChipCmdBits */
 418         CmdReset        = 0x10,
 419         CmdRxEnb        = 0x08,
 420         CmdTxEnb        = 0x04,
 421         RxBufEmpty      = 0x01,
 422
 423         /* TXPoll register p.5 */
 424         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 425         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 426         FSWInt          = 0x01,         /* Forced software interrupt */
 427
 428         /* Cfg9346Bits */
 429         Cfg9346_Lock    = 0x00,
 430         Cfg9346_Unlock  = 0xc0,
 431
 432         /* rx_mode_bits */
 433         AcceptErr       = 0x20,
 434         AcceptRunt      = 0x10,
 435         AcceptBroadcast = 0x08,
 436         AcceptMulticast = 0x04,
 437         AcceptMyPhys    = 0x02,
 438         AcceptAllPhys   = 0x01,
 439
 440         /* RxConfigBits */
 441         RxCfgFIFOShift  = 13,
 442         RxCfgDMAShift   =  8,
 443
 444         /* TxConfigBits */
 445         TxInterFrameGapShift = 24,
 446         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 447
 448         /* Config1 register p.24 */
 449         LEDS1           = (1 << 7),
 450         LEDS0           = (1 << 6),
 451         MSIEnable       = (1 << 5),     /* Enable Message Signaled Interrupt */
 452         Speed_down      = (1 << 4),
 453         MEMMAP          = (1 << 3),
 454         IOMAP           = (1 << 2),
 455         VPD             = (1 << 1),
 456         PMEnable        = (1 << 0),     /* Power Management Enable */
 457
 458         /* Config2 register p. 25 */
 459         PCI_Clock_66MHz = 0x01,
 460         PCI_Clock_33MHz = 0x00,
 461
 462         /* Config3 register p.25 */
 463         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 464         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 465         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 466         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 467
 468         /* Config4 register */
 469         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 470
 471         /* Config5 register p.27 */
 472         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 473         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 474         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 475         Spi_en          = (1 << 3),
 476         LanWake         = (1 << 1),     /* LanWake enable/disable */
 477         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 478
 479         /* TBICSR p.28 */
 480         TBIReset        = 0x80000000,
 481         TBILoopback     = 0x40000000,
 482         TBINwEnable     = 0x20000000,
 483         TBINwRestart    = 0x10000000,
 484         TBILinkOk       = 0x02000000,
 485         TBINwComplete   = 0x01000000,
 486
 487         /* CPlusCmd p.31 */
 488         EnableBist      = (1 << 15),    // 8168 8101
 489         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 490         Normal_mode     = (1 << 13),    // unused
 491         Force_half_dup  = (1 << 12),    // 8168 8101
 492         Force_rxflow_en = (1 << 11),    // 8168 8101
 493         Force_txflow_en = (1 << 10),    // 8168 8101
 494         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 495         ASF             = (1 << 8),     // 8168 8101
 496         PktCntrDisable  = (1 << 7),     // 8168 8101
 497         Mac_dbgo_sel    = 0x001c,       // 8168
 498         RxVlan          = (1 << 6),
 499         RxChkSum        = (1 << 5),
 500         PCIDAC          = (1 << 4),
 501         PCIMulRW        = (1 << 3),
 502         INTT_0          = 0x0000,       // 8168
 503         INTT_1          = 0x0001,       // 8168
 504         INTT_2          = 0x0002,       // 8168
 505         INTT_3          = 0x0003,       // 8168
 506
 507         /* rtl8169_PHYstatus */
 508         TBI_Enable      = 0x80,
 509         TxFlowCtrl      = 0x40,
 510         RxFlowCtrl      = 0x20,
 511         _1000bpsF       = 0x10,
 512         _100bps         = 0x08,
 513         _10bps          = 0x04,
 514         LinkStatus      = 0x02,
 515         FullDup         = 0x01,
 516
 517         /* _TBICSRBit */
 518         TBILinkOK       = 0x02000000,
 519
 520         /* DumpCounterCommand */
 521         CounterDump     = 0x8,
 522 };
 523
 524 enum rtl_desc_bit {
 525         /* First doubleword. */
 526         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 527         RingEnd         = (1 << 30), /* End of descriptor ring */
 528         FirstFrag       = (1 << 29), /* First segment of a packet */
 529         LastFrag        = (1 << 28), /* Final segment of a packet */
 530 };
 531
 532 /* Generic case. */
 533 enum rtl_tx_desc_bit {
 534         /* First doubleword. */
 535         TD_LSO          = (1 << 27),            /* Large Send Offload */
 536 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 537
 538         /* Second doubleword. */
 539         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 540 };
 541
 542 /* 8169, 8168b and 810x except 8102e. */
 543 enum rtl_tx_desc_bit_0 {
 544         /* First doubleword. */
 545 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 546         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 547         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 548         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 549 };
 550
 551 /* 8102e, 8168c and beyond. */
 552 enum rtl_tx_desc_bit_1 {
 553         /* Second doubleword. */
 554 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 555         TD1_IP_CS       = (1 << 29),            /* Calculate IP checksum */
 556         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 557         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 558 };
 559
 560 static const struct rtl_tx_desc_info {
 561         struct {
 562                 u32 udp;
 563                 u32 tcp;
 564         } checksum;
 565         u16 mss_shift;
 566         u16 opts_offset;
 567 } tx_desc_info [] = {
 568         [RTL_TD_0] = {
 569                 .checksum = {
 570                         .udp    = TD0_IP_CS | TD0_UDP_CS,
 571                         .tcp    = TD0_IP_CS | TD0_TCP_CS
 572                 },
 573                 .mss_shift      = TD0_MSS_SHIFT,
 574                 .opts_offset    = 0
 575         },
 576         [RTL_TD_1] = {
 577                 .checksum = {
 578                         .udp    = TD1_IP_CS | TD1_UDP_CS,
 579                         .tcp    = TD1_IP_CS | TD1_TCP_CS
 580                 },
 581                 .mss_shift      = TD1_MSS_SHIFT,
 582                 .opts_offset    = 1
 583         }
 584 };
 585
 586 enum rtl_rx_desc_bit {
 587         /* Rx private */
 588         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 589         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
 590
 591 #define RxProtoUDP      (PID1)
 592 #define RxProtoTCP      (PID0)
 593 #define RxProtoIP       (PID1 | PID0)
 594 #define RxProtoMask     RxProtoIP
 595
 596         IPFail          = (1 << 16), /* IP checksum failed */
 597         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 598         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 599         RxVlanTag       = (1 << 16), /* VLAN tag available */
 600 };
 601
 602 #define RsvdMask        0x3fffc000
 603
 604 struct TxDesc {
 605         __le32 opts1;
 606         __le32 opts2;
 607         __le64 addr;
 608 };
 609
 610 struct RxDesc {
 611         __le32 opts1;
 612         __le32 opts2;
 613         __le64 addr;
 614 };
 615
 616 struct ring_info {
 617         struct sk_buff  *skb;
 618         u32             len;
 619         u8              __pad[sizeof(void *) - sizeof(u32)];
 620 };
 621
 622 enum features {
 623         RTL_FEATURE_WOL         = (1 << 0),
 624         RTL_FEATURE_MSI         = (1 << 1),
 625         RTL_FEATURE_GMII        = (1 << 2),
 626 };
 627
 628 struct rtl8169_counters {
 629         __le64  tx_packets;
 630         __le64  rx_packets;
 631         __le64  tx_errors;
 632         __le32  rx_errors;
 633         __le16  rx_missed;
 634         __le16  align_errors;
 635         __le32  tx_one_collision;
 636         __le32  tx_multi_collision;
 637         __le64  rx_unicast;
 638         __le64  rx_broadcast;
 639         __le32  rx_multicast;
 640         __le16  tx_aborted;
 641         __le16  tx_underun;
 642 };
 643
 644 struct rtl8169_private {
 645         void __iomem *mmio_addr;        /* memory map physical address */
 646         struct pci_dev *pci_dev;
 647         struct net_device *dev;
 648         struct napi_struct napi;
 649         spinlock_t lock;
 650         u32 msg_enable;
 651         u16 txd_version;
 652         u16 mac_version;
 653         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 654         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 655         u32 dirty_rx;
 656         u32 dirty_tx;
 657         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 658         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 659         dma_addr_t TxPhyAddr;
 660         dma_addr_t RxPhyAddr;
 661         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 662         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 663         struct timer_list timer;
 664         u16 cp_cmd;
 665         u16 intr_event;
 666         u16 napi_event;
 667         u16 intr_mask;
 668
 669         struct mdio_ops {
 670                 void (*write)(void __iomem *, int, int);
 671                 int (*read)(void __iomem *, int);
 672         } mdio_ops;
 673
 674         struct pll_power_ops {
 675                 void (*down)(struct rtl8169_private *);
 676                 void (*up)(struct rtl8169_private *);
 677         } pll_power_ops;
 678
 679         struct jumbo_ops {
 680                 void (*enable)(struct rtl8169_private *);
 681                 void (*disable)(struct rtl8169_private *);
 682         } jumbo_ops;
 683
 684         int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
 685         int (*get_settings)(struct net_device *, struct ethtool_cmd *);
 686         void (*phy_reset_enable)(struct rtl8169_private *tp);
 687         void (*hw_start)(struct net_device *);
 688         unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
 689         unsigned int (*link_ok)(void __iomem *);
 690         int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
 691         int pcie_cap;
 692         struct delayed_work task;
 693         unsigned features;
 694
 695         struct mii_if_info mii;
 696         struct rtl8169_counters counters;
 697         u32 saved_wolopts;
 698         u32 opts1_mask;
 699
 700         const struct firmware *fw;
 701 #define RTL_FIRMWARE_UNKNOWN    ERR_PTR(-EAGAIN);
 702 };
 703
 704 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 705 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 706 module_param(use_dac, int, 0);
 707 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 708 module_param_named(debug, debug.msg_enable, int, 0);
 709 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 710 MODULE_LICENSE("GPL");
 711 MODULE_VERSION(RTL8169_VERSION);
 712 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 713 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 714 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 715 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 716 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 717
 718 static int rtl8169_open(struct net_device *dev);
 719 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
 720                                       struct net_device *dev);
 721 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
 722 static int rtl8169_init_ring(struct net_device *dev);
 723 static void rtl_hw_start(struct net_device *dev);
 724 static int rtl8169_close(struct net_device *dev);
 725 static void rtl_set_rx_mode(struct net_device *dev);
 726 static void rtl8169_tx_timeout(struct net_device *dev);
 727 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
 728 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
 729                                 void __iomem *, u32 budget);
 730 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
 731 static void rtl8169_down(struct net_device *dev);
 732 static void rtl8169_rx_clear(struct rtl8169_private *tp);
 733 static int rtl8169_poll(struct napi_struct *napi, int budget);
 734
 735 static const unsigned int rtl8169_rx_config =
 736         (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
 737
 738 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
 739 {
 740         struct net_device *dev = pci_get_drvdata(pdev);
 741         struct rtl8169_private *tp = netdev_priv(dev);
 742         int cap = tp->pcie_cap;
 743
 744         if (cap) {
 745                 u16 ctl;
 746
 747                 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
 748                 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
 749                 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
 750         }
 751 }
 752
 753 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
 754 {
 755         void __iomem *ioaddr = tp->mmio_addr;
 756         int i;
 757
 758         RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 759         for (i = 0; i < 20; i++) {
 760                 udelay(100);
 761                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
 762                         break;
 763         }
 764         return RTL_R32(OCPDR);
 765 }
 766
 767 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
 768 {
 769         void __iomem *ioaddr = tp->mmio_addr;
 770         int i;
 771
 772         RTL_W32(OCPDR, data);
 773         RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 774         for (i = 0; i < 20; i++) {
 775                 udelay(100);
 776                 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
 777                         break;
 778         }
 779 }
 780
 781 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
 782 {
 783         void __iomem *ioaddr = tp->mmio_addr;
 784         int i;
 785
 786         RTL_W8(ERIDR, cmd);
 787         RTL_W32(ERIAR, 0x800010e8);
 788         msleep(2);
 789         for (i = 0; i < 5; i++) {
 790                 udelay(100);
 791                 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
 792                         break;
 793         }
 794
 795         ocp_write(tp, 0x1, 0x30, 0x00000001);
 796 }
 797
 798 #define OOB_CMD_RESET           0x00
 799 #define OOB_CMD_DRIVER_START    0x05
 800 #define OOB_CMD_DRIVER_STOP     0x06
 801
 802 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
 803 {
 804         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
 805 }
 806
 807 static void rtl8168_driver_start(struct rtl8169_private *tp)
 808 {
 809         u16 reg;
 810         int i;
 811
 812         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
 813
 814         reg = rtl8168_get_ocp_reg(tp);
 815
 816         for (i = 0; i < 10; i++) {
 817                 msleep(10);
 818                 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
 819                         break;
 820         }
 821 }
 822
 823 static void rtl8168_driver_stop(struct rtl8169_private *tp)
 824 {
 825         u16 reg;
 826         int i;
 827
 828         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
 829
 830         reg = rtl8168_get_ocp_reg(tp);
 831
 832         for (i = 0; i < 10; i++) {
 833                 msleep(10);
 834                 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
 835                         break;
 836         }
 837 }
 838
 839 static int r8168dp_check_dash(struct rtl8169_private *tp)
 840 {
 841         u16 reg = rtl8168_get_ocp_reg(tp);
 842
 843         return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
 844 }
 845
 846 static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 847 {
 848         int i;
 849
 850         RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
 851
 852         for (i = 20; i > 0; i--) {
 853                 /*
 854                  * Check if the RTL8169 has completed writing to the specified
 855                  * MII register.
 856                  */
 857                 if (!(RTL_R32(PHYAR) & 0x80000000))
 858                         break;
 859                 udelay(25);
 860         }
 861         /*
 862          * According to hardware specs a 20us delay is required after write
 863          * complete indication, but before sending next command.
 864          */
 865         udelay(20);
 866 }
 867
 868 static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
 869 {
 870         int i, value = -1;
 871
 872         RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
 873
 874         for (i = 20; i > 0; i--) {
 875                 /*
 876                  * Check if the RTL8169 has completed retrieving data from
 877                  * the specified MII register.
 878                  */
 879                 if (RTL_R32(PHYAR) & 0x80000000) {
 880                         value = RTL_R32(PHYAR) & 0xffff;
 881                         break;
 882                 }
 883                 udelay(25);
 884         }
 885         /*
 886          * According to hardware specs a 20us delay is required after read
 887          * complete indication, but before sending next command.
 888          */
 889         udelay(20);
 890
 891         return value;
 892 }
 893
 894 static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
 895 {
 896         int i;
 897
 898         RTL_W32(OCPDR, data |
 899                 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
 900         RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
 901         RTL_W32(EPHY_RXER_NUM, 0);
 902
 903         for (i = 0; i < 100; i++) {
 904                 mdelay(1);
 905                 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
 906                         break;
 907         }
 908 }
 909
 910 static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 911 {
 912         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
 913                 (value & OCPDR_DATA_MASK));
 914 }
 915
 916 static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
 917 {
 918         int i;
 919
 920         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
 921
 922         mdelay(1);
 923         RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
 924         RTL_W32(EPHY_RXER_NUM, 0);
 925
 926         for (i = 0; i < 100; i++) {
 927                 mdelay(1);
 928                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
 929                         break;
 930         }
 931
 932         return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
 933 }
 934
 935 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
 936
 937 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
 938 {
 939         RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
 940 }
 941
 942 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
 943 {
 944         RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
 945 }
 946
 947 static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 948 {
 949         r8168dp_2_mdio_start(ioaddr);
 950
 951         r8169_mdio_write(ioaddr, reg_addr, value);
 952
 953         r8168dp_2_mdio_stop(ioaddr);
 954 }
 955
 956 static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
 957 {
 958         int value;
 959
 960         r8168dp_2_mdio_start(ioaddr);
 961
 962         value = r8169_mdio_read(ioaddr, reg_addr);
 963
 964         r8168dp_2_mdio_stop(ioaddr);
 965
 966         return value;
 967 }
 968
 969 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
 970 {
 971         tp->mdio_ops.write(tp->mmio_addr, location, val);
 972 }
 973
 974 static int rtl_readphy(struct rtl8169_private *tp, int location)
 975 {
 976         return tp->mdio_ops.read(tp->mmio_addr, location);
 977 }
 978
 979 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
 980 {
 981         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
 982 }
 983
 984 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
 985 {
 986         int val;
 987
 988         val = rtl_readphy(tp, reg_addr);
 989         rtl_writephy(tp, reg_addr, (val | p) & ~m);
 990 }
 991
 992 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
 993                            int val)
 994 {
 995         struct rtl8169_private *tp = netdev_priv(dev);
 996
 997         rtl_writephy(tp, location, val);
 998 }
 999
1000 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1001 {
1002         struct rtl8169_private *tp = netdev_priv(dev);
1003
1004         return rtl_readphy(tp, location);
1005 }
1006
1007 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
1008 {
1009         unsigned int i;
1010
1011         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1012                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1013
1014         for (i = 0; i < 100; i++) {
1015                 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
1016                         break;
1017                 udelay(10);
1018         }
1019 }
1020
1021 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
1022 {
1023         u16 value = 0xffff;
1024         unsigned int i;
1025
1026         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1027
1028         for (i = 0; i < 100; i++) {
1029                 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
1030                         value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
1031                         break;
1032                 }
1033                 udelay(10);
1034         }
1035
1036         return value;
1037 }
1038
1039 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
1040 {
1041         unsigned int i;
1042
1043         RTL_W32(CSIDR, value);
1044         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
1045                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1046
1047         for (i = 0; i < 100; i++) {
1048                 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
1049                         break;
1050                 udelay(10);
1051         }
1052 }
1053
1054 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
1055 {
1056         u32 value = ~0x00;
1057         unsigned int i;
1058
1059         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
1060                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1061
1062         for (i = 0; i < 100; i++) {
1063                 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
1064                         value = RTL_R32(CSIDR);
1065                         break;
1066                 }
1067                 udelay(10);
1068         }
1069
1070         return value;
1071 }
1072
1073 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
1074 {
1075         u8 value = 0xff;
1076         unsigned int i;
1077
1078         RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1079
1080         for (i = 0; i < 300; i++) {
1081                 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
1082                         value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
1083                         break;
1084                 }
1085                 udelay(100);
1086         }
1087
1088         return value;
1089 }
1090
1091 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
1092 {
1093         RTL_W16(IntrMask, 0x0000);
1094
1095         RTL_W16(IntrStatus, 0xffff);
1096 }
1097
1098 static void rtl8169_asic_down(void __iomem *ioaddr)
1099 {
1100         RTL_W8(ChipCmd, 0x00);
1101         rtl8169_irq_mask_and_ack(ioaddr);
1102         RTL_R16(CPlusCmd);
1103 }
1104
1105 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1106 {
1107         void __iomem *ioaddr = tp->mmio_addr;
1108
1109         return RTL_R32(TBICSR) & TBIReset;
1110 }
1111
1112 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1113 {
1114         return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1115 }
1116
1117 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1118 {
1119         return RTL_R32(TBICSR) & TBILinkOk;
1120 }
1121
1122 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1123 {
1124         return RTL_R8(PHYstatus) & LinkStatus;
1125 }
1126
1127 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1128 {
1129         void __iomem *ioaddr = tp->mmio_addr;
1130
1131         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1132 }
1133
1134 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1135 {
1136         unsigned int val;
1137
1138         val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1139         rtl_writephy(tp, MII_BMCR, val & 0xffff);
1140 }
1141
1142 static void __rtl8169_check_link_status(struct net_device *dev,
1143                                         struct rtl8169_private *tp,
1144                                         void __iomem *ioaddr, bool pm)
1145 {
1146         unsigned long flags;
1147
1148         spin_lock_irqsave(&tp->lock, flags);
1149         if (tp->link_ok(ioaddr)) {
1150                 /* This is to cancel a scheduled suspend if there's one. */
1151                 if (pm)
1152                         pm_request_resume(&tp->pci_dev->dev);
1153                 netif_carrier_on(dev);
1154                 if (net_ratelimit())
1155                         netif_info(tp, ifup, dev, "link up\n");
1156         } else {
1157                 netif_carrier_off(dev);
1158                 netif_info(tp, ifdown, dev, "link down\n");
1159                 if (pm)
1160                         pm_schedule_suspend(&tp->pci_dev->dev, 5000);
1161         }
1162         spin_unlock_irqrestore(&tp->lock, flags);
1163 }
1164
1165 static void rtl8169_check_link_status(struct net_device *dev,
1166                                       struct rtl8169_private *tp,
1167                                       void __iomem *ioaddr)
1168 {
1169         __rtl8169_check_link_status(dev, tp, ioaddr, false);
1170 }
1171
1172 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1173
1174 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1175 {
1176         void __iomem *ioaddr = tp->mmio_addr;
1177         u8 options;
1178         u32 wolopts = 0;
1179
1180         options = RTL_R8(Config1);
1181         if (!(options & PMEnable))
1182                 return 0;
1183
1184         options = RTL_R8(Config3);
1185         if (options & LinkUp)
1186                 wolopts |= WAKE_PHY;
1187         if (options & MagicPacket)
1188                 wolopts |= WAKE_MAGIC;
1189
1190         options = RTL_R8(Config5);
1191         if (options & UWF)
1192                 wolopts |= WAKE_UCAST;
1193         if (options & BWF)
1194                 wolopts |= WAKE_BCAST;
1195         if (options & MWF)
1196                 wolopts |= WAKE_MCAST;
1197
1198         return wolopts;
1199 }
1200
1201 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1202 {
1203         struct rtl8169_private *tp = netdev_priv(dev);
1204
1205         spin_lock_irq(&tp->lock);
1206
1207         wol->supported = WAKE_ANY;
1208         wol->wolopts = __rtl8169_get_wol(tp);
1209
1210         spin_unlock_irq(&tp->lock);
1211 }
1212
1213 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1214 {
1215         void __iomem *ioaddr = tp->mmio_addr;
1216         unsigned int i;
1217         static const struct {
1218                 u32 opt;
1219                 u16 reg;
1220                 u8  mask;
1221         } cfg[] = {
1222                 { WAKE_ANY,   Config1, PMEnable },
1223                 { WAKE_PHY,   Config3, LinkUp },
1224                 { WAKE_MAGIC, Config3, MagicPacket },
1225                 { WAKE_UCAST, Config5, UWF },
1226                 { WAKE_BCAST, Config5, BWF },
1227                 { WAKE_MCAST, Config5, MWF },
1228                 { WAKE_ANY,   Config5, LanWake }
1229         };
1230
1231         RTL_W8(Cfg9346, Cfg9346_Unlock);
1232
1233         for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1234                 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1235                 if (wolopts & cfg[i].opt)
1236                         options |= cfg[i].mask;
1237                 RTL_W8(cfg[i].reg, options);
1238         }
1239
1240         RTL_W8(Cfg9346, Cfg9346_Lock);
1241 }
1242
1243 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1244 {
1245         struct rtl8169_private *tp = netdev_priv(dev);
1246
1247         spin_lock_irq(&tp->lock);
1248
1249         if (wol->wolopts)
1250                 tp->features |= RTL_FEATURE_WOL;
1251         else
1252                 tp->features &= ~RTL_FEATURE_WOL;
1253         __rtl8169_set_wol(tp, wol->wolopts);
1254         spin_unlock_irq(&tp->lock);
1255
1256         device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1257
1258         return 0;
1259 }
1260
1261 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1262 {
1263         return rtl_chip_infos[tp->mac_version].fw_name;
1264 }
1265
1266 static void rtl8169_get_drvinfo(struct net_device *dev,
1267                                 struct ethtool_drvinfo *info)
1268 {
1269         struct rtl8169_private *tp = netdev_priv(dev);
1270
1271         strcpy(info->driver, MODULENAME);
1272         strcpy(info->version, RTL8169_VERSION);
1273         strcpy(info->bus_info, pci_name(tp->pci_dev));
1274         strncpy(info->fw_version, IS_ERR_OR_NULL(tp->fw) ? "N/A" :
1275                 rtl_lookup_firmware_name(tp), sizeof(info->fw_version) - 1);
1276 }
1277
1278 static int rtl8169_get_regs_len(struct net_device *dev)
1279 {
1280         return R8169_REGS_SIZE;
1281 }
1282
1283 static int rtl8169_set_speed_tbi(struct net_device *dev,
1284                                  u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1285 {
1286         struct rtl8169_private *tp = netdev_priv(dev);
1287         void __iomem *ioaddr = tp->mmio_addr;
1288         int ret = 0;
1289         u32 reg;
1290
1291         reg = RTL_R32(TBICSR);
1292         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1293             (duplex == DUPLEX_FULL)) {
1294                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1295         } else if (autoneg == AUTONEG_ENABLE)
1296                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1297         else {
1298                 netif_warn(tp, link, dev,
1299                            "incorrect speed setting refused in TBI mode\n");
1300                 ret = -EOPNOTSUPP;
1301         }
1302
1303         return ret;
1304 }
1305
1306 static int rtl8169_set_speed_xmii(struct net_device *dev,
1307                                   u8 autoneg, u16 speed, u8 duplex, u32 adv)
1308 {
1309         struct rtl8169_private *tp = netdev_priv(dev);
1310         int giga_ctrl, bmcr;
1311         int rc = -EINVAL;
1312
1313         rtl_writephy(tp, 0x1f, 0x0000);
1314
1315         if (autoneg == AUTONEG_ENABLE) {
1316                 int auto_nego;
1317
1318                 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1319                 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1320                                 ADVERTISE_100HALF | ADVERTISE_100FULL);
1321
1322                 if (adv & ADVERTISED_10baseT_Half)
1323                         auto_nego |= ADVERTISE_10HALF;
1324                 if (adv & ADVERTISED_10baseT_Full)
1325                         auto_nego |= ADVERTISE_10FULL;
1326                 if (adv & ADVERTISED_100baseT_Half)
1327                         auto_nego |= ADVERTISE_100HALF;
1328                 if (adv & ADVERTISED_100baseT_Full)
1329                         auto_nego |= ADVERTISE_100FULL;
1330
1331                 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1332
1333                 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1334                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1335
1336                 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1337                 if (tp->mii.supports_gmii) {
1338                         if (adv & ADVERTISED_1000baseT_Half)
1339                                 giga_ctrl |= ADVERTISE_1000HALF;
1340                         if (adv & ADVERTISED_1000baseT_Full)
1341                                 giga_ctrl |= ADVERTISE_1000FULL;
1342                 } else if (adv & (ADVERTISED_1000baseT_Half |
1343                                   ADVERTISED_1000baseT_Full)) {
1344                         netif_info(tp, link, dev,
1345                                    "PHY does not support 1000Mbps\n");
1346                         goto out;
1347                 }
1348
1349                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1350
1351                 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1352                 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1353         } else {
1354                 giga_ctrl = 0;
1355
1356                 if (speed == SPEED_10)
1357                         bmcr = 0;
1358                 else if (speed == SPEED_100)
1359                         bmcr = BMCR_SPEED100;
1360                 else
1361                         goto out;
1362
1363                 if (duplex == DUPLEX_FULL)
1364                         bmcr |= BMCR_FULLDPLX;
1365         }
1366
1367         rtl_writephy(tp, MII_BMCR, bmcr);
1368
1369         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1370             tp->mac_version == RTL_GIGA_MAC_VER_03) {
1371                 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1372                         rtl_writephy(tp, 0x17, 0x2138);
1373                         rtl_writephy(tp, 0x0e, 0x0260);
1374                 } else {
1375                         rtl_writephy(tp, 0x17, 0x2108);
1376                         rtl_writephy(tp, 0x0e, 0x0000);
1377                 }
1378         }
1379
1380         rc = 0;
1381 out:
1382         return rc;
1383 }
1384
1385 static int rtl8169_set_speed(struct net_device *dev,
1386                              u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1387 {
1388         struct rtl8169_private *tp = netdev_priv(dev);
1389         int ret;
1390
1391         ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1392         if (ret < 0)
1393                 goto out;
1394
1395         if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1396             (advertising & ADVERTISED_1000baseT_Full)) {
1397                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1398         }
1399 out:
1400         return ret;
1401 }
1402
1403 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1404 {
1405         struct rtl8169_private *tp = netdev_priv(dev);
1406         unsigned long flags;
1407         int ret;
1408
1409         del_timer_sync(&tp->timer);
1410
1411         spin_lock_irqsave(&tp->lock, flags);
1412         ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
1413                                 cmd->duplex, cmd->advertising);
1414         spin_unlock_irqrestore(&tp->lock, flags);
1415
1416         return ret;
1417 }
1418
1419 static u32 rtl8169_fix_features(struct net_device *dev, u32 features)
1420 {
1421         struct rtl8169_private *tp = netdev_priv(dev);
1422
1423         if (dev->mtu > TD_MSS_MAX)
1424                 features &= ~NETIF_F_ALL_TSO;
1425
1426         if (dev->mtu > JUMBO_1K &&
1427             !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1428                 features &= ~NETIF_F_IP_CSUM;
1429
1430         return features;
1431 }
1432
1433 static int rtl8169_set_features(struct net_device *dev, u32 features)
1434 {
1435         struct rtl8169_private *tp = netdev_priv(dev);
1436         void __iomem *ioaddr = tp->mmio_addr;
1437         unsigned long flags;
1438
1439         spin_lock_irqsave(&tp->lock, flags);
1440
1441         if (features & NETIF_F_RXCSUM)
1442                 tp->cp_cmd |= RxChkSum;
1443         else
1444                 tp->cp_cmd &= ~RxChkSum;
1445
1446         if (dev->features & NETIF_F_HW_VLAN_RX)
1447                 tp->cp_cmd |= RxVlan;
1448         else
1449                 tp->cp_cmd &= ~RxVlan;
1450
1451         RTL_W16(CPlusCmd, tp->cp_cmd);
1452         RTL_R16(CPlusCmd);
1453
1454         spin_unlock_irqrestore(&tp->lock, flags);
1455
1456         return 0;
1457 }
1458
1459 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1460                                       struct sk_buff *skb)
1461 {
1462         return (vlan_tx_tag_present(skb)) ?
1463                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1464 }
1465
1466 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1467 {
1468         u32 opts2 = le32_to_cpu(desc->opts2);
1469
1470         if (opts2 & RxVlanTag)
1471                 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
1472
1473         desc->opts2 = 0;
1474 }
1475
1476 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1477 {
1478         struct rtl8169_private *tp = netdev_priv(dev);
1479         void __iomem *ioaddr = tp->mmio_addr;
1480         u32 status;
1481
1482         cmd->supported =
1483                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1484         cmd->port = PORT_FIBRE;
1485         cmd->transceiver = XCVR_INTERNAL;
1486
1487         status = RTL_R32(TBICSR);
1488         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
1489         cmd->autoneg = !!(status & TBINwEnable);
1490
1491         ethtool_cmd_speed_set(cmd, SPEED_1000);
1492         cmd->duplex = DUPLEX_FULL; /* Always set */
1493
1494         return 0;
1495 }
1496
1497 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1498 {
1499         struct rtl8169_private *tp = netdev_priv(dev);
1500
1501         return mii_ethtool_gset(&tp->mii, cmd);
1502 }
1503
1504 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1505 {
1506         struct rtl8169_private *tp = netdev_priv(dev);
1507         unsigned long flags;
1508         int rc;
1509
1510         spin_lock_irqsave(&tp->lock, flags);
1511
1512         rc = tp->get_settings(dev, cmd);
1513
1514         spin_unlock_irqrestore(&tp->lock, flags);
1515         return rc;
1516 }
1517
1518 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1519                              void *p)
1520 {
1521         struct rtl8169_private *tp = netdev_priv(dev);
1522         unsigned long flags;
1523
1524         if (regs->len > R8169_REGS_SIZE)
1525                 regs->len = R8169_REGS_SIZE;
1526
1527         spin_lock_irqsave(&tp->lock, flags);
1528         memcpy_fromio(p, tp->mmio_addr, regs->len);
1529         spin_unlock_irqrestore(&tp->lock, flags);
1530 }
1531
1532 static u32 rtl8169_get_msglevel(struct net_device *dev)
1533 {
1534         struct rtl8169_private *tp = netdev_priv(dev);
1535
1536         return tp->msg_enable;
1537 }
1538
1539 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1540 {
1541         struct rtl8169_private *tp = netdev_priv(dev);
1542
1543         tp->msg_enable = value;
1544 }
1545
1546 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1547         "tx_packets",
1548         "rx_packets",
1549         "tx_errors",
1550         "rx_errors",
1551         "rx_missed",
1552         "align_errors",
1553         "tx_single_collisions",
1554         "tx_multi_collisions",
1555         "unicast",
1556         "broadcast",
1557         "multicast",
1558         "tx_aborted",
1559         "tx_underrun",
1560 };
1561
1562 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1563 {
1564         switch (sset) {
1565         case ETH_SS_STATS:
1566                 return ARRAY_SIZE(rtl8169_gstrings);
1567         default:
1568                 return -EOPNOTSUPP;
1569         }
1570 }
1571
1572 static void rtl8169_update_counters(struct net_device *dev)
1573 {
1574         struct rtl8169_private *tp = netdev_priv(dev);
1575         void __iomem *ioaddr = tp->mmio_addr;
1576         struct device *d = &tp->pci_dev->dev;
1577         struct rtl8169_counters *counters;
1578         dma_addr_t paddr;
1579         u32 cmd;
1580         int wait = 1000;
1581
1582         /*
1583          * Some chips are unable to dump tally counters when the receiver
1584          * is disabled.
1585          */
1586         if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1587                 return;
1588
1589         counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1590         if (!counters)
1591                 return;
1592
1593         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1594         cmd = (u64)paddr & DMA_BIT_MASK(32);
1595         RTL_W32(CounterAddrLow, cmd);
1596         RTL_W32(CounterAddrLow, cmd | CounterDump);
1597
1598         while (wait--) {
1599                 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1600                         memcpy(&tp->counters, counters, sizeof(*counters));
1601                         break;
1602                 }
1603                 udelay(10);
1604         }
1605
1606         RTL_W32(CounterAddrLow, 0);
1607         RTL_W32(CounterAddrHigh, 0);
1608
1609         dma_free_coherent(d, sizeof(*counters), counters, paddr);
1610 }
1611
1612 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1613                                       struct ethtool_stats *stats, u64 *data)
1614 {
1615         struct rtl8169_private *tp = netdev_priv(dev);
1616
1617         ASSERT_RTNL();
1618
1619         rtl8169_update_counters(dev);
1620
1621         data[0] = le64_to_cpu(tp->counters.tx_packets);
1622         data[1] = le64_to_cpu(tp->counters.rx_packets);
1623         data[2] = le64_to_cpu(tp->counters.tx_errors);
1624         data[3] = le32_to_cpu(tp->counters.rx_errors);
1625         data[4] = le16_to_cpu(tp->counters.rx_missed);
1626         data[5] = le16_to_cpu(tp->counters.align_errors);
1627         data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1628         data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1629         data[8] = le64_to_cpu(tp->counters.rx_unicast);
1630         data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1631         data[10] = le32_to_cpu(tp->counters.rx_multicast);
1632         data[11] = le16_to_cpu(tp->counters.tx_aborted);
1633         data[12] = le16_to_cpu(tp->counters.tx_underun);
1634 }
1635
1636 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1637 {
1638         switch(stringset) {
1639         case ETH_SS_STATS:
1640                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1641                 break;
1642         }
1643 }
1644
1645 static const struct ethtool_ops rtl8169_ethtool_ops = {
1646         .get_drvinfo            = rtl8169_get_drvinfo,
1647         .get_regs_len           = rtl8169_get_regs_len,
1648         .get_link               = ethtool_op_get_link,
1649         .get_settings           = rtl8169_get_settings,
1650         .set_settings           = rtl8169_set_settings,
1651         .get_msglevel           = rtl8169_get_msglevel,
1652         .set_msglevel           = rtl8169_set_msglevel,
1653         .get_regs               = rtl8169_get_regs,
1654         .get_wol                = rtl8169_get_wol,
1655         .set_wol                = rtl8169_set_wol,
1656         .get_strings            = rtl8169_get_strings,
1657         .get_sset_count         = rtl8169_get_sset_count,
1658         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1659 };
1660
1661 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1662                                     struct net_device *dev, u8 default_version)
1663 {
1664         void __iomem *ioaddr = tp->mmio_addr;
1665         /*
1666          * The driver currently handles the 8168Bf and the 8168Be identically
1667          * but they can be identified more specifically through the test below
1668          * if needed:
1669          *
1670          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1671          *
1672          * Same thing for the 8101Eb and the 8101Ec:
1673          *
1674          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1675          */
1676         static const struct rtl_mac_info {
1677                 u32 mask;
1678                 u32 val;
1679                 int mac_version;
1680         } mac_info[] = {
1681                 /* 8168E family. */
1682                 { 0x7cf00000, 0x2c200000,       RTL_GIGA_MAC_VER_33 },
1683                 { 0x7cf00000, 0x2c100000,       RTL_GIGA_MAC_VER_32 },
1684                 { 0x7c800000, 0x2c000000,       RTL_GIGA_MAC_VER_33 },
1685
1686                 /* 8168D family. */
1687                 { 0x7cf00000, 0x28300000,       RTL_GIGA_MAC_VER_26 },
1688                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
1689                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
1690
1691                 /* 8168DP family. */
1692                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
1693                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
1694                 { 0x7cf00000, 0x28b00000,       RTL_GIGA_MAC_VER_31 },
1695
1696                 /* 8168C family. */
1697                 { 0x7cf00000, 0x3cb00000,       RTL_GIGA_MAC_VER_24 },
1698                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
1699                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
1700                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
1701                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
1702                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
1703                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
1704                 { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
1705                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
1706
1707                 /* 8168B family. */
1708                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
1709                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
1710                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
1711                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
1712
1713                 /* 8101 family. */
1714                 { 0x7cf00000, 0x40b00000,       RTL_GIGA_MAC_VER_30 },
1715                 { 0x7cf00000, 0x40a00000,       RTL_GIGA_MAC_VER_30 },
1716                 { 0x7cf00000, 0x40900000,       RTL_GIGA_MAC_VER_29 },
1717                 { 0x7c800000, 0x40800000,       RTL_GIGA_MAC_VER_30 },
1718                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
1719                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
1720                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
1721                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
1722                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
1723                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
1724                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
1725                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
1726                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
1727                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
1728                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
1729                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
1730                 /* FIXME: where did these entries come from ? -- FR */
1731                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
1732                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
1733
1734                 /* 8110 family. */
1735                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
1736                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
1737                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
1738                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
1739                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
1740                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
1741
1742                 /* Catch-all */
1743                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
1744         };
1745         const struct rtl_mac_info *p = mac_info;
1746         u32 reg;
1747
1748         reg = RTL_R32(TxConfig);
1749         while ((reg & p->mask) != p->val)
1750                 p++;
1751         tp->mac_version = p->mac_version;
1752
1753         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
1754                 netif_notice(tp, probe, dev,
1755                              "unknown MAC, using family default\n");
1756                 tp->mac_version = default_version;
1757         }
1758 }
1759
1760 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1761 {
1762         dprintk("mac_version = 0x%02x\n", tp->mac_version);
1763 }
1764
1765 struct phy_reg {
1766         u16 reg;
1767         u16 val;
1768 };
1769
1770 static void rtl_writephy_batch(struct rtl8169_private *tp,
1771                                const struct phy_reg *regs, int len)
1772 {
1773         while (len-- > 0) {
1774                 rtl_writephy(tp, regs->reg, regs->val);
1775                 regs++;
1776         }
1777 }
1778
1779 #define PHY_READ                0x00000000
1780 #define PHY_DATA_OR             0x10000000
1781 #define PHY_DATA_AND            0x20000000
1782 #define PHY_BJMPN               0x30000000
1783 #define PHY_READ_EFUSE          0x40000000
1784 #define PHY_READ_MAC_BYTE       0x50000000
1785 #define PHY_WRITE_MAC_BYTE      0x60000000
1786 #define PHY_CLEAR_READCOUNT     0x70000000
1787 #define PHY_WRITE               0x80000000
1788 #define PHY_READCOUNT_EQ_SKIP   0x90000000
1789 #define PHY_COMP_EQ_SKIPN       0xa0000000
1790 #define PHY_COMP_NEQ_SKIPN      0xb0000000
1791 #define PHY_WRITE_PREVIOUS      0xc0000000
1792 #define PHY_SKIPN               0xd0000000
1793 #define PHY_DELAY_MS            0xe0000000
1794 #define PHY_WRITE_ERI_WORD      0xf0000000
1795
1796 static void
1797 rtl_phy_write_fw(struct rtl8169_private *tp, const struct firmware *fw)
1798 {
1799         __le32 *phytable = (__le32 *)fw->data;
1800         struct net_device *dev = tp->dev;
1801         size_t index, fw_size = fw->size / sizeof(*phytable);
1802         u32 predata, count;
1803
1804         if (fw->size % sizeof(*phytable)) {
1805                 netif_err(tp, probe, dev, "odd sized firmware %zd\n", fw->size);
1806                 return;
1807         }
1808
1809         for (index = 0; index < fw_size; index++) {
1810                 u32 action = le32_to_cpu(phytable[index]);
1811                 u32 regno = (action & 0x0fff0000) >> 16;
1812
1813                 switch(action & 0xf0000000) {
1814                 case PHY_READ:
1815                 case PHY_DATA_OR:
1816                 case PHY_DATA_AND:
1817                 case PHY_READ_EFUSE:
1818                 case PHY_CLEAR_READCOUNT:
1819                 case PHY_WRITE:
1820                 case PHY_WRITE_PREVIOUS:
1821                 case PHY_DELAY_MS:
1822                         break;
1823
1824                 case PHY_BJMPN:
1825                         if (regno > index) {
1826                                 netif_err(tp, probe, tp->dev,
1827                                           "Out of range of firmware\n");
1828                                 return;
1829                         }
1830                         break;
1831                 case PHY_READCOUNT_EQ_SKIP:
1832                         if (index + 2 >= fw_size) {
1833                                 netif_err(tp, probe, tp->dev,
1834                                           "Out of range of firmware\n");
1835                                 return;
1836                         }
1837                         break;
1838                 case PHY_COMP_EQ_SKIPN:
1839                 case PHY_COMP_NEQ_SKIPN:
1840                 case PHY_SKIPN:
1841                         if (index + 1 + regno >= fw_size) {
1842                                 netif_err(tp, probe, tp->dev,
1843                                           "Out of range of firmware\n");
1844                                 return;
1845                         }
1846                         break;
1847
1848                 case PHY_READ_MAC_BYTE:
1849                 case PHY_WRITE_MAC_BYTE:
1850                 case PHY_WRITE_ERI_WORD:
1851                 default:
1852                         netif_err(tp, probe, tp->dev,
1853                                   "Invalid action 0x%08x\n", action);
1854                         return;
1855                 }
1856         }
1857
1858         predata = 0;
1859         count = 0;
1860
1861         for (index = 0; index < fw_size; ) {
1862                 u32 action = le32_to_cpu(phytable[index]);
1863                 u32 data = action & 0x0000ffff;
1864                 u32 regno = (action & 0x0fff0000) >> 16;
1865
1866                 if (!action)
1867                         break;
1868
1869                 switch(action & 0xf0000000) {
1870                 case PHY_READ:
1871                         predata = rtl_readphy(tp, regno);
1872                         count++;
1873                         index++;
1874                         break;
1875                 case PHY_DATA_OR:
1876                         predata |= data;
1877                         index++;
1878                         break;
1879                 case PHY_DATA_AND:
1880                         predata &= data;
1881                         index++;
1882                         break;
1883                 case PHY_BJMPN:
1884                         index -= regno;
1885                         break;
1886                 case PHY_READ_EFUSE:
1887                         predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
1888                         index++;
1889                         break;
1890                 case PHY_CLEAR_READCOUNT:
1891                         count = 0;
1892                         index++;
1893                         break;
1894                 case PHY_WRITE:
1895                         rtl_writephy(tp, regno, data);
1896                         index++;
1897                         break;
1898                 case PHY_READCOUNT_EQ_SKIP:
1899                         index += (count == data) ? 2 : 1;
1900                         break;
1901                 case PHY_COMP_EQ_SKIPN:
1902                         if (predata == data)
1903                                 index += regno;
1904                         index++;
1905                         break;
1906                 case PHY_COMP_NEQ_SKIPN:
1907                         if (predata != data)
1908                                 index += regno;
1909                         index++;
1910                         break;
1911                 case PHY_WRITE_PREVIOUS:
1912                         rtl_writephy(tp, regno, predata);
1913                         index++;
1914                         break;
1915                 case PHY_SKIPN:
1916                         index += regno + 1;
1917                         break;
1918                 case PHY_DELAY_MS:
1919                         mdelay(data);
1920                         index++;
1921                         break;
1922
1923                 case PHY_READ_MAC_BYTE:
1924                 case PHY_WRITE_MAC_BYTE:
1925                 case PHY_WRITE_ERI_WORD:
1926                 default:
1927                         BUG();
1928                 }
1929         }
1930 }
1931
1932 static void rtl_release_firmware(struct rtl8169_private *tp)
1933 {
1934         if (!IS_ERR_OR_NULL(tp->fw))
1935                 release_firmware(tp->fw);
1936         tp->fw = RTL_FIRMWARE_UNKNOWN;
1937 }
1938
1939 static void rtl_apply_firmware(struct rtl8169_private *tp)
1940 {
1941         const struct firmware *fw = tp->fw;
1942
1943         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
1944         if (!IS_ERR_OR_NULL(fw))
1945                 rtl_phy_write_fw(tp, fw);
1946 }
1947
1948 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
1949 {
1950         if (rtl_readphy(tp, reg) != val)
1951                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
1952         else
1953                 rtl_apply_firmware(tp);
1954 }
1955
1956 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1957 {
1958         static const struct phy_reg phy_reg_init[] = {
1959                 { 0x1f, 0x0001 },
1960                 { 0x06, 0x006e },
1961                 { 0x08, 0x0708 },
1962                 { 0x15, 0x4000 },
1963                 { 0x18, 0x65c7 },
1964
1965                 { 0x1f, 0x0001 },
1966                 { 0x03, 0x00a1 },
1967                 { 0x02, 0x0008 },
1968                 { 0x01, 0x0120 },
1969                 { 0x00, 0x1000 },
1970                 { 0x04, 0x0800 },
1971                 { 0x04, 0x0000 },
1972
1973                 { 0x03, 0xff41 },
1974                 { 0x02, 0xdf60 },
1975                 { 0x01, 0x0140 },
1976                 { 0x00, 0x0077 },
1977                 { 0x04, 0x7800 },
1978                 { 0x04, 0x7000 },
1979
1980                 { 0x03, 0x802f },
1981                 { 0x02, 0x4f02 },
1982                 { 0x01, 0x0409 },
1983                 { 0x00, 0xf0f9 },
1984                 { 0x04, 0x9800 },
1985                 { 0x04, 0x9000 },
1986
1987                 { 0x03, 0xdf01 },
1988                 { 0x02, 0xdf20 },
1989                 { 0x01, 0xff95 },
1990                 { 0x00, 0xba00 },
1991                 { 0x04, 0xa800 },
1992                 { 0x04, 0xa000 },
1993
1994                 { 0x03, 0xff41 },
1995                 { 0x02, 0xdf20 },
1996                 { 0x01, 0x0140 },
1997                 { 0x00, 0x00bb },
1998                 { 0x04, 0xb800 },
1999                 { 0x04, 0xb000 },
2000
2001                 { 0x03, 0xdf41 },
2002                 { 0x02, 0xdc60 },
2003                 { 0x01, 0x6340 },
2004                 { 0x00, 0x007d },
2005                 { 0x04, 0xd800 },
2006                 { 0x04, 0xd000 },
2007
2008                 { 0x03, 0xdf01 },
2009                 { 0x02, 0xdf20 },
2010                 { 0x01, 0x100a },
2011                 { 0x00, 0xa0ff },
2012                 { 0x04, 0xf800 },
2013                 { 0x04, 0xf000 },
2014
2015                 { 0x1f, 0x0000 },
2016                 { 0x0b, 0x0000 },
2017                 { 0x00, 0x9200 }
2018         };
2019
2020         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2021 }
2022
2023 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2024 {
2025         static const struct phy_reg phy_reg_init[] = {
2026                 { 0x1f, 0x0002 },
2027                 { 0x01, 0x90d0 },
2028                 { 0x1f, 0x0000 }
2029         };
2030
2031         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2032 }
2033
2034 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2035 {
2036         struct pci_dev *pdev = tp->pci_dev;
2037         u16 vendor_id, device_id;
2038
2039         pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
2040         pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
2041
2042         if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
2043                 return;
2044
2045         rtl_writephy(tp, 0x1f, 0x0001);
2046         rtl_writephy(tp, 0x10, 0xf01b);
2047         rtl_writephy(tp, 0x1f, 0x0000);
2048 }
2049
2050 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2051 {
2052         static const struct phy_reg phy_reg_init[] = {
2053                 { 0x1f, 0x0001 },
2054                 { 0x04, 0x0000 },
2055                 { 0x03, 0x00a1 },
2056                 { 0x02, 0x0008 },
2057                 { 0x01, 0x0120 },
2058                 { 0x00, 0x1000 },
2059                 { 0x04, 0x0800 },
2060                 { 0x04, 0x9000 },
2061                 { 0x03, 0x802f },
2062                 { 0x02, 0x4f02 },
2063                 { 0x01, 0x0409 },
2064                 { 0x00, 0xf099 },
2065                 { 0x04, 0x9800 },
2066                 { 0x04, 0xa000 },
2067                 { 0x03, 0xdf01 },
2068                 { 0x02, 0xdf20 },
2069                 { 0x01, 0xff95 },
2070                 { 0x00, 0xba00 },
2071                 { 0x04, 0xa800 },
2072                 { 0x04, 0xf000 },
2073                 { 0x03, 0xdf01 },
2074                 { 0x02, 0xdf20 },
2075                 { 0x01, 0x101a },
2076                 { 0x00, 0xa0ff },
2077                 { 0x04, 0xf800 },
2078                 { 0x04, 0x0000 },
2079                 { 0x1f, 0x0000 },
2080
2081                 { 0x1f, 0x0001 },
2082                 { 0x10, 0xf41b },
2083                 { 0x14, 0xfb54 },
2084                 { 0x18, 0xf5c7 },
2085                 { 0x1f, 0x0000 },
2086
2087                 { 0x1f, 0x0001 },
2088                 { 0x17, 0x0cc0 },
2089                 { 0x1f, 0x0000 }
2090         };
2091
2092         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2093
2094         rtl8169scd_hw_phy_config_quirk(tp);
2095 }
2096
2097 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2098 {
2099         static const struct phy_reg phy_reg_init[] = {
2100                 { 0x1f, 0x0001 },
2101                 { 0x04, 0x0000 },
2102                 { 0x03, 0x00a1 },
2103                 { 0x02, 0x0008 },
2104                 { 0x01, 0x0120 },
2105                 { 0x00, 0x1000 },
2106                 { 0x04, 0x0800 },
2107                 { 0x04, 0x9000 },
2108                 { 0x03, 0x802f },
2109                 { 0x02, 0x4f02 },
2110                 { 0x01, 0x0409 },
2111                 { 0x00, 0xf099 },
2112                 { 0x04, 0x9800 },
2113                 { 0x04, 0xa000 },
2114                 { 0x03, 0xdf01 },
2115                 { 0x02, 0xdf20 },
2116                 { 0x01, 0xff95 },
2117                 { 0x00, 0xba00 },
2118                 { 0x04, 0xa800 },
2119                 { 0x04, 0xf000 },
2120                 { 0x03, 0xdf01 },
2121                 { 0x02, 0xdf20 },
2122                 { 0x01, 0x101a },
2123                 { 0x00, 0xa0ff },
2124                 { 0x04, 0xf800 },
2125                 { 0x04, 0x0000 },
2126                 { 0x1f, 0x0000 },
2127
2128                 { 0x1f, 0x0001 },
2129                 { 0x0b, 0x8480 },
2130                 { 0x1f, 0x0000 },
2131
2132                 { 0x1f, 0x0001 },
2133                 { 0x18, 0x67c7 },
2134                 { 0x04, 0x2000 },
2135                 { 0x03, 0x002f },
2136                 { 0x02, 0x4360 },
2137                 { 0x01, 0x0109 },
2138                 { 0x00, 0x3022 },
2139                 { 0x04, 0x2800 },
2140                 { 0x1f, 0x0000 },
2141
2142                 { 0x1f, 0x0001 },
2143                 { 0x17, 0x0cc0 },
2144                 { 0x1f, 0x0000 }
2145         };
2146
2147         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2148 }
2149
2150 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2151 {
2152         static const struct phy_reg phy_reg_init[] = {
2153                 { 0x10, 0xf41b },
2154                 { 0x1f, 0x0000 }
2155         };
2156
2157         rtl_writephy(tp, 0x1f, 0x0001);
2158         rtl_patchphy(tp, 0x16, 1 << 0);
2159
2160         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2161 }
2162
2163 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2164 {
2165         static const struct phy_reg phy_reg_init[] = {
2166                 { 0x1f, 0x0001 },
2167                 { 0x10, 0xf41b },
2168                 { 0x1f, 0x0000 }
2169         };
2170
2171         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2172 }
2173
2174 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2175 {
2176         static const struct phy_reg phy_reg_init[] = {
2177                 { 0x1f, 0x0000 },
2178                 { 0x1d, 0x0f00 },
2179                 { 0x1f, 0x0002 },
2180                 { 0x0c, 0x1ec8 },
2181                 { 0x1f, 0x0000 }
2182         };
2183
2184         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2185 }
2186
2187 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2188 {
2189         static const struct phy_reg phy_reg_init[] = {
2190                 { 0x1f, 0x0001 },
2191                 { 0x1d, 0x3d98 },
2192                 { 0x1f, 0x0000 }
2193         };
2194
2195         rtl_writephy(tp, 0x1f, 0x0000);
2196         rtl_patchphy(tp, 0x14, 1 << 5);
2197         rtl_patchphy(tp, 0x0d, 1 << 5);
2198
2199         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2200 }
2201
2202 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2203 {
2204         static const struct phy_reg phy_reg_init[] = {
2205                 { 0x1f, 0x0001 },
2206                 { 0x12, 0x2300 },
2207                 { 0x1f, 0x0002 },
2208                 { 0x00, 0x88d4 },
2209                 { 0x01, 0x82b1 },
2210                 { 0x03, 0x7002 },
2211                 { 0x08, 0x9e30 },
2212                 { 0x09, 0x01f0 },
2213                 { 0x0a, 0x5500 },
2214                 { 0x0c, 0x00c8 },
2215                 { 0x1f, 0x0003 },
2216                 { 0x12, 0xc096 },
2217                 { 0x16, 0x000a },
2218                 { 0x1f, 0x0000 },
2219                 { 0x1f, 0x0000 },
2220                 { 0x09, 0x2000 },
2221                 { 0x09, 0x0000 }
2222         };
2223
2224         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2225
2226         rtl_patchphy(tp, 0x14, 1 << 5);
2227         rtl_patchphy(tp, 0x0d, 1 << 5);
2228         rtl_writephy(tp, 0x1f, 0x0000);
2229 }
2230
2231 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2232 {
2233         static const struct phy_reg phy_reg_init[] = {
2234                 { 0x1f, 0x0001 },
2235                 { 0x12, 0x2300 },
2236                 { 0x03, 0x802f },
2237                 { 0x02, 0x4f02 },
2238                 { 0x01, 0x0409 },
2239                 { 0x00, 0xf099 },
2240                 { 0x04, 0x9800 },
2241                 { 0x04, 0x9000 },
2242                 { 0x1d, 0x3d98 },
2243                 { 0x1f, 0x0002 },
2244                 { 0x0c, 0x7eb8 },
2245                 { 0x06, 0x0761 },
2246                 { 0x1f, 0x0003 },
2247                 { 0x16, 0x0f0a },
2248                 { 0x1f, 0x0000 }
2249         };
2250
2251         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2252
2253         rtl_patchphy(tp, 0x16, 1 << 0);
2254         rtl_patchphy(tp, 0x14, 1 << 5);
2255         rtl_patchphy(tp, 0x0d, 1 << 5);
2256         rtl_writephy(tp, 0x1f, 0x0000);
2257 }
2258
2259 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2260 {
2261         static const struct phy_reg phy_reg_init[] = {
2262                 { 0x1f, 0x0001 },
2263                 { 0x12, 0x2300 },
2264                 { 0x1d, 0x3d98 },
2265                 { 0x1f, 0x0002 },
2266                 { 0x0c, 0x7eb8 },
2267                 { 0x06, 0x5461 },
2268                 { 0x1f, 0x0003 },
2269                 { 0x16, 0x0f0a },
2270                 { 0x1f, 0x0000 }
2271         };
2272
2273         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2274
2275         rtl_patchphy(tp, 0x16, 1 << 0);
2276         rtl_patchphy(tp, 0x14, 1 << 5);
2277         rtl_patchphy(tp, 0x0d, 1 << 5);
2278         rtl_writephy(tp, 0x1f, 0x0000);
2279 }
2280
2281 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2282 {
2283         rtl8168c_3_hw_phy_config(tp);
2284 }
2285
2286 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2287 {
2288         static const struct phy_reg phy_reg_init_0[] = {
2289                 /* Channel Estimation */
2290                 { 0x1f, 0x0001 },
2291                 { 0x06, 0x4064 },
2292                 { 0x07, 0x2863 },
2293                 { 0x08, 0x059c },
2294                 { 0x09, 0x26b4 },
2295                 { 0x0a, 0x6a19 },
2296                 { 0x0b, 0xdcc8 },
2297                 { 0x10, 0xf06d },
2298                 { 0x14, 0x7f68 },
2299                 { 0x18, 0x7fd9 },
2300                 { 0x1c, 0xf0ff },
2301                 { 0x1d, 0x3d9c },
2302                 { 0x1f, 0x0003 },
2303                 { 0x12, 0xf49f },
2304                 { 0x13, 0x070b },
2305                 { 0x1a, 0x05ad },
2306                 { 0x14, 0x94c0 },
2307
2308                 /*
2309                  * Tx Error Issue
2310                  * Enhance line driver power
2311                  */
2312                 { 0x1f, 0x0002 },
2313                 { 0x06, 0x5561 },
2314                 { 0x1f, 0x0005 },
2315                 { 0x05, 0x8332 },
2316                 { 0x06, 0x5561 },
2317
2318                 /*
2319                  * Can not link to 1Gbps with bad cable
2320                  * Decrease SNR threshold form 21.07dB to 19.04dB
2321                  */
2322                 { 0x1f, 0x0001 },
2323                 { 0x17, 0x0cc0 },
2324
2325                 { 0x1f, 0x0000 },
2326                 { 0x0d, 0xf880 }
2327         };
2328         void __iomem *ioaddr = tp->mmio_addr;
2329
2330         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2331
2332         /*
2333          * Rx Error Issue
2334          * Fine Tune Switching regulator parameter
2335          */
2336         rtl_writephy(tp, 0x1f, 0x0002);
2337         rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2338         rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2339
2340         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2341                 static const struct phy_reg phy_reg_init[] = {
2342                         { 0x1f, 0x0002 },
2343                         { 0x05, 0x669a },
2344                         { 0x1f, 0x0005 },
2345                         { 0x05, 0x8330 },
2346                         { 0x06, 0x669a },
2347                         { 0x1f, 0x0002 }
2348                 };
2349                 int val;
2350
2351                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2352
2353                 val = rtl_readphy(tp, 0x0d);
2354
2355                 if ((val & 0x00ff) != 0x006c) {
2356                         static const u32 set[] = {
2357                                 0x0065, 0x0066, 0x0067, 0x0068,
2358                                 0x0069, 0x006a, 0x006b, 0x006c
2359                         };
2360                         int i;
2361
2362                         rtl_writephy(tp, 0x1f, 0x0002);
2363
2364                         val &= 0xff00;
2365                         for (i = 0; i < ARRAY_SIZE(set); i++)
2366                                 rtl_writephy(tp, 0x0d, val | set[i]);
2367                 }
2368         } else {
2369                 static const struct phy_reg phy_reg_init[] = {
2370                         { 0x1f, 0x0002 },
2371                         { 0x05, 0x6662 },
2372                         { 0x1f, 0x0005 },
2373                         { 0x05, 0x8330 },
2374                         { 0x06, 0x6662 }
2375                 };
2376
2377                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2378         }
2379
2380         /* RSET couple improve */
2381         rtl_writephy(tp, 0x1f, 0x0002);
2382         rtl_patchphy(tp, 0x0d, 0x0300);
2383         rtl_patchphy(tp, 0x0f, 0x0010);
2384
2385         /* Fine tune PLL performance */
2386         rtl_writephy(tp, 0x1f, 0x0002);
2387         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2388         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2389
2390         rtl_writephy(tp, 0x1f, 0x0005);
2391         rtl_writephy(tp, 0x05, 0x001b);
2392
2393         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2394
2395         rtl_writephy(tp, 0x1f, 0x0000);
2396 }
2397
2398 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2399 {
2400         static const struct phy_reg phy_reg_init_0[] = {
2401                 /* Channel Estimation */
2402                 { 0x1f, 0x0001 },
2403                 { 0x06, 0x4064 },
2404                 { 0x07, 0x2863 },
2405                 { 0x08, 0x059c },
2406                 { 0x09, 0x26b4 },
2407                 { 0x0a, 0x6a19 },
2408                 { 0x0b, 0xdcc8 },
2409                 { 0x10, 0xf06d },
2410                 { 0x14, 0x7f68 },
2411                 { 0x18, 0x7fd9 },
2412                 { 0x1c, 0xf0ff },
2413                 { 0x1d, 0x3d9c },
2414                 { 0x1f, 0x0003 },
2415                 { 0x12, 0xf49f },
2416                 { 0x13, 0x070b },
2417                 { 0x1a, 0x05ad },
2418                 { 0x14, 0x94c0 },
2419
2420                 /*
2421                  * Tx Error Issue
2422                  * Enhance line driver power
2423                  */
2424                 { 0x1f, 0x0002 },
2425                 { 0x06, 0x5561 },
2426                 { 0x1f, 0x0005 },
2427                 { 0x05, 0x8332 },
2428                 { 0x06, 0x5561 },
2429
2430                 /*
2431                  * Can not link to 1Gbps with bad cable
2432                  * Decrease SNR threshold form 21.07dB to 19.04dB
2433                  */
2434                 { 0x1f, 0x0001 },
2435                 { 0x17, 0x0cc0 },
2436
2437                 { 0x1f, 0x0000 },
2438                 { 0x0d, 0xf880 }
2439         };
2440         void __iomem *ioaddr = tp->mmio_addr;
2441
2442         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2443
2444         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2445                 static const struct phy_reg phy_reg_init[] = {
2446                         { 0x1f, 0x0002 },
2447                         { 0x05, 0x669a },
2448                         { 0x1f, 0x0005 },
2449                         { 0x05, 0x8330 },
2450                         { 0x06, 0x669a },
2451
2452                         { 0x1f, 0x0002 }
2453                 };
2454                 int val;
2455
2456                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2457
2458                 val = rtl_readphy(tp, 0x0d);
2459                 if ((val & 0x00ff) != 0x006c) {
2460                         static const u32 set[] = {
2461                                 0x0065, 0x0066, 0x0067, 0x0068,
2462                                 0x0069, 0x006a, 0x006b, 0x006c
2463                         };
2464                         int i;
2465
2466                         rtl_writephy(tp, 0x1f, 0x0002);
2467
2468                         val &= 0xff00;
2469                         for (i = 0; i < ARRAY_SIZE(set); i++)
2470                                 rtl_writephy(tp, 0x0d, val | set[i]);
2471                 }
2472         } else {
2473                 static const struct phy_reg phy_reg_init[] = {
2474                         { 0x1f, 0x0002 },
2475                         { 0x05, 0x2642 },
2476                         { 0x1f, 0x0005 },
2477                         { 0x05, 0x8330 },
2478                         { 0x06, 0x2642 }
2479                 };
2480
2481                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2482         }
2483
2484         /* Fine tune PLL performance */
2485         rtl_writephy(tp, 0x1f, 0x0002);
2486         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2487         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2488
2489         /* Switching regulator Slew rate */
2490         rtl_writephy(tp, 0x1f, 0x0002);
2491         rtl_patchphy(tp, 0x0f, 0x0017);
2492
2493         rtl_writephy(tp, 0x1f, 0x0005);
2494         rtl_writephy(tp, 0x05, 0x001b);
2495
2496         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2497
2498         rtl_writephy(tp, 0x1f, 0x0000);
2499 }
2500
2501 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2502 {
2503         static const struct phy_reg phy_reg_init[] = {
2504                 { 0x1f, 0x0002 },
2505                 { 0x10, 0x0008 },
2506                 { 0x0d, 0x006c },
2507
2508                 { 0x1f, 0x0000 },
2509                 { 0x0d, 0xf880 },
2510
2511                 { 0x1f, 0x0001 },
2512                 { 0x17, 0x0cc0 },
2513
2514                 { 0x1f, 0x0001 },
2515                 { 0x0b, 0xa4d8 },
2516                 { 0x09, 0x281c },
2517                 { 0x07, 0x2883 },
2518                 { 0x0a, 0x6b35 },
2519                 { 0x1d, 0x3da4 },
2520                 { 0x1c, 0xeffd },
2521                 { 0x14, 0x7f52 },
2522                 { 0x18, 0x7fc6 },
2523                 { 0x08, 0x0601 },
2524                 { 0x06, 0x4063 },
2525                 { 0x10, 0xf074 },
2526                 { 0x1f, 0x0003 },
2527                 { 0x13, 0x0789 },
2528                 { 0x12, 0xf4bd },
2529                 { 0x1a, 0x04fd },
2530                 { 0x14, 0x84b0 },
2531                 { 0x1f, 0x0000 },
2532                 { 0x00, 0x9200 },
2533
2534                 { 0x1f, 0x0005 },
2535                 { 0x01, 0x0340 },
2536                 { 0x1f, 0x0001 },
2537                 { 0x04, 0x4000 },
2538                 { 0x03, 0x1d21 },
2539                 { 0x02, 0x0c32 },
2540                 { 0x01, 0x0200 },
2541                 { 0x00, 0x5554 },
2542                 { 0x04, 0x4800 },
2543                 { 0x04, 0x4000 },
2544                 { 0x04, 0xf000 },
2545                 { 0x03, 0xdf01 },
2546                 { 0x02, 0xdf20 },
2547                 { 0x01, 0x101a },
2548                 { 0x00, 0xa0ff },
2549                 { 0x04, 0xf800 },
2550                 { 0x04, 0xf000 },
2551                 { 0x1f, 0x0000 },
2552
2553                 { 0x1f, 0x0007 },
2554                 { 0x1e, 0x0023 },
2555                 { 0x16, 0x0000 },
2556                 { 0x1f, 0x0000 }
2557         };
2558
2559         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2560 }
2561
2562 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2563 {
2564         static const struct phy_reg phy_reg_init[] = {
2565                 { 0x1f, 0x0001 },
2566                 { 0x17, 0x0cc0 },
2567
2568                 { 0x1f, 0x0007 },
2569                 { 0x1e, 0x002d },
2570                 { 0x18, 0x0040 },
2571                 { 0x1f, 0x0000 }
2572         };
2573
2574         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2575         rtl_patchphy(tp, 0x0d, 1 << 5);
2576 }
2577
2578 static void rtl8168e_hw_phy_config(struct rtl8169_private *tp)
2579 {
2580         static const struct phy_reg phy_reg_init[] = {
2581                 /* Enable Delay cap */
2582                 { 0x1f, 0x0005 },
2583                 { 0x05, 0x8b80 },
2584                 { 0x06, 0xc896 },
2585                 { 0x1f, 0x0000 },
2586
2587                 /* Channel estimation fine tune */
2588                 { 0x1f, 0x0001 },
2589                 { 0x0b, 0x6c20 },
2590                 { 0x07, 0x2872 },
2591                 { 0x1c, 0xefff },
2592                 { 0x1f, 0x0003 },
2593                 { 0x14, 0x6420 },
2594                 { 0x1f, 0x0000 },
2595
2596                 /* Update PFM & 10M TX idle timer */
2597                 { 0x1f, 0x0007 },
2598                 { 0x1e, 0x002f },
2599                 { 0x15, 0x1919 },
2600                 { 0x1f, 0x0000 },
2601
2602                 { 0x1f, 0x0007 },
2603                 { 0x1e, 0x00ac },
2604                 { 0x18, 0x0006 },
2605                 { 0x1f, 0x0000 }
2606         };
2607
2608         rtl_apply_firmware(tp);
2609
2610         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2611
2612         /* DCO enable for 10M IDLE Power */
2613         rtl_writephy(tp, 0x1f, 0x0007);
2614         rtl_writephy(tp, 0x1e, 0x0023);
2615         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2616         rtl_writephy(tp, 0x1f, 0x0000);
2617
2618         /* For impedance matching */
2619         rtl_writephy(tp, 0x1f, 0x0002);
2620         rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
2621         rtl_writephy(tp, 0x1f, 0x0000);
2622
2623         /* PHY auto speed down */
2624         rtl_writephy(tp, 0x1f, 0x0007);
2625         rtl_writephy(tp, 0x1e, 0x002d);
2626         rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2627         rtl_writephy(tp, 0x1f, 0x0000);
2628         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2629
2630         rtl_writephy(tp, 0x1f, 0x0005);
2631         rtl_writephy(tp, 0x05, 0x8b86);
2632         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2633         rtl_writephy(tp, 0x1f, 0x0000);
2634
2635         rtl_writephy(tp, 0x1f, 0x0005);
2636         rtl_writephy(tp, 0x05, 0x8b85);
2637         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2638         rtl_writephy(tp, 0x1f, 0x0007);
2639         rtl_writephy(tp, 0x1e, 0x0020);
2640         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2641         rtl_writephy(tp, 0x1f, 0x0006);
2642         rtl_writephy(tp, 0x00, 0x5a00);
2643         rtl_writephy(tp, 0x1f, 0x0000);
2644         rtl_writephy(tp, 0x0d, 0x0007);
2645         rtl_writephy(tp, 0x0e, 0x003c);
2646         rtl_writephy(tp, 0x0d, 0x4007);
2647         rtl_writephy(tp, 0x0e, 0x0000);
2648         rtl_writephy(tp, 0x0d, 0x0000);
2649 }
2650
2651 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2652 {
2653         static const struct phy_reg phy_reg_init[] = {
2654                 { 0x1f, 0x0003 },
2655                 { 0x08, 0x441d },
2656                 { 0x01, 0x9100 },
2657                 { 0x1f, 0x0000 }
2658         };
2659
2660         rtl_writephy(tp, 0x1f, 0x0000);
2661         rtl_patchphy(tp, 0x11, 1 << 12);
2662         rtl_patchphy(tp, 0x19, 1 << 13);
2663         rtl_patchphy(tp, 0x10, 1 << 15);
2664
2665         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2666 }
2667
2668 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
2669 {
2670         static const struct phy_reg phy_reg_init[] = {
2671                 { 0x1f, 0x0005 },
2672                 { 0x1a, 0x0000 },
2673                 { 0x1f, 0x0000 },
2674
2675                 { 0x1f, 0x0004 },
2676                 { 0x1c, 0x0000 },
2677                 { 0x1f, 0x0000 },
2678
2679                 { 0x1f, 0x0001 },
2680                 { 0x15, 0x7701 },
2681                 { 0x1f, 0x0000 }
2682         };
2683
2684         /* Disable ALDPS before ram code */
2685         rtl_writephy(tp, 0x1f, 0x0000);
2686         rtl_writephy(tp, 0x18, 0x0310);
2687         msleep(100);
2688
2689         rtl_apply_firmware(tp);
2690
2691         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2692 }
2693
2694 static void rtl_hw_phy_config(struct net_device *dev)
2695 {
2696         struct rtl8169_private *tp = netdev_priv(dev);
2697
2698         rtl8169_print_mac_version(tp);
2699
2700         switch (tp->mac_version) {
2701         case RTL_GIGA_MAC_VER_01:
2702                 break;
2703         case RTL_GIGA_MAC_VER_02:
2704         case RTL_GIGA_MAC_VER_03:
2705                 rtl8169s_hw_phy_config(tp);
2706                 break;
2707         case RTL_GIGA_MAC_VER_04:
2708                 rtl8169sb_hw_phy_config(tp);
2709                 break;
2710         case RTL_GIGA_MAC_VER_05:
2711                 rtl8169scd_hw_phy_config(tp);
2712                 break;
2713         case RTL_GIGA_MAC_VER_06:
2714                 rtl8169sce_hw_phy_config(tp);
2715                 break;
2716         case RTL_GIGA_MAC_VER_07:
2717         case RTL_GIGA_MAC_VER_08:
2718         case RTL_GIGA_MAC_VER_09:
2719                 rtl8102e_hw_phy_config(tp);
2720                 break;
2721         case RTL_GIGA_MAC_VER_11:
2722                 rtl8168bb_hw_phy_config(tp);
2723                 break;
2724         case RTL_GIGA_MAC_VER_12:
2725                 rtl8168bef_hw_phy_config(tp);
2726                 break;
2727         case RTL_GIGA_MAC_VER_17:
2728                 rtl8168bef_hw_phy_config(tp);
2729                 break;
2730         case RTL_GIGA_MAC_VER_18:
2731                 rtl8168cp_1_hw_phy_config(tp);
2732                 break;
2733         case RTL_GIGA_MAC_VER_19:
2734                 rtl8168c_1_hw_phy_config(tp);
2735                 break;
2736         case RTL_GIGA_MAC_VER_20:
2737                 rtl8168c_2_hw_phy_config(tp);
2738                 break;
2739         case RTL_GIGA_MAC_VER_21:
2740                 rtl8168c_3_hw_phy_config(tp);
2741                 break;
2742         case RTL_GIGA_MAC_VER_22:
2743                 rtl8168c_4_hw_phy_config(tp);
2744                 break;
2745         case RTL_GIGA_MAC_VER_23:
2746         case RTL_GIGA_MAC_VER_24:
2747                 rtl8168cp_2_hw_phy_config(tp);
2748                 break;
2749         case RTL_GIGA_MAC_VER_25:
2750                 rtl8168d_1_hw_phy_config(tp);
2751                 break;
2752         case RTL_GIGA_MAC_VER_26:
2753                 rtl8168d_2_hw_phy_config(tp);
2754                 break;
2755         case RTL_GIGA_MAC_VER_27:
2756                 rtl8168d_3_hw_phy_config(tp);
2757                 break;
2758         case RTL_GIGA_MAC_VER_28:
2759                 rtl8168d_4_hw_phy_config(tp);
2760                 break;
2761         case RTL_GIGA_MAC_VER_29:
2762         case RTL_GIGA_MAC_VER_30:
2763                 rtl8105e_hw_phy_config(tp);
2764                 break;
2765         case RTL_GIGA_MAC_VER_31:
2766                 /* None. */
2767                 break;
2768         case RTL_GIGA_MAC_VER_32:
2769         case RTL_GIGA_MAC_VER_33:
2770                 rtl8168e_hw_phy_config(tp);
2771                 break;
2772
2773         default:
2774                 break;
2775         }
2776 }
2777
2778 static void rtl8169_phy_timer(unsigned long __opaque)
2779 {
2780         struct net_device *dev = (struct net_device *)__opaque;
2781         struct rtl8169_private *tp = netdev_priv(dev);
2782         struct timer_list *timer = &tp->timer;
2783         void __iomem *ioaddr = tp->mmio_addr;
2784         unsigned long timeout = RTL8169_PHY_TIMEOUT;
2785
2786         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
2787
2788         spin_lock_irq(&tp->lock);
2789
2790         if (tp->phy_reset_pending(tp)) {
2791                 /*
2792                  * A busy loop could burn quite a few cycles on nowadays CPU.
2793                  * Let's delay the execution of the timer for a few ticks.
2794                  */
2795                 timeout = HZ/10;
2796                 goto out_mod_timer;
2797         }
2798
2799         if (tp->link_ok(ioaddr))
2800                 goto out_unlock;
2801
2802         netif_warn(tp, link, dev, "PHY reset until link up\n");
2803
2804         tp->phy_reset_enable(tp);
2805
2806 out_mod_timer:
2807         mod_timer(timer, jiffies + timeout);
2808 out_unlock:
2809         spin_unlock_irq(&tp->lock);
2810 }
2811
2812 #ifdef CONFIG_NET_POLL_CONTROLLER
2813 /*
2814  * Polling 'interrupt' - used by things like netconsole to send skbs
2815  * without having to re-enable interrupts. It's not called while
2816  * the interrupt routine is executing.
2817  */
2818 static void rtl8169_netpoll(struct net_device *dev)
2819 {
2820         struct rtl8169_private *tp = netdev_priv(dev);
2821         struct pci_dev *pdev = tp->pci_dev;
2822
2823         disable_irq(pdev->irq);
2824         rtl8169_interrupt(pdev->irq, dev);
2825         enable_irq(pdev->irq);
2826 }
2827 #endif
2828
2829 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
2830                                   void __iomem *ioaddr)
2831 {
2832         iounmap(ioaddr);
2833         pci_release_regions(pdev);
2834         pci_clear_mwi(pdev);
2835         pci_disable_device(pdev);
2836         free_netdev(dev);
2837 }
2838
2839 static void rtl8169_phy_reset(struct net_device *dev,
2840                               struct rtl8169_private *tp)
2841 {
2842         unsigned int i;
2843
2844         tp->phy_reset_enable(tp);
2845         for (i = 0; i < 100; i++) {
2846                 if (!tp->phy_reset_pending(tp))
2847                         return;
2848                 msleep(1);
2849         }
2850         netif_err(tp, link, dev, "PHY reset failed\n");
2851 }
2852
2853 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
2854 {
2855         void __iomem *ioaddr = tp->mmio_addr;
2856
2857         rtl_hw_phy_config(dev);
2858
2859         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2860                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2861                 RTL_W8(0x82, 0x01);
2862         }
2863
2864         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2865
2866         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
2867                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
2868
2869         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
2870                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2871                 RTL_W8(0x82, 0x01);
2872                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
2873                 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
2874         }
2875
2876         rtl8169_phy_reset(dev, tp);
2877
2878         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
2879                           ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
2880                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
2881                           (tp->mii.supports_gmii ?
2882                            ADVERTISED_1000baseT_Half |
2883                            ADVERTISED_1000baseT_Full : 0));
2884
2885         if (RTL_R8(PHYstatus) & TBI_Enable)
2886                 netif_info(tp, link, dev, "TBI auto-negotiating\n");
2887 }
2888
2889 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2890 {
2891         void __iomem *ioaddr = tp->mmio_addr;
2892         u32 high;
2893         u32 low;
2894
2895         low  = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
2896         high = addr[4] | (addr[5] << 8);
2897
2898         spin_lock_irq(&tp->lock);
2899
2900         RTL_W8(Cfg9346, Cfg9346_Unlock);
2901
2902         RTL_W32(MAC4, high);
2903         RTL_R32(MAC4);
2904
2905         RTL_W32(MAC0, low);
2906         RTL_R32(MAC0);
2907
2908         RTL_W8(Cfg9346, Cfg9346_Lock);
2909
2910         spin_unlock_irq(&tp->lock);
2911 }
2912
2913 static int rtl_set_mac_address(struct net_device *dev, void *p)
2914 {
2915         struct rtl8169_private *tp = netdev_priv(dev);
2916         struct sockaddr *addr = p;
2917
2918         if (!is_valid_ether_addr(addr->sa_data))
2919                 return -EADDRNOTAVAIL;
2920
2921         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2922
2923         rtl_rar_set(tp, dev->dev_addr);
2924
2925         return 0;
2926 }
2927
2928 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2929 {
2930         struct rtl8169_private *tp = netdev_priv(dev);
2931         struct mii_ioctl_data *data = if_mii(ifr);
2932
2933         return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
2934 }
2935
2936 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
2937                           struct mii_ioctl_data *data, int cmd)
2938 {
2939         switch (cmd) {
2940         case SIOCGMIIPHY:
2941                 data->phy_id = 32; /* Internal PHY */
2942                 return 0;
2943
2944         case SIOCGMIIREG:
2945                 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
2946                 return 0;
2947
2948         case SIOCSMIIREG:
2949                 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
2950                 return 0;
2951         }
2952         return -EOPNOTSUPP;
2953 }
2954
2955 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2956 {
2957         return -EOPNOTSUPP;
2958 }
2959
2960 static const struct rtl_cfg_info {
2961         void (*hw_start)(struct net_device *);
2962         unsigned int region;
2963         unsigned int align;
2964         u16 intr_event;
2965         u16 napi_event;
2966         unsigned features;
2967         u8 default_ver;
2968 } rtl_cfg_infos [] = {
2969         [RTL_CFG_0] = {
2970                 .hw_start       = rtl_hw_start_8169,
2971                 .region         = 1,
2972                 .align          = 0,
2973                 .intr_event     = SYSErr | LinkChg | RxOverflow |
2974                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2975                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2976                 .features       = RTL_FEATURE_GMII,
2977                 .default_ver    = RTL_GIGA_MAC_VER_01,
2978         },
2979         [RTL_CFG_1] = {
2980                 .hw_start       = rtl_hw_start_8168,
2981                 .region         = 2,
2982                 .align          = 8,
2983                 .intr_event     = SYSErr | LinkChg | RxOverflow |
2984                                   TxErr | TxOK | RxOK | RxErr,
2985                 .napi_event     = TxErr | TxOK | RxOK | RxOverflow,
2986                 .features       = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
2987                 .default_ver    = RTL_GIGA_MAC_VER_11,
2988         },
2989         [RTL_CFG_2] = {
2990                 .hw_start       = rtl_hw_start_8101,
2991                 .region         = 2,
2992                 .align          = 8,
2993                 .intr_event     = SYSErr | LinkChg | RxOverflow | PCSTimeout |
2994                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2995                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2996                 .features       = RTL_FEATURE_MSI,
2997                 .default_ver    = RTL_GIGA_MAC_VER_13,
2998         }
2999 };
3000
3001 /* Cfg9346_Unlock assumed. */
3002 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
3003                             const struct rtl_cfg_info *cfg)
3004 {
3005         unsigned msi = 0;
3006         u8 cfg2;
3007
3008         cfg2 = RTL_R8(Config2) & ~MSIEnable;
3009         if (cfg->features & RTL_FEATURE_MSI) {
3010                 if (pci_enable_msi(pdev)) {
3011                         dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
3012                 } else {
3013                         cfg2 |= MSIEnable;
3014                         msi = RTL_FEATURE_MSI;
3015                 }
3016         }
3017         RTL_W8(Config2, cfg2);
3018         return msi;
3019 }
3020
3021 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3022 {
3023         if (tp->features & RTL_FEATURE_MSI) {
3024                 pci_disable_msi(pdev);
3025                 tp->features &= ~RTL_FEATURE_MSI;
3026         }
3027 }
3028
3029 static const struct net_device_ops rtl8169_netdev_ops = {
3030         .ndo_open               = rtl8169_open,
3031         .ndo_stop               = rtl8169_close,
3032         .ndo_get_stats          = rtl8169_get_stats,
3033         .ndo_start_xmit         = rtl8169_start_xmit,
3034         .ndo_tx_timeout         = rtl8169_tx_timeout,
3035         .ndo_validate_addr      = eth_validate_addr,
3036         .ndo_change_mtu         = rtl8169_change_mtu,
3037         .ndo_fix_features       = rtl8169_fix_features,
3038         .ndo_set_features       = rtl8169_set_features,
3039         .ndo_set_mac_address    = rtl_set_mac_address,
3040         .ndo_do_ioctl           = rtl8169_ioctl,
3041         .ndo_set_multicast_list = rtl_set_rx_mode,
3042 #ifdef CONFIG_NET_POLL_CONTROLLER
3043         .ndo_poll_controller    = rtl8169_netpoll,
3044 #endif
3045
3046 };
3047
3048 static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
3049 {
3050         struct mdio_ops *ops = &tp->mdio_ops;
3051
3052         switch (tp->mac_version) {
3053         case RTL_GIGA_MAC_VER_27:
3054                 ops->write      = r8168dp_1_mdio_write;
3055                 ops->read       = r8168dp_1_mdio_read;
3056                 break;
3057         case RTL_GIGA_MAC_VER_28:
3058         case RTL_GIGA_MAC_VER_31:
3059                 ops->write      = r8168dp_2_mdio_write;
3060                 ops->read       = r8168dp_2_mdio_read;
3061                 break;
3062         default:
3063                 ops->write      = r8169_mdio_write;
3064                 ops->read       = r8169_mdio_read;
3065                 break;
3066         }
3067 }
3068
3069 static void r810x_phy_power_down(struct rtl8169_private *tp)
3070 {
3071         rtl_writephy(tp, 0x1f, 0x0000);
3072         rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3073 }
3074
3075 static void r810x_phy_power_up(struct rtl8169_private *tp)
3076 {
3077         rtl_writephy(tp, 0x1f, 0x0000);
3078         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3079 }
3080
3081 static void r810x_pll_power_down(struct rtl8169_private *tp)
3082 {
3083         if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3084                 rtl_writephy(tp, 0x1f, 0x0000);
3085                 rtl_writephy(tp, MII_BMCR, 0x0000);
3086                 return;
3087         }
3088
3089         r810x_phy_power_down(tp);
3090 }
3091
3092 static void r810x_pll_power_up(struct rtl8169_private *tp)
3093 {
3094         r810x_phy_power_up(tp);
3095 }
3096
3097 static void r8168_phy_power_up(struct rtl8169_private *tp)
3098 {
3099         rtl_writephy(tp, 0x1f, 0x0000);
3100         switch (tp->mac_version) {
3101         case RTL_GIGA_MAC_VER_11:
3102         case RTL_GIGA_MAC_VER_12:
3103         case RTL_GIGA_MAC_VER_17:
3104         case RTL_GIGA_MAC_VER_18:
3105         case RTL_GIGA_MAC_VER_19:
3106         case RTL_GIGA_MAC_VER_20:
3107         case RTL_GIGA_MAC_VER_21:
3108         case RTL_GIGA_MAC_VER_22:
3109         case RTL_GIGA_MAC_VER_23:
3110         case RTL_GIGA_MAC_VER_24:
3111         case RTL_GIGA_MAC_VER_25:
3112         case RTL_GIGA_MAC_VER_26:
3113         case RTL_GIGA_MAC_VER_27:
3114         case RTL_GIGA_MAC_VER_28:
3115         case RTL_GIGA_MAC_VER_31:
3116                 rtl_writephy(tp, 0x0e, 0x0000);
3117                 break;
3118         default:
3119                 break;
3120         }
3121         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3122 }
3123
3124 static void r8168_phy_power_down(struct rtl8169_private *tp)
3125 {
3126         rtl_writephy(tp, 0x1f, 0x0000);
3127         switch (tp->mac_version) {
3128         case RTL_GIGA_MAC_VER_32:
3129         case RTL_GIGA_MAC_VER_33:
3130                 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3131                 break;
3132
3133         case RTL_GIGA_MAC_VER_11:
3134         case RTL_GIGA_MAC_VER_12:
3135         case RTL_GIGA_MAC_VER_17:
3136         case RTL_GIGA_MAC_VER_18:
3137         case RTL_GIGA_MAC_VER_19:
3138         case RTL_GIGA_MAC_VER_20:
3139         case RTL_GIGA_MAC_VER_21:
3140         case RTL_GIGA_MAC_VER_22:
3141         case RTL_GIGA_MAC_VER_23:
3142         case RTL_GIGA_MAC_VER_24:
3143         case RTL_GIGA_MAC_VER_25:
3144         case RTL_GIGA_MAC_VER_26:
3145         case RTL_GIGA_MAC_VER_27:
3146         case RTL_GIGA_MAC_VER_28:
3147         case RTL_GIGA_MAC_VER_31:
3148                 rtl_writephy(tp, 0x0e, 0x0200);
3149         default:
3150                 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3151                 break;
3152         }
3153 }
3154
3155 static void r8168_pll_power_down(struct rtl8169_private *tp)
3156 {
3157         void __iomem *ioaddr = tp->mmio_addr;
3158
3159         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3160              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3161              tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3162             r8168dp_check_dash(tp)) {
3163                 return;
3164         }
3165
3166         if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
3167              tp->mac_version == RTL_GIGA_MAC_VER_24) &&
3168             (RTL_R16(CPlusCmd) & ASF)) {
3169                 return;
3170         }
3171
3172         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3173             tp->mac_version == RTL_GIGA_MAC_VER_33)
3174                 rtl_ephy_write(ioaddr, 0x19, 0xff64);
3175
3176         if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3177                 rtl_writephy(tp, 0x1f, 0x0000);
3178                 rtl_writephy(tp, MII_BMCR, 0x0000);
3179
3180                 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3181                     tp->mac_version == RTL_GIGA_MAC_VER_33)
3182                         RTL_W32(RxConfig, RTL_R32(RxConfig) | AcceptBroadcast |
3183                                 AcceptMulticast | AcceptMyPhys);
3184                 return;
3185         }
3186
3187         r8168_phy_power_down(tp);
3188
3189         switch (tp->mac_version) {
3190         case RTL_GIGA_MAC_VER_25:
3191         case RTL_GIGA_MAC_VER_26:
3192         case RTL_GIGA_MAC_VER_27:
3193         case RTL_GIGA_MAC_VER_28:
3194         case RTL_GIGA_MAC_VER_31:
3195         case RTL_GIGA_MAC_VER_32:
3196         case RTL_GIGA_MAC_VER_33:
3197                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3198                 break;
3199         }
3200 }
3201
3202 static void r8168_pll_power_up(struct rtl8169_private *tp)
3203 {
3204         void __iomem *ioaddr = tp->mmio_addr;
3205
3206         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3207              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3208              tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3209             r8168dp_check_dash(tp)) {
3210                 return;
3211         }
3212
3213         switch (tp->mac_version) {
3214         case RTL_GIGA_MAC_VER_25:
3215         case RTL_GIGA_MAC_VER_26:
3216         case RTL_GIGA_MAC_VER_27:
3217         case RTL_GIGA_MAC_VER_28:
3218         case RTL_GIGA_MAC_VER_31:
3219         case RTL_GIGA_MAC_VER_32:
3220         case RTL_GIGA_MAC_VER_33:
3221                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3222                 break;
3223         }
3224
3225         r8168_phy_power_up(tp);
3226 }
3227
3228 static void rtl_generic_op(struct rtl8169_private *tp,
3229                            void (*op)(struct rtl8169_private *))
3230 {
3231         if (op)
3232                 op(tp);
3233 }
3234
3235 static void rtl_pll_power_down(struct rtl8169_private *tp)
3236 {
3237         rtl_generic_op(tp, tp->pll_power_ops.down);
3238 }
3239
3240 static void rtl_pll_power_up(struct rtl8169_private *tp)
3241 {
3242         rtl_generic_op(tp, tp->pll_power_ops.up);
3243 }
3244
3245 static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3246 {
3247         struct pll_power_ops *ops = &tp->pll_power_ops;
3248
3249         switch (tp->mac_version) {
3250         case RTL_GIGA_MAC_VER_07:
3251         case RTL_GIGA_MAC_VER_08:
3252         case RTL_GIGA_MAC_VER_09:
3253         case RTL_GIGA_MAC_VER_10:
3254         case RTL_GIGA_MAC_VER_16:
3255         case RTL_GIGA_MAC_VER_29:
3256         case RTL_GIGA_MAC_VER_30:
3257                 ops->down       = r810x_pll_power_down;
3258                 ops->up         = r810x_pll_power_up;
3259                 break;
3260
3261         case RTL_GIGA_MAC_VER_11:
3262         case RTL_GIGA_MAC_VER_12:
3263         case RTL_GIGA_MAC_VER_17:
3264         case RTL_GIGA_MAC_VER_18:
3265         case RTL_GIGA_MAC_VER_19:
3266         case RTL_GIGA_MAC_VER_20:
3267         case RTL_GIGA_MAC_VER_21:
3268         case RTL_GIGA_MAC_VER_22:
3269         case RTL_GIGA_MAC_VER_23:
3270         case RTL_GIGA_MAC_VER_24:
3271         case RTL_GIGA_MAC_VER_25:
3272         case RTL_GIGA_MAC_VER_26:
3273         case RTL_GIGA_MAC_VER_27:
3274         case RTL_GIGA_MAC_VER_28:
3275         case RTL_GIGA_MAC_VER_31:
3276         case RTL_GIGA_MAC_VER_32:
3277         case RTL_GIGA_MAC_VER_33:
3278                 ops->down       = r8168_pll_power_down;
3279                 ops->up         = r8168_pll_power_up;
3280                 break;
3281
3282         default:
3283                 ops->down       = NULL;
3284                 ops->up         = NULL;
3285                 break;
3286         }
3287 }
3288
3289 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
3290 {
3291         rtl_generic_op(tp, tp->jumbo_ops.enable);
3292 }
3293
3294 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
3295 {
3296         rtl_generic_op(tp, tp->jumbo_ops.disable);
3297 }
3298
3299 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
3300 {
3301         void __iomem *ioaddr = tp->mmio_addr;
3302
3303         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3304         RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
3305         rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
3306 }
3307
3308 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
3309 {
3310         void __iomem *ioaddr = tp->mmio_addr;
3311
3312         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3313         RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
3314         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
3315 }
3316
3317 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
3318 {
3319         void __iomem *ioaddr = tp->mmio_addr;
3320
3321         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3322 }
3323
3324 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
3325 {
3326         void __iomem *ioaddr = tp->mmio_addr;
3327
3328         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3329 }
3330
3331 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
3332 {
3333         void __iomem *ioaddr = tp->mmio_addr;
3334         struct pci_dev *pdev = tp->pci_dev;
3335
3336         RTL_W8(MaxTxPacketSize, 0x3f);
3337         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3338         RTL_W8(Config4, RTL_R8(Config4) | 0x01);
3339         pci_write_config_byte(pdev, 0x79, 0x20);
3340 }
3341
3342 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
3343 {
3344         void __iomem *ioaddr = tp->mmio_addr;
3345         struct pci_dev *pdev = tp->pci_dev;
3346
3347         RTL_W8(MaxTxPacketSize, 0x0c);
3348         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3349         RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
3350         pci_write_config_byte(pdev, 0x79, 0x50);
3351 }
3352
3353 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
3354 {
3355         rtl_tx_performance_tweak(tp->pci_dev,
3356                 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3357 }
3358
3359 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
3360 {
3361         rtl_tx_performance_tweak(tp->pci_dev,
3362                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3363 }
3364
3365 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
3366 {
3367         void __iomem *ioaddr = tp->mmio_addr;
3368
3369         r8168b_0_hw_jumbo_enable(tp);
3370
3371         RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
3372 }
3373
3374 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
3375 {
3376         void __iomem *ioaddr = tp->mmio_addr;
3377
3378         r8168b_0_hw_jumbo_disable(tp);
3379
3380         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
3381 }
3382
3383 static void __devinit rtl_init_jumbo_ops(struct rtl8169_private *tp)
3384 {
3385         struct jumbo_ops *ops = &tp->jumbo_ops;
3386
3387         switch (tp->mac_version) {
3388         case RTL_GIGA_MAC_VER_11:
3389                 ops->disable    = r8168b_0_hw_jumbo_disable;
3390                 ops->enable     = r8168b_0_hw_jumbo_enable;
3391                 break;
3392         case RTL_GIGA_MAC_VER_12:
3393         case RTL_GIGA_MAC_VER_17:
3394                 ops->disable    = r8168b_1_hw_jumbo_disable;
3395                 ops->enable     = r8168b_1_hw_jumbo_enable;
3396                 break;
3397         case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
3398         case RTL_GIGA_MAC_VER_19:
3399         case RTL_GIGA_MAC_VER_20:
3400         case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
3401         case RTL_GIGA_MAC_VER_22:
3402         case RTL_GIGA_MAC_VER_23:
3403         case RTL_GIGA_MAC_VER_24:
3404         case RTL_GIGA_MAC_VER_25:
3405         case RTL_GIGA_MAC_VER_26:
3406                 ops->disable    = r8168c_hw_jumbo_disable;
3407                 ops->enable     = r8168c_hw_jumbo_enable;
3408                 break;
3409         case RTL_GIGA_MAC_VER_27:
3410         case RTL_GIGA_MAC_VER_28:
3411                 ops->disable    = r8168dp_hw_jumbo_disable;
3412                 ops->enable     = r8168dp_hw_jumbo_enable;
3413                 break;
3414         case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
3415         case RTL_GIGA_MAC_VER_32:
3416         case RTL_GIGA_MAC_VER_33:
3417                 ops->disable    = r8168e_hw_jumbo_disable;
3418                 ops->enable     = r8168e_hw_jumbo_enable;
3419                 break;
3420
3421         /*
3422          * No action needed for jumbo frames with 8169.
3423          * No jumbo for 810x at all.
3424          */
3425         default:
3426                 ops->disable    = NULL;
3427                 ops->enable     = NULL;
3428                 break;
3429         }
3430 }
3431
3432 static void rtl_hw_reset(struct rtl8169_private *tp)
3433 {
3434         void __iomem *ioaddr = tp->mmio_addr;
3435         int i;
3436
3437         /* Soft reset the chip. */
3438         RTL_W8(ChipCmd, CmdReset);
3439
3440         /* Check that the chip has finished the reset. */
3441         for (i = 0; i < 100; i++) {
3442                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3443                         break;
3444                 msleep_interruptible(1);
3445         }
3446 }
3447
3448 static int __devinit
3449 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3450 {
3451         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
3452         const unsigned int region = cfg->region;
3453         struct rtl8169_private *tp;
3454         struct mii_if_info *mii;
3455         struct net_device *dev;
3456         void __iomem *ioaddr;
3457         int chipset, i;
3458         int rc;
3459
3460         if (netif_msg_drv(&debug)) {
3461                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
3462                        MODULENAME, RTL8169_VERSION);
3463         }
3464
3465         dev = alloc_etherdev(sizeof (*tp));
3466         if (!dev) {
3467                 if (netif_msg_drv(&debug))
3468                         dev_err(&pdev->dev, "unable to alloc new ethernet\n");
3469                 rc = -ENOMEM;
3470                 goto out;
3471         }
3472
3473         SET_NETDEV_DEV(dev, &pdev->dev);
3474         dev->netdev_ops = &rtl8169_netdev_ops;
3475         tp = netdev_priv(dev);
3476         tp->dev = dev;
3477         tp->pci_dev = pdev;
3478         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
3479
3480         mii = &tp->mii;
3481         mii->dev = dev;
3482         mii->mdio_read = rtl_mdio_read;
3483         mii->mdio_write = rtl_mdio_write;
3484         mii->phy_id_mask = 0x1f;
3485         mii->reg_num_mask = 0x1f;
3486         mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3487
3488         /* disable ASPM completely as that cause random device stop working
3489          * problems as well as full system hangs for some PCIe devices users */
3490         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3491                                      PCIE_LINK_STATE_CLKPM);
3492
3493         /* enable device (incl. PCI PM wakeup and hotplug setup) */
3494         rc = pci_enable_device(pdev);
3495         if (rc < 0) {
3496                 netif_err(tp, probe, dev, "enable failure\n");
3497                 goto err_out_free_dev_1;
3498         }
3499
3500         if (pci_set_mwi(pdev) < 0)
3501                 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
3502
3503         /* make sure PCI base addr 1 is MMIO */
3504         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
3505                 netif_err(tp, probe, dev,
3506                           "region #%d not an MMIO resource, aborting\n",
3507                           region);
3508                 rc = -ENODEV;
3509                 goto err_out_mwi_2;
3510         }
3511
3512         /* check for weird/broken PCI region reporting */
3513         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
3514                 netif_err(tp, probe, dev,
3515                           "Invalid PCI region size(s), aborting\n");
3516                 rc = -ENODEV;
3517                 goto err_out_mwi_2;
3518         }
3519
3520         rc = pci_request_regions(pdev, MODULENAME);
3521         if (rc < 0) {
3522                 netif_err(tp, probe, dev, "could not request regions\n");
3523                 goto err_out_mwi_2;
3524         }
3525
3526         tp->cp_cmd = RxChkSum;
3527
3528         if ((sizeof(dma_addr_t) > 4) &&
3529             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
3530                 tp->cp_cmd |= PCIDAC;
3531                 dev->features |= NETIF_F_HIGHDMA;
3532         } else {
3533                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3534                 if (rc < 0) {
3535                         netif_err(tp, probe, dev, "DMA configuration failed\n");
3536                         goto err_out_free_res_3;
3537                 }
3538         }
3539
3540         /* ioremap MMIO region */
3541         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
3542         if (!ioaddr) {
3543                 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
3544                 rc = -EIO;
3545                 goto err_out_free_res_3;
3546         }
3547         tp->mmio_addr = ioaddr;
3548
3549         tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3550         if (!tp->pcie_cap)
3551                 netif_info(tp, probe, dev, "no PCI Express capability\n");
3552
3553         RTL_W16(IntrMask, 0x0000);
3554
3555         rtl_hw_reset(tp);
3556
3557         RTL_W16(IntrStatus, 0xffff);
3558
3559         pci_set_master(pdev);
3560
3561         /* Identify chip attached to board */
3562         rtl8169_get_mac_version(tp, dev, cfg->default_ver);
3563
3564         /*
3565          * Pretend we are using VLANs; This bypasses a nasty bug where
3566          * Interrupts stop flowing on high load on 8110SCd controllers.
3567          */
3568         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3569                 tp->cp_cmd |= RxVlan;
3570
3571         rtl_init_mdio_ops(tp);
3572         rtl_init_pll_power_ops(tp);
3573         rtl_init_jumbo_ops(tp);
3574
3575         rtl8169_print_mac_version(tp);
3576
3577         chipset = tp->mac_version;
3578         tp->txd_version = rtl_chip_infos[chipset].txd_version;
3579
3580         RTL_W8(Cfg9346, Cfg9346_Unlock);
3581         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3582         RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
3583         if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3584                 tp->features |= RTL_FEATURE_WOL;
3585         if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3586                 tp->features |= RTL_FEATURE_WOL;
3587         tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
3588         RTL_W8(Cfg9346, Cfg9346_Lock);
3589
3590         if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3591             (RTL_R8(PHYstatus) & TBI_Enable)) {
3592                 tp->set_speed = rtl8169_set_speed_tbi;
3593                 tp->get_settings = rtl8169_gset_tbi;
3594                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3595                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3596                 tp->link_ok = rtl8169_tbi_link_ok;
3597                 tp->do_ioctl = rtl_tbi_ioctl;
3598         } else {
3599                 tp->set_speed = rtl8169_set_speed_xmii;
3600                 tp->get_settings = rtl8169_gset_xmii;
3601                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3602                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3603                 tp->link_ok = rtl8169_xmii_link_ok;
3604                 tp->do_ioctl = rtl_xmii_ioctl;
3605         }
3606
3607         spin_lock_init(&tp->lock);
3608
3609         /* Get MAC address */
3610         for (i = 0; i < MAC_ADDR_LEN; i++)
3611                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
3612         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3613
3614         SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
3615         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3616         dev->irq = pdev->irq;
3617         dev->base_addr = (unsigned long) ioaddr;
3618
3619         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
3620
3621         /* don't enable SG, IP_CSUM and TSO by default - it might not work
3622          * properly for all devices */
3623         dev->features |= NETIF_F_RXCSUM |
3624                 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3625
3626         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3627                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3628         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3629                 NETIF_F_HIGHDMA;
3630
3631         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3632                 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
3633                 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
3634
3635         tp->intr_mask = 0xffff;
3636         tp->hw_start = cfg->hw_start;
3637         tp->intr_event = cfg->intr_event;
3638         tp->napi_event = cfg->napi_event;
3639
3640         tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
3641                 ~(RxBOVF | RxFOVF) : ~0;
3642
3643         init_timer(&tp->timer);
3644         tp->timer.data = (unsigned long) dev;
3645         tp->timer.function = rtl8169_phy_timer;
3646
3647         tp->fw = RTL_FIRMWARE_UNKNOWN;
3648
3649         rc = register_netdev(dev);
3650         if (rc < 0)
3651                 goto err_out_msi_4;
3652
3653         pci_set_drvdata(pdev, dev);
3654
3655         netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
3656                    rtl_chip_infos[chipset].name, dev->base_addr, dev->dev_addr,
3657                    (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
3658         if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
3659                 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
3660                            "tx checksumming: %s]\n",
3661                            rtl_chip_infos[chipset].jumbo_max,
3662                            rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
3663         }
3664
3665         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3666             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3667             tp->mac_version == RTL_GIGA_MAC_VER_31) {
3668                 rtl8168_driver_start(tp);
3669         }
3670
3671         device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
3672
3673         if (pci_dev_run_wake(pdev))
3674                 pm_runtime_put_noidle(&pdev->dev);
3675
3676         netif_carrier_off(dev);
3677
3678 out:
3679         return rc;
3680
3681 err_out_msi_4:
3682         rtl_disable_msi(pdev, tp);
3683         iounmap(ioaddr);
3684 err_out_free_res_3:
3685         pci_release_regions(pdev);
3686 err_out_mwi_2:
3687         pci_clear_mwi(pdev);
3688         pci_disable_device(pdev);
3689 err_out_free_dev_1:
3690         free_netdev(dev);
3691         goto out;
3692 }
3693
3694 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
3695 {
3696         struct net_device *dev = pci_get_drvdata(pdev);
3697         struct rtl8169_private *tp = netdev_priv(dev);
3698
3699         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3700             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3701             tp->mac_version == RTL_GIGA_MAC_VER_31) {
3702                 rtl8168_driver_stop(tp);
3703         }
3704
3705         cancel_delayed_work_sync(&tp->task);
3706
3707         unregister_netdev(dev);
3708
3709         rtl_release_firmware(tp);
3710
3711         if (pci_dev_run_wake(pdev))
3712                 pm_runtime_get_noresume(&pdev->dev);
3713
3714         /* restore original MAC address */
3715         rtl_rar_set(tp, dev->perm_addr);
3716
3717         rtl_disable_msi(pdev, tp);
3718         rtl8169_release_board(pdev, dev, tp->mmio_addr);
3719         pci_set_drvdata(pdev, NULL);
3720 }
3721
3722 static void rtl_request_firmware(struct rtl8169_private *tp)
3723 {
3724         /* Return early if the firmware is already loaded / cached. */
3725         if (IS_ERR(tp->fw)) {
3726                 const char *name;
3727
3728                 name = rtl_lookup_firmware_name(tp);
3729                 if (name) {
3730                         int rc;
3731
3732                         rc = request_firmware(&tp->fw, name, &tp->pci_dev->dev);
3733                         if (rc >= 0)
3734                                 return;
3735
3736                         netif_warn(tp, ifup, tp->dev, "unable to load "
3737                                 "firmware patch %s (%d)\n", name, rc);
3738                 }
3739                 tp->fw = NULL;
3740         }
3741 }
3742
3743 static int rtl8169_open(struct net_device *dev)
3744 {
3745         struct rtl8169_private *tp = netdev_priv(dev);
3746         void __iomem *ioaddr = tp->mmio_addr;
3747         struct pci_dev *pdev = tp->pci_dev;
3748         int retval = -ENOMEM;
3749
3750         pm_runtime_get_sync(&pdev->dev);
3751
3752         /*
3753          * Rx and Tx desscriptors needs 256 bytes alignment.
3754          * dma_alloc_coherent provides more.
3755          */
3756         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
3757                                              &tp->TxPhyAddr, GFP_KERNEL);
3758         if (!tp->TxDescArray)
3759                 goto err_pm_runtime_put;
3760
3761         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
3762                                              &tp->RxPhyAddr, GFP_KERNEL);
3763         if (!tp->RxDescArray)
3764                 goto err_free_tx_0;
3765
3766         retval = rtl8169_init_ring(dev);
3767         if (retval < 0)
3768                 goto err_free_rx_1;
3769
3770         INIT_DELAYED_WORK(&tp->task, NULL);
3771
3772         smp_mb();
3773
3774         rtl_request_firmware(tp);
3775
3776         retval = request_irq(dev->irq, rtl8169_interrupt,
3777                              (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
3778                              dev->name, dev);
3779         if (retval < 0)
3780                 goto err_release_fw_2;
3781
3782         napi_enable(&tp->napi);
3783
3784         rtl8169_init_phy(dev, tp);
3785
3786         rtl8169_set_features(dev, dev->features);
3787
3788         rtl_pll_power_up(tp);
3789
3790         rtl_hw_start(dev);
3791
3792         tp->saved_wolopts = 0;
3793         pm_runtime_put_noidle(&pdev->dev);
3794
3795         rtl8169_check_link_status(dev, tp, ioaddr);
3796 out:
3797         return retval;
3798
3799 err_release_fw_2:
3800         rtl_release_firmware(tp);
3801         rtl8169_rx_clear(tp);
3802 err_free_rx_1:
3803         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
3804                           tp->RxPhyAddr);
3805         tp->RxDescArray = NULL;
3806 err_free_tx_0:
3807         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
3808                           tp->TxPhyAddr);
3809         tp->TxDescArray = NULL;
3810 err_pm_runtime_put:
3811         pm_runtime_put_noidle(&pdev->dev);
3812         goto out;
3813 }
3814
3815 static void rtl8169_hw_reset(struct rtl8169_private *tp)
3816 {
3817         void __iomem *ioaddr = tp->mmio_addr;
3818
3819         /* Disable interrupts */
3820         rtl8169_irq_mask_and_ack(ioaddr);
3821
3822         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3823             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3824             tp->mac_version == RTL_GIGA_MAC_VER_31) {
3825                 while (RTL_R8(TxPoll) & NPQ)
3826                         udelay(20);
3827
3828         }
3829
3830         /* Reset the chipset */
3831         RTL_W8(ChipCmd, CmdReset);
3832
3833         /* PCI commit */
3834         RTL_R8(ChipCmd);
3835 }
3836
3837 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
3838 {
3839         void __iomem *ioaddr = tp->mmio_addr;
3840         u32 cfg = rtl8169_rx_config;
3841
3842         cfg |= (RTL_R32(RxConfig) & RTL_RX_CONFIG_MASK);
3843         RTL_W32(RxConfig, cfg);
3844
3845         /* Set DMA burst size and Interframe Gap Time */
3846         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3847                 (InterFrameGap << TxInterFrameGapShift));
3848 }
3849
3850 static void rtl_hw_start(struct net_device *dev)
3851 {
3852         struct rtl8169_private *tp = netdev_priv(dev);
3853
3854         rtl_hw_reset(tp);
3855
3856         tp->hw_start(dev);
3857
3858         netif_start_queue(dev);
3859 }
3860
3861 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3862                                          void __iomem *ioaddr)
3863 {
3864         /*
3865          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3866          * register to be written before TxDescAddrLow to work.
3867          * Switching from MMIO to I/O access fixes the issue as well.
3868          */
3869         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
3870         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
3871         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
3872         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
3873 }
3874
3875 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
3876 {
3877         u16 cmd;
3878
3879         cmd = RTL_R16(CPlusCmd);
3880         RTL_W16(CPlusCmd, cmd);
3881         return cmd;
3882 }
3883
3884 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
3885 {
3886         /* Low hurts. Let's disable the filtering. */
3887         RTL_W16(RxMaxSize, rx_buf_sz + 1);
3888 }
3889
3890 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
3891 {
3892         static const struct rtl_cfg2_info {
3893                 u32 mac_version;
3894                 u32 clk;
3895                 u32 val;
3896         } cfg2_info [] = {
3897                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
3898                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
3899                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
3900                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3901         };
3902         const struct rtl_cfg2_info *p = cfg2_info;
3903         unsigned int i;
3904         u32 clk;
3905
3906         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
3907         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
3908                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
3909                         RTL_W32(0x7c, p->val);
3910                         break;
3911                 }
3912         }
3913 }
3914
3915 static void rtl_hw_start_8169(struct net_device *dev)
3916 {
3917         struct rtl8169_private *tp = netdev_priv(dev);
3918         void __iomem *ioaddr = tp->mmio_addr;
3919         struct pci_dev *pdev = tp->pci_dev;
3920
3921         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
3922                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
3923                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
3924         }
3925
3926         RTL_W8(Cfg9346, Cfg9346_Unlock);
3927         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
3928             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3929             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
3930             tp->mac_version == RTL_GIGA_MAC_VER_04)
3931                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3932
3933         RTL_W8(EarlyTxThres, NoEarlyTx);
3934
3935         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
3936
3937         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
3938             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3939             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
3940             tp->mac_version == RTL_GIGA_MAC_VER_04)
3941                 rtl_set_rx_tx_config_registers(tp);
3942
3943         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3944
3945         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3946             tp->mac_version == RTL_GIGA_MAC_VER_03) {
3947                 dprintk("Set MAC Reg C+CR Offset 0xE0. "
3948                         "Bit-3 and bit-14 MUST be 1\n");
3949                 tp->cp_cmd |= (1 << 14);
3950         }
3951
3952         RTL_W16(CPlusCmd, tp->cp_cmd);
3953
3954         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
3955
3956         /*
3957          * Undocumented corner. Supposedly:
3958          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3959          */
3960         RTL_W16(IntrMitigate, 0x0000);
3961
3962         rtl_set_rx_tx_desc_registers(tp, ioaddr);
3963
3964         if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
3965             tp->mac_version != RTL_GIGA_MAC_VER_02 &&
3966             tp->mac_version != RTL_GIGA_MAC_VER_03 &&
3967             tp->mac_version != RTL_GIGA_MAC_VER_04) {
3968                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3969                 rtl_set_rx_tx_config_registers(tp);
3970         }
3971
3972         RTL_W8(Cfg9346, Cfg9346_Lock);
3973
3974         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3975         RTL_R8(IntrMask);
3976
3977         RTL_W32(RxMissed, 0);
3978
3979         rtl_set_rx_mode(dev);
3980
3981         /* no early-rx interrupts */
3982         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
3983
3984         /* Enable all known interrupts by setting the interrupt mask. */
3985         RTL_W16(IntrMask, tp->intr_event);
3986 }
3987
3988 static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
3989 {
3990         u32 csi;
3991
3992         csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
3993         rtl_csi_write(ioaddr, 0x070c, csi | bits);
3994 }
3995
3996 static void rtl_csi_access_enable_1(void __iomem *ioaddr)
3997 {
3998         rtl_csi_access_enable(ioaddr, 0x17000000);
3999 }
4000
4001 static void rtl_csi_access_enable_2(void __iomem *ioaddr)
4002 {
4003         rtl_csi_access_enable(ioaddr, 0x27000000);
4004 }
4005
4006 struct ephy_info {
4007         unsigned int offset;
4008         u16 mask;
4009         u16 bits;
4010 };
4011
4012 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
4013 {
4014         u16 w;
4015
4016         while (len-- > 0) {
4017                 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
4018                 rtl_ephy_write(ioaddr, e->offset, w);
4019                 e++;
4020         }
4021 }
4022
4023 static void rtl_disable_clock_request(struct pci_dev *pdev)
4024 {
4025         struct net_device *dev = pci_get_drvdata(pdev);
4026         struct rtl8169_private *tp = netdev_priv(dev);
4027         int cap = tp->pcie_cap;
4028
4029         if (cap) {
4030                 u16 ctl;
4031
4032                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4033                 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
4034                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4035         }
4036 }
4037
4038 static void rtl_enable_clock_request(struct pci_dev *pdev)
4039 {
4040         struct net_device *dev = pci_get_drvdata(pdev);
4041         struct rtl8169_private *tp = netdev_priv(dev);
4042         int cap = tp->pcie_cap;
4043
4044         if (cap) {
4045                 u16 ctl;
4046
4047                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4048                 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
4049                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4050         }
4051 }
4052
4053 #define R8168_CPCMD_QUIRK_MASK (\
4054         EnableBist | \
4055         Mac_dbgo_oe | \
4056         Force_half_dup | \
4057         Force_rxflow_en | \
4058         Force_txflow_en | \
4059         Cxpl_dbg_sel | \
4060         ASF | \
4061         PktCntrDisable | \
4062         Mac_dbgo_sel)
4063
4064 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
4065 {
4066         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4067
4068         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4069
4070         rtl_tx_performance_tweak(pdev,
4071                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4072 }
4073
4074 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
4075 {
4076         rtl_hw_start_8168bb(ioaddr, pdev);
4077
4078         RTL_W8(MaxTxPacketSize, TxPacketMax);
4079
4080         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4081 }
4082
4083 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
4084 {
4085         RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4086
4087         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4088
4089         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4090
4091         rtl_disable_clock_request(pdev);
4092
4093         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4094 }
4095
4096 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
4097 {
4098         static const struct ephy_info e_info_8168cp[] = {
4099                 { 0x01, 0,      0x0001 },
4100                 { 0x02, 0x0800, 0x1000 },
4101                 { 0x03, 0,      0x0042 },
4102                 { 0x06, 0x0080, 0x0000 },
4103                 { 0x07, 0,      0x2000 }
4104         };
4105
4106         rtl_csi_access_enable_2(ioaddr);
4107
4108         rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4109
4110         __rtl_hw_start_8168cp(ioaddr, pdev);
4111 }
4112
4113 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
4114 {
4115         rtl_csi_access_enable_2(ioaddr);
4116
4117         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4118
4119         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4120
4121         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4122 }
4123
4124 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
4125 {
4126         rtl_csi_access_enable_2(ioaddr);
4127
4128         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4129
4130         /* Magic. */
4131         RTL_W8(DBG_REG, 0x20);
4132
4133         RTL_W8(MaxTxPacketSize, TxPacketMax);
4134
4135         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4136
4137         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4138 }
4139
4140 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
4141 {
4142         static const struct ephy_info e_info_8168c_1[] = {
4143                 { 0x02, 0x0800, 0x1000 },
4144                 { 0x03, 0,      0x0002 },
4145                 { 0x06, 0x0080, 0x0000 }
4146         };
4147
4148         rtl_csi_access_enable_2(ioaddr);
4149
4150         RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4151
4152         rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4153
4154         __rtl_hw_start_8168cp(ioaddr, pdev);
4155 }
4156
4157 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
4158 {
4159         static const struct ephy_info e_info_8168c_2[] = {
4160                 { 0x01, 0,      0x0001 },
4161                 { 0x03, 0x0400, 0x0220 }
4162         };
4163
4164         rtl_csi_access_enable_2(ioaddr);
4165
4166         rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4167
4168         __rtl_hw_start_8168cp(ioaddr, pdev);
4169 }
4170
4171 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
4172 {
4173         rtl_hw_start_8168c_2(ioaddr, pdev);
4174 }
4175
4176 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
4177 {
4178         rtl_csi_access_enable_2(ioaddr);
4179
4180         __rtl_hw_start_8168cp(ioaddr, pdev);
4181 }
4182
4183 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
4184 {
4185         rtl_csi_access_enable_2(ioaddr);
4186
4187         rtl_disable_clock_request(pdev);
4188
4189         RTL_W8(MaxTxPacketSize, TxPacketMax);
4190
4191         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4192
4193         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4194 }
4195
4196 static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev)
4197 {
4198         rtl_csi_access_enable_1(ioaddr);
4199
4200         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4201
4202         RTL_W8(MaxTxPacketSize, TxPacketMax);
4203
4204         rtl_disable_clock_request(pdev);
4205 }
4206
4207 static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
4208 {
4209         static const struct ephy_info e_info_8168d_4[] = {
4210                 { 0x0b, ~0,     0x48 },
4211                 { 0x19, 0x20,   0x50 },
4212                 { 0x0c, ~0,     0x20 }
4213         };
4214         int i;
4215
4216         rtl_csi_access_enable_1(ioaddr);
4217
4218         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4219
4220         RTL_W8(MaxTxPacketSize, TxPacketMax);
4221
4222         for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4223                 const struct ephy_info *e = e_info_8168d_4 + i;
4224                 u16 w;
4225
4226                 w = rtl_ephy_read(ioaddr, e->offset);
4227                 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
4228         }
4229
4230         rtl_enable_clock_request(pdev);
4231 }
4232
4233 static void rtl_hw_start_8168e(void __iomem *ioaddr, struct pci_dev *pdev)
4234 {
4235         static const struct ephy_info e_info_8168e[] = {
4236                 { 0x00, 0x0200, 0x0100 },
4237                 { 0x00, 0x0000, 0x0004 },
4238                 { 0x06, 0x0002, 0x0001 },
4239                 { 0x06, 0x0000, 0x0030 },
4240                 { 0x07, 0x0000, 0x2000 },
4241                 { 0x00, 0x0000, 0x0020 },
4242                 { 0x03, 0x5800, 0x2000 },
4243                 { 0x03, 0x0000, 0x0001 },
4244                 { 0x01, 0x0800, 0x1000 },
4245                 { 0x07, 0x0000, 0x4000 },
4246                 { 0x1e, 0x0000, 0x2000 },
4247                 { 0x19, 0xffff, 0xfe6c },
4248                 { 0x0a, 0x0000, 0x0040 }
4249         };
4250
4251         rtl_csi_access_enable_2(ioaddr);
4252
4253         rtl_ephy_init(ioaddr, e_info_8168e, ARRAY_SIZE(e_info_8168e));
4254
4255         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4256
4257         RTL_W8(MaxTxPacketSize, TxPacketMax);
4258
4259         rtl_disable_clock_request(pdev);
4260
4261         /* Reset tx FIFO pointer */
4262         RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
4263         RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
4264
4265         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4266 }
4267
4268 static void rtl_hw_start_8168(struct net_device *dev)
4269 {
4270         struct rtl8169_private *tp = netdev_priv(dev);
4271         void __iomem *ioaddr = tp->mmio_addr;
4272         struct pci_dev *pdev = tp->pci_dev;
4273
4274         RTL_W8(Cfg9346, Cfg9346_Unlock);
4275
4276         RTL_W8(MaxTxPacketSize, TxPacketMax);
4277
4278         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4279
4280         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
4281
4282         RTL_W16(CPlusCmd, tp->cp_cmd);
4283
4284         RTL_W16(IntrMitigate, 0x5151);
4285
4286         /* Work around for RxFIFO overflow. */
4287         if (tp->mac_version == RTL_GIGA_MAC_VER_11 ||
4288             tp->mac_version == RTL_GIGA_MAC_VER_22) {
4289                 tp->intr_event |= RxFIFOOver | PCSTimeout;
4290                 tp->intr_event &= ~RxOverflow;
4291         }
4292
4293         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4294
4295         rtl_set_rx_mode(dev);
4296
4297         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4298                 (InterFrameGap << TxInterFrameGapShift));
4299
4300         RTL_R8(IntrMask);
4301
4302         switch (tp->mac_version) {
4303         case RTL_GIGA_MAC_VER_11:
4304                 rtl_hw_start_8168bb(ioaddr, pdev);
4305                 break;
4306
4307         case RTL_GIGA_MAC_VER_12:
4308         case RTL_GIGA_MAC_VER_17:
4309                 rtl_hw_start_8168bef(ioaddr, pdev);
4310                 break;
4311
4312         case RTL_GIGA_MAC_VER_18:
4313                 rtl_hw_start_8168cp_1(ioaddr, pdev);
4314                 break;
4315
4316         case RTL_GIGA_MAC_VER_19:
4317                 rtl_hw_start_8168c_1(ioaddr, pdev);
4318                 break;
4319
4320         case RTL_GIGA_MAC_VER_20:
4321                 rtl_hw_start_8168c_2(ioaddr, pdev);
4322                 break;
4323
4324         case RTL_GIGA_MAC_VER_21:
4325                 rtl_hw_start_8168c_3(ioaddr, pdev);
4326                 break;
4327
4328         case RTL_GIGA_MAC_VER_22:
4329                 rtl_hw_start_8168c_4(ioaddr, pdev);
4330                 break;
4331
4332         case RTL_GIGA_MAC_VER_23:
4333                 rtl_hw_start_8168cp_2(ioaddr, pdev);
4334                 break;
4335
4336         case RTL_GIGA_MAC_VER_24:
4337                 rtl_hw_start_8168cp_3(ioaddr, pdev);
4338                 break;
4339
4340         case RTL_GIGA_MAC_VER_25:
4341         case RTL_GIGA_MAC_VER_26:
4342         case RTL_GIGA_MAC_VER_27:
4343                 rtl_hw_start_8168d(ioaddr, pdev);
4344                 break;
4345
4346         case RTL_GIGA_MAC_VER_28:
4347                 rtl_hw_start_8168d_4(ioaddr, pdev);
4348                 break;
4349
4350         case RTL_GIGA_MAC_VER_31:
4351                 rtl_hw_start_8168dp(ioaddr, pdev);
4352                 break;
4353
4354         case RTL_GIGA_MAC_VER_32:
4355         case RTL_GIGA_MAC_VER_33:
4356                 rtl_hw_start_8168e(ioaddr, pdev);
4357                 break;
4358
4359         default:
4360                 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
4361                         dev->name, tp->mac_version);
4362                 break;
4363         }
4364
4365         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4366
4367         RTL_W8(Cfg9346, Cfg9346_Lock);
4368
4369         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4370
4371         RTL_W16(IntrMask, tp->intr_event);
4372 }
4373
4374 #define R810X_CPCMD_QUIRK_MASK (\
4375         EnableBist | \
4376         Mac_dbgo_oe | \
4377         Force_half_dup | \
4378         Force_rxflow_en | \
4379         Force_txflow_en | \
4380         Cxpl_dbg_sel | \
4381         ASF | \
4382         PktCntrDisable | \
4383         Mac_dbgo_sel)
4384
4385 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4386 {
4387         static const struct ephy_info e_info_8102e_1[] = {
4388                 { 0x01, 0, 0x6e65 },
4389                 { 0x02, 0, 0x091f },
4390                 { 0x03, 0, 0xc2f9 },
4391                 { 0x06, 0, 0xafb5 },
4392                 { 0x07, 0, 0x0e00 },
4393                 { 0x19, 0, 0xec80 },
4394                 { 0x01, 0, 0x2e65 },
4395                 { 0x01, 0, 0x6e65 }
4396         };
4397         u8 cfg1;
4398
4399         rtl_csi_access_enable_2(ioaddr);
4400
4401         RTL_W8(DBG_REG, FIX_NAK_1);
4402
4403         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4404
4405         RTL_W8(Config1,
4406                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
4407         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4408
4409         cfg1 = RTL_R8(Config1);
4410         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
4411                 RTL_W8(Config1, cfg1 & ~LEDS0);
4412
4413         rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
4414 }
4415
4416 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4417 {
4418         rtl_csi_access_enable_2(ioaddr);
4419
4420         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4421
4422         RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
4423         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4424 }
4425
4426 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
4427 {
4428         rtl_hw_start_8102e_2(ioaddr, pdev);
4429
4430         rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
4431 }
4432
4433 static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4434 {
4435         static const struct ephy_info e_info_8105e_1[] = {
4436                 { 0x07, 0, 0x4000 },
4437                 { 0x19, 0, 0x0200 },
4438                 { 0x19, 0, 0x0020 },
4439                 { 0x1e, 0, 0x2000 },
4440                 { 0x03, 0, 0x0001 },
4441                 { 0x19, 0, 0x0100 },
4442                 { 0x19, 0, 0x0004 },
4443                 { 0x0a, 0, 0x0020 }
4444         };
4445
4446         /* Force LAN exit from ASPM if Rx/Tx are not idle */
4447         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
4448
4449         /* Disable Early Tally Counter */
4450         RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
4451
4452         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4453         RTL_W8(DLLPR, RTL_R8(DLLPR) | PM_SWITCH);
4454
4455         rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
4456 }
4457
4458 static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4459 {
4460         rtl_hw_start_8105e_1(ioaddr, pdev);
4461         rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
4462 }
4463
4464 static void rtl_hw_start_8101(struct net_device *dev)
4465 {
4466         struct rtl8169_private *tp = netdev_priv(dev);
4467         void __iomem *ioaddr = tp->mmio_addr;
4468         struct pci_dev *pdev = tp->pci_dev;
4469
4470         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
4471             tp->mac_version == RTL_GIGA_MAC_VER_16) {
4472                 int cap = tp->pcie_cap;
4473
4474                 if (cap) {
4475                         pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
4476                                               PCI_EXP_DEVCTL_NOSNOOP_EN);
4477                 }
4478         }
4479
4480         RTL_W8(Cfg9346, Cfg9346_Unlock);
4481
4482         switch (tp->mac_version) {
4483         case RTL_GIGA_MAC_VER_07:
4484                 rtl_hw_start_8102e_1(ioaddr, pdev);
4485                 break;
4486
4487         case RTL_GIGA_MAC_VER_08:
4488                 rtl_hw_start_8102e_3(ioaddr, pdev);
4489                 break;
4490
4491         case RTL_GIGA_MAC_VER_09:
4492                 rtl_hw_start_8102e_2(ioaddr, pdev);
4493                 break;
4494
4495         case RTL_GIGA_MAC_VER_29:
4496                 rtl_hw_start_8105e_1(ioaddr, pdev);
4497                 break;
4498         case RTL_GIGA_MAC_VER_30:
4499                 rtl_hw_start_8105e_2(ioaddr, pdev);
4500                 break;
4501         }
4502
4503         RTL_W8(Cfg9346, Cfg9346_Lock);
4504
4505         RTL_W8(MaxTxPacketSize, TxPacketMax);
4506
4507         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4508
4509         tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
4510         RTL_W16(CPlusCmd, tp->cp_cmd);
4511
4512         RTL_W16(IntrMitigate, 0x0000);
4513
4514         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4515
4516         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4517         rtl_set_rx_tx_config_registers(tp);
4518
4519         RTL_R8(IntrMask);
4520
4521         rtl_set_rx_mode(dev);
4522
4523         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
4524
4525         RTL_W16(IntrMask, tp->intr_event);
4526 }
4527
4528 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
4529 {
4530         struct rtl8169_private *tp = netdev_priv(dev);
4531
4532         if (new_mtu < ETH_ZLEN ||
4533             new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
4534                 return -EINVAL;
4535
4536         if (new_mtu > ETH_DATA_LEN)
4537                 rtl_hw_jumbo_enable(tp);
4538         else
4539                 rtl_hw_jumbo_disable(tp);
4540
4541         dev->mtu = new_mtu;
4542         netdev_update_features(dev);
4543
4544         return 0;
4545 }
4546
4547 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
4548 {
4549         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
4550         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
4551 }
4552
4553 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
4554                                      void **data_buff, struct RxDesc *desc)
4555 {
4556         dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
4557                          DMA_FROM_DEVICE);
4558
4559         kfree(*data_buff);
4560         *data_buff = NULL;
4561         rtl8169_make_unusable_by_asic(desc);
4562 }
4563
4564 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
4565 {
4566         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
4567
4568         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
4569 }
4570
4571 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
4572                                        u32 rx_buf_sz)
4573 {
4574         desc->addr = cpu_to_le64(mapping);
4575         wmb();
4576         rtl8169_mark_to_asic(desc, rx_buf_sz);
4577 }
4578
4579 static inline void *rtl8169_align(void *data)
4580 {
4581         return (void *)ALIGN((long)data, 16);
4582 }
4583
4584 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
4585                                              struct RxDesc *desc)
4586 {
4587         void *data;
4588         dma_addr_t mapping;
4589         struct device *d = &tp->pci_dev->dev;
4590         struct net_device *dev = tp->dev;
4591         int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
4592
4593         data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
4594         if (!data)
4595                 return NULL;
4596
4597         if (rtl8169_align(data) != data) {
4598                 kfree(data);
4599                 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
4600                 if (!data)
4601                         return NULL;
4602         }
4603
4604         mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
4605                                  DMA_FROM_DEVICE);
4606         if (unlikely(dma_mapping_error(d, mapping))) {
4607                 if (net_ratelimit())
4608                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
4609                 goto err_out;
4610         }
4611
4612         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
4613         return data;
4614
4615 err_out:
4616         kfree(data);
4617         return NULL;
4618 }
4619
4620 static void rtl8169_rx_clear(struct rtl8169_private *tp)
4621 {
4622         unsigned int i;
4623
4624         for (i = 0; i < NUM_RX_DESC; i++) {
4625                 if (tp->Rx_databuff[i]) {
4626                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
4627                                             tp->RxDescArray + i);
4628                 }
4629         }
4630 }
4631
4632 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
4633 {
4634         desc->opts1 |= cpu_to_le32(RingEnd);
4635 }
4636
4637 static int rtl8169_rx_fill(struct rtl8169_private *tp)
4638 {
4639         unsigned int i;
4640
4641         for (i = 0; i < NUM_RX_DESC; i++) {
4642                 void *data;
4643
4644                 if (tp->Rx_databuff[i])
4645                         continue;
4646
4647                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
4648                 if (!data) {
4649                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
4650                         goto err_out;
4651                 }
4652                 tp->Rx_databuff[i] = data;
4653         }
4654
4655         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4656         return 0;
4657
4658 err_out:
4659         rtl8169_rx_clear(tp);
4660         return -ENOMEM;
4661 }
4662
4663 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4664 {
4665         tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
4666 }
4667
4668 static int rtl8169_init_ring(struct net_device *dev)
4669 {
4670         struct rtl8169_private *tp = netdev_priv(dev);
4671
4672         rtl8169_init_ring_indexes(tp);
4673
4674         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
4675         memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
4676
4677         return rtl8169_rx_fill(tp);
4678 }
4679
4680 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
4681                                  struct TxDesc *desc)
4682 {
4683         unsigned int len = tx_skb->len;
4684
4685         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
4686
4687         desc->opts1 = 0x00;
4688         desc->opts2 = 0x00;
4689         desc->addr = 0x00;
4690         tx_skb->len = 0;
4691 }
4692
4693 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4694                                    unsigned int n)
4695 {
4696         unsigned int i;
4697
4698         for (i = 0; i < n; i++) {
4699                 unsigned int entry = (start + i) % NUM_TX_DESC;
4700                 struct ring_info *tx_skb = tp->tx_skb + entry;
4701                 unsigned int len = tx_skb->len;
4702
4703                 if (len) {
4704                         struct sk_buff *skb = tx_skb->skb;
4705
4706                         rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4707                                              tp->TxDescArray + entry);
4708                         if (skb) {
4709                                 tp->dev->stats.tx_dropped++;
4710                                 dev_kfree_skb(skb);
4711                                 tx_skb->skb = NULL;
4712                         }
4713                 }
4714         }
4715 }
4716
4717 static void rtl8169_tx_clear(struct rtl8169_private *tp)
4718 {
4719         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
4720         tp->cur_tx = tp->dirty_tx = 0;
4721 }
4722
4723 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
4724 {
4725         struct rtl8169_private *tp = netdev_priv(dev);
4726
4727         PREPARE_DELAYED_WORK(&tp->task, task);
4728         schedule_delayed_work(&tp->task, 4);
4729 }
4730
4731 static void rtl8169_wait_for_quiescence(struct net_device *dev)
4732 {
4733         struct rtl8169_private *tp = netdev_priv(dev);
4734         void __iomem *ioaddr = tp->mmio_addr;
4735
4736         synchronize_irq(dev->irq);
4737
4738         /* Wait for any pending NAPI task to complete */
4739         napi_disable(&tp->napi);
4740
4741         rtl8169_irq_mask_and_ack(ioaddr);
4742
4743         tp->intr_mask = 0xffff;
4744         RTL_W16(IntrMask, tp->intr_event);
4745         napi_enable(&tp->napi);
4746 }
4747
4748 static void rtl8169_reinit_task(struct work_struct *work)
4749 {
4750         struct rtl8169_private *tp =
4751                 container_of(work, struct rtl8169_private, task.work);
4752         struct net_device *dev = tp->dev;
4753         int ret;
4754
4755         rtnl_lock();
4756
4757         if (!netif_running(dev))
4758                 goto out_unlock;
4759
4760         rtl8169_wait_for_quiescence(dev);
4761         rtl8169_close(dev);
4762
4763         ret = rtl8169_open(dev);
4764         if (unlikely(ret < 0)) {
4765                 if (net_ratelimit())
4766                         netif_err(tp, drv, dev,
4767                                   "reinit failure (status = %d). Rescheduling\n",
4768                                   ret);
4769                 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4770         }
4771
4772 out_unlock:
4773         rtnl_unlock();
4774 }
4775
4776 static void rtl8169_reset_task(struct work_struct *work)
4777 {
4778         struct rtl8169_private *tp =
4779                 container_of(work, struct rtl8169_private, task.work);
4780         struct net_device *dev = tp->dev;
4781         int i;
4782
4783         rtnl_lock();
4784
4785         if (!netif_running(dev))
4786                 goto out_unlock;
4787
4788         rtl8169_wait_for_quiescence(dev);
4789
4790         for (i = 0; i < NUM_RX_DESC; i++)
4791                 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
4792
4793         rtl8169_tx_clear(tp);
4794
4795         rtl8169_init_ring_indexes(tp);
4796         rtl_hw_start(dev);
4797         netif_wake_queue(dev);
4798         rtl8169_check_link_status(dev, tp, tp->mmio_addr);
4799
4800 out_unlock:
4801         rtnl_unlock();
4802 }
4803
4804 static void rtl8169_tx_timeout(struct net_device *dev)
4805 {
4806         struct rtl8169_private *tp = netdev_priv(dev);
4807
4808         rtl8169_hw_reset(tp);
4809
4810         /* Let's wait a bit while any (async) irq lands on */
4811         rtl8169_schedule_work(dev, rtl8169_reset_task);
4812 }
4813
4814 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4815                               u32 *opts)
4816 {
4817         struct skb_shared_info *info = skb_shinfo(skb);
4818         unsigned int cur_frag, entry;
4819         struct TxDesc * uninitialized_var(txd);
4820         struct device *d = &tp->pci_dev->dev;
4821
4822         entry = tp->cur_tx;
4823         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4824                 skb_frag_t *frag = info->frags + cur_frag;
4825                 dma_addr_t mapping;
4826                 u32 status, len;
4827                 void *addr;
4828
4829                 entry = (entry + 1) % NUM_TX_DESC;
4830
4831                 txd = tp->TxDescArray + entry;
4832                 len = frag->size;
4833                 addr = ((void *) page_address(frag->page)) + frag->page_offset;
4834                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
4835                 if (unlikely(dma_mapping_error(d, mapping))) {
4836                         if (net_ratelimit())
4837                                 netif_err(tp, drv, tp->dev,
4838                                           "Failed to map TX fragments DMA!\n");
4839                         goto err_out;
4840                 }
4841
4842                 /* Anti gcc 2.95.3 bugware (sic) */
4843                 status = opts[0] | len |
4844                         (RingEnd * !((entry + 1) % NUM_TX_DESC));
4845
4846                 txd->opts1 = cpu_to_le32(status);
4847                 txd->opts2 = cpu_to_le32(opts[1]);
4848                 txd->addr = cpu_to_le64(mapping);
4849
4850                 tp->tx_skb[entry].len = len;
4851         }
4852
4853         if (cur_frag) {
4854                 tp->tx_skb[entry].skb = skb;
4855                 txd->opts1 |= cpu_to_le32(LastFrag);
4856         }
4857
4858         return cur_frag;
4859
4860 err_out:
4861         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4862         return -EIO;
4863 }
4864
4865 static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
4866                                     struct sk_buff *skb, u32 *opts)
4867 {
4868         const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
4869         u32 mss = skb_shinfo(skb)->gso_size;
4870         int offset = info->opts_offset;
4871
4872         if (mss) {
4873                 opts[0] |= TD_LSO;
4874                 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
4875         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4876                 const struct iphdr *ip = ip_hdr(skb);
4877
4878                 if (ip->protocol == IPPROTO_TCP)
4879                         opts[offset] |= info->checksum.tcp;
4880                 else if (ip->protocol == IPPROTO_UDP)
4881                         opts[offset] |= info->checksum.udp;
4882                 else
4883                         WARN_ON_ONCE(1);
4884         }
4885 }
4886
4887 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4888                                       struct net_device *dev)
4889 {
4890         struct rtl8169_private *tp = netdev_priv(dev);
4891         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
4892         struct TxDesc *txd = tp->TxDescArray + entry;
4893         void __iomem *ioaddr = tp->mmio_addr;
4894         struct device *d = &tp->pci_dev->dev;
4895         dma_addr_t mapping;
4896         u32 status, len;
4897         u32 opts[2];
4898         int frags;
4899
4900         if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
4901                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
4902                 goto err_stop_0;
4903         }
4904
4905         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
4906                 goto err_stop_0;
4907
4908         len = skb_headlen(skb);
4909         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
4910         if (unlikely(dma_mapping_error(d, mapping))) {
4911                 if (net_ratelimit())
4912                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
4913                 goto err_dma_0;
4914         }
4915
4916         tp->tx_skb[entry].len = len;
4917         txd->addr = cpu_to_le64(mapping);
4918
4919         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
4920         opts[0] = DescOwn;
4921
4922         rtl8169_tso_csum(tp, skb, opts);
4923
4924         frags = rtl8169_xmit_frags(tp, skb, opts);
4925         if (frags < 0)
4926                 goto err_dma_1;
4927         else if (frags)
4928                 opts[0] |= FirstFrag;
4929         else {
4930                 opts[0] |= FirstFrag | LastFrag;
4931                 tp->tx_skb[entry].skb = skb;
4932         }
4933
4934         txd->opts2 = cpu_to_le32(opts[1]);
4935
4936         wmb();
4937
4938         /* Anti gcc 2.95.3 bugware (sic) */
4939         status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4940         txd->opts1 = cpu_to_le32(status);
4941
4942         tp->cur_tx += frags + 1;
4943
4944         wmb();
4945
4946         RTL_W8(TxPoll, NPQ);
4947
4948         if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
4949                 netif_stop_queue(dev);
4950                 smp_rmb();
4951                 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
4952                         netif_wake_queue(dev);
4953         }
4954
4955         return NETDEV_TX_OK;
4956
4957 err_dma_1:
4958         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
4959 err_dma_0:
4960         dev_kfree_skb(skb);
4961         dev->stats.tx_dropped++;
4962         return NETDEV_TX_OK;
4963
4964 err_stop_0:
4965         netif_stop_queue(dev);
4966         dev->stats.tx_dropped++;
4967         return NETDEV_TX_BUSY;
4968 }
4969
4970 static void rtl8169_pcierr_interrupt(struct net_device *dev)
4971 {
4972         struct rtl8169_private *tp = netdev_priv(dev);
4973         struct pci_dev *pdev = tp->pci_dev;
4974         u16 pci_status, pci_cmd;
4975
4976         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4977         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
4978
4979         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
4980                   pci_cmd, pci_status);
4981
4982         /*
4983          * The recovery sequence below admits a very elaborated explanation:
4984          * - it seems to work;
4985          * - I did not see what else could be done;
4986          * - it makes iop3xx happy.
4987          *
4988          * Feel free to adjust to your needs.
4989          */
4990         if (pdev->broken_parity_status)
4991                 pci_cmd &= ~PCI_COMMAND_PARITY;
4992         else
4993                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
4994
4995         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
4996
4997         pci_write_config_word(pdev, PCI_STATUS,
4998                 pci_status & (PCI_STATUS_DETECTED_PARITY |
4999                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5000                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5001
5002         /* The infamous DAC f*ckup only happens at boot time */
5003         if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
5004                 void __iomem *ioaddr = tp->mmio_addr;
5005
5006                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
5007                 tp->cp_cmd &= ~PCIDAC;
5008                 RTL_W16(CPlusCmd, tp->cp_cmd);
5009                 dev->features &= ~NETIF_F_HIGHDMA;
5010         }
5011
5012         rtl8169_hw_reset(tp);
5013
5014         rtl8169_schedule_work(dev, rtl8169_reinit_task);
5015 }
5016
5017 static void rtl8169_tx_interrupt(struct net_device *dev,
5018                                  struct rtl8169_private *tp,
5019                                  void __iomem *ioaddr)
5020 {
5021         unsigned int dirty_tx, tx_left;
5022
5023         dirty_tx = tp->dirty_tx;
5024         smp_rmb();
5025         tx_left = tp->cur_tx - dirty_tx;
5026
5027         while (tx_left > 0) {
5028                 unsigned int entry = dirty_tx % NUM_TX_DESC;
5029                 struct ring_info *tx_skb = tp->tx_skb + entry;
5030                 u32 status;
5031
5032                 rmb();
5033                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5034                 if (status & DescOwn)
5035                         break;
5036
5037                 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5038                                      tp->TxDescArray + entry);
5039                 if (status & LastFrag) {
5040                         dev->stats.tx_packets++;
5041                         dev->stats.tx_bytes += tx_skb->skb->len;
5042                         dev_kfree_skb(tx_skb->skb);
5043                         tx_skb->skb = NULL;
5044                 }
5045                 dirty_tx++;
5046                 tx_left--;
5047         }
5048
5049         if (tp->dirty_tx != dirty_tx) {
5050                 tp->dirty_tx = dirty_tx;
5051                 smp_wmb();
5052                 if (netif_queue_stopped(dev) &&
5053                     (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
5054                         netif_wake_queue(dev);
5055                 }
5056                 /*
5057                  * 8168 hack: TxPoll requests are lost when the Tx packets are
5058                  * too close. Let's kick an extra TxPoll request when a burst
5059                  * of start_xmit activity is detected (if it is not detected,
5060                  * it is slow enough). -- FR
5061                  */
5062                 smp_rmb();
5063                 if (tp->cur_tx != dirty_tx)
5064                         RTL_W8(TxPoll, NPQ);
5065         }
5066 }
5067
5068 static inline int rtl8169_fragmented_frame(u32 status)
5069 {
5070         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
5071 }
5072
5073 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
5074 {
5075         u32 status = opts1 & RxProtoMask;
5076
5077         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
5078             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
5079                 skb->ip_summed = CHECKSUM_UNNECESSARY;
5080         else
5081                 skb_checksum_none_assert(skb);
5082 }
5083
5084 static struct sk_buff *rtl8169_try_rx_copy(void *data,
5085                                            struct rtl8169_private *tp,
5086                                            int pkt_size,
5087                                            dma_addr_t addr)
5088 {
5089         struct sk_buff *skb;
5090         struct device *d = &tp->pci_dev->dev;
5091
5092         data = rtl8169_align(data);
5093         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
5094         prefetch(data);
5095         skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
5096         if (skb)
5097                 memcpy(skb->data, data, pkt_size);
5098         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
5099
5100         return skb;
5101 }
5102
5103 static int rtl8169_rx_interrupt(struct net_device *dev,
5104                                 struct rtl8169_private *tp,
5105                                 void __iomem *ioaddr, u32 budget)
5106 {
5107         unsigned int cur_rx, rx_left;
5108         unsigned int count;
5109
5110         cur_rx = tp->cur_rx;
5111         rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
5112         rx_left = min(rx_left, budget);
5113
5114         for (; rx_left > 0; rx_left--, cur_rx++) {
5115                 unsigned int entry = cur_rx % NUM_RX_DESC;
5116                 struct RxDesc *desc = tp->RxDescArray + entry;
5117                 u32 status;
5118
5119                 rmb();
5120                 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
5121
5122                 if (status & DescOwn)
5123                         break;
5124                 if (unlikely(status & RxRES)) {
5125                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
5126                                    status);
5127                         dev->stats.rx_errors++;
5128                         if (status & (RxRWT | RxRUNT))
5129                                 dev->stats.rx_length_errors++;
5130                         if (status & RxCRC)
5131                                 dev->stats.rx_crc_errors++;
5132                         if (status & RxFOVF) {
5133                                 rtl8169_schedule_work(dev, rtl8169_reset_task);
5134                                 dev->stats.rx_fifo_errors++;
5135                         }
5136                         rtl8169_mark_to_asic(desc, rx_buf_sz);
5137                 } else {
5138                         struct sk_buff *skb;
5139                         dma_addr_t addr = le64_to_cpu(desc->addr);
5140                         int pkt_size = (status & 0x00003fff) - 4;
5141
5142                         /*
5143                          * The driver does not support incoming fragmented
5144                          * frames. They are seen as a symptom of over-mtu
5145                          * sized frames.
5146                          */
5147                         if (unlikely(rtl8169_fragmented_frame(status))) {
5148                                 dev->stats.rx_dropped++;
5149                                 dev->stats.rx_length_errors++;
5150                                 rtl8169_mark_to_asic(desc, rx_buf_sz);
5151                                 continue;
5152                         }
5153
5154                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
5155                                                   tp, pkt_size, addr);
5156                         rtl8169_mark_to_asic(desc, rx_buf_sz);
5157                         if (!skb) {
5158                                 dev->stats.rx_dropped++;
5159                                 continue;
5160                         }
5161
5162                         rtl8169_rx_csum(skb, status);
5163                         skb_put(skb, pkt_size);
5164                         skb->protocol = eth_type_trans(skb, dev);
5165
5166                         rtl8169_rx_vlan_tag(desc, skb);
5167
5168                         napi_gro_receive(&tp->napi, skb);
5169
5170                         dev->stats.rx_bytes += pkt_size;
5171                         dev->stats.rx_packets++;
5172                 }
5173
5174                 /* Work around for AMD plateform. */
5175                 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
5176                     (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
5177                         desc->opts2 = 0;
5178                         cur_rx++;
5179                 }
5180         }
5181
5182         count = cur_rx - tp->cur_rx;
5183         tp->cur_rx = cur_rx;
5184
5185         tp->dirty_rx += count;
5186
5187         return count;
5188 }
5189
5190 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
5191 {
5192         struct net_device *dev = dev_instance;
5193         struct rtl8169_private *tp = netdev_priv(dev);
5194         void __iomem *ioaddr = tp->mmio_addr;
5195         int handled = 0;
5196         int status;
5197
5198         /* loop handling interrupts until we have no new ones or
5199          * we hit a invalid/hotplug case.
5200          */
5201         status = RTL_R16(IntrStatus);
5202         while (status && status != 0xffff) {
5203                 handled = 1;
5204
5205                 /* Handle all of the error cases first. These will reset
5206                  * the chip, so just exit the loop.
5207                  */
5208                 if (unlikely(!netif_running(dev))) {
5209                         rtl8169_asic_down(ioaddr);
5210                         break;
5211                 }
5212
5213                 if (unlikely(status & RxFIFOOver)) {
5214                         switch (tp->mac_version) {
5215                         /* Work around for rx fifo overflow */
5216                         case RTL_GIGA_MAC_VER_11:
5217                         case RTL_GIGA_MAC_VER_22:
5218                         case RTL_GIGA_MAC_VER_26:
5219                                 netif_stop_queue(dev);
5220                                 rtl8169_tx_timeout(dev);
5221                                 goto done;
5222                         /* Testers needed. */
5223                         case RTL_GIGA_MAC_VER_17:
5224                         case RTL_GIGA_MAC_VER_19:
5225                         case RTL_GIGA_MAC_VER_20:
5226                         case RTL_GIGA_MAC_VER_21:
5227                         case RTL_GIGA_MAC_VER_23:
5228                         case RTL_GIGA_MAC_VER_24:
5229                         case RTL_GIGA_MAC_VER_27:
5230                         case RTL_GIGA_MAC_VER_28:
5231                         case RTL_GIGA_MAC_VER_31:
5232                         /* Experimental science. Pktgen proof. */
5233                         case RTL_GIGA_MAC_VER_12:
5234                         case RTL_GIGA_MAC_VER_25:
5235                                 if (status == RxFIFOOver)
5236                                         goto done;
5237                                 break;
5238                         default:
5239                                 break;
5240                         }
5241                 }
5242
5243                 if (unlikely(status & SYSErr)) {
5244                         rtl8169_pcierr_interrupt(dev);
5245                         break;
5246                 }
5247
5248                 if (status & LinkChg)
5249                         __rtl8169_check_link_status(dev, tp, ioaddr, true);
5250
5251                 /* We need to see the lastest version of tp->intr_mask to
5252                  * avoid ignoring an MSI interrupt and having to wait for
5253                  * another event which may never come.
5254                  */
5255                 smp_rmb();
5256                 if (status & tp->intr_mask & tp->napi_event) {
5257                         RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
5258                         tp->intr_mask = ~tp->napi_event;
5259
5260                         if (likely(napi_schedule_prep(&tp->napi)))
5261                                 __napi_schedule(&tp->napi);
5262                         else
5263                                 netif_info(tp, intr, dev,
5264                                            "interrupt %04x in poll\n", status);
5265                 }
5266
5267                 /* We only get a new MSI interrupt when all active irq
5268                  * sources on the chip have been acknowledged. So, ack
5269                  * everything we've seen and check if new sources have become
5270                  * active to avoid blocking all interrupts from the chip.
5271                  */
5272                 RTL_W16(IntrStatus,
5273                         (status & RxFIFOOver) ? (status | RxOverflow) : status);
5274                 status = RTL_R16(IntrStatus);
5275         }
5276 done:
5277         return IRQ_RETVAL(handled);
5278 }
5279
5280 static int rtl8169_poll(struct napi_struct *napi, int budget)
5281 {
5282         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5283         struct net_device *dev = tp->dev;
5284         void __iomem *ioaddr = tp->mmio_addr;
5285         int work_done;
5286
5287         work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
5288         rtl8169_tx_interrupt(dev, tp, ioaddr);
5289
5290         if (work_done < budget) {
5291                 napi_complete(napi);
5292
5293                 /* We need for force the visibility of tp->intr_mask
5294                  * for other CPUs, as we can loose an MSI interrupt
5295                  * and potentially wait for a retransmit timeout if we don't.
5296                  * The posted write to IntrMask is safe, as it will
5297                  * eventually make it to the chip and we won't loose anything
5298                  * until it does.
5299                  */
5300                 tp->intr_mask = 0xffff;
5301                 wmb();
5302                 RTL_W16(IntrMask, tp->intr_event);
5303         }
5304
5305         return work_done;
5306 }
5307
5308 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
5309 {
5310         struct rtl8169_private *tp = netdev_priv(dev);
5311
5312         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5313                 return;
5314
5315         dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
5316         RTL_W32(RxMissed, 0);
5317 }
5318
5319 static void rtl8169_down(struct net_device *dev)
5320 {
5321         struct rtl8169_private *tp = netdev_priv(dev);
5322         void __iomem *ioaddr = tp->mmio_addr;
5323
5324         del_timer_sync(&tp->timer);
5325
5326         netif_stop_queue(dev);
5327
5328         napi_disable(&tp->napi);
5329
5330         spin_lock_irq(&tp->lock);
5331
5332         rtl8169_asic_down(ioaddr);
5333         /*
5334          * At this point device interrupts can not be enabled in any function,
5335          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
5336          * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
5337          */
5338         rtl8169_rx_missed(dev, ioaddr);
5339
5340         spin_unlock_irq(&tp->lock);
5341
5342         synchronize_irq(dev->irq);
5343
5344         /* Give a racing hard_start_xmit a few cycles to complete. */
5345         synchronize_sched();  /* FIXME: should this be synchronize_irq()? */
5346
5347         rtl8169_tx_clear(tp);
5348
5349         rtl8169_rx_clear(tp);
5350
5351         rtl_pll_power_down(tp);
5352 }
5353
5354 static int rtl8169_close(struct net_device *dev)
5355 {
5356         struct rtl8169_private *tp = netdev_priv(dev);
5357         struct pci_dev *pdev = tp->pci_dev;
5358
5359         pm_runtime_get_sync(&pdev->dev);
5360
5361         /* Update counters before going down */
5362         rtl8169_update_counters(dev);
5363
5364         rtl8169_down(dev);
5365
5366         free_irq(dev->irq, dev);
5367
5368         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5369                           tp->RxPhyAddr);
5370         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5371                           tp->TxPhyAddr);
5372         tp->TxDescArray = NULL;
5373         tp->RxDescArray = NULL;
5374
5375         pm_runtime_put_sync(&pdev->dev);
5376
5377         return 0;
5378 }
5379
5380 static void rtl_set_rx_mode(struct net_device *dev)
5381 {
5382         struct rtl8169_private *tp = netdev_priv(dev);
5383         void __iomem *ioaddr = tp->mmio_addr;
5384         unsigned long flags;
5385         u32 mc_filter[2];       /* Multicast hash filter */
5386         int rx_mode;
5387         u32 tmp = 0;
5388
5389         if (dev->flags & IFF_PROMISC) {
5390                 /* Unconditionally log net taps. */
5391                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
5392                 rx_mode =
5393                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5394                     AcceptAllPhys;
5395                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5396         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
5397                    (dev->flags & IFF_ALLMULTI)) {
5398                 /* Too many to filter perfectly -- accept all multicasts. */
5399                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5400                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5401         } else {
5402                 struct netdev_hw_addr *ha;
5403
5404                 rx_mode = AcceptBroadcast | AcceptMyPhys;
5405                 mc_filter[1] = mc_filter[0] = 0;
5406                 netdev_for_each_mc_addr(ha, dev) {
5407                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
5408                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5409                         rx_mode |= AcceptMulticast;
5410                 }
5411         }
5412
5413         spin_lock_irqsave(&tp->lock, flags);
5414
5415         tmp = rtl8169_rx_config | rx_mode |
5416               (RTL_R32(RxConfig) & RTL_RX_CONFIG_MASK);
5417
5418         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
5419                 u32 data = mc_filter[0];
5420
5421                 mc_filter[0] = swab32(mc_filter[1]);
5422                 mc_filter[1] = swab32(data);
5423         }
5424
5425         RTL_W32(MAR0 + 4, mc_filter[1]);
5426         RTL_W32(MAR0 + 0, mc_filter[0]);
5427
5428         RTL_W32(RxConfig, tmp);
5429
5430         spin_unlock_irqrestore(&tp->lock, flags);
5431 }
5432
5433 /**
5434  *  rtl8169_get_stats - Get rtl8169 read/write statistics
5435  *  @dev: The Ethernet Device to get statistics for
5436  *
5437  *  Get TX/RX statistics for rtl8169
5438  */
5439 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
5440 {
5441         struct rtl8169_private *tp = netdev_priv(dev);
5442         void __iomem *ioaddr = tp->mmio_addr;
5443         unsigned long flags;
5444
5445         if (netif_running(dev)) {
5446                 spin_lock_irqsave(&tp->lock, flags);
5447                 rtl8169_rx_missed(dev, ioaddr);
5448                 spin_unlock_irqrestore(&tp->lock, flags);
5449         }
5450
5451         return &dev->stats;
5452 }
5453
5454 static void rtl8169_net_suspend(struct net_device *dev)
5455 {
5456         struct rtl8169_private *tp = netdev_priv(dev);
5457
5458         if (!netif_running(dev))
5459                 return;
5460
5461         rtl_pll_power_down(tp);
5462
5463         netif_device_detach(dev);
5464         netif_stop_queue(dev);
5465 }
5466
5467 #ifdef CONFIG_PM
5468
5469 static int rtl8169_suspend(struct device *device)
5470 {
5471         struct pci_dev *pdev = to_pci_dev(device);
5472         struct net_device *dev = pci_get_drvdata(pdev);
5473
5474         rtl8169_net_suspend(dev);
5475
5476         return 0;
5477 }
5478
5479 static void __rtl8169_resume(struct net_device *dev)
5480 {
5481         struct rtl8169_private *tp = netdev_priv(dev);
5482
5483         netif_device_attach(dev);
5484
5485         rtl_pll_power_up(tp);
5486
5487         rtl8169_schedule_work(dev, rtl8169_reset_task);
5488 }
5489
5490 static int rtl8169_resume(struct device *device)
5491 {
5492         struct pci_dev *pdev = to_pci_dev(device);
5493         struct net_device *dev = pci_get_drvdata(pdev);
5494         struct rtl8169_private *tp = netdev_priv(dev);
5495
5496         rtl8169_init_phy(dev, tp);
5497
5498         if (netif_running(dev))
5499                 __rtl8169_resume(dev);
5500
5501         return 0;
5502 }
5503
5504 static int rtl8169_runtime_suspend(struct device *device)
5505 {
5506         struct pci_dev *pdev = to_pci_dev(device);
5507         struct net_device *dev = pci_get_drvdata(pdev);
5508         struct rtl8169_private *tp = netdev_priv(dev);
5509
5510         if (!tp->TxDescArray)
5511                 return 0;
5512
5513         spin_lock_irq(&tp->lock);
5514         tp->saved_wolopts = __rtl8169_get_wol(tp);
5515         __rtl8169_set_wol(tp, WAKE_ANY);
5516         spin_unlock_irq(&tp->lock);
5517
5518         rtl8169_net_suspend(dev);
5519
5520         return 0;
5521 }
5522
5523 static int rtl8169_runtime_resume(struct device *device)
5524 {
5525         struct pci_dev *pdev = to_pci_dev(device);
5526         struct net_device *dev = pci_get_drvdata(pdev);
5527         struct rtl8169_private *tp = netdev_priv(dev);
5528
5529         if (!tp->TxDescArray)
5530                 return 0;
5531
5532         spin_lock_irq(&tp->lock);
5533         __rtl8169_set_wol(tp, tp->saved_wolopts);
5534         tp->saved_wolopts = 0;
5535         spin_unlock_irq(&tp->lock);
5536
5537         rtl8169_init_phy(dev, tp);
5538
5539         __rtl8169_resume(dev);
5540
5541         return 0;
5542 }
5543
5544 static int rtl8169_runtime_idle(struct device *device)
5545 {
5546         struct pci_dev *pdev = to_pci_dev(device);
5547         struct net_device *dev = pci_get_drvdata(pdev);
5548         struct rtl8169_private *tp = netdev_priv(dev);
5549
5550         return tp->TxDescArray ? -EBUSY : 0;
5551 }
5552
5553 static const struct dev_pm_ops rtl8169_pm_ops = {
5554         .suspend                = rtl8169_suspend,
5555         .resume                 = rtl8169_resume,
5556         .freeze                 = rtl8169_suspend,
5557         .thaw                   = rtl8169_resume,
5558         .poweroff               = rtl8169_suspend,
5559         .restore                = rtl8169_resume,
5560         .runtime_suspend        = rtl8169_runtime_suspend,
5561         .runtime_resume         = rtl8169_runtime_resume,
5562         .runtime_idle           = rtl8169_runtime_idle,
5563 };
5564
5565 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
5566
5567 #else /* !CONFIG_PM */
5568
5569 #define RTL8169_PM_OPS  NULL
5570
5571 #endif /* !CONFIG_PM */
5572
5573 static void rtl_shutdown(struct pci_dev *pdev)
5574 {
5575         struct net_device *dev = pci_get_drvdata(pdev);
5576         struct rtl8169_private *tp = netdev_priv(dev);
5577         void __iomem *ioaddr = tp->mmio_addr;
5578
5579         rtl8169_net_suspend(dev);
5580
5581         /* Restore original MAC address */
5582         rtl_rar_set(tp, dev->perm_addr);
5583
5584         spin_lock_irq(&tp->lock);
5585
5586         rtl8169_asic_down(ioaddr);
5587
5588         spin_unlock_irq(&tp->lock);
5589
5590         if (system_state == SYSTEM_POWER_OFF) {
5591                 /* WoL fails with 8168b when the receiver is disabled. */
5592                 if ((tp->mac_version == RTL_GIGA_MAC_VER_11 ||
5593                      tp->mac_version == RTL_GIGA_MAC_VER_12 ||
5594                      tp->mac_version == RTL_GIGA_MAC_VER_17) &&
5595                     (tp->features & RTL_FEATURE_WOL)) {
5596                         pci_clear_master(pdev);
5597
5598                         RTL_W8(ChipCmd, CmdRxEnb);
5599                         /* PCI commit */
5600                         RTL_R8(ChipCmd);
5601                 }
5602
5603                 pci_wake_from_d3(pdev, true);
5604                 pci_set_power_state(pdev, PCI_D3hot);
5605         }
5606 }
5607
5608 static struct pci_driver rtl8169_pci_driver = {
5609         .name           = MODULENAME,
5610         .id_table       = rtl8169_pci_tbl,
5611         .probe          = rtl8169_init_one,
5612         .remove         = __devexit_p(rtl8169_remove_one),
5613         .shutdown       = rtl_shutdown,
5614         .driver.pm      = RTL8169_PM_OPS,
5615 };
5616
5617 static int __init rtl8169_init_module(void)
5618 {
5619         return pci_register_driver(&rtl8169_pci_driver);
5620 }
5621
5622 static void __exit rtl8169_cleanup_module(void)
5623 {
5624         pci_unregister_driver(&rtl8169_pci_driver);
5625 }
5626
5627 module_init(rtl8169_init_module);
5628 module_exit(rtl8169_cleanup_module);