drivers/net/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/mii.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/crc32.h>
  21 #include <linux/in.h>
  22 #include <linux/ip.h>
  23 #include <linux/tcp.h>
  24 #include <linux/init.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/firmware.h>
  28 #include <linux/pci-aspm.h>
  29 #include <linux/prefetch.h>
  30
  31 #include <asm/system.h>
  32 #include <asm/io.h>
  33 #include <asm/irq.h>
  34
  35 #define RTL8169_VERSION "2.3LK-NAPI"
  36 #define MODULENAME "r8169"
  37 #define PFX MODULENAME ": "
  38
  39 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  40 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  41 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  42 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  43 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  44
  45 #ifdef RTL8169_DEBUG
  46 #define assert(expr) \
  47         if (!(expr)) {                                  \
  48                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  49                 #expr,__FILE__,__func__,__LINE__);              \
  50         }
  51 #define dprintk(fmt, args...) \
  52         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
  53 #else
  54 #define assert(expr) do {} while (0)
  55 #define dprintk(fmt, args...)   do {} while (0)
  56 #endif /* RTL8169_DEBUG */
  57
  58 #define R8169_MSG_DEFAULT \
  59         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  60
  61 #define TX_BUFFS_AVAIL(tp) \
  62         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
  63
  64 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  65    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  66 static const int multicast_filter_limit = 32;
  67
  68 /* MAC address length */
  69 #define MAC_ADDR_LEN    6
  70
  71 #define MAX_READ_REQUEST_SHIFT  12
  72 #define RX_FIFO_THRESH  7       /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
  73 #define RX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  74 #define TX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  75 #define SafeMtu         0x1c20  /* ... actually life sucks beyond ~7k */
  76 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  77
  78 #define R8169_REGS_SIZE         256
  79 #define R8169_NAPI_WEIGHT       64
  80 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  81 #define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
  82 #define RX_BUF_SIZE     1536    /* Rx Buffer size */
  83 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  84 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  85
  86 #define RTL8169_TX_TIMEOUT      (6*HZ)
  87 #define RTL8169_PHY_TIMEOUT     (10*HZ)
  88
  89 #define RTL_EEPROM_SIG          cpu_to_le32(0x8129)
  90 #define RTL_EEPROM_SIG_MASK     cpu_to_le32(0xffff)
  91 #define RTL_EEPROM_SIG_ADDR     0x0000
  92
  93 /* write/read MMIO register */
  94 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
  95 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
  96 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
  97 #define RTL_R8(reg)             readb (ioaddr + (reg))
  98 #define RTL_R16(reg)            readw (ioaddr + (reg))
  99 #define RTL_R32(reg)            readl (ioaddr + (reg))
 100
 101 enum mac_version {
 102         RTL_GIGA_MAC_VER_01 = 0,
 103         RTL_GIGA_MAC_VER_02,
 104         RTL_GIGA_MAC_VER_03,
 105         RTL_GIGA_MAC_VER_04,
 106         RTL_GIGA_MAC_VER_05,
 107         RTL_GIGA_MAC_VER_06,
 108         RTL_GIGA_MAC_VER_07,
 109         RTL_GIGA_MAC_VER_08,
 110         RTL_GIGA_MAC_VER_09,
 111         RTL_GIGA_MAC_VER_10,
 112         RTL_GIGA_MAC_VER_11,
 113         RTL_GIGA_MAC_VER_12,
 114         RTL_GIGA_MAC_VER_13,
 115         RTL_GIGA_MAC_VER_14,
 116         RTL_GIGA_MAC_VER_15,
 117         RTL_GIGA_MAC_VER_16,
 118         RTL_GIGA_MAC_VER_17,
 119         RTL_GIGA_MAC_VER_18,
 120         RTL_GIGA_MAC_VER_19,
 121         RTL_GIGA_MAC_VER_20,
 122         RTL_GIGA_MAC_VER_21,
 123         RTL_GIGA_MAC_VER_22,
 124         RTL_GIGA_MAC_VER_23,
 125         RTL_GIGA_MAC_VER_24,
 126         RTL_GIGA_MAC_VER_25,
 127         RTL_GIGA_MAC_VER_26,
 128         RTL_GIGA_MAC_VER_27,
 129         RTL_GIGA_MAC_VER_28,
 130         RTL_GIGA_MAC_VER_29,
 131         RTL_GIGA_MAC_VER_30,
 132         RTL_GIGA_MAC_VER_31,
 133         RTL_GIGA_MAC_VER_32,
 134         RTL_GIGA_MAC_VER_33,
 135         RTL_GIGA_MAC_NONE   = 0xff,
 136 };
 137
 138 enum rtl_tx_desc_version {
 139         RTL_TD_0        = 0,
 140         RTL_TD_1        = 1,
 141 };
 142
 143 #define JUMBO_1K        ETH_DATA_LEN
 144 #define JUMBO_4K        (4*1024 - ETH_HLEN - 2)
 145 #define JUMBO_6K        (6*1024 - ETH_HLEN - 2)
 146 #define JUMBO_7K        (7*1024 - ETH_HLEN - 2)
 147 #define JUMBO_9K        (9*1024 - ETH_HLEN - 2)
 148
 149 #define _R(NAME,TD,FW,SZ,B) {   \
 150         .name = NAME,           \
 151         .txd_version = TD,      \
 152         .fw_name = FW,          \
 153         .jumbo_max = SZ,        \
 154         .jumbo_tx_csum = B      \
 155 }
 156
 157 static const struct {
 158         const char *name;
 159         enum rtl_tx_desc_version txd_version;
 160         const char *fw_name;
 161         u16 jumbo_max;
 162         bool jumbo_tx_csum;
 163 } rtl_chip_infos[] = {
 164         /* PCI devices. */
 165         [RTL_GIGA_MAC_VER_01] =
 166                 _R("RTL8169",           RTL_TD_0, NULL, JUMBO_7K, true),
 167         [RTL_GIGA_MAC_VER_02] =
 168                 _R("RTL8169s",          RTL_TD_0, NULL, JUMBO_7K, true),
 169         [RTL_GIGA_MAC_VER_03] =
 170                 _R("RTL8110s",          RTL_TD_0, NULL, JUMBO_7K, true),
 171         [RTL_GIGA_MAC_VER_04] =
 172                 _R("RTL8169sb/8110sb",  RTL_TD_0, NULL, JUMBO_7K, true),
 173         [RTL_GIGA_MAC_VER_05] =
 174                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 175         [RTL_GIGA_MAC_VER_06] =
 176                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 177         /* PCI-E devices. */
 178         [RTL_GIGA_MAC_VER_07] =
 179                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 180         [RTL_GIGA_MAC_VER_08] =
 181                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 182         [RTL_GIGA_MAC_VER_09] =
 183                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 184         [RTL_GIGA_MAC_VER_10] =
 185                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 186         [RTL_GIGA_MAC_VER_11] =
 187                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 188         [RTL_GIGA_MAC_VER_12] =
 189                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 190         [RTL_GIGA_MAC_VER_13] =
 191                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 192         [RTL_GIGA_MAC_VER_14] =
 193                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 194         [RTL_GIGA_MAC_VER_15] =
 195                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 196         [RTL_GIGA_MAC_VER_16] =
 197                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 198         [RTL_GIGA_MAC_VER_17] =
 199                 _R("RTL8168b/8111b",    RTL_TD_1, NULL, JUMBO_4K, false),
 200         [RTL_GIGA_MAC_VER_18] =
 201                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 202         [RTL_GIGA_MAC_VER_19] =
 203                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 204         [RTL_GIGA_MAC_VER_20] =
 205                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 206         [RTL_GIGA_MAC_VER_21] =
 207                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 208         [RTL_GIGA_MAC_VER_22] =
 209                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 210         [RTL_GIGA_MAC_VER_23] =
 211                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 212         [RTL_GIGA_MAC_VER_24] =
 213                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 214         [RTL_GIGA_MAC_VER_25] =
 215                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_1,
 216                                                         JUMBO_9K, false),
 217         [RTL_GIGA_MAC_VER_26] =
 218                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_2,
 219                                                         JUMBO_9K, false),
 220         [RTL_GIGA_MAC_VER_27] =
 221                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 222         [RTL_GIGA_MAC_VER_28] =
 223                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 224         [RTL_GIGA_MAC_VER_29] =
 225                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 226                                                         JUMBO_1K, true),
 227         [RTL_GIGA_MAC_VER_30] =
 228                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 229                                                         JUMBO_1K, true),
 230         [RTL_GIGA_MAC_VER_31] =
 231                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 232         [RTL_GIGA_MAC_VER_32] =
 233                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_1,
 234                                                         JUMBO_9K, false),
 235         [RTL_GIGA_MAC_VER_33] =
 236                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_2,
 237                                                         JUMBO_9K, false)
 238 };
 239 #undef _R
 240
 241 enum cfg_version {
 242         RTL_CFG_0 = 0x00,
 243         RTL_CFG_1,
 244         RTL_CFG_2
 245 };
 246
 247 static void rtl_hw_start_8169(struct net_device *);
 248 static void rtl_hw_start_8168(struct net_device *);
 249 static void rtl_hw_start_8101(struct net_device *);
 250
 251 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
 252         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 253         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 254         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 255         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 256         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 257         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 258         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4302), 0, 0, RTL_CFG_0 },
 259         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
 260         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 261         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 262                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 263         { 0x0001,                               0x8168,
 264                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 265         {0,},
 266 };
 267
 268 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 269
 270 static int rx_buf_sz = 16383;
 271 static int use_dac;
 272 static struct {
 273         u32 msg_enable;
 274 } debug = { -1 };
 275
 276 enum rtl_registers {
 277         MAC0            = 0,    /* Ethernet hardware address. */
 278         MAC4            = 4,
 279         MAR0            = 8,    /* Multicast filter. */
 280         CounterAddrLow          = 0x10,
 281         CounterAddrHigh         = 0x14,
 282         TxDescStartAddrLow      = 0x20,
 283         TxDescStartAddrHigh     = 0x24,
 284         TxHDescStartAddrLow     = 0x28,
 285         TxHDescStartAddrHigh    = 0x2c,
 286         FLASH           = 0x30,
 287         ERSR            = 0x36,
 288         ChipCmd         = 0x37,
 289         TxPoll          = 0x38,
 290         IntrMask        = 0x3c,
 291         IntrStatus      = 0x3e,
 292         TxConfig        = 0x40,
 293         RxConfig        = 0x44,
 294
 295 #define RTL_RX_CONFIG_MASK              0xff7e1880u
 296
 297         RxMissed        = 0x4c,
 298         Cfg9346         = 0x50,
 299         Config0         = 0x51,
 300         Config1         = 0x52,
 301         Config2         = 0x53,
 302         Config3         = 0x54,
 303         Config4         = 0x55,
 304         Config5         = 0x56,
 305         MultiIntr       = 0x5c,
 306         PHYAR           = 0x60,
 307         PHYstatus       = 0x6c,
 308         RxMaxSize       = 0xda,
 309         CPlusCmd        = 0xe0,
 310         IntrMitigate    = 0xe2,
 311         RxDescAddrLow   = 0xe4,
 312         RxDescAddrHigh  = 0xe8,
 313         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 314
 315 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 316
 317         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 318
 319 #define TxPacketMax     (8064 >> 7)
 320
 321         FuncEvent       = 0xf0,
 322         FuncEventMask   = 0xf4,
 323         FuncPresetState = 0xf8,
 324         FuncForceEvent  = 0xfc,
 325 };
 326
 327 enum rtl8110_registers {
 328         TBICSR                  = 0x64,
 329         TBI_ANAR                = 0x68,
 330         TBI_LPAR                = 0x6a,
 331 };
 332
 333 enum rtl8168_8101_registers {
 334         CSIDR                   = 0x64,
 335         CSIAR                   = 0x68,
 336 #define CSIAR_FLAG                      0x80000000
 337 #define CSIAR_WRITE_CMD                 0x80000000
 338 #define CSIAR_BYTE_ENABLE               0x0f
 339 #define CSIAR_BYTE_ENABLE_SHIFT         12
 340 #define CSIAR_ADDR_MASK                 0x0fff
 341         PMCH                    = 0x6f,
 342         EPHYAR                  = 0x80,
 343 #define EPHYAR_FLAG                     0x80000000
 344 #define EPHYAR_WRITE_CMD                0x80000000
 345 #define EPHYAR_REG_MASK                 0x1f
 346 #define EPHYAR_REG_SHIFT                16
 347 #define EPHYAR_DATA_MASK                0xffff
 348         DLLPR                   = 0xd0,
 349 #define PM_SWITCH                       (1 << 6)
 350         DBG_REG                 = 0xd1,
 351 #define FIX_NAK_1                       (1 << 4)
 352 #define FIX_NAK_2                       (1 << 3)
 353         TWSI                    = 0xd2,
 354         MCU                     = 0xd3,
 355 #define EN_NDP                          (1 << 3)
 356 #define EN_OOB_RESET                    (1 << 2)
 357         EFUSEAR                 = 0xdc,
 358 #define EFUSEAR_FLAG                    0x80000000
 359 #define EFUSEAR_WRITE_CMD               0x80000000
 360 #define EFUSEAR_READ_CMD                0x00000000
 361 #define EFUSEAR_REG_MASK                0x03ff
 362 #define EFUSEAR_REG_SHIFT               8
 363 #define EFUSEAR_DATA_MASK               0xff
 364 };
 365
 366 enum rtl8168_registers {
 367         ERIDR                   = 0x70,
 368         ERIAR                   = 0x74,
 369 #define ERIAR_FLAG                      0x80000000
 370 #define ERIAR_WRITE_CMD                 0x80000000
 371 #define ERIAR_READ_CMD                  0x00000000
 372 #define ERIAR_ADDR_BYTE_ALIGN           4
 373 #define ERIAR_EXGMAC                    0
 374 #define ERIAR_MSIX                      1
 375 #define ERIAR_ASF                       2
 376 #define ERIAR_TYPE_SHIFT                16
 377 #define ERIAR_BYTEEN                    0x0f
 378 #define ERIAR_BYTEEN_SHIFT              12
 379         EPHY_RXER_NUM           = 0x7c,
 380         OCPDR                   = 0xb0, /* OCP GPHY access */
 381 #define OCPDR_WRITE_CMD                 0x80000000
 382 #define OCPDR_READ_CMD                  0x00000000
 383 #define OCPDR_REG_MASK                  0x7f
 384 #define OCPDR_GPHY_REG_SHIFT            16
 385 #define OCPDR_DATA_MASK                 0xffff
 386         OCPAR                   = 0xb4,
 387 #define OCPAR_FLAG                      0x80000000
 388 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 389 #define OCPAR_GPHY_READ_CMD             0x0000f060
 390         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 391         MISC                    = 0xf0, /* 8168e only. */
 392 #define TXPLA_RST                       (1 << 29)
 393 };
 394
 395 enum rtl_register_content {
 396         /* InterruptStatusBits */
 397         SYSErr          = 0x8000,
 398         PCSTimeout      = 0x4000,
 399         SWInt           = 0x0100,
 400         TxDescUnavail   = 0x0080,
 401         RxFIFOOver      = 0x0040,
 402         LinkChg         = 0x0020,
 403         RxOverflow      = 0x0010,
 404         TxErr           = 0x0008,
 405         TxOK            = 0x0004,
 406         RxErr           = 0x0002,
 407         RxOK            = 0x0001,
 408
 409         /* RxStatusDesc */
 410         RxBOVF  = (1 << 24),
 411         RxFOVF  = (1 << 23),
 412         RxRWT   = (1 << 22),
 413         RxRES   = (1 << 21),
 414         RxRUNT  = (1 << 20),
 415         RxCRC   = (1 << 19),
 416
 417         /* ChipCmdBits */
 418         CmdReset        = 0x10,
 419         CmdRxEnb        = 0x08,
 420         CmdTxEnb        = 0x04,
 421         RxBufEmpty      = 0x01,
 422
 423         /* TXPoll register p.5 */
 424         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 425         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 426         FSWInt          = 0x01,         /* Forced software interrupt */
 427
 428         /* Cfg9346Bits */
 429         Cfg9346_Lock    = 0x00,
 430         Cfg9346_Unlock  = 0xc0,
 431
 432         /* rx_mode_bits */
 433         AcceptErr       = 0x20,
 434         AcceptRunt      = 0x10,
 435         AcceptBroadcast = 0x08,
 436         AcceptMulticast = 0x04,
 437         AcceptMyPhys    = 0x02,
 438         AcceptAllPhys   = 0x01,
 439
 440         /* RxConfigBits */
 441         RxCfgFIFOShift  = 13,
 442         RxCfgDMAShift   =  8,
 443
 444         /* TxConfigBits */
 445         TxInterFrameGapShift = 24,
 446         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 447
 448         /* Config1 register p.24 */
 449         LEDS1           = (1 << 7),
 450         LEDS0           = (1 << 6),
 451         Speed_down      = (1 << 4),
 452         MEMMAP          = (1 << 3),
 453         IOMAP           = (1 << 2),
 454         VPD             = (1 << 1),
 455         PMEnable        = (1 << 0),     /* Power Management Enable */
 456
 457         /* Config2 register p. 25 */
 458         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 459         PCI_Clock_66MHz = 0x01,
 460         PCI_Clock_33MHz = 0x00,
 461
 462         /* Config3 register p.25 */
 463         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 464         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 465         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 466         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 467
 468         /* Config4 register */
 469         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 470
 471         /* Config5 register p.27 */
 472         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 473         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 474         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 475         Spi_en          = (1 << 3),
 476         LanWake         = (1 << 1),     /* LanWake enable/disable */
 477         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 478
 479         /* TBICSR p.28 */
 480         TBIReset        = 0x80000000,
 481         TBILoopback     = 0x40000000,
 482         TBINwEnable     = 0x20000000,
 483         TBINwRestart    = 0x10000000,
 484         TBILinkOk       = 0x02000000,
 485         TBINwComplete   = 0x01000000,
 486
 487         /* CPlusCmd p.31 */
 488         EnableBist      = (1 << 15),    // 8168 8101
 489         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 490         Normal_mode     = (1 << 13),    // unused
 491         Force_half_dup  = (1 << 12),    // 8168 8101
 492         Force_rxflow_en = (1 << 11),    // 8168 8101
 493         Force_txflow_en = (1 << 10),    // 8168 8101
 494         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 495         ASF             = (1 << 8),     // 8168 8101
 496         PktCntrDisable  = (1 << 7),     // 8168 8101
 497         Mac_dbgo_sel    = 0x001c,       // 8168
 498         RxVlan          = (1 << 6),
 499         RxChkSum        = (1 << 5),
 500         PCIDAC          = (1 << 4),
 501         PCIMulRW        = (1 << 3),
 502         INTT_0          = 0x0000,       // 8168
 503         INTT_1          = 0x0001,       // 8168
 504         INTT_2          = 0x0002,       // 8168
 505         INTT_3          = 0x0003,       // 8168
 506
 507         /* rtl8169_PHYstatus */
 508         TBI_Enable      = 0x80,
 509         TxFlowCtrl      = 0x40,
 510         RxFlowCtrl      = 0x20,
 511         _1000bpsF       = 0x10,
 512         _100bps         = 0x08,
 513         _10bps          = 0x04,
 514         LinkStatus      = 0x02,
 515         FullDup         = 0x01,
 516
 517         /* _TBICSRBit */
 518         TBILinkOK       = 0x02000000,
 519
 520         /* DumpCounterCommand */
 521         CounterDump     = 0x8,
 522 };
 523
 524 enum rtl_desc_bit {
 525         /* First doubleword. */
 526         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 527         RingEnd         = (1 << 30), /* End of descriptor ring */
 528         FirstFrag       = (1 << 29), /* First segment of a packet */
 529         LastFrag        = (1 << 28), /* Final segment of a packet */
 530 };
 531
 532 /* Generic case. */
 533 enum rtl_tx_desc_bit {
 534         /* First doubleword. */
 535         TD_LSO          = (1 << 27),            /* Large Send Offload */
 536 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 537
 538         /* Second doubleword. */
 539         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 540 };
 541
 542 /* 8169, 8168b and 810x except 8102e. */
 543 enum rtl_tx_desc_bit_0 {
 544         /* First doubleword. */
 545 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 546         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 547         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 548         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 549 };
 550
 551 /* 8102e, 8168c and beyond. */
 552 enum rtl_tx_desc_bit_1 {
 553         /* Second doubleword. */
 554 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 555         TD1_IP_CS       = (1 << 29),            /* Calculate IP checksum */
 556         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 557         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 558 };
 559
 560 static const struct rtl_tx_desc_info {
 561         struct {
 562                 u32 udp;
 563                 u32 tcp;
 564         } checksum;
 565         u16 mss_shift;
 566         u16 opts_offset;
 567 } tx_desc_info [] = {
 568         [RTL_TD_0] = {
 569                 .checksum = {
 570                         .udp    = TD0_IP_CS | TD0_UDP_CS,
 571                         .tcp    = TD0_IP_CS | TD0_TCP_CS
 572                 },
 573                 .mss_shift      = TD0_MSS_SHIFT,
 574                 .opts_offset    = 0
 575         },
 576         [RTL_TD_1] = {
 577                 .checksum = {
 578                         .udp    = TD1_IP_CS | TD1_UDP_CS,
 579                         .tcp    = TD1_IP_CS | TD1_TCP_CS
 580                 },
 581                 .mss_shift      = TD1_MSS_SHIFT,
 582                 .opts_offset    = 1
 583         }
 584 };
 585
 586 enum rtl_rx_desc_bit {
 587         /* Rx private */
 588         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 589         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
 590
 591 #define RxProtoUDP      (PID1)
 592 #define RxProtoTCP      (PID0)
 593 #define RxProtoIP       (PID1 | PID0)
 594 #define RxProtoMask     RxProtoIP
 595
 596         IPFail          = (1 << 16), /* IP checksum failed */
 597         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 598         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 599         RxVlanTag       = (1 << 16), /* VLAN tag available */
 600 };
 601
 602 #define RsvdMask        0x3fffc000
 603
 604 struct TxDesc {
 605         __le32 opts1;
 606         __le32 opts2;
 607         __le64 addr;
 608 };
 609
 610 struct RxDesc {
 611         __le32 opts1;
 612         __le32 opts2;
 613         __le64 addr;
 614 };
 615
 616 struct ring_info {
 617         struct sk_buff  *skb;
 618         u32             len;
 619         u8              __pad[sizeof(void *) - sizeof(u32)];
 620 };
 621
 622 enum features {
 623         RTL_FEATURE_WOL         = (1 << 0),
 624         RTL_FEATURE_MSI         = (1 << 1),
 625         RTL_FEATURE_GMII        = (1 << 2),
 626 };
 627
 628 struct rtl8169_counters {
 629         __le64  tx_packets;
 630         __le64  rx_packets;
 631         __le64  tx_errors;
 632         __le32  rx_errors;
 633         __le16  rx_missed;
 634         __le16  align_errors;
 635         __le32  tx_one_collision;
 636         __le32  tx_multi_collision;
 637         __le64  rx_unicast;
 638         __le64  rx_broadcast;
 639         __le32  rx_multicast;
 640         __le16  tx_aborted;
 641         __le16  tx_underun;
 642 };
 643
 644 struct rtl8169_private {
 645         void __iomem *mmio_addr;        /* memory map physical address */
 646         struct pci_dev *pci_dev;
 647         struct net_device *dev;
 648         struct napi_struct napi;
 649         spinlock_t lock;
 650         u32 msg_enable;
 651         u16 txd_version;
 652         u16 mac_version;
 653         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 654         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 655         u32 dirty_rx;
 656         u32 dirty_tx;
 657         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 658         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 659         dma_addr_t TxPhyAddr;
 660         dma_addr_t RxPhyAddr;
 661         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 662         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 663         struct timer_list timer;
 664         u16 cp_cmd;
 665         u16 intr_event;
 666         u16 napi_event;
 667         u16 intr_mask;
 668
 669         struct mdio_ops {
 670                 void (*write)(void __iomem *, int, int);
 671                 int (*read)(void __iomem *, int);
 672         } mdio_ops;
 673
 674         struct pll_power_ops {
 675                 void (*down)(struct rtl8169_private *);
 676                 void (*up)(struct rtl8169_private *);
 677         } pll_power_ops;
 678
 679         struct jumbo_ops {
 680                 void (*enable)(struct rtl8169_private *);
 681                 void (*disable)(struct rtl8169_private *);
 682         } jumbo_ops;
 683
 684         int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
 685         int (*get_settings)(struct net_device *, struct ethtool_cmd *);
 686         void (*phy_reset_enable)(struct rtl8169_private *tp);
 687         void (*hw_start)(struct net_device *);
 688         unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
 689         unsigned int (*link_ok)(void __iomem *);
 690         int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
 691         int pcie_cap;
 692         struct delayed_work task;
 693         unsigned features;
 694
 695         struct mii_if_info mii;
 696         struct rtl8169_counters counters;
 697         u32 saved_wolopts;
 698         u32 opts1_mask;
 699
 700         const struct firmware *fw;
 701 #define RTL_FIRMWARE_UNKNOWN    ERR_PTR(-EAGAIN);
 702 };
 703
 704 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 705 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 706 module_param(use_dac, int, 0);
 707 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 708 module_param_named(debug, debug.msg_enable, int, 0);
 709 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 710 MODULE_LICENSE("GPL");
 711 MODULE_VERSION(RTL8169_VERSION);
 712 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 713 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 714 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 715 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 716 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 717
 718 static int rtl8169_open(struct net_device *dev);
 719 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
 720                                       struct net_device *dev);
 721 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
 722 static int rtl8169_init_ring(struct net_device *dev);
 723 static void rtl_hw_start(struct net_device *dev);
 724 static int rtl8169_close(struct net_device *dev);
 725 static void rtl_set_rx_mode(struct net_device *dev);
 726 static void rtl8169_tx_timeout(struct net_device *dev);
 727 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
 728 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
 729                                 void __iomem *, u32 budget);
 730 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
 731 static void rtl8169_down(struct net_device *dev);
 732 static void rtl8169_rx_clear(struct rtl8169_private *tp);
 733 static int rtl8169_poll(struct napi_struct *napi, int budget);
 734
 735 static const unsigned int rtl8169_rx_config =
 736         (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
 737
 738 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
 739 {
 740         struct net_device *dev = pci_get_drvdata(pdev);
 741         struct rtl8169_private *tp = netdev_priv(dev);
 742         int cap = tp->pcie_cap;
 743
 744         if (cap) {
 745                 u16 ctl;
 746
 747                 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
 748                 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
 749                 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
 750         }
 751 }
 752
 753 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
 754 {
 755         void __iomem *ioaddr = tp->mmio_addr;
 756         int i;
 757
 758         RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 759         for (i = 0; i < 20; i++) {
 760                 udelay(100);
 761                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
 762                         break;
 763         }
 764         return RTL_R32(OCPDR);
 765 }
 766
 767 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
 768 {
 769         void __iomem *ioaddr = tp->mmio_addr;
 770         int i;
 771
 772         RTL_W32(OCPDR, data);
 773         RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 774         for (i = 0; i < 20; i++) {
 775                 udelay(100);
 776                 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
 777                         break;
 778         }
 779 }
 780
 781 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
 782 {
 783         void __iomem *ioaddr = tp->mmio_addr;
 784         int i;
 785
 786         RTL_W8(ERIDR, cmd);
 787         RTL_W32(ERIAR, 0x800010e8);
 788         msleep(2);
 789         for (i = 0; i < 5; i++) {
 790                 udelay(100);
 791                 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
 792                         break;
 793         }
 794
 795         ocp_write(tp, 0x1, 0x30, 0x00000001);
 796 }
 797
 798 #define OOB_CMD_RESET           0x00
 799 #define OOB_CMD_DRIVER_START    0x05
 800 #define OOB_CMD_DRIVER_STOP     0x06
 801
 802 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
 803 {
 804         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
 805 }
 806
 807 static void rtl8168_driver_start(struct rtl8169_private *tp)
 808 {
 809         u16 reg;
 810         int i;
 811
 812         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
 813
 814         reg = rtl8168_get_ocp_reg(tp);
 815
 816         for (i = 0; i < 10; i++) {
 817                 msleep(10);
 818                 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
 819                         break;
 820         }
 821 }
 822
 823 static void rtl8168_driver_stop(struct rtl8169_private *tp)
 824 {
 825         u16 reg;
 826         int i;
 827
 828         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
 829
 830         reg = rtl8168_get_ocp_reg(tp);
 831
 832         for (i = 0; i < 10; i++) {
 833                 msleep(10);
 834                 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
 835                         break;
 836         }
 837 }
 838
 839 static int r8168dp_check_dash(struct rtl8169_private *tp)
 840 {
 841         u16 reg = rtl8168_get_ocp_reg(tp);
 842
 843         return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
 844 }
 845
 846 static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 847 {
 848         int i;
 849
 850         RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
 851
 852         for (i = 20; i > 0; i--) {
 853                 /*
 854                  * Check if the RTL8169 has completed writing to the specified
 855                  * MII register.
 856                  */
 857                 if (!(RTL_R32(PHYAR) & 0x80000000))
 858                         break;
 859                 udelay(25);
 860         }
 861         /*
 862          * According to hardware specs a 20us delay is required after write
 863          * complete indication, but before sending next command.
 864          */
 865         udelay(20);
 866 }
 867
 868 static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
 869 {
 870         int i, value = -1;
 871
 872         RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
 873
 874         for (i = 20; i > 0; i--) {
 875                 /*
 876                  * Check if the RTL8169 has completed retrieving data from
 877                  * the specified MII register.
 878                  */
 879                 if (RTL_R32(PHYAR) & 0x80000000) {
 880                         value = RTL_R32(PHYAR) & 0xffff;
 881                         break;
 882                 }
 883                 udelay(25);
 884         }
 885         /*
 886          * According to hardware specs a 20us delay is required after read
 887          * complete indication, but before sending next command.
 888          */
 889         udelay(20);
 890
 891         return value;
 892 }
 893
 894 static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
 895 {
 896         int i;
 897
 898         RTL_W32(OCPDR, data |
 899                 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
 900         RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
 901         RTL_W32(EPHY_RXER_NUM, 0);
 902
 903         for (i = 0; i < 100; i++) {
 904                 mdelay(1);
 905                 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
 906                         break;
 907         }
 908 }
 909
 910 static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 911 {
 912         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
 913                 (value & OCPDR_DATA_MASK));
 914 }
 915
 916 static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
 917 {
 918         int i;
 919
 920         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
 921
 922         mdelay(1);
 923         RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
 924         RTL_W32(EPHY_RXER_NUM, 0);
 925
 926         for (i = 0; i < 100; i++) {
 927                 mdelay(1);
 928                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
 929                         break;
 930         }
 931
 932         return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
 933 }
 934
 935 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
 936
 937 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
 938 {
 939         RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
 940 }
 941
 942 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
 943 {
 944         RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
 945 }
 946
 947 static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 948 {
 949         r8168dp_2_mdio_start(ioaddr);
 950
 951         r8169_mdio_write(ioaddr, reg_addr, value);
 952
 953         r8168dp_2_mdio_stop(ioaddr);
 954 }
 955
 956 static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
 957 {
 958         int value;
 959
 960         r8168dp_2_mdio_start(ioaddr);
 961
 962         value = r8169_mdio_read(ioaddr, reg_addr);
 963
 964         r8168dp_2_mdio_stop(ioaddr);
 965
 966         return value;
 967 }
 968
 969 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
 970 {
 971         tp->mdio_ops.write(tp->mmio_addr, location, val);
 972 }
 973
 974 static int rtl_readphy(struct rtl8169_private *tp, int location)
 975 {
 976         return tp->mdio_ops.read(tp->mmio_addr, location);
 977 }
 978
 979 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
 980 {
 981         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
 982 }
 983
 984 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
 985 {
 986         int val;
 987
 988         val = rtl_readphy(tp, reg_addr);
 989         rtl_writephy(tp, reg_addr, (val | p) & ~m);
 990 }
 991
 992 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
 993                            int val)
 994 {
 995         struct rtl8169_private *tp = netdev_priv(dev);
 996
 997         rtl_writephy(tp, location, val);
 998 }
 999
1000 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1001 {
1002         struct rtl8169_private *tp = netdev_priv(dev);
1003
1004         return rtl_readphy(tp, location);
1005 }
1006
1007 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
1008 {
1009         unsigned int i;
1010
1011         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1012                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1013
1014         for (i = 0; i < 100; i++) {
1015                 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
1016                         break;
1017                 udelay(10);
1018         }
1019 }
1020
1021 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
1022 {
1023         u16 value = 0xffff;
1024         unsigned int i;
1025
1026         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1027
1028         for (i = 0; i < 100; i++) {
1029                 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
1030                         value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
1031                         break;
1032                 }
1033                 udelay(10);
1034         }
1035
1036         return value;
1037 }
1038
1039 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
1040 {
1041         unsigned int i;
1042
1043         RTL_W32(CSIDR, value);
1044         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
1045                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1046
1047         for (i = 0; i < 100; i++) {
1048                 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
1049                         break;
1050                 udelay(10);
1051         }
1052 }
1053
1054 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
1055 {
1056         u32 value = ~0x00;
1057         unsigned int i;
1058
1059         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
1060                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1061
1062         for (i = 0; i < 100; i++) {
1063                 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
1064                         value = RTL_R32(CSIDR);
1065                         break;
1066                 }
1067                 udelay(10);
1068         }
1069
1070         return value;
1071 }
1072
1073 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
1074 {
1075         u8 value = 0xff;
1076         unsigned int i;
1077
1078         RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1079
1080         for (i = 0; i < 300; i++) {
1081                 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
1082                         value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
1083                         break;
1084                 }
1085                 udelay(100);
1086         }
1087
1088         return value;
1089 }
1090
1091 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1092 {
1093         void __iomem *ioaddr = tp->mmio_addr;
1094
1095         RTL_W16(IntrMask, 0x0000);
1096         RTL_W16(IntrStatus, tp->intr_event);
1097         RTL_R8(ChipCmd);
1098 }
1099
1100 static void rtl8169_asic_down(struct rtl8169_private *tp)
1101 {
1102         void __iomem *ioaddr = tp->mmio_addr;
1103
1104         RTL_W8(ChipCmd, 0x00);
1105         rtl8169_irq_mask_and_ack(tp);
1106         RTL_R16(CPlusCmd);
1107 }
1108
1109 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1110 {
1111         void __iomem *ioaddr = tp->mmio_addr;
1112
1113         return RTL_R32(TBICSR) & TBIReset;
1114 }
1115
1116 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1117 {
1118         return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1119 }
1120
1121 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1122 {
1123         return RTL_R32(TBICSR) & TBILinkOk;
1124 }
1125
1126 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1127 {
1128         return RTL_R8(PHYstatus) & LinkStatus;
1129 }
1130
1131 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1132 {
1133         void __iomem *ioaddr = tp->mmio_addr;
1134
1135         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1136 }
1137
1138 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1139 {
1140         unsigned int val;
1141
1142         val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1143         rtl_writephy(tp, MII_BMCR, val & 0xffff);
1144 }
1145
1146 static void __rtl8169_check_link_status(struct net_device *dev,
1147                                         struct rtl8169_private *tp,
1148                                         void __iomem *ioaddr, bool pm)
1149 {
1150         unsigned long flags;
1151
1152         spin_lock_irqsave(&tp->lock, flags);
1153         if (tp->link_ok(ioaddr)) {
1154                 /* This is to cancel a scheduled suspend if there's one. */
1155                 if (pm)
1156                         pm_request_resume(&tp->pci_dev->dev);
1157                 netif_carrier_on(dev);
1158                 if (net_ratelimit())
1159                         netif_info(tp, ifup, dev, "link up\n");
1160         } else {
1161                 netif_carrier_off(dev);
1162                 netif_info(tp, ifdown, dev, "link down\n");
1163                 if (pm)
1164                         pm_schedule_suspend(&tp->pci_dev->dev, 5000);
1165         }
1166         spin_unlock_irqrestore(&tp->lock, flags);
1167 }
1168
1169 static void rtl8169_check_link_status(struct net_device *dev,
1170                                       struct rtl8169_private *tp,
1171                                       void __iomem *ioaddr)
1172 {
1173         __rtl8169_check_link_status(dev, tp, ioaddr, false);
1174 }
1175
1176 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1177
1178 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1179 {
1180         void __iomem *ioaddr = tp->mmio_addr;
1181         u8 options;
1182         u32 wolopts = 0;
1183
1184         options = RTL_R8(Config1);
1185         if (!(options & PMEnable))
1186                 return 0;
1187
1188         options = RTL_R8(Config3);
1189         if (options & LinkUp)
1190                 wolopts |= WAKE_PHY;
1191         if (options & MagicPacket)
1192                 wolopts |= WAKE_MAGIC;
1193
1194         options = RTL_R8(Config5);
1195         if (options & UWF)
1196                 wolopts |= WAKE_UCAST;
1197         if (options & BWF)
1198                 wolopts |= WAKE_BCAST;
1199         if (options & MWF)
1200                 wolopts |= WAKE_MCAST;
1201
1202         return wolopts;
1203 }
1204
1205 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1206 {
1207         struct rtl8169_private *tp = netdev_priv(dev);
1208
1209         spin_lock_irq(&tp->lock);
1210
1211         wol->supported = WAKE_ANY;
1212         wol->wolopts = __rtl8169_get_wol(tp);
1213
1214         spin_unlock_irq(&tp->lock);
1215 }
1216
1217 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1218 {
1219         void __iomem *ioaddr = tp->mmio_addr;
1220         unsigned int i;
1221         static const struct {
1222                 u32 opt;
1223                 u16 reg;
1224                 u8  mask;
1225         } cfg[] = {
1226                 { WAKE_ANY,   Config1, PMEnable },
1227                 { WAKE_PHY,   Config3, LinkUp },
1228                 { WAKE_MAGIC, Config3, MagicPacket },
1229                 { WAKE_UCAST, Config5, UWF },
1230                 { WAKE_BCAST, Config5, BWF },
1231                 { WAKE_MCAST, Config5, MWF },
1232                 { WAKE_ANY,   Config5, LanWake }
1233         };
1234
1235         RTL_W8(Cfg9346, Cfg9346_Unlock);
1236
1237         for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1238                 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1239                 if (wolopts & cfg[i].opt)
1240                         options |= cfg[i].mask;
1241                 RTL_W8(cfg[i].reg, options);
1242         }
1243
1244         RTL_W8(Cfg9346, Cfg9346_Lock);
1245 }
1246
1247 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1248 {
1249         struct rtl8169_private *tp = netdev_priv(dev);
1250
1251         spin_lock_irq(&tp->lock);
1252
1253         if (wol->wolopts)
1254                 tp->features |= RTL_FEATURE_WOL;
1255         else
1256                 tp->features &= ~RTL_FEATURE_WOL;
1257         __rtl8169_set_wol(tp, wol->wolopts);
1258         spin_unlock_irq(&tp->lock);
1259
1260         device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1261
1262         return 0;
1263 }
1264
1265 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1266 {
1267         return rtl_chip_infos[tp->mac_version].fw_name;
1268 }
1269
1270 static void rtl8169_get_drvinfo(struct net_device *dev,
1271                                 struct ethtool_drvinfo *info)
1272 {
1273         struct rtl8169_private *tp = netdev_priv(dev);
1274
1275         strcpy(info->driver, MODULENAME);
1276         strcpy(info->version, RTL8169_VERSION);
1277         strcpy(info->bus_info, pci_name(tp->pci_dev));
1278         strncpy(info->fw_version, IS_ERR_OR_NULL(tp->fw) ? "N/A" :
1279                 rtl_lookup_firmware_name(tp), sizeof(info->fw_version) - 1);
1280 }
1281
1282 static int rtl8169_get_regs_len(struct net_device *dev)
1283 {
1284         return R8169_REGS_SIZE;
1285 }
1286
1287 static int rtl8169_set_speed_tbi(struct net_device *dev,
1288                                  u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1289 {
1290         struct rtl8169_private *tp = netdev_priv(dev);
1291         void __iomem *ioaddr = tp->mmio_addr;
1292         int ret = 0;
1293         u32 reg;
1294
1295         reg = RTL_R32(TBICSR);
1296         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1297             (duplex == DUPLEX_FULL)) {
1298                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1299         } else if (autoneg == AUTONEG_ENABLE)
1300                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1301         else {
1302                 netif_warn(tp, link, dev,
1303                            "incorrect speed setting refused in TBI mode\n");
1304                 ret = -EOPNOTSUPP;
1305         }
1306
1307         return ret;
1308 }
1309
1310 static int rtl8169_set_speed_xmii(struct net_device *dev,
1311                                   u8 autoneg, u16 speed, u8 duplex, u32 adv)
1312 {
1313         struct rtl8169_private *tp = netdev_priv(dev);
1314         int giga_ctrl, bmcr;
1315         int rc = -EINVAL;
1316
1317         rtl_writephy(tp, 0x1f, 0x0000);
1318
1319         if (autoneg == AUTONEG_ENABLE) {
1320                 int auto_nego;
1321
1322                 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1323                 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1324                                 ADVERTISE_100HALF | ADVERTISE_100FULL);
1325
1326                 if (adv & ADVERTISED_10baseT_Half)
1327                         auto_nego |= ADVERTISE_10HALF;
1328                 if (adv & ADVERTISED_10baseT_Full)
1329                         auto_nego |= ADVERTISE_10FULL;
1330                 if (adv & ADVERTISED_100baseT_Half)
1331                         auto_nego |= ADVERTISE_100HALF;
1332                 if (adv & ADVERTISED_100baseT_Full)
1333                         auto_nego |= ADVERTISE_100FULL;
1334
1335                 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1336
1337                 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1338                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1339
1340                 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1341                 if (tp->mii.supports_gmii) {
1342                         if (adv & ADVERTISED_1000baseT_Half)
1343                                 giga_ctrl |= ADVERTISE_1000HALF;
1344                         if (adv & ADVERTISED_1000baseT_Full)
1345                                 giga_ctrl |= ADVERTISE_1000FULL;
1346                 } else if (adv & (ADVERTISED_1000baseT_Half |
1347                                   ADVERTISED_1000baseT_Full)) {
1348                         netif_info(tp, link, dev,
1349                                    "PHY does not support 1000Mbps\n");
1350                         goto out;
1351                 }
1352
1353                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1354
1355                 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1356                 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1357         } else {
1358                 giga_ctrl = 0;
1359
1360                 if (speed == SPEED_10)
1361                         bmcr = 0;
1362                 else if (speed == SPEED_100)
1363                         bmcr = BMCR_SPEED100;
1364                 else
1365                         goto out;
1366
1367                 if (duplex == DUPLEX_FULL)
1368                         bmcr |= BMCR_FULLDPLX;
1369         }
1370
1371         rtl_writephy(tp, MII_BMCR, bmcr);
1372
1373         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1374             tp->mac_version == RTL_GIGA_MAC_VER_03) {
1375                 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1376                         rtl_writephy(tp, 0x17, 0x2138);
1377                         rtl_writephy(tp, 0x0e, 0x0260);
1378                 } else {
1379                         rtl_writephy(tp, 0x17, 0x2108);
1380                         rtl_writephy(tp, 0x0e, 0x0000);
1381                 }
1382         }
1383
1384         rc = 0;
1385 out:
1386         return rc;
1387 }
1388
1389 static int rtl8169_set_speed(struct net_device *dev,
1390                              u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1391 {
1392         struct rtl8169_private *tp = netdev_priv(dev);
1393         int ret;
1394
1395         ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1396         if (ret < 0)
1397                 goto out;
1398
1399         if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1400             (advertising & ADVERTISED_1000baseT_Full)) {
1401                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1402         }
1403 out:
1404         return ret;
1405 }
1406
1407 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1408 {
1409         struct rtl8169_private *tp = netdev_priv(dev);
1410         unsigned long flags;
1411         int ret;
1412
1413         del_timer_sync(&tp->timer);
1414
1415         spin_lock_irqsave(&tp->lock, flags);
1416         ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
1417                                 cmd->duplex, cmd->advertising);
1418         spin_unlock_irqrestore(&tp->lock, flags);
1419
1420         return ret;
1421 }
1422
1423 static u32 rtl8169_fix_features(struct net_device *dev, u32 features)
1424 {
1425         struct rtl8169_private *tp = netdev_priv(dev);
1426
1427         if (dev->mtu > TD_MSS_MAX)
1428                 features &= ~NETIF_F_ALL_TSO;
1429
1430         if (dev->mtu > JUMBO_1K &&
1431             !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1432                 features &= ~NETIF_F_IP_CSUM;
1433
1434         return features;
1435 }
1436
1437 static int rtl8169_set_features(struct net_device *dev, u32 features)
1438 {
1439         struct rtl8169_private *tp = netdev_priv(dev);
1440         void __iomem *ioaddr = tp->mmio_addr;
1441         unsigned long flags;
1442
1443         spin_lock_irqsave(&tp->lock, flags);
1444
1445         if (features & NETIF_F_RXCSUM)
1446                 tp->cp_cmd |= RxChkSum;
1447         else
1448                 tp->cp_cmd &= ~RxChkSum;
1449
1450         if (dev->features & NETIF_F_HW_VLAN_RX)
1451                 tp->cp_cmd |= RxVlan;
1452         else
1453                 tp->cp_cmd &= ~RxVlan;
1454
1455         RTL_W16(CPlusCmd, tp->cp_cmd);
1456         RTL_R16(CPlusCmd);
1457
1458         spin_unlock_irqrestore(&tp->lock, flags);
1459
1460         return 0;
1461 }
1462
1463 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1464                                       struct sk_buff *skb)
1465 {
1466         return (vlan_tx_tag_present(skb)) ?
1467                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1468 }
1469
1470 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1471 {
1472         u32 opts2 = le32_to_cpu(desc->opts2);
1473
1474         if (opts2 & RxVlanTag)
1475                 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
1476
1477         desc->opts2 = 0;
1478 }
1479
1480 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1481 {
1482         struct rtl8169_private *tp = netdev_priv(dev);
1483         void __iomem *ioaddr = tp->mmio_addr;
1484         u32 status;
1485
1486         cmd->supported =
1487                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1488         cmd->port = PORT_FIBRE;
1489         cmd->transceiver = XCVR_INTERNAL;
1490
1491         status = RTL_R32(TBICSR);
1492         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
1493         cmd->autoneg = !!(status & TBINwEnable);
1494
1495         ethtool_cmd_speed_set(cmd, SPEED_1000);
1496         cmd->duplex = DUPLEX_FULL; /* Always set */
1497
1498         return 0;
1499 }
1500
1501 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1502 {
1503         struct rtl8169_private *tp = netdev_priv(dev);
1504
1505         return mii_ethtool_gset(&tp->mii, cmd);
1506 }
1507
1508 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1509 {
1510         struct rtl8169_private *tp = netdev_priv(dev);
1511         unsigned long flags;
1512         int rc;
1513
1514         spin_lock_irqsave(&tp->lock, flags);
1515
1516         rc = tp->get_settings(dev, cmd);
1517
1518         spin_unlock_irqrestore(&tp->lock, flags);
1519         return rc;
1520 }
1521
1522 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1523                              void *p)
1524 {
1525         struct rtl8169_private *tp = netdev_priv(dev);
1526         unsigned long flags;
1527
1528         if (regs->len > R8169_REGS_SIZE)
1529                 regs->len = R8169_REGS_SIZE;
1530
1531         spin_lock_irqsave(&tp->lock, flags);
1532         memcpy_fromio(p, tp->mmio_addr, regs->len);
1533         spin_unlock_irqrestore(&tp->lock, flags);
1534 }
1535
1536 static u32 rtl8169_get_msglevel(struct net_device *dev)
1537 {
1538         struct rtl8169_private *tp = netdev_priv(dev);
1539
1540         return tp->msg_enable;
1541 }
1542
1543 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1544 {
1545         struct rtl8169_private *tp = netdev_priv(dev);
1546
1547         tp->msg_enable = value;
1548 }
1549
1550 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1551         "tx_packets",
1552         "rx_packets",
1553         "tx_errors",
1554         "rx_errors",
1555         "rx_missed",
1556         "align_errors",
1557         "tx_single_collisions",
1558         "tx_multi_collisions",
1559         "unicast",
1560         "broadcast",
1561         "multicast",
1562         "tx_aborted",
1563         "tx_underrun",
1564 };
1565
1566 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1567 {
1568         switch (sset) {
1569         case ETH_SS_STATS:
1570                 return ARRAY_SIZE(rtl8169_gstrings);
1571         default:
1572                 return -EOPNOTSUPP;
1573         }
1574 }
1575
1576 static void rtl8169_update_counters(struct net_device *dev)
1577 {
1578         struct rtl8169_private *tp = netdev_priv(dev);
1579         void __iomem *ioaddr = tp->mmio_addr;
1580         struct device *d = &tp->pci_dev->dev;
1581         struct rtl8169_counters *counters;
1582         dma_addr_t paddr;
1583         u32 cmd;
1584         int wait = 1000;
1585
1586         /*
1587          * Some chips are unable to dump tally counters when the receiver
1588          * is disabled.
1589          */
1590         if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1591                 return;
1592
1593         counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1594         if (!counters)
1595                 return;
1596
1597         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1598         cmd = (u64)paddr & DMA_BIT_MASK(32);
1599         RTL_W32(CounterAddrLow, cmd);
1600         RTL_W32(CounterAddrLow, cmd | CounterDump);
1601
1602         while (wait--) {
1603                 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1604                         memcpy(&tp->counters, counters, sizeof(*counters));
1605                         break;
1606                 }
1607                 udelay(10);
1608         }
1609
1610         RTL_W32(CounterAddrLow, 0);
1611         RTL_W32(CounterAddrHigh, 0);
1612
1613         dma_free_coherent(d, sizeof(*counters), counters, paddr);
1614 }
1615
1616 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1617                                       struct ethtool_stats *stats, u64 *data)
1618 {
1619         struct rtl8169_private *tp = netdev_priv(dev);
1620
1621         ASSERT_RTNL();
1622
1623         rtl8169_update_counters(dev);
1624
1625         data[0] = le64_to_cpu(tp->counters.tx_packets);
1626         data[1] = le64_to_cpu(tp->counters.rx_packets);
1627         data[2] = le64_to_cpu(tp->counters.tx_errors);
1628         data[3] = le32_to_cpu(tp->counters.rx_errors);
1629         data[4] = le16_to_cpu(tp->counters.rx_missed);
1630         data[5] = le16_to_cpu(tp->counters.align_errors);
1631         data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1632         data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1633         data[8] = le64_to_cpu(tp->counters.rx_unicast);
1634         data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1635         data[10] = le32_to_cpu(tp->counters.rx_multicast);
1636         data[11] = le16_to_cpu(tp->counters.tx_aborted);
1637         data[12] = le16_to_cpu(tp->counters.tx_underun);
1638 }
1639
1640 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1641 {
1642         switch(stringset) {
1643         case ETH_SS_STATS:
1644                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1645                 break;
1646         }
1647 }
1648
1649 static const struct ethtool_ops rtl8169_ethtool_ops = {
1650         .get_drvinfo            = rtl8169_get_drvinfo,
1651         .get_regs_len           = rtl8169_get_regs_len,
1652         .get_link               = ethtool_op_get_link,
1653         .get_settings           = rtl8169_get_settings,
1654         .set_settings           = rtl8169_set_settings,
1655         .get_msglevel           = rtl8169_get_msglevel,
1656         .set_msglevel           = rtl8169_set_msglevel,
1657         .get_regs               = rtl8169_get_regs,
1658         .get_wol                = rtl8169_get_wol,
1659         .set_wol                = rtl8169_set_wol,
1660         .get_strings            = rtl8169_get_strings,
1661         .get_sset_count         = rtl8169_get_sset_count,
1662         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1663 };
1664
1665 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1666                                     struct net_device *dev, u8 default_version)
1667 {
1668         void __iomem *ioaddr = tp->mmio_addr;
1669         /*
1670          * The driver currently handles the 8168Bf and the 8168Be identically
1671          * but they can be identified more specifically through the test below
1672          * if needed:
1673          *
1674          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1675          *
1676          * Same thing for the 8101Eb and the 8101Ec:
1677          *
1678          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1679          */
1680         static const struct rtl_mac_info {
1681                 u32 mask;
1682                 u32 val;
1683                 int mac_version;
1684         } mac_info[] = {
1685                 /* 8168E family. */
1686                 { 0x7cf00000, 0x2c200000,       RTL_GIGA_MAC_VER_33 },
1687                 { 0x7cf00000, 0x2c100000,       RTL_GIGA_MAC_VER_32 },
1688                 { 0x7c800000, 0x2c000000,       RTL_GIGA_MAC_VER_33 },
1689
1690                 /* 8168D family. */
1691                 { 0x7cf00000, 0x28300000,       RTL_GIGA_MAC_VER_26 },
1692                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
1693                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
1694
1695                 /* 8168DP family. */
1696                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
1697                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
1698                 { 0x7cf00000, 0x28b00000,       RTL_GIGA_MAC_VER_31 },
1699
1700                 /* 8168C family. */
1701                 { 0x7cf00000, 0x3cb00000,       RTL_GIGA_MAC_VER_24 },
1702                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
1703                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
1704                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
1705                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
1706                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
1707                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
1708                 { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
1709                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
1710
1711                 /* 8168B family. */
1712                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
1713                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
1714                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
1715                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
1716
1717                 /* 8101 family. */
1718                 { 0x7cf00000, 0x40b00000,       RTL_GIGA_MAC_VER_30 },
1719                 { 0x7cf00000, 0x40a00000,       RTL_GIGA_MAC_VER_30 },
1720                 { 0x7cf00000, 0x40900000,       RTL_GIGA_MAC_VER_29 },
1721                 { 0x7c800000, 0x40800000,       RTL_GIGA_MAC_VER_30 },
1722                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
1723                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
1724                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
1725                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
1726                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
1727                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
1728                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
1729                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
1730                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
1731                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
1732                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
1733                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
1734                 /* FIXME: where did these entries come from ? -- FR */
1735                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
1736                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
1737
1738                 /* 8110 family. */
1739                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
1740                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
1741                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
1742                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
1743                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
1744                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
1745
1746                 /* Catch-all */
1747                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
1748         };
1749         const struct rtl_mac_info *p = mac_info;
1750         u32 reg;
1751
1752         reg = RTL_R32(TxConfig);
1753         while ((reg & p->mask) != p->val)
1754                 p++;
1755         tp->mac_version = p->mac_version;
1756
1757         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
1758                 netif_notice(tp, probe, dev,
1759                              "unknown MAC, using family default\n");
1760                 tp->mac_version = default_version;
1761         }
1762 }
1763
1764 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1765 {
1766         dprintk("mac_version = 0x%02x\n", tp->mac_version);
1767 }
1768
1769 struct phy_reg {
1770         u16 reg;
1771         u16 val;
1772 };
1773
1774 static void rtl_writephy_batch(struct rtl8169_private *tp,
1775                                const struct phy_reg *regs, int len)
1776 {
1777         while (len-- > 0) {
1778                 rtl_writephy(tp, regs->reg, regs->val);
1779                 regs++;
1780         }
1781 }
1782
1783 #define PHY_READ                0x00000000
1784 #define PHY_DATA_OR             0x10000000
1785 #define PHY_DATA_AND            0x20000000
1786 #define PHY_BJMPN               0x30000000
1787 #define PHY_READ_EFUSE          0x40000000
1788 #define PHY_READ_MAC_BYTE       0x50000000
1789 #define PHY_WRITE_MAC_BYTE      0x60000000
1790 #define PHY_CLEAR_READCOUNT     0x70000000
1791 #define PHY_WRITE               0x80000000
1792 #define PHY_READCOUNT_EQ_SKIP   0x90000000
1793 #define PHY_COMP_EQ_SKIPN       0xa0000000
1794 #define PHY_COMP_NEQ_SKIPN      0xb0000000
1795 #define PHY_WRITE_PREVIOUS      0xc0000000
1796 #define PHY_SKIPN               0xd0000000
1797 #define PHY_DELAY_MS            0xe0000000
1798 #define PHY_WRITE_ERI_WORD      0xf0000000
1799
1800 static void
1801 rtl_phy_write_fw(struct rtl8169_private *tp, const struct firmware *fw)
1802 {
1803         __le32 *phytable = (__le32 *)fw->data;
1804         struct net_device *dev = tp->dev;
1805         size_t index, fw_size = fw->size / sizeof(*phytable);
1806         u32 predata, count;
1807
1808         if (fw->size % sizeof(*phytable)) {
1809                 netif_err(tp, probe, dev, "odd sized firmware %zd\n", fw->size);
1810                 return;
1811         }
1812
1813         for (index = 0; index < fw_size; index++) {
1814                 u32 action = le32_to_cpu(phytable[index]);
1815                 u32 regno = (action & 0x0fff0000) >> 16;
1816
1817                 switch(action & 0xf0000000) {
1818                 case PHY_READ:
1819                 case PHY_DATA_OR:
1820                 case PHY_DATA_AND:
1821                 case PHY_READ_EFUSE:
1822                 case PHY_CLEAR_READCOUNT:
1823                 case PHY_WRITE:
1824                 case PHY_WRITE_PREVIOUS:
1825                 case PHY_DELAY_MS:
1826                         break;
1827
1828                 case PHY_BJMPN:
1829                         if (regno > index) {
1830                                 netif_err(tp, probe, tp->dev,
1831                                           "Out of range of firmware\n");
1832                                 return;
1833                         }
1834                         break;
1835                 case PHY_READCOUNT_EQ_SKIP:
1836                         if (index + 2 >= fw_size) {
1837                                 netif_err(tp, probe, tp->dev,
1838                                           "Out of range of firmware\n");
1839                                 return;
1840                         }
1841                         break;
1842                 case PHY_COMP_EQ_SKIPN:
1843                 case PHY_COMP_NEQ_SKIPN:
1844                 case PHY_SKIPN:
1845                         if (index + 1 + regno >= fw_size) {
1846                                 netif_err(tp, probe, tp->dev,
1847                                           "Out of range of firmware\n");
1848                                 return;
1849                         }
1850                         break;
1851
1852                 case PHY_READ_MAC_BYTE:
1853                 case PHY_WRITE_MAC_BYTE:
1854                 case PHY_WRITE_ERI_WORD:
1855                 default:
1856                         netif_err(tp, probe, tp->dev,
1857                                   "Invalid action 0x%08x\n", action);
1858                         return;
1859                 }
1860         }
1861
1862         predata = 0;
1863         count = 0;
1864
1865         for (index = 0; index < fw_size; ) {
1866                 u32 action = le32_to_cpu(phytable[index]);
1867                 u32 data = action & 0x0000ffff;
1868                 u32 regno = (action & 0x0fff0000) >> 16;
1869
1870                 if (!action)
1871                         break;
1872
1873                 switch(action & 0xf0000000) {
1874                 case PHY_READ:
1875                         predata = rtl_readphy(tp, regno);
1876                         count++;
1877                         index++;
1878                         break;
1879                 case PHY_DATA_OR:
1880                         predata |= data;
1881                         index++;
1882                         break;
1883                 case PHY_DATA_AND:
1884                         predata &= data;
1885                         index++;
1886                         break;
1887                 case PHY_BJMPN:
1888                         index -= regno;
1889                         break;
1890                 case PHY_READ_EFUSE:
1891                         predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
1892                         index++;
1893                         break;
1894                 case PHY_CLEAR_READCOUNT:
1895                         count = 0;
1896                         index++;
1897                         break;
1898                 case PHY_WRITE:
1899                         rtl_writephy(tp, regno, data);
1900                         index++;
1901                         break;
1902                 case PHY_READCOUNT_EQ_SKIP:
1903                         index += (count == data) ? 2 : 1;
1904                         break;
1905                 case PHY_COMP_EQ_SKIPN:
1906                         if (predata == data)
1907                                 index += regno;
1908                         index++;
1909                         break;
1910                 case PHY_COMP_NEQ_SKIPN:
1911                         if (predata != data)
1912                                 index += regno;
1913                         index++;
1914                         break;
1915                 case PHY_WRITE_PREVIOUS:
1916                         rtl_writephy(tp, regno, predata);
1917                         index++;
1918                         break;
1919                 case PHY_SKIPN:
1920                         index += regno + 1;
1921                         break;
1922                 case PHY_DELAY_MS:
1923                         mdelay(data);
1924                         index++;
1925                         break;
1926
1927                 case PHY_READ_MAC_BYTE:
1928                 case PHY_WRITE_MAC_BYTE:
1929                 case PHY_WRITE_ERI_WORD:
1930                 default:
1931                         BUG();
1932                 }
1933         }
1934 }
1935
1936 static void rtl_release_firmware(struct rtl8169_private *tp)
1937 {
1938         if (!IS_ERR_OR_NULL(tp->fw))
1939                 release_firmware(tp->fw);
1940         tp->fw = RTL_FIRMWARE_UNKNOWN;
1941 }
1942
1943 static void rtl_apply_firmware(struct rtl8169_private *tp)
1944 {
1945         const struct firmware *fw = tp->fw;
1946
1947         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
1948         if (!IS_ERR_OR_NULL(fw))
1949                 rtl_phy_write_fw(tp, fw);
1950 }
1951
1952 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
1953 {
1954         if (rtl_readphy(tp, reg) != val)
1955                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
1956         else
1957                 rtl_apply_firmware(tp);
1958 }
1959
1960 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1961 {
1962         static const struct phy_reg phy_reg_init[] = {
1963                 { 0x1f, 0x0001 },
1964                 { 0x06, 0x006e },
1965                 { 0x08, 0x0708 },
1966                 { 0x15, 0x4000 },
1967                 { 0x18, 0x65c7 },
1968
1969                 { 0x1f, 0x0001 },
1970                 { 0x03, 0x00a1 },
1971                 { 0x02, 0x0008 },
1972                 { 0x01, 0x0120 },
1973                 { 0x00, 0x1000 },
1974                 { 0x04, 0x0800 },
1975                 { 0x04, 0x0000 },
1976
1977                 { 0x03, 0xff41 },
1978                 { 0x02, 0xdf60 },
1979                 { 0x01, 0x0140 },
1980                 { 0x00, 0x0077 },
1981                 { 0x04, 0x7800 },
1982                 { 0x04, 0x7000 },
1983
1984                 { 0x03, 0x802f },
1985                 { 0x02, 0x4f02 },
1986                 { 0x01, 0x0409 },
1987                 { 0x00, 0xf0f9 },
1988                 { 0x04, 0x9800 },
1989                 { 0x04, 0x9000 },
1990
1991                 { 0x03, 0xdf01 },
1992                 { 0x02, 0xdf20 },
1993                 { 0x01, 0xff95 },
1994                 { 0x00, 0xba00 },
1995                 { 0x04, 0xa800 },
1996                 { 0x04, 0xa000 },
1997
1998                 { 0x03, 0xff41 },
1999                 { 0x02, 0xdf20 },
2000                 { 0x01, 0x0140 },
2001                 { 0x00, 0x00bb },
2002                 { 0x04, 0xb800 },
2003                 { 0x04, 0xb000 },
2004
2005                 { 0x03, 0xdf41 },
2006                 { 0x02, 0xdc60 },
2007                 { 0x01, 0x6340 },
2008                 { 0x00, 0x007d },
2009                 { 0x04, 0xd800 },
2010                 { 0x04, 0xd000 },
2011
2012                 { 0x03, 0xdf01 },
2013                 { 0x02, 0xdf20 },
2014                 { 0x01, 0x100a },
2015                 { 0x00, 0xa0ff },
2016                 { 0x04, 0xf800 },
2017                 { 0x04, 0xf000 },
2018
2019                 { 0x1f, 0x0000 },
2020                 { 0x0b, 0x0000 },
2021                 { 0x00, 0x9200 }
2022         };
2023
2024         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2025 }
2026
2027 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2028 {
2029         static const struct phy_reg phy_reg_init[] = {
2030                 { 0x1f, 0x0002 },
2031                 { 0x01, 0x90d0 },
2032                 { 0x1f, 0x0000 }
2033         };
2034
2035         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2036 }
2037
2038 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2039 {
2040         struct pci_dev *pdev = tp->pci_dev;
2041         u16 vendor_id, device_id;
2042
2043         pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
2044         pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
2045
2046         if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
2047                 return;
2048
2049         rtl_writephy(tp, 0x1f, 0x0001);
2050         rtl_writephy(tp, 0x10, 0xf01b);
2051         rtl_writephy(tp, 0x1f, 0x0000);
2052 }
2053
2054 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2055 {
2056         static const struct phy_reg phy_reg_init[] = {
2057                 { 0x1f, 0x0001 },
2058                 { 0x04, 0x0000 },
2059                 { 0x03, 0x00a1 },
2060                 { 0x02, 0x0008 },
2061                 { 0x01, 0x0120 },
2062                 { 0x00, 0x1000 },
2063                 { 0x04, 0x0800 },
2064                 { 0x04, 0x9000 },
2065                 { 0x03, 0x802f },
2066                 { 0x02, 0x4f02 },
2067                 { 0x01, 0x0409 },
2068                 { 0x00, 0xf099 },
2069                 { 0x04, 0x9800 },
2070                 { 0x04, 0xa000 },
2071                 { 0x03, 0xdf01 },
2072                 { 0x02, 0xdf20 },
2073                 { 0x01, 0xff95 },
2074                 { 0x00, 0xba00 },
2075                 { 0x04, 0xa800 },
2076                 { 0x04, 0xf000 },
2077                 { 0x03, 0xdf01 },
2078                 { 0x02, 0xdf20 },
2079                 { 0x01, 0x101a },
2080                 { 0x00, 0xa0ff },
2081                 { 0x04, 0xf800 },
2082                 { 0x04, 0x0000 },
2083                 { 0x1f, 0x0000 },
2084
2085                 { 0x1f, 0x0001 },
2086                 { 0x10, 0xf41b },
2087                 { 0x14, 0xfb54 },
2088                 { 0x18, 0xf5c7 },
2089                 { 0x1f, 0x0000 },
2090
2091                 { 0x1f, 0x0001 },
2092                 { 0x17, 0x0cc0 },
2093                 { 0x1f, 0x0000 }
2094         };
2095
2096         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2097
2098         rtl8169scd_hw_phy_config_quirk(tp);
2099 }
2100
2101 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2102 {
2103         static const struct phy_reg phy_reg_init[] = {
2104                 { 0x1f, 0x0001 },
2105                 { 0x04, 0x0000 },
2106                 { 0x03, 0x00a1 },
2107                 { 0x02, 0x0008 },
2108                 { 0x01, 0x0120 },
2109                 { 0x00, 0x1000 },
2110                 { 0x04, 0x0800 },
2111                 { 0x04, 0x9000 },
2112                 { 0x03, 0x802f },
2113                 { 0x02, 0x4f02 },
2114                 { 0x01, 0x0409 },
2115                 { 0x00, 0xf099 },
2116                 { 0x04, 0x9800 },
2117                 { 0x04, 0xa000 },
2118                 { 0x03, 0xdf01 },
2119                 { 0x02, 0xdf20 },
2120                 { 0x01, 0xff95 },
2121                 { 0x00, 0xba00 },
2122                 { 0x04, 0xa800 },
2123                 { 0x04, 0xf000 },
2124                 { 0x03, 0xdf01 },
2125                 { 0x02, 0xdf20 },
2126                 { 0x01, 0x101a },
2127                 { 0x00, 0xa0ff },
2128                 { 0x04, 0xf800 },
2129                 { 0x04, 0x0000 },
2130                 { 0x1f, 0x0000 },
2131
2132                 { 0x1f, 0x0001 },
2133                 { 0x0b, 0x8480 },
2134                 { 0x1f, 0x0000 },
2135
2136                 { 0x1f, 0x0001 },
2137                 { 0x18, 0x67c7 },
2138                 { 0x04, 0x2000 },
2139                 { 0x03, 0x002f },
2140                 { 0x02, 0x4360 },
2141                 { 0x01, 0x0109 },
2142                 { 0x00, 0x3022 },
2143                 { 0x04, 0x2800 },
2144                 { 0x1f, 0x0000 },
2145
2146                 { 0x1f, 0x0001 },
2147                 { 0x17, 0x0cc0 },
2148                 { 0x1f, 0x0000 }
2149         };
2150
2151         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2152 }
2153
2154 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2155 {
2156         static const struct phy_reg phy_reg_init[] = {
2157                 { 0x10, 0xf41b },
2158                 { 0x1f, 0x0000 }
2159         };
2160
2161         rtl_writephy(tp, 0x1f, 0x0001);
2162         rtl_patchphy(tp, 0x16, 1 << 0);
2163
2164         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2165 }
2166
2167 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2168 {
2169         static const struct phy_reg phy_reg_init[] = {
2170                 { 0x1f, 0x0001 },
2171                 { 0x10, 0xf41b },
2172                 { 0x1f, 0x0000 }
2173         };
2174
2175         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2176 }
2177
2178 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2179 {
2180         static const struct phy_reg phy_reg_init[] = {
2181                 { 0x1f, 0x0000 },
2182                 { 0x1d, 0x0f00 },
2183                 { 0x1f, 0x0002 },
2184                 { 0x0c, 0x1ec8 },
2185                 { 0x1f, 0x0000 }
2186         };
2187
2188         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2189 }
2190
2191 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2192 {
2193         static const struct phy_reg phy_reg_init[] = {
2194                 { 0x1f, 0x0001 },
2195                 { 0x1d, 0x3d98 },
2196                 { 0x1f, 0x0000 }
2197         };
2198
2199         rtl_writephy(tp, 0x1f, 0x0000);
2200         rtl_patchphy(tp, 0x14, 1 << 5);
2201         rtl_patchphy(tp, 0x0d, 1 << 5);
2202
2203         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2204 }
2205
2206 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2207 {
2208         static const struct phy_reg phy_reg_init[] = {
2209                 { 0x1f, 0x0001 },
2210                 { 0x12, 0x2300 },
2211                 { 0x1f, 0x0002 },
2212                 { 0x00, 0x88d4 },
2213                 { 0x01, 0x82b1 },
2214                 { 0x03, 0x7002 },
2215                 { 0x08, 0x9e30 },
2216                 { 0x09, 0x01f0 },
2217                 { 0x0a, 0x5500 },
2218                 { 0x0c, 0x00c8 },
2219                 { 0x1f, 0x0003 },
2220                 { 0x12, 0xc096 },
2221                 { 0x16, 0x000a },
2222                 { 0x1f, 0x0000 },
2223                 { 0x1f, 0x0000 },
2224                 { 0x09, 0x2000 },
2225                 { 0x09, 0x0000 }
2226         };
2227
2228         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2229
2230         rtl_patchphy(tp, 0x14, 1 << 5);
2231         rtl_patchphy(tp, 0x0d, 1 << 5);
2232         rtl_writephy(tp, 0x1f, 0x0000);
2233 }
2234
2235 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2236 {
2237         static const struct phy_reg phy_reg_init[] = {
2238                 { 0x1f, 0x0001 },
2239                 { 0x12, 0x2300 },
2240                 { 0x03, 0x802f },
2241                 { 0x02, 0x4f02 },
2242                 { 0x01, 0x0409 },
2243                 { 0x00, 0xf099 },
2244                 { 0x04, 0x9800 },
2245                 { 0x04, 0x9000 },
2246                 { 0x1d, 0x3d98 },
2247                 { 0x1f, 0x0002 },
2248                 { 0x0c, 0x7eb8 },
2249                 { 0x06, 0x0761 },
2250                 { 0x1f, 0x0003 },
2251                 { 0x16, 0x0f0a },
2252                 { 0x1f, 0x0000 }
2253         };
2254
2255         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2256
2257         rtl_patchphy(tp, 0x16, 1 << 0);
2258         rtl_patchphy(tp, 0x14, 1 << 5);
2259         rtl_patchphy(tp, 0x0d, 1 << 5);
2260         rtl_writephy(tp, 0x1f, 0x0000);
2261 }
2262
2263 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2264 {
2265         static const struct phy_reg phy_reg_init[] = {
2266                 { 0x1f, 0x0001 },
2267                 { 0x12, 0x2300 },
2268                 { 0x1d, 0x3d98 },
2269                 { 0x1f, 0x0002 },
2270                 { 0x0c, 0x7eb8 },
2271                 { 0x06, 0x5461 },
2272                 { 0x1f, 0x0003 },
2273                 { 0x16, 0x0f0a },
2274                 { 0x1f, 0x0000 }
2275         };
2276
2277         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2278
2279         rtl_patchphy(tp, 0x16, 1 << 0);
2280         rtl_patchphy(tp, 0x14, 1 << 5);
2281         rtl_patchphy(tp, 0x0d, 1 << 5);
2282         rtl_writephy(tp, 0x1f, 0x0000);
2283 }
2284
2285 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2286 {
2287         rtl8168c_3_hw_phy_config(tp);
2288 }
2289
2290 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2291 {
2292         static const struct phy_reg phy_reg_init_0[] = {
2293                 /* Channel Estimation */
2294                 { 0x1f, 0x0001 },
2295                 { 0x06, 0x4064 },
2296                 { 0x07, 0x2863 },
2297                 { 0x08, 0x059c },
2298                 { 0x09, 0x26b4 },
2299                 { 0x0a, 0x6a19 },
2300                 { 0x0b, 0xdcc8 },
2301                 { 0x10, 0xf06d },
2302                 { 0x14, 0x7f68 },
2303                 { 0x18, 0x7fd9 },
2304                 { 0x1c, 0xf0ff },
2305                 { 0x1d, 0x3d9c },
2306                 { 0x1f, 0x0003 },
2307                 { 0x12, 0xf49f },
2308                 { 0x13, 0x070b },
2309                 { 0x1a, 0x05ad },
2310                 { 0x14, 0x94c0 },
2311
2312                 /*
2313                  * Tx Error Issue
2314                  * Enhance line driver power
2315                  */
2316                 { 0x1f, 0x0002 },
2317                 { 0x06, 0x5561 },
2318                 { 0x1f, 0x0005 },
2319                 { 0x05, 0x8332 },
2320                 { 0x06, 0x5561 },
2321
2322                 /*
2323                  * Can not link to 1Gbps with bad cable
2324                  * Decrease SNR threshold form 21.07dB to 19.04dB
2325                  */
2326                 { 0x1f, 0x0001 },
2327                 { 0x17, 0x0cc0 },
2328
2329                 { 0x1f, 0x0000 },
2330                 { 0x0d, 0xf880 }
2331         };
2332         void __iomem *ioaddr = tp->mmio_addr;
2333
2334         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2335
2336         /*
2337          * Rx Error Issue
2338          * Fine Tune Switching regulator parameter
2339          */
2340         rtl_writephy(tp, 0x1f, 0x0002);
2341         rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2342         rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2343
2344         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2345                 static const struct phy_reg phy_reg_init[] = {
2346                         { 0x1f, 0x0002 },
2347                         { 0x05, 0x669a },
2348                         { 0x1f, 0x0005 },
2349                         { 0x05, 0x8330 },
2350                         { 0x06, 0x669a },
2351                         { 0x1f, 0x0002 }
2352                 };
2353                 int val;
2354
2355                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2356
2357                 val = rtl_readphy(tp, 0x0d);
2358
2359                 if ((val & 0x00ff) != 0x006c) {
2360                         static const u32 set[] = {
2361                                 0x0065, 0x0066, 0x0067, 0x0068,
2362                                 0x0069, 0x006a, 0x006b, 0x006c
2363                         };
2364                         int i;
2365
2366                         rtl_writephy(tp, 0x1f, 0x0002);
2367
2368                         val &= 0xff00;
2369                         for (i = 0; i < ARRAY_SIZE(set); i++)
2370                                 rtl_writephy(tp, 0x0d, val | set[i]);
2371                 }
2372         } else {
2373                 static const struct phy_reg phy_reg_init[] = {
2374                         { 0x1f, 0x0002 },
2375                         { 0x05, 0x6662 },
2376                         { 0x1f, 0x0005 },
2377                         { 0x05, 0x8330 },
2378                         { 0x06, 0x6662 }
2379                 };
2380
2381                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2382         }
2383
2384         /* RSET couple improve */
2385         rtl_writephy(tp, 0x1f, 0x0002);
2386         rtl_patchphy(tp, 0x0d, 0x0300);
2387         rtl_patchphy(tp, 0x0f, 0x0010);
2388
2389         /* Fine tune PLL performance */
2390         rtl_writephy(tp, 0x1f, 0x0002);
2391         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2392         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2393
2394         rtl_writephy(tp, 0x1f, 0x0005);
2395         rtl_writephy(tp, 0x05, 0x001b);
2396
2397         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2398
2399         rtl_writephy(tp, 0x1f, 0x0000);
2400 }
2401
2402 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2403 {
2404         static const struct phy_reg phy_reg_init_0[] = {
2405                 /* Channel Estimation */
2406                 { 0x1f, 0x0001 },
2407                 { 0x06, 0x4064 },
2408                 { 0x07, 0x2863 },
2409                 { 0x08, 0x059c },
2410                 { 0x09, 0x26b4 },
2411                 { 0x0a, 0x6a19 },
2412                 { 0x0b, 0xdcc8 },
2413                 { 0x10, 0xf06d },
2414                 { 0x14, 0x7f68 },
2415                 { 0x18, 0x7fd9 },
2416                 { 0x1c, 0xf0ff },
2417                 { 0x1d, 0x3d9c },
2418                 { 0x1f, 0x0003 },
2419                 { 0x12, 0xf49f },
2420                 { 0x13, 0x070b },
2421                 { 0x1a, 0x05ad },
2422                 { 0x14, 0x94c0 },
2423
2424                 /*
2425                  * Tx Error Issue
2426                  * Enhance line driver power
2427                  */
2428                 { 0x1f, 0x0002 },
2429                 { 0x06, 0x5561 },
2430                 { 0x1f, 0x0005 },
2431                 { 0x05, 0x8332 },
2432                 { 0x06, 0x5561 },
2433
2434                 /*
2435                  * Can not link to 1Gbps with bad cable
2436                  * Decrease SNR threshold form 21.07dB to 19.04dB
2437                  */
2438                 { 0x1f, 0x0001 },
2439                 { 0x17, 0x0cc0 },
2440
2441                 { 0x1f, 0x0000 },
2442                 { 0x0d, 0xf880 }
2443         };
2444         void __iomem *ioaddr = tp->mmio_addr;
2445
2446         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2447
2448         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2449                 static const struct phy_reg phy_reg_init[] = {
2450                         { 0x1f, 0x0002 },
2451                         { 0x05, 0x669a },
2452                         { 0x1f, 0x0005 },
2453                         { 0x05, 0x8330 },
2454                         { 0x06, 0x669a },
2455
2456                         { 0x1f, 0x0002 }
2457                 };
2458                 int val;
2459
2460                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2461
2462                 val = rtl_readphy(tp, 0x0d);
2463                 if ((val & 0x00ff) != 0x006c) {
2464                         static const u32 set[] = {
2465                                 0x0065, 0x0066, 0x0067, 0x0068,
2466                                 0x0069, 0x006a, 0x006b, 0x006c
2467                         };
2468                         int i;
2469
2470                         rtl_writephy(tp, 0x1f, 0x0002);
2471
2472                         val &= 0xff00;
2473                         for (i = 0; i < ARRAY_SIZE(set); i++)
2474                                 rtl_writephy(tp, 0x0d, val | set[i]);
2475                 }
2476         } else {
2477                 static const struct phy_reg phy_reg_init[] = {
2478                         { 0x1f, 0x0002 },
2479                         { 0x05, 0x2642 },
2480                         { 0x1f, 0x0005 },
2481                         { 0x05, 0x8330 },
2482                         { 0x06, 0x2642 }
2483                 };
2484
2485                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2486         }
2487
2488         /* Fine tune PLL performance */
2489         rtl_writephy(tp, 0x1f, 0x0002);
2490         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2491         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2492
2493         /* Switching regulator Slew rate */
2494         rtl_writephy(tp, 0x1f, 0x0002);
2495         rtl_patchphy(tp, 0x0f, 0x0017);
2496
2497         rtl_writephy(tp, 0x1f, 0x0005);
2498         rtl_writephy(tp, 0x05, 0x001b);
2499
2500         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2501
2502         rtl_writephy(tp, 0x1f, 0x0000);
2503 }
2504
2505 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2506 {
2507         static const struct phy_reg phy_reg_init[] = {
2508                 { 0x1f, 0x0002 },
2509                 { 0x10, 0x0008 },
2510                 { 0x0d, 0x006c },
2511
2512                 { 0x1f, 0x0000 },
2513                 { 0x0d, 0xf880 },
2514
2515                 { 0x1f, 0x0001 },
2516                 { 0x17, 0x0cc0 },
2517
2518                 { 0x1f, 0x0001 },
2519                 { 0x0b, 0xa4d8 },
2520                 { 0x09, 0x281c },
2521                 { 0x07, 0x2883 },
2522                 { 0x0a, 0x6b35 },
2523                 { 0x1d, 0x3da4 },
2524                 { 0x1c, 0xeffd },
2525                 { 0x14, 0x7f52 },
2526                 { 0x18, 0x7fc6 },
2527                 { 0x08, 0x0601 },
2528                 { 0x06, 0x4063 },
2529                 { 0x10, 0xf074 },
2530                 { 0x1f, 0x0003 },
2531                 { 0x13, 0x0789 },
2532                 { 0x12, 0xf4bd },
2533                 { 0x1a, 0x04fd },
2534                 { 0x14, 0x84b0 },
2535                 { 0x1f, 0x0000 },
2536                 { 0x00, 0x9200 },
2537
2538                 { 0x1f, 0x0005 },
2539                 { 0x01, 0x0340 },
2540                 { 0x1f, 0x0001 },
2541                 { 0x04, 0x4000 },
2542                 { 0x03, 0x1d21 },
2543                 { 0x02, 0x0c32 },
2544                 { 0x01, 0x0200 },
2545                 { 0x00, 0x5554 },
2546                 { 0x04, 0x4800 },
2547                 { 0x04, 0x4000 },
2548                 { 0x04, 0xf000 },
2549                 { 0x03, 0xdf01 },
2550                 { 0x02, 0xdf20 },
2551                 { 0x01, 0x101a },
2552                 { 0x00, 0xa0ff },
2553                 { 0x04, 0xf800 },
2554                 { 0x04, 0xf000 },
2555                 { 0x1f, 0x0000 },
2556
2557                 { 0x1f, 0x0007 },
2558                 { 0x1e, 0x0023 },
2559                 { 0x16, 0x0000 },
2560                 { 0x1f, 0x0000 }
2561         };
2562
2563         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2564 }
2565
2566 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2567 {
2568         static const struct phy_reg phy_reg_init[] = {
2569                 { 0x1f, 0x0001 },
2570                 { 0x17, 0x0cc0 },
2571
2572                 { 0x1f, 0x0007 },
2573                 { 0x1e, 0x002d },
2574                 { 0x18, 0x0040 },
2575                 { 0x1f, 0x0000 }
2576         };
2577
2578         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2579         rtl_patchphy(tp, 0x0d, 1 << 5);
2580 }
2581
2582 static void rtl8168e_hw_phy_config(struct rtl8169_private *tp)
2583 {
2584         static const struct phy_reg phy_reg_init[] = {
2585                 /* Enable Delay cap */
2586                 { 0x1f, 0x0005 },
2587                 { 0x05, 0x8b80 },
2588                 { 0x06, 0xc896 },
2589                 { 0x1f, 0x0000 },
2590
2591                 /* Channel estimation fine tune */
2592                 { 0x1f, 0x0001 },
2593                 { 0x0b, 0x6c20 },
2594                 { 0x07, 0x2872 },
2595                 { 0x1c, 0xefff },
2596                 { 0x1f, 0x0003 },
2597                 { 0x14, 0x6420 },
2598                 { 0x1f, 0x0000 },
2599
2600                 /* Update PFM & 10M TX idle timer */
2601                 { 0x1f, 0x0007 },
2602                 { 0x1e, 0x002f },
2603                 { 0x15, 0x1919 },
2604                 { 0x1f, 0x0000 },
2605
2606                 { 0x1f, 0x0007 },
2607                 { 0x1e, 0x00ac },
2608                 { 0x18, 0x0006 },
2609                 { 0x1f, 0x0000 }
2610         };
2611
2612         rtl_apply_firmware(tp);
2613
2614         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2615
2616         /* DCO enable for 10M IDLE Power */
2617         rtl_writephy(tp, 0x1f, 0x0007);
2618         rtl_writephy(tp, 0x1e, 0x0023);
2619         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2620         rtl_writephy(tp, 0x1f, 0x0000);
2621
2622         /* For impedance matching */
2623         rtl_writephy(tp, 0x1f, 0x0002);
2624         rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
2625         rtl_writephy(tp, 0x1f, 0x0000);
2626
2627         /* PHY auto speed down */
2628         rtl_writephy(tp, 0x1f, 0x0007);
2629         rtl_writephy(tp, 0x1e, 0x002d);
2630         rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2631         rtl_writephy(tp, 0x1f, 0x0000);
2632         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2633
2634         rtl_writephy(tp, 0x1f, 0x0005);
2635         rtl_writephy(tp, 0x05, 0x8b86);
2636         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2637         rtl_writephy(tp, 0x1f, 0x0000);
2638
2639         rtl_writephy(tp, 0x1f, 0x0005);
2640         rtl_writephy(tp, 0x05, 0x8b85);
2641         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2642         rtl_writephy(tp, 0x1f, 0x0007);
2643         rtl_writephy(tp, 0x1e, 0x0020);
2644         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2645         rtl_writephy(tp, 0x1f, 0x0006);
2646         rtl_writephy(tp, 0x00, 0x5a00);
2647         rtl_writephy(tp, 0x1f, 0x0000);
2648         rtl_writephy(tp, 0x0d, 0x0007);
2649         rtl_writephy(tp, 0x0e, 0x003c);
2650         rtl_writephy(tp, 0x0d, 0x4007);
2651         rtl_writephy(tp, 0x0e, 0x0000);
2652         rtl_writephy(tp, 0x0d, 0x0000);
2653 }
2654
2655 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2656 {
2657         static const struct phy_reg phy_reg_init[] = {
2658                 { 0x1f, 0x0003 },
2659                 { 0x08, 0x441d },
2660                 { 0x01, 0x9100 },
2661                 { 0x1f, 0x0000 }
2662         };
2663
2664         rtl_writephy(tp, 0x1f, 0x0000);
2665         rtl_patchphy(tp, 0x11, 1 << 12);
2666         rtl_patchphy(tp, 0x19, 1 << 13);
2667         rtl_patchphy(tp, 0x10, 1 << 15);
2668
2669         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2670 }
2671
2672 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
2673 {
2674         static const struct phy_reg phy_reg_init[] = {
2675                 { 0x1f, 0x0005 },
2676                 { 0x1a, 0x0000 },
2677                 { 0x1f, 0x0000 },
2678
2679                 { 0x1f, 0x0004 },
2680                 { 0x1c, 0x0000 },
2681                 { 0x1f, 0x0000 },
2682
2683                 { 0x1f, 0x0001 },
2684                 { 0x15, 0x7701 },
2685                 { 0x1f, 0x0000 }
2686         };
2687
2688         /* Disable ALDPS before ram code */
2689         rtl_writephy(tp, 0x1f, 0x0000);
2690         rtl_writephy(tp, 0x18, 0x0310);
2691         msleep(100);
2692
2693         rtl_apply_firmware(tp);
2694
2695         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2696 }
2697
2698 static void rtl_hw_phy_config(struct net_device *dev)
2699 {
2700         struct rtl8169_private *tp = netdev_priv(dev);
2701
2702         rtl8169_print_mac_version(tp);
2703
2704         switch (tp->mac_version) {
2705         case RTL_GIGA_MAC_VER_01:
2706                 break;
2707         case RTL_GIGA_MAC_VER_02:
2708         case RTL_GIGA_MAC_VER_03:
2709                 rtl8169s_hw_phy_config(tp);
2710                 break;
2711         case RTL_GIGA_MAC_VER_04:
2712                 rtl8169sb_hw_phy_config(tp);
2713                 break;
2714         case RTL_GIGA_MAC_VER_05:
2715                 rtl8169scd_hw_phy_config(tp);
2716                 break;
2717         case RTL_GIGA_MAC_VER_06:
2718                 rtl8169sce_hw_phy_config(tp);
2719                 break;
2720         case RTL_GIGA_MAC_VER_07:
2721         case RTL_GIGA_MAC_VER_08:
2722         case RTL_GIGA_MAC_VER_09:
2723                 rtl8102e_hw_phy_config(tp);
2724                 break;
2725         case RTL_GIGA_MAC_VER_11:
2726                 rtl8168bb_hw_phy_config(tp);
2727                 break;
2728         case RTL_GIGA_MAC_VER_12:
2729                 rtl8168bef_hw_phy_config(tp);
2730                 break;
2731         case RTL_GIGA_MAC_VER_17:
2732                 rtl8168bef_hw_phy_config(tp);
2733                 break;
2734         case RTL_GIGA_MAC_VER_18:
2735                 rtl8168cp_1_hw_phy_config(tp);
2736                 break;
2737         case RTL_GIGA_MAC_VER_19:
2738                 rtl8168c_1_hw_phy_config(tp);
2739                 break;
2740         case RTL_GIGA_MAC_VER_20:
2741                 rtl8168c_2_hw_phy_config(tp);
2742                 break;
2743         case RTL_GIGA_MAC_VER_21:
2744                 rtl8168c_3_hw_phy_config(tp);
2745                 break;
2746         case RTL_GIGA_MAC_VER_22:
2747                 rtl8168c_4_hw_phy_config(tp);
2748                 break;
2749         case RTL_GIGA_MAC_VER_23:
2750         case RTL_GIGA_MAC_VER_24:
2751                 rtl8168cp_2_hw_phy_config(tp);
2752                 break;
2753         case RTL_GIGA_MAC_VER_25:
2754                 rtl8168d_1_hw_phy_config(tp);
2755                 break;
2756         case RTL_GIGA_MAC_VER_26:
2757                 rtl8168d_2_hw_phy_config(tp);
2758                 break;
2759         case RTL_GIGA_MAC_VER_27:
2760                 rtl8168d_3_hw_phy_config(tp);
2761                 break;
2762         case RTL_GIGA_MAC_VER_28:
2763                 rtl8168d_4_hw_phy_config(tp);
2764                 break;
2765         case RTL_GIGA_MAC_VER_29:
2766         case RTL_GIGA_MAC_VER_30:
2767                 rtl8105e_hw_phy_config(tp);
2768                 break;
2769         case RTL_GIGA_MAC_VER_31:
2770                 /* None. */
2771                 break;
2772         case RTL_GIGA_MAC_VER_32:
2773         case RTL_GIGA_MAC_VER_33:
2774                 rtl8168e_hw_phy_config(tp);
2775                 break;
2776
2777         default:
2778                 break;
2779         }
2780 }
2781
2782 static void rtl8169_phy_timer(unsigned long __opaque)
2783 {
2784         struct net_device *dev = (struct net_device *)__opaque;
2785         struct rtl8169_private *tp = netdev_priv(dev);
2786         struct timer_list *timer = &tp->timer;
2787         void __iomem *ioaddr = tp->mmio_addr;
2788         unsigned long timeout = RTL8169_PHY_TIMEOUT;
2789
2790         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
2791
2792         spin_lock_irq(&tp->lock);
2793
2794         if (tp->phy_reset_pending(tp)) {
2795                 /*
2796                  * A busy loop could burn quite a few cycles on nowadays CPU.
2797                  * Let's delay the execution of the timer for a few ticks.
2798                  */
2799                 timeout = HZ/10;
2800                 goto out_mod_timer;
2801         }
2802
2803         if (tp->link_ok(ioaddr))
2804                 goto out_unlock;
2805
2806         netif_warn(tp, link, dev, "PHY reset until link up\n");
2807
2808         tp->phy_reset_enable(tp);
2809
2810 out_mod_timer:
2811         mod_timer(timer, jiffies + timeout);
2812 out_unlock:
2813         spin_unlock_irq(&tp->lock);
2814 }
2815
2816 #ifdef CONFIG_NET_POLL_CONTROLLER
2817 /*
2818  * Polling 'interrupt' - used by things like netconsole to send skbs
2819  * without having to re-enable interrupts. It's not called while
2820  * the interrupt routine is executing.
2821  */
2822 static void rtl8169_netpoll(struct net_device *dev)
2823 {
2824         struct rtl8169_private *tp = netdev_priv(dev);
2825         struct pci_dev *pdev = tp->pci_dev;
2826
2827         disable_irq(pdev->irq);
2828         rtl8169_interrupt(pdev->irq, dev);
2829         enable_irq(pdev->irq);
2830 }
2831 #endif
2832
2833 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
2834                                   void __iomem *ioaddr)
2835 {
2836         iounmap(ioaddr);
2837         pci_release_regions(pdev);
2838         pci_clear_mwi(pdev);
2839         pci_disable_device(pdev);
2840         free_netdev(dev);
2841 }
2842
2843 static void rtl8169_phy_reset(struct net_device *dev,
2844                               struct rtl8169_private *tp)
2845 {
2846         unsigned int i;
2847
2848         tp->phy_reset_enable(tp);
2849         for (i = 0; i < 100; i++) {
2850                 if (!tp->phy_reset_pending(tp))
2851                         return;
2852                 msleep(1);
2853         }
2854         netif_err(tp, link, dev, "PHY reset failed\n");
2855 }
2856
2857 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
2858 {
2859         void __iomem *ioaddr = tp->mmio_addr;
2860
2861         rtl_hw_phy_config(dev);
2862
2863         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2864                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2865                 RTL_W8(0x82, 0x01);
2866         }
2867
2868         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2869
2870         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
2871                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
2872
2873         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
2874                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2875                 RTL_W8(0x82, 0x01);
2876                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
2877                 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
2878         }
2879
2880         rtl8169_phy_reset(dev, tp);
2881
2882         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
2883                           ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
2884                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
2885                           (tp->mii.supports_gmii ?
2886                            ADVERTISED_1000baseT_Half |
2887                            ADVERTISED_1000baseT_Full : 0));
2888
2889         if (RTL_R8(PHYstatus) & TBI_Enable)
2890                 netif_info(tp, link, dev, "TBI auto-negotiating\n");
2891 }
2892
2893 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2894 {
2895         void __iomem *ioaddr = tp->mmio_addr;
2896         u32 high;
2897         u32 low;
2898
2899         low  = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
2900         high = addr[4] | (addr[5] << 8);
2901
2902         spin_lock_irq(&tp->lock);
2903
2904         RTL_W8(Cfg9346, Cfg9346_Unlock);
2905
2906         RTL_W32(MAC4, high);
2907         RTL_R32(MAC4);
2908
2909         RTL_W32(MAC0, low);
2910         RTL_R32(MAC0);
2911
2912         RTL_W8(Cfg9346, Cfg9346_Lock);
2913
2914         spin_unlock_irq(&tp->lock);
2915 }
2916
2917 static int rtl_set_mac_address(struct net_device *dev, void *p)
2918 {
2919         struct rtl8169_private *tp = netdev_priv(dev);
2920         struct sockaddr *addr = p;
2921
2922         if (!is_valid_ether_addr(addr->sa_data))
2923                 return -EADDRNOTAVAIL;
2924
2925         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2926
2927         rtl_rar_set(tp, dev->dev_addr);
2928
2929         return 0;
2930 }
2931
2932 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2933 {
2934         struct rtl8169_private *tp = netdev_priv(dev);
2935         struct mii_ioctl_data *data = if_mii(ifr);
2936
2937         return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
2938 }
2939
2940 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
2941                           struct mii_ioctl_data *data, int cmd)
2942 {
2943         switch (cmd) {
2944         case SIOCGMIIPHY:
2945                 data->phy_id = 32; /* Internal PHY */
2946                 return 0;
2947
2948         case SIOCGMIIREG:
2949                 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
2950                 return 0;
2951
2952         case SIOCSMIIREG:
2953                 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
2954                 return 0;
2955         }
2956         return -EOPNOTSUPP;
2957 }
2958
2959 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2960 {
2961         return -EOPNOTSUPP;
2962 }
2963
2964 static const struct rtl_cfg_info {
2965         void (*hw_start)(struct net_device *);
2966         unsigned int region;
2967         unsigned int align;
2968         u16 intr_event;
2969         u16 napi_event;
2970         unsigned features;
2971         u8 default_ver;
2972 } rtl_cfg_infos [] = {
2973         [RTL_CFG_0] = {
2974                 .hw_start       = rtl_hw_start_8169,
2975                 .region         = 1,
2976                 .align          = 0,
2977                 .intr_event     = SYSErr | LinkChg | RxOverflow |
2978                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2979                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2980                 .features       = RTL_FEATURE_GMII,
2981                 .default_ver    = RTL_GIGA_MAC_VER_01,
2982         },
2983         [RTL_CFG_1] = {
2984                 .hw_start       = rtl_hw_start_8168,
2985                 .region         = 2,
2986                 .align          = 8,
2987                 .intr_event     = SYSErr | LinkChg | RxOverflow |
2988                                   TxErr | TxOK | RxOK | RxErr,
2989                 .napi_event     = TxErr | TxOK | RxOK | RxOverflow,
2990                 .features       = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
2991                 .default_ver    = RTL_GIGA_MAC_VER_11,
2992         },
2993         [RTL_CFG_2] = {
2994                 .hw_start       = rtl_hw_start_8101,
2995                 .region         = 2,
2996                 .align          = 8,
2997                 .intr_event     = SYSErr | LinkChg | RxOverflow | PCSTimeout |
2998                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2999                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
3000                 .features       = RTL_FEATURE_MSI,
3001                 .default_ver    = RTL_GIGA_MAC_VER_13,
3002         }
3003 };
3004
3005 /* Cfg9346_Unlock assumed. */
3006 static unsigned rtl_try_msi(struct rtl8169_private *tp,
3007                             const struct rtl_cfg_info *cfg)
3008 {
3009         void __iomem *ioaddr = tp->mmio_addr;
3010         unsigned msi = 0;
3011         u8 cfg2;
3012
3013         cfg2 = RTL_R8(Config2) & ~MSIEnable;
3014         if (cfg->features & RTL_FEATURE_MSI) {
3015                 if (pci_enable_msi(tp->pci_dev)) {
3016                         netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
3017                 } else {
3018                         cfg2 |= MSIEnable;
3019                         msi = RTL_FEATURE_MSI;
3020                 }
3021         }
3022         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3023                 RTL_W8(Config2, cfg2);
3024         return msi;
3025 }
3026
3027 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3028 {
3029         if (tp->features & RTL_FEATURE_MSI) {
3030                 pci_disable_msi(pdev);
3031                 tp->features &= ~RTL_FEATURE_MSI;
3032         }
3033 }
3034
3035 static const struct net_device_ops rtl8169_netdev_ops = {
3036         .ndo_open               = rtl8169_open,
3037         .ndo_stop               = rtl8169_close,
3038         .ndo_get_stats          = rtl8169_get_stats,
3039         .ndo_start_xmit         = rtl8169_start_xmit,
3040         .ndo_tx_timeout         = rtl8169_tx_timeout,
3041         .ndo_validate_addr      = eth_validate_addr,
3042         .ndo_change_mtu         = rtl8169_change_mtu,
3043         .ndo_fix_features       = rtl8169_fix_features,
3044         .ndo_set_features       = rtl8169_set_features,
3045         .ndo_set_mac_address    = rtl_set_mac_address,
3046         .ndo_do_ioctl           = rtl8169_ioctl,
3047         .ndo_set_multicast_list = rtl_set_rx_mode,
3048 #ifdef CONFIG_NET_POLL_CONTROLLER
3049         .ndo_poll_controller    = rtl8169_netpoll,
3050 #endif
3051
3052 };
3053
3054 static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
3055 {
3056         struct mdio_ops *ops = &tp->mdio_ops;
3057
3058         switch (tp->mac_version) {
3059         case RTL_GIGA_MAC_VER_27:
3060                 ops->write      = r8168dp_1_mdio_write;
3061                 ops->read       = r8168dp_1_mdio_read;
3062                 break;
3063         case RTL_GIGA_MAC_VER_28:
3064         case RTL_GIGA_MAC_VER_31:
3065                 ops->write      = r8168dp_2_mdio_write;
3066                 ops->read       = r8168dp_2_mdio_read;
3067                 break;
3068         default:
3069                 ops->write      = r8169_mdio_write;
3070                 ops->read       = r8169_mdio_read;
3071                 break;
3072         }
3073 }
3074
3075 static void r810x_phy_power_down(struct rtl8169_private *tp)
3076 {
3077         rtl_writephy(tp, 0x1f, 0x0000);
3078         rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3079 }
3080
3081 static void r810x_phy_power_up(struct rtl8169_private *tp)
3082 {
3083         rtl_writephy(tp, 0x1f, 0x0000);
3084         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3085 }
3086
3087 static void r810x_pll_power_down(struct rtl8169_private *tp)
3088 {
3089         if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3090                 rtl_writephy(tp, 0x1f, 0x0000);
3091                 rtl_writephy(tp, MII_BMCR, 0x0000);
3092                 return;
3093         }
3094
3095         r810x_phy_power_down(tp);
3096 }
3097
3098 static void r810x_pll_power_up(struct rtl8169_private *tp)
3099 {
3100         r810x_phy_power_up(tp);
3101 }
3102
3103 static void r8168_phy_power_up(struct rtl8169_private *tp)
3104 {
3105         rtl_writephy(tp, 0x1f, 0x0000);
3106         switch (tp->mac_version) {
3107         case RTL_GIGA_MAC_VER_11:
3108         case RTL_GIGA_MAC_VER_12:
3109         case RTL_GIGA_MAC_VER_17:
3110         case RTL_GIGA_MAC_VER_18:
3111         case RTL_GIGA_MAC_VER_19:
3112         case RTL_GIGA_MAC_VER_20:
3113         case RTL_GIGA_MAC_VER_21:
3114         case RTL_GIGA_MAC_VER_22:
3115         case RTL_GIGA_MAC_VER_23:
3116         case RTL_GIGA_MAC_VER_24:
3117         case RTL_GIGA_MAC_VER_25:
3118         case RTL_GIGA_MAC_VER_26:
3119         case RTL_GIGA_MAC_VER_27:
3120         case RTL_GIGA_MAC_VER_28:
3121         case RTL_GIGA_MAC_VER_31:
3122                 rtl_writephy(tp, 0x0e, 0x0000);
3123                 break;
3124         default:
3125                 break;
3126         }
3127         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3128 }
3129
3130 static void r8168_phy_power_down(struct rtl8169_private *tp)
3131 {
3132         rtl_writephy(tp, 0x1f, 0x0000);
3133         switch (tp->mac_version) {
3134         case RTL_GIGA_MAC_VER_32:
3135         case RTL_GIGA_MAC_VER_33:
3136                 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3137                 break;
3138
3139         case RTL_GIGA_MAC_VER_11:
3140         case RTL_GIGA_MAC_VER_12:
3141         case RTL_GIGA_MAC_VER_17:
3142         case RTL_GIGA_MAC_VER_18:
3143         case RTL_GIGA_MAC_VER_19:
3144         case RTL_GIGA_MAC_VER_20:
3145         case RTL_GIGA_MAC_VER_21:
3146         case RTL_GIGA_MAC_VER_22:
3147         case RTL_GIGA_MAC_VER_23:
3148         case RTL_GIGA_MAC_VER_24:
3149         case RTL_GIGA_MAC_VER_25:
3150         case RTL_GIGA_MAC_VER_26:
3151         case RTL_GIGA_MAC_VER_27:
3152         case RTL_GIGA_MAC_VER_28:
3153         case RTL_GIGA_MAC_VER_31:
3154                 rtl_writephy(tp, 0x0e, 0x0200);
3155         default:
3156                 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3157                 break;
3158         }
3159 }
3160
3161 static void r8168_pll_power_down(struct rtl8169_private *tp)
3162 {
3163         void __iomem *ioaddr = tp->mmio_addr;
3164
3165         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3166              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3167              tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3168             r8168dp_check_dash(tp)) {
3169                 return;
3170         }
3171
3172         if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
3173              tp->mac_version == RTL_GIGA_MAC_VER_24) &&
3174             (RTL_R16(CPlusCmd) & ASF)) {
3175                 return;
3176         }
3177
3178         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3179             tp->mac_version == RTL_GIGA_MAC_VER_33)
3180                 rtl_ephy_write(ioaddr, 0x19, 0xff64);
3181
3182         if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3183                 rtl_writephy(tp, 0x1f, 0x0000);
3184                 rtl_writephy(tp, MII_BMCR, 0x0000);
3185
3186                 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3187                     tp->mac_version == RTL_GIGA_MAC_VER_33)
3188                         RTL_W32(RxConfig, RTL_R32(RxConfig) | AcceptBroadcast |
3189                                 AcceptMulticast | AcceptMyPhys);
3190                 return;
3191         }
3192
3193         r8168_phy_power_down(tp);
3194
3195         switch (tp->mac_version) {
3196         case RTL_GIGA_MAC_VER_25:
3197         case RTL_GIGA_MAC_VER_26:
3198         case RTL_GIGA_MAC_VER_27:
3199         case RTL_GIGA_MAC_VER_28:
3200         case RTL_GIGA_MAC_VER_31:
3201         case RTL_GIGA_MAC_VER_32:
3202         case RTL_GIGA_MAC_VER_33:
3203                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3204                 break;
3205         }
3206 }
3207
3208 static void r8168_pll_power_up(struct rtl8169_private *tp)
3209 {
3210         void __iomem *ioaddr = tp->mmio_addr;
3211
3212         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3213              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3214              tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3215             r8168dp_check_dash(tp)) {
3216                 return;
3217         }
3218
3219         switch (tp->mac_version) {
3220         case RTL_GIGA_MAC_VER_25:
3221         case RTL_GIGA_MAC_VER_26:
3222         case RTL_GIGA_MAC_VER_27:
3223         case RTL_GIGA_MAC_VER_28:
3224         case RTL_GIGA_MAC_VER_31:
3225         case RTL_GIGA_MAC_VER_32:
3226         case RTL_GIGA_MAC_VER_33:
3227                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3228                 break;
3229         }
3230
3231         r8168_phy_power_up(tp);
3232 }
3233
3234 static void rtl_generic_op(struct rtl8169_private *tp,
3235                            void (*op)(struct rtl8169_private *))
3236 {
3237         if (op)
3238                 op(tp);
3239 }
3240
3241 static void rtl_pll_power_down(struct rtl8169_private *tp)
3242 {
3243         rtl_generic_op(tp, tp->pll_power_ops.down);
3244 }
3245
3246 static void rtl_pll_power_up(struct rtl8169_private *tp)
3247 {
3248         rtl_generic_op(tp, tp->pll_power_ops.up);
3249 }
3250
3251 static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3252 {
3253         struct pll_power_ops *ops = &tp->pll_power_ops;
3254
3255         switch (tp->mac_version) {
3256         case RTL_GIGA_MAC_VER_07:
3257         case RTL_GIGA_MAC_VER_08:
3258         case RTL_GIGA_MAC_VER_09:
3259         case RTL_GIGA_MAC_VER_10:
3260         case RTL_GIGA_MAC_VER_16:
3261         case RTL_GIGA_MAC_VER_29:
3262         case RTL_GIGA_MAC_VER_30:
3263                 ops->down       = r810x_pll_power_down;
3264                 ops->up         = r810x_pll_power_up;
3265                 break;
3266
3267         case RTL_GIGA_MAC_VER_11:
3268         case RTL_GIGA_MAC_VER_12:
3269         case RTL_GIGA_MAC_VER_17:
3270         case RTL_GIGA_MAC_VER_18:
3271         case RTL_GIGA_MAC_VER_19:
3272         case RTL_GIGA_MAC_VER_20:
3273         case RTL_GIGA_MAC_VER_21:
3274         case RTL_GIGA_MAC_VER_22:
3275         case RTL_GIGA_MAC_VER_23:
3276         case RTL_GIGA_MAC_VER_24:
3277         case RTL_GIGA_MAC_VER_25:
3278         case RTL_GIGA_MAC_VER_26:
3279         case RTL_GIGA_MAC_VER_27:
3280         case RTL_GIGA_MAC_VER_28:
3281         case RTL_GIGA_MAC_VER_31:
3282         case RTL_GIGA_MAC_VER_32:
3283         case RTL_GIGA_MAC_VER_33:
3284                 ops->down       = r8168_pll_power_down;
3285                 ops->up         = r8168_pll_power_up;
3286                 break;
3287
3288         default:
3289                 ops->down       = NULL;
3290                 ops->up         = NULL;
3291                 break;
3292         }
3293 }
3294
3295 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
3296 {
3297         rtl_generic_op(tp, tp->jumbo_ops.enable);
3298 }
3299
3300 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
3301 {
3302         rtl_generic_op(tp, tp->jumbo_ops.disable);
3303 }
3304
3305 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
3306 {
3307         void __iomem *ioaddr = tp->mmio_addr;
3308
3309         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3310         RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
3311         rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
3312 }
3313
3314 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
3315 {
3316         void __iomem *ioaddr = tp->mmio_addr;
3317
3318         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3319         RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
3320         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
3321 }
3322
3323 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
3324 {
3325         void __iomem *ioaddr = tp->mmio_addr;
3326
3327         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3328 }
3329
3330 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
3331 {
3332         void __iomem *ioaddr = tp->mmio_addr;
3333
3334         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3335 }
3336
3337 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
3338 {
3339         void __iomem *ioaddr = tp->mmio_addr;
3340         struct pci_dev *pdev = tp->pci_dev;
3341
3342         RTL_W8(MaxTxPacketSize, 0x3f);
3343         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3344         RTL_W8(Config4, RTL_R8(Config4) | 0x01);
3345         pci_write_config_byte(pdev, 0x79, 0x20);
3346 }
3347
3348 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
3349 {
3350         void __iomem *ioaddr = tp->mmio_addr;
3351         struct pci_dev *pdev = tp->pci_dev;
3352
3353         RTL_W8(MaxTxPacketSize, 0x0c);
3354         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3355         RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
3356         pci_write_config_byte(pdev, 0x79, 0x50);
3357 }
3358
3359 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
3360 {
3361         rtl_tx_performance_tweak(tp->pci_dev,
3362                 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3363 }
3364
3365 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
3366 {
3367         rtl_tx_performance_tweak(tp->pci_dev,
3368                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3369 }
3370
3371 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
3372 {
3373         void __iomem *ioaddr = tp->mmio_addr;
3374
3375         r8168b_0_hw_jumbo_enable(tp);
3376
3377         RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
3378 }
3379
3380 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
3381 {
3382         void __iomem *ioaddr = tp->mmio_addr;
3383
3384         r8168b_0_hw_jumbo_disable(tp);
3385
3386         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
3387 }
3388
3389 static void __devinit rtl_init_jumbo_ops(struct rtl8169_private *tp)
3390 {
3391         struct jumbo_ops *ops = &tp->jumbo_ops;
3392
3393         switch (tp->mac_version) {
3394         case RTL_GIGA_MAC_VER_11:
3395                 ops->disable    = r8168b_0_hw_jumbo_disable;
3396                 ops->enable     = r8168b_0_hw_jumbo_enable;
3397                 break;
3398         case RTL_GIGA_MAC_VER_12:
3399         case RTL_GIGA_MAC_VER_17:
3400                 ops->disable    = r8168b_1_hw_jumbo_disable;
3401                 ops->enable     = r8168b_1_hw_jumbo_enable;
3402                 break;
3403         case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
3404         case RTL_GIGA_MAC_VER_19:
3405         case RTL_GIGA_MAC_VER_20:
3406         case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
3407         case RTL_GIGA_MAC_VER_22:
3408         case RTL_GIGA_MAC_VER_23:
3409         case RTL_GIGA_MAC_VER_24:
3410         case RTL_GIGA_MAC_VER_25:
3411         case RTL_GIGA_MAC_VER_26:
3412                 ops->disable    = r8168c_hw_jumbo_disable;
3413                 ops->enable     = r8168c_hw_jumbo_enable;
3414                 break;
3415         case RTL_GIGA_MAC_VER_27:
3416         case RTL_GIGA_MAC_VER_28:
3417                 ops->disable    = r8168dp_hw_jumbo_disable;
3418                 ops->enable     = r8168dp_hw_jumbo_enable;
3419                 break;
3420         case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
3421         case RTL_GIGA_MAC_VER_32:
3422         case RTL_GIGA_MAC_VER_33:
3423                 ops->disable    = r8168e_hw_jumbo_disable;
3424                 ops->enable     = r8168e_hw_jumbo_enable;
3425                 break;
3426
3427         /*
3428          * No action needed for jumbo frames with 8169.
3429          * No jumbo for 810x at all.
3430          */
3431         default:
3432                 ops->disable    = NULL;
3433                 ops->enable     = NULL;
3434                 break;
3435         }
3436 }
3437
3438 static void rtl_hw_reset(struct rtl8169_private *tp)
3439 {
3440         void __iomem *ioaddr = tp->mmio_addr;
3441         int i;
3442
3443         /* Soft reset the chip. */
3444         RTL_W8(ChipCmd, CmdReset);
3445
3446         /* Check that the chip has finished the reset. */
3447         for (i = 0; i < 100; i++) {
3448                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3449                         break;
3450                 msleep_interruptible(1);
3451         }
3452 }
3453
3454 static int __devinit
3455 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3456 {
3457         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
3458         const unsigned int region = cfg->region;
3459         struct rtl8169_private *tp;
3460         struct mii_if_info *mii;
3461         struct net_device *dev;
3462         void __iomem *ioaddr;
3463         int chipset, i;
3464         int rc;
3465
3466         if (netif_msg_drv(&debug)) {
3467                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
3468                        MODULENAME, RTL8169_VERSION);
3469         }
3470
3471         dev = alloc_etherdev(sizeof (*tp));
3472         if (!dev) {
3473                 if (netif_msg_drv(&debug))
3474                         dev_err(&pdev->dev, "unable to alloc new ethernet\n");
3475                 rc = -ENOMEM;
3476                 goto out;
3477         }
3478
3479         SET_NETDEV_DEV(dev, &pdev->dev);
3480         dev->netdev_ops = &rtl8169_netdev_ops;
3481         tp = netdev_priv(dev);
3482         tp->dev = dev;
3483         tp->pci_dev = pdev;
3484         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
3485
3486         mii = &tp->mii;
3487         mii->dev = dev;
3488         mii->mdio_read = rtl_mdio_read;
3489         mii->mdio_write = rtl_mdio_write;
3490         mii->phy_id_mask = 0x1f;
3491         mii->reg_num_mask = 0x1f;
3492         mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3493
3494         /* disable ASPM completely as that cause random device stop working
3495          * problems as well as full system hangs for some PCIe devices users */
3496         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3497                                      PCIE_LINK_STATE_CLKPM);
3498
3499         /* enable device (incl. PCI PM wakeup and hotplug setup) */
3500         rc = pci_enable_device(pdev);
3501         if (rc < 0) {
3502                 netif_err(tp, probe, dev, "enable failure\n");
3503                 goto err_out_free_dev_1;
3504         }
3505
3506         if (pci_set_mwi(pdev) < 0)
3507                 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
3508
3509         /* make sure PCI base addr 1 is MMIO */
3510         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
3511                 netif_err(tp, probe, dev,
3512                           "region #%d not an MMIO resource, aborting\n",
3513                           region);
3514                 rc = -ENODEV;
3515                 goto err_out_mwi_2;
3516         }
3517
3518         /* check for weird/broken PCI region reporting */
3519         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
3520                 netif_err(tp, probe, dev,
3521                           "Invalid PCI region size(s), aborting\n");
3522                 rc = -ENODEV;
3523                 goto err_out_mwi_2;
3524         }
3525
3526         rc = pci_request_regions(pdev, MODULENAME);
3527         if (rc < 0) {
3528                 netif_err(tp, probe, dev, "could not request regions\n");
3529                 goto err_out_mwi_2;
3530         }
3531
3532         tp->cp_cmd = RxChkSum;
3533
3534         if ((sizeof(dma_addr_t) > 4) &&
3535             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
3536                 tp->cp_cmd |= PCIDAC;
3537                 dev->features |= NETIF_F_HIGHDMA;
3538         } else {
3539                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3540                 if (rc < 0) {
3541                         netif_err(tp, probe, dev, "DMA configuration failed\n");
3542                         goto err_out_free_res_3;
3543                 }
3544         }
3545
3546         /* ioremap MMIO region */
3547         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
3548         if (!ioaddr) {
3549                 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
3550                 rc = -EIO;
3551                 goto err_out_free_res_3;
3552         }
3553         tp->mmio_addr = ioaddr;
3554
3555         tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3556         if (!tp->pcie_cap)
3557                 netif_info(tp, probe, dev, "no PCI Express capability\n");
3558
3559         RTL_W16(IntrMask, 0x0000);
3560
3561         rtl_hw_reset(tp);
3562
3563         RTL_W16(IntrStatus, 0xffff);
3564
3565         pci_set_master(pdev);
3566
3567         /* Identify chip attached to board */
3568         rtl8169_get_mac_version(tp, dev, cfg->default_ver);
3569
3570         /*
3571          * Pretend we are using VLANs; This bypasses a nasty bug where
3572          * Interrupts stop flowing on high load on 8110SCd controllers.
3573          */
3574         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3575                 tp->cp_cmd |= RxVlan;
3576
3577         rtl_init_mdio_ops(tp);
3578         rtl_init_pll_power_ops(tp);
3579         rtl_init_jumbo_ops(tp);
3580
3581         rtl8169_print_mac_version(tp);
3582
3583         chipset = tp->mac_version;
3584         tp->txd_version = rtl_chip_infos[chipset].txd_version;
3585
3586         RTL_W8(Cfg9346, Cfg9346_Unlock);
3587         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3588         RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
3589         if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3590                 tp->features |= RTL_FEATURE_WOL;
3591         if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3592                 tp->features |= RTL_FEATURE_WOL;
3593         tp->features |= rtl_try_msi(tp, cfg);
3594         RTL_W8(Cfg9346, Cfg9346_Lock);
3595
3596         if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3597             (RTL_R8(PHYstatus) & TBI_Enable)) {
3598                 tp->set_speed = rtl8169_set_speed_tbi;
3599                 tp->get_settings = rtl8169_gset_tbi;
3600                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3601                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3602                 tp->link_ok = rtl8169_tbi_link_ok;
3603                 tp->do_ioctl = rtl_tbi_ioctl;
3604         } else {
3605                 tp->set_speed = rtl8169_set_speed_xmii;
3606                 tp->get_settings = rtl8169_gset_xmii;
3607                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3608                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3609                 tp->link_ok = rtl8169_xmii_link_ok;
3610                 tp->do_ioctl = rtl_xmii_ioctl;
3611         }
3612
3613         spin_lock_init(&tp->lock);
3614
3615         /* Get MAC address */
3616         for (i = 0; i < MAC_ADDR_LEN; i++)
3617                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
3618         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3619
3620         SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
3621         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3622         dev->irq = pdev->irq;
3623         dev->base_addr = (unsigned long) ioaddr;
3624
3625         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
3626
3627         /* don't enable SG, IP_CSUM and TSO by default - it might not work
3628          * properly for all devices */
3629         dev->features |= NETIF_F_RXCSUM |
3630                 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3631
3632         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3633                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3634         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3635                 NETIF_F_HIGHDMA;
3636
3637         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3638                 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
3639                 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
3640
3641         tp->intr_mask = 0xffff;
3642         tp->hw_start = cfg->hw_start;
3643         tp->intr_event = cfg->intr_event;
3644         tp->napi_event = cfg->napi_event;
3645
3646         tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
3647                 ~(RxBOVF | RxFOVF) : ~0;
3648
3649         init_timer(&tp->timer);
3650         tp->timer.data = (unsigned long) dev;
3651         tp->timer.function = rtl8169_phy_timer;
3652
3653         tp->fw = RTL_FIRMWARE_UNKNOWN;
3654
3655         rc = register_netdev(dev);
3656         if (rc < 0)
3657                 goto err_out_msi_4;
3658
3659         pci_set_drvdata(pdev, dev);
3660
3661         netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
3662                    rtl_chip_infos[chipset].name, dev->base_addr, dev->dev_addr,
3663                    (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
3664         if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
3665                 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
3666                            "tx checksumming: %s]\n",
3667                            rtl_chip_infos[chipset].jumbo_max,
3668                            rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
3669         }
3670
3671         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3672             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3673             tp->mac_version == RTL_GIGA_MAC_VER_31) {
3674                 rtl8168_driver_start(tp);
3675         }
3676
3677         device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
3678
3679         if (pci_dev_run_wake(pdev))
3680                 pm_runtime_put_noidle(&pdev->dev);
3681
3682         netif_carrier_off(dev);
3683
3684 out:
3685         return rc;
3686
3687 err_out_msi_4:
3688         rtl_disable_msi(pdev, tp);
3689         iounmap(ioaddr);
3690 err_out_free_res_3:
3691         pci_release_regions(pdev);
3692 err_out_mwi_2:
3693         pci_clear_mwi(pdev);
3694         pci_disable_device(pdev);
3695 err_out_free_dev_1:
3696         free_netdev(dev);
3697         goto out;
3698 }
3699
3700 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
3701 {
3702         struct net_device *dev = pci_get_drvdata(pdev);
3703         struct rtl8169_private *tp = netdev_priv(dev);
3704
3705         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3706             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3707             tp->mac_version == RTL_GIGA_MAC_VER_31) {
3708                 rtl8168_driver_stop(tp);
3709         }
3710
3711         cancel_delayed_work_sync(&tp->task);
3712
3713         unregister_netdev(dev);
3714
3715         rtl_release_firmware(tp);
3716
3717         if (pci_dev_run_wake(pdev))
3718                 pm_runtime_get_noresume(&pdev->dev);
3719
3720         /* restore original MAC address */
3721         rtl_rar_set(tp, dev->perm_addr);
3722
3723         rtl_disable_msi(pdev, tp);
3724         rtl8169_release_board(pdev, dev, tp->mmio_addr);
3725         pci_set_drvdata(pdev, NULL);
3726 }
3727
3728 static void rtl_request_firmware(struct rtl8169_private *tp)
3729 {
3730         /* Return early if the firmware is already loaded / cached. */
3731         if (IS_ERR(tp->fw)) {
3732                 const char *name;
3733
3734                 name = rtl_lookup_firmware_name(tp);
3735                 if (name) {
3736                         int rc;
3737
3738                         rc = request_firmware(&tp->fw, name, &tp->pci_dev->dev);
3739                         if (rc >= 0)
3740                                 return;
3741
3742                         netif_warn(tp, ifup, tp->dev, "unable to load "
3743                                 "firmware patch %s (%d)\n", name, rc);
3744                 }
3745                 tp->fw = NULL;
3746         }
3747 }
3748
3749 static int rtl8169_open(struct net_device *dev)
3750 {
3751         struct rtl8169_private *tp = netdev_priv(dev);
3752         void __iomem *ioaddr = tp->mmio_addr;
3753         struct pci_dev *pdev = tp->pci_dev;
3754         int retval = -ENOMEM;
3755
3756         pm_runtime_get_sync(&pdev->dev);
3757
3758         /*
3759          * Rx and Tx desscriptors needs 256 bytes alignment.
3760          * dma_alloc_coherent provides more.
3761          */
3762         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
3763                                              &tp->TxPhyAddr, GFP_KERNEL);
3764         if (!tp->TxDescArray)
3765                 goto err_pm_runtime_put;
3766
3767         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
3768                                              &tp->RxPhyAddr, GFP_KERNEL);
3769         if (!tp->RxDescArray)
3770                 goto err_free_tx_0;
3771
3772         retval = rtl8169_init_ring(dev);
3773         if (retval < 0)
3774                 goto err_free_rx_1;
3775
3776         INIT_DELAYED_WORK(&tp->task, NULL);
3777
3778         smp_mb();
3779
3780         rtl_request_firmware(tp);
3781
3782         retval = request_irq(dev->irq, rtl8169_interrupt,
3783                              (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
3784                              dev->name, dev);
3785         if (retval < 0)
3786                 goto err_release_fw_2;
3787
3788         napi_enable(&tp->napi);
3789
3790         rtl8169_init_phy(dev, tp);
3791
3792         rtl8169_set_features(dev, dev->features);
3793
3794         rtl_pll_power_up(tp);
3795
3796         rtl_hw_start(dev);
3797
3798         tp->saved_wolopts = 0;
3799         pm_runtime_put_noidle(&pdev->dev);
3800
3801         rtl8169_check_link_status(dev, tp, ioaddr);
3802 out:
3803         return retval;
3804
3805 err_release_fw_2:
3806         rtl_release_firmware(tp);
3807         rtl8169_rx_clear(tp);
3808 err_free_rx_1:
3809         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
3810                           tp->RxPhyAddr);
3811         tp->RxDescArray = NULL;
3812 err_free_tx_0:
3813         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
3814                           tp->TxPhyAddr);
3815         tp->TxDescArray = NULL;
3816 err_pm_runtime_put:
3817         pm_runtime_put_noidle(&pdev->dev);
3818         goto out;
3819 }
3820
3821 static void rtl8169_hw_reset(struct rtl8169_private *tp)
3822 {
3823         void __iomem *ioaddr = tp->mmio_addr;
3824
3825         /* Disable interrupts */
3826         rtl8169_irq_mask_and_ack(tp);
3827
3828         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3829             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3830             tp->mac_version == RTL_GIGA_MAC_VER_31) {
3831                 while (RTL_R8(TxPoll) & NPQ)
3832                         udelay(20);
3833
3834         }
3835
3836         /* Reset the chipset */
3837         RTL_W8(ChipCmd, CmdReset);
3838
3839         /* PCI commit */
3840         RTL_R8(ChipCmd);
3841 }
3842
3843 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
3844 {
3845         void __iomem *ioaddr = tp->mmio_addr;
3846         u32 cfg = rtl8169_rx_config;
3847
3848         cfg |= (RTL_R32(RxConfig) & RTL_RX_CONFIG_MASK);
3849         RTL_W32(RxConfig, cfg);
3850
3851         /* Set DMA burst size and Interframe Gap Time */
3852         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3853                 (InterFrameGap << TxInterFrameGapShift));
3854 }
3855
3856 static void rtl_hw_start(struct net_device *dev)
3857 {
3858         struct rtl8169_private *tp = netdev_priv(dev);
3859
3860         rtl_hw_reset(tp);
3861
3862         tp->hw_start(dev);
3863
3864         netif_start_queue(dev);
3865 }
3866
3867 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3868                                          void __iomem *ioaddr)
3869 {
3870         /*
3871          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3872          * register to be written before TxDescAddrLow to work.
3873          * Switching from MMIO to I/O access fixes the issue as well.
3874          */
3875         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
3876         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
3877         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
3878         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
3879 }
3880
3881 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
3882 {
3883         u16 cmd;
3884
3885         cmd = RTL_R16(CPlusCmd);
3886         RTL_W16(CPlusCmd, cmd);
3887         return cmd;
3888 }
3889
3890 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
3891 {
3892         /* Low hurts. Let's disable the filtering. */
3893         RTL_W16(RxMaxSize, rx_buf_sz + 1);
3894 }
3895
3896 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
3897 {
3898         static const struct rtl_cfg2_info {
3899                 u32 mac_version;
3900                 u32 clk;
3901                 u32 val;
3902         } cfg2_info [] = {
3903                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
3904                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
3905                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
3906                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3907         };
3908         const struct rtl_cfg2_info *p = cfg2_info;
3909         unsigned int i;
3910         u32 clk;
3911
3912         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
3913         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
3914                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
3915                         RTL_W32(0x7c, p->val);
3916                         break;
3917                 }
3918         }
3919 }
3920
3921 static void rtl_hw_start_8169(struct net_device *dev)
3922 {
3923         struct rtl8169_private *tp = netdev_priv(dev);
3924         void __iomem *ioaddr = tp->mmio_addr;
3925         struct pci_dev *pdev = tp->pci_dev;
3926
3927         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
3928                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
3929                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
3930         }
3931
3932         RTL_W8(Cfg9346, Cfg9346_Unlock);
3933         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
3934             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3935             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
3936             tp->mac_version == RTL_GIGA_MAC_VER_04)
3937                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3938
3939         RTL_W8(EarlyTxThres, NoEarlyTx);
3940
3941         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
3942
3943         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
3944             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3945             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
3946             tp->mac_version == RTL_GIGA_MAC_VER_04)
3947                 rtl_set_rx_tx_config_registers(tp);
3948
3949         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3950
3951         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3952             tp->mac_version == RTL_GIGA_MAC_VER_03) {
3953                 dprintk("Set MAC Reg C+CR Offset 0xE0. "
3954                         "Bit-3 and bit-14 MUST be 1\n");
3955                 tp->cp_cmd |= (1 << 14);
3956         }
3957
3958         RTL_W16(CPlusCmd, tp->cp_cmd);
3959
3960         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
3961
3962         /*
3963          * Undocumented corner. Supposedly:
3964          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3965          */
3966         RTL_W16(IntrMitigate, 0x0000);
3967
3968         rtl_set_rx_tx_desc_registers(tp, ioaddr);
3969
3970         if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
3971             tp->mac_version != RTL_GIGA_MAC_VER_02 &&
3972             tp->mac_version != RTL_GIGA_MAC_VER_03 &&
3973             tp->mac_version != RTL_GIGA_MAC_VER_04) {
3974                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3975                 rtl_set_rx_tx_config_registers(tp);
3976         }
3977
3978         RTL_W8(Cfg9346, Cfg9346_Lock);
3979
3980         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3981         RTL_R8(IntrMask);
3982
3983         RTL_W32(RxMissed, 0);
3984
3985         rtl_set_rx_mode(dev);
3986
3987         /* no early-rx interrupts */
3988         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
3989
3990         /* Enable all known interrupts by setting the interrupt mask. */
3991         RTL_W16(IntrMask, tp->intr_event);
3992 }
3993
3994 static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
3995 {
3996         u32 csi;
3997
3998         csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
3999         rtl_csi_write(ioaddr, 0x070c, csi | bits);
4000 }
4001
4002 static void rtl_csi_access_enable_1(void __iomem *ioaddr)
4003 {
4004         rtl_csi_access_enable(ioaddr, 0x17000000);
4005 }
4006
4007 static void rtl_csi_access_enable_2(void __iomem *ioaddr)
4008 {
4009         rtl_csi_access_enable(ioaddr, 0x27000000);
4010 }
4011
4012 struct ephy_info {
4013         unsigned int offset;
4014         u16 mask;
4015         u16 bits;
4016 };
4017
4018 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
4019 {
4020         u16 w;
4021
4022         while (len-- > 0) {
4023                 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
4024                 rtl_ephy_write(ioaddr, e->offset, w);
4025                 e++;
4026         }
4027 }
4028
4029 static void rtl_disable_clock_request(struct pci_dev *pdev)
4030 {
4031         struct net_device *dev = pci_get_drvdata(pdev);
4032         struct rtl8169_private *tp = netdev_priv(dev);
4033         int cap = tp->pcie_cap;
4034
4035         if (cap) {
4036                 u16 ctl;
4037
4038                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4039                 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
4040                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4041         }
4042 }
4043
4044 static void rtl_enable_clock_request(struct pci_dev *pdev)
4045 {
4046         struct net_device *dev = pci_get_drvdata(pdev);
4047         struct rtl8169_private *tp = netdev_priv(dev);
4048         int cap = tp->pcie_cap;
4049
4050         if (cap) {
4051                 u16 ctl;
4052
4053                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4054                 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
4055                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4056         }
4057 }
4058
4059 #define R8168_CPCMD_QUIRK_MASK (\
4060         EnableBist | \
4061         Mac_dbgo_oe | \
4062         Force_half_dup | \
4063         Force_rxflow_en | \
4064         Force_txflow_en | \
4065         Cxpl_dbg_sel | \
4066         ASF | \
4067         PktCntrDisable | \
4068         Mac_dbgo_sel)
4069
4070 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
4071 {
4072         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4073
4074         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4075
4076         rtl_tx_performance_tweak(pdev,
4077                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4078 }
4079
4080 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
4081 {
4082         rtl_hw_start_8168bb(ioaddr, pdev);
4083
4084         RTL_W8(MaxTxPacketSize, TxPacketMax);
4085
4086         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4087 }
4088
4089 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
4090 {
4091         RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4092
4093         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4094
4095         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4096
4097         rtl_disable_clock_request(pdev);
4098
4099         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4100 }
4101
4102 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
4103 {
4104         static const struct ephy_info e_info_8168cp[] = {
4105                 { 0x01, 0,      0x0001 },
4106                 { 0x02, 0x0800, 0x1000 },
4107                 { 0x03, 0,      0x0042 },
4108                 { 0x06, 0x0080, 0x0000 },
4109                 { 0x07, 0,      0x2000 }
4110         };
4111
4112         rtl_csi_access_enable_2(ioaddr);
4113
4114         rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4115
4116         __rtl_hw_start_8168cp(ioaddr, pdev);
4117 }
4118
4119 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
4120 {
4121         rtl_csi_access_enable_2(ioaddr);
4122
4123         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4124
4125         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4126
4127         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4128 }
4129
4130 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
4131 {
4132         rtl_csi_access_enable_2(ioaddr);
4133
4134         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4135
4136         /* Magic. */
4137         RTL_W8(DBG_REG, 0x20);
4138
4139         RTL_W8(MaxTxPacketSize, TxPacketMax);
4140
4141         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4142
4143         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4144 }
4145
4146 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
4147 {
4148         static const struct ephy_info e_info_8168c_1[] = {
4149                 { 0x02, 0x0800, 0x1000 },
4150                 { 0x03, 0,      0x0002 },
4151                 { 0x06, 0x0080, 0x0000 }
4152         };
4153
4154         rtl_csi_access_enable_2(ioaddr);
4155
4156         RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4157
4158         rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4159
4160         __rtl_hw_start_8168cp(ioaddr, pdev);
4161 }
4162
4163 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
4164 {
4165         static const struct ephy_info e_info_8168c_2[] = {
4166                 { 0x01, 0,      0x0001 },
4167                 { 0x03, 0x0400, 0x0220 }
4168         };
4169
4170         rtl_csi_access_enable_2(ioaddr);
4171
4172         rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4173
4174         __rtl_hw_start_8168cp(ioaddr, pdev);
4175 }
4176
4177 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
4178 {
4179         rtl_hw_start_8168c_2(ioaddr, pdev);
4180 }
4181
4182 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
4183 {
4184         rtl_csi_access_enable_2(ioaddr);
4185
4186         __rtl_hw_start_8168cp(ioaddr, pdev);
4187 }
4188
4189 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
4190 {
4191         rtl_csi_access_enable_2(ioaddr);
4192
4193         rtl_disable_clock_request(pdev);
4194
4195         RTL_W8(MaxTxPacketSize, TxPacketMax);
4196
4197         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4198
4199         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4200 }
4201
4202 static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev)
4203 {
4204         rtl_csi_access_enable_1(ioaddr);
4205
4206         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4207
4208         RTL_W8(MaxTxPacketSize, TxPacketMax);
4209
4210         rtl_disable_clock_request(pdev);
4211 }
4212
4213 static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
4214 {
4215         static const struct ephy_info e_info_8168d_4[] = {
4216                 { 0x0b, ~0,     0x48 },
4217                 { 0x19, 0x20,   0x50 },
4218                 { 0x0c, ~0,     0x20 }
4219         };
4220         int i;
4221
4222         rtl_csi_access_enable_1(ioaddr);
4223
4224         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4225
4226         RTL_W8(MaxTxPacketSize, TxPacketMax);
4227
4228         for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4229                 const struct ephy_info *e = e_info_8168d_4 + i;
4230                 u16 w;
4231
4232                 w = rtl_ephy_read(ioaddr, e->offset);
4233                 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
4234         }
4235
4236         rtl_enable_clock_request(pdev);
4237 }
4238
4239 static void rtl_hw_start_8168e(void __iomem *ioaddr, struct pci_dev *pdev)
4240 {
4241         static const struct ephy_info e_info_8168e[] = {
4242                 { 0x00, 0x0200, 0x0100 },
4243                 { 0x00, 0x0000, 0x0004 },
4244                 { 0x06, 0x0002, 0x0001 },
4245                 { 0x06, 0x0000, 0x0030 },
4246                 { 0x07, 0x0000, 0x2000 },
4247                 { 0x00, 0x0000, 0x0020 },
4248                 { 0x03, 0x5800, 0x2000 },
4249                 { 0x03, 0x0000, 0x0001 },
4250                 { 0x01, 0x0800, 0x1000 },
4251                 { 0x07, 0x0000, 0x4000 },
4252                 { 0x1e, 0x0000, 0x2000 },
4253                 { 0x19, 0xffff, 0xfe6c },
4254                 { 0x0a, 0x0000, 0x0040 }
4255         };
4256
4257         rtl_csi_access_enable_2(ioaddr);
4258
4259         rtl_ephy_init(ioaddr, e_info_8168e, ARRAY_SIZE(e_info_8168e));
4260
4261         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4262
4263         RTL_W8(MaxTxPacketSize, TxPacketMax);
4264
4265         rtl_disable_clock_request(pdev);
4266
4267         /* Reset tx FIFO pointer */
4268         RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
4269         RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
4270
4271         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4272 }
4273
4274 static void rtl_hw_start_8168(struct net_device *dev)
4275 {
4276         struct rtl8169_private *tp = netdev_priv(dev);
4277         void __iomem *ioaddr = tp->mmio_addr;
4278         struct pci_dev *pdev = tp->pci_dev;
4279
4280         RTL_W8(Cfg9346, Cfg9346_Unlock);
4281
4282         RTL_W8(MaxTxPacketSize, TxPacketMax);
4283
4284         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4285
4286         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
4287
4288         RTL_W16(CPlusCmd, tp->cp_cmd);
4289
4290         RTL_W16(IntrMitigate, 0x5151);
4291
4292         /* Work around for RxFIFO overflow. */
4293         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
4294                 tp->intr_event |= RxFIFOOver | PCSTimeout;
4295                 tp->intr_event &= ~RxOverflow;
4296         }
4297
4298         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4299
4300         rtl_set_rx_mode(dev);
4301
4302         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4303                 (InterFrameGap << TxInterFrameGapShift));
4304
4305         RTL_R8(IntrMask);
4306
4307         switch (tp->mac_version) {
4308         case RTL_GIGA_MAC_VER_11:
4309                 rtl_hw_start_8168bb(ioaddr, pdev);
4310                 break;
4311
4312         case RTL_GIGA_MAC_VER_12:
4313         case RTL_GIGA_MAC_VER_17:
4314                 rtl_hw_start_8168bef(ioaddr, pdev);
4315                 break;
4316
4317         case RTL_GIGA_MAC_VER_18:
4318                 rtl_hw_start_8168cp_1(ioaddr, pdev);
4319                 break;
4320
4321         case RTL_GIGA_MAC_VER_19:
4322                 rtl_hw_start_8168c_1(ioaddr, pdev);
4323                 break;
4324
4325         case RTL_GIGA_MAC_VER_20:
4326                 rtl_hw_start_8168c_2(ioaddr, pdev);
4327                 break;
4328
4329         case RTL_GIGA_MAC_VER_21:
4330                 rtl_hw_start_8168c_3(ioaddr, pdev);
4331                 break;
4332
4333         case RTL_GIGA_MAC_VER_22:
4334                 rtl_hw_start_8168c_4(ioaddr, pdev);
4335                 break;
4336
4337         case RTL_GIGA_MAC_VER_23:
4338                 rtl_hw_start_8168cp_2(ioaddr, pdev);
4339                 break;
4340
4341         case RTL_GIGA_MAC_VER_24:
4342                 rtl_hw_start_8168cp_3(ioaddr, pdev);
4343                 break;
4344
4345         case RTL_GIGA_MAC_VER_25:
4346         case RTL_GIGA_MAC_VER_26:
4347         case RTL_GIGA_MAC_VER_27:
4348                 rtl_hw_start_8168d(ioaddr, pdev);
4349                 break;
4350
4351         case RTL_GIGA_MAC_VER_28:
4352                 rtl_hw_start_8168d_4(ioaddr, pdev);
4353                 break;
4354
4355         case RTL_GIGA_MAC_VER_31:
4356                 rtl_hw_start_8168dp(ioaddr, pdev);
4357                 break;
4358
4359         case RTL_GIGA_MAC_VER_32:
4360         case RTL_GIGA_MAC_VER_33:
4361                 rtl_hw_start_8168e(ioaddr, pdev);
4362                 break;
4363
4364         default:
4365                 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
4366                         dev->name, tp->mac_version);
4367                 break;
4368         }
4369
4370         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4371
4372         RTL_W8(Cfg9346, Cfg9346_Lock);
4373
4374         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4375
4376         RTL_W16(IntrMask, tp->intr_event);
4377 }
4378
4379 #define R810X_CPCMD_QUIRK_MASK (\
4380         EnableBist | \
4381         Mac_dbgo_oe | \
4382         Force_half_dup | \
4383         Force_rxflow_en | \
4384         Force_txflow_en | \
4385         Cxpl_dbg_sel | \
4386         ASF | \
4387         PktCntrDisable | \
4388         Mac_dbgo_sel)
4389
4390 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4391 {
4392         static const struct ephy_info e_info_8102e_1[] = {
4393                 { 0x01, 0, 0x6e65 },
4394                 { 0x02, 0, 0x091f },
4395                 { 0x03, 0, 0xc2f9 },
4396                 { 0x06, 0, 0xafb5 },
4397                 { 0x07, 0, 0x0e00 },
4398                 { 0x19, 0, 0xec80 },
4399                 { 0x01, 0, 0x2e65 },
4400                 { 0x01, 0, 0x6e65 }
4401         };
4402         u8 cfg1;
4403
4404         rtl_csi_access_enable_2(ioaddr);
4405
4406         RTL_W8(DBG_REG, FIX_NAK_1);
4407
4408         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4409
4410         RTL_W8(Config1,
4411                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
4412         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4413
4414         cfg1 = RTL_R8(Config1);
4415         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
4416                 RTL_W8(Config1, cfg1 & ~LEDS0);
4417
4418         rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
4419 }
4420
4421 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4422 {
4423         rtl_csi_access_enable_2(ioaddr);
4424
4425         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4426
4427         RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
4428         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4429 }
4430
4431 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
4432 {
4433         rtl_hw_start_8102e_2(ioaddr, pdev);
4434
4435         rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
4436 }
4437
4438 static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4439 {
4440         static const struct ephy_info e_info_8105e_1[] = {
4441                 { 0x07, 0, 0x4000 },
4442                 { 0x19, 0, 0x0200 },
4443                 { 0x19, 0, 0x0020 },
4444                 { 0x1e, 0, 0x2000 },
4445                 { 0x03, 0, 0x0001 },
4446                 { 0x19, 0, 0x0100 },
4447                 { 0x19, 0, 0x0004 },
4448                 { 0x0a, 0, 0x0020 }
4449         };
4450
4451         /* Force LAN exit from ASPM if Rx/Tx are not idle */
4452         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
4453
4454         /* Disable Early Tally Counter */
4455         RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
4456
4457         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4458         RTL_W8(DLLPR, RTL_R8(DLLPR) | PM_SWITCH);
4459
4460         rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
4461 }
4462
4463 static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4464 {
4465         rtl_hw_start_8105e_1(ioaddr, pdev);
4466         rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
4467 }
4468
4469 static void rtl_hw_start_8101(struct net_device *dev)
4470 {
4471         struct rtl8169_private *tp = netdev_priv(dev);
4472         void __iomem *ioaddr = tp->mmio_addr;
4473         struct pci_dev *pdev = tp->pci_dev;
4474
4475         if (tp->mac_version >= RTL_GIGA_MAC_VER_30) {
4476                 tp->intr_event &= ~RxFIFOOver;
4477                 tp->napi_event &= ~RxFIFOOver;
4478         }
4479
4480         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
4481             tp->mac_version == RTL_GIGA_MAC_VER_16) {
4482                 int cap = tp->pcie_cap;
4483
4484                 if (cap) {
4485                         pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
4486                                               PCI_EXP_DEVCTL_NOSNOOP_EN);
4487                 }
4488         }
4489
4490         RTL_W8(Cfg9346, Cfg9346_Unlock);
4491
4492         switch (tp->mac_version) {
4493         case RTL_GIGA_MAC_VER_07:
4494                 rtl_hw_start_8102e_1(ioaddr, pdev);
4495                 break;
4496
4497         case RTL_GIGA_MAC_VER_08:
4498                 rtl_hw_start_8102e_3(ioaddr, pdev);
4499                 break;
4500
4501         case RTL_GIGA_MAC_VER_09:
4502                 rtl_hw_start_8102e_2(ioaddr, pdev);
4503                 break;
4504
4505         case RTL_GIGA_MAC_VER_29:
4506                 rtl_hw_start_8105e_1(ioaddr, pdev);
4507                 break;
4508         case RTL_GIGA_MAC_VER_30:
4509                 rtl_hw_start_8105e_2(ioaddr, pdev);
4510                 break;
4511         }
4512
4513         RTL_W8(Cfg9346, Cfg9346_Lock);
4514
4515         RTL_W8(MaxTxPacketSize, TxPacketMax);
4516
4517         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4518
4519         tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
4520         RTL_W16(CPlusCmd, tp->cp_cmd);
4521
4522         RTL_W16(IntrMitigate, 0x0000);
4523
4524         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4525
4526         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4527         rtl_set_rx_tx_config_registers(tp);
4528
4529         RTL_R8(IntrMask);
4530
4531         rtl_set_rx_mode(dev);
4532
4533         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
4534
4535         RTL_W16(IntrMask, tp->intr_event);
4536 }
4537
4538 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
4539 {
4540         struct rtl8169_private *tp = netdev_priv(dev);
4541
4542         if (new_mtu < ETH_ZLEN ||
4543             new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
4544                 return -EINVAL;
4545
4546         if (new_mtu > ETH_DATA_LEN)
4547                 rtl_hw_jumbo_enable(tp);
4548         else
4549                 rtl_hw_jumbo_disable(tp);
4550
4551         dev->mtu = new_mtu;
4552         netdev_update_features(dev);
4553
4554         return 0;
4555 }
4556
4557 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
4558 {
4559         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
4560         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
4561 }
4562
4563 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
4564                                      void **data_buff, struct RxDesc *desc)
4565 {
4566         dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
4567                          DMA_FROM_DEVICE);
4568
4569         kfree(*data_buff);
4570         *data_buff = NULL;
4571         rtl8169_make_unusable_by_asic(desc);
4572 }
4573
4574 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
4575 {
4576         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
4577
4578         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
4579 }
4580
4581 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
4582                                        u32 rx_buf_sz)
4583 {
4584         desc->addr = cpu_to_le64(mapping);
4585         wmb();
4586         rtl8169_mark_to_asic(desc, rx_buf_sz);
4587 }
4588
4589 static inline void *rtl8169_align(void *data)
4590 {
4591         return (void *)ALIGN((long)data, 16);
4592 }
4593
4594 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
4595                                              struct RxDesc *desc)
4596 {
4597         void *data;
4598         dma_addr_t mapping;
4599         struct device *d = &tp->pci_dev->dev;
4600         struct net_device *dev = tp->dev;
4601         int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
4602
4603         data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
4604         if (!data)
4605                 return NULL;
4606
4607         if (rtl8169_align(data) != data) {
4608                 kfree(data);
4609                 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
4610                 if (!data)
4611                         return NULL;
4612         }
4613
4614         mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
4615                                  DMA_FROM_DEVICE);
4616         if (unlikely(dma_mapping_error(d, mapping))) {
4617                 if (net_ratelimit())
4618                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
4619                 goto err_out;
4620         }
4621
4622         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
4623         return data;
4624
4625 err_out:
4626         kfree(data);
4627         return NULL;
4628 }
4629
4630 static void rtl8169_rx_clear(struct rtl8169_private *tp)
4631 {
4632         unsigned int i;
4633
4634         for (i = 0; i < NUM_RX_DESC; i++) {
4635                 if (tp->Rx_databuff[i]) {
4636                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
4637                                             tp->RxDescArray + i);
4638                 }
4639         }
4640 }
4641
4642 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
4643 {
4644         desc->opts1 |= cpu_to_le32(RingEnd);
4645 }
4646
4647 static int rtl8169_rx_fill(struct rtl8169_private *tp)
4648 {
4649         unsigned int i;
4650
4651         for (i = 0; i < NUM_RX_DESC; i++) {
4652                 void *data;
4653
4654                 if (tp->Rx_databuff[i])
4655                         continue;
4656
4657                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
4658                 if (!data) {
4659                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
4660                         goto err_out;
4661                 }
4662                 tp->Rx_databuff[i] = data;
4663         }
4664
4665         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4666         return 0;
4667
4668 err_out:
4669         rtl8169_rx_clear(tp);
4670         return -ENOMEM;
4671 }
4672
4673 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4674 {
4675         tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
4676 }
4677
4678 static int rtl8169_init_ring(struct net_device *dev)
4679 {
4680         struct rtl8169_private *tp = netdev_priv(dev);
4681
4682         rtl8169_init_ring_indexes(tp);
4683
4684         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
4685         memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
4686
4687         return rtl8169_rx_fill(tp);
4688 }
4689
4690 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
4691                                  struct TxDesc *desc)
4692 {
4693         unsigned int len = tx_skb->len;
4694
4695         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
4696
4697         desc->opts1 = 0x00;
4698         desc->opts2 = 0x00;
4699         desc->addr = 0x00;
4700         tx_skb->len = 0;
4701 }
4702
4703 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4704                                    unsigned int n)
4705 {
4706         unsigned int i;
4707
4708         for (i = 0; i < n; i++) {
4709                 unsigned int entry = (start + i) % NUM_TX_DESC;
4710                 struct ring_info *tx_skb = tp->tx_skb + entry;
4711                 unsigned int len = tx_skb->len;
4712
4713                 if (len) {
4714                         struct sk_buff *skb = tx_skb->skb;
4715
4716                         rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4717                                              tp->TxDescArray + entry);
4718                         if (skb) {
4719                                 tp->dev->stats.tx_dropped++;
4720                                 dev_kfree_skb(skb);
4721                                 tx_skb->skb = NULL;
4722                         }
4723                 }
4724         }
4725 }
4726
4727 static void rtl8169_tx_clear(struct rtl8169_private *tp)
4728 {
4729         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
4730         tp->cur_tx = tp->dirty_tx = 0;
4731 }
4732
4733 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
4734 {
4735         struct rtl8169_private *tp = netdev_priv(dev);
4736
4737         PREPARE_DELAYED_WORK(&tp->task, task);
4738         schedule_delayed_work(&tp->task, 4);
4739 }
4740
4741 static void rtl8169_wait_for_quiescence(struct net_device *dev)
4742 {
4743         struct rtl8169_private *tp = netdev_priv(dev);
4744         void __iomem *ioaddr = tp->mmio_addr;
4745
4746         synchronize_irq(dev->irq);
4747
4748         /* Wait for any pending NAPI task to complete */
4749         napi_disable(&tp->napi);
4750
4751         rtl8169_irq_mask_and_ack(tp);
4752
4753         tp->intr_mask = 0xffff;
4754         RTL_W16(IntrMask, tp->intr_event);
4755         napi_enable(&tp->napi);
4756 }
4757
4758 static void rtl8169_reinit_task(struct work_struct *work)
4759 {
4760         struct rtl8169_private *tp =
4761                 container_of(work, struct rtl8169_private, task.work);
4762         struct net_device *dev = tp->dev;
4763         int ret;
4764
4765         rtnl_lock();
4766
4767         if (!netif_running(dev))
4768                 goto out_unlock;
4769
4770         rtl8169_wait_for_quiescence(dev);
4771         rtl8169_close(dev);
4772
4773         ret = rtl8169_open(dev);
4774         if (unlikely(ret < 0)) {
4775                 if (net_ratelimit())
4776                         netif_err(tp, drv, dev,
4777                                   "reinit failure (status = %d). Rescheduling\n",
4778                                   ret);
4779                 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4780         }
4781
4782 out_unlock:
4783         rtnl_unlock();
4784 }
4785
4786 static void rtl8169_reset_task(struct work_struct *work)
4787 {
4788         struct rtl8169_private *tp =
4789                 container_of(work, struct rtl8169_private, task.work);
4790         struct net_device *dev = tp->dev;
4791         int i;
4792
4793         rtnl_lock();
4794
4795         if (!netif_running(dev))
4796                 goto out_unlock;
4797
4798         rtl8169_wait_for_quiescence(dev);
4799
4800         for (i = 0; i < NUM_RX_DESC; i++)
4801                 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
4802
4803         rtl8169_tx_clear(tp);
4804
4805         rtl8169_init_ring_indexes(tp);
4806         rtl_hw_start(dev);
4807         netif_wake_queue(dev);
4808         rtl8169_check_link_status(dev, tp, tp->mmio_addr);
4809
4810 out_unlock:
4811         rtnl_unlock();
4812 }
4813
4814 static void rtl8169_tx_timeout(struct net_device *dev)
4815 {
4816         struct rtl8169_private *tp = netdev_priv(dev);
4817
4818         rtl8169_hw_reset(tp);
4819
4820         /* Let's wait a bit while any (async) irq lands on */
4821         rtl8169_schedule_work(dev, rtl8169_reset_task);
4822 }
4823
4824 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4825                               u32 *opts)
4826 {
4827         struct skb_shared_info *info = skb_shinfo(skb);
4828         unsigned int cur_frag, entry;
4829         struct TxDesc * uninitialized_var(txd);
4830         struct device *d = &tp->pci_dev->dev;
4831
4832         entry = tp->cur_tx;
4833         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4834                 skb_frag_t *frag = info->frags + cur_frag;
4835                 dma_addr_t mapping;
4836                 u32 status, len;
4837                 void *addr;
4838
4839                 entry = (entry + 1) % NUM_TX_DESC;
4840
4841                 txd = tp->TxDescArray + entry;
4842                 len = frag->size;
4843                 addr = ((void *) page_address(frag->page)) + frag->page_offset;
4844                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
4845                 if (unlikely(dma_mapping_error(d, mapping))) {
4846                         if (net_ratelimit())
4847                                 netif_err(tp, drv, tp->dev,
4848                                           "Failed to map TX fragments DMA!\n");
4849                         goto err_out;
4850                 }
4851
4852                 /* Anti gcc 2.95.3 bugware (sic) */
4853                 status = opts[0] | len |
4854                         (RingEnd * !((entry + 1) % NUM_TX_DESC));
4855
4856                 txd->opts1 = cpu_to_le32(status);
4857                 txd->opts2 = cpu_to_le32(opts[1]);
4858                 txd->addr = cpu_to_le64(mapping);
4859
4860                 tp->tx_skb[entry].len = len;
4861         }
4862
4863         if (cur_frag) {
4864                 tp->tx_skb[entry].skb = skb;
4865                 txd->opts1 |= cpu_to_le32(LastFrag);
4866         }
4867
4868         return cur_frag;
4869
4870 err_out:
4871         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4872         return -EIO;
4873 }
4874
4875 static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
4876                                     struct sk_buff *skb, u32 *opts)
4877 {
4878         const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
4879         u32 mss = skb_shinfo(skb)->gso_size;
4880         int offset = info->opts_offset;
4881
4882         if (mss) {
4883                 opts[0] |= TD_LSO;
4884                 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
4885         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4886                 const struct iphdr *ip = ip_hdr(skb);
4887
4888                 if (ip->protocol == IPPROTO_TCP)
4889                         opts[offset] |= info->checksum.tcp;
4890                 else if (ip->protocol == IPPROTO_UDP)
4891                         opts[offset] |= info->checksum.udp;
4892                 else
4893                         WARN_ON_ONCE(1);
4894         }
4895 }
4896
4897 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4898                                       struct net_device *dev)
4899 {
4900         struct rtl8169_private *tp = netdev_priv(dev);
4901         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
4902         struct TxDesc *txd = tp->TxDescArray + entry;
4903         void __iomem *ioaddr = tp->mmio_addr;
4904         struct device *d = &tp->pci_dev->dev;
4905         dma_addr_t mapping;
4906         u32 status, len;
4907         u32 opts[2];
4908         int frags;
4909
4910         if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
4911                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
4912                 goto err_stop_0;
4913         }
4914
4915         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
4916                 goto err_stop_0;
4917
4918         len = skb_headlen(skb);
4919         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
4920         if (unlikely(dma_mapping_error(d, mapping))) {
4921                 if (net_ratelimit())
4922                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
4923                 goto err_dma_0;
4924         }
4925
4926         tp->tx_skb[entry].len = len;
4927         txd->addr = cpu_to_le64(mapping);
4928
4929         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
4930         opts[0] = DescOwn;
4931
4932         rtl8169_tso_csum(tp, skb, opts);
4933
4934         frags = rtl8169_xmit_frags(tp, skb, opts);
4935         if (frags < 0)
4936                 goto err_dma_1;
4937         else if (frags)
4938                 opts[0] |= FirstFrag;
4939         else {
4940                 opts[0] |= FirstFrag | LastFrag;
4941                 tp->tx_skb[entry].skb = skb;
4942         }
4943
4944         txd->opts2 = cpu_to_le32(opts[1]);
4945
4946         wmb();
4947
4948         /* Anti gcc 2.95.3 bugware (sic) */
4949         status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4950         txd->opts1 = cpu_to_le32(status);
4951
4952         tp->cur_tx += frags + 1;
4953
4954         wmb();
4955
4956         RTL_W8(TxPoll, NPQ);
4957
4958         if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
4959                 netif_stop_queue(dev);
4960                 smp_mb();
4961                 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
4962                         netif_wake_queue(dev);
4963         }
4964
4965         return NETDEV_TX_OK;
4966
4967 err_dma_1:
4968         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
4969 err_dma_0:
4970         dev_kfree_skb(skb);
4971         dev->stats.tx_dropped++;
4972         return NETDEV_TX_OK;
4973
4974 err_stop_0:
4975         netif_stop_queue(dev);
4976         dev->stats.tx_dropped++;
4977         return NETDEV_TX_BUSY;
4978 }
4979
4980 static void rtl8169_pcierr_interrupt(struct net_device *dev)
4981 {
4982         struct rtl8169_private *tp = netdev_priv(dev);
4983         struct pci_dev *pdev = tp->pci_dev;
4984         u16 pci_status, pci_cmd;
4985
4986         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4987         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
4988
4989         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
4990                   pci_cmd, pci_status);
4991
4992         /*
4993          * The recovery sequence below admits a very elaborated explanation:
4994          * - it seems to work;
4995          * - I did not see what else could be done;
4996          * - it makes iop3xx happy.
4997          *
4998          * Feel free to adjust to your needs.
4999          */
5000         if (pdev->broken_parity_status)
5001                 pci_cmd &= ~PCI_COMMAND_PARITY;
5002         else
5003                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5004
5005         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
5006
5007         pci_write_config_word(pdev, PCI_STATUS,
5008                 pci_status & (PCI_STATUS_DETECTED_PARITY |
5009                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5010                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5011
5012         /* The infamous DAC f*ckup only happens at boot time */
5013         if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
5014                 void __iomem *ioaddr = tp->mmio_addr;
5015
5016                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
5017                 tp->cp_cmd &= ~PCIDAC;
5018                 RTL_W16(CPlusCmd, tp->cp_cmd);
5019                 dev->features &= ~NETIF_F_HIGHDMA;
5020         }
5021
5022         rtl8169_hw_reset(tp);
5023
5024         rtl8169_schedule_work(dev, rtl8169_reinit_task);
5025 }
5026
5027 static void rtl8169_tx_interrupt(struct net_device *dev,
5028                                  struct rtl8169_private *tp,
5029                                  void __iomem *ioaddr)
5030 {
5031         unsigned int dirty_tx, tx_left;
5032
5033         dirty_tx = tp->dirty_tx;
5034         smp_rmb();
5035         tx_left = tp->cur_tx - dirty_tx;
5036
5037         while (tx_left > 0) {
5038                 unsigned int entry = dirty_tx % NUM_TX_DESC;
5039                 struct ring_info *tx_skb = tp->tx_skb + entry;
5040                 u32 status;
5041
5042                 rmb();
5043                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5044                 if (status & DescOwn)
5045                         break;
5046
5047                 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5048                                      tp->TxDescArray + entry);
5049                 if (status & LastFrag) {
5050                         dev->stats.tx_packets++;
5051                         dev->stats.tx_bytes += tx_skb->skb->len;
5052                         dev_kfree_skb(tx_skb->skb);
5053                         tx_skb->skb = NULL;
5054                 }
5055                 dirty_tx++;
5056                 tx_left--;
5057         }
5058
5059         if (tp->dirty_tx != dirty_tx) {
5060                 tp->dirty_tx = dirty_tx;
5061                 smp_mb();
5062                 if (netif_queue_stopped(dev) &&
5063                     (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
5064                         netif_wake_queue(dev);
5065                 }
5066                 /*
5067                  * 8168 hack: TxPoll requests are lost when the Tx packets are
5068                  * too close. Let's kick an extra TxPoll request when a burst
5069                  * of start_xmit activity is detected (if it is not detected,
5070                  * it is slow enough). -- FR
5071                  */
5072                 if (tp->cur_tx != dirty_tx)
5073                         RTL_W8(TxPoll, NPQ);
5074         }
5075 }
5076
5077 static inline int rtl8169_fragmented_frame(u32 status)
5078 {
5079         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
5080 }
5081
5082 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
5083 {
5084         u32 status = opts1 & RxProtoMask;
5085
5086         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
5087             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
5088                 skb->ip_summed = CHECKSUM_UNNECESSARY;
5089         else
5090                 skb_checksum_none_assert(skb);
5091 }
5092
5093 static struct sk_buff *rtl8169_try_rx_copy(void *data,
5094                                            struct rtl8169_private *tp,
5095                                            int pkt_size,
5096                                            dma_addr_t addr)
5097 {
5098         struct sk_buff *skb;
5099         struct device *d = &tp->pci_dev->dev;
5100
5101         data = rtl8169_align(data);
5102         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
5103         prefetch(data);
5104         skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
5105         if (skb)
5106                 memcpy(skb->data, data, pkt_size);
5107         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
5108
5109         return skb;
5110 }
5111
5112 static int rtl8169_rx_interrupt(struct net_device *dev,
5113                                 struct rtl8169_private *tp,
5114                                 void __iomem *ioaddr, u32 budget)
5115 {
5116         unsigned int cur_rx, rx_left;
5117         unsigned int count;
5118
5119         cur_rx = tp->cur_rx;
5120         rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
5121         rx_left = min(rx_left, budget);
5122
5123         for (; rx_left > 0; rx_left--, cur_rx++) {
5124                 unsigned int entry = cur_rx % NUM_RX_DESC;
5125                 struct RxDesc *desc = tp->RxDescArray + entry;
5126                 u32 status;
5127
5128                 rmb();
5129                 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
5130
5131                 if (status & DescOwn)
5132                         break;
5133                 if (unlikely(status & RxRES)) {
5134                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
5135                                    status);
5136                         dev->stats.rx_errors++;
5137                         if (status & (RxRWT | RxRUNT))
5138                                 dev->stats.rx_length_errors++;
5139                         if (status & RxCRC)
5140                                 dev->stats.rx_crc_errors++;
5141                         if (status & RxFOVF) {
5142                                 rtl8169_schedule_work(dev, rtl8169_reset_task);
5143                                 dev->stats.rx_fifo_errors++;
5144                         }
5145                         rtl8169_mark_to_asic(desc, rx_buf_sz);
5146                 } else {
5147                         struct sk_buff *skb;
5148                         dma_addr_t addr = le64_to_cpu(desc->addr);
5149                         int pkt_size = (status & 0x00003fff) - 4;
5150
5151                         /*
5152                          * The driver does not support incoming fragmented
5153                          * frames. They are seen as a symptom of over-mtu
5154                          * sized frames.
5155                          */
5156                         if (unlikely(rtl8169_fragmented_frame(status))) {
5157                                 dev->stats.rx_dropped++;
5158                                 dev->stats.rx_length_errors++;
5159                                 rtl8169_mark_to_asic(desc, rx_buf_sz);
5160                                 continue;
5161                         }
5162
5163                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
5164                                                   tp, pkt_size, addr);
5165                         rtl8169_mark_to_asic(desc, rx_buf_sz);
5166                         if (!skb) {
5167                                 dev->stats.rx_dropped++;
5168                                 continue;
5169                         }
5170
5171                         rtl8169_rx_csum(skb, status);
5172                         skb_put(skb, pkt_size);
5173                         skb->protocol = eth_type_trans(skb, dev);
5174
5175                         rtl8169_rx_vlan_tag(desc, skb);
5176
5177                         napi_gro_receive(&tp->napi, skb);
5178
5179                         dev->stats.rx_bytes += pkt_size;
5180                         dev->stats.rx_packets++;
5181                 }
5182
5183                 /* Work around for AMD plateform. */
5184                 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
5185                     (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
5186                         desc->opts2 = 0;
5187                         cur_rx++;
5188                 }
5189         }
5190
5191         count = cur_rx - tp->cur_rx;
5192         tp->cur_rx = cur_rx;
5193
5194         tp->dirty_rx += count;
5195
5196         return count;
5197 }
5198
5199 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
5200 {
5201         struct net_device *dev = dev_instance;
5202         struct rtl8169_private *tp = netdev_priv(dev);
5203         void __iomem *ioaddr = tp->mmio_addr;
5204         int handled = 0;
5205         int status;
5206
5207         /* loop handling interrupts until we have no new ones or
5208          * we hit a invalid/hotplug case.
5209          */
5210         status = RTL_R16(IntrStatus);
5211         while (status && status != 0xffff) {
5212                 status &= tp->intr_event;
5213                 if (!status)
5214                         break;
5215
5216                 handled = 1;
5217
5218                 /* Handle all of the error cases first. These will reset
5219                  * the chip, so just exit the loop.
5220                  */
5221                 if (unlikely(!netif_running(dev))) {
5222                         rtl8169_asic_down(tp);
5223                         break;
5224                 }
5225
5226                 if (unlikely(status & RxFIFOOver)) {
5227                         switch (tp->mac_version) {
5228                         /* Work around for rx fifo overflow */
5229                         case RTL_GIGA_MAC_VER_11:
5230                                 netif_stop_queue(dev);
5231                                 rtl8169_tx_timeout(dev);
5232                                 goto done;
5233                         default:
5234                                 break;
5235                         }
5236                 }
5237
5238                 if (unlikely(status & SYSErr)) {
5239                         rtl8169_pcierr_interrupt(dev);
5240                         break;
5241                 }
5242
5243                 if (status & LinkChg)
5244                         __rtl8169_check_link_status(dev, tp, ioaddr, true);
5245
5246                 /* We need to see the lastest version of tp->intr_mask to
5247                  * avoid ignoring an MSI interrupt and having to wait for
5248                  * another event which may never come.
5249                  */
5250                 smp_rmb();
5251                 if (status & tp->intr_mask & tp->napi_event) {
5252                         RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
5253                         tp->intr_mask = ~tp->napi_event;
5254
5255                         if (likely(napi_schedule_prep(&tp->napi)))
5256                                 __napi_schedule(&tp->napi);
5257                         else
5258                                 netif_info(tp, intr, dev,
5259                                            "interrupt %04x in poll\n", status);
5260                 }
5261
5262                 /* We only get a new MSI interrupt when all active irq
5263                  * sources on the chip have been acknowledged. So, ack
5264                  * everything we've seen and check if new sources have become
5265                  * active to avoid blocking all interrupts from the chip.
5266                  */
5267                 RTL_W16(IntrStatus,
5268                         (status & RxFIFOOver) ? (status | RxOverflow) : status);
5269                 status = RTL_R16(IntrStatus);
5270         }
5271 done:
5272         return IRQ_RETVAL(handled);
5273 }
5274
5275 static int rtl8169_poll(struct napi_struct *napi, int budget)
5276 {
5277         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5278         struct net_device *dev = tp->dev;
5279         void __iomem *ioaddr = tp->mmio_addr;
5280         int work_done;
5281
5282         work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
5283         rtl8169_tx_interrupt(dev, tp, ioaddr);
5284
5285         if (work_done < budget) {
5286                 napi_complete(napi);
5287
5288                 /* We need for force the visibility of tp->intr_mask
5289                  * for other CPUs, as we can loose an MSI interrupt
5290                  * and potentially wait for a retransmit timeout if we don't.
5291                  * The posted write to IntrMask is safe, as it will
5292                  * eventually make it to the chip and we won't loose anything
5293                  * until it does.
5294                  */
5295                 tp->intr_mask = 0xffff;
5296                 wmb();
5297                 RTL_W16(IntrMask, tp->intr_event);
5298         }
5299
5300         return work_done;
5301 }
5302
5303 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
5304 {
5305         struct rtl8169_private *tp = netdev_priv(dev);
5306
5307         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5308                 return;
5309
5310         dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
5311         RTL_W32(RxMissed, 0);
5312 }
5313
5314 static void rtl8169_down(struct net_device *dev)
5315 {
5316         struct rtl8169_private *tp = netdev_priv(dev);
5317         void __iomem *ioaddr = tp->mmio_addr;
5318
5319         del_timer_sync(&tp->timer);
5320
5321         netif_stop_queue(dev);
5322
5323         napi_disable(&tp->napi);
5324
5325         spin_lock_irq(&tp->lock);
5326
5327         rtl8169_asic_down(tp);
5328         /*
5329          * At this point device interrupts can not be enabled in any function,
5330          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
5331          * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
5332          */
5333         rtl8169_rx_missed(dev, ioaddr);
5334
5335         spin_unlock_irq(&tp->lock);
5336
5337         synchronize_irq(dev->irq);
5338
5339         /* Give a racing hard_start_xmit a few cycles to complete. */
5340         synchronize_sched();  /* FIXME: should this be synchronize_irq()? */
5341
5342         rtl8169_tx_clear(tp);
5343
5344         rtl8169_rx_clear(tp);
5345
5346         rtl_pll_power_down(tp);
5347 }
5348
5349 static int rtl8169_close(struct net_device *dev)
5350 {
5351         struct rtl8169_private *tp = netdev_priv(dev);
5352         struct pci_dev *pdev = tp->pci_dev;
5353
5354         pm_runtime_get_sync(&pdev->dev);
5355
5356         /* Update counters before going down */
5357         rtl8169_update_counters(dev);
5358
5359         rtl8169_down(dev);
5360
5361         free_irq(dev->irq, dev);
5362
5363         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5364                           tp->RxPhyAddr);
5365         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5366                           tp->TxPhyAddr);
5367         tp->TxDescArray = NULL;
5368         tp->RxDescArray = NULL;
5369
5370         pm_runtime_put_sync(&pdev->dev);
5371
5372         return 0;
5373 }
5374
5375 static void rtl_set_rx_mode(struct net_device *dev)
5376 {
5377         struct rtl8169_private *tp = netdev_priv(dev);
5378         void __iomem *ioaddr = tp->mmio_addr;
5379         unsigned long flags;
5380         u32 mc_filter[2];       /* Multicast hash filter */
5381         int rx_mode;
5382         u32 tmp = 0;
5383
5384         if (dev->flags & IFF_PROMISC) {
5385                 /* Unconditionally log net taps. */
5386                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
5387                 rx_mode =
5388                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5389                     AcceptAllPhys;
5390                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5391         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
5392                    (dev->flags & IFF_ALLMULTI)) {
5393                 /* Too many to filter perfectly -- accept all multicasts. */
5394                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5395                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5396         } else {
5397                 struct netdev_hw_addr *ha;
5398
5399                 rx_mode = AcceptBroadcast | AcceptMyPhys;
5400                 mc_filter[1] = mc_filter[0] = 0;
5401                 netdev_for_each_mc_addr(ha, dev) {
5402                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
5403                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5404                         rx_mode |= AcceptMulticast;
5405                 }
5406         }
5407
5408         spin_lock_irqsave(&tp->lock, flags);
5409
5410         tmp = rtl8169_rx_config | rx_mode |
5411               (RTL_R32(RxConfig) & RTL_RX_CONFIG_MASK);
5412
5413         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
5414                 u32 data = mc_filter[0];
5415
5416                 mc_filter[0] = swab32(mc_filter[1]);
5417                 mc_filter[1] = swab32(data);
5418         }
5419
5420         RTL_W32(MAR0 + 4, mc_filter[1]);
5421         RTL_W32(MAR0 + 0, mc_filter[0]);
5422
5423         RTL_W32(RxConfig, tmp);
5424
5425         spin_unlock_irqrestore(&tp->lock, flags);
5426 }
5427
5428 /**
5429  *  rtl8169_get_stats - Get rtl8169 read/write statistics
5430  *  @dev: The Ethernet Device to get statistics for
5431  *
5432  *  Get TX/RX statistics for rtl8169
5433  */
5434 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
5435 {
5436         struct rtl8169_private *tp = netdev_priv(dev);
5437         void __iomem *ioaddr = tp->mmio_addr;
5438         unsigned long flags;
5439
5440         if (netif_running(dev)) {
5441                 spin_lock_irqsave(&tp->lock, flags);
5442                 rtl8169_rx_missed(dev, ioaddr);
5443                 spin_unlock_irqrestore(&tp->lock, flags);
5444         }
5445
5446         return &dev->stats;
5447 }
5448
5449 static void rtl8169_net_suspend(struct net_device *dev)
5450 {
5451         struct rtl8169_private *tp = netdev_priv(dev);
5452
5453         if (!netif_running(dev))
5454                 return;
5455
5456         rtl_pll_power_down(tp);
5457
5458         netif_device_detach(dev);
5459         netif_stop_queue(dev);
5460 }
5461
5462 #ifdef CONFIG_PM
5463
5464 static int rtl8169_suspend(struct device *device)
5465 {
5466         struct pci_dev *pdev = to_pci_dev(device);
5467         struct net_device *dev = pci_get_drvdata(pdev);
5468
5469         rtl8169_net_suspend(dev);
5470
5471         return 0;
5472 }
5473
5474 static void __rtl8169_resume(struct net_device *dev)
5475 {
5476         struct rtl8169_private *tp = netdev_priv(dev);
5477
5478         netif_device_attach(dev);
5479
5480         rtl_pll_power_up(tp);
5481
5482         rtl8169_schedule_work(dev, rtl8169_reset_task);
5483 }
5484
5485 static int rtl8169_resume(struct device *device)
5486 {
5487         struct pci_dev *pdev = to_pci_dev(device);
5488         struct net_device *dev = pci_get_drvdata(pdev);
5489         struct rtl8169_private *tp = netdev_priv(dev);
5490
5491         rtl8169_init_phy(dev, tp);
5492
5493         if (netif_running(dev))
5494                 __rtl8169_resume(dev);
5495
5496         return 0;
5497 }
5498
5499 static int rtl8169_runtime_suspend(struct device *device)
5500 {
5501         struct pci_dev *pdev = to_pci_dev(device);
5502         struct net_device *dev = pci_get_drvdata(pdev);
5503         struct rtl8169_private *tp = netdev_priv(dev);
5504
5505         if (!tp->TxDescArray)
5506                 return 0;
5507
5508         spin_lock_irq(&tp->lock);
5509         tp->saved_wolopts = __rtl8169_get_wol(tp);
5510         __rtl8169_set_wol(tp, WAKE_ANY);
5511         spin_unlock_irq(&tp->lock);
5512
5513         rtl8169_net_suspend(dev);
5514
5515         return 0;
5516 }
5517
5518 static int rtl8169_runtime_resume(struct device *device)
5519 {
5520         struct pci_dev *pdev = to_pci_dev(device);
5521         struct net_device *dev = pci_get_drvdata(pdev);
5522         struct rtl8169_private *tp = netdev_priv(dev);
5523
5524         if (!tp->TxDescArray)
5525                 return 0;
5526
5527         spin_lock_irq(&tp->lock);
5528         __rtl8169_set_wol(tp, tp->saved_wolopts);
5529         tp->saved_wolopts = 0;
5530         spin_unlock_irq(&tp->lock);
5531
5532         rtl8169_init_phy(dev, tp);
5533
5534         __rtl8169_resume(dev);
5535
5536         return 0;
5537 }
5538
5539 static int rtl8169_runtime_idle(struct device *device)
5540 {
5541         struct pci_dev *pdev = to_pci_dev(device);
5542         struct net_device *dev = pci_get_drvdata(pdev);
5543         struct rtl8169_private *tp = netdev_priv(dev);
5544
5545         return tp->TxDescArray ? -EBUSY : 0;
5546 }
5547
5548 static const struct dev_pm_ops rtl8169_pm_ops = {
5549         .suspend                = rtl8169_suspend,
5550         .resume                 = rtl8169_resume,
5551         .freeze                 = rtl8169_suspend,
5552         .thaw                   = rtl8169_resume,
5553         .poweroff               = rtl8169_suspend,
5554         .restore                = rtl8169_resume,
5555         .runtime_suspend        = rtl8169_runtime_suspend,
5556         .runtime_resume         = rtl8169_runtime_resume,
5557         .runtime_idle           = rtl8169_runtime_idle,
5558 };
5559
5560 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
5561
5562 #else /* !CONFIG_PM */
5563
5564 #define RTL8169_PM_OPS  NULL
5565
5566 #endif /* !CONFIG_PM */
5567
5568 static void rtl_shutdown(struct pci_dev *pdev)
5569 {
5570         struct net_device *dev = pci_get_drvdata(pdev);
5571         struct rtl8169_private *tp = netdev_priv(dev);
5572         void __iomem *ioaddr = tp->mmio_addr;
5573         struct device *d = &pdev->dev;
5574
5575         pm_runtime_get_sync(d);
5576
5577         rtl8169_net_suspend(dev);
5578
5579         /* Restore original MAC address */
5580         rtl_rar_set(tp, dev->perm_addr);
5581
5582         spin_lock_irq(&tp->lock);
5583
5584         rtl8169_asic_down(tp);
5585
5586         spin_unlock_irq(&tp->lock);
5587
5588         if (system_state == SYSTEM_POWER_OFF) {
5589                 /* WoL fails with 8168b when the receiver is disabled. */
5590                 if ((tp->mac_version == RTL_GIGA_MAC_VER_11 ||
5591                      tp->mac_version == RTL_GIGA_MAC_VER_12 ||
5592                      tp->mac_version == RTL_GIGA_MAC_VER_17) &&
5593                     (tp->features & RTL_FEATURE_WOL)) {
5594                         pci_clear_master(pdev);
5595
5596                         RTL_W8(ChipCmd, CmdRxEnb);
5597                         /* PCI commit */
5598                         RTL_R8(ChipCmd);
5599                 }
5600
5601                 pci_wake_from_d3(pdev, true);
5602                 pci_set_power_state(pdev, PCI_D3hot);
5603         }
5604
5605         pm_runtime_put_noidle(d);
5606 }
5607
5608 static struct pci_driver rtl8169_pci_driver = {
5609         .name           = MODULENAME,
5610         .id_table       = rtl8169_pci_tbl,
5611         .probe          = rtl8169_init_one,
5612         .remove         = __devexit_p(rtl8169_remove_one),
5613         .shutdown       = rtl_shutdown,
5614         .driver.pm      = RTL8169_PM_OPS,
5615 };
5616
5617 static int __init rtl8169_init_module(void)
5618 {
5619         return pci_register_driver(&rtl8169_pci_driver);
5620 }
5621
5622 static void __exit rtl8169_cleanup_module(void)
5623 {
5624         pci_unregister_driver(&rtl8169_pci_driver);
5625 }
5626
5627 module_init(rtl8169_init_module);
5628 module_exit(rtl8169_cleanup_module);