2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/firmware.h>
29 #include <linux/pci-aspm.h>
30 #include <linux/prefetch.h>
32 #include <asm/system.h>
36 #define RTL8169_VERSION "2.3LK-NAPI"
37 #define MODULENAME "r8169"
38 #define PFX MODULENAME ": "
40 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
41 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
42 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
43 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
44 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
45 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
48 #define assert(expr) \
50 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
51 #expr,__FILE__,__func__,__LINE__); \
53 #define dprintk(fmt, args...) \
54 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
56 #define assert(expr) do {} while (0)
57 #define dprintk(fmt, args...) do {} while (0)
58 #endif /* RTL8169_DEBUG */
60 #define R8169_MSG_DEFAULT \
61 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
63 #define TX_BUFFS_AVAIL(tp) \
64 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
66 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
67 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
68 static const int multicast_filter_limit = 32;
70 /* MAC address length */
71 #define MAC_ADDR_LEN 6
73 #define MAX_READ_REQUEST_SHIFT 12
74 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
75 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
76 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
78 #define R8169_REGS_SIZE 256
79 #define R8169_NAPI_WEIGHT 64
80 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
81 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
82 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
83 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
84 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
86 #define RTL8169_TX_TIMEOUT (6*HZ)
87 #define RTL8169_PHY_TIMEOUT (10*HZ)
89 #define RTL_EEPROM_SIG cpu_to_le32(0x8129)
90 #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
91 #define RTL_EEPROM_SIG_ADDR 0x0000
93 /* write/read MMIO register */
94 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
95 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
96 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
97 #define RTL_R8(reg) readb (ioaddr + (reg))
98 #define RTL_R16(reg) readw (ioaddr + (reg))
99 #define RTL_R32(reg) readl (ioaddr + (reg))
102 RTL_GIGA_MAC_VER_01 = 0,
136 RTL_GIGA_MAC_NONE = 0xff,
139 enum rtl_tx_desc_version {
144 #define _R(NAME,TD,FW) \
145 { .name = NAME, .txd_version = TD, .fw_name = FW }
147 static const struct {
149 enum rtl_tx_desc_version txd_version;
151 } rtl_chip_infos[] = {
153 [RTL_GIGA_MAC_VER_01] =
154 _R("RTL8169", RTL_TD_0, NULL),
155 [RTL_GIGA_MAC_VER_02] =
156 _R("RTL8169s", RTL_TD_0, NULL),
157 [RTL_GIGA_MAC_VER_03] =
158 _R("RTL8110s", RTL_TD_0, NULL),
159 [RTL_GIGA_MAC_VER_04] =
160 _R("RTL8169sb/8110sb", RTL_TD_0, NULL),
161 [RTL_GIGA_MAC_VER_05] =
162 _R("RTL8169sc/8110sc", RTL_TD_0, NULL),
163 [RTL_GIGA_MAC_VER_06] =
164 _R("RTL8169sc/8110sc", RTL_TD_0, NULL),
166 [RTL_GIGA_MAC_VER_07] =
167 _R("RTL8102e", RTL_TD_1, NULL),
168 [RTL_GIGA_MAC_VER_08] =
169 _R("RTL8102e", RTL_TD_1, NULL),
170 [RTL_GIGA_MAC_VER_09] =
171 _R("RTL8102e", RTL_TD_1, NULL),
172 [RTL_GIGA_MAC_VER_10] =
173 _R("RTL8101e", RTL_TD_0, NULL),
174 [RTL_GIGA_MAC_VER_11] =
175 _R("RTL8168b/8111b", RTL_TD_0, NULL),
176 [RTL_GIGA_MAC_VER_12] =
177 _R("RTL8168b/8111b", RTL_TD_0, NULL),
178 [RTL_GIGA_MAC_VER_13] =
179 _R("RTL8101e", RTL_TD_0, NULL),
180 [RTL_GIGA_MAC_VER_14] =
181 _R("RTL8100e", RTL_TD_0, NULL),
182 [RTL_GIGA_MAC_VER_15] =
183 _R("RTL8100e", RTL_TD_0, NULL),
184 [RTL_GIGA_MAC_VER_16] =
185 _R("RTL8101e", RTL_TD_0, NULL),
186 [RTL_GIGA_MAC_VER_17] =
187 _R("RTL8168b/8111b", RTL_TD_0, NULL),
188 [RTL_GIGA_MAC_VER_18] =
189 _R("RTL8168cp/8111cp", RTL_TD_1, NULL),
190 [RTL_GIGA_MAC_VER_19] =
191 _R("RTL8168c/8111c", RTL_TD_1, NULL),
192 [RTL_GIGA_MAC_VER_20] =
193 _R("RTL8168c/8111c", RTL_TD_1, NULL),
194 [RTL_GIGA_MAC_VER_21] =
195 _R("RTL8168c/8111c", RTL_TD_1, NULL),
196 [RTL_GIGA_MAC_VER_22] =
197 _R("RTL8168c/8111c", RTL_TD_1, NULL),
198 [RTL_GIGA_MAC_VER_23] =
199 _R("RTL8168cp/8111cp", RTL_TD_1, NULL),
200 [RTL_GIGA_MAC_VER_24] =
201 _R("RTL8168cp/8111cp", RTL_TD_1, NULL),
202 [RTL_GIGA_MAC_VER_25] =
203 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1),
204 [RTL_GIGA_MAC_VER_26] =
205 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2),
206 [RTL_GIGA_MAC_VER_27] =
207 _R("RTL8168dp/8111dp", RTL_TD_1, NULL),
208 [RTL_GIGA_MAC_VER_28] =
209 _R("RTL8168dp/8111dp", RTL_TD_1, NULL),
210 [RTL_GIGA_MAC_VER_29] =
211 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1),
212 [RTL_GIGA_MAC_VER_30] =
213 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1),
214 [RTL_GIGA_MAC_VER_31] =
215 _R("RTL8168dp/8111dp", RTL_TD_1, NULL),
216 [RTL_GIGA_MAC_VER_32] =
217 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1),
218 [RTL_GIGA_MAC_VER_33] =
219 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2),
220 [RTL_GIGA_MAC_VER_34] =
221 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3)
231 static void rtl_hw_start_8169(struct net_device *);
232 static void rtl_hw_start_8168(struct net_device *);
233 static void rtl_hw_start_8101(struct net_device *);
235 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
236 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
237 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
238 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
239 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
240 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
241 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
242 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
243 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
244 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
245 { PCI_VENDOR_ID_LINKSYS, 0x1032,
246 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
248 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
252 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
254 static int rx_buf_sz = 16383;
261 MAC0 = 0, /* Ethernet hardware address. */
263 MAR0 = 8, /* Multicast filter. */
264 CounterAddrLow = 0x10,
265 CounterAddrHigh = 0x14,
266 TxDescStartAddrLow = 0x20,
267 TxDescStartAddrHigh = 0x24,
268 TxHDescStartAddrLow = 0x28,
269 TxHDescStartAddrHigh = 0x2c,
278 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
279 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
282 #define RX128_INT_EN (1 << 15) /* 8111c and later */
283 #define RX_MULTI_EN (1 << 14) /* 8111c only */
284 #define RXCFG_FIFO_SHIFT 13
285 /* No threshold before first PCI xfer */
286 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
287 #define RXCFG_DMA_SHIFT 8
288 /* Unlimited maximum PCI burst. */
289 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
305 RxDescAddrLow = 0xe4,
306 RxDescAddrHigh = 0xe8,
307 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
309 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
311 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
313 #define TxPacketMax (8064 >> 7)
316 FuncEventMask = 0xf4,
317 FuncPresetState = 0xf8,
318 FuncForceEvent = 0xfc,
321 enum rtl8110_registers {
327 enum rtl8168_8101_registers {
330 #define CSIAR_FLAG 0x80000000
331 #define CSIAR_WRITE_CMD 0x80000000
332 #define CSIAR_BYTE_ENABLE 0x0f
333 #define CSIAR_BYTE_ENABLE_SHIFT 12
334 #define CSIAR_ADDR_MASK 0x0fff
337 #define EPHYAR_FLAG 0x80000000
338 #define EPHYAR_WRITE_CMD 0x80000000
339 #define EPHYAR_REG_MASK 0x1f
340 #define EPHYAR_REG_SHIFT 16
341 #define EPHYAR_DATA_MASK 0xffff
343 #define PFM_EN (1 << 6)
345 #define FIX_NAK_1 (1 << 4)
346 #define FIX_NAK_2 (1 << 3)
349 #define NOW_IS_OOB (1 << 7)
350 #define EN_NDP (1 << 3)
351 #define EN_OOB_RESET (1 << 2)
353 #define EFUSEAR_FLAG 0x80000000
354 #define EFUSEAR_WRITE_CMD 0x80000000
355 #define EFUSEAR_READ_CMD 0x00000000
356 #define EFUSEAR_REG_MASK 0x03ff
357 #define EFUSEAR_REG_SHIFT 8
358 #define EFUSEAR_DATA_MASK 0xff
361 enum rtl8168_registers {
366 #define ERIAR_FLAG 0x80000000
367 #define ERIAR_WRITE_CMD 0x80000000
368 #define ERIAR_READ_CMD 0x00000000
369 #define ERIAR_ADDR_BYTE_ALIGN 4
370 #define ERIAR_TYPE_SHIFT 16
371 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
372 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
373 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
374 #define ERIAR_MASK_SHIFT 12
375 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
376 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
377 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
378 EPHY_RXER_NUM = 0x7c,
379 OCPDR = 0xb0, /* OCP GPHY access */
380 #define OCPDR_WRITE_CMD 0x80000000
381 #define OCPDR_READ_CMD 0x00000000
382 #define OCPDR_REG_MASK 0x7f
383 #define OCPDR_GPHY_REG_SHIFT 16
384 #define OCPDR_DATA_MASK 0xffff
386 #define OCPAR_FLAG 0x80000000
387 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
388 #define OCPAR_GPHY_READ_CMD 0x0000f060
389 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
390 MISC = 0xf0, /* 8168e only. */
391 #define TXPLA_RST (1 << 29)
392 #define PWM_EN (1 << 22)
395 enum rtl_register_content {
396 /* InterruptStatusBits */
400 TxDescUnavail = 0x0080,
423 /* TXPoll register p.5 */
424 HPQ = 0x80, /* Poll cmd on the high prio queue */
425 NPQ = 0x40, /* Poll cmd on the low prio queue */
426 FSWInt = 0x01, /* Forced software interrupt */
430 Cfg9346_Unlock = 0xc0,
435 AcceptBroadcast = 0x08,
436 AcceptMulticast = 0x04,
438 AcceptAllPhys = 0x01,
439 #define RX_CONFIG_ACCEPT_MASK 0x3f
442 TxInterFrameGapShift = 24,
443 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
445 /* Config1 register p.24 */
448 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
449 Speed_down = (1 << 4),
453 PMEnable = (1 << 0), /* Power Management Enable */
455 /* Config2 register p. 25 */
456 PCI_Clock_66MHz = 0x01,
457 PCI_Clock_33MHz = 0x00,
459 /* Config3 register p.25 */
460 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
461 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
462 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
464 /* Config5 register p.27 */
465 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
466 MWF = (1 << 5), /* Accept Multicast wakeup frame */
467 UWF = (1 << 4), /* Accept Unicast wakeup frame */
469 LanWake = (1 << 1), /* LanWake enable/disable */
470 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
473 TBIReset = 0x80000000,
474 TBILoopback = 0x40000000,
475 TBINwEnable = 0x20000000,
476 TBINwRestart = 0x10000000,
477 TBILinkOk = 0x02000000,
478 TBINwComplete = 0x01000000,
481 EnableBist = (1 << 15), // 8168 8101
482 Mac_dbgo_oe = (1 << 14), // 8168 8101
483 Normal_mode = (1 << 13), // unused
484 Force_half_dup = (1 << 12), // 8168 8101
485 Force_rxflow_en = (1 << 11), // 8168 8101
486 Force_txflow_en = (1 << 10), // 8168 8101
487 Cxpl_dbg_sel = (1 << 9), // 8168 8101
488 ASF = (1 << 8), // 8168 8101
489 PktCntrDisable = (1 << 7), // 8168 8101
490 Mac_dbgo_sel = 0x001c, // 8168
495 INTT_0 = 0x0000, // 8168
496 INTT_1 = 0x0001, // 8168
497 INTT_2 = 0x0002, // 8168
498 INTT_3 = 0x0003, // 8168
500 /* rtl8169_PHYstatus */
511 TBILinkOK = 0x02000000,
513 /* DumpCounterCommand */
518 /* First doubleword. */
519 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
520 RingEnd = (1 << 30), /* End of descriptor ring */
521 FirstFrag = (1 << 29), /* First segment of a packet */
522 LastFrag = (1 << 28), /* Final segment of a packet */
526 enum rtl_tx_desc_bit {
527 /* First doubleword. */
528 TD_LSO = (1 << 27), /* Large Send Offload */
529 #define TD_MSS_MAX 0x07ffu /* MSS value */
531 /* Second doubleword. */
532 TxVlanTag = (1 << 17), /* Add VLAN tag */
535 /* 8169, 8168b and 810x except 8102e. */
536 enum rtl_tx_desc_bit_0 {
537 /* First doubleword. */
538 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
539 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
540 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
541 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
544 /* 8102e, 8168c and beyond. */
545 enum rtl_tx_desc_bit_1 {
546 /* Second doubleword. */
547 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
548 TD1_IP_CS = (1 << 29), /* Calculate IP checksum */
549 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
550 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
553 static const struct rtl_tx_desc_info {
560 } tx_desc_info [] = {
563 .udp = TD0_IP_CS | TD0_UDP_CS,
564 .tcp = TD0_IP_CS | TD0_TCP_CS
566 .mss_shift = TD0_MSS_SHIFT,
571 .udp = TD1_IP_CS | TD1_UDP_CS,
572 .tcp = TD1_IP_CS | TD1_TCP_CS
574 .mss_shift = TD1_MSS_SHIFT,
579 enum rtl_rx_desc_bit {
581 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
582 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
584 #define RxProtoUDP (PID1)
585 #define RxProtoTCP (PID0)
586 #define RxProtoIP (PID1 | PID0)
587 #define RxProtoMask RxProtoIP
589 IPFail = (1 << 16), /* IP checksum failed */
590 UDPFail = (1 << 15), /* UDP/IP checksum failed */
591 TCPFail = (1 << 14), /* TCP/IP checksum failed */
592 RxVlanTag = (1 << 16), /* VLAN tag available */
595 #define RsvdMask 0x3fffc000
612 u8 __pad[sizeof(void *) - sizeof(u32)];
616 RTL_FEATURE_WOL = (1 << 0),
617 RTL_FEATURE_MSI = (1 << 1),
618 RTL_FEATURE_GMII = (1 << 2),
621 struct rtl8169_counters {
628 __le32 tx_one_collision;
629 __le32 tx_multi_collision;
637 struct rtl8169_private {
638 void __iomem *mmio_addr; /* memory map physical address */
639 struct pci_dev *pci_dev;
640 struct net_device *dev;
641 struct napi_struct napi;
646 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
647 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
650 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
651 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
652 dma_addr_t TxPhyAddr;
653 dma_addr_t RxPhyAddr;
654 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
655 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
656 struct timer_list timer;
663 void (*write)(void __iomem *, int, int);
664 int (*read)(void __iomem *, int);
667 struct pll_power_ops {
668 void (*down)(struct rtl8169_private *);
669 void (*up)(struct rtl8169_private *);
672 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
673 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
674 void (*phy_reset_enable)(struct rtl8169_private *tp);
675 void (*hw_start)(struct net_device *);
676 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
677 unsigned int (*link_ok)(void __iomem *);
678 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
679 struct delayed_work task;
682 struct mii_if_info mii;
683 struct rtl8169_counters counters;
687 const struct firmware *fw;
689 #define RTL_VER_SIZE 32
691 char version[RTL_VER_SIZE];
693 struct rtl_fw_phy_action {
698 #define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
701 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
702 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
703 module_param(use_dac, int, 0);
704 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
705 module_param_named(debug, debug.msg_enable, int, 0);
706 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
707 MODULE_LICENSE("GPL");
708 MODULE_VERSION(RTL8169_VERSION);
709 MODULE_FIRMWARE(FIRMWARE_8168D_1);
710 MODULE_FIRMWARE(FIRMWARE_8168D_2);
711 MODULE_FIRMWARE(FIRMWARE_8168E_1);
712 MODULE_FIRMWARE(FIRMWARE_8168E_2);
713 MODULE_FIRMWARE(FIRMWARE_8168E_3);
714 MODULE_FIRMWARE(FIRMWARE_8105E_1);
716 static int rtl8169_open(struct net_device *dev);
717 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
718 struct net_device *dev);
719 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
720 static int rtl8169_init_ring(struct net_device *dev);
721 static void rtl_hw_start(struct net_device *dev);
722 static int rtl8169_close(struct net_device *dev);
723 static void rtl_set_rx_mode(struct net_device *dev);
724 static void rtl8169_tx_timeout(struct net_device *dev);
725 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
726 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
727 void __iomem *, u32 budget);
728 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
729 static void rtl8169_down(struct net_device *dev);
730 static void rtl8169_rx_clear(struct rtl8169_private *tp);
731 static int rtl8169_poll(struct napi_struct *napi, int budget);
733 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
735 void __iomem *ioaddr = tp->mmio_addr;
738 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
739 for (i = 0; i < 20; i++) {
741 if (RTL_R32(OCPAR) & OCPAR_FLAG)
744 return RTL_R32(OCPDR);
747 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
749 void __iomem *ioaddr = tp->mmio_addr;
752 RTL_W32(OCPDR, data);
753 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
754 for (i = 0; i < 20; i++) {
756 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
761 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
763 void __iomem *ioaddr = tp->mmio_addr;
767 RTL_W32(ERIAR, 0x800010e8);
769 for (i = 0; i < 5; i++) {
771 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
775 ocp_write(tp, 0x1, 0x30, 0x00000001);
778 #define OOB_CMD_RESET 0x00
779 #define OOB_CMD_DRIVER_START 0x05
780 #define OOB_CMD_DRIVER_STOP 0x06
782 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
784 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
787 static void rtl8168_driver_start(struct rtl8169_private *tp)
792 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
794 reg = rtl8168_get_ocp_reg(tp);
796 for (i = 0; i < 10; i++) {
798 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
803 static void rtl8168_driver_stop(struct rtl8169_private *tp)
808 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
810 reg = rtl8168_get_ocp_reg(tp);
812 for (i = 0; i < 10; i++) {
814 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
819 static int r8168dp_check_dash(struct rtl8169_private *tp)
821 u16 reg = rtl8168_get_ocp_reg(tp);
823 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
826 static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
830 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
832 for (i = 20; i > 0; i--) {
834 * Check if the RTL8169 has completed writing to the specified
837 if (!(RTL_R32(PHYAR) & 0x80000000))
842 * According to hardware specs a 20us delay is required after write
843 * complete indication, but before sending next command.
848 static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
852 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
854 for (i = 20; i > 0; i--) {
856 * Check if the RTL8169 has completed retrieving data from
857 * the specified MII register.
859 if (RTL_R32(PHYAR) & 0x80000000) {
860 value = RTL_R32(PHYAR) & 0xffff;
866 * According to hardware specs a 20us delay is required after read
867 * complete indication, but before sending next command.
874 static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
878 RTL_W32(OCPDR, data |
879 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
880 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
881 RTL_W32(EPHY_RXER_NUM, 0);
883 for (i = 0; i < 100; i++) {
885 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
890 static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
892 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
893 (value & OCPDR_DATA_MASK));
896 static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
900 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
903 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
904 RTL_W32(EPHY_RXER_NUM, 0);
906 for (i = 0; i < 100; i++) {
908 if (RTL_R32(OCPAR) & OCPAR_FLAG)
912 return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
915 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
917 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
919 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
922 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
924 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
927 static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
929 r8168dp_2_mdio_start(ioaddr);
931 r8169_mdio_write(ioaddr, reg_addr, value);
933 r8168dp_2_mdio_stop(ioaddr);
936 static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
940 r8168dp_2_mdio_start(ioaddr);
942 value = r8169_mdio_read(ioaddr, reg_addr);
944 r8168dp_2_mdio_stop(ioaddr);
949 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
951 tp->mdio_ops.write(tp->mmio_addr, location, val);
954 static int rtl_readphy(struct rtl8169_private *tp, int location)
956 return tp->mdio_ops.read(tp->mmio_addr, location);
959 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
961 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
964 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
968 val = rtl_readphy(tp, reg_addr);
969 rtl_writephy(tp, reg_addr, (val | p) & ~m);
972 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
975 struct rtl8169_private *tp = netdev_priv(dev);
977 rtl_writephy(tp, location, val);
980 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
982 struct rtl8169_private *tp = netdev_priv(dev);
984 return rtl_readphy(tp, location);
987 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
991 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
992 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
994 for (i = 0; i < 100; i++) {
995 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
1001 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
1006 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1008 for (i = 0; i < 100; i++) {
1009 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
1010 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
1019 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
1023 RTL_W32(CSIDR, value);
1024 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
1025 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1027 for (i = 0; i < 100; i++) {
1028 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
1034 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
1039 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
1040 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1042 for (i = 0; i < 100; i++) {
1043 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
1044 value = RTL_R32(CSIDR);
1054 void rtl_eri_write(void __iomem *ioaddr, int addr, u32 mask, u32 val, int type)
1058 BUG_ON((addr & 3) || (mask == 0));
1059 RTL_W32(ERIDR, val);
1060 RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1062 for (i = 0; i < 100; i++) {
1063 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
1069 static u32 rtl_eri_read(void __iomem *ioaddr, int addr, int type)
1074 RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1076 for (i = 0; i < 100; i++) {
1077 if (RTL_R32(ERIAR) & ERIAR_FLAG) {
1078 value = RTL_R32(ERIDR);
1088 rtl_w1w0_eri(void __iomem *ioaddr, int addr, u32 mask, u32 p, u32 m, int type)
1092 val = rtl_eri_read(ioaddr, addr, type);
1093 rtl_eri_write(ioaddr, addr, mask, (val & ~m) | p, type);
1102 static void rtl_write_exgmac_batch(void __iomem *ioaddr,
1103 const struct exgmac_reg *r, int len)
1106 rtl_eri_write(ioaddr, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1111 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
1116 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1118 for (i = 0; i < 300; i++) {
1119 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
1120 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
1129 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
1131 RTL_W16(IntrMask, 0x0000);
1133 RTL_W16(IntrStatus, 0xffff);
1136 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1138 void __iomem *ioaddr = tp->mmio_addr;
1140 return RTL_R32(TBICSR) & TBIReset;
1143 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1145 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1148 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1150 return RTL_R32(TBICSR) & TBILinkOk;
1153 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1155 return RTL_R8(PHYstatus) & LinkStatus;
1158 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1160 void __iomem *ioaddr = tp->mmio_addr;
1162 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1165 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1169 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1170 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1173 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1175 void __iomem *ioaddr = tp->mmio_addr;
1176 struct net_device *dev = tp->dev;
1178 if (!netif_running(dev))
1181 if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
1182 if (RTL_R8(PHYstatus) & _1000bpsF) {
1183 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1184 0x00000011, ERIAR_EXGMAC);
1185 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1186 0x00000005, ERIAR_EXGMAC);
1187 } else if (RTL_R8(PHYstatus) & _100bps) {
1188 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1189 0x0000001f, ERIAR_EXGMAC);
1190 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1191 0x00000005, ERIAR_EXGMAC);
1193 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1194 0x0000001f, ERIAR_EXGMAC);
1195 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1196 0x0000003f, ERIAR_EXGMAC);
1198 /* Reset packet filter */
1199 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1201 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1206 static void __rtl8169_check_link_status(struct net_device *dev,
1207 struct rtl8169_private *tp,
1208 void __iomem *ioaddr, bool pm)
1210 unsigned long flags;
1212 spin_lock_irqsave(&tp->lock, flags);
1213 if (tp->link_ok(ioaddr)) {
1214 rtl_link_chg_patch(tp);
1215 /* This is to cancel a scheduled suspend if there's one. */
1217 pm_request_resume(&tp->pci_dev->dev);
1218 netif_carrier_on(dev);
1219 if (net_ratelimit())
1220 netif_info(tp, ifup, dev, "link up\n");
1222 netif_carrier_off(dev);
1223 netif_info(tp, ifdown, dev, "link down\n");
1225 pm_schedule_suspend(&tp->pci_dev->dev, 100);
1227 spin_unlock_irqrestore(&tp->lock, flags);
1230 static void rtl8169_check_link_status(struct net_device *dev,
1231 struct rtl8169_private *tp,
1232 void __iomem *ioaddr)
1234 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1237 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1239 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1241 void __iomem *ioaddr = tp->mmio_addr;
1245 options = RTL_R8(Config1);
1246 if (!(options & PMEnable))
1249 options = RTL_R8(Config3);
1250 if (options & LinkUp)
1251 wolopts |= WAKE_PHY;
1252 if (options & MagicPacket)
1253 wolopts |= WAKE_MAGIC;
1255 options = RTL_R8(Config5);
1257 wolopts |= WAKE_UCAST;
1259 wolopts |= WAKE_BCAST;
1261 wolopts |= WAKE_MCAST;
1266 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1268 struct rtl8169_private *tp = netdev_priv(dev);
1270 spin_lock_irq(&tp->lock);
1272 wol->supported = WAKE_ANY;
1273 wol->wolopts = __rtl8169_get_wol(tp);
1275 spin_unlock_irq(&tp->lock);
1278 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1280 void __iomem *ioaddr = tp->mmio_addr;
1282 static const struct {
1287 { WAKE_ANY, Config1, PMEnable },
1288 { WAKE_PHY, Config3, LinkUp },
1289 { WAKE_MAGIC, Config3, MagicPacket },
1290 { WAKE_UCAST, Config5, UWF },
1291 { WAKE_BCAST, Config5, BWF },
1292 { WAKE_MCAST, Config5, MWF },
1293 { WAKE_ANY, Config5, LanWake }
1296 RTL_W8(Cfg9346, Cfg9346_Unlock);
1298 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1299 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1300 if (wolopts & cfg[i].opt)
1301 options |= cfg[i].mask;
1302 RTL_W8(cfg[i].reg, options);
1305 RTL_W8(Cfg9346, Cfg9346_Lock);
1308 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1310 struct rtl8169_private *tp = netdev_priv(dev);
1312 spin_lock_irq(&tp->lock);
1315 tp->features |= RTL_FEATURE_WOL;
1317 tp->features &= ~RTL_FEATURE_WOL;
1318 __rtl8169_set_wol(tp, wol->wolopts);
1319 spin_unlock_irq(&tp->lock);
1321 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1326 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1328 return rtl_chip_infos[tp->mac_version].fw_name;
1331 static void rtl8169_get_drvinfo(struct net_device *dev,
1332 struct ethtool_drvinfo *info)
1334 struct rtl8169_private *tp = netdev_priv(dev);
1335 struct rtl_fw *rtl_fw = tp->rtl_fw;
1337 strcpy(info->driver, MODULENAME);
1338 strcpy(info->version, RTL8169_VERSION);
1339 strcpy(info->bus_info, pci_name(tp->pci_dev));
1340 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1341 strcpy(info->fw_version, IS_ERR_OR_NULL(rtl_fw) ? "N/A" :
1345 static int rtl8169_get_regs_len(struct net_device *dev)
1347 return R8169_REGS_SIZE;
1350 static int rtl8169_set_speed_tbi(struct net_device *dev,
1351 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1353 struct rtl8169_private *tp = netdev_priv(dev);
1354 void __iomem *ioaddr = tp->mmio_addr;
1358 reg = RTL_R32(TBICSR);
1359 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1360 (duplex == DUPLEX_FULL)) {
1361 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1362 } else if (autoneg == AUTONEG_ENABLE)
1363 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1365 netif_warn(tp, link, dev,
1366 "incorrect speed setting refused in TBI mode\n");
1373 static int rtl8169_set_speed_xmii(struct net_device *dev,
1374 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1376 struct rtl8169_private *tp = netdev_priv(dev);
1377 int giga_ctrl, bmcr;
1380 rtl_writephy(tp, 0x1f, 0x0000);
1382 if (autoneg == AUTONEG_ENABLE) {
1385 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1386 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1387 ADVERTISE_100HALF | ADVERTISE_100FULL);
1389 if (adv & ADVERTISED_10baseT_Half)
1390 auto_nego |= ADVERTISE_10HALF;
1391 if (adv & ADVERTISED_10baseT_Full)
1392 auto_nego |= ADVERTISE_10FULL;
1393 if (adv & ADVERTISED_100baseT_Half)
1394 auto_nego |= ADVERTISE_100HALF;
1395 if (adv & ADVERTISED_100baseT_Full)
1396 auto_nego |= ADVERTISE_100FULL;
1398 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1400 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1401 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1403 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1404 if (tp->mii.supports_gmii) {
1405 if (adv & ADVERTISED_1000baseT_Half)
1406 giga_ctrl |= ADVERTISE_1000HALF;
1407 if (adv & ADVERTISED_1000baseT_Full)
1408 giga_ctrl |= ADVERTISE_1000FULL;
1409 } else if (adv & (ADVERTISED_1000baseT_Half |
1410 ADVERTISED_1000baseT_Full)) {
1411 netif_info(tp, link, dev,
1412 "PHY does not support 1000Mbps\n");
1416 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1418 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1419 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1423 if (speed == SPEED_10)
1425 else if (speed == SPEED_100)
1426 bmcr = BMCR_SPEED100;
1430 if (duplex == DUPLEX_FULL)
1431 bmcr |= BMCR_FULLDPLX;
1434 rtl_writephy(tp, MII_BMCR, bmcr);
1436 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1437 tp->mac_version == RTL_GIGA_MAC_VER_03) {
1438 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1439 rtl_writephy(tp, 0x17, 0x2138);
1440 rtl_writephy(tp, 0x0e, 0x0260);
1442 rtl_writephy(tp, 0x17, 0x2108);
1443 rtl_writephy(tp, 0x0e, 0x0000);
1452 static int rtl8169_set_speed(struct net_device *dev,
1453 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1455 struct rtl8169_private *tp = netdev_priv(dev);
1458 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1462 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1463 (advertising & ADVERTISED_1000baseT_Full)) {
1464 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1470 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1472 struct rtl8169_private *tp = netdev_priv(dev);
1473 unsigned long flags;
1476 del_timer_sync(&tp->timer);
1478 spin_lock_irqsave(&tp->lock, flags);
1479 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
1480 cmd->duplex, cmd->advertising);
1481 spin_unlock_irqrestore(&tp->lock, flags);
1486 static u32 rtl8169_fix_features(struct net_device *dev, u32 features)
1488 if (dev->mtu > TD_MSS_MAX)
1489 features &= ~NETIF_F_ALL_TSO;
1494 static int rtl8169_set_features(struct net_device *dev, u32 features)
1496 struct rtl8169_private *tp = netdev_priv(dev);
1497 void __iomem *ioaddr = tp->mmio_addr;
1498 unsigned long flags;
1500 spin_lock_irqsave(&tp->lock, flags);
1502 if (features & NETIF_F_RXCSUM)
1503 tp->cp_cmd |= RxChkSum;
1505 tp->cp_cmd &= ~RxChkSum;
1507 if (dev->features & NETIF_F_HW_VLAN_RX)
1508 tp->cp_cmd |= RxVlan;
1510 tp->cp_cmd &= ~RxVlan;
1512 RTL_W16(CPlusCmd, tp->cp_cmd);
1515 spin_unlock_irqrestore(&tp->lock, flags);
1520 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1521 struct sk_buff *skb)
1523 return (vlan_tx_tag_present(skb)) ?
1524 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1527 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1529 u32 opts2 = le32_to_cpu(desc->opts2);
1531 if (opts2 & RxVlanTag)
1532 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
1537 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1539 struct rtl8169_private *tp = netdev_priv(dev);
1540 void __iomem *ioaddr = tp->mmio_addr;
1544 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1545 cmd->port = PORT_FIBRE;
1546 cmd->transceiver = XCVR_INTERNAL;
1548 status = RTL_R32(TBICSR);
1549 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1550 cmd->autoneg = !!(status & TBINwEnable);
1552 ethtool_cmd_speed_set(cmd, SPEED_1000);
1553 cmd->duplex = DUPLEX_FULL; /* Always set */
1558 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1560 struct rtl8169_private *tp = netdev_priv(dev);
1562 return mii_ethtool_gset(&tp->mii, cmd);
1565 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1567 struct rtl8169_private *tp = netdev_priv(dev);
1568 unsigned long flags;
1571 spin_lock_irqsave(&tp->lock, flags);
1573 rc = tp->get_settings(dev, cmd);
1575 spin_unlock_irqrestore(&tp->lock, flags);
1579 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1582 struct rtl8169_private *tp = netdev_priv(dev);
1583 unsigned long flags;
1585 if (regs->len > R8169_REGS_SIZE)
1586 regs->len = R8169_REGS_SIZE;
1588 spin_lock_irqsave(&tp->lock, flags);
1589 memcpy_fromio(p, tp->mmio_addr, regs->len);
1590 spin_unlock_irqrestore(&tp->lock, flags);
1593 static u32 rtl8169_get_msglevel(struct net_device *dev)
1595 struct rtl8169_private *tp = netdev_priv(dev);
1597 return tp->msg_enable;
1600 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1602 struct rtl8169_private *tp = netdev_priv(dev);
1604 tp->msg_enable = value;
1607 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1614 "tx_single_collisions",
1615 "tx_multi_collisions",
1623 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1627 return ARRAY_SIZE(rtl8169_gstrings);
1633 static void rtl8169_update_counters(struct net_device *dev)
1635 struct rtl8169_private *tp = netdev_priv(dev);
1636 void __iomem *ioaddr = tp->mmio_addr;
1637 struct device *d = &tp->pci_dev->dev;
1638 struct rtl8169_counters *counters;
1644 * Some chips are unable to dump tally counters when the receiver
1647 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1650 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1654 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1655 cmd = (u64)paddr & DMA_BIT_MASK(32);
1656 RTL_W32(CounterAddrLow, cmd);
1657 RTL_W32(CounterAddrLow, cmd | CounterDump);
1660 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1661 memcpy(&tp->counters, counters, sizeof(*counters));
1667 RTL_W32(CounterAddrLow, 0);
1668 RTL_W32(CounterAddrHigh, 0);
1670 dma_free_coherent(d, sizeof(*counters), counters, paddr);
1673 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1674 struct ethtool_stats *stats, u64 *data)
1676 struct rtl8169_private *tp = netdev_priv(dev);
1680 rtl8169_update_counters(dev);
1682 data[0] = le64_to_cpu(tp->counters.tx_packets);
1683 data[1] = le64_to_cpu(tp->counters.rx_packets);
1684 data[2] = le64_to_cpu(tp->counters.tx_errors);
1685 data[3] = le32_to_cpu(tp->counters.rx_errors);
1686 data[4] = le16_to_cpu(tp->counters.rx_missed);
1687 data[5] = le16_to_cpu(tp->counters.align_errors);
1688 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1689 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1690 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1691 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1692 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1693 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1694 data[12] = le16_to_cpu(tp->counters.tx_underun);
1697 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1701 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1706 static const struct ethtool_ops rtl8169_ethtool_ops = {
1707 .get_drvinfo = rtl8169_get_drvinfo,
1708 .get_regs_len = rtl8169_get_regs_len,
1709 .get_link = ethtool_op_get_link,
1710 .get_settings = rtl8169_get_settings,
1711 .set_settings = rtl8169_set_settings,
1712 .get_msglevel = rtl8169_get_msglevel,
1713 .set_msglevel = rtl8169_set_msglevel,
1714 .get_regs = rtl8169_get_regs,
1715 .get_wol = rtl8169_get_wol,
1716 .set_wol = rtl8169_set_wol,
1717 .get_strings = rtl8169_get_strings,
1718 .get_sset_count = rtl8169_get_sset_count,
1719 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1722 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1723 struct net_device *dev, u8 default_version)
1725 void __iomem *ioaddr = tp->mmio_addr;
1727 * The driver currently handles the 8168Bf and the 8168Be identically
1728 * but they can be identified more specifically through the test below
1731 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1733 * Same thing for the 8101Eb and the 8101Ec:
1735 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1737 static const struct rtl_mac_info {
1743 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
1744 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
1745 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
1746 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
1749 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
1750 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
1751 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
1753 /* 8168DP family. */
1754 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
1755 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
1756 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
1759 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
1760 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
1761 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
1762 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
1763 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1764 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
1765 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
1766 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
1767 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
1770 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1771 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1772 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1773 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1776 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
1777 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
1778 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
1779 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
1780 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1781 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1782 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1783 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1784 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1785 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
1786 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
1787 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
1788 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
1789 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1790 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
1791 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1792 /* FIXME: where did these entries come from ? -- FR */
1793 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1794 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1797 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1798 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1799 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1800 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1801 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1802 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1805 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
1807 const struct rtl_mac_info *p = mac_info;
1810 reg = RTL_R32(TxConfig);
1811 while ((reg & p->mask) != p->val)
1813 tp->mac_version = p->mac_version;
1815 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
1816 netif_notice(tp, probe, dev,
1817 "unknown MAC, using family default\n");
1818 tp->mac_version = default_version;
1822 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1824 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1832 static void rtl_writephy_batch(struct rtl8169_private *tp,
1833 const struct phy_reg *regs, int len)
1836 rtl_writephy(tp, regs->reg, regs->val);
1841 #define PHY_READ 0x00000000
1842 #define PHY_DATA_OR 0x10000000
1843 #define PHY_DATA_AND 0x20000000
1844 #define PHY_BJMPN 0x30000000
1845 #define PHY_READ_EFUSE 0x40000000
1846 #define PHY_READ_MAC_BYTE 0x50000000
1847 #define PHY_WRITE_MAC_BYTE 0x60000000
1848 #define PHY_CLEAR_READCOUNT 0x70000000
1849 #define PHY_WRITE 0x80000000
1850 #define PHY_READCOUNT_EQ_SKIP 0x90000000
1851 #define PHY_COMP_EQ_SKIPN 0xa0000000
1852 #define PHY_COMP_NEQ_SKIPN 0xb0000000
1853 #define PHY_WRITE_PREVIOUS 0xc0000000
1854 #define PHY_SKIPN 0xd0000000
1855 #define PHY_DELAY_MS 0xe0000000
1856 #define PHY_WRITE_ERI_WORD 0xf0000000
1860 char version[RTL_VER_SIZE];
1866 #define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
1868 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
1870 const struct firmware *fw = rtl_fw->fw;
1871 struct fw_info *fw_info = (struct fw_info *)fw->data;
1872 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
1873 char *version = rtl_fw->version;
1876 if (fw->size < FW_OPCODE_SIZE)
1879 if (!fw_info->magic) {
1880 size_t i, size, start;
1883 if (fw->size < sizeof(*fw_info))
1886 for (i = 0; i < fw->size; i++)
1887 checksum += fw->data[i];
1891 start = le32_to_cpu(fw_info->fw_start);
1892 if (start > fw->size)
1895 size = le32_to_cpu(fw_info->fw_len);
1896 if (size > (fw->size - start) / FW_OPCODE_SIZE)
1899 memcpy(version, fw_info->version, RTL_VER_SIZE);
1901 pa->code = (__le32 *)(fw->data + start);
1904 if (fw->size % FW_OPCODE_SIZE)
1907 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
1909 pa->code = (__le32 *)fw->data;
1910 pa->size = fw->size / FW_OPCODE_SIZE;
1912 version[RTL_VER_SIZE - 1] = 0;
1919 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
1920 struct rtl_fw_phy_action *pa)
1925 for (index = 0; index < pa->size; index++) {
1926 u32 action = le32_to_cpu(pa->code[index]);
1927 u32 regno = (action & 0x0fff0000) >> 16;
1929 switch(action & 0xf0000000) {
1933 case PHY_READ_EFUSE:
1934 case PHY_CLEAR_READCOUNT:
1936 case PHY_WRITE_PREVIOUS:
1941 if (regno > index) {
1942 netif_err(tp, ifup, tp->dev,
1943 "Out of range of firmware\n");
1947 case PHY_READCOUNT_EQ_SKIP:
1948 if (index + 2 >= pa->size) {
1949 netif_err(tp, ifup, tp->dev,
1950 "Out of range of firmware\n");
1954 case PHY_COMP_EQ_SKIPN:
1955 case PHY_COMP_NEQ_SKIPN:
1957 if (index + 1 + regno >= pa->size) {
1958 netif_err(tp, ifup, tp->dev,
1959 "Out of range of firmware\n");
1964 case PHY_READ_MAC_BYTE:
1965 case PHY_WRITE_MAC_BYTE:
1966 case PHY_WRITE_ERI_WORD:
1968 netif_err(tp, ifup, tp->dev,
1969 "Invalid action 0x%08x\n", action);
1978 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
1980 struct net_device *dev = tp->dev;
1983 if (!rtl_fw_format_ok(tp, rtl_fw)) {
1984 netif_err(tp, ifup, dev, "invalid firwmare\n");
1988 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
1994 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
1996 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2000 predata = count = 0;
2002 for (index = 0; index < pa->size; ) {
2003 u32 action = le32_to_cpu(pa->code[index]);
2004 u32 data = action & 0x0000ffff;
2005 u32 regno = (action & 0x0fff0000) >> 16;
2010 switch(action & 0xf0000000) {
2012 predata = rtl_readphy(tp, regno);
2027 case PHY_READ_EFUSE:
2028 predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
2031 case PHY_CLEAR_READCOUNT:
2036 rtl_writephy(tp, regno, data);
2039 case PHY_READCOUNT_EQ_SKIP:
2040 index += (count == data) ? 2 : 1;
2042 case PHY_COMP_EQ_SKIPN:
2043 if (predata == data)
2047 case PHY_COMP_NEQ_SKIPN:
2048 if (predata != data)
2052 case PHY_WRITE_PREVIOUS:
2053 rtl_writephy(tp, regno, predata);
2064 case PHY_READ_MAC_BYTE:
2065 case PHY_WRITE_MAC_BYTE:
2066 case PHY_WRITE_ERI_WORD:
2073 static void rtl_release_firmware(struct rtl8169_private *tp)
2075 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2076 release_firmware(tp->rtl_fw->fw);
2079 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2082 static void rtl_apply_firmware(struct rtl8169_private *tp)
2084 struct rtl_fw *rtl_fw = tp->rtl_fw;
2086 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2087 if (!IS_ERR_OR_NULL(rtl_fw))
2088 rtl_phy_write_fw(tp, rtl_fw);
2091 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2093 if (rtl_readphy(tp, reg) != val)
2094 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2096 rtl_apply_firmware(tp);
2099 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2101 static const struct phy_reg phy_reg_init[] = {
2163 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2166 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2168 static const struct phy_reg phy_reg_init[] = {
2174 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2177 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2179 struct pci_dev *pdev = tp->pci_dev;
2181 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2182 (pdev->subsystem_device != 0xe000))
2185 rtl_writephy(tp, 0x1f, 0x0001);
2186 rtl_writephy(tp, 0x10, 0xf01b);
2187 rtl_writephy(tp, 0x1f, 0x0000);
2190 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2192 static const struct phy_reg phy_reg_init[] = {
2232 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2234 rtl8169scd_hw_phy_config_quirk(tp);
2237 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2239 static const struct phy_reg phy_reg_init[] = {
2287 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2290 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2292 static const struct phy_reg phy_reg_init[] = {
2297 rtl_writephy(tp, 0x1f, 0x0001);
2298 rtl_patchphy(tp, 0x16, 1 << 0);
2300 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2303 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2305 static const struct phy_reg phy_reg_init[] = {
2311 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2314 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2316 static const struct phy_reg phy_reg_init[] = {
2324 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2327 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2329 static const struct phy_reg phy_reg_init[] = {
2335 rtl_writephy(tp, 0x1f, 0x0000);
2336 rtl_patchphy(tp, 0x14, 1 << 5);
2337 rtl_patchphy(tp, 0x0d, 1 << 5);
2339 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2342 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2344 static const struct phy_reg phy_reg_init[] = {
2364 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2366 rtl_patchphy(tp, 0x14, 1 << 5);
2367 rtl_patchphy(tp, 0x0d, 1 << 5);
2368 rtl_writephy(tp, 0x1f, 0x0000);
2371 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2373 static const struct phy_reg phy_reg_init[] = {
2391 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2393 rtl_patchphy(tp, 0x16, 1 << 0);
2394 rtl_patchphy(tp, 0x14, 1 << 5);
2395 rtl_patchphy(tp, 0x0d, 1 << 5);
2396 rtl_writephy(tp, 0x1f, 0x0000);
2399 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2401 static const struct phy_reg phy_reg_init[] = {
2413 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2415 rtl_patchphy(tp, 0x16, 1 << 0);
2416 rtl_patchphy(tp, 0x14, 1 << 5);
2417 rtl_patchphy(tp, 0x0d, 1 << 5);
2418 rtl_writephy(tp, 0x1f, 0x0000);
2421 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2423 rtl8168c_3_hw_phy_config(tp);
2426 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2428 static const struct phy_reg phy_reg_init_0[] = {
2429 /* Channel Estimation */
2450 * Enhance line driver power
2459 * Can not link to 1Gbps with bad cable
2460 * Decrease SNR threshold form 21.07dB to 19.04dB
2468 void __iomem *ioaddr = tp->mmio_addr;
2470 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2474 * Fine Tune Switching regulator parameter
2476 rtl_writephy(tp, 0x1f, 0x0002);
2477 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2478 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2480 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2481 static const struct phy_reg phy_reg_init[] = {
2491 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2493 val = rtl_readphy(tp, 0x0d);
2495 if ((val & 0x00ff) != 0x006c) {
2496 static const u32 set[] = {
2497 0x0065, 0x0066, 0x0067, 0x0068,
2498 0x0069, 0x006a, 0x006b, 0x006c
2502 rtl_writephy(tp, 0x1f, 0x0002);
2505 for (i = 0; i < ARRAY_SIZE(set); i++)
2506 rtl_writephy(tp, 0x0d, val | set[i]);
2509 static const struct phy_reg phy_reg_init[] = {
2517 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2520 /* RSET couple improve */
2521 rtl_writephy(tp, 0x1f, 0x0002);
2522 rtl_patchphy(tp, 0x0d, 0x0300);
2523 rtl_patchphy(tp, 0x0f, 0x0010);
2525 /* Fine tune PLL performance */
2526 rtl_writephy(tp, 0x1f, 0x0002);
2527 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2528 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2530 rtl_writephy(tp, 0x1f, 0x0005);
2531 rtl_writephy(tp, 0x05, 0x001b);
2533 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2535 rtl_writephy(tp, 0x1f, 0x0000);
2538 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2540 static const struct phy_reg phy_reg_init_0[] = {
2541 /* Channel Estimation */
2562 * Enhance line driver power
2571 * Can not link to 1Gbps with bad cable
2572 * Decrease SNR threshold form 21.07dB to 19.04dB
2580 void __iomem *ioaddr = tp->mmio_addr;
2582 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2584 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2585 static const struct phy_reg phy_reg_init[] = {
2596 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2598 val = rtl_readphy(tp, 0x0d);
2599 if ((val & 0x00ff) != 0x006c) {
2600 static const u32 set[] = {
2601 0x0065, 0x0066, 0x0067, 0x0068,
2602 0x0069, 0x006a, 0x006b, 0x006c
2606 rtl_writephy(tp, 0x1f, 0x0002);
2609 for (i = 0; i < ARRAY_SIZE(set); i++)
2610 rtl_writephy(tp, 0x0d, val | set[i]);
2613 static const struct phy_reg phy_reg_init[] = {
2621 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2624 /* Fine tune PLL performance */
2625 rtl_writephy(tp, 0x1f, 0x0002);
2626 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2627 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2629 /* Switching regulator Slew rate */
2630 rtl_writephy(tp, 0x1f, 0x0002);
2631 rtl_patchphy(tp, 0x0f, 0x0017);
2633 rtl_writephy(tp, 0x1f, 0x0005);
2634 rtl_writephy(tp, 0x05, 0x001b);
2636 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2638 rtl_writephy(tp, 0x1f, 0x0000);
2641 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2643 static const struct phy_reg phy_reg_init[] = {
2699 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2702 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2704 static const struct phy_reg phy_reg_init[] = {
2714 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2715 rtl_patchphy(tp, 0x0d, 1 << 5);
2718 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
2720 static const struct phy_reg phy_reg_init[] = {
2721 /* Enable Delay cap */
2727 /* Channel estimation fine tune */
2736 /* Update PFM & 10M TX idle timer */
2748 rtl_apply_firmware(tp);
2750 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2752 /* DCO enable for 10M IDLE Power */
2753 rtl_writephy(tp, 0x1f, 0x0007);
2754 rtl_writephy(tp, 0x1e, 0x0023);
2755 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2756 rtl_writephy(tp, 0x1f, 0x0000);
2758 /* For impedance matching */
2759 rtl_writephy(tp, 0x1f, 0x0002);
2760 rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
2761 rtl_writephy(tp, 0x1f, 0x0000);
2763 /* PHY auto speed down */
2764 rtl_writephy(tp, 0x1f, 0x0007);
2765 rtl_writephy(tp, 0x1e, 0x002d);
2766 rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2767 rtl_writephy(tp, 0x1f, 0x0000);
2768 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2770 rtl_writephy(tp, 0x1f, 0x0005);
2771 rtl_writephy(tp, 0x05, 0x8b86);
2772 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2773 rtl_writephy(tp, 0x1f, 0x0000);
2775 rtl_writephy(tp, 0x1f, 0x0005);
2776 rtl_writephy(tp, 0x05, 0x8b85);
2777 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2778 rtl_writephy(tp, 0x1f, 0x0007);
2779 rtl_writephy(tp, 0x1e, 0x0020);
2780 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2781 rtl_writephy(tp, 0x1f, 0x0006);
2782 rtl_writephy(tp, 0x00, 0x5a00);
2783 rtl_writephy(tp, 0x1f, 0x0000);
2784 rtl_writephy(tp, 0x0d, 0x0007);
2785 rtl_writephy(tp, 0x0e, 0x003c);
2786 rtl_writephy(tp, 0x0d, 0x4007);
2787 rtl_writephy(tp, 0x0e, 0x0000);
2788 rtl_writephy(tp, 0x0d, 0x0000);
2791 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
2793 static const struct phy_reg phy_reg_init[] = {
2794 /* Enable Delay cap */
2803 /* Channel estimation fine tune */
2820 rtl_apply_firmware(tp);
2822 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2824 /* For 4-corner performance improve */
2825 rtl_writephy(tp, 0x1f, 0x0005);
2826 rtl_writephy(tp, 0x05, 0x8b80);
2827 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2828 rtl_writephy(tp, 0x1f, 0x0000);
2830 /* PHY auto speed down */
2831 rtl_writephy(tp, 0x1f, 0x0004);
2832 rtl_writephy(tp, 0x1f, 0x0007);
2833 rtl_writephy(tp, 0x1e, 0x002d);
2834 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
2835 rtl_writephy(tp, 0x1f, 0x0002);
2836 rtl_writephy(tp, 0x1f, 0x0000);
2837 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2839 /* improve 10M EEE waveform */
2840 rtl_writephy(tp, 0x1f, 0x0005);
2841 rtl_writephy(tp, 0x05, 0x8b86);
2842 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2843 rtl_writephy(tp, 0x1f, 0x0000);
2845 /* Improve 2-pair detection performance */
2846 rtl_writephy(tp, 0x1f, 0x0005);
2847 rtl_writephy(tp, 0x05, 0x8b85);
2848 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
2849 rtl_writephy(tp, 0x1f, 0x0000);
2852 rtl_w1w0_eri(tp->mmio_addr, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003,
2854 rtl_writephy(tp, 0x1f, 0x0005);
2855 rtl_writephy(tp, 0x05, 0x8b85);
2856 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2857 rtl_writephy(tp, 0x1f, 0x0004);
2858 rtl_writephy(tp, 0x1f, 0x0007);
2859 rtl_writephy(tp, 0x1e, 0x0020);
2860 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
2861 rtl_writephy(tp, 0x1f, 0x0002);
2862 rtl_writephy(tp, 0x1f, 0x0000);
2863 rtl_writephy(tp, 0x0d, 0x0007);
2864 rtl_writephy(tp, 0x0e, 0x003c);
2865 rtl_writephy(tp, 0x0d, 0x4007);
2866 rtl_writephy(tp, 0x0e, 0x0000);
2867 rtl_writephy(tp, 0x0d, 0x0000);
2870 rtl_writephy(tp, 0x1f, 0x0003);
2871 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
2872 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
2873 rtl_writephy(tp, 0x1f, 0x0000);
2876 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2878 static const struct phy_reg phy_reg_init[] = {
2885 rtl_writephy(tp, 0x1f, 0x0000);
2886 rtl_patchphy(tp, 0x11, 1 << 12);
2887 rtl_patchphy(tp, 0x19, 1 << 13);
2888 rtl_patchphy(tp, 0x10, 1 << 15);
2890 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2893 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
2895 static const struct phy_reg phy_reg_init[] = {
2909 /* Disable ALDPS before ram code */
2910 rtl_writephy(tp, 0x1f, 0x0000);
2911 rtl_writephy(tp, 0x18, 0x0310);
2914 rtl_apply_firmware(tp);
2916 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2919 static void rtl_hw_phy_config(struct net_device *dev)
2921 struct rtl8169_private *tp = netdev_priv(dev);
2923 rtl8169_print_mac_version(tp);
2925 switch (tp->mac_version) {
2926 case RTL_GIGA_MAC_VER_01:
2928 case RTL_GIGA_MAC_VER_02:
2929 case RTL_GIGA_MAC_VER_03:
2930 rtl8169s_hw_phy_config(tp);
2932 case RTL_GIGA_MAC_VER_04:
2933 rtl8169sb_hw_phy_config(tp);
2935 case RTL_GIGA_MAC_VER_05:
2936 rtl8169scd_hw_phy_config(tp);
2938 case RTL_GIGA_MAC_VER_06:
2939 rtl8169sce_hw_phy_config(tp);
2941 case RTL_GIGA_MAC_VER_07:
2942 case RTL_GIGA_MAC_VER_08:
2943 case RTL_GIGA_MAC_VER_09:
2944 rtl8102e_hw_phy_config(tp);
2946 case RTL_GIGA_MAC_VER_11:
2947 rtl8168bb_hw_phy_config(tp);
2949 case RTL_GIGA_MAC_VER_12:
2950 rtl8168bef_hw_phy_config(tp);
2952 case RTL_GIGA_MAC_VER_17:
2953 rtl8168bef_hw_phy_config(tp);
2955 case RTL_GIGA_MAC_VER_18:
2956 rtl8168cp_1_hw_phy_config(tp);
2958 case RTL_GIGA_MAC_VER_19:
2959 rtl8168c_1_hw_phy_config(tp);
2961 case RTL_GIGA_MAC_VER_20:
2962 rtl8168c_2_hw_phy_config(tp);
2964 case RTL_GIGA_MAC_VER_21:
2965 rtl8168c_3_hw_phy_config(tp);
2967 case RTL_GIGA_MAC_VER_22:
2968 rtl8168c_4_hw_phy_config(tp);
2970 case RTL_GIGA_MAC_VER_23:
2971 case RTL_GIGA_MAC_VER_24:
2972 rtl8168cp_2_hw_phy_config(tp);
2974 case RTL_GIGA_MAC_VER_25:
2975 rtl8168d_1_hw_phy_config(tp);
2977 case RTL_GIGA_MAC_VER_26:
2978 rtl8168d_2_hw_phy_config(tp);
2980 case RTL_GIGA_MAC_VER_27:
2981 rtl8168d_3_hw_phy_config(tp);
2983 case RTL_GIGA_MAC_VER_28:
2984 rtl8168d_4_hw_phy_config(tp);
2986 case RTL_GIGA_MAC_VER_29:
2987 case RTL_GIGA_MAC_VER_30:
2988 rtl8105e_hw_phy_config(tp);
2990 case RTL_GIGA_MAC_VER_31:
2993 case RTL_GIGA_MAC_VER_32:
2994 case RTL_GIGA_MAC_VER_33:
2995 rtl8168e_1_hw_phy_config(tp);
2997 case RTL_GIGA_MAC_VER_34:
2998 rtl8168e_2_hw_phy_config(tp);
3006 static void rtl8169_phy_timer(unsigned long __opaque)
3008 struct net_device *dev = (struct net_device *)__opaque;
3009 struct rtl8169_private *tp = netdev_priv(dev);
3010 struct timer_list *timer = &tp->timer;
3011 void __iomem *ioaddr = tp->mmio_addr;
3012 unsigned long timeout = RTL8169_PHY_TIMEOUT;
3014 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
3016 spin_lock_irq(&tp->lock);
3018 if (tp->phy_reset_pending(tp)) {
3020 * A busy loop could burn quite a few cycles on nowadays CPU.
3021 * Let's delay the execution of the timer for a few ticks.
3027 if (tp->link_ok(ioaddr))
3030 netif_warn(tp, link, dev, "PHY reset until link up\n");
3032 tp->phy_reset_enable(tp);
3035 mod_timer(timer, jiffies + timeout);
3037 spin_unlock_irq(&tp->lock);
3040 #ifdef CONFIG_NET_POLL_CONTROLLER
3042 * Polling 'interrupt' - used by things like netconsole to send skbs
3043 * without having to re-enable interrupts. It's not called while
3044 * the interrupt routine is executing.
3046 static void rtl8169_netpoll(struct net_device *dev)
3048 struct rtl8169_private *tp = netdev_priv(dev);
3049 struct pci_dev *pdev = tp->pci_dev;
3051 disable_irq(pdev->irq);
3052 rtl8169_interrupt(pdev->irq, dev);
3053 enable_irq(pdev->irq);
3057 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3058 void __iomem *ioaddr)
3061 pci_release_regions(pdev);
3062 pci_clear_mwi(pdev);
3063 pci_disable_device(pdev);
3067 static void rtl8169_phy_reset(struct net_device *dev,
3068 struct rtl8169_private *tp)
3072 tp->phy_reset_enable(tp);
3073 for (i = 0; i < 100; i++) {
3074 if (!tp->phy_reset_pending(tp))
3078 netif_err(tp, link, dev, "PHY reset failed\n");
3081 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3083 void __iomem *ioaddr = tp->mmio_addr;
3085 rtl_hw_phy_config(dev);
3087 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3088 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3092 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3094 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3095 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
3097 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
3098 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3100 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
3101 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
3104 rtl8169_phy_reset(dev, tp);
3106 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
3107 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3108 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3109 (tp->mii.supports_gmii ?
3110 ADVERTISED_1000baseT_Half |
3111 ADVERTISED_1000baseT_Full : 0));
3113 if (RTL_R8(PHYstatus) & TBI_Enable)
3114 netif_info(tp, link, dev, "TBI auto-negotiating\n");
3117 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3119 void __iomem *ioaddr = tp->mmio_addr;
3123 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
3124 high = addr[4] | (addr[5] << 8);
3126 spin_lock_irq(&tp->lock);
3128 RTL_W8(Cfg9346, Cfg9346_Unlock);
3130 RTL_W32(MAC4, high);
3136 if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
3137 const struct exgmac_reg e[] = {
3138 { .addr = 0xe0, ERIAR_MASK_1111, .val = low },
3139 { .addr = 0xe4, ERIAR_MASK_1111, .val = high },
3140 { .addr = 0xf0, ERIAR_MASK_1111, .val = low << 16 },
3141 { .addr = 0xf4, ERIAR_MASK_1111, .val = high << 16 |
3145 rtl_write_exgmac_batch(ioaddr, e, ARRAY_SIZE(e));
3148 RTL_W8(Cfg9346, Cfg9346_Lock);
3150 spin_unlock_irq(&tp->lock);
3153 static int rtl_set_mac_address(struct net_device *dev, void *p)
3155 struct rtl8169_private *tp = netdev_priv(dev);
3156 struct sockaddr *addr = p;
3158 if (!is_valid_ether_addr(addr->sa_data))
3159 return -EADDRNOTAVAIL;
3161 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3163 rtl_rar_set(tp, dev->dev_addr);
3168 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3170 struct rtl8169_private *tp = netdev_priv(dev);
3171 struct mii_ioctl_data *data = if_mii(ifr);
3173 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
3176 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
3177 struct mii_ioctl_data *data, int cmd)
3181 data->phy_id = 32; /* Internal PHY */
3185 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
3189 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
3195 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
3200 static const struct rtl_cfg_info {
3201 void (*hw_start)(struct net_device *);
3202 unsigned int region;
3208 } rtl_cfg_infos [] = {
3210 .hw_start = rtl_hw_start_8169,
3213 .intr_event = SYSErr | LinkChg | RxOverflow |
3214 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
3215 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
3216 .features = RTL_FEATURE_GMII,
3217 .default_ver = RTL_GIGA_MAC_VER_01,
3220 .hw_start = rtl_hw_start_8168,
3223 .intr_event = SYSErr | LinkChg | RxOverflow |
3224 TxErr | TxOK | RxOK | RxErr,
3225 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
3226 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
3227 .default_ver = RTL_GIGA_MAC_VER_11,
3230 .hw_start = rtl_hw_start_8101,
3233 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
3234 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
3235 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
3236 .features = RTL_FEATURE_MSI,
3237 .default_ver = RTL_GIGA_MAC_VER_13,
3241 /* Cfg9346_Unlock assumed. */
3242 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
3243 const struct rtl_cfg_info *cfg)
3248 cfg2 = RTL_R8(Config2) & ~MSIEnable;
3249 if (cfg->features & RTL_FEATURE_MSI) {
3250 if (pci_enable_msi(pdev)) {
3251 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
3254 msi = RTL_FEATURE_MSI;
3257 RTL_W8(Config2, cfg2);
3261 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3263 if (tp->features & RTL_FEATURE_MSI) {
3264 pci_disable_msi(pdev);
3265 tp->features &= ~RTL_FEATURE_MSI;
3269 static const struct net_device_ops rtl8169_netdev_ops = {
3270 .ndo_open = rtl8169_open,
3271 .ndo_stop = rtl8169_close,
3272 .ndo_get_stats = rtl8169_get_stats,
3273 .ndo_start_xmit = rtl8169_start_xmit,
3274 .ndo_tx_timeout = rtl8169_tx_timeout,
3275 .ndo_validate_addr = eth_validate_addr,
3276 .ndo_change_mtu = rtl8169_change_mtu,
3277 .ndo_fix_features = rtl8169_fix_features,
3278 .ndo_set_features = rtl8169_set_features,
3279 .ndo_set_mac_address = rtl_set_mac_address,
3280 .ndo_do_ioctl = rtl8169_ioctl,
3281 .ndo_set_multicast_list = rtl_set_rx_mode,
3282 #ifdef CONFIG_NET_POLL_CONTROLLER
3283 .ndo_poll_controller = rtl8169_netpoll,
3288 static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
3290 struct mdio_ops *ops = &tp->mdio_ops;
3292 switch (tp->mac_version) {
3293 case RTL_GIGA_MAC_VER_27:
3294 ops->write = r8168dp_1_mdio_write;
3295 ops->read = r8168dp_1_mdio_read;
3297 case RTL_GIGA_MAC_VER_28:
3298 case RTL_GIGA_MAC_VER_31:
3299 ops->write = r8168dp_2_mdio_write;
3300 ops->read = r8168dp_2_mdio_read;
3303 ops->write = r8169_mdio_write;
3304 ops->read = r8169_mdio_read;
3309 static void r810x_phy_power_down(struct rtl8169_private *tp)
3311 rtl_writephy(tp, 0x1f, 0x0000);
3312 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3315 static void r810x_phy_power_up(struct rtl8169_private *tp)
3317 rtl_writephy(tp, 0x1f, 0x0000);
3318 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3321 static void r810x_pll_power_down(struct rtl8169_private *tp)
3323 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3324 rtl_writephy(tp, 0x1f, 0x0000);
3325 rtl_writephy(tp, MII_BMCR, 0x0000);
3329 r810x_phy_power_down(tp);
3332 static void r810x_pll_power_up(struct rtl8169_private *tp)
3334 r810x_phy_power_up(tp);
3337 static void r8168_phy_power_up(struct rtl8169_private *tp)
3339 rtl_writephy(tp, 0x1f, 0x0000);
3340 switch (tp->mac_version) {
3341 case RTL_GIGA_MAC_VER_11:
3342 case RTL_GIGA_MAC_VER_12:
3343 case RTL_GIGA_MAC_VER_17:
3344 case RTL_GIGA_MAC_VER_18:
3345 case RTL_GIGA_MAC_VER_19:
3346 case RTL_GIGA_MAC_VER_20:
3347 case RTL_GIGA_MAC_VER_21:
3348 case RTL_GIGA_MAC_VER_22:
3349 case RTL_GIGA_MAC_VER_23:
3350 case RTL_GIGA_MAC_VER_24:
3351 case RTL_GIGA_MAC_VER_25:
3352 case RTL_GIGA_MAC_VER_26:
3353 case RTL_GIGA_MAC_VER_27:
3354 case RTL_GIGA_MAC_VER_28:
3355 case RTL_GIGA_MAC_VER_31:
3356 rtl_writephy(tp, 0x0e, 0x0000);
3361 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3364 static void r8168_phy_power_down(struct rtl8169_private *tp)
3366 rtl_writephy(tp, 0x1f, 0x0000);
3367 switch (tp->mac_version) {
3368 case RTL_GIGA_MAC_VER_32:
3369 case RTL_GIGA_MAC_VER_33:
3370 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3373 case RTL_GIGA_MAC_VER_11:
3374 case RTL_GIGA_MAC_VER_12:
3375 case RTL_GIGA_MAC_VER_17:
3376 case RTL_GIGA_MAC_VER_18:
3377 case RTL_GIGA_MAC_VER_19:
3378 case RTL_GIGA_MAC_VER_20:
3379 case RTL_GIGA_MAC_VER_21:
3380 case RTL_GIGA_MAC_VER_22:
3381 case RTL_GIGA_MAC_VER_23:
3382 case RTL_GIGA_MAC_VER_24:
3383 case RTL_GIGA_MAC_VER_25:
3384 case RTL_GIGA_MAC_VER_26:
3385 case RTL_GIGA_MAC_VER_27:
3386 case RTL_GIGA_MAC_VER_28:
3387 case RTL_GIGA_MAC_VER_31:
3388 rtl_writephy(tp, 0x0e, 0x0200);
3390 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3395 static void r8168_pll_power_down(struct rtl8169_private *tp)
3397 void __iomem *ioaddr = tp->mmio_addr;
3399 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3400 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3401 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3402 r8168dp_check_dash(tp)) {
3406 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
3407 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
3408 (RTL_R16(CPlusCmd) & ASF)) {
3412 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3413 tp->mac_version == RTL_GIGA_MAC_VER_33)
3414 rtl_ephy_write(ioaddr, 0x19, 0xff64);
3416 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3417 rtl_writephy(tp, 0x1f, 0x0000);
3418 rtl_writephy(tp, MII_BMCR, 0x0000);
3420 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3421 tp->mac_version == RTL_GIGA_MAC_VER_33)
3422 RTL_W32(RxConfig, RTL_R32(RxConfig) | AcceptBroadcast |
3423 AcceptMulticast | AcceptMyPhys);
3427 r8168_phy_power_down(tp);
3429 switch (tp->mac_version) {
3430 case RTL_GIGA_MAC_VER_25:
3431 case RTL_GIGA_MAC_VER_26:
3432 case RTL_GIGA_MAC_VER_27:
3433 case RTL_GIGA_MAC_VER_28:
3434 case RTL_GIGA_MAC_VER_31:
3435 case RTL_GIGA_MAC_VER_32:
3436 case RTL_GIGA_MAC_VER_33:
3437 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3442 static void r8168_pll_power_up(struct rtl8169_private *tp)
3444 void __iomem *ioaddr = tp->mmio_addr;
3446 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3447 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3448 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3449 r8168dp_check_dash(tp)) {
3453 switch (tp->mac_version) {
3454 case RTL_GIGA_MAC_VER_25:
3455 case RTL_GIGA_MAC_VER_26:
3456 case RTL_GIGA_MAC_VER_27:
3457 case RTL_GIGA_MAC_VER_28:
3458 case RTL_GIGA_MAC_VER_31:
3459 case RTL_GIGA_MAC_VER_32:
3460 case RTL_GIGA_MAC_VER_33:
3461 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3465 r8168_phy_power_up(tp);
3468 static void rtl_pll_power_op(struct rtl8169_private *tp,
3469 void (*op)(struct rtl8169_private *))
3475 static void rtl_pll_power_down(struct rtl8169_private *tp)
3477 rtl_pll_power_op(tp, tp->pll_power_ops.down);
3480 static void rtl_pll_power_up(struct rtl8169_private *tp)
3482 rtl_pll_power_op(tp, tp->pll_power_ops.up);
3485 static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3487 struct pll_power_ops *ops = &tp->pll_power_ops;
3489 switch (tp->mac_version) {
3490 case RTL_GIGA_MAC_VER_07:
3491 case RTL_GIGA_MAC_VER_08:
3492 case RTL_GIGA_MAC_VER_09:
3493 case RTL_GIGA_MAC_VER_10:
3494 case RTL_GIGA_MAC_VER_16:
3495 case RTL_GIGA_MAC_VER_29:
3496 case RTL_GIGA_MAC_VER_30:
3497 ops->down = r810x_pll_power_down;
3498 ops->up = r810x_pll_power_up;
3501 case RTL_GIGA_MAC_VER_11:
3502 case RTL_GIGA_MAC_VER_12:
3503 case RTL_GIGA_MAC_VER_17:
3504 case RTL_GIGA_MAC_VER_18:
3505 case RTL_GIGA_MAC_VER_19:
3506 case RTL_GIGA_MAC_VER_20:
3507 case RTL_GIGA_MAC_VER_21:
3508 case RTL_GIGA_MAC_VER_22:
3509 case RTL_GIGA_MAC_VER_23:
3510 case RTL_GIGA_MAC_VER_24:
3511 case RTL_GIGA_MAC_VER_25:
3512 case RTL_GIGA_MAC_VER_26:
3513 case RTL_GIGA_MAC_VER_27:
3514 case RTL_GIGA_MAC_VER_28:
3515 case RTL_GIGA_MAC_VER_31:
3516 case RTL_GIGA_MAC_VER_32:
3517 case RTL_GIGA_MAC_VER_33:
3518 case RTL_GIGA_MAC_VER_34:
3519 ops->down = r8168_pll_power_down;
3520 ops->up = r8168_pll_power_up;
3530 static void rtl_init_rxcfg(struct rtl8169_private *tp)
3532 void __iomem *ioaddr = tp->mmio_addr;
3534 switch (tp->mac_version) {
3535 case RTL_GIGA_MAC_VER_01:
3536 case RTL_GIGA_MAC_VER_02:
3537 case RTL_GIGA_MAC_VER_03:
3538 case RTL_GIGA_MAC_VER_04:
3539 case RTL_GIGA_MAC_VER_05:
3540 case RTL_GIGA_MAC_VER_06:
3541 case RTL_GIGA_MAC_VER_10:
3542 case RTL_GIGA_MAC_VER_11:
3543 case RTL_GIGA_MAC_VER_12:
3544 case RTL_GIGA_MAC_VER_13:
3545 case RTL_GIGA_MAC_VER_14:
3546 case RTL_GIGA_MAC_VER_15:
3547 case RTL_GIGA_MAC_VER_16:
3548 case RTL_GIGA_MAC_VER_17:
3549 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
3551 case RTL_GIGA_MAC_VER_18:
3552 case RTL_GIGA_MAC_VER_19:
3553 case RTL_GIGA_MAC_VER_20:
3554 case RTL_GIGA_MAC_VER_21:
3555 case RTL_GIGA_MAC_VER_22:
3556 case RTL_GIGA_MAC_VER_23:
3557 case RTL_GIGA_MAC_VER_24:
3558 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
3561 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
3566 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3568 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
3571 static void rtl_hw_reset(struct rtl8169_private *tp)
3573 void __iomem *ioaddr = tp->mmio_addr;
3576 /* Soft reset the chip. */
3577 RTL_W8(ChipCmd, CmdReset);
3579 /* Check that the chip has finished the reset. */
3580 for (i = 0; i < 100; i++) {
3581 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3586 rtl8169_init_ring_indexes(tp);
3589 static int __devinit
3590 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3592 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
3593 const unsigned int region = cfg->region;
3594 struct rtl8169_private *tp;
3595 struct mii_if_info *mii;
3596 struct net_device *dev;
3597 void __iomem *ioaddr;
3601 if (netif_msg_drv(&debug)) {
3602 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
3603 MODULENAME, RTL8169_VERSION);
3606 dev = alloc_etherdev(sizeof (*tp));
3608 if (netif_msg_drv(&debug))
3609 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
3614 SET_NETDEV_DEV(dev, &pdev->dev);
3615 dev->netdev_ops = &rtl8169_netdev_ops;
3616 tp = netdev_priv(dev);
3619 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
3623 mii->mdio_read = rtl_mdio_read;
3624 mii->mdio_write = rtl_mdio_write;
3625 mii->phy_id_mask = 0x1f;
3626 mii->reg_num_mask = 0x1f;
3627 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3629 /* disable ASPM completely as that cause random device stop working
3630 * problems as well as full system hangs for some PCIe devices users */
3631 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3632 PCIE_LINK_STATE_CLKPM);
3634 /* enable device (incl. PCI PM wakeup and hotplug setup) */
3635 rc = pci_enable_device(pdev);
3637 netif_err(tp, probe, dev, "enable failure\n");
3638 goto err_out_free_dev_1;
3641 if (pci_set_mwi(pdev) < 0)
3642 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
3644 /* make sure PCI base addr 1 is MMIO */
3645 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
3646 netif_err(tp, probe, dev,
3647 "region #%d not an MMIO resource, aborting\n",
3653 /* check for weird/broken PCI region reporting */
3654 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
3655 netif_err(tp, probe, dev,
3656 "Invalid PCI region size(s), aborting\n");
3661 rc = pci_request_regions(pdev, MODULENAME);
3663 netif_err(tp, probe, dev, "could not request regions\n");
3667 tp->cp_cmd = RxChkSum;
3669 if ((sizeof(dma_addr_t) > 4) &&
3670 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
3671 tp->cp_cmd |= PCIDAC;
3672 dev->features |= NETIF_F_HIGHDMA;
3674 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3676 netif_err(tp, probe, dev, "DMA configuration failed\n");
3677 goto err_out_free_res_3;
3681 /* ioremap MMIO region */
3682 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
3684 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
3686 goto err_out_free_res_3;
3688 tp->mmio_addr = ioaddr;
3690 if (!pci_is_pcie(pdev))
3691 netif_info(tp, probe, dev, "not PCI Express\n");
3693 /* Identify chip attached to board */
3694 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
3698 RTL_W16(IntrMask, 0x0000);
3702 RTL_W16(IntrStatus, 0xffff);
3704 pci_set_master(pdev);
3707 * Pretend we are using VLANs; This bypasses a nasty bug where
3708 * Interrupts stop flowing on high load on 8110SCd controllers.
3710 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3711 tp->cp_cmd |= RxVlan;
3713 rtl_init_mdio_ops(tp);
3714 rtl_init_pll_power_ops(tp);
3716 rtl8169_print_mac_version(tp);
3718 chipset = tp->mac_version;
3719 tp->txd_version = rtl_chip_infos[chipset].txd_version;
3721 RTL_W8(Cfg9346, Cfg9346_Unlock);
3722 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3723 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
3724 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3725 tp->features |= RTL_FEATURE_WOL;
3726 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3727 tp->features |= RTL_FEATURE_WOL;
3728 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
3729 RTL_W8(Cfg9346, Cfg9346_Lock);
3731 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3732 (RTL_R8(PHYstatus) & TBI_Enable)) {
3733 tp->set_speed = rtl8169_set_speed_tbi;
3734 tp->get_settings = rtl8169_gset_tbi;
3735 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3736 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3737 tp->link_ok = rtl8169_tbi_link_ok;
3738 tp->do_ioctl = rtl_tbi_ioctl;
3740 tp->set_speed = rtl8169_set_speed_xmii;
3741 tp->get_settings = rtl8169_gset_xmii;
3742 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3743 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3744 tp->link_ok = rtl8169_xmii_link_ok;
3745 tp->do_ioctl = rtl_xmii_ioctl;
3748 spin_lock_init(&tp->lock);
3750 /* Get MAC address */
3751 for (i = 0; i < MAC_ADDR_LEN; i++)
3752 dev->dev_addr[i] = RTL_R8(MAC0 + i);
3753 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3755 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
3756 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3757 dev->irq = pdev->irq;
3758 dev->base_addr = (unsigned long) ioaddr;
3760 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
3762 /* don't enable SG, IP_CSUM and TSO by default - it might not work
3763 * properly for all devices */
3764 dev->features |= NETIF_F_RXCSUM |
3765 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3767 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3768 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3769 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3772 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3773 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
3774 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
3776 tp->intr_mask = 0xffff;
3777 tp->hw_start = cfg->hw_start;
3778 tp->intr_event = cfg->intr_event;
3779 tp->napi_event = cfg->napi_event;
3781 init_timer(&tp->timer);
3782 tp->timer.data = (unsigned long) dev;
3783 tp->timer.function = rtl8169_phy_timer;
3785 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
3787 rc = register_netdev(dev);
3791 pci_set_drvdata(pdev, dev);
3793 netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
3794 rtl_chip_infos[chipset].name, dev->base_addr, dev->dev_addr,
3795 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
3797 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3798 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3799 tp->mac_version == RTL_GIGA_MAC_VER_31) {
3800 rtl8168_driver_start(tp);
3803 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
3805 if (pci_dev_run_wake(pdev))
3806 pm_runtime_put_noidle(&pdev->dev);
3808 netif_carrier_off(dev);
3814 rtl_disable_msi(pdev, tp);
3817 pci_release_regions(pdev);
3819 pci_clear_mwi(pdev);
3820 pci_disable_device(pdev);
3826 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
3828 struct net_device *dev = pci_get_drvdata(pdev);
3829 struct rtl8169_private *tp = netdev_priv(dev);
3831 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3832 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3833 tp->mac_version == RTL_GIGA_MAC_VER_31) {
3834 rtl8168_driver_stop(tp);
3837 cancel_delayed_work_sync(&tp->task);
3839 unregister_netdev(dev);
3841 rtl_release_firmware(tp);
3843 if (pci_dev_run_wake(pdev))
3844 pm_runtime_get_noresume(&pdev->dev);
3846 /* restore original MAC address */
3847 rtl_rar_set(tp, dev->perm_addr);
3849 rtl_disable_msi(pdev, tp);
3850 rtl8169_release_board(pdev, dev, tp->mmio_addr);
3851 pci_set_drvdata(pdev, NULL);
3854 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
3856 struct rtl_fw *rtl_fw;
3860 name = rtl_lookup_firmware_name(tp);
3862 goto out_no_firmware;
3864 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
3868 rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
3872 rc = rtl_check_firmware(tp, rtl_fw);
3874 goto err_release_firmware;
3876 tp->rtl_fw = rtl_fw;
3880 err_release_firmware:
3881 release_firmware(rtl_fw->fw);
3885 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
3892 static void rtl_request_firmware(struct rtl8169_private *tp)
3894 if (IS_ERR(tp->rtl_fw))
3895 rtl_request_uncached_firmware(tp);
3898 static int rtl8169_open(struct net_device *dev)
3900 struct rtl8169_private *tp = netdev_priv(dev);
3901 void __iomem *ioaddr = tp->mmio_addr;
3902 struct pci_dev *pdev = tp->pci_dev;
3903 int retval = -ENOMEM;
3905 pm_runtime_get_sync(&pdev->dev);
3908 * Rx and Tx desscriptors needs 256 bytes alignment.
3909 * dma_alloc_coherent provides more.
3911 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
3912 &tp->TxPhyAddr, GFP_KERNEL);
3913 if (!tp->TxDescArray)
3914 goto err_pm_runtime_put;
3916 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
3917 &tp->RxPhyAddr, GFP_KERNEL);
3918 if (!tp->RxDescArray)
3921 retval = rtl8169_init_ring(dev);
3925 INIT_DELAYED_WORK(&tp->task, NULL);
3929 rtl_request_firmware(tp);
3931 retval = request_irq(dev->irq, rtl8169_interrupt,
3932 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
3935 goto err_release_fw_2;
3937 napi_enable(&tp->napi);
3939 rtl8169_init_phy(dev, tp);
3941 rtl8169_set_features(dev, dev->features);
3943 rtl_pll_power_up(tp);
3947 tp->saved_wolopts = 0;
3948 pm_runtime_put_noidle(&pdev->dev);
3950 rtl8169_check_link_status(dev, tp, ioaddr);
3955 rtl_release_firmware(tp);
3956 rtl8169_rx_clear(tp);
3958 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
3960 tp->RxDescArray = NULL;
3962 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
3964 tp->TxDescArray = NULL;
3966 pm_runtime_put_noidle(&pdev->dev);
3970 static void rtl_rx_close(struct rtl8169_private *tp)
3972 void __iomem *ioaddr = tp->mmio_addr;
3974 RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
3977 static void rtl8169_hw_reset(struct rtl8169_private *tp)
3979 void __iomem *ioaddr = tp->mmio_addr;
3981 /* Disable interrupts */
3982 rtl8169_irq_mask_and_ack(ioaddr);
3986 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3987 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3988 tp->mac_version == RTL_GIGA_MAC_VER_31) {
3989 while (RTL_R8(TxPoll) & NPQ)
3991 } else if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
3992 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
3993 while (!(RTL_R32(TxConfig) & TXCFG_EMPTY))
3996 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4003 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
4005 void __iomem *ioaddr = tp->mmio_addr;
4007 /* Set DMA burst size and Interframe Gap Time */
4008 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4009 (InterFrameGap << TxInterFrameGapShift));
4012 static void rtl_hw_start(struct net_device *dev)
4014 struct rtl8169_private *tp = netdev_priv(dev);
4018 netif_start_queue(dev);
4021 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
4022 void __iomem *ioaddr)
4025 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4026 * register to be written before TxDescAddrLow to work.
4027 * Switching from MMIO to I/O access fixes the issue as well.
4029 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4030 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4031 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4032 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4035 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
4039 cmd = RTL_R16(CPlusCmd);
4040 RTL_W16(CPlusCmd, cmd);
4044 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
4046 /* Low hurts. Let's disable the filtering. */
4047 RTL_W16(RxMaxSize, rx_buf_sz + 1);
4050 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
4052 static const struct rtl_cfg2_info {
4057 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4058 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4059 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4060 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
4062 const struct rtl_cfg2_info *p = cfg2_info;
4066 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
4067 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
4068 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4069 RTL_W32(0x7c, p->val);
4075 static void rtl_hw_start_8169(struct net_device *dev)
4077 struct rtl8169_private *tp = netdev_priv(dev);
4078 void __iomem *ioaddr = tp->mmio_addr;
4079 struct pci_dev *pdev = tp->pci_dev;
4081 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4082 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4083 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4086 RTL_W8(Cfg9346, Cfg9346_Unlock);
4087 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4088 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4089 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4090 tp->mac_version == RTL_GIGA_MAC_VER_04)
4091 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4095 RTL_W8(EarlyTxThres, NoEarlyTx);
4097 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4099 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4100 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4101 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4102 tp->mac_version == RTL_GIGA_MAC_VER_04)
4103 rtl_set_rx_tx_config_registers(tp);
4105 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
4107 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4108 tp->mac_version == RTL_GIGA_MAC_VER_03) {
4109 dprintk("Set MAC Reg C+CR Offset 0xE0. "
4110 "Bit-3 and bit-14 MUST be 1\n");
4111 tp->cp_cmd |= (1 << 14);
4114 RTL_W16(CPlusCmd, tp->cp_cmd);
4116 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
4119 * Undocumented corner. Supposedly:
4120 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4122 RTL_W16(IntrMitigate, 0x0000);
4124 rtl_set_rx_tx_desc_registers(tp, ioaddr);
4126 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
4127 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
4128 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
4129 tp->mac_version != RTL_GIGA_MAC_VER_04) {
4130 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4131 rtl_set_rx_tx_config_registers(tp);
4134 RTL_W8(Cfg9346, Cfg9346_Lock);
4136 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4139 RTL_W32(RxMissed, 0);
4141 rtl_set_rx_mode(dev);
4143 /* no early-rx interrupts */
4144 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4146 /* Enable all known interrupts by setting the interrupt mask. */
4147 RTL_W16(IntrMask, tp->intr_event);
4150 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
4152 int cap = pci_pcie_cap(pdev);
4157 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
4158 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
4159 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
4163 static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
4167 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
4168 rtl_csi_write(ioaddr, 0x070c, csi | bits);
4171 static void rtl_csi_access_enable_1(void __iomem *ioaddr)
4173 rtl_csi_access_enable(ioaddr, 0x17000000);
4176 static void rtl_csi_access_enable_2(void __iomem *ioaddr)
4178 rtl_csi_access_enable(ioaddr, 0x27000000);
4182 unsigned int offset;
4187 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
4192 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
4193 rtl_ephy_write(ioaddr, e->offset, w);
4198 static void rtl_disable_clock_request(struct pci_dev *pdev)
4200 int cap = pci_pcie_cap(pdev);
4205 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4206 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
4207 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4211 static void rtl_enable_clock_request(struct pci_dev *pdev)
4213 int cap = pci_pcie_cap(pdev);
4218 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4219 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
4220 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4224 #define R8168_CPCMD_QUIRK_MASK (\
4235 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
4237 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4239 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4241 rtl_tx_performance_tweak(pdev,
4242 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4245 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
4247 rtl_hw_start_8168bb(ioaddr, pdev);
4249 RTL_W8(MaxTxPacketSize, TxPacketMax);
4251 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4254 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
4256 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4258 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4260 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4262 rtl_disable_clock_request(pdev);
4264 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4267 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
4269 static const struct ephy_info e_info_8168cp[] = {
4270 { 0x01, 0, 0x0001 },
4271 { 0x02, 0x0800, 0x1000 },
4272 { 0x03, 0, 0x0042 },
4273 { 0x06, 0x0080, 0x0000 },
4277 rtl_csi_access_enable_2(ioaddr);
4279 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4281 __rtl_hw_start_8168cp(ioaddr, pdev);
4284 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
4286 rtl_csi_access_enable_2(ioaddr);
4288 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4290 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4292 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4295 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
4297 rtl_csi_access_enable_2(ioaddr);
4299 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4302 RTL_W8(DBG_REG, 0x20);
4304 RTL_W8(MaxTxPacketSize, TxPacketMax);
4306 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4308 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4311 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
4313 static const struct ephy_info e_info_8168c_1[] = {
4314 { 0x02, 0x0800, 0x1000 },
4315 { 0x03, 0, 0x0002 },
4316 { 0x06, 0x0080, 0x0000 }
4319 rtl_csi_access_enable_2(ioaddr);
4321 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4323 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4325 __rtl_hw_start_8168cp(ioaddr, pdev);
4328 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
4330 static const struct ephy_info e_info_8168c_2[] = {
4331 { 0x01, 0, 0x0001 },
4332 { 0x03, 0x0400, 0x0220 }
4335 rtl_csi_access_enable_2(ioaddr);
4337 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4339 __rtl_hw_start_8168cp(ioaddr, pdev);
4342 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
4344 rtl_hw_start_8168c_2(ioaddr, pdev);
4347 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
4349 rtl_csi_access_enable_2(ioaddr);
4351 __rtl_hw_start_8168cp(ioaddr, pdev);
4354 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
4356 rtl_csi_access_enable_2(ioaddr);
4358 rtl_disable_clock_request(pdev);
4360 RTL_W8(MaxTxPacketSize, TxPacketMax);
4362 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4364 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4367 static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev)
4369 rtl_csi_access_enable_1(ioaddr);
4371 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4373 RTL_W8(MaxTxPacketSize, TxPacketMax);
4375 rtl_disable_clock_request(pdev);
4378 static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
4380 static const struct ephy_info e_info_8168d_4[] = {
4382 { 0x19, 0x20, 0x50 },
4387 rtl_csi_access_enable_1(ioaddr);
4389 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4391 RTL_W8(MaxTxPacketSize, TxPacketMax);
4393 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4394 const struct ephy_info *e = e_info_8168d_4 + i;
4397 w = rtl_ephy_read(ioaddr, e->offset);
4398 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
4401 rtl_enable_clock_request(pdev);
4404 static void rtl_hw_start_8168e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4406 static const struct ephy_info e_info_8168e_1[] = {
4407 { 0x00, 0x0200, 0x0100 },
4408 { 0x00, 0x0000, 0x0004 },
4409 { 0x06, 0x0002, 0x0001 },
4410 { 0x06, 0x0000, 0x0030 },
4411 { 0x07, 0x0000, 0x2000 },
4412 { 0x00, 0x0000, 0x0020 },
4413 { 0x03, 0x5800, 0x2000 },
4414 { 0x03, 0x0000, 0x0001 },
4415 { 0x01, 0x0800, 0x1000 },
4416 { 0x07, 0x0000, 0x4000 },
4417 { 0x1e, 0x0000, 0x2000 },
4418 { 0x19, 0xffff, 0xfe6c },
4419 { 0x0a, 0x0000, 0x0040 }
4422 rtl_csi_access_enable_2(ioaddr);
4424 rtl_ephy_init(ioaddr, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
4426 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4428 RTL_W8(MaxTxPacketSize, TxPacketMax);
4430 rtl_disable_clock_request(pdev);
4432 /* Reset tx FIFO pointer */
4433 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
4434 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
4436 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4439 static void rtl_hw_start_8168e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4441 static const struct ephy_info e_info_8168e_2[] = {
4442 { 0x09, 0x0000, 0x0080 },
4443 { 0x19, 0x0000, 0x0224 }
4446 rtl_csi_access_enable_1(ioaddr);
4448 rtl_ephy_init(ioaddr, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
4450 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4452 rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4453 rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4454 rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4455 rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4456 rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4457 rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
4458 rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4459 rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4462 RTL_W8(MaxTxPacketSize, 0x27);
4464 rtl_disable_clock_request(pdev);
4466 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4467 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4469 /* Adjust EEE LED frequency */
4470 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4472 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4473 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4474 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4477 static void rtl_hw_start_8168(struct net_device *dev)
4479 struct rtl8169_private *tp = netdev_priv(dev);
4480 void __iomem *ioaddr = tp->mmio_addr;
4481 struct pci_dev *pdev = tp->pci_dev;
4483 RTL_W8(Cfg9346, Cfg9346_Unlock);
4485 RTL_W8(MaxTxPacketSize, TxPacketMax);
4487 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4489 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
4491 RTL_W16(CPlusCmd, tp->cp_cmd);
4493 RTL_W16(IntrMitigate, 0x5151);
4495 /* Work around for RxFIFO overflow. */
4496 if (tp->mac_version == RTL_GIGA_MAC_VER_11 ||
4497 tp->mac_version == RTL_GIGA_MAC_VER_22) {
4498 tp->intr_event |= RxFIFOOver | PCSTimeout;
4499 tp->intr_event &= ~RxOverflow;
4502 rtl_set_rx_tx_desc_registers(tp, ioaddr);
4504 rtl_set_rx_mode(dev);
4506 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4507 (InterFrameGap << TxInterFrameGapShift));
4511 switch (tp->mac_version) {
4512 case RTL_GIGA_MAC_VER_11:
4513 rtl_hw_start_8168bb(ioaddr, pdev);
4516 case RTL_GIGA_MAC_VER_12:
4517 case RTL_GIGA_MAC_VER_17:
4518 rtl_hw_start_8168bef(ioaddr, pdev);
4521 case RTL_GIGA_MAC_VER_18:
4522 rtl_hw_start_8168cp_1(ioaddr, pdev);
4525 case RTL_GIGA_MAC_VER_19:
4526 rtl_hw_start_8168c_1(ioaddr, pdev);
4529 case RTL_GIGA_MAC_VER_20:
4530 rtl_hw_start_8168c_2(ioaddr, pdev);
4533 case RTL_GIGA_MAC_VER_21:
4534 rtl_hw_start_8168c_3(ioaddr, pdev);
4537 case RTL_GIGA_MAC_VER_22:
4538 rtl_hw_start_8168c_4(ioaddr, pdev);
4541 case RTL_GIGA_MAC_VER_23:
4542 rtl_hw_start_8168cp_2(ioaddr, pdev);
4545 case RTL_GIGA_MAC_VER_24:
4546 rtl_hw_start_8168cp_3(ioaddr, pdev);
4549 case RTL_GIGA_MAC_VER_25:
4550 case RTL_GIGA_MAC_VER_26:
4551 case RTL_GIGA_MAC_VER_27:
4552 rtl_hw_start_8168d(ioaddr, pdev);
4555 case RTL_GIGA_MAC_VER_28:
4556 rtl_hw_start_8168d_4(ioaddr, pdev);
4559 case RTL_GIGA_MAC_VER_31:
4560 rtl_hw_start_8168dp(ioaddr, pdev);
4563 case RTL_GIGA_MAC_VER_32:
4564 case RTL_GIGA_MAC_VER_33:
4565 rtl_hw_start_8168e_1(ioaddr, pdev);
4567 case RTL_GIGA_MAC_VER_34:
4568 rtl_hw_start_8168e_2(ioaddr, pdev);
4572 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
4573 dev->name, tp->mac_version);
4577 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4579 RTL_W8(Cfg9346, Cfg9346_Lock);
4581 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4583 RTL_W16(IntrMask, tp->intr_event);
4586 #define R810X_CPCMD_QUIRK_MASK (\
4597 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4599 static const struct ephy_info e_info_8102e_1[] = {
4600 { 0x01, 0, 0x6e65 },
4601 { 0x02, 0, 0x091f },
4602 { 0x03, 0, 0xc2f9 },
4603 { 0x06, 0, 0xafb5 },
4604 { 0x07, 0, 0x0e00 },
4605 { 0x19, 0, 0xec80 },
4606 { 0x01, 0, 0x2e65 },
4611 rtl_csi_access_enable_2(ioaddr);
4613 RTL_W8(DBG_REG, FIX_NAK_1);
4615 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4618 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
4619 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4621 cfg1 = RTL_R8(Config1);
4622 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
4623 RTL_W8(Config1, cfg1 & ~LEDS0);
4625 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
4628 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4630 rtl_csi_access_enable_2(ioaddr);
4632 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4634 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
4635 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4638 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
4640 rtl_hw_start_8102e_2(ioaddr, pdev);
4642 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
4645 static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4647 static const struct ephy_info e_info_8105e_1[] = {
4648 { 0x07, 0, 0x4000 },
4649 { 0x19, 0, 0x0200 },
4650 { 0x19, 0, 0x0020 },
4651 { 0x1e, 0, 0x2000 },
4652 { 0x03, 0, 0x0001 },
4653 { 0x19, 0, 0x0100 },
4654 { 0x19, 0, 0x0004 },
4658 /* Force LAN exit from ASPM if Rx/Tx are not idle */
4659 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
4661 /* Disable Early Tally Counter */
4662 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
4664 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4665 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4667 rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
4670 static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4672 rtl_hw_start_8105e_1(ioaddr, pdev);
4673 rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
4676 static void rtl_hw_start_8101(struct net_device *dev)
4678 struct rtl8169_private *tp = netdev_priv(dev);
4679 void __iomem *ioaddr = tp->mmio_addr;
4680 struct pci_dev *pdev = tp->pci_dev;
4682 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
4683 tp->mac_version == RTL_GIGA_MAC_VER_16) {
4684 int cap = pci_pcie_cap(pdev);
4687 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
4688 PCI_EXP_DEVCTL_NOSNOOP_EN);
4692 RTL_W8(Cfg9346, Cfg9346_Unlock);
4694 switch (tp->mac_version) {
4695 case RTL_GIGA_MAC_VER_07:
4696 rtl_hw_start_8102e_1(ioaddr, pdev);
4699 case RTL_GIGA_MAC_VER_08:
4700 rtl_hw_start_8102e_3(ioaddr, pdev);
4703 case RTL_GIGA_MAC_VER_09:
4704 rtl_hw_start_8102e_2(ioaddr, pdev);
4707 case RTL_GIGA_MAC_VER_29:
4708 rtl_hw_start_8105e_1(ioaddr, pdev);
4710 case RTL_GIGA_MAC_VER_30:
4711 rtl_hw_start_8105e_2(ioaddr, pdev);
4715 RTL_W8(Cfg9346, Cfg9346_Lock);
4717 RTL_W8(MaxTxPacketSize, TxPacketMax);
4719 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4721 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
4722 RTL_W16(CPlusCmd, tp->cp_cmd);
4724 RTL_W16(IntrMitigate, 0x0000);
4726 rtl_set_rx_tx_desc_registers(tp, ioaddr);
4728 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4729 rtl_set_rx_tx_config_registers(tp);
4733 rtl_set_rx_mode(dev);
4735 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
4737 RTL_W16(IntrMask, tp->intr_event);
4740 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
4742 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
4746 netdev_update_features(dev);
4751 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
4753 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
4754 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
4757 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
4758 void **data_buff, struct RxDesc *desc)
4760 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
4765 rtl8169_make_unusable_by_asic(desc);
4768 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
4770 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
4772 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
4775 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
4778 desc->addr = cpu_to_le64(mapping);
4780 rtl8169_mark_to_asic(desc, rx_buf_sz);
4783 static inline void *rtl8169_align(void *data)
4785 return (void *)ALIGN((long)data, 16);
4788 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
4789 struct RxDesc *desc)
4793 struct device *d = &tp->pci_dev->dev;
4794 struct net_device *dev = tp->dev;
4795 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
4797 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
4801 if (rtl8169_align(data) != data) {
4803 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
4808 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
4810 if (unlikely(dma_mapping_error(d, mapping))) {
4811 if (net_ratelimit())
4812 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
4816 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
4824 static void rtl8169_rx_clear(struct rtl8169_private *tp)
4828 for (i = 0; i < NUM_RX_DESC; i++) {
4829 if (tp->Rx_databuff[i]) {
4830 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
4831 tp->RxDescArray + i);
4836 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
4838 desc->opts1 |= cpu_to_le32(RingEnd);
4841 static int rtl8169_rx_fill(struct rtl8169_private *tp)
4845 for (i = 0; i < NUM_RX_DESC; i++) {
4848 if (tp->Rx_databuff[i])
4851 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
4853 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
4856 tp->Rx_databuff[i] = data;
4859 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4863 rtl8169_rx_clear(tp);
4867 static int rtl8169_init_ring(struct net_device *dev)
4869 struct rtl8169_private *tp = netdev_priv(dev);
4871 rtl8169_init_ring_indexes(tp);
4873 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
4874 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
4876 return rtl8169_rx_fill(tp);
4879 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
4880 struct TxDesc *desc)
4882 unsigned int len = tx_skb->len;
4884 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
4892 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4897 for (i = 0; i < n; i++) {
4898 unsigned int entry = (start + i) % NUM_TX_DESC;
4899 struct ring_info *tx_skb = tp->tx_skb + entry;
4900 unsigned int len = tx_skb->len;
4903 struct sk_buff *skb = tx_skb->skb;
4905 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4906 tp->TxDescArray + entry);
4908 tp->dev->stats.tx_dropped++;
4916 static void rtl8169_tx_clear(struct rtl8169_private *tp)
4918 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
4919 tp->cur_tx = tp->dirty_tx = 0;
4922 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
4924 struct rtl8169_private *tp = netdev_priv(dev);
4926 PREPARE_DELAYED_WORK(&tp->task, task);
4927 schedule_delayed_work(&tp->task, 4);
4930 static void rtl8169_wait_for_quiescence(struct net_device *dev)
4932 struct rtl8169_private *tp = netdev_priv(dev);
4933 void __iomem *ioaddr = tp->mmio_addr;
4935 synchronize_irq(dev->irq);
4937 /* Wait for any pending NAPI task to complete */
4938 napi_disable(&tp->napi);
4940 rtl8169_irq_mask_and_ack(ioaddr);
4942 tp->intr_mask = 0xffff;
4943 RTL_W16(IntrMask, tp->intr_event);
4944 napi_enable(&tp->napi);
4947 static void rtl8169_reinit_task(struct work_struct *work)
4949 struct rtl8169_private *tp =
4950 container_of(work, struct rtl8169_private, task.work);
4951 struct net_device *dev = tp->dev;
4956 if (!netif_running(dev))
4959 rtl8169_wait_for_quiescence(dev);
4962 ret = rtl8169_open(dev);
4963 if (unlikely(ret < 0)) {
4964 if (net_ratelimit())
4965 netif_err(tp, drv, dev,
4966 "reinit failure (status = %d). Rescheduling\n",
4968 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4975 static void rtl8169_reset_task(struct work_struct *work)
4977 struct rtl8169_private *tp =
4978 container_of(work, struct rtl8169_private, task.work);
4979 struct net_device *dev = tp->dev;
4984 if (!netif_running(dev))
4987 rtl8169_wait_for_quiescence(dev);
4989 for (i = 0; i < NUM_RX_DESC; i++)
4990 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
4992 rtl8169_tx_clear(tp);
4994 rtl8169_hw_reset(tp);
4996 netif_wake_queue(dev);
4997 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
5003 static void rtl8169_tx_timeout(struct net_device *dev)
5005 struct rtl8169_private *tp = netdev_priv(dev);
5007 rtl8169_hw_reset(tp);
5009 /* Let's wait a bit while any (async) irq lands on */
5010 rtl8169_schedule_work(dev, rtl8169_reset_task);
5013 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5016 struct skb_shared_info *info = skb_shinfo(skb);
5017 unsigned int cur_frag, entry;
5018 struct TxDesc * uninitialized_var(txd);
5019 struct device *d = &tp->pci_dev->dev;
5022 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5023 skb_frag_t *frag = info->frags + cur_frag;
5028 entry = (entry + 1) % NUM_TX_DESC;
5030 txd = tp->TxDescArray + entry;
5032 addr = ((void *) page_address(frag->page)) + frag->page_offset;
5033 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5034 if (unlikely(dma_mapping_error(d, mapping))) {
5035 if (net_ratelimit())
5036 netif_err(tp, drv, tp->dev,
5037 "Failed to map TX fragments DMA!\n");
5041 /* Anti gcc 2.95.3 bugware (sic) */
5042 status = opts[0] | len |
5043 (RingEnd * !((entry + 1) % NUM_TX_DESC));
5045 txd->opts1 = cpu_to_le32(status);
5046 txd->opts2 = cpu_to_le32(opts[1]);
5047 txd->addr = cpu_to_le64(mapping);
5049 tp->tx_skb[entry].len = len;
5053 tp->tx_skb[entry].skb = skb;
5054 txd->opts1 |= cpu_to_le32(LastFrag);
5060 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5064 static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
5065 struct sk_buff *skb, u32 *opts)
5067 const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
5068 u32 mss = skb_shinfo(skb)->gso_size;
5069 int offset = info->opts_offset;
5073 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
5074 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5075 const struct iphdr *ip = ip_hdr(skb);
5077 if (ip->protocol == IPPROTO_TCP)
5078 opts[offset] |= info->checksum.tcp;
5079 else if (ip->protocol == IPPROTO_UDP)
5080 opts[offset] |= info->checksum.udp;
5086 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5087 struct net_device *dev)
5089 struct rtl8169_private *tp = netdev_priv(dev);
5090 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
5091 struct TxDesc *txd = tp->TxDescArray + entry;
5092 void __iomem *ioaddr = tp->mmio_addr;
5093 struct device *d = &tp->pci_dev->dev;
5099 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
5100 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
5104 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
5107 len = skb_headlen(skb);
5108 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
5109 if (unlikely(dma_mapping_error(d, mapping))) {
5110 if (net_ratelimit())
5111 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
5115 tp->tx_skb[entry].len = len;
5116 txd->addr = cpu_to_le64(mapping);
5118 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
5121 rtl8169_tso_csum(tp, skb, opts);
5123 frags = rtl8169_xmit_frags(tp, skb, opts);
5127 opts[0] |= FirstFrag;
5129 opts[0] |= FirstFrag | LastFrag;
5130 tp->tx_skb[entry].skb = skb;
5133 txd->opts2 = cpu_to_le32(opts[1]);
5137 /* Anti gcc 2.95.3 bugware (sic) */
5138 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
5139 txd->opts1 = cpu_to_le32(status);
5141 tp->cur_tx += frags + 1;
5145 RTL_W8(TxPoll, NPQ);
5147 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
5148 netif_stop_queue(dev);
5150 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
5151 netif_wake_queue(dev);
5154 return NETDEV_TX_OK;
5157 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
5160 dev->stats.tx_dropped++;
5161 return NETDEV_TX_OK;
5164 netif_stop_queue(dev);
5165 dev->stats.tx_dropped++;
5166 return NETDEV_TX_BUSY;
5169 static void rtl8169_pcierr_interrupt(struct net_device *dev)
5171 struct rtl8169_private *tp = netdev_priv(dev);
5172 struct pci_dev *pdev = tp->pci_dev;
5173 u16 pci_status, pci_cmd;
5175 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5176 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5178 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5179 pci_cmd, pci_status);
5182 * The recovery sequence below admits a very elaborated explanation:
5183 * - it seems to work;
5184 * - I did not see what else could be done;
5185 * - it makes iop3xx happy.
5187 * Feel free to adjust to your needs.
5189 if (pdev->broken_parity_status)
5190 pci_cmd &= ~PCI_COMMAND_PARITY;
5192 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5194 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
5196 pci_write_config_word(pdev, PCI_STATUS,
5197 pci_status & (PCI_STATUS_DETECTED_PARITY |
5198 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5199 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5201 /* The infamous DAC f*ckup only happens at boot time */
5202 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
5203 void __iomem *ioaddr = tp->mmio_addr;
5205 netif_info(tp, intr, dev, "disabling PCI DAC\n");
5206 tp->cp_cmd &= ~PCIDAC;
5207 RTL_W16(CPlusCmd, tp->cp_cmd);
5208 dev->features &= ~NETIF_F_HIGHDMA;
5211 rtl8169_hw_reset(tp);
5213 rtl8169_schedule_work(dev, rtl8169_reinit_task);
5216 static void rtl8169_tx_interrupt(struct net_device *dev,
5217 struct rtl8169_private *tp,
5218 void __iomem *ioaddr)
5220 unsigned int dirty_tx, tx_left;
5222 dirty_tx = tp->dirty_tx;
5224 tx_left = tp->cur_tx - dirty_tx;
5226 while (tx_left > 0) {
5227 unsigned int entry = dirty_tx % NUM_TX_DESC;
5228 struct ring_info *tx_skb = tp->tx_skb + entry;
5232 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5233 if (status & DescOwn)
5236 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5237 tp->TxDescArray + entry);
5238 if (status & LastFrag) {
5239 dev->stats.tx_packets++;
5240 dev->stats.tx_bytes += tx_skb->skb->len;
5241 dev_kfree_skb(tx_skb->skb);
5248 if (tp->dirty_tx != dirty_tx) {
5249 tp->dirty_tx = dirty_tx;
5251 if (netif_queue_stopped(dev) &&
5252 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
5253 netif_wake_queue(dev);
5256 * 8168 hack: TxPoll requests are lost when the Tx packets are
5257 * too close. Let's kick an extra TxPoll request when a burst
5258 * of start_xmit activity is detected (if it is not detected,
5259 * it is slow enough). -- FR
5262 if (tp->cur_tx != dirty_tx)
5263 RTL_W8(TxPoll, NPQ);
5267 static inline int rtl8169_fragmented_frame(u32 status)
5269 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
5272 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
5274 u32 status = opts1 & RxProtoMask;
5276 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
5277 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
5278 skb->ip_summed = CHECKSUM_UNNECESSARY;
5280 skb_checksum_none_assert(skb);
5283 static struct sk_buff *rtl8169_try_rx_copy(void *data,
5284 struct rtl8169_private *tp,
5288 struct sk_buff *skb;
5289 struct device *d = &tp->pci_dev->dev;
5291 data = rtl8169_align(data);
5292 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
5294 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
5296 memcpy(skb->data, data, pkt_size);
5297 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
5302 static int rtl8169_rx_interrupt(struct net_device *dev,
5303 struct rtl8169_private *tp,
5304 void __iomem *ioaddr, u32 budget)
5306 unsigned int cur_rx, rx_left;
5309 cur_rx = tp->cur_rx;
5310 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
5311 rx_left = min(rx_left, budget);
5313 for (; rx_left > 0; rx_left--, cur_rx++) {
5314 unsigned int entry = cur_rx % NUM_RX_DESC;
5315 struct RxDesc *desc = tp->RxDescArray + entry;
5319 status = le32_to_cpu(desc->opts1);
5321 if (status & DescOwn)
5323 if (unlikely(status & RxRES)) {
5324 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
5326 dev->stats.rx_errors++;
5327 if (status & (RxRWT | RxRUNT))
5328 dev->stats.rx_length_errors++;
5330 dev->stats.rx_crc_errors++;
5331 if (status & RxFOVF) {
5332 rtl8169_schedule_work(dev, rtl8169_reset_task);
5333 dev->stats.rx_fifo_errors++;
5335 rtl8169_mark_to_asic(desc, rx_buf_sz);
5337 struct sk_buff *skb;
5338 dma_addr_t addr = le64_to_cpu(desc->addr);
5339 int pkt_size = (status & 0x00001FFF) - 4;
5342 * The driver does not support incoming fragmented
5343 * frames. They are seen as a symptom of over-mtu
5346 if (unlikely(rtl8169_fragmented_frame(status))) {
5347 dev->stats.rx_dropped++;
5348 dev->stats.rx_length_errors++;
5349 rtl8169_mark_to_asic(desc, rx_buf_sz);
5353 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
5354 tp, pkt_size, addr);
5355 rtl8169_mark_to_asic(desc, rx_buf_sz);
5357 dev->stats.rx_dropped++;
5361 rtl8169_rx_csum(skb, status);
5362 skb_put(skb, pkt_size);
5363 skb->protocol = eth_type_trans(skb, dev);
5365 rtl8169_rx_vlan_tag(desc, skb);
5367 napi_gro_receive(&tp->napi, skb);
5369 dev->stats.rx_bytes += pkt_size;
5370 dev->stats.rx_packets++;
5373 /* Work around for AMD plateform. */
5374 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
5375 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
5381 count = cur_rx - tp->cur_rx;
5382 tp->cur_rx = cur_rx;
5384 tp->dirty_rx += count;
5389 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
5391 struct net_device *dev = dev_instance;
5392 struct rtl8169_private *tp = netdev_priv(dev);
5393 void __iomem *ioaddr = tp->mmio_addr;
5397 /* loop handling interrupts until we have no new ones or
5398 * we hit a invalid/hotplug case.
5400 status = RTL_R16(IntrStatus);
5401 while (status && status != 0xffff) {
5404 /* Handle all of the error cases first. These will reset
5405 * the chip, so just exit the loop.
5407 if (unlikely(!netif_running(dev))) {
5408 rtl8169_hw_reset(tp);
5412 if (unlikely(status & RxFIFOOver)) {
5413 switch (tp->mac_version) {
5414 /* Work around for rx fifo overflow */
5415 case RTL_GIGA_MAC_VER_11:
5416 case RTL_GIGA_MAC_VER_22:
5417 case RTL_GIGA_MAC_VER_26:
5418 netif_stop_queue(dev);
5419 rtl8169_tx_timeout(dev);
5421 /* Testers needed. */
5422 case RTL_GIGA_MAC_VER_17:
5423 case RTL_GIGA_MAC_VER_19:
5424 case RTL_GIGA_MAC_VER_20:
5425 case RTL_GIGA_MAC_VER_21:
5426 case RTL_GIGA_MAC_VER_23:
5427 case RTL_GIGA_MAC_VER_24:
5428 case RTL_GIGA_MAC_VER_27:
5429 case RTL_GIGA_MAC_VER_28:
5430 case RTL_GIGA_MAC_VER_31:
5431 /* Experimental science. Pktgen proof. */
5432 case RTL_GIGA_MAC_VER_12:
5433 case RTL_GIGA_MAC_VER_25:
5434 if (status == RxFIFOOver)
5442 if (unlikely(status & SYSErr)) {
5443 rtl8169_pcierr_interrupt(dev);
5447 if (status & LinkChg)
5448 __rtl8169_check_link_status(dev, tp, ioaddr, true);
5450 /* We need to see the lastest version of tp->intr_mask to
5451 * avoid ignoring an MSI interrupt and having to wait for
5452 * another event which may never come.
5455 if (status & tp->intr_mask & tp->napi_event) {
5456 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
5457 tp->intr_mask = ~tp->napi_event;
5459 if (likely(napi_schedule_prep(&tp->napi)))
5460 __napi_schedule(&tp->napi);
5462 netif_info(tp, intr, dev,
5463 "interrupt %04x in poll\n", status);
5466 /* We only get a new MSI interrupt when all active irq
5467 * sources on the chip have been acknowledged. So, ack
5468 * everything we've seen and check if new sources have become
5469 * active to avoid blocking all interrupts from the chip.
5472 (status & RxFIFOOver) ? (status | RxOverflow) : status);
5473 status = RTL_R16(IntrStatus);
5476 return IRQ_RETVAL(handled);
5479 static int rtl8169_poll(struct napi_struct *napi, int budget)
5481 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5482 struct net_device *dev = tp->dev;
5483 void __iomem *ioaddr = tp->mmio_addr;
5486 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
5487 rtl8169_tx_interrupt(dev, tp, ioaddr);
5489 if (work_done < budget) {
5490 napi_complete(napi);
5492 /* We need for force the visibility of tp->intr_mask
5493 * for other CPUs, as we can loose an MSI interrupt
5494 * and potentially wait for a retransmit timeout if we don't.
5495 * The posted write to IntrMask is safe, as it will
5496 * eventually make it to the chip and we won't loose anything
5499 tp->intr_mask = 0xffff;
5501 RTL_W16(IntrMask, tp->intr_event);
5507 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
5509 struct rtl8169_private *tp = netdev_priv(dev);
5511 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5514 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
5515 RTL_W32(RxMissed, 0);
5518 static void rtl8169_down(struct net_device *dev)
5520 struct rtl8169_private *tp = netdev_priv(dev);
5521 void __iomem *ioaddr = tp->mmio_addr;
5523 del_timer_sync(&tp->timer);
5525 netif_stop_queue(dev);
5527 napi_disable(&tp->napi);
5529 spin_lock_irq(&tp->lock);
5531 rtl8169_hw_reset(tp);
5533 * At this point device interrupts can not be enabled in any function,
5534 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
5535 * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
5537 rtl8169_rx_missed(dev, ioaddr);
5539 spin_unlock_irq(&tp->lock);
5541 synchronize_irq(dev->irq);
5543 /* Give a racing hard_start_xmit a few cycles to complete. */
5544 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
5546 rtl8169_tx_clear(tp);
5548 rtl8169_rx_clear(tp);
5550 rtl_pll_power_down(tp);
5553 static int rtl8169_close(struct net_device *dev)
5555 struct rtl8169_private *tp = netdev_priv(dev);
5556 struct pci_dev *pdev = tp->pci_dev;
5558 pm_runtime_get_sync(&pdev->dev);
5560 /* Update counters before going down */
5561 rtl8169_update_counters(dev);
5565 free_irq(dev->irq, dev);
5567 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5569 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5571 tp->TxDescArray = NULL;
5572 tp->RxDescArray = NULL;
5574 pm_runtime_put_sync(&pdev->dev);
5579 static void rtl_set_rx_mode(struct net_device *dev)
5581 struct rtl8169_private *tp = netdev_priv(dev);
5582 void __iomem *ioaddr = tp->mmio_addr;
5583 unsigned long flags;
5584 u32 mc_filter[2]; /* Multicast hash filter */
5588 if (dev->flags & IFF_PROMISC) {
5589 /* Unconditionally log net taps. */
5590 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
5592 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5594 mc_filter[1] = mc_filter[0] = 0xffffffff;
5595 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
5596 (dev->flags & IFF_ALLMULTI)) {
5597 /* Too many to filter perfectly -- accept all multicasts. */
5598 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5599 mc_filter[1] = mc_filter[0] = 0xffffffff;
5601 struct netdev_hw_addr *ha;
5603 rx_mode = AcceptBroadcast | AcceptMyPhys;
5604 mc_filter[1] = mc_filter[0] = 0;
5605 netdev_for_each_mc_addr(ha, dev) {
5606 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
5607 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5608 rx_mode |= AcceptMulticast;
5612 spin_lock_irqsave(&tp->lock, flags);
5614 tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
5616 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
5617 u32 data = mc_filter[0];
5619 mc_filter[0] = swab32(mc_filter[1]);
5620 mc_filter[1] = swab32(data);
5623 RTL_W32(MAR0 + 4, mc_filter[1]);
5624 RTL_W32(MAR0 + 0, mc_filter[0]);
5626 RTL_W32(RxConfig, tmp);
5628 spin_unlock_irqrestore(&tp->lock, flags);
5632 * rtl8169_get_stats - Get rtl8169 read/write statistics
5633 * @dev: The Ethernet Device to get statistics for
5635 * Get TX/RX statistics for rtl8169
5637 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
5639 struct rtl8169_private *tp = netdev_priv(dev);
5640 void __iomem *ioaddr = tp->mmio_addr;
5641 unsigned long flags;
5643 if (netif_running(dev)) {
5644 spin_lock_irqsave(&tp->lock, flags);
5645 rtl8169_rx_missed(dev, ioaddr);
5646 spin_unlock_irqrestore(&tp->lock, flags);
5652 static void rtl8169_net_suspend(struct net_device *dev)
5654 struct rtl8169_private *tp = netdev_priv(dev);
5656 if (!netif_running(dev))
5659 rtl_pll_power_down(tp);
5661 netif_device_detach(dev);
5662 netif_stop_queue(dev);
5667 static int rtl8169_suspend(struct device *device)
5669 struct pci_dev *pdev = to_pci_dev(device);
5670 struct net_device *dev = pci_get_drvdata(pdev);
5672 rtl8169_net_suspend(dev);
5677 static void __rtl8169_resume(struct net_device *dev)
5679 struct rtl8169_private *tp = netdev_priv(dev);
5681 netif_device_attach(dev);
5683 rtl_pll_power_up(tp);
5685 rtl8169_schedule_work(dev, rtl8169_reset_task);
5688 static int rtl8169_resume(struct device *device)
5690 struct pci_dev *pdev = to_pci_dev(device);
5691 struct net_device *dev = pci_get_drvdata(pdev);
5692 struct rtl8169_private *tp = netdev_priv(dev);
5694 rtl8169_init_phy(dev, tp);
5696 if (netif_running(dev))
5697 __rtl8169_resume(dev);
5702 static int rtl8169_runtime_suspend(struct device *device)
5704 struct pci_dev *pdev = to_pci_dev(device);
5705 struct net_device *dev = pci_get_drvdata(pdev);
5706 struct rtl8169_private *tp = netdev_priv(dev);
5708 if (!tp->TxDescArray)
5711 spin_lock_irq(&tp->lock);
5712 tp->saved_wolopts = __rtl8169_get_wol(tp);
5713 __rtl8169_set_wol(tp, WAKE_ANY);
5714 spin_unlock_irq(&tp->lock);
5716 rtl8169_net_suspend(dev);
5721 static int rtl8169_runtime_resume(struct device *device)
5723 struct pci_dev *pdev = to_pci_dev(device);
5724 struct net_device *dev = pci_get_drvdata(pdev);
5725 struct rtl8169_private *tp = netdev_priv(dev);
5727 if (!tp->TxDescArray)
5730 spin_lock_irq(&tp->lock);
5731 __rtl8169_set_wol(tp, tp->saved_wolopts);
5732 tp->saved_wolopts = 0;
5733 spin_unlock_irq(&tp->lock);
5735 rtl8169_init_phy(dev, tp);
5737 __rtl8169_resume(dev);
5742 static int rtl8169_runtime_idle(struct device *device)
5744 struct pci_dev *pdev = to_pci_dev(device);
5745 struct net_device *dev = pci_get_drvdata(pdev);
5746 struct rtl8169_private *tp = netdev_priv(dev);
5748 return tp->TxDescArray ? -EBUSY : 0;
5751 static const struct dev_pm_ops rtl8169_pm_ops = {
5752 .suspend = rtl8169_suspend,
5753 .resume = rtl8169_resume,
5754 .freeze = rtl8169_suspend,
5755 .thaw = rtl8169_resume,
5756 .poweroff = rtl8169_suspend,
5757 .restore = rtl8169_resume,
5758 .runtime_suspend = rtl8169_runtime_suspend,
5759 .runtime_resume = rtl8169_runtime_resume,
5760 .runtime_idle = rtl8169_runtime_idle,
5763 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
5765 #else /* !CONFIG_PM */
5767 #define RTL8169_PM_OPS NULL
5769 #endif /* !CONFIG_PM */
5771 static void rtl_shutdown(struct pci_dev *pdev)
5773 struct net_device *dev = pci_get_drvdata(pdev);
5774 struct rtl8169_private *tp = netdev_priv(dev);
5775 void __iomem *ioaddr = tp->mmio_addr;
5777 rtl8169_net_suspend(dev);
5779 /* Restore original MAC address */
5780 rtl_rar_set(tp, dev->perm_addr);
5782 spin_lock_irq(&tp->lock);
5784 rtl8169_hw_reset(tp);
5786 spin_unlock_irq(&tp->lock);
5788 if (system_state == SYSTEM_POWER_OFF) {
5789 /* WoL fails with 8168b when the receiver is disabled. */
5790 if ((tp->mac_version == RTL_GIGA_MAC_VER_11 ||
5791 tp->mac_version == RTL_GIGA_MAC_VER_12 ||
5792 tp->mac_version == RTL_GIGA_MAC_VER_17) &&
5793 (tp->features & RTL_FEATURE_WOL)) {
5794 pci_clear_master(pdev);
5796 RTL_W8(ChipCmd, CmdRxEnb);
5801 pci_wake_from_d3(pdev, true);
5802 pci_set_power_state(pdev, PCI_D3hot);
5806 static struct pci_driver rtl8169_pci_driver = {
5808 .id_table = rtl8169_pci_tbl,
5809 .probe = rtl8169_init_one,
5810 .remove = __devexit_p(rtl8169_remove_one),
5811 .shutdown = rtl_shutdown,
5812 .driver.pm = RTL8169_PM_OPS,
5815 static int __init rtl8169_init_module(void)
5817 return pci_register_driver(&rtl8169_pci_driver);
5820 static void __exit rtl8169_cleanup_module(void)
5822 pci_unregister_driver(&rtl8169_pci_driver);
5825 module_init(rtl8169_init_module);
5826 module_exit(rtl8169_cleanup_module);