2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/firmware.h>
29 #include <asm/system.h>
33 #define RTL8169_VERSION "2.3LK-NAPI"
34 #define MODULENAME "r8169"
35 #define PFX MODULENAME ": "
37 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
38 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
41 #define assert(expr) \
43 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
44 #expr,__FILE__,__func__,__LINE__); \
46 #define dprintk(fmt, args...) \
47 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
49 #define assert(expr) do {} while (0)
50 #define dprintk(fmt, args...) do {} while (0)
51 #endif /* RTL8169_DEBUG */
53 #define R8169_MSG_DEFAULT \
54 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
56 #define TX_BUFFS_AVAIL(tp) \
57 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
59 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
60 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
61 static const int multicast_filter_limit = 32;
63 /* MAC address length */
64 #define MAC_ADDR_LEN 6
66 #define MAX_READ_REQUEST_SHIFT 12
67 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
68 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
69 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
70 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
71 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
73 #define R8169_REGS_SIZE 256
74 #define R8169_NAPI_WEIGHT 64
75 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
76 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
77 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
78 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
79 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
81 #define RTL8169_TX_TIMEOUT (6*HZ)
82 #define RTL8169_PHY_TIMEOUT (10*HZ)
84 #define RTL_EEPROM_SIG cpu_to_le32(0x8129)
85 #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
86 #define RTL_EEPROM_SIG_ADDR 0x0000
88 /* write/read MMIO register */
89 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
90 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
91 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
92 #define RTL_R8(reg) readb (ioaddr + (reg))
93 #define RTL_R16(reg) readw (ioaddr + (reg))
94 #define RTL_R32(reg) readl (ioaddr + (reg))
97 RTL_GIGA_MAC_NONE = 0x00,
98 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
99 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
100 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
101 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
102 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
103 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
104 RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
105 RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
106 RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
107 RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
108 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
109 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
110 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
111 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
112 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
113 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
114 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
115 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
116 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
117 RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
118 RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
119 RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
120 RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
121 RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
122 RTL_GIGA_MAC_VER_25 = 0x19, // 8168D
123 RTL_GIGA_MAC_VER_26 = 0x1a, // 8168D
124 RTL_GIGA_MAC_VER_27 = 0x1b, // 8168DP
125 RTL_GIGA_MAC_VER_28 = 0x1c, // 8168DP
128 #define _R(NAME,MAC,MASK) \
129 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
131 static const struct {
134 u32 RxConfigMask; /* Clears the bits supported by this chip */
135 } rtl_chip_info[] = {
136 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
137 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
138 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
139 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
140 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
141 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
142 _R("RTL8102e", RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
143 _R("RTL8102e", RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
144 _R("RTL8102e", RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
145 _R("RTL8101e", RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
146 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
147 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
148 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
149 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
150 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
151 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
152 _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
153 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
154 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
155 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E
156 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E
157 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E
158 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E
159 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E
160 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25, 0xff7e1880), // PCI-E
161 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_26, 0xff7e1880), // PCI-E
162 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_27, 0xff7e1880), // PCI-E
163 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_28, 0xff7e1880) // PCI-E
173 static void rtl_hw_start_8169(struct net_device *);
174 static void rtl_hw_start_8168(struct net_device *);
175 static void rtl_hw_start_8101(struct net_device *);
177 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
178 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
179 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
180 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
181 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
182 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
183 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
184 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
185 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
186 { PCI_VENDOR_ID_LINKSYS, 0x1032,
187 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
189 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
193 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
195 static int rx_buf_sz = 16383;
202 MAC0 = 0, /* Ethernet hardware address. */
204 MAR0 = 8, /* Multicast filter. */
205 CounterAddrLow = 0x10,
206 CounterAddrHigh = 0x14,
207 TxDescStartAddrLow = 0x20,
208 TxDescStartAddrHigh = 0x24,
209 TxHDescStartAddrLow = 0x28,
210 TxHDescStartAddrHigh = 0x2c,
233 RxDescAddrLow = 0xe4,
234 RxDescAddrHigh = 0xe8,
235 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
237 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
239 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
241 #define TxPacketMax (8064 >> 7)
244 FuncEventMask = 0xf4,
245 FuncPresetState = 0xf8,
246 FuncForceEvent = 0xfc,
249 enum rtl8110_registers {
255 enum rtl8168_8101_registers {
258 #define CSIAR_FLAG 0x80000000
259 #define CSIAR_WRITE_CMD 0x80000000
260 #define CSIAR_BYTE_ENABLE 0x0f
261 #define CSIAR_BYTE_ENABLE_SHIFT 12
262 #define CSIAR_ADDR_MASK 0x0fff
265 #define EPHYAR_FLAG 0x80000000
266 #define EPHYAR_WRITE_CMD 0x80000000
267 #define EPHYAR_REG_MASK 0x1f
268 #define EPHYAR_REG_SHIFT 16
269 #define EPHYAR_DATA_MASK 0xffff
271 #define FIX_NAK_1 (1 << 4)
272 #define FIX_NAK_2 (1 << 3)
274 #define EFUSEAR_FLAG 0x80000000
275 #define EFUSEAR_WRITE_CMD 0x80000000
276 #define EFUSEAR_READ_CMD 0x00000000
277 #define EFUSEAR_REG_MASK 0x03ff
278 #define EFUSEAR_REG_SHIFT 8
279 #define EFUSEAR_DATA_MASK 0xff
282 enum rtl8168_registers {
285 #define ERIAR_FLAG 0x80000000
286 #define ERIAR_WRITE_CMD 0x80000000
287 #define ERIAR_READ_CMD 0x00000000
288 #define ERIAR_ADDR_BYTE_ALIGN 4
289 #define ERIAR_EXGMAC 0
292 #define ERIAR_TYPE_SHIFT 16
293 #define ERIAR_BYTEEN 0x0f
294 #define ERIAR_BYTEEN_SHIFT 12
295 EPHY_RXER_NUM = 0x7c,
296 OCPDR = 0xb0, /* OCP GPHY access */
297 #define OCPDR_WRITE_CMD 0x80000000
298 #define OCPDR_READ_CMD 0x00000000
299 #define OCPDR_REG_MASK 0x7f
300 #define OCPDR_GPHY_REG_SHIFT 16
301 #define OCPDR_DATA_MASK 0xffff
303 #define OCPAR_FLAG 0x80000000
304 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
305 #define OCPAR_GPHY_READ_CMD 0x0000f060
306 RDSAR1 = 0xd0 /* 8168c only. Undocumented on 8168dp */
309 enum rtl_register_content {
310 /* InterruptStatusBits */
314 TxDescUnavail = 0x0080,
336 /* TXPoll register p.5 */
337 HPQ = 0x80, /* Poll cmd on the high prio queue */
338 NPQ = 0x40, /* Poll cmd on the low prio queue */
339 FSWInt = 0x01, /* Forced software interrupt */
343 Cfg9346_Unlock = 0xc0,
348 AcceptBroadcast = 0x08,
349 AcceptMulticast = 0x04,
351 AcceptAllPhys = 0x01,
358 TxInterFrameGapShift = 24,
359 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
361 /* Config1 register p.24 */
364 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
365 Speed_down = (1 << 4),
369 PMEnable = (1 << 0), /* Power Management Enable */
371 /* Config2 register p. 25 */
372 PCI_Clock_66MHz = 0x01,
373 PCI_Clock_33MHz = 0x00,
375 /* Config3 register p.25 */
376 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
377 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
378 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
380 /* Config5 register p.27 */
381 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
382 MWF = (1 << 5), /* Accept Multicast wakeup frame */
383 UWF = (1 << 4), /* Accept Unicast wakeup frame */
384 LanWake = (1 << 1), /* LanWake enable/disable */
385 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
388 TBIReset = 0x80000000,
389 TBILoopback = 0x40000000,
390 TBINwEnable = 0x20000000,
391 TBINwRestart = 0x10000000,
392 TBILinkOk = 0x02000000,
393 TBINwComplete = 0x01000000,
396 EnableBist = (1 << 15), // 8168 8101
397 Mac_dbgo_oe = (1 << 14), // 8168 8101
398 Normal_mode = (1 << 13), // unused
399 Force_half_dup = (1 << 12), // 8168 8101
400 Force_rxflow_en = (1 << 11), // 8168 8101
401 Force_txflow_en = (1 << 10), // 8168 8101
402 Cxpl_dbg_sel = (1 << 9), // 8168 8101
403 ASF = (1 << 8), // 8168 8101
404 PktCntrDisable = (1 << 7), // 8168 8101
405 Mac_dbgo_sel = 0x001c, // 8168
410 INTT_0 = 0x0000, // 8168
411 INTT_1 = 0x0001, // 8168
412 INTT_2 = 0x0002, // 8168
413 INTT_3 = 0x0003, // 8168
415 /* rtl8169_PHYstatus */
426 TBILinkOK = 0x02000000,
428 /* DumpCounterCommand */
432 enum desc_status_bit {
433 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
434 RingEnd = (1 << 30), /* End of descriptor ring */
435 FirstFrag = (1 << 29), /* First segment of a packet */
436 LastFrag = (1 << 28), /* Final segment of a packet */
439 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
440 MSSShift = 16, /* MSS value position */
441 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
442 IPCS = (1 << 18), /* Calculate IP checksum */
443 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
444 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
445 TxVlanTag = (1 << 17), /* Add VLAN tag */
448 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
449 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
451 #define RxProtoUDP (PID1)
452 #define RxProtoTCP (PID0)
453 #define RxProtoIP (PID1 | PID0)
454 #define RxProtoMask RxProtoIP
456 IPFail = (1 << 16), /* IP checksum failed */
457 UDPFail = (1 << 15), /* UDP/IP checksum failed */
458 TCPFail = (1 << 14), /* TCP/IP checksum failed */
459 RxVlanTag = (1 << 16), /* VLAN tag available */
462 #define RsvdMask 0x3fffc000
479 u8 __pad[sizeof(void *) - sizeof(u32)];
483 RTL_FEATURE_WOL = (1 << 0),
484 RTL_FEATURE_MSI = (1 << 1),
485 RTL_FEATURE_GMII = (1 << 2),
488 struct rtl8169_counters {
495 __le32 tx_one_collision;
496 __le32 tx_multi_collision;
504 struct rtl8169_private {
505 void __iomem *mmio_addr; /* memory map physical address */
506 struct pci_dev *pci_dev; /* Index of PCI device */
507 struct net_device *dev;
508 struct napi_struct napi;
509 spinlock_t lock; /* spin lock flag */
513 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
514 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
517 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
518 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
519 dma_addr_t TxPhyAddr;
520 dma_addr_t RxPhyAddr;
521 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
522 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
523 struct timer_list timer;
528 int phy_1000_ctrl_reg;
529 #ifdef CONFIG_R8169_VLAN
530 struct vlan_group *vlgrp;
534 void (*write)(void __iomem *, int, int);
535 int (*read)(void __iomem *, int);
538 struct pll_power_ops {
539 void (*down)(struct rtl8169_private *);
540 void (*up)(struct rtl8169_private *);
543 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
544 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
545 void (*phy_reset_enable)(struct rtl8169_private *tp);
546 void (*hw_start)(struct net_device *);
547 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
548 unsigned int (*link_ok)(void __iomem *);
549 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
551 struct delayed_work task;
554 struct mii_if_info mii;
555 struct rtl8169_counters counters;
558 const struct firmware *fw;
561 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
562 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
563 module_param(use_dac, int, 0);
564 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
565 module_param_named(debug, debug.msg_enable, int, 0);
566 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
567 MODULE_LICENSE("GPL");
568 MODULE_VERSION(RTL8169_VERSION);
569 MODULE_FIRMWARE(FIRMWARE_8168D_1);
570 MODULE_FIRMWARE(FIRMWARE_8168D_2);
572 static int rtl8169_open(struct net_device *dev);
573 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
574 struct net_device *dev);
575 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
576 static int rtl8169_init_ring(struct net_device *dev);
577 static void rtl_hw_start(struct net_device *dev);
578 static int rtl8169_close(struct net_device *dev);
579 static void rtl_set_rx_mode(struct net_device *dev);
580 static void rtl8169_tx_timeout(struct net_device *dev);
581 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
582 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
583 void __iomem *, u32 budget);
584 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
585 static void rtl8169_down(struct net_device *dev);
586 static void rtl8169_rx_clear(struct rtl8169_private *tp);
587 static int rtl8169_poll(struct napi_struct *napi, int budget);
589 static const unsigned int rtl8169_rx_config =
590 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
592 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
594 void __iomem *ioaddr = tp->mmio_addr;
597 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
598 for (i = 0; i < 20; i++) {
600 if (RTL_R32(OCPAR) & OCPAR_FLAG)
603 return RTL_R32(OCPDR);
606 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
608 void __iomem *ioaddr = tp->mmio_addr;
611 RTL_W32(OCPDR, data);
612 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
613 for (i = 0; i < 20; i++) {
615 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
620 static void rtl8168_oob_notify(void __iomem *ioaddr, u8 cmd)
625 RTL_W32(ERIAR, 0x800010e8);
627 for (i = 0; i < 5; i++) {
629 if (!(RTL_R32(ERIDR) & ERIAR_FLAG))
633 ocp_write(ioaddr, 0x1, 0x30, 0x00000001);
636 #define OOB_CMD_RESET 0x00
637 #define OOB_CMD_DRIVER_START 0x05
638 #define OOB_CMD_DRIVER_STOP 0x06
640 static void rtl8168_driver_start(struct rtl8169_private *tp)
644 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
646 for (i = 0; i < 10; i++) {
648 if (ocp_read(tp, 0x0f, 0x0010) & 0x00000800)
653 static void rtl8168_driver_stop(struct rtl8169_private *tp)
657 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
659 for (i = 0; i < 10; i++) {
661 if ((ocp_read(tp, 0x0f, 0x0010) & 0x00000800) == 0)
667 static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
671 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
673 for (i = 20; i > 0; i--) {
675 * Check if the RTL8169 has completed writing to the specified
678 if (!(RTL_R32(PHYAR) & 0x80000000))
683 * According to hardware specs a 20us delay is required after write
684 * complete indication, but before sending next command.
689 static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
693 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
695 for (i = 20; i > 0; i--) {
697 * Check if the RTL8169 has completed retrieving data from
698 * the specified MII register.
700 if (RTL_R32(PHYAR) & 0x80000000) {
701 value = RTL_R32(PHYAR) & 0xffff;
707 * According to hardware specs a 20us delay is required after read
708 * complete indication, but before sending next command.
715 static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
719 RTL_W32(OCPDR, data |
720 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
721 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
722 RTL_W32(EPHY_RXER_NUM, 0);
724 for (i = 0; i < 100; i++) {
726 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
731 static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
733 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
734 (value & OCPDR_DATA_MASK));
737 static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
741 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
744 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
745 RTL_W32(EPHY_RXER_NUM, 0);
747 for (i = 0; i < 100; i++) {
749 if (RTL_R32(OCPAR) & OCPAR_FLAG)
753 return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
756 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
758 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
760 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
763 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
765 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
768 static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
770 r8168dp_2_mdio_start(ioaddr);
772 r8169_mdio_write(ioaddr, reg_addr, value);
774 r8168dp_2_mdio_stop(ioaddr);
777 static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
781 r8168dp_2_mdio_start(ioaddr);
783 value = r8169_mdio_read(ioaddr, reg_addr);
785 r8168dp_2_mdio_stop(ioaddr);
790 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
792 tp->mdio_ops.write(tp->mmio_addr, location, val);
795 static int rtl_readphy(struct rtl8169_private *tp, int location)
797 return tp->mdio_ops.read(tp->mmio_addr, location);
800 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
802 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
805 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
809 val = rtl_readphy(tp, reg_addr);
810 rtl_writephy(tp, reg_addr, (val | p) & ~m);
813 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
816 struct rtl8169_private *tp = netdev_priv(dev);
818 rtl_writephy(tp, location, val);
821 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
823 struct rtl8169_private *tp = netdev_priv(dev);
825 return rtl_readphy(tp, location);
828 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
832 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
833 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
835 for (i = 0; i < 100; i++) {
836 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
842 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
847 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
849 for (i = 0; i < 100; i++) {
850 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
851 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
860 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
864 RTL_W32(CSIDR, value);
865 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
866 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
868 for (i = 0; i < 100; i++) {
869 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
875 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
880 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
881 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
883 for (i = 0; i < 100; i++) {
884 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
885 value = RTL_R32(CSIDR);
894 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
899 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
901 for (i = 0; i < 300; i++) {
902 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
903 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
912 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
914 RTL_W16(IntrMask, 0x0000);
916 RTL_W16(IntrStatus, 0xffff);
919 static void rtl8169_asic_down(void __iomem *ioaddr)
921 RTL_W8(ChipCmd, 0x00);
922 rtl8169_irq_mask_and_ack(ioaddr);
926 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
928 void __iomem *ioaddr = tp->mmio_addr;
930 return RTL_R32(TBICSR) & TBIReset;
933 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
935 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
938 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
940 return RTL_R32(TBICSR) & TBILinkOk;
943 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
945 return RTL_R8(PHYstatus) & LinkStatus;
948 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
950 void __iomem *ioaddr = tp->mmio_addr;
952 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
955 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
959 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
960 rtl_writephy(tp, MII_BMCR, val & 0xffff);
963 static void __rtl8169_check_link_status(struct net_device *dev,
964 struct rtl8169_private *tp,
965 void __iomem *ioaddr,
970 spin_lock_irqsave(&tp->lock, flags);
971 if (tp->link_ok(ioaddr)) {
972 /* This is to cancel a scheduled suspend if there's one. */
974 pm_request_resume(&tp->pci_dev->dev);
975 netif_carrier_on(dev);
977 netif_info(tp, ifup, dev, "link up\n");
979 netif_carrier_off(dev);
980 netif_info(tp, ifdown, dev, "link down\n");
982 pm_schedule_suspend(&tp->pci_dev->dev, 100);
984 spin_unlock_irqrestore(&tp->lock, flags);
987 static void rtl8169_check_link_status(struct net_device *dev,
988 struct rtl8169_private *tp,
989 void __iomem *ioaddr)
991 __rtl8169_check_link_status(dev, tp, ioaddr, false);
994 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
996 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
998 void __iomem *ioaddr = tp->mmio_addr;
1002 options = RTL_R8(Config1);
1003 if (!(options & PMEnable))
1006 options = RTL_R8(Config3);
1007 if (options & LinkUp)
1008 wolopts |= WAKE_PHY;
1009 if (options & MagicPacket)
1010 wolopts |= WAKE_MAGIC;
1012 options = RTL_R8(Config5);
1014 wolopts |= WAKE_UCAST;
1016 wolopts |= WAKE_BCAST;
1018 wolopts |= WAKE_MCAST;
1023 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1025 struct rtl8169_private *tp = netdev_priv(dev);
1027 spin_lock_irq(&tp->lock);
1029 wol->supported = WAKE_ANY;
1030 wol->wolopts = __rtl8169_get_wol(tp);
1032 spin_unlock_irq(&tp->lock);
1035 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1037 void __iomem *ioaddr = tp->mmio_addr;
1039 static const struct {
1044 { WAKE_ANY, Config1, PMEnable },
1045 { WAKE_PHY, Config3, LinkUp },
1046 { WAKE_MAGIC, Config3, MagicPacket },
1047 { WAKE_UCAST, Config5, UWF },
1048 { WAKE_BCAST, Config5, BWF },
1049 { WAKE_MCAST, Config5, MWF },
1050 { WAKE_ANY, Config5, LanWake }
1053 RTL_W8(Cfg9346, Cfg9346_Unlock);
1055 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1056 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1057 if (wolopts & cfg[i].opt)
1058 options |= cfg[i].mask;
1059 RTL_W8(cfg[i].reg, options);
1062 RTL_W8(Cfg9346, Cfg9346_Lock);
1065 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1067 struct rtl8169_private *tp = netdev_priv(dev);
1069 spin_lock_irq(&tp->lock);
1072 tp->features |= RTL_FEATURE_WOL;
1074 tp->features &= ~RTL_FEATURE_WOL;
1075 __rtl8169_set_wol(tp, wol->wolopts);
1076 spin_unlock_irq(&tp->lock);
1078 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1083 static void rtl8169_get_drvinfo(struct net_device *dev,
1084 struct ethtool_drvinfo *info)
1086 struct rtl8169_private *tp = netdev_priv(dev);
1088 strcpy(info->driver, MODULENAME);
1089 strcpy(info->version, RTL8169_VERSION);
1090 strcpy(info->bus_info, pci_name(tp->pci_dev));
1093 static int rtl8169_get_regs_len(struct net_device *dev)
1095 return R8169_REGS_SIZE;
1098 static int rtl8169_set_speed_tbi(struct net_device *dev,
1099 u8 autoneg, u16 speed, u8 duplex)
1101 struct rtl8169_private *tp = netdev_priv(dev);
1102 void __iomem *ioaddr = tp->mmio_addr;
1106 reg = RTL_R32(TBICSR);
1107 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1108 (duplex == DUPLEX_FULL)) {
1109 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1110 } else if (autoneg == AUTONEG_ENABLE)
1111 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1113 netif_warn(tp, link, dev,
1114 "incorrect speed setting refused in TBI mode\n");
1121 static int rtl8169_set_speed_xmii(struct net_device *dev,
1122 u8 autoneg, u16 speed, u8 duplex)
1124 struct rtl8169_private *tp = netdev_priv(dev);
1125 int giga_ctrl, bmcr;
1127 rtl_writephy(tp, 0x1f, 0x0000);
1129 if (autoneg == AUTONEG_ENABLE) {
1132 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1133 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
1134 ADVERTISE_100HALF | ADVERTISE_100FULL);
1135 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1137 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1138 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1140 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1141 if ((tp->mac_version != RTL_GIGA_MAC_VER_07) &&
1142 (tp->mac_version != RTL_GIGA_MAC_VER_08) &&
1143 (tp->mac_version != RTL_GIGA_MAC_VER_09) &&
1144 (tp->mac_version != RTL_GIGA_MAC_VER_10) &&
1145 (tp->mac_version != RTL_GIGA_MAC_VER_13) &&
1146 (tp->mac_version != RTL_GIGA_MAC_VER_14) &&
1147 (tp->mac_version != RTL_GIGA_MAC_VER_15) &&
1148 (tp->mac_version != RTL_GIGA_MAC_VER_16)) {
1149 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
1151 netif_info(tp, link, dev,
1152 "PHY does not support 1000Mbps\n");
1155 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1157 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1158 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1162 if (speed == SPEED_10)
1164 else if (speed == SPEED_100)
1165 bmcr = BMCR_SPEED100;
1169 if (duplex == DUPLEX_FULL)
1170 bmcr |= BMCR_FULLDPLX;
1173 tp->phy_1000_ctrl_reg = giga_ctrl;
1175 rtl_writephy(tp, MII_BMCR, bmcr);
1177 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1178 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
1179 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1180 rtl_writephy(tp, 0x17, 0x2138);
1181 rtl_writephy(tp, 0x0e, 0x0260);
1183 rtl_writephy(tp, 0x17, 0x2108);
1184 rtl_writephy(tp, 0x0e, 0x0000);
1191 static int rtl8169_set_speed(struct net_device *dev,
1192 u8 autoneg, u16 speed, u8 duplex)
1194 struct rtl8169_private *tp = netdev_priv(dev);
1197 ret = tp->set_speed(dev, autoneg, speed, duplex);
1199 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1200 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1205 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1207 struct rtl8169_private *tp = netdev_priv(dev);
1208 unsigned long flags;
1211 spin_lock_irqsave(&tp->lock, flags);
1212 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
1213 spin_unlock_irqrestore(&tp->lock, flags);
1218 static u32 rtl8169_get_rx_csum(struct net_device *dev)
1220 struct rtl8169_private *tp = netdev_priv(dev);
1222 return tp->cp_cmd & RxChkSum;
1225 static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
1227 struct rtl8169_private *tp = netdev_priv(dev);
1228 void __iomem *ioaddr = tp->mmio_addr;
1229 unsigned long flags;
1231 spin_lock_irqsave(&tp->lock, flags);
1234 tp->cp_cmd |= RxChkSum;
1236 tp->cp_cmd &= ~RxChkSum;
1238 RTL_W16(CPlusCmd, tp->cp_cmd);
1241 spin_unlock_irqrestore(&tp->lock, flags);
1246 #ifdef CONFIG_R8169_VLAN
1248 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1249 struct sk_buff *skb)
1251 return (vlan_tx_tag_present(skb)) ?
1252 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1255 static void rtl8169_vlan_rx_register(struct net_device *dev,
1256 struct vlan_group *grp)
1258 struct rtl8169_private *tp = netdev_priv(dev);
1259 void __iomem *ioaddr = tp->mmio_addr;
1260 unsigned long flags;
1262 spin_lock_irqsave(&tp->lock, flags);
1265 * Do not disable RxVlan on 8110SCd.
1267 if (tp->vlgrp || (tp->mac_version == RTL_GIGA_MAC_VER_05))
1268 tp->cp_cmd |= RxVlan;
1270 tp->cp_cmd &= ~RxVlan;
1271 RTL_W16(CPlusCmd, tp->cp_cmd);
1273 spin_unlock_irqrestore(&tp->lock, flags);
1276 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1277 struct sk_buff *skb, int polling)
1279 u32 opts2 = le32_to_cpu(desc->opts2);
1280 struct vlan_group *vlgrp = tp->vlgrp;
1283 if (vlgrp && (opts2 & RxVlanTag)) {
1284 u16 vtag = swab16(opts2 & 0xffff);
1286 if (likely(polling))
1287 vlan_gro_receive(&tp->napi, vlgrp, vtag, skb);
1289 __vlan_hwaccel_rx(skb, vlgrp, vtag, polling);
1297 #else /* !CONFIG_R8169_VLAN */
1299 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1300 struct sk_buff *skb)
1305 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1306 struct sk_buff *skb, int polling)
1313 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1315 struct rtl8169_private *tp = netdev_priv(dev);
1316 void __iomem *ioaddr = tp->mmio_addr;
1320 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1321 cmd->port = PORT_FIBRE;
1322 cmd->transceiver = XCVR_INTERNAL;
1324 status = RTL_R32(TBICSR);
1325 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1326 cmd->autoneg = !!(status & TBINwEnable);
1328 cmd->speed = SPEED_1000;
1329 cmd->duplex = DUPLEX_FULL; /* Always set */
1334 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1336 struct rtl8169_private *tp = netdev_priv(dev);
1338 return mii_ethtool_gset(&tp->mii, cmd);
1341 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1343 struct rtl8169_private *tp = netdev_priv(dev);
1344 unsigned long flags;
1347 spin_lock_irqsave(&tp->lock, flags);
1349 rc = tp->get_settings(dev, cmd);
1351 spin_unlock_irqrestore(&tp->lock, flags);
1355 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1358 struct rtl8169_private *tp = netdev_priv(dev);
1359 unsigned long flags;
1361 if (regs->len > R8169_REGS_SIZE)
1362 regs->len = R8169_REGS_SIZE;
1364 spin_lock_irqsave(&tp->lock, flags);
1365 memcpy_fromio(p, tp->mmio_addr, regs->len);
1366 spin_unlock_irqrestore(&tp->lock, flags);
1369 static u32 rtl8169_get_msglevel(struct net_device *dev)
1371 struct rtl8169_private *tp = netdev_priv(dev);
1373 return tp->msg_enable;
1376 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1378 struct rtl8169_private *tp = netdev_priv(dev);
1380 tp->msg_enable = value;
1383 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1390 "tx_single_collisions",
1391 "tx_multi_collisions",
1399 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1403 return ARRAY_SIZE(rtl8169_gstrings);
1409 static void rtl8169_update_counters(struct net_device *dev)
1411 struct rtl8169_private *tp = netdev_priv(dev);
1412 void __iomem *ioaddr = tp->mmio_addr;
1413 struct rtl8169_counters *counters;
1417 struct device *d = &tp->pci_dev->dev;
1420 * Some chips are unable to dump tally counters when the receiver
1423 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1426 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1430 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1431 cmd = (u64)paddr & DMA_BIT_MASK(32);
1432 RTL_W32(CounterAddrLow, cmd);
1433 RTL_W32(CounterAddrLow, cmd | CounterDump);
1436 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1437 /* copy updated counters */
1438 memcpy(&tp->counters, counters, sizeof(*counters));
1444 RTL_W32(CounterAddrLow, 0);
1445 RTL_W32(CounterAddrHigh, 0);
1447 dma_free_coherent(d, sizeof(*counters), counters, paddr);
1450 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1451 struct ethtool_stats *stats, u64 *data)
1453 struct rtl8169_private *tp = netdev_priv(dev);
1457 rtl8169_update_counters(dev);
1459 data[0] = le64_to_cpu(tp->counters.tx_packets);
1460 data[1] = le64_to_cpu(tp->counters.rx_packets);
1461 data[2] = le64_to_cpu(tp->counters.tx_errors);
1462 data[3] = le32_to_cpu(tp->counters.rx_errors);
1463 data[4] = le16_to_cpu(tp->counters.rx_missed);
1464 data[5] = le16_to_cpu(tp->counters.align_errors);
1465 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1466 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1467 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1468 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1469 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1470 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1471 data[12] = le16_to_cpu(tp->counters.tx_underun);
1474 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1478 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1483 static const struct ethtool_ops rtl8169_ethtool_ops = {
1484 .get_drvinfo = rtl8169_get_drvinfo,
1485 .get_regs_len = rtl8169_get_regs_len,
1486 .get_link = ethtool_op_get_link,
1487 .get_settings = rtl8169_get_settings,
1488 .set_settings = rtl8169_set_settings,
1489 .get_msglevel = rtl8169_get_msglevel,
1490 .set_msglevel = rtl8169_set_msglevel,
1491 .get_rx_csum = rtl8169_get_rx_csum,
1492 .set_rx_csum = rtl8169_set_rx_csum,
1493 .set_tx_csum = ethtool_op_set_tx_csum,
1494 .set_sg = ethtool_op_set_sg,
1495 .set_tso = ethtool_op_set_tso,
1496 .get_regs = rtl8169_get_regs,
1497 .get_wol = rtl8169_get_wol,
1498 .set_wol = rtl8169_set_wol,
1499 .get_strings = rtl8169_get_strings,
1500 .get_sset_count = rtl8169_get_sset_count,
1501 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1504 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1505 void __iomem *ioaddr)
1508 * The driver currently handles the 8168Bf and the 8168Be identically
1509 * but they can be identified more specifically through the test below
1512 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1514 * Same thing for the 8101Eb and the 8101Ec:
1516 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1518 static const struct {
1524 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
1525 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
1526 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
1528 /* 8168DP family. */
1529 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
1530 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
1533 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
1534 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
1535 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
1536 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
1537 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1538 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
1539 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
1540 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
1541 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
1544 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1545 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1546 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1547 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1550 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1551 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1552 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1553 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1554 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1555 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
1556 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
1557 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
1558 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
1559 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1560 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
1561 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1562 /* FIXME: where did these entries come from ? -- FR */
1563 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1564 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1567 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1568 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1569 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1570 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1571 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1572 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1575 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
1579 reg = RTL_R32(TxConfig);
1580 while ((reg & p->mask) != p->val)
1582 tp->mac_version = p->mac_version;
1585 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1587 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1595 static void rtl_writephy_batch(struct rtl8169_private *tp,
1596 const struct phy_reg *regs, int len)
1599 rtl_writephy(tp, regs->reg, regs->val);
1604 #define PHY_READ 0x00000000
1605 #define PHY_DATA_OR 0x10000000
1606 #define PHY_DATA_AND 0x20000000
1607 #define PHY_BJMPN 0x30000000
1608 #define PHY_READ_EFUSE 0x40000000
1609 #define PHY_READ_MAC_BYTE 0x50000000
1610 #define PHY_WRITE_MAC_BYTE 0x60000000
1611 #define PHY_CLEAR_READCOUNT 0x70000000
1612 #define PHY_WRITE 0x80000000
1613 #define PHY_READCOUNT_EQ_SKIP 0x90000000
1614 #define PHY_COMP_EQ_SKIPN 0xa0000000
1615 #define PHY_COMP_NEQ_SKIPN 0xb0000000
1616 #define PHY_WRITE_PREVIOUS 0xc0000000
1617 #define PHY_SKIPN 0xd0000000
1618 #define PHY_DELAY_MS 0xe0000000
1619 #define PHY_WRITE_ERI_WORD 0xf0000000
1622 rtl_phy_write_fw(struct rtl8169_private *tp, const struct firmware *fw)
1624 __le32 *phytable = (__le32 *)fw->data;
1625 struct net_device *dev = tp->dev;
1626 size_t index, fw_size = fw->size / sizeof(*phytable);
1629 if (fw->size % sizeof(*phytable)) {
1630 netif_err(tp, probe, dev, "odd sized firmware %zd\n", fw->size);
1634 for (index = 0; index < fw_size; index++) {
1635 u32 action = le32_to_cpu(phytable[index]);
1636 u32 regno = (action & 0x0fff0000) >> 16;
1638 switch(action & 0xf0000000) {
1642 case PHY_READ_EFUSE:
1643 case PHY_CLEAR_READCOUNT:
1645 case PHY_WRITE_PREVIOUS:
1650 if (regno > index) {
1651 netif_err(tp, probe, tp->dev,
1652 "Out of range of firmware\n");
1656 case PHY_READCOUNT_EQ_SKIP:
1657 if (index + 2 >= fw_size) {
1658 netif_err(tp, probe, tp->dev,
1659 "Out of range of firmware\n");
1663 case PHY_COMP_EQ_SKIPN:
1664 case PHY_COMP_NEQ_SKIPN:
1666 if (index + 1 + regno >= fw_size) {
1667 netif_err(tp, probe, tp->dev,
1668 "Out of range of firmware\n");
1673 case PHY_READ_MAC_BYTE:
1674 case PHY_WRITE_MAC_BYTE:
1675 case PHY_WRITE_ERI_WORD:
1677 netif_err(tp, probe, tp->dev,
1678 "Invalid action 0x%08x\n", action);
1686 for (index = 0; index < fw_size; ) {
1687 u32 action = le32_to_cpu(phytable[index]);
1688 u32 data = action & 0x0000ffff;
1689 u32 regno = (action & 0x0fff0000) >> 16;
1694 switch(action & 0xf0000000) {
1696 predata = rtl_readphy(tp, regno);
1711 case PHY_READ_EFUSE:
1712 predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
1715 case PHY_CLEAR_READCOUNT:
1720 rtl_writephy(tp, regno, data);
1723 case PHY_READCOUNT_EQ_SKIP:
1729 case PHY_COMP_EQ_SKIPN:
1730 if (predata == data)
1734 case PHY_COMP_NEQ_SKIPN:
1735 if (predata != data)
1739 case PHY_WRITE_PREVIOUS:
1740 rtl_writephy(tp, regno, predata);
1751 case PHY_READ_MAC_BYTE:
1752 case PHY_WRITE_MAC_BYTE:
1753 case PHY_WRITE_ERI_WORD:
1760 static void rtl_release_firmware(struct rtl8169_private *tp)
1762 release_firmware(tp->fw);
1766 static int rtl_apply_firmware(struct rtl8169_private *tp, const char *fw_name)
1768 const struct firmware **fw = &tp->fw;
1772 rc = request_firmware(fw, fw_name, &tp->pci_dev->dev);
1777 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
1778 rtl_phy_write_fw(tp, *fw);
1783 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1785 static const struct phy_reg phy_reg_init[] = {
1847 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1850 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
1852 static const struct phy_reg phy_reg_init[] = {
1858 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1861 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
1863 struct pci_dev *pdev = tp->pci_dev;
1864 u16 vendor_id, device_id;
1866 pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
1867 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
1869 if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
1872 rtl_writephy(tp, 0x1f, 0x0001);
1873 rtl_writephy(tp, 0x10, 0xf01b);
1874 rtl_writephy(tp, 0x1f, 0x0000);
1877 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
1879 static const struct phy_reg phy_reg_init[] = {
1919 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1921 rtl8169scd_hw_phy_config_quirk(tp);
1924 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
1926 static const struct phy_reg phy_reg_init[] = {
1974 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1977 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
1979 static const struct phy_reg phy_reg_init[] = {
1984 rtl_writephy(tp, 0x1f, 0x0001);
1985 rtl_patchphy(tp, 0x16, 1 << 0);
1987 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1990 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
1992 static const struct phy_reg phy_reg_init[] = {
1998 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2001 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2003 static const struct phy_reg phy_reg_init[] = {
2011 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2014 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2016 static const struct phy_reg phy_reg_init[] = {
2022 rtl_writephy(tp, 0x1f, 0x0000);
2023 rtl_patchphy(tp, 0x14, 1 << 5);
2024 rtl_patchphy(tp, 0x0d, 1 << 5);
2026 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2029 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2031 static const struct phy_reg phy_reg_init[] = {
2051 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2053 rtl_patchphy(tp, 0x14, 1 << 5);
2054 rtl_patchphy(tp, 0x0d, 1 << 5);
2055 rtl_writephy(tp, 0x1f, 0x0000);
2058 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2060 static const struct phy_reg phy_reg_init[] = {
2078 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2080 rtl_patchphy(tp, 0x16, 1 << 0);
2081 rtl_patchphy(tp, 0x14, 1 << 5);
2082 rtl_patchphy(tp, 0x0d, 1 << 5);
2083 rtl_writephy(tp, 0x1f, 0x0000);
2086 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2088 static const struct phy_reg phy_reg_init[] = {
2100 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2102 rtl_patchphy(tp, 0x16, 1 << 0);
2103 rtl_patchphy(tp, 0x14, 1 << 5);
2104 rtl_patchphy(tp, 0x0d, 1 << 5);
2105 rtl_writephy(tp, 0x1f, 0x0000);
2108 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2110 rtl8168c_3_hw_phy_config(tp);
2113 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2115 static const struct phy_reg phy_reg_init_0[] = {
2116 /* Channel Estimation */
2137 * enhance line driver power
2146 * Can not link to 1Gbps with bad cable
2147 * Decrease SNR threshold form 21.07dB to 19.04dB
2155 void __iomem *ioaddr = tp->mmio_addr;
2157 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2161 * Fine Tune Switching regulator parameter
2163 rtl_writephy(tp, 0x1f, 0x0002);
2164 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2165 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2167 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2168 static const struct phy_reg phy_reg_init[] = {
2178 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2180 val = rtl_readphy(tp, 0x0d);
2182 if ((val & 0x00ff) != 0x006c) {
2183 static const u32 set[] = {
2184 0x0065, 0x0066, 0x0067, 0x0068,
2185 0x0069, 0x006a, 0x006b, 0x006c
2189 rtl_writephy(tp, 0x1f, 0x0002);
2192 for (i = 0; i < ARRAY_SIZE(set); i++)
2193 rtl_writephy(tp, 0x0d, val | set[i]);
2196 static const struct phy_reg phy_reg_init[] = {
2204 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2207 /* RSET couple improve */
2208 rtl_writephy(tp, 0x1f, 0x0002);
2209 rtl_patchphy(tp, 0x0d, 0x0300);
2210 rtl_patchphy(tp, 0x0f, 0x0010);
2212 /* Fine tune PLL performance */
2213 rtl_writephy(tp, 0x1f, 0x0002);
2214 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2215 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2217 rtl_writephy(tp, 0x1f, 0x0005);
2218 rtl_writephy(tp, 0x05, 0x001b);
2219 if ((rtl_readphy(tp, 0x06) != 0xbf00) ||
2220 (rtl_apply_firmware(tp, FIRMWARE_8168D_1) < 0)) {
2221 netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n");
2224 rtl_writephy(tp, 0x1f, 0x0000);
2227 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2229 static const struct phy_reg phy_reg_init_0[] = {
2230 /* Channel Estimation */
2251 * enhance line driver power
2260 * Can not link to 1Gbps with bad cable
2261 * Decrease SNR threshold form 21.07dB to 19.04dB
2269 void __iomem *ioaddr = tp->mmio_addr;
2271 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2273 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2274 static const struct phy_reg phy_reg_init[] = {
2285 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2287 val = rtl_readphy(tp, 0x0d);
2288 if ((val & 0x00ff) != 0x006c) {
2289 static const u32 set[] = {
2290 0x0065, 0x0066, 0x0067, 0x0068,
2291 0x0069, 0x006a, 0x006b, 0x006c
2295 rtl_writephy(tp, 0x1f, 0x0002);
2298 for (i = 0; i < ARRAY_SIZE(set); i++)
2299 rtl_writephy(tp, 0x0d, val | set[i]);
2302 static const struct phy_reg phy_reg_init[] = {
2310 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2313 /* Fine tune PLL performance */
2314 rtl_writephy(tp, 0x1f, 0x0002);
2315 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2316 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2318 /* Switching regulator Slew rate */
2319 rtl_writephy(tp, 0x1f, 0x0002);
2320 rtl_patchphy(tp, 0x0f, 0x0017);
2322 rtl_writephy(tp, 0x1f, 0x0005);
2323 rtl_writephy(tp, 0x05, 0x001b);
2324 if ((rtl_readphy(tp, 0x06) != 0xb300) ||
2325 (rtl_apply_firmware(tp, FIRMWARE_8168D_2) < 0)) {
2326 netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n");
2329 rtl_writephy(tp, 0x1f, 0x0000);
2332 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2334 static const struct phy_reg phy_reg_init[] = {
2390 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2393 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2395 static const struct phy_reg phy_reg_init[] = {
2405 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2406 rtl_patchphy(tp, 0x0d, 1 << 5);
2409 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2411 static const struct phy_reg phy_reg_init[] = {
2418 rtl_writephy(tp, 0x1f, 0x0000);
2419 rtl_patchphy(tp, 0x11, 1 << 12);
2420 rtl_patchphy(tp, 0x19, 1 << 13);
2421 rtl_patchphy(tp, 0x10, 1 << 15);
2423 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2426 static void rtl_hw_phy_config(struct net_device *dev)
2428 struct rtl8169_private *tp = netdev_priv(dev);
2430 rtl8169_print_mac_version(tp);
2432 switch (tp->mac_version) {
2433 case RTL_GIGA_MAC_VER_01:
2435 case RTL_GIGA_MAC_VER_02:
2436 case RTL_GIGA_MAC_VER_03:
2437 rtl8169s_hw_phy_config(tp);
2439 case RTL_GIGA_MAC_VER_04:
2440 rtl8169sb_hw_phy_config(tp);
2442 case RTL_GIGA_MAC_VER_05:
2443 rtl8169scd_hw_phy_config(tp);
2445 case RTL_GIGA_MAC_VER_06:
2446 rtl8169sce_hw_phy_config(tp);
2448 case RTL_GIGA_MAC_VER_07:
2449 case RTL_GIGA_MAC_VER_08:
2450 case RTL_GIGA_MAC_VER_09:
2451 rtl8102e_hw_phy_config(tp);
2453 case RTL_GIGA_MAC_VER_11:
2454 rtl8168bb_hw_phy_config(tp);
2456 case RTL_GIGA_MAC_VER_12:
2457 rtl8168bef_hw_phy_config(tp);
2459 case RTL_GIGA_MAC_VER_17:
2460 rtl8168bef_hw_phy_config(tp);
2462 case RTL_GIGA_MAC_VER_18:
2463 rtl8168cp_1_hw_phy_config(tp);
2465 case RTL_GIGA_MAC_VER_19:
2466 rtl8168c_1_hw_phy_config(tp);
2468 case RTL_GIGA_MAC_VER_20:
2469 rtl8168c_2_hw_phy_config(tp);
2471 case RTL_GIGA_MAC_VER_21:
2472 rtl8168c_3_hw_phy_config(tp);
2474 case RTL_GIGA_MAC_VER_22:
2475 rtl8168c_4_hw_phy_config(tp);
2477 case RTL_GIGA_MAC_VER_23:
2478 case RTL_GIGA_MAC_VER_24:
2479 rtl8168cp_2_hw_phy_config(tp);
2481 case RTL_GIGA_MAC_VER_25:
2482 rtl8168d_1_hw_phy_config(tp);
2484 case RTL_GIGA_MAC_VER_26:
2485 rtl8168d_2_hw_phy_config(tp);
2487 case RTL_GIGA_MAC_VER_27:
2488 rtl8168d_3_hw_phy_config(tp);
2490 case RTL_GIGA_MAC_VER_28:
2491 rtl8168d_4_hw_phy_config(tp);
2499 static void rtl8169_phy_timer(unsigned long __opaque)
2501 struct net_device *dev = (struct net_device *)__opaque;
2502 struct rtl8169_private *tp = netdev_priv(dev);
2503 struct timer_list *timer = &tp->timer;
2504 void __iomem *ioaddr = tp->mmio_addr;
2505 unsigned long timeout = RTL8169_PHY_TIMEOUT;
2507 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
2509 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
2512 spin_lock_irq(&tp->lock);
2514 if (tp->phy_reset_pending(tp)) {
2516 * A busy loop could burn quite a few cycles on nowadays CPU.
2517 * Let's delay the execution of the timer for a few ticks.
2523 if (tp->link_ok(ioaddr))
2526 netif_warn(tp, link, dev, "PHY reset until link up\n");
2528 tp->phy_reset_enable(tp);
2531 mod_timer(timer, jiffies + timeout);
2533 spin_unlock_irq(&tp->lock);
2536 static inline void rtl8169_delete_timer(struct net_device *dev)
2538 struct rtl8169_private *tp = netdev_priv(dev);
2539 struct timer_list *timer = &tp->timer;
2541 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
2544 del_timer_sync(timer);
2547 static inline void rtl8169_request_timer(struct net_device *dev)
2549 struct rtl8169_private *tp = netdev_priv(dev);
2550 struct timer_list *timer = &tp->timer;
2552 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
2555 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
2558 #ifdef CONFIG_NET_POLL_CONTROLLER
2560 * Polling 'interrupt' - used by things like netconsole to send skbs
2561 * without having to re-enable interrupts. It's not called while
2562 * the interrupt routine is executing.
2564 static void rtl8169_netpoll(struct net_device *dev)
2566 struct rtl8169_private *tp = netdev_priv(dev);
2567 struct pci_dev *pdev = tp->pci_dev;
2569 disable_irq(pdev->irq);
2570 rtl8169_interrupt(pdev->irq, dev);
2571 enable_irq(pdev->irq);
2575 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
2576 void __iomem *ioaddr)
2579 pci_release_regions(pdev);
2580 pci_clear_mwi(pdev);
2581 pci_disable_device(pdev);
2585 static void rtl8169_phy_reset(struct net_device *dev,
2586 struct rtl8169_private *tp)
2590 tp->phy_reset_enable(tp);
2591 for (i = 0; i < 100; i++) {
2592 if (!tp->phy_reset_pending(tp))
2596 netif_err(tp, link, dev, "PHY reset failed\n");
2599 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
2601 void __iomem *ioaddr = tp->mmio_addr;
2603 rtl_hw_phy_config(dev);
2605 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2606 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2610 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2612 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
2613 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
2615 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
2616 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2618 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
2619 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
2622 rtl8169_phy_reset(dev, tp);
2625 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
2626 * only 8101. Don't panic.
2628 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
2630 if (RTL_R8(PHYstatus) & TBI_Enable)
2631 netif_info(tp, link, dev, "TBI auto-negotiating\n");
2634 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2636 void __iomem *ioaddr = tp->mmio_addr;
2640 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
2641 high = addr[4] | (addr[5] << 8);
2643 spin_lock_irq(&tp->lock);
2645 RTL_W8(Cfg9346, Cfg9346_Unlock);
2647 RTL_W32(MAC4, high);
2653 RTL_W8(Cfg9346, Cfg9346_Lock);
2655 spin_unlock_irq(&tp->lock);
2658 static int rtl_set_mac_address(struct net_device *dev, void *p)
2660 struct rtl8169_private *tp = netdev_priv(dev);
2661 struct sockaddr *addr = p;
2663 if (!is_valid_ether_addr(addr->sa_data))
2664 return -EADDRNOTAVAIL;
2666 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2668 rtl_rar_set(tp, dev->dev_addr);
2673 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2675 struct rtl8169_private *tp = netdev_priv(dev);
2676 struct mii_ioctl_data *data = if_mii(ifr);
2678 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
2681 static int rtl_xmii_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2685 data->phy_id = 32; /* Internal PHY */
2689 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
2693 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
2699 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2704 static const struct rtl_cfg_info {
2705 void (*hw_start)(struct net_device *);
2706 unsigned int region;
2712 } rtl_cfg_infos [] = {
2714 .hw_start = rtl_hw_start_8169,
2717 .intr_event = SYSErr | LinkChg | RxOverflow |
2718 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2719 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2720 .features = RTL_FEATURE_GMII,
2721 .default_ver = RTL_GIGA_MAC_VER_01,
2724 .hw_start = rtl_hw_start_8168,
2727 .intr_event = SYSErr | LinkChg | RxOverflow |
2728 TxErr | TxOK | RxOK | RxErr,
2729 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
2730 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
2731 .default_ver = RTL_GIGA_MAC_VER_11,
2734 .hw_start = rtl_hw_start_8101,
2737 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
2738 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2739 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2740 .features = RTL_FEATURE_MSI,
2741 .default_ver = RTL_GIGA_MAC_VER_13,
2745 /* Cfg9346_Unlock assumed. */
2746 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
2747 const struct rtl_cfg_info *cfg)
2752 cfg2 = RTL_R8(Config2) & ~MSIEnable;
2753 if (cfg->features & RTL_FEATURE_MSI) {
2754 if (pci_enable_msi(pdev)) {
2755 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
2758 msi = RTL_FEATURE_MSI;
2761 RTL_W8(Config2, cfg2);
2765 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
2767 if (tp->features & RTL_FEATURE_MSI) {
2768 pci_disable_msi(pdev);
2769 tp->features &= ~RTL_FEATURE_MSI;
2773 static const struct net_device_ops rtl8169_netdev_ops = {
2774 .ndo_open = rtl8169_open,
2775 .ndo_stop = rtl8169_close,
2776 .ndo_get_stats = rtl8169_get_stats,
2777 .ndo_start_xmit = rtl8169_start_xmit,
2778 .ndo_tx_timeout = rtl8169_tx_timeout,
2779 .ndo_validate_addr = eth_validate_addr,
2780 .ndo_change_mtu = rtl8169_change_mtu,
2781 .ndo_set_mac_address = rtl_set_mac_address,
2782 .ndo_do_ioctl = rtl8169_ioctl,
2783 .ndo_set_multicast_list = rtl_set_rx_mode,
2784 #ifdef CONFIG_R8169_VLAN
2785 .ndo_vlan_rx_register = rtl8169_vlan_rx_register,
2787 #ifdef CONFIG_NET_POLL_CONTROLLER
2788 .ndo_poll_controller = rtl8169_netpoll,
2793 static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
2795 struct mdio_ops *ops = &tp->mdio_ops;
2797 switch (tp->mac_version) {
2798 case RTL_GIGA_MAC_VER_27:
2799 ops->write = r8168dp_1_mdio_write;
2800 ops->read = r8168dp_1_mdio_read;
2802 case RTL_GIGA_MAC_VER_28:
2803 ops->write = r8168dp_2_mdio_write;
2804 ops->read = r8168dp_2_mdio_read;
2807 ops->write = r8169_mdio_write;
2808 ops->read = r8169_mdio_read;
2813 static void r810x_phy_power_down(struct rtl8169_private *tp)
2815 rtl_writephy(tp, 0x1f, 0x0000);
2816 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
2819 static void r810x_phy_power_up(struct rtl8169_private *tp)
2821 rtl_writephy(tp, 0x1f, 0x0000);
2822 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
2825 static void r810x_pll_power_down(struct rtl8169_private *tp)
2827 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
2828 rtl_writephy(tp, 0x1f, 0x0000);
2829 rtl_writephy(tp, MII_BMCR, 0x0000);
2833 r810x_phy_power_down(tp);
2836 static void r810x_pll_power_up(struct rtl8169_private *tp)
2838 r810x_phy_power_up(tp);
2841 static void r8168_phy_power_up(struct rtl8169_private *tp)
2843 rtl_writephy(tp, 0x1f, 0x0000);
2844 rtl_writephy(tp, 0x0e, 0x0000);
2845 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
2848 static void r8168_phy_power_down(struct rtl8169_private *tp)
2850 rtl_writephy(tp, 0x1f, 0x0000);
2851 rtl_writephy(tp, 0x0e, 0x0200);
2852 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
2855 static void r8168_pll_power_down(struct rtl8169_private *tp)
2857 void __iomem *ioaddr = tp->mmio_addr;
2859 if (tp->mac_version == RTL_GIGA_MAC_VER_27)
2862 if (((tp->mac_version == RTL_GIGA_MAC_VER_23) ||
2863 (tp->mac_version == RTL_GIGA_MAC_VER_24)) &&
2864 (RTL_R16(CPlusCmd) & ASF)) {
2868 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
2869 rtl_writephy(tp, 0x1f, 0x0000);
2870 rtl_writephy(tp, MII_BMCR, 0x0000);
2872 RTL_W32(RxConfig, RTL_R32(RxConfig) |
2873 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
2877 r8168_phy_power_down(tp);
2879 switch (tp->mac_version) {
2880 case RTL_GIGA_MAC_VER_25:
2881 case RTL_GIGA_MAC_VER_26:
2882 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
2887 static void r8168_pll_power_up(struct rtl8169_private *tp)
2889 void __iomem *ioaddr = tp->mmio_addr;
2891 if (tp->mac_version == RTL_GIGA_MAC_VER_27)
2894 switch (tp->mac_version) {
2895 case RTL_GIGA_MAC_VER_25:
2896 case RTL_GIGA_MAC_VER_26:
2897 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
2901 r8168_phy_power_up(tp);
2904 static void rtl_pll_power_op(struct rtl8169_private *tp,
2905 void (*op)(struct rtl8169_private *))
2911 static void rtl_pll_power_down(struct rtl8169_private *tp)
2913 rtl_pll_power_op(tp, tp->pll_power_ops.down);
2916 static void rtl_pll_power_up(struct rtl8169_private *tp)
2918 rtl_pll_power_op(tp, tp->pll_power_ops.up);
2921 static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
2923 struct pll_power_ops *ops = &tp->pll_power_ops;
2925 switch (tp->mac_version) {
2926 case RTL_GIGA_MAC_VER_07:
2927 case RTL_GIGA_MAC_VER_08:
2928 case RTL_GIGA_MAC_VER_09:
2929 case RTL_GIGA_MAC_VER_10:
2930 case RTL_GIGA_MAC_VER_16:
2931 ops->down = r810x_pll_power_down;
2932 ops->up = r810x_pll_power_up;
2935 case RTL_GIGA_MAC_VER_11:
2936 case RTL_GIGA_MAC_VER_12:
2937 case RTL_GIGA_MAC_VER_17:
2938 case RTL_GIGA_MAC_VER_18:
2939 case RTL_GIGA_MAC_VER_19:
2940 case RTL_GIGA_MAC_VER_20:
2941 case RTL_GIGA_MAC_VER_21:
2942 case RTL_GIGA_MAC_VER_22:
2943 case RTL_GIGA_MAC_VER_23:
2944 case RTL_GIGA_MAC_VER_24:
2945 case RTL_GIGA_MAC_VER_25:
2946 case RTL_GIGA_MAC_VER_26:
2947 case RTL_GIGA_MAC_VER_27:
2948 case RTL_GIGA_MAC_VER_28:
2949 ops->down = r8168_pll_power_down;
2950 ops->up = r8168_pll_power_up;
2960 static int __devinit
2961 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2963 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
2964 const unsigned int region = cfg->region;
2965 struct rtl8169_private *tp;
2966 struct mii_if_info *mii;
2967 struct net_device *dev;
2968 void __iomem *ioaddr;
2972 if (netif_msg_drv(&debug)) {
2973 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
2974 MODULENAME, RTL8169_VERSION);
2977 dev = alloc_etherdev(sizeof (*tp));
2979 if (netif_msg_drv(&debug))
2980 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
2985 SET_NETDEV_DEV(dev, &pdev->dev);
2986 dev->netdev_ops = &rtl8169_netdev_ops;
2987 tp = netdev_priv(dev);
2990 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
2994 mii->mdio_read = rtl_mdio_read;
2995 mii->mdio_write = rtl_mdio_write;
2996 mii->phy_id_mask = 0x1f;
2997 mii->reg_num_mask = 0x1f;
2998 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3000 /* enable device (incl. PCI PM wakeup and hotplug setup) */
3001 rc = pci_enable_device(pdev);
3003 netif_err(tp, probe, dev, "enable failure\n");
3004 goto err_out_free_dev_1;
3007 if (pci_set_mwi(pdev) < 0)
3008 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
3010 /* make sure PCI base addr 1 is MMIO */
3011 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
3012 netif_err(tp, probe, dev,
3013 "region #%d not an MMIO resource, aborting\n",
3019 /* check for weird/broken PCI region reporting */
3020 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
3021 netif_err(tp, probe, dev,
3022 "Invalid PCI region size(s), aborting\n");
3027 rc = pci_request_regions(pdev, MODULENAME);
3029 netif_err(tp, probe, dev, "could not request regions\n");
3033 tp->cp_cmd = PCIMulRW | RxChkSum;
3035 if ((sizeof(dma_addr_t) > 4) &&
3036 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
3037 tp->cp_cmd |= PCIDAC;
3038 dev->features |= NETIF_F_HIGHDMA;
3040 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3042 netif_err(tp, probe, dev, "DMA configuration failed\n");
3043 goto err_out_free_res_3;
3047 /* ioremap MMIO region */
3048 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
3050 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
3052 goto err_out_free_res_3;
3055 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3057 netif_info(tp, probe, dev, "no PCI Express capability\n");
3059 RTL_W16(IntrMask, 0x0000);
3061 /* Soft reset the chip. */
3062 RTL_W8(ChipCmd, CmdReset);
3064 /* Check that the chip has finished the reset. */
3065 for (i = 0; i < 100; i++) {
3066 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3068 msleep_interruptible(1);
3071 RTL_W16(IntrStatus, 0xffff);
3073 pci_set_master(pdev);
3075 /* Identify chip attached to board */
3076 rtl8169_get_mac_version(tp, ioaddr);
3078 rtl_init_mdio_ops(tp);
3079 rtl_init_pll_power_ops(tp);
3081 /* Use appropriate default if unknown */
3082 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
3083 netif_notice(tp, probe, dev,
3084 "unknown MAC, using family default\n");
3085 tp->mac_version = cfg->default_ver;
3088 rtl8169_print_mac_version(tp);
3090 for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
3091 if (tp->mac_version == rtl_chip_info[i].mac_version)
3094 if (i == ARRAY_SIZE(rtl_chip_info)) {
3096 "driver bug, MAC version not found in rtl_chip_info\n");
3101 RTL_W8(Cfg9346, Cfg9346_Unlock);
3102 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3103 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
3104 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3105 tp->features |= RTL_FEATURE_WOL;
3106 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3107 tp->features |= RTL_FEATURE_WOL;
3108 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
3109 RTL_W8(Cfg9346, Cfg9346_Lock);
3111 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3112 (RTL_R8(PHYstatus) & TBI_Enable)) {
3113 tp->set_speed = rtl8169_set_speed_tbi;
3114 tp->get_settings = rtl8169_gset_tbi;
3115 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3116 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3117 tp->link_ok = rtl8169_tbi_link_ok;
3118 tp->do_ioctl = rtl_tbi_ioctl;
3120 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
3122 tp->set_speed = rtl8169_set_speed_xmii;
3123 tp->get_settings = rtl8169_gset_xmii;
3124 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3125 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3126 tp->link_ok = rtl8169_xmii_link_ok;
3127 tp->do_ioctl = rtl_xmii_ioctl;
3130 spin_lock_init(&tp->lock);
3132 tp->mmio_addr = ioaddr;
3134 /* Get MAC address */
3135 for (i = 0; i < MAC_ADDR_LEN; i++)
3136 dev->dev_addr[i] = RTL_R8(MAC0 + i);
3137 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3139 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
3140 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3141 dev->irq = pdev->irq;
3142 dev->base_addr = (unsigned long) ioaddr;
3144 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
3146 #ifdef CONFIG_R8169_VLAN
3147 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3149 dev->features |= NETIF_F_GRO;
3151 tp->intr_mask = 0xffff;
3152 tp->hw_start = cfg->hw_start;
3153 tp->intr_event = cfg->intr_event;
3154 tp->napi_event = cfg->napi_event;
3156 init_timer(&tp->timer);
3157 tp->timer.data = (unsigned long) dev;
3158 tp->timer.function = rtl8169_phy_timer;
3160 rc = register_netdev(dev);
3164 pci_set_drvdata(pdev, dev);
3166 netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
3167 rtl_chip_info[tp->chipset].name,
3168 dev->base_addr, dev->dev_addr,
3169 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
3171 if ((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
3172 (tp->mac_version == RTL_GIGA_MAC_VER_28)) {
3173 rtl8168_driver_start(tp);
3176 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
3178 if (pci_dev_run_wake(pdev))
3179 pm_runtime_put_noidle(&pdev->dev);
3181 netif_carrier_off(dev);
3187 rtl_disable_msi(pdev, tp);
3190 pci_release_regions(pdev);
3192 pci_clear_mwi(pdev);
3193 pci_disable_device(pdev);
3199 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
3201 struct net_device *dev = pci_get_drvdata(pdev);
3202 struct rtl8169_private *tp = netdev_priv(dev);
3204 if ((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
3205 (tp->mac_version == RTL_GIGA_MAC_VER_28)) {
3206 rtl8168_driver_stop(tp);
3209 cancel_delayed_work_sync(&tp->task);
3211 rtl_release_firmware(tp);
3213 unregister_netdev(dev);
3215 if (pci_dev_run_wake(pdev))
3216 pm_runtime_get_noresume(&pdev->dev);
3218 /* restore original MAC address */
3219 rtl_rar_set(tp, dev->perm_addr);
3221 rtl_disable_msi(pdev, tp);
3222 rtl8169_release_board(pdev, dev, tp->mmio_addr);
3223 pci_set_drvdata(pdev, NULL);
3226 static int rtl8169_open(struct net_device *dev)
3228 struct rtl8169_private *tp = netdev_priv(dev);
3229 void __iomem *ioaddr = tp->mmio_addr;
3230 struct pci_dev *pdev = tp->pci_dev;
3231 int retval = -ENOMEM;
3233 pm_runtime_get_sync(&pdev->dev);
3236 * Rx and Tx desscriptors needs 256 bytes alignment.
3237 * dma_alloc_coherent provides more.
3239 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
3240 &tp->TxPhyAddr, GFP_KERNEL);
3241 if (!tp->TxDescArray)
3242 goto err_pm_runtime_put;
3244 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
3245 &tp->RxPhyAddr, GFP_KERNEL);
3246 if (!tp->RxDescArray)
3249 retval = rtl8169_init_ring(dev);
3253 INIT_DELAYED_WORK(&tp->task, NULL);
3257 retval = request_irq(dev->irq, rtl8169_interrupt,
3258 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
3261 goto err_release_ring_2;
3263 napi_enable(&tp->napi);
3265 rtl8169_init_phy(dev, tp);
3268 * Pretend we are using VLANs; This bypasses a nasty bug where
3269 * Interrupts stop flowing on high load on 8110SCd controllers.
3271 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3272 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | RxVlan);
3274 rtl_pll_power_up(tp);
3278 rtl8169_request_timer(dev);
3280 tp->saved_wolopts = 0;
3281 pm_runtime_put_noidle(&pdev->dev);
3283 rtl8169_check_link_status(dev, tp, ioaddr);
3288 rtl8169_rx_clear(tp);
3290 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
3292 tp->RxDescArray = NULL;
3294 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
3296 tp->TxDescArray = NULL;
3298 pm_runtime_put_noidle(&pdev->dev);
3302 static void rtl8169_hw_reset(struct rtl8169_private *tp)
3304 void __iomem *ioaddr = tp->mmio_addr;
3306 /* Disable interrupts */
3307 rtl8169_irq_mask_and_ack(ioaddr);
3309 if (tp->mac_version == RTL_GIGA_MAC_VER_28) {
3310 while (RTL_R8(TxPoll) & NPQ)
3315 /* Reset the chipset */
3316 RTL_W8(ChipCmd, CmdReset);
3322 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
3324 void __iomem *ioaddr = tp->mmio_addr;
3325 u32 cfg = rtl8169_rx_config;
3327 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3328 RTL_W32(RxConfig, cfg);
3330 /* Set DMA burst size and Interframe Gap Time */
3331 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3332 (InterFrameGap << TxInterFrameGapShift));
3335 static void rtl_hw_start(struct net_device *dev)
3337 struct rtl8169_private *tp = netdev_priv(dev);
3338 void __iomem *ioaddr = tp->mmio_addr;
3341 /* Soft reset the chip. */
3342 RTL_W8(ChipCmd, CmdReset);
3344 /* Check that the chip has finished the reset. */
3345 for (i = 0; i < 100; i++) {
3346 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3348 msleep_interruptible(1);
3353 netif_start_queue(dev);
3357 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3358 void __iomem *ioaddr)
3361 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3362 * register to be written before TxDescAddrLow to work.
3363 * Switching from MMIO to I/O access fixes the issue as well.
3365 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
3366 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
3367 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
3368 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
3371 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
3375 cmd = RTL_R16(CPlusCmd);
3376 RTL_W16(CPlusCmd, cmd);
3380 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
3382 /* Low hurts. Let's disable the filtering. */
3383 RTL_W16(RxMaxSize, rx_buf_sz + 1);
3386 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
3388 static const struct {
3393 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
3394 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
3395 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
3396 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3401 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
3402 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
3403 if ((p->mac_version == mac_version) && (p->clk == clk)) {
3404 RTL_W32(0x7c, p->val);
3410 static void rtl_hw_start_8169(struct net_device *dev)
3412 struct rtl8169_private *tp = netdev_priv(dev);
3413 void __iomem *ioaddr = tp->mmio_addr;
3414 struct pci_dev *pdev = tp->pci_dev;
3416 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
3417 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
3418 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
3421 RTL_W8(Cfg9346, Cfg9346_Unlock);
3422 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3423 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3424 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3425 (tp->mac_version == RTL_GIGA_MAC_VER_04))
3426 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3428 RTL_W8(EarlyTxThres, NoEarlyTx);
3430 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
3432 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3433 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3434 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3435 (tp->mac_version == RTL_GIGA_MAC_VER_04))
3436 rtl_set_rx_tx_config_registers(tp);
3438 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3440 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3441 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
3442 dprintk("Set MAC Reg C+CR Offset 0xE0. "
3443 "Bit-3 and bit-14 MUST be 1\n");
3444 tp->cp_cmd |= (1 << 14);
3447 RTL_W16(CPlusCmd, tp->cp_cmd);
3449 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
3452 * Undocumented corner. Supposedly:
3453 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3455 RTL_W16(IntrMitigate, 0x0000);
3457 rtl_set_rx_tx_desc_registers(tp, ioaddr);
3459 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
3460 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
3461 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
3462 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
3463 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3464 rtl_set_rx_tx_config_registers(tp);
3467 RTL_W8(Cfg9346, Cfg9346_Lock);
3469 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3472 RTL_W32(RxMissed, 0);
3474 rtl_set_rx_mode(dev);
3476 /* no early-rx interrupts */
3477 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
3479 /* Enable all known interrupts by setting the interrupt mask. */
3480 RTL_W16(IntrMask, tp->intr_event);
3483 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
3485 struct net_device *dev = pci_get_drvdata(pdev);
3486 struct rtl8169_private *tp = netdev_priv(dev);
3487 int cap = tp->pcie_cap;
3492 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
3493 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
3494 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
3498 static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
3502 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
3503 rtl_csi_write(ioaddr, 0x070c, csi | bits);
3506 static void rtl_csi_access_enable_1(void __iomem *ioaddr)
3508 rtl_csi_access_enable(ioaddr, 0x17000000);
3511 static void rtl_csi_access_enable_2(void __iomem *ioaddr)
3513 rtl_csi_access_enable(ioaddr, 0x27000000);
3517 unsigned int offset;
3522 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
3527 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
3528 rtl_ephy_write(ioaddr, e->offset, w);
3533 static void rtl_disable_clock_request(struct pci_dev *pdev)
3535 struct net_device *dev = pci_get_drvdata(pdev);
3536 struct rtl8169_private *tp = netdev_priv(dev);
3537 int cap = tp->pcie_cap;
3542 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3543 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
3544 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3548 static void rtl_enable_clock_request(struct pci_dev *pdev)
3550 struct net_device *dev = pci_get_drvdata(pdev);
3551 struct rtl8169_private *tp = netdev_priv(dev);
3552 int cap = tp->pcie_cap;
3557 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3558 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
3559 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3563 #define R8168_CPCMD_QUIRK_MASK (\
3574 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
3576 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3578 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3580 rtl_tx_performance_tweak(pdev,
3581 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3584 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
3586 rtl_hw_start_8168bb(ioaddr, pdev);
3588 RTL_W8(MaxTxPacketSize, TxPacketMax);
3590 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
3593 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
3595 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
3597 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3599 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3601 rtl_disable_clock_request(pdev);
3603 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3606 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
3608 static const struct ephy_info e_info_8168cp[] = {
3609 { 0x01, 0, 0x0001 },
3610 { 0x02, 0x0800, 0x1000 },
3611 { 0x03, 0, 0x0042 },
3612 { 0x06, 0x0080, 0x0000 },
3616 rtl_csi_access_enable_2(ioaddr);
3618 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
3620 __rtl_hw_start_8168cp(ioaddr, pdev);
3623 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
3625 rtl_csi_access_enable_2(ioaddr);
3627 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3629 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3631 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3634 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
3636 rtl_csi_access_enable_2(ioaddr);
3638 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3641 RTL_W8(DBG_REG, 0x20);
3643 RTL_W8(MaxTxPacketSize, TxPacketMax);
3645 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3647 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3650 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
3652 static const struct ephy_info e_info_8168c_1[] = {
3653 { 0x02, 0x0800, 0x1000 },
3654 { 0x03, 0, 0x0002 },
3655 { 0x06, 0x0080, 0x0000 }
3658 rtl_csi_access_enable_2(ioaddr);
3660 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
3662 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
3664 __rtl_hw_start_8168cp(ioaddr, pdev);
3667 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
3669 static const struct ephy_info e_info_8168c_2[] = {
3670 { 0x01, 0, 0x0001 },
3671 { 0x03, 0x0400, 0x0220 }
3674 rtl_csi_access_enable_2(ioaddr);
3676 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
3678 __rtl_hw_start_8168cp(ioaddr, pdev);
3681 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
3683 rtl_hw_start_8168c_2(ioaddr, pdev);
3686 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
3688 rtl_csi_access_enable_2(ioaddr);
3690 __rtl_hw_start_8168cp(ioaddr, pdev);
3693 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
3695 rtl_csi_access_enable_2(ioaddr);
3697 rtl_disable_clock_request(pdev);
3699 RTL_W8(MaxTxPacketSize, TxPacketMax);
3701 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3703 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3706 static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
3708 static const struct ephy_info e_info_8168d_4[] = {
3710 { 0x19, 0x20, 0x50 },
3715 rtl_csi_access_enable_1(ioaddr);
3717 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3719 RTL_W8(MaxTxPacketSize, TxPacketMax);
3721 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
3722 const struct ephy_info *e = e_info_8168d_4 + i;
3725 w = rtl_ephy_read(ioaddr, e->offset);
3726 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
3729 rtl_enable_clock_request(pdev);
3732 static void rtl_hw_start_8168(struct net_device *dev)
3734 struct rtl8169_private *tp = netdev_priv(dev);
3735 void __iomem *ioaddr = tp->mmio_addr;
3736 struct pci_dev *pdev = tp->pci_dev;
3738 RTL_W8(Cfg9346, Cfg9346_Unlock);
3740 RTL_W8(MaxTxPacketSize, TxPacketMax);
3742 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
3744 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
3746 RTL_W16(CPlusCmd, tp->cp_cmd);
3748 RTL_W16(IntrMitigate, 0x5151);
3750 /* Work around for RxFIFO overflow. */
3751 if (tp->mac_version == RTL_GIGA_MAC_VER_11 ||
3752 tp->mac_version == RTL_GIGA_MAC_VER_22) {
3753 tp->intr_event |= RxFIFOOver | PCSTimeout;
3754 tp->intr_event &= ~RxOverflow;
3757 rtl_set_rx_tx_desc_registers(tp, ioaddr);
3759 rtl_set_rx_mode(dev);
3761 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3762 (InterFrameGap << TxInterFrameGapShift));
3766 switch (tp->mac_version) {
3767 case RTL_GIGA_MAC_VER_11:
3768 rtl_hw_start_8168bb(ioaddr, pdev);
3771 case RTL_GIGA_MAC_VER_12:
3772 case RTL_GIGA_MAC_VER_17:
3773 rtl_hw_start_8168bef(ioaddr, pdev);
3776 case RTL_GIGA_MAC_VER_18:
3777 rtl_hw_start_8168cp_1(ioaddr, pdev);
3780 case RTL_GIGA_MAC_VER_19:
3781 rtl_hw_start_8168c_1(ioaddr, pdev);
3784 case RTL_GIGA_MAC_VER_20:
3785 rtl_hw_start_8168c_2(ioaddr, pdev);
3788 case RTL_GIGA_MAC_VER_21:
3789 rtl_hw_start_8168c_3(ioaddr, pdev);
3792 case RTL_GIGA_MAC_VER_22:
3793 rtl_hw_start_8168c_4(ioaddr, pdev);
3796 case RTL_GIGA_MAC_VER_23:
3797 rtl_hw_start_8168cp_2(ioaddr, pdev);
3800 case RTL_GIGA_MAC_VER_24:
3801 rtl_hw_start_8168cp_3(ioaddr, pdev);
3804 case RTL_GIGA_MAC_VER_25:
3805 case RTL_GIGA_MAC_VER_26:
3806 case RTL_GIGA_MAC_VER_27:
3807 rtl_hw_start_8168d(ioaddr, pdev);
3810 case RTL_GIGA_MAC_VER_28:
3811 rtl_hw_start_8168d_4(ioaddr, pdev);
3815 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
3816 dev->name, tp->mac_version);
3820 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3822 RTL_W8(Cfg9346, Cfg9346_Lock);
3824 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
3826 RTL_W16(IntrMask, tp->intr_event);
3829 #define R810X_CPCMD_QUIRK_MASK (\
3841 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
3843 static const struct ephy_info e_info_8102e_1[] = {
3844 { 0x01, 0, 0x6e65 },
3845 { 0x02, 0, 0x091f },
3846 { 0x03, 0, 0xc2f9 },
3847 { 0x06, 0, 0xafb5 },
3848 { 0x07, 0, 0x0e00 },
3849 { 0x19, 0, 0xec80 },
3850 { 0x01, 0, 0x2e65 },
3855 rtl_csi_access_enable_2(ioaddr);
3857 RTL_W8(DBG_REG, FIX_NAK_1);
3859 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3862 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
3863 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3865 cfg1 = RTL_R8(Config1);
3866 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
3867 RTL_W8(Config1, cfg1 & ~LEDS0);
3869 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3871 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
3874 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
3876 rtl_csi_access_enable_2(ioaddr);
3878 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3880 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
3881 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3883 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3886 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
3888 rtl_hw_start_8102e_2(ioaddr, pdev);
3890 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
3893 static void rtl_hw_start_8101(struct net_device *dev)
3895 struct rtl8169_private *tp = netdev_priv(dev);
3896 void __iomem *ioaddr = tp->mmio_addr;
3897 struct pci_dev *pdev = tp->pci_dev;
3899 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
3900 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
3901 int cap = tp->pcie_cap;
3904 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
3905 PCI_EXP_DEVCTL_NOSNOOP_EN);
3909 switch (tp->mac_version) {
3910 case RTL_GIGA_MAC_VER_07:
3911 rtl_hw_start_8102e_1(ioaddr, pdev);
3914 case RTL_GIGA_MAC_VER_08:
3915 rtl_hw_start_8102e_3(ioaddr, pdev);
3918 case RTL_GIGA_MAC_VER_09:
3919 rtl_hw_start_8102e_2(ioaddr, pdev);
3923 RTL_W8(Cfg9346, Cfg9346_Unlock);
3925 RTL_W8(MaxTxPacketSize, TxPacketMax);
3927 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
3929 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3931 RTL_W16(CPlusCmd, tp->cp_cmd);
3933 RTL_W16(IntrMitigate, 0x0000);
3935 rtl_set_rx_tx_desc_registers(tp, ioaddr);
3937 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3938 rtl_set_rx_tx_config_registers(tp);
3940 RTL_W8(Cfg9346, Cfg9346_Lock);
3944 rtl_set_rx_mode(dev);
3946 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3948 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
3950 RTL_W16(IntrMask, tp->intr_event);
3953 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
3955 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
3962 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
3964 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
3965 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
3968 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
3969 void **data_buff, struct RxDesc *desc)
3971 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
3976 rtl8169_make_unusable_by_asic(desc);
3979 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
3981 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
3983 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
3986 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
3989 desc->addr = cpu_to_le64(mapping);
3991 rtl8169_mark_to_asic(desc, rx_buf_sz);
3994 static inline void *rtl8169_align(void *data)
3996 return (void *)ALIGN((long)data, 16);
3999 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
4000 struct RxDesc *desc)
4004 struct device *d = &tp->pci_dev->dev;
4005 struct net_device *dev = tp->dev;
4006 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
4008 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
4012 if (rtl8169_align(data) != data) {
4014 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
4019 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
4021 if (unlikely(dma_mapping_error(d, mapping))) {
4022 if (net_ratelimit())
4023 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
4027 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
4035 static void rtl8169_rx_clear(struct rtl8169_private *tp)
4039 for (i = 0; i < NUM_RX_DESC; i++) {
4040 if (tp->Rx_databuff[i]) {
4041 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
4042 tp->RxDescArray + i);
4047 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
4049 desc->opts1 |= cpu_to_le32(RingEnd);
4052 static int rtl8169_rx_fill(struct rtl8169_private *tp)
4056 for (i = 0; i < NUM_RX_DESC; i++) {
4059 if (tp->Rx_databuff[i])
4062 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
4064 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
4067 tp->Rx_databuff[i] = data;
4070 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4074 rtl8169_rx_clear(tp);
4078 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4080 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
4083 static int rtl8169_init_ring(struct net_device *dev)
4085 struct rtl8169_private *tp = netdev_priv(dev);
4087 rtl8169_init_ring_indexes(tp);
4089 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
4090 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
4092 return rtl8169_rx_fill(tp);
4095 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
4096 struct TxDesc *desc)
4098 unsigned int len = tx_skb->len;
4100 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
4108 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4113 for (i = 0; i < n; i++) {
4114 unsigned int entry = (start + i) % NUM_TX_DESC;
4115 struct ring_info *tx_skb = tp->tx_skb + entry;
4116 unsigned int len = tx_skb->len;
4119 struct sk_buff *skb = tx_skb->skb;
4121 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4122 tp->TxDescArray + entry);
4124 tp->dev->stats.tx_dropped++;
4132 static void rtl8169_tx_clear(struct rtl8169_private *tp)
4134 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
4135 tp->cur_tx = tp->dirty_tx = 0;
4138 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
4140 struct rtl8169_private *tp = netdev_priv(dev);
4142 PREPARE_DELAYED_WORK(&tp->task, task);
4143 schedule_delayed_work(&tp->task, 4);
4146 static void rtl8169_wait_for_quiescence(struct net_device *dev)
4148 struct rtl8169_private *tp = netdev_priv(dev);
4149 void __iomem *ioaddr = tp->mmio_addr;
4151 synchronize_irq(dev->irq);
4153 /* Wait for any pending NAPI task to complete */
4154 napi_disable(&tp->napi);
4156 rtl8169_irq_mask_and_ack(ioaddr);
4158 tp->intr_mask = 0xffff;
4159 RTL_W16(IntrMask, tp->intr_event);
4160 napi_enable(&tp->napi);
4163 static void rtl8169_reinit_task(struct work_struct *work)
4165 struct rtl8169_private *tp =
4166 container_of(work, struct rtl8169_private, task.work);
4167 struct net_device *dev = tp->dev;
4172 if (!netif_running(dev))
4175 rtl8169_wait_for_quiescence(dev);
4178 ret = rtl8169_open(dev);
4179 if (unlikely(ret < 0)) {
4180 if (net_ratelimit())
4181 netif_err(tp, drv, dev,
4182 "reinit failure (status = %d). Rescheduling\n",
4184 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4191 static void rtl8169_reset_task(struct work_struct *work)
4193 struct rtl8169_private *tp =
4194 container_of(work, struct rtl8169_private, task.work);
4195 struct net_device *dev = tp->dev;
4199 if (!netif_running(dev))
4202 rtl8169_wait_for_quiescence(dev);
4204 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
4205 rtl8169_tx_clear(tp);
4207 if (tp->dirty_rx == tp->cur_rx) {
4208 rtl8169_init_ring_indexes(tp);
4210 netif_wake_queue(dev);
4211 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
4213 if (net_ratelimit())
4214 netif_emerg(tp, intr, dev, "Rx buffers shortage\n");
4215 rtl8169_schedule_work(dev, rtl8169_reset_task);
4222 static void rtl8169_tx_timeout(struct net_device *dev)
4224 struct rtl8169_private *tp = netdev_priv(dev);
4226 rtl8169_hw_reset(tp);
4228 /* Let's wait a bit while any (async) irq lands on */
4229 rtl8169_schedule_work(dev, rtl8169_reset_task);
4232 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4235 struct skb_shared_info *info = skb_shinfo(skb);
4236 unsigned int cur_frag, entry;
4237 struct TxDesc * uninitialized_var(txd);
4238 struct device *d = &tp->pci_dev->dev;
4241 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4242 skb_frag_t *frag = info->frags + cur_frag;
4247 entry = (entry + 1) % NUM_TX_DESC;
4249 txd = tp->TxDescArray + entry;
4251 addr = ((void *) page_address(frag->page)) + frag->page_offset;
4252 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
4253 if (unlikely(dma_mapping_error(d, mapping))) {
4254 if (net_ratelimit())
4255 netif_err(tp, drv, tp->dev,
4256 "Failed to map TX fragments DMA!\n");
4260 /* anti gcc 2.95.3 bugware (sic) */
4261 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4263 txd->opts1 = cpu_to_le32(status);
4264 txd->addr = cpu_to_le64(mapping);
4266 tp->tx_skb[entry].len = len;
4270 tp->tx_skb[entry].skb = skb;
4271 txd->opts1 |= cpu_to_le32(LastFrag);
4277 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4281 static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
4283 if (dev->features & NETIF_F_TSO) {
4284 u32 mss = skb_shinfo(skb)->gso_size;
4287 return LargeSend | ((mss & MSSMask) << MSSShift);
4289 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4290 const struct iphdr *ip = ip_hdr(skb);
4292 if (ip->protocol == IPPROTO_TCP)
4293 return IPCS | TCPCS;
4294 else if (ip->protocol == IPPROTO_UDP)
4295 return IPCS | UDPCS;
4296 WARN_ON(1); /* we need a WARN() */
4301 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4302 struct net_device *dev)
4304 struct rtl8169_private *tp = netdev_priv(dev);
4305 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
4306 struct TxDesc *txd = tp->TxDescArray + entry;
4307 void __iomem *ioaddr = tp->mmio_addr;
4308 struct device *d = &tp->pci_dev->dev;
4314 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
4315 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
4319 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
4322 len = skb_headlen(skb);
4323 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
4324 if (unlikely(dma_mapping_error(d, mapping))) {
4325 if (net_ratelimit())
4326 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
4330 tp->tx_skb[entry].len = len;
4331 txd->addr = cpu_to_le64(mapping);
4332 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
4334 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
4336 frags = rtl8169_xmit_frags(tp, skb, opts1);
4342 opts1 |= FirstFrag | LastFrag;
4343 tp->tx_skb[entry].skb = skb;
4348 /* anti gcc 2.95.3 bugware (sic) */
4349 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4350 txd->opts1 = cpu_to_le32(status);
4352 tp->cur_tx += frags + 1;
4356 RTL_W8(TxPoll, NPQ); /* set polling bit */
4358 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
4359 netif_stop_queue(dev);
4361 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
4362 netif_wake_queue(dev);
4365 return NETDEV_TX_OK;
4368 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
4371 dev->stats.tx_dropped++;
4372 return NETDEV_TX_OK;
4375 netif_stop_queue(dev);
4376 dev->stats.tx_dropped++;
4377 return NETDEV_TX_BUSY;
4380 static void rtl8169_pcierr_interrupt(struct net_device *dev)
4382 struct rtl8169_private *tp = netdev_priv(dev);
4383 struct pci_dev *pdev = tp->pci_dev;
4384 u16 pci_status, pci_cmd;
4386 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4387 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
4389 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
4390 pci_cmd, pci_status);
4393 * The recovery sequence below admits a very elaborated explanation:
4394 * - it seems to work;
4395 * - I did not see what else could be done;
4396 * - it makes iop3xx happy.
4398 * Feel free to adjust to your needs.
4400 if (pdev->broken_parity_status)
4401 pci_cmd &= ~PCI_COMMAND_PARITY;
4403 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
4405 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
4407 pci_write_config_word(pdev, PCI_STATUS,
4408 pci_status & (PCI_STATUS_DETECTED_PARITY |
4409 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
4410 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
4412 /* The infamous DAC f*ckup only happens at boot time */
4413 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
4414 void __iomem *ioaddr = tp->mmio_addr;
4416 netif_info(tp, intr, dev, "disabling PCI DAC\n");
4417 tp->cp_cmd &= ~PCIDAC;
4418 RTL_W16(CPlusCmd, tp->cp_cmd);
4419 dev->features &= ~NETIF_F_HIGHDMA;
4422 rtl8169_hw_reset(tp);
4424 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4427 static void rtl8169_tx_interrupt(struct net_device *dev,
4428 struct rtl8169_private *tp,
4429 void __iomem *ioaddr)
4431 unsigned int dirty_tx, tx_left;
4433 dirty_tx = tp->dirty_tx;
4435 tx_left = tp->cur_tx - dirty_tx;
4437 while (tx_left > 0) {
4438 unsigned int entry = dirty_tx % NUM_TX_DESC;
4439 struct ring_info *tx_skb = tp->tx_skb + entry;
4443 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4444 if (status & DescOwn)
4447 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4448 tp->TxDescArray + entry);
4449 if (status & LastFrag) {
4450 dev->stats.tx_packets++;
4451 dev->stats.tx_bytes += tx_skb->skb->len;
4452 dev_kfree_skb(tx_skb->skb);
4459 if (tp->dirty_tx != dirty_tx) {
4460 tp->dirty_tx = dirty_tx;
4462 if (netif_queue_stopped(dev) &&
4463 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
4464 netif_wake_queue(dev);
4467 * 8168 hack: TxPoll requests are lost when the Tx packets are
4468 * too close. Let's kick an extra TxPoll request when a burst
4469 * of start_xmit activity is detected (if it is not detected,
4470 * it is slow enough). -- FR
4473 if (tp->cur_tx != dirty_tx)
4474 RTL_W8(TxPoll, NPQ);
4478 static inline int rtl8169_fragmented_frame(u32 status)
4480 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4483 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
4485 u32 status = opts1 & RxProtoMask;
4487 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
4488 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
4489 skb->ip_summed = CHECKSUM_UNNECESSARY;
4491 skb_checksum_none_assert(skb);
4494 static struct sk_buff *rtl8169_try_rx_copy(void *data,
4495 struct rtl8169_private *tp,
4499 struct sk_buff *skb;
4500 struct device *d = &tp->pci_dev->dev;
4502 data = rtl8169_align(data);
4503 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
4505 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
4507 memcpy(skb->data, data, pkt_size);
4508 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
4514 * Warning : rtl8169_rx_interrupt() might be called :
4515 * 1) from NAPI (softirq) context
4516 * (polling = 1 : we should call netif_receive_skb())
4517 * 2) from process context (rtl8169_reset_task())
4518 * (polling = 0 : we must call netif_rx() instead)
4520 static int rtl8169_rx_interrupt(struct net_device *dev,
4521 struct rtl8169_private *tp,
4522 void __iomem *ioaddr, u32 budget)
4524 unsigned int cur_rx, rx_left;
4526 int polling = (budget != ~(u32)0) ? 1 : 0;
4528 cur_rx = tp->cur_rx;
4529 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
4530 rx_left = min(rx_left, budget);
4532 for (; rx_left > 0; rx_left--, cur_rx++) {
4533 unsigned int entry = cur_rx % NUM_RX_DESC;
4534 struct RxDesc *desc = tp->RxDescArray + entry;
4538 status = le32_to_cpu(desc->opts1);
4540 if (status & DescOwn)
4542 if (unlikely(status & RxRES)) {
4543 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
4545 dev->stats.rx_errors++;
4546 if (status & (RxRWT | RxRUNT))
4547 dev->stats.rx_length_errors++;
4549 dev->stats.rx_crc_errors++;
4550 if (status & RxFOVF) {
4551 rtl8169_schedule_work(dev, rtl8169_reset_task);
4552 dev->stats.rx_fifo_errors++;
4554 rtl8169_mark_to_asic(desc, rx_buf_sz);
4556 struct sk_buff *skb;
4557 dma_addr_t addr = le64_to_cpu(desc->addr);
4558 int pkt_size = (status & 0x00001FFF) - 4;
4561 * The driver does not support incoming fragmented
4562 * frames. They are seen as a symptom of over-mtu
4565 if (unlikely(rtl8169_fragmented_frame(status))) {
4566 dev->stats.rx_dropped++;
4567 dev->stats.rx_length_errors++;
4568 rtl8169_mark_to_asic(desc, rx_buf_sz);
4572 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
4573 tp, pkt_size, addr);
4574 rtl8169_mark_to_asic(desc, rx_buf_sz);
4576 dev->stats.rx_dropped++;
4580 rtl8169_rx_csum(skb, status);
4581 skb_put(skb, pkt_size);
4582 skb->protocol = eth_type_trans(skb, dev);
4584 if (rtl8169_rx_vlan_skb(tp, desc, skb, polling) < 0) {
4585 if (likely(polling))
4586 napi_gro_receive(&tp->napi, skb);
4591 dev->stats.rx_bytes += pkt_size;
4592 dev->stats.rx_packets++;
4595 /* Work around for AMD plateform. */
4596 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
4597 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
4603 count = cur_rx - tp->cur_rx;
4604 tp->cur_rx = cur_rx;
4606 tp->dirty_rx += count;
4611 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
4613 struct net_device *dev = dev_instance;
4614 struct rtl8169_private *tp = netdev_priv(dev);
4615 void __iomem *ioaddr = tp->mmio_addr;
4619 /* loop handling interrupts until we have no new ones or
4620 * we hit a invalid/hotplug case.
4622 status = RTL_R16(IntrStatus);
4623 while (status && status != 0xffff) {
4626 /* Handle all of the error cases first. These will reset
4627 * the chip, so just exit the loop.
4629 if (unlikely(!netif_running(dev))) {
4630 rtl8169_asic_down(ioaddr);
4634 if (unlikely(status & RxFIFOOver)) {
4635 switch (tp->mac_version) {
4636 /* Work around for rx fifo overflow */
4637 case RTL_GIGA_MAC_VER_11:
4638 case RTL_GIGA_MAC_VER_22:
4639 case RTL_GIGA_MAC_VER_26:
4640 netif_stop_queue(dev);
4641 rtl8169_tx_timeout(dev);
4643 /* Testers needed. */
4644 case RTL_GIGA_MAC_VER_17:
4645 case RTL_GIGA_MAC_VER_19:
4646 case RTL_GIGA_MAC_VER_20:
4647 case RTL_GIGA_MAC_VER_21:
4648 case RTL_GIGA_MAC_VER_23:
4649 case RTL_GIGA_MAC_VER_24:
4650 case RTL_GIGA_MAC_VER_27:
4651 case RTL_GIGA_MAC_VER_28:
4652 /* Experimental science. Pktgen proof. */
4653 case RTL_GIGA_MAC_VER_12:
4654 case RTL_GIGA_MAC_VER_25:
4655 if (status == RxFIFOOver)
4663 if (unlikely(status & SYSErr)) {
4664 rtl8169_pcierr_interrupt(dev);
4668 if (status & LinkChg)
4669 __rtl8169_check_link_status(dev, tp, ioaddr, true);
4671 /* We need to see the lastest version of tp->intr_mask to
4672 * avoid ignoring an MSI interrupt and having to wait for
4673 * another event which may never come.
4676 if (status & tp->intr_mask & tp->napi_event) {
4677 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
4678 tp->intr_mask = ~tp->napi_event;
4680 if (likely(napi_schedule_prep(&tp->napi)))
4681 __napi_schedule(&tp->napi);
4683 netif_info(tp, intr, dev,
4684 "interrupt %04x in poll\n", status);
4687 /* We only get a new MSI interrupt when all active irq
4688 * sources on the chip have been acknowledged. So, ack
4689 * everything we've seen and check if new sources have become
4690 * active to avoid blocking all interrupts from the chip.
4693 (status & RxFIFOOver) ? (status | RxOverflow) : status);
4694 status = RTL_R16(IntrStatus);
4697 return IRQ_RETVAL(handled);
4700 static int rtl8169_poll(struct napi_struct *napi, int budget)
4702 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4703 struct net_device *dev = tp->dev;
4704 void __iomem *ioaddr = tp->mmio_addr;
4707 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
4708 rtl8169_tx_interrupt(dev, tp, ioaddr);
4710 if (work_done < budget) {
4711 napi_complete(napi);
4713 /* We need for force the visibility of tp->intr_mask
4714 * for other CPUs, as we can loose an MSI interrupt
4715 * and potentially wait for a retransmit timeout if we don't.
4716 * The posted write to IntrMask is safe, as it will
4717 * eventually make it to the chip and we won't loose anything
4720 tp->intr_mask = 0xffff;
4722 RTL_W16(IntrMask, tp->intr_event);
4728 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
4730 struct rtl8169_private *tp = netdev_priv(dev);
4732 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
4735 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
4736 RTL_W32(RxMissed, 0);
4739 static void rtl8169_down(struct net_device *dev)
4741 struct rtl8169_private *tp = netdev_priv(dev);
4742 void __iomem *ioaddr = tp->mmio_addr;
4744 rtl8169_delete_timer(dev);
4746 netif_stop_queue(dev);
4748 napi_disable(&tp->napi);
4750 spin_lock_irq(&tp->lock);
4752 rtl8169_asic_down(ioaddr);
4754 * At this point device interrupts can not be enabled in any function,
4755 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
4756 * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
4758 rtl8169_rx_missed(dev, ioaddr);
4760 spin_unlock_irq(&tp->lock);
4762 synchronize_irq(dev->irq);
4764 /* Give a racing hard_start_xmit a few cycles to complete. */
4765 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
4767 rtl8169_tx_clear(tp);
4769 rtl8169_rx_clear(tp);
4771 rtl_pll_power_down(tp);
4774 static int rtl8169_close(struct net_device *dev)
4776 struct rtl8169_private *tp = netdev_priv(dev);
4777 struct pci_dev *pdev = tp->pci_dev;
4779 pm_runtime_get_sync(&pdev->dev);
4781 /* update counters before going down */
4782 rtl8169_update_counters(dev);
4786 free_irq(dev->irq, dev);
4788 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4790 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4792 tp->TxDescArray = NULL;
4793 tp->RxDescArray = NULL;
4795 pm_runtime_put_sync(&pdev->dev);
4800 static void rtl_set_rx_mode(struct net_device *dev)
4802 struct rtl8169_private *tp = netdev_priv(dev);
4803 void __iomem *ioaddr = tp->mmio_addr;
4804 unsigned long flags;
4805 u32 mc_filter[2]; /* Multicast hash filter */
4809 if (dev->flags & IFF_PROMISC) {
4810 /* Unconditionally log net taps. */
4811 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4813 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4815 mc_filter[1] = mc_filter[0] = 0xffffffff;
4816 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4817 (dev->flags & IFF_ALLMULTI)) {
4818 /* Too many to filter perfectly -- accept all multicasts. */
4819 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4820 mc_filter[1] = mc_filter[0] = 0xffffffff;
4822 struct netdev_hw_addr *ha;
4824 rx_mode = AcceptBroadcast | AcceptMyPhys;
4825 mc_filter[1] = mc_filter[0] = 0;
4826 netdev_for_each_mc_addr(ha, dev) {
4827 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4828 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4829 rx_mode |= AcceptMulticast;
4833 spin_lock_irqsave(&tp->lock, flags);
4835 tmp = rtl8169_rx_config | rx_mode |
4836 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
4838 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4839 u32 data = mc_filter[0];
4841 mc_filter[0] = swab32(mc_filter[1]);
4842 mc_filter[1] = swab32(data);
4845 RTL_W32(MAR0 + 4, mc_filter[1]);
4846 RTL_W32(MAR0 + 0, mc_filter[0]);
4848 RTL_W32(RxConfig, tmp);
4850 spin_unlock_irqrestore(&tp->lock, flags);
4854 * rtl8169_get_stats - Get rtl8169 read/write statistics
4855 * @dev: The Ethernet Device to get statistics for
4857 * Get TX/RX statistics for rtl8169
4859 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
4861 struct rtl8169_private *tp = netdev_priv(dev);
4862 void __iomem *ioaddr = tp->mmio_addr;
4863 unsigned long flags;
4865 if (netif_running(dev)) {
4866 spin_lock_irqsave(&tp->lock, flags);
4867 rtl8169_rx_missed(dev, ioaddr);
4868 spin_unlock_irqrestore(&tp->lock, flags);
4874 static void rtl8169_net_suspend(struct net_device *dev)
4876 struct rtl8169_private *tp = netdev_priv(dev);
4878 if (!netif_running(dev))
4881 rtl_pll_power_down(tp);
4883 netif_device_detach(dev);
4884 netif_stop_queue(dev);
4889 static int rtl8169_suspend(struct device *device)
4891 struct pci_dev *pdev = to_pci_dev(device);
4892 struct net_device *dev = pci_get_drvdata(pdev);
4894 rtl8169_net_suspend(dev);
4899 static void __rtl8169_resume(struct net_device *dev)
4901 struct rtl8169_private *tp = netdev_priv(dev);
4903 netif_device_attach(dev);
4905 rtl_pll_power_up(tp);
4907 rtl8169_schedule_work(dev, rtl8169_reset_task);
4910 static int rtl8169_resume(struct device *device)
4912 struct pci_dev *pdev = to_pci_dev(device);
4913 struct net_device *dev = pci_get_drvdata(pdev);
4914 struct rtl8169_private *tp = netdev_priv(dev);
4916 rtl8169_init_phy(dev, tp);
4918 if (netif_running(dev))
4919 __rtl8169_resume(dev);
4924 static int rtl8169_runtime_suspend(struct device *device)
4926 struct pci_dev *pdev = to_pci_dev(device);
4927 struct net_device *dev = pci_get_drvdata(pdev);
4928 struct rtl8169_private *tp = netdev_priv(dev);
4930 if (!tp->TxDescArray)
4933 spin_lock_irq(&tp->lock);
4934 tp->saved_wolopts = __rtl8169_get_wol(tp);
4935 __rtl8169_set_wol(tp, WAKE_ANY);
4936 spin_unlock_irq(&tp->lock);
4938 rtl8169_net_suspend(dev);
4943 static int rtl8169_runtime_resume(struct device *device)
4945 struct pci_dev *pdev = to_pci_dev(device);
4946 struct net_device *dev = pci_get_drvdata(pdev);
4947 struct rtl8169_private *tp = netdev_priv(dev);
4949 if (!tp->TxDescArray)
4952 spin_lock_irq(&tp->lock);
4953 __rtl8169_set_wol(tp, tp->saved_wolopts);
4954 tp->saved_wolopts = 0;
4955 spin_unlock_irq(&tp->lock);
4957 rtl8169_init_phy(dev, tp);
4959 __rtl8169_resume(dev);
4964 static int rtl8169_runtime_idle(struct device *device)
4966 struct pci_dev *pdev = to_pci_dev(device);
4967 struct net_device *dev = pci_get_drvdata(pdev);
4968 struct rtl8169_private *tp = netdev_priv(dev);
4970 return tp->TxDescArray ? -EBUSY : 0;
4973 static const struct dev_pm_ops rtl8169_pm_ops = {
4974 .suspend = rtl8169_suspend,
4975 .resume = rtl8169_resume,
4976 .freeze = rtl8169_suspend,
4977 .thaw = rtl8169_resume,
4978 .poweroff = rtl8169_suspend,
4979 .restore = rtl8169_resume,
4980 .runtime_suspend = rtl8169_runtime_suspend,
4981 .runtime_resume = rtl8169_runtime_resume,
4982 .runtime_idle = rtl8169_runtime_idle,
4985 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
4987 #else /* !CONFIG_PM */
4989 #define RTL8169_PM_OPS NULL
4991 #endif /* !CONFIG_PM */
4993 static void rtl_shutdown(struct pci_dev *pdev)
4995 struct net_device *dev = pci_get_drvdata(pdev);
4996 struct rtl8169_private *tp = netdev_priv(dev);
4997 void __iomem *ioaddr = tp->mmio_addr;
4999 rtl8169_net_suspend(dev);
5001 /* restore original MAC address */
5002 rtl_rar_set(tp, dev->perm_addr);
5004 spin_lock_irq(&tp->lock);
5006 rtl8169_asic_down(ioaddr);
5008 spin_unlock_irq(&tp->lock);
5010 if (system_state == SYSTEM_POWER_OFF) {
5011 /* WoL fails with some 8168 when the receiver is disabled. */
5012 if (tp->features & RTL_FEATURE_WOL) {
5013 pci_clear_master(pdev);
5015 RTL_W8(ChipCmd, CmdRxEnb);
5020 pci_wake_from_d3(pdev, true);
5021 pci_set_power_state(pdev, PCI_D3hot);
5025 static struct pci_driver rtl8169_pci_driver = {
5027 .id_table = rtl8169_pci_tbl,
5028 .probe = rtl8169_init_one,
5029 .remove = __devexit_p(rtl8169_remove_one),
5030 .shutdown = rtl_shutdown,
5031 .driver.pm = RTL8169_PM_OPS,
5034 static int __init rtl8169_init_module(void)
5036 return pci_register_driver(&rtl8169_pci_driver);
5039 static void __exit rtl8169_cleanup_module(void)
5041 pci_unregister_driver(&rtl8169_pci_driver);
5044 module_init(rtl8169_init_module);
5045 module_exit(rtl8169_cleanup_module);