drivers/net/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/mii.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/crc32.h>
  21 #include <linux/in.h>
  22 #include <linux/ip.h>
  23 #include <linux/tcp.h>
  24 #include <linux/init.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/firmware.h>
  28 #include <linux/pci-aspm.h>
  29 #include <linux/prefetch.h>
  30
  31 #include <asm/system.h>
  32 #include <asm/io.h>
  33 #include <asm/irq.h>
  34
  35 #define RTL8169_VERSION "2.3LK-NAPI"
  36 #define MODULENAME "r8169"
  37 #define PFX MODULENAME ": "
  38
  39 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  40 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  41 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  42 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  43 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  44
  45 #ifdef RTL8169_DEBUG
  46 #define assert(expr) \
  47         if (!(expr)) {                                  \
  48                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  49                 #expr,__FILE__,__func__,__LINE__);              \
  50         }
  51 #define dprintk(fmt, args...) \
  52         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
  53 #else
  54 #define assert(expr) do {} while (0)
  55 #define dprintk(fmt, args...)   do {} while (0)
  56 #endif /* RTL8169_DEBUG */
  57
  58 #define R8169_MSG_DEFAULT \
  59         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  60
  61 #define TX_BUFFS_AVAIL(tp) \
  62         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
  63
  64 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  65    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  66 static const int multicast_filter_limit = 32;
  67
  68 /* MAC address length */
  69 #define MAC_ADDR_LEN    6
  70
  71 #define MAX_READ_REQUEST_SHIFT  12
  72 #define RX_FIFO_THRESH  7       /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
  73 #define RX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  74 #define TX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  75 #define SafeMtu         0x1c20  /* ... actually life sucks beyond ~7k */
  76 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  77
  78 #define R8169_REGS_SIZE         256
  79 #define R8169_NAPI_WEIGHT       64
  80 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  81 #define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
  82 #define RX_BUF_SIZE     1536    /* Rx Buffer size */
  83 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  84 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  85
  86 #define RTL8169_TX_TIMEOUT      (6*HZ)
  87 #define RTL8169_PHY_TIMEOUT     (10*HZ)
  88
  89 #define RTL_EEPROM_SIG          cpu_to_le32(0x8129)
  90 #define RTL_EEPROM_SIG_MASK     cpu_to_le32(0xffff)
  91 #define RTL_EEPROM_SIG_ADDR     0x0000
  92
  93 /* write/read MMIO register */
  94 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
  95 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
  96 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
  97 #define RTL_R8(reg)             readb (ioaddr + (reg))
  98 #define RTL_R16(reg)            readw (ioaddr + (reg))
  99 #define RTL_R32(reg)            readl (ioaddr + (reg))
 100
 101 enum mac_version {
 102         RTL_GIGA_MAC_VER_01 = 0,
 103         RTL_GIGA_MAC_VER_02,
 104         RTL_GIGA_MAC_VER_03,
 105         RTL_GIGA_MAC_VER_04,
 106         RTL_GIGA_MAC_VER_05,
 107         RTL_GIGA_MAC_VER_06,
 108         RTL_GIGA_MAC_VER_07,
 109         RTL_GIGA_MAC_VER_08,
 110         RTL_GIGA_MAC_VER_09,
 111         RTL_GIGA_MAC_VER_10,
 112         RTL_GIGA_MAC_VER_11,
 113         RTL_GIGA_MAC_VER_12,
 114         RTL_GIGA_MAC_VER_13,
 115         RTL_GIGA_MAC_VER_14,
 116         RTL_GIGA_MAC_VER_15,
 117         RTL_GIGA_MAC_VER_16,
 118         RTL_GIGA_MAC_VER_17,
 119         RTL_GIGA_MAC_VER_18,
 120         RTL_GIGA_MAC_VER_19,
 121         RTL_GIGA_MAC_VER_20,
 122         RTL_GIGA_MAC_VER_21,
 123         RTL_GIGA_MAC_VER_22,
 124         RTL_GIGA_MAC_VER_23,
 125         RTL_GIGA_MAC_VER_24,
 126         RTL_GIGA_MAC_VER_25,
 127         RTL_GIGA_MAC_VER_26,
 128         RTL_GIGA_MAC_VER_27,
 129         RTL_GIGA_MAC_VER_28,
 130         RTL_GIGA_MAC_VER_29,
 131         RTL_GIGA_MAC_VER_30,
 132         RTL_GIGA_MAC_VER_31,
 133         RTL_GIGA_MAC_VER_32,
 134         RTL_GIGA_MAC_VER_33,
 135         RTL_GIGA_MAC_NONE   = 0xff,
 136 };
 137
 138 enum rtl_tx_desc_version {
 139         RTL_TD_0        = 0,
 140         RTL_TD_1        = 1,
 141 };
 142
 143 #define _R(NAME,TD,FW) \
 144         { .name = NAME, .txd_version = TD, .fw_name = FW }
 145
 146 static const struct {
 147         const char *name;
 148         enum rtl_tx_desc_version txd_version;
 149         const char *fw_name;
 150 } rtl_chip_infos[] = {
 151         /* PCI devices. */
 152         [RTL_GIGA_MAC_VER_01] =
 153                 _R("RTL8169",           RTL_TD_0, NULL),
 154         [RTL_GIGA_MAC_VER_02] =
 155                 _R("RTL8169s",          RTL_TD_0, NULL),
 156         [RTL_GIGA_MAC_VER_03] =
 157                 _R("RTL8110s",          RTL_TD_0, NULL),
 158         [RTL_GIGA_MAC_VER_04] =
 159                 _R("RTL8169sb/8110sb",  RTL_TD_0, NULL),
 160         [RTL_GIGA_MAC_VER_05] =
 161                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL),
 162         [RTL_GIGA_MAC_VER_06] =
 163                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL),
 164         /* PCI-E devices. */
 165         [RTL_GIGA_MAC_VER_07] =
 166                 _R("RTL8102e",          RTL_TD_1, NULL),
 167         [RTL_GIGA_MAC_VER_08] =
 168                 _R("RTL8102e",          RTL_TD_1, NULL),
 169         [RTL_GIGA_MAC_VER_09] =
 170                 _R("RTL8102e",          RTL_TD_1, NULL),
 171         [RTL_GIGA_MAC_VER_10] =
 172                 _R("RTL8101e",          RTL_TD_0, NULL),
 173         [RTL_GIGA_MAC_VER_11] =
 174                 _R("RTL8168b/8111b",    RTL_TD_0, NULL),
 175         [RTL_GIGA_MAC_VER_12] =
 176                 _R("RTL8168b/8111b",    RTL_TD_0, NULL),
 177         [RTL_GIGA_MAC_VER_13] =
 178                 _R("RTL8101e",          RTL_TD_0, NULL),
 179         [RTL_GIGA_MAC_VER_14] =
 180                 _R("RTL8100e",          RTL_TD_0, NULL),
 181         [RTL_GIGA_MAC_VER_15] =
 182                 _R("RTL8100e",          RTL_TD_0, NULL),
 183         [RTL_GIGA_MAC_VER_16] =
 184                 _R("RTL8101e",          RTL_TD_0, NULL),
 185         [RTL_GIGA_MAC_VER_17] =
 186                 _R("RTL8168b/8111b",    RTL_TD_0, NULL),
 187         [RTL_GIGA_MAC_VER_18] =
 188                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL),
 189         [RTL_GIGA_MAC_VER_19] =
 190                 _R("RTL8168c/8111c",    RTL_TD_1, NULL),
 191         [RTL_GIGA_MAC_VER_20] =
 192                 _R("RTL8168c/8111c",    RTL_TD_1, NULL),
 193         [RTL_GIGA_MAC_VER_21] =
 194                 _R("RTL8168c/8111c",    RTL_TD_1, NULL),
 195         [RTL_GIGA_MAC_VER_22] =
 196                 _R("RTL8168c/8111c",    RTL_TD_1, NULL),
 197         [RTL_GIGA_MAC_VER_23] =
 198                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL),
 199         [RTL_GIGA_MAC_VER_24] =
 200                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL),
 201         [RTL_GIGA_MAC_VER_25] =
 202                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_1),
 203         [RTL_GIGA_MAC_VER_26] =
 204                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_2),
 205         [RTL_GIGA_MAC_VER_27] =
 206                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL),
 207         [RTL_GIGA_MAC_VER_28] =
 208                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL),
 209         [RTL_GIGA_MAC_VER_29] =
 210                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1),
 211         [RTL_GIGA_MAC_VER_30] =
 212                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1),
 213         [RTL_GIGA_MAC_VER_31] =
 214                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL),
 215         [RTL_GIGA_MAC_VER_32] =
 216                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_1),
 217         [RTL_GIGA_MAC_VER_33] =
 218                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_2)
 219 };
 220 #undef _R
 221
 222 enum cfg_version {
 223         RTL_CFG_0 = 0x00,
 224         RTL_CFG_1,
 225         RTL_CFG_2
 226 };
 227
 228 static void rtl_hw_start_8169(struct net_device *);
 229 static void rtl_hw_start_8168(struct net_device *);
 230 static void rtl_hw_start_8101(struct net_device *);
 231
 232 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
 233         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 234         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 235         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 236         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 237         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 238         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 239         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4302), 0, 0, RTL_CFG_0 },
 240         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
 241         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 242         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 243                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 244         { 0x0001,                               0x8168,
 245                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 246         {0,},
 247 };
 248
 249 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 250
 251 static int rx_buf_sz = 16383;
 252 static int use_dac;
 253 static struct {
 254         u32 msg_enable;
 255 } debug = { -1 };
 256
 257 enum rtl_registers {
 258         MAC0            = 0,    /* Ethernet hardware address. */
 259         MAC4            = 4,
 260         MAR0            = 8,    /* Multicast filter. */
 261         CounterAddrLow          = 0x10,
 262         CounterAddrHigh         = 0x14,
 263         TxDescStartAddrLow      = 0x20,
 264         TxDescStartAddrHigh     = 0x24,
 265         TxHDescStartAddrLow     = 0x28,
 266         TxHDescStartAddrHigh    = 0x2c,
 267         FLASH           = 0x30,
 268         ERSR            = 0x36,
 269         ChipCmd         = 0x37,
 270         TxPoll          = 0x38,
 271         IntrMask        = 0x3c,
 272         IntrStatus      = 0x3e,
 273         TxConfig        = 0x40,
 274         RxConfig        = 0x44,
 275
 276 #define RTL_RX_CONFIG_MASK              0xff7e1880u
 277
 278         RxMissed        = 0x4c,
 279         Cfg9346         = 0x50,
 280         Config0         = 0x51,
 281         Config1         = 0x52,
 282         Config2         = 0x53,
 283         Config3         = 0x54,
 284         Config4         = 0x55,
 285         Config5         = 0x56,
 286         MultiIntr       = 0x5c,
 287         PHYAR           = 0x60,
 288         PHYstatus       = 0x6c,
 289         RxMaxSize       = 0xda,
 290         CPlusCmd        = 0xe0,
 291         IntrMitigate    = 0xe2,
 292         RxDescAddrLow   = 0xe4,
 293         RxDescAddrHigh  = 0xe8,
 294         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 295
 296 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 297
 298         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 299
 300 #define TxPacketMax     (8064 >> 7)
 301
 302         FuncEvent       = 0xf0,
 303         FuncEventMask   = 0xf4,
 304         FuncPresetState = 0xf8,
 305         FuncForceEvent  = 0xfc,
 306 };
 307
 308 enum rtl8110_registers {
 309         TBICSR                  = 0x64,
 310         TBI_ANAR                = 0x68,
 311         TBI_LPAR                = 0x6a,
 312 };
 313
 314 enum rtl8168_8101_registers {
 315         CSIDR                   = 0x64,
 316         CSIAR                   = 0x68,
 317 #define CSIAR_FLAG                      0x80000000
 318 #define CSIAR_WRITE_CMD                 0x80000000
 319 #define CSIAR_BYTE_ENABLE               0x0f
 320 #define CSIAR_BYTE_ENABLE_SHIFT         12
 321 #define CSIAR_ADDR_MASK                 0x0fff
 322         PMCH                    = 0x6f,
 323         EPHYAR                  = 0x80,
 324 #define EPHYAR_FLAG                     0x80000000
 325 #define EPHYAR_WRITE_CMD                0x80000000
 326 #define EPHYAR_REG_MASK                 0x1f
 327 #define EPHYAR_REG_SHIFT                16
 328 #define EPHYAR_DATA_MASK                0xffff
 329         DLLPR                   = 0xd0,
 330 #define PM_SWITCH                       (1 << 6)
 331         DBG_REG                 = 0xd1,
 332 #define FIX_NAK_1                       (1 << 4)
 333 #define FIX_NAK_2                       (1 << 3)
 334         TWSI                    = 0xd2,
 335         MCU                     = 0xd3,
 336 #define EN_NDP                          (1 << 3)
 337 #define EN_OOB_RESET                    (1 << 2)
 338         EFUSEAR                 = 0xdc,
 339 #define EFUSEAR_FLAG                    0x80000000
 340 #define EFUSEAR_WRITE_CMD               0x80000000
 341 #define EFUSEAR_READ_CMD                0x00000000
 342 #define EFUSEAR_REG_MASK                0x03ff
 343 #define EFUSEAR_REG_SHIFT               8
 344 #define EFUSEAR_DATA_MASK               0xff
 345 };
 346
 347 enum rtl8168_registers {
 348         ERIDR                   = 0x70,
 349         ERIAR                   = 0x74,
 350 #define ERIAR_FLAG                      0x80000000
 351 #define ERIAR_WRITE_CMD                 0x80000000
 352 #define ERIAR_READ_CMD                  0x00000000
 353 #define ERIAR_ADDR_BYTE_ALIGN           4
 354 #define ERIAR_EXGMAC                    0
 355 #define ERIAR_MSIX                      1
 356 #define ERIAR_ASF                       2
 357 #define ERIAR_TYPE_SHIFT                16
 358 #define ERIAR_BYTEEN                    0x0f
 359 #define ERIAR_BYTEEN_SHIFT              12
 360         EPHY_RXER_NUM           = 0x7c,
 361         OCPDR                   = 0xb0, /* OCP GPHY access */
 362 #define OCPDR_WRITE_CMD                 0x80000000
 363 #define OCPDR_READ_CMD                  0x00000000
 364 #define OCPDR_REG_MASK                  0x7f
 365 #define OCPDR_GPHY_REG_SHIFT            16
 366 #define OCPDR_DATA_MASK                 0xffff
 367         OCPAR                   = 0xb4,
 368 #define OCPAR_FLAG                      0x80000000
 369 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 370 #define OCPAR_GPHY_READ_CMD             0x0000f060
 371         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 372         MISC                    = 0xf0, /* 8168e only. */
 373 #define TXPLA_RST                       (1 << 29)
 374 };
 375
 376 enum rtl_register_content {
 377         /* InterruptStatusBits */
 378         SYSErr          = 0x8000,
 379         PCSTimeout      = 0x4000,
 380         SWInt           = 0x0100,
 381         TxDescUnavail   = 0x0080,
 382         RxFIFOOver      = 0x0040,
 383         LinkChg         = 0x0020,
 384         RxOverflow      = 0x0010,
 385         TxErr           = 0x0008,
 386         TxOK            = 0x0004,
 387         RxErr           = 0x0002,
 388         RxOK            = 0x0001,
 389
 390         /* RxStatusDesc */
 391         RxFOVF  = (1 << 23),
 392         RxRWT   = (1 << 22),
 393         RxRES   = (1 << 21),
 394         RxRUNT  = (1 << 20),
 395         RxCRC   = (1 << 19),
 396
 397         /* ChipCmdBits */
 398         CmdReset        = 0x10,
 399         CmdRxEnb        = 0x08,
 400         CmdTxEnb        = 0x04,
 401         RxBufEmpty      = 0x01,
 402
 403         /* TXPoll register p.5 */
 404         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 405         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 406         FSWInt          = 0x01,         /* Forced software interrupt */
 407
 408         /* Cfg9346Bits */
 409         Cfg9346_Lock    = 0x00,
 410         Cfg9346_Unlock  = 0xc0,
 411
 412         /* rx_mode_bits */
 413         AcceptErr       = 0x20,
 414         AcceptRunt      = 0x10,
 415         AcceptBroadcast = 0x08,
 416         AcceptMulticast = 0x04,
 417         AcceptMyPhys    = 0x02,
 418         AcceptAllPhys   = 0x01,
 419
 420         /* RxConfigBits */
 421         RxCfgFIFOShift  = 13,
 422         RxCfgDMAShift   =  8,
 423
 424         /* TxConfigBits */
 425         TxInterFrameGapShift = 24,
 426         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 427
 428         /* Config1 register p.24 */
 429         LEDS1           = (1 << 7),
 430         LEDS0           = (1 << 6),
 431         MSIEnable       = (1 << 5),     /* Enable Message Signaled Interrupt */
 432         Speed_down      = (1 << 4),
 433         MEMMAP          = (1 << 3),
 434         IOMAP           = (1 << 2),
 435         VPD             = (1 << 1),
 436         PMEnable        = (1 << 0),     /* Power Management Enable */
 437
 438         /* Config2 register p. 25 */
 439         PCI_Clock_66MHz = 0x01,
 440         PCI_Clock_33MHz = 0x00,
 441
 442         /* Config3 register p.25 */
 443         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 444         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 445         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 446
 447         /* Config5 register p.27 */
 448         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 449         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 450         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 451         Spi_en          = (1 << 3),
 452         LanWake         = (1 << 1),     /* LanWake enable/disable */
 453         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 454
 455         /* TBICSR p.28 */
 456         TBIReset        = 0x80000000,
 457         TBILoopback     = 0x40000000,
 458         TBINwEnable     = 0x20000000,
 459         TBINwRestart    = 0x10000000,
 460         TBILinkOk       = 0x02000000,
 461         TBINwComplete   = 0x01000000,
 462
 463         /* CPlusCmd p.31 */
 464         EnableBist      = (1 << 15),    // 8168 8101
 465         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 466         Normal_mode     = (1 << 13),    // unused
 467         Force_half_dup  = (1 << 12),    // 8168 8101
 468         Force_rxflow_en = (1 << 11),    // 8168 8101
 469         Force_txflow_en = (1 << 10),    // 8168 8101
 470         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 471         ASF             = (1 << 8),     // 8168 8101
 472         PktCntrDisable  = (1 << 7),     // 8168 8101
 473         Mac_dbgo_sel    = 0x001c,       // 8168
 474         RxVlan          = (1 << 6),
 475         RxChkSum        = (1 << 5),
 476         PCIDAC          = (1 << 4),
 477         PCIMulRW        = (1 << 3),
 478         INTT_0          = 0x0000,       // 8168
 479         INTT_1          = 0x0001,       // 8168
 480         INTT_2          = 0x0002,       // 8168
 481         INTT_3          = 0x0003,       // 8168
 482
 483         /* rtl8169_PHYstatus */
 484         TBI_Enable      = 0x80,
 485         TxFlowCtrl      = 0x40,
 486         RxFlowCtrl      = 0x20,
 487         _1000bpsF       = 0x10,
 488         _100bps         = 0x08,
 489         _10bps          = 0x04,
 490         LinkStatus      = 0x02,
 491         FullDup         = 0x01,
 492
 493         /* _TBICSRBit */
 494         TBILinkOK       = 0x02000000,
 495
 496         /* DumpCounterCommand */
 497         CounterDump     = 0x8,
 498 };
 499
 500 enum rtl_desc_bit {
 501         /* First doubleword. */
 502         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 503         RingEnd         = (1 << 30), /* End of descriptor ring */
 504         FirstFrag       = (1 << 29), /* First segment of a packet */
 505         LastFrag        = (1 << 28), /* Final segment of a packet */
 506 };
 507
 508 /* Generic case. */
 509 enum rtl_tx_desc_bit {
 510         /* First doubleword. */
 511         TD_LSO          = (1 << 27),            /* Large Send Offload */
 512 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 513
 514         /* Second doubleword. */
 515         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 516 };
 517
 518 /* 8169, 8168b and 810x except 8102e. */
 519 enum rtl_tx_desc_bit_0 {
 520         /* First doubleword. */
 521 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 522         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 523         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 524         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 525 };
 526
 527 /* 8102e, 8168c and beyond. */
 528 enum rtl_tx_desc_bit_1 {
 529         /* Second doubleword. */
 530 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 531         TD1_IP_CS       = (1 << 29),            /* Calculate IP checksum */
 532         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 533         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 534 };
 535
 536 static const struct rtl_tx_desc_info {
 537         struct {
 538                 u32 udp;
 539                 u32 tcp;
 540         } checksum;
 541         u16 mss_shift;
 542         u16 opts_offset;
 543 } tx_desc_info [] = {
 544         [RTL_TD_0] = {
 545                 .checksum = {
 546                         .udp    = TD0_IP_CS | TD0_UDP_CS,
 547                         .tcp    = TD0_IP_CS | TD0_TCP_CS
 548                 },
 549                 .mss_shift      = TD0_MSS_SHIFT,
 550                 .opts_offset    = 0
 551         },
 552         [RTL_TD_1] = {
 553                 .checksum = {
 554                         .udp    = TD1_IP_CS | TD1_UDP_CS,
 555                         .tcp    = TD1_IP_CS | TD1_TCP_CS
 556                 },
 557                 .mss_shift      = TD1_MSS_SHIFT,
 558                 .opts_offset    = 1
 559         }
 560 };
 561
 562 enum rtl_rx_desc_bit {
 563         /* Rx private */
 564         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 565         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
 566
 567 #define RxProtoUDP      (PID1)
 568 #define RxProtoTCP      (PID0)
 569 #define RxProtoIP       (PID1 | PID0)
 570 #define RxProtoMask     RxProtoIP
 571
 572         IPFail          = (1 << 16), /* IP checksum failed */
 573         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 574         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 575         RxVlanTag       = (1 << 16), /* VLAN tag available */
 576 };
 577
 578 #define RsvdMask        0x3fffc000
 579
 580 struct TxDesc {
 581         __le32 opts1;
 582         __le32 opts2;
 583         __le64 addr;
 584 };
 585
 586 struct RxDesc {
 587         __le32 opts1;
 588         __le32 opts2;
 589         __le64 addr;
 590 };
 591
 592 struct ring_info {
 593         struct sk_buff  *skb;
 594         u32             len;
 595         u8              __pad[sizeof(void *) - sizeof(u32)];
 596 };
 597
 598 enum features {
 599         RTL_FEATURE_WOL         = (1 << 0),
 600         RTL_FEATURE_MSI         = (1 << 1),
 601         RTL_FEATURE_GMII        = (1 << 2),
 602 };
 603
 604 struct rtl8169_counters {
 605         __le64  tx_packets;
 606         __le64  rx_packets;
 607         __le64  tx_errors;
 608         __le32  rx_errors;
 609         __le16  rx_missed;
 610         __le16  align_errors;
 611         __le32  tx_one_collision;
 612         __le32  tx_multi_collision;
 613         __le64  rx_unicast;
 614         __le64  rx_broadcast;
 615         __le32  rx_multicast;
 616         __le16  tx_aborted;
 617         __le16  tx_underun;
 618 };
 619
 620 struct rtl8169_private {
 621         void __iomem *mmio_addr;        /* memory map physical address */
 622         struct pci_dev *pci_dev;
 623         struct net_device *dev;
 624         struct napi_struct napi;
 625         spinlock_t lock;
 626         u32 msg_enable;
 627         u16 txd_version;
 628         u16 mac_version;
 629         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 630         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 631         u32 dirty_rx;
 632         u32 dirty_tx;
 633         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 634         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 635         dma_addr_t TxPhyAddr;
 636         dma_addr_t RxPhyAddr;
 637         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 638         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 639         struct timer_list timer;
 640         u16 cp_cmd;
 641         u16 intr_event;
 642         u16 napi_event;
 643         u16 intr_mask;
 644
 645         struct mdio_ops {
 646                 void (*write)(void __iomem *, int, int);
 647                 int (*read)(void __iomem *, int);
 648         } mdio_ops;
 649
 650         struct pll_power_ops {
 651                 void (*down)(struct rtl8169_private *);
 652                 void (*up)(struct rtl8169_private *);
 653         } pll_power_ops;
 654
 655         int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
 656         int (*get_settings)(struct net_device *, struct ethtool_cmd *);
 657         void (*phy_reset_enable)(struct rtl8169_private *tp);
 658         void (*hw_start)(struct net_device *);
 659         unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
 660         unsigned int (*link_ok)(void __iomem *);
 661         int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
 662         int pcie_cap;
 663         struct delayed_work task;
 664         unsigned features;
 665
 666         struct mii_if_info mii;
 667         struct rtl8169_counters counters;
 668         u32 saved_wolopts;
 669
 670         const struct firmware *fw;
 671 #define RTL_FIRMWARE_UNKNOWN    ERR_PTR(-EAGAIN);
 672 };
 673
 674 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 675 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 676 module_param(use_dac, int, 0);
 677 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 678 module_param_named(debug, debug.msg_enable, int, 0);
 679 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 680 MODULE_LICENSE("GPL");
 681 MODULE_VERSION(RTL8169_VERSION);
 682 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 683 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 684 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 685 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 686 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 687
 688 static int rtl8169_open(struct net_device *dev);
 689 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
 690                                       struct net_device *dev);
 691 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
 692 static int rtl8169_init_ring(struct net_device *dev);
 693 static void rtl_hw_start(struct net_device *dev);
 694 static int rtl8169_close(struct net_device *dev);
 695 static void rtl_set_rx_mode(struct net_device *dev);
 696 static void rtl8169_tx_timeout(struct net_device *dev);
 697 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
 698 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
 699                                 void __iomem *, u32 budget);
 700 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
 701 static void rtl8169_down(struct net_device *dev);
 702 static void rtl8169_rx_clear(struct rtl8169_private *tp);
 703 static int rtl8169_poll(struct napi_struct *napi, int budget);
 704
 705 static const unsigned int rtl8169_rx_config =
 706         (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
 707
 708 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
 709 {
 710         void __iomem *ioaddr = tp->mmio_addr;
 711         int i;
 712
 713         RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 714         for (i = 0; i < 20; i++) {
 715                 udelay(100);
 716                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
 717                         break;
 718         }
 719         return RTL_R32(OCPDR);
 720 }
 721
 722 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
 723 {
 724         void __iomem *ioaddr = tp->mmio_addr;
 725         int i;
 726
 727         RTL_W32(OCPDR, data);
 728         RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 729         for (i = 0; i < 20; i++) {
 730                 udelay(100);
 731                 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
 732                         break;
 733         }
 734 }
 735
 736 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
 737 {
 738         void __iomem *ioaddr = tp->mmio_addr;
 739         int i;
 740
 741         RTL_W8(ERIDR, cmd);
 742         RTL_W32(ERIAR, 0x800010e8);
 743         msleep(2);
 744         for (i = 0; i < 5; i++) {
 745                 udelay(100);
 746                 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
 747                         break;
 748         }
 749
 750         ocp_write(tp, 0x1, 0x30, 0x00000001);
 751 }
 752
 753 #define OOB_CMD_RESET           0x00
 754 #define OOB_CMD_DRIVER_START    0x05
 755 #define OOB_CMD_DRIVER_STOP     0x06
 756
 757 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
 758 {
 759         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
 760 }
 761
 762 static void rtl8168_driver_start(struct rtl8169_private *tp)
 763 {
 764         u16 reg;
 765         int i;
 766
 767         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
 768
 769         reg = rtl8168_get_ocp_reg(tp);
 770
 771         for (i = 0; i < 10; i++) {
 772                 msleep(10);
 773                 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
 774                         break;
 775         }
 776 }
 777
 778 static void rtl8168_driver_stop(struct rtl8169_private *tp)
 779 {
 780         u16 reg;
 781         int i;
 782
 783         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
 784
 785         reg = rtl8168_get_ocp_reg(tp);
 786
 787         for (i = 0; i < 10; i++) {
 788                 msleep(10);
 789                 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
 790                         break;
 791         }
 792 }
 793
 794 static int r8168dp_check_dash(struct rtl8169_private *tp)
 795 {
 796         u16 reg = rtl8168_get_ocp_reg(tp);
 797
 798         return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
 799 }
 800
 801 static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 802 {
 803         int i;
 804
 805         RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
 806
 807         for (i = 20; i > 0; i--) {
 808                 /*
 809                  * Check if the RTL8169 has completed writing to the specified
 810                  * MII register.
 811                  */
 812                 if (!(RTL_R32(PHYAR) & 0x80000000))
 813                         break;
 814                 udelay(25);
 815         }
 816         /*
 817          * According to hardware specs a 20us delay is required after write
 818          * complete indication, but before sending next command.
 819          */
 820         udelay(20);
 821 }
 822
 823 static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
 824 {
 825         int i, value = -1;
 826
 827         RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
 828
 829         for (i = 20; i > 0; i--) {
 830                 /*
 831                  * Check if the RTL8169 has completed retrieving data from
 832                  * the specified MII register.
 833                  */
 834                 if (RTL_R32(PHYAR) & 0x80000000) {
 835                         value = RTL_R32(PHYAR) & 0xffff;
 836                         break;
 837                 }
 838                 udelay(25);
 839         }
 840         /*
 841          * According to hardware specs a 20us delay is required after read
 842          * complete indication, but before sending next command.
 843          */
 844         udelay(20);
 845
 846         return value;
 847 }
 848
 849 static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
 850 {
 851         int i;
 852
 853         RTL_W32(OCPDR, data |
 854                 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
 855         RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
 856         RTL_W32(EPHY_RXER_NUM, 0);
 857
 858         for (i = 0; i < 100; i++) {
 859                 mdelay(1);
 860                 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
 861                         break;
 862         }
 863 }
 864
 865 static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 866 {
 867         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
 868                 (value & OCPDR_DATA_MASK));
 869 }
 870
 871 static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
 872 {
 873         int i;
 874
 875         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
 876
 877         mdelay(1);
 878         RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
 879         RTL_W32(EPHY_RXER_NUM, 0);
 880
 881         for (i = 0; i < 100; i++) {
 882                 mdelay(1);
 883                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
 884                         break;
 885         }
 886
 887         return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
 888 }
 889
 890 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
 891
 892 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
 893 {
 894         RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
 895 }
 896
 897 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
 898 {
 899         RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
 900 }
 901
 902 static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 903 {
 904         r8168dp_2_mdio_start(ioaddr);
 905
 906         r8169_mdio_write(ioaddr, reg_addr, value);
 907
 908         r8168dp_2_mdio_stop(ioaddr);
 909 }
 910
 911 static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
 912 {
 913         int value;
 914
 915         r8168dp_2_mdio_start(ioaddr);
 916
 917         value = r8169_mdio_read(ioaddr, reg_addr);
 918
 919         r8168dp_2_mdio_stop(ioaddr);
 920
 921         return value;
 922 }
 923
 924 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
 925 {
 926         tp->mdio_ops.write(tp->mmio_addr, location, val);
 927 }
 928
 929 static int rtl_readphy(struct rtl8169_private *tp, int location)
 930 {
 931         return tp->mdio_ops.read(tp->mmio_addr, location);
 932 }
 933
 934 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
 935 {
 936         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
 937 }
 938
 939 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
 940 {
 941         int val;
 942
 943         val = rtl_readphy(tp, reg_addr);
 944         rtl_writephy(tp, reg_addr, (val | p) & ~m);
 945 }
 946
 947 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
 948                            int val)
 949 {
 950         struct rtl8169_private *tp = netdev_priv(dev);
 951
 952         rtl_writephy(tp, location, val);
 953 }
 954
 955 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
 956 {
 957         struct rtl8169_private *tp = netdev_priv(dev);
 958
 959         return rtl_readphy(tp, location);
 960 }
 961
 962 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
 963 {
 964         unsigned int i;
 965
 966         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
 967                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
 968
 969         for (i = 0; i < 100; i++) {
 970                 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
 971                         break;
 972                 udelay(10);
 973         }
 974 }
 975
 976 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
 977 {
 978         u16 value = 0xffff;
 979         unsigned int i;
 980
 981         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
 982
 983         for (i = 0; i < 100; i++) {
 984                 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
 985                         value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
 986                         break;
 987                 }
 988                 udelay(10);
 989         }
 990
 991         return value;
 992 }
 993
 994 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
 995 {
 996         unsigned int i;
 997
 998         RTL_W32(CSIDR, value);
 999         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
1000                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1001
1002         for (i = 0; i < 100; i++) {
1003                 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
1004                         break;
1005                 udelay(10);
1006         }
1007 }
1008
1009 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
1010 {
1011         u32 value = ~0x00;
1012         unsigned int i;
1013
1014         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
1015                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1016
1017         for (i = 0; i < 100; i++) {
1018                 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
1019                         value = RTL_R32(CSIDR);
1020                         break;
1021                 }
1022                 udelay(10);
1023         }
1024
1025         return value;
1026 }
1027
1028 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
1029 {
1030         u8 value = 0xff;
1031         unsigned int i;
1032
1033         RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1034
1035         for (i = 0; i < 300; i++) {
1036                 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
1037                         value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
1038                         break;
1039                 }
1040                 udelay(100);
1041         }
1042
1043         return value;
1044 }
1045
1046 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
1047 {
1048         RTL_W16(IntrMask, 0x0000);
1049
1050         RTL_W16(IntrStatus, 0xffff);
1051 }
1052
1053 static void rtl8169_asic_down(void __iomem *ioaddr)
1054 {
1055         RTL_W8(ChipCmd, 0x00);
1056         rtl8169_irq_mask_and_ack(ioaddr);
1057         RTL_R16(CPlusCmd);
1058 }
1059
1060 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1061 {
1062         void __iomem *ioaddr = tp->mmio_addr;
1063
1064         return RTL_R32(TBICSR) & TBIReset;
1065 }
1066
1067 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1068 {
1069         return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1070 }
1071
1072 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1073 {
1074         return RTL_R32(TBICSR) & TBILinkOk;
1075 }
1076
1077 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1078 {
1079         return RTL_R8(PHYstatus) & LinkStatus;
1080 }
1081
1082 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1083 {
1084         void __iomem *ioaddr = tp->mmio_addr;
1085
1086         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1087 }
1088
1089 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1090 {
1091         unsigned int val;
1092
1093         val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1094         rtl_writephy(tp, MII_BMCR, val & 0xffff);
1095 }
1096
1097 static void __rtl8169_check_link_status(struct net_device *dev,
1098                                         struct rtl8169_private *tp,
1099                                         void __iomem *ioaddr, bool pm)
1100 {
1101         unsigned long flags;
1102
1103         spin_lock_irqsave(&tp->lock, flags);
1104         if (tp->link_ok(ioaddr)) {
1105                 /* This is to cancel a scheduled suspend if there's one. */
1106                 if (pm)
1107                         pm_request_resume(&tp->pci_dev->dev);
1108                 netif_carrier_on(dev);
1109                 if (net_ratelimit())
1110                         netif_info(tp, ifup, dev, "link up\n");
1111         } else {
1112                 netif_carrier_off(dev);
1113                 netif_info(tp, ifdown, dev, "link down\n");
1114                 if (pm)
1115                         pm_schedule_suspend(&tp->pci_dev->dev, 100);
1116         }
1117         spin_unlock_irqrestore(&tp->lock, flags);
1118 }
1119
1120 static void rtl8169_check_link_status(struct net_device *dev,
1121                                       struct rtl8169_private *tp,
1122                                       void __iomem *ioaddr)
1123 {
1124         __rtl8169_check_link_status(dev, tp, ioaddr, false);
1125 }
1126
1127 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1128
1129 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1130 {
1131         void __iomem *ioaddr = tp->mmio_addr;
1132         u8 options;
1133         u32 wolopts = 0;
1134
1135         options = RTL_R8(Config1);
1136         if (!(options & PMEnable))
1137                 return 0;
1138
1139         options = RTL_R8(Config3);
1140         if (options & LinkUp)
1141                 wolopts |= WAKE_PHY;
1142         if (options & MagicPacket)
1143                 wolopts |= WAKE_MAGIC;
1144
1145         options = RTL_R8(Config5);
1146         if (options & UWF)
1147                 wolopts |= WAKE_UCAST;
1148         if (options & BWF)
1149                 wolopts |= WAKE_BCAST;
1150         if (options & MWF)
1151                 wolopts |= WAKE_MCAST;
1152
1153         return wolopts;
1154 }
1155
1156 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1157 {
1158         struct rtl8169_private *tp = netdev_priv(dev);
1159
1160         spin_lock_irq(&tp->lock);
1161
1162         wol->supported = WAKE_ANY;
1163         wol->wolopts = __rtl8169_get_wol(tp);
1164
1165         spin_unlock_irq(&tp->lock);
1166 }
1167
1168 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1169 {
1170         void __iomem *ioaddr = tp->mmio_addr;
1171         unsigned int i;
1172         static const struct {
1173                 u32 opt;
1174                 u16 reg;
1175                 u8  mask;
1176         } cfg[] = {
1177                 { WAKE_ANY,   Config1, PMEnable },
1178                 { WAKE_PHY,   Config3, LinkUp },
1179                 { WAKE_MAGIC, Config3, MagicPacket },
1180                 { WAKE_UCAST, Config5, UWF },
1181                 { WAKE_BCAST, Config5, BWF },
1182                 { WAKE_MCAST, Config5, MWF },
1183                 { WAKE_ANY,   Config5, LanWake }
1184         };
1185
1186         RTL_W8(Cfg9346, Cfg9346_Unlock);
1187
1188         for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1189                 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1190                 if (wolopts & cfg[i].opt)
1191                         options |= cfg[i].mask;
1192                 RTL_W8(cfg[i].reg, options);
1193         }
1194
1195         RTL_W8(Cfg9346, Cfg9346_Lock);
1196 }
1197
1198 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1199 {
1200         struct rtl8169_private *tp = netdev_priv(dev);
1201
1202         spin_lock_irq(&tp->lock);
1203
1204         if (wol->wolopts)
1205                 tp->features |= RTL_FEATURE_WOL;
1206         else
1207                 tp->features &= ~RTL_FEATURE_WOL;
1208         __rtl8169_set_wol(tp, wol->wolopts);
1209         spin_unlock_irq(&tp->lock);
1210
1211         device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1212
1213         return 0;
1214 }
1215
1216 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1217 {
1218         return rtl_chip_infos[tp->mac_version].fw_name;
1219 }
1220
1221 static void rtl8169_get_drvinfo(struct net_device *dev,
1222                                 struct ethtool_drvinfo *info)
1223 {
1224         struct rtl8169_private *tp = netdev_priv(dev);
1225
1226         strcpy(info->driver, MODULENAME);
1227         strcpy(info->version, RTL8169_VERSION);
1228         strcpy(info->bus_info, pci_name(tp->pci_dev));
1229         strncpy(info->fw_version, IS_ERR_OR_NULL(tp->fw) ? "N/A" :
1230                 rtl_lookup_firmware_name(tp), sizeof(info->fw_version) - 1);
1231 }
1232
1233 static int rtl8169_get_regs_len(struct net_device *dev)
1234 {
1235         return R8169_REGS_SIZE;
1236 }
1237
1238 static int rtl8169_set_speed_tbi(struct net_device *dev,
1239                                  u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1240 {
1241         struct rtl8169_private *tp = netdev_priv(dev);
1242         void __iomem *ioaddr = tp->mmio_addr;
1243         int ret = 0;
1244         u32 reg;
1245
1246         reg = RTL_R32(TBICSR);
1247         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1248             (duplex == DUPLEX_FULL)) {
1249                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1250         } else if (autoneg == AUTONEG_ENABLE)
1251                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1252         else {
1253                 netif_warn(tp, link, dev,
1254                            "incorrect speed setting refused in TBI mode\n");
1255                 ret = -EOPNOTSUPP;
1256         }
1257
1258         return ret;
1259 }
1260
1261 static int rtl8169_set_speed_xmii(struct net_device *dev,
1262                                   u8 autoneg, u16 speed, u8 duplex, u32 adv)
1263 {
1264         struct rtl8169_private *tp = netdev_priv(dev);
1265         int giga_ctrl, bmcr;
1266         int rc = -EINVAL;
1267
1268         rtl_writephy(tp, 0x1f, 0x0000);
1269
1270         if (autoneg == AUTONEG_ENABLE) {
1271                 int auto_nego;
1272
1273                 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1274                 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1275                                 ADVERTISE_100HALF | ADVERTISE_100FULL);
1276
1277                 if (adv & ADVERTISED_10baseT_Half)
1278                         auto_nego |= ADVERTISE_10HALF;
1279                 if (adv & ADVERTISED_10baseT_Full)
1280                         auto_nego |= ADVERTISE_10FULL;
1281                 if (adv & ADVERTISED_100baseT_Half)
1282                         auto_nego |= ADVERTISE_100HALF;
1283                 if (adv & ADVERTISED_100baseT_Full)
1284                         auto_nego |= ADVERTISE_100FULL;
1285
1286                 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1287
1288                 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1289                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1290
1291                 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1292                 if (tp->mii.supports_gmii) {
1293                         if (adv & ADVERTISED_1000baseT_Half)
1294                                 giga_ctrl |= ADVERTISE_1000HALF;
1295                         if (adv & ADVERTISED_1000baseT_Full)
1296                                 giga_ctrl |= ADVERTISE_1000FULL;
1297                 } else if (adv & (ADVERTISED_1000baseT_Half |
1298                                   ADVERTISED_1000baseT_Full)) {
1299                         netif_info(tp, link, dev,
1300                                    "PHY does not support 1000Mbps\n");
1301                         goto out;
1302                 }
1303
1304                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1305
1306                 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1307                 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1308         } else {
1309                 giga_ctrl = 0;
1310
1311                 if (speed == SPEED_10)
1312                         bmcr = 0;
1313                 else if (speed == SPEED_100)
1314                         bmcr = BMCR_SPEED100;
1315                 else
1316                         goto out;
1317
1318                 if (duplex == DUPLEX_FULL)
1319                         bmcr |= BMCR_FULLDPLX;
1320         }
1321
1322         rtl_writephy(tp, MII_BMCR, bmcr);
1323
1324         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1325             tp->mac_version == RTL_GIGA_MAC_VER_03) {
1326                 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1327                         rtl_writephy(tp, 0x17, 0x2138);
1328                         rtl_writephy(tp, 0x0e, 0x0260);
1329                 } else {
1330                         rtl_writephy(tp, 0x17, 0x2108);
1331                         rtl_writephy(tp, 0x0e, 0x0000);
1332                 }
1333         }
1334
1335         rc = 0;
1336 out:
1337         return rc;
1338 }
1339
1340 static int rtl8169_set_speed(struct net_device *dev,
1341                              u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1342 {
1343         struct rtl8169_private *tp = netdev_priv(dev);
1344         int ret;
1345
1346         ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1347         if (ret < 0)
1348                 goto out;
1349
1350         if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1351             (advertising & ADVERTISED_1000baseT_Full)) {
1352                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1353         }
1354 out:
1355         return ret;
1356 }
1357
1358 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1359 {
1360         struct rtl8169_private *tp = netdev_priv(dev);
1361         unsigned long flags;
1362         int ret;
1363
1364         del_timer_sync(&tp->timer);
1365
1366         spin_lock_irqsave(&tp->lock, flags);
1367         ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
1368                                 cmd->duplex, cmd->advertising);
1369         spin_unlock_irqrestore(&tp->lock, flags);
1370
1371         return ret;
1372 }
1373
1374 static u32 rtl8169_fix_features(struct net_device *dev, u32 features)
1375 {
1376         if (dev->mtu > TD_MSS_MAX)
1377                 features &= ~NETIF_F_ALL_TSO;
1378
1379         return features;
1380 }
1381
1382 static int rtl8169_set_features(struct net_device *dev, u32 features)
1383 {
1384         struct rtl8169_private *tp = netdev_priv(dev);
1385         void __iomem *ioaddr = tp->mmio_addr;
1386         unsigned long flags;
1387
1388         spin_lock_irqsave(&tp->lock, flags);
1389
1390         if (features & NETIF_F_RXCSUM)
1391                 tp->cp_cmd |= RxChkSum;
1392         else
1393                 tp->cp_cmd &= ~RxChkSum;
1394
1395         if (dev->features & NETIF_F_HW_VLAN_RX)
1396                 tp->cp_cmd |= RxVlan;
1397         else
1398                 tp->cp_cmd &= ~RxVlan;
1399
1400         RTL_W16(CPlusCmd, tp->cp_cmd);
1401         RTL_R16(CPlusCmd);
1402
1403         spin_unlock_irqrestore(&tp->lock, flags);
1404
1405         return 0;
1406 }
1407
1408 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1409                                       struct sk_buff *skb)
1410 {
1411         return (vlan_tx_tag_present(skb)) ?
1412                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1413 }
1414
1415 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1416 {
1417         u32 opts2 = le32_to_cpu(desc->opts2);
1418
1419         if (opts2 & RxVlanTag)
1420                 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
1421
1422         desc->opts2 = 0;
1423 }
1424
1425 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1426 {
1427         struct rtl8169_private *tp = netdev_priv(dev);
1428         void __iomem *ioaddr = tp->mmio_addr;
1429         u32 status;
1430
1431         cmd->supported =
1432                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1433         cmd->port = PORT_FIBRE;
1434         cmd->transceiver = XCVR_INTERNAL;
1435
1436         status = RTL_R32(TBICSR);
1437         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
1438         cmd->autoneg = !!(status & TBINwEnable);
1439
1440         ethtool_cmd_speed_set(cmd, SPEED_1000);
1441         cmd->duplex = DUPLEX_FULL; /* Always set */
1442
1443         return 0;
1444 }
1445
1446 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1447 {
1448         struct rtl8169_private *tp = netdev_priv(dev);
1449
1450         return mii_ethtool_gset(&tp->mii, cmd);
1451 }
1452
1453 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1454 {
1455         struct rtl8169_private *tp = netdev_priv(dev);
1456         unsigned long flags;
1457         int rc;
1458
1459         spin_lock_irqsave(&tp->lock, flags);
1460
1461         rc = tp->get_settings(dev, cmd);
1462
1463         spin_unlock_irqrestore(&tp->lock, flags);
1464         return rc;
1465 }
1466
1467 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1468                              void *p)
1469 {
1470         struct rtl8169_private *tp = netdev_priv(dev);
1471         unsigned long flags;
1472
1473         if (regs->len > R8169_REGS_SIZE)
1474                 regs->len = R8169_REGS_SIZE;
1475
1476         spin_lock_irqsave(&tp->lock, flags);
1477         memcpy_fromio(p, tp->mmio_addr, regs->len);
1478         spin_unlock_irqrestore(&tp->lock, flags);
1479 }
1480
1481 static u32 rtl8169_get_msglevel(struct net_device *dev)
1482 {
1483         struct rtl8169_private *tp = netdev_priv(dev);
1484
1485         return tp->msg_enable;
1486 }
1487
1488 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1489 {
1490         struct rtl8169_private *tp = netdev_priv(dev);
1491
1492         tp->msg_enable = value;
1493 }
1494
1495 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1496         "tx_packets",
1497         "rx_packets",
1498         "tx_errors",
1499         "rx_errors",
1500         "rx_missed",
1501         "align_errors",
1502         "tx_single_collisions",
1503         "tx_multi_collisions",
1504         "unicast",
1505         "broadcast",
1506         "multicast",
1507         "tx_aborted",
1508         "tx_underrun",
1509 };
1510
1511 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1512 {
1513         switch (sset) {
1514         case ETH_SS_STATS:
1515                 return ARRAY_SIZE(rtl8169_gstrings);
1516         default:
1517                 return -EOPNOTSUPP;
1518         }
1519 }
1520
1521 static void rtl8169_update_counters(struct net_device *dev)
1522 {
1523         struct rtl8169_private *tp = netdev_priv(dev);
1524         void __iomem *ioaddr = tp->mmio_addr;
1525         struct device *d = &tp->pci_dev->dev;
1526         struct rtl8169_counters *counters;
1527         dma_addr_t paddr;
1528         u32 cmd;
1529         int wait = 1000;
1530
1531         /*
1532          * Some chips are unable to dump tally counters when the receiver
1533          * is disabled.
1534          */
1535         if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1536                 return;
1537
1538         counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1539         if (!counters)
1540                 return;
1541
1542         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1543         cmd = (u64)paddr & DMA_BIT_MASK(32);
1544         RTL_W32(CounterAddrLow, cmd);
1545         RTL_W32(CounterAddrLow, cmd | CounterDump);
1546
1547         while (wait--) {
1548                 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1549                         memcpy(&tp->counters, counters, sizeof(*counters));
1550                         break;
1551                 }
1552                 udelay(10);
1553         }
1554
1555         RTL_W32(CounterAddrLow, 0);
1556         RTL_W32(CounterAddrHigh, 0);
1557
1558         dma_free_coherent(d, sizeof(*counters), counters, paddr);
1559 }
1560
1561 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1562                                       struct ethtool_stats *stats, u64 *data)
1563 {
1564         struct rtl8169_private *tp = netdev_priv(dev);
1565
1566         ASSERT_RTNL();
1567
1568         rtl8169_update_counters(dev);
1569
1570         data[0] = le64_to_cpu(tp->counters.tx_packets);
1571         data[1] = le64_to_cpu(tp->counters.rx_packets);
1572         data[2] = le64_to_cpu(tp->counters.tx_errors);
1573         data[3] = le32_to_cpu(tp->counters.rx_errors);
1574         data[4] = le16_to_cpu(tp->counters.rx_missed);
1575         data[5] = le16_to_cpu(tp->counters.align_errors);
1576         data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1577         data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1578         data[8] = le64_to_cpu(tp->counters.rx_unicast);
1579         data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1580         data[10] = le32_to_cpu(tp->counters.rx_multicast);
1581         data[11] = le16_to_cpu(tp->counters.tx_aborted);
1582         data[12] = le16_to_cpu(tp->counters.tx_underun);
1583 }
1584
1585 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1586 {
1587         switch(stringset) {
1588         case ETH_SS_STATS:
1589                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1590                 break;
1591         }
1592 }
1593
1594 static const struct ethtool_ops rtl8169_ethtool_ops = {
1595         .get_drvinfo            = rtl8169_get_drvinfo,
1596         .get_regs_len           = rtl8169_get_regs_len,
1597         .get_link               = ethtool_op_get_link,
1598         .get_settings           = rtl8169_get_settings,
1599         .set_settings           = rtl8169_set_settings,
1600         .get_msglevel           = rtl8169_get_msglevel,
1601         .set_msglevel           = rtl8169_set_msglevel,
1602         .get_regs               = rtl8169_get_regs,
1603         .get_wol                = rtl8169_get_wol,
1604         .set_wol                = rtl8169_set_wol,
1605         .get_strings            = rtl8169_get_strings,
1606         .get_sset_count         = rtl8169_get_sset_count,
1607         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1608 };
1609
1610 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1611                                     struct net_device *dev, u8 default_version)
1612 {
1613         void __iomem *ioaddr = tp->mmio_addr;
1614         /*
1615          * The driver currently handles the 8168Bf and the 8168Be identically
1616          * but they can be identified more specifically through the test below
1617          * if needed:
1618          *
1619          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1620          *
1621          * Same thing for the 8101Eb and the 8101Ec:
1622          *
1623          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1624          */
1625         static const struct rtl_mac_info {
1626                 u32 mask;
1627                 u32 val;
1628                 int mac_version;
1629         } mac_info[] = {
1630                 /* 8168E family. */
1631                 { 0x7cf00000, 0x2c200000,       RTL_GIGA_MAC_VER_33 },
1632                 { 0x7cf00000, 0x2c100000,       RTL_GIGA_MAC_VER_32 },
1633                 { 0x7c800000, 0x2c000000,       RTL_GIGA_MAC_VER_33 },
1634
1635                 /* 8168D family. */
1636                 { 0x7cf00000, 0x28300000,       RTL_GIGA_MAC_VER_26 },
1637                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
1638                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
1639
1640                 /* 8168DP family. */
1641                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
1642                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
1643                 { 0x7cf00000, 0x28b00000,       RTL_GIGA_MAC_VER_31 },
1644
1645                 /* 8168C family. */
1646                 { 0x7cf00000, 0x3cb00000,       RTL_GIGA_MAC_VER_24 },
1647                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
1648                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
1649                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
1650                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
1651                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
1652                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
1653                 { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
1654                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
1655
1656                 /* 8168B family. */
1657                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
1658                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
1659                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
1660                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
1661
1662                 /* 8101 family. */
1663                 { 0x7cf00000, 0x40b00000,       RTL_GIGA_MAC_VER_30 },
1664                 { 0x7cf00000, 0x40a00000,       RTL_GIGA_MAC_VER_30 },
1665                 { 0x7cf00000, 0x40900000,       RTL_GIGA_MAC_VER_29 },
1666                 { 0x7c800000, 0x40800000,       RTL_GIGA_MAC_VER_30 },
1667                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
1668                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
1669                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
1670                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
1671                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
1672                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
1673                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
1674                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
1675                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
1676                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
1677                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
1678                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
1679                 /* FIXME: where did these entries come from ? -- FR */
1680                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
1681                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
1682
1683                 /* 8110 family. */
1684                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
1685                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
1686                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
1687                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
1688                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
1689                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
1690
1691                 /* Catch-all */
1692                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
1693         };
1694         const struct rtl_mac_info *p = mac_info;
1695         u32 reg;
1696
1697         reg = RTL_R32(TxConfig);
1698         while ((reg & p->mask) != p->val)
1699                 p++;
1700         tp->mac_version = p->mac_version;
1701
1702         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
1703                 netif_notice(tp, probe, dev,
1704                              "unknown MAC, using family default\n");
1705                 tp->mac_version = default_version;
1706         }
1707 }
1708
1709 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1710 {
1711         dprintk("mac_version = 0x%02x\n", tp->mac_version);
1712 }
1713
1714 struct phy_reg {
1715         u16 reg;
1716         u16 val;
1717 };
1718
1719 static void rtl_writephy_batch(struct rtl8169_private *tp,
1720                                const struct phy_reg *regs, int len)
1721 {
1722         while (len-- > 0) {
1723                 rtl_writephy(tp, regs->reg, regs->val);
1724                 regs++;
1725         }
1726 }
1727
1728 #define PHY_READ                0x00000000
1729 #define PHY_DATA_OR             0x10000000
1730 #define PHY_DATA_AND            0x20000000
1731 #define PHY_BJMPN               0x30000000
1732 #define PHY_READ_EFUSE          0x40000000
1733 #define PHY_READ_MAC_BYTE       0x50000000
1734 #define PHY_WRITE_MAC_BYTE      0x60000000
1735 #define PHY_CLEAR_READCOUNT     0x70000000
1736 #define PHY_WRITE               0x80000000
1737 #define PHY_READCOUNT_EQ_SKIP   0x90000000
1738 #define PHY_COMP_EQ_SKIPN       0xa0000000
1739 #define PHY_COMP_NEQ_SKIPN      0xb0000000
1740 #define PHY_WRITE_PREVIOUS      0xc0000000
1741 #define PHY_SKIPN               0xd0000000
1742 #define PHY_DELAY_MS            0xe0000000
1743 #define PHY_WRITE_ERI_WORD      0xf0000000
1744
1745 static void
1746 rtl_phy_write_fw(struct rtl8169_private *tp, const struct firmware *fw)
1747 {
1748         __le32 *phytable = (__le32 *)fw->data;
1749         struct net_device *dev = tp->dev;
1750         size_t index, fw_size = fw->size / sizeof(*phytable);
1751         u32 predata, count;
1752
1753         if (fw->size % sizeof(*phytable)) {
1754                 netif_err(tp, probe, dev, "odd sized firmware %zd\n", fw->size);
1755                 return;
1756         }
1757
1758         for (index = 0; index < fw_size; index++) {
1759                 u32 action = le32_to_cpu(phytable[index]);
1760                 u32 regno = (action & 0x0fff0000) >> 16;
1761
1762                 switch(action & 0xf0000000) {
1763                 case PHY_READ:
1764                 case PHY_DATA_OR:
1765                 case PHY_DATA_AND:
1766                 case PHY_READ_EFUSE:
1767                 case PHY_CLEAR_READCOUNT:
1768                 case PHY_WRITE:
1769                 case PHY_WRITE_PREVIOUS:
1770                 case PHY_DELAY_MS:
1771                         break;
1772
1773                 case PHY_BJMPN:
1774                         if (regno > index) {
1775                                 netif_err(tp, probe, tp->dev,
1776                                           "Out of range of firmware\n");
1777                                 return;
1778                         }
1779                         break;
1780                 case PHY_READCOUNT_EQ_SKIP:
1781                         if (index + 2 >= fw_size) {
1782                                 netif_err(tp, probe, tp->dev,
1783                                           "Out of range of firmware\n");
1784                                 return;
1785                         }
1786                         break;
1787                 case PHY_COMP_EQ_SKIPN:
1788                 case PHY_COMP_NEQ_SKIPN:
1789                 case PHY_SKIPN:
1790                         if (index + 1 + regno >= fw_size) {
1791                                 netif_err(tp, probe, tp->dev,
1792                                           "Out of range of firmware\n");
1793                                 return;
1794                         }
1795                         break;
1796
1797                 case PHY_READ_MAC_BYTE:
1798                 case PHY_WRITE_MAC_BYTE:
1799                 case PHY_WRITE_ERI_WORD:
1800                 default:
1801                         netif_err(tp, probe, tp->dev,
1802                                   "Invalid action 0x%08x\n", action);
1803                         return;
1804                 }
1805         }
1806
1807         predata = 0;
1808         count = 0;
1809
1810         for (index = 0; index < fw_size; ) {
1811                 u32 action = le32_to_cpu(phytable[index]);
1812                 u32 data = action & 0x0000ffff;
1813                 u32 regno = (action & 0x0fff0000) >> 16;
1814
1815                 if (!action)
1816                         break;
1817
1818                 switch(action & 0xf0000000) {
1819                 case PHY_READ:
1820                         predata = rtl_readphy(tp, regno);
1821                         count++;
1822                         index++;
1823                         break;
1824                 case PHY_DATA_OR:
1825                         predata |= data;
1826                         index++;
1827                         break;
1828                 case PHY_DATA_AND:
1829                         predata &= data;
1830                         index++;
1831                         break;
1832                 case PHY_BJMPN:
1833                         index -= regno;
1834                         break;
1835                 case PHY_READ_EFUSE:
1836                         predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
1837                         index++;
1838                         break;
1839                 case PHY_CLEAR_READCOUNT:
1840                         count = 0;
1841                         index++;
1842                         break;
1843                 case PHY_WRITE:
1844                         rtl_writephy(tp, regno, data);
1845                         index++;
1846                         break;
1847                 case PHY_READCOUNT_EQ_SKIP:
1848                         index += (count == data) ? 2 : 1;
1849                         break;
1850                 case PHY_COMP_EQ_SKIPN:
1851                         if (predata == data)
1852                                 index += regno;
1853                         index++;
1854                         break;
1855                 case PHY_COMP_NEQ_SKIPN:
1856                         if (predata != data)
1857                                 index += regno;
1858                         index++;
1859                         break;
1860                 case PHY_WRITE_PREVIOUS:
1861                         rtl_writephy(tp, regno, predata);
1862                         index++;
1863                         break;
1864                 case PHY_SKIPN:
1865                         index += regno + 1;
1866                         break;
1867                 case PHY_DELAY_MS:
1868                         mdelay(data);
1869                         index++;
1870                         break;
1871
1872                 case PHY_READ_MAC_BYTE:
1873                 case PHY_WRITE_MAC_BYTE:
1874                 case PHY_WRITE_ERI_WORD:
1875                 default:
1876                         BUG();
1877                 }
1878         }
1879 }
1880
1881 static void rtl_release_firmware(struct rtl8169_private *tp)
1882 {
1883         if (!IS_ERR_OR_NULL(tp->fw))
1884                 release_firmware(tp->fw);
1885         tp->fw = RTL_FIRMWARE_UNKNOWN;
1886 }
1887
1888 static void rtl_apply_firmware(struct rtl8169_private *tp)
1889 {
1890         const struct firmware *fw = tp->fw;
1891
1892         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
1893         if (!IS_ERR_OR_NULL(fw))
1894                 rtl_phy_write_fw(tp, fw);
1895 }
1896
1897 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
1898 {
1899         if (rtl_readphy(tp, reg) != val)
1900                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
1901         else
1902                 rtl_apply_firmware(tp);
1903 }
1904
1905 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1906 {
1907         static const struct phy_reg phy_reg_init[] = {
1908                 { 0x1f, 0x0001 },
1909                 { 0x06, 0x006e },
1910                 { 0x08, 0x0708 },
1911                 { 0x15, 0x4000 },
1912                 { 0x18, 0x65c7 },
1913
1914                 { 0x1f, 0x0001 },
1915                 { 0x03, 0x00a1 },
1916                 { 0x02, 0x0008 },
1917                 { 0x01, 0x0120 },
1918                 { 0x00, 0x1000 },
1919                 { 0x04, 0x0800 },
1920                 { 0x04, 0x0000 },
1921
1922                 { 0x03, 0xff41 },
1923                 { 0x02, 0xdf60 },
1924                 { 0x01, 0x0140 },
1925                 { 0x00, 0x0077 },
1926                 { 0x04, 0x7800 },
1927                 { 0x04, 0x7000 },
1928
1929                 { 0x03, 0x802f },
1930                 { 0x02, 0x4f02 },
1931                 { 0x01, 0x0409 },
1932                 { 0x00, 0xf0f9 },
1933                 { 0x04, 0x9800 },
1934                 { 0x04, 0x9000 },
1935
1936                 { 0x03, 0xdf01 },
1937                 { 0x02, 0xdf20 },
1938                 { 0x01, 0xff95 },
1939                 { 0x00, 0xba00 },
1940                 { 0x04, 0xa800 },
1941                 { 0x04, 0xa000 },
1942
1943                 { 0x03, 0xff41 },
1944                 { 0x02, 0xdf20 },
1945                 { 0x01, 0x0140 },
1946                 { 0x00, 0x00bb },
1947                 { 0x04, 0xb800 },
1948                 { 0x04, 0xb000 },
1949
1950                 { 0x03, 0xdf41 },
1951                 { 0x02, 0xdc60 },
1952                 { 0x01, 0x6340 },
1953                 { 0x00, 0x007d },
1954                 { 0x04, 0xd800 },
1955                 { 0x04, 0xd000 },
1956
1957                 { 0x03, 0xdf01 },
1958                 { 0x02, 0xdf20 },
1959                 { 0x01, 0x100a },
1960                 { 0x00, 0xa0ff },
1961                 { 0x04, 0xf800 },
1962                 { 0x04, 0xf000 },
1963
1964                 { 0x1f, 0x0000 },
1965                 { 0x0b, 0x0000 },
1966                 { 0x00, 0x9200 }
1967         };
1968
1969         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1970 }
1971
1972 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
1973 {
1974         static const struct phy_reg phy_reg_init[] = {
1975                 { 0x1f, 0x0002 },
1976                 { 0x01, 0x90d0 },
1977                 { 0x1f, 0x0000 }
1978         };
1979
1980         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1981 }
1982
1983 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
1984 {
1985         struct pci_dev *pdev = tp->pci_dev;
1986         u16 vendor_id, device_id;
1987
1988         pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
1989         pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
1990
1991         if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
1992                 return;
1993
1994         rtl_writephy(tp, 0x1f, 0x0001);
1995         rtl_writephy(tp, 0x10, 0xf01b);
1996         rtl_writephy(tp, 0x1f, 0x0000);
1997 }
1998
1999 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2000 {
2001         static const struct phy_reg phy_reg_init[] = {
2002                 { 0x1f, 0x0001 },
2003                 { 0x04, 0x0000 },
2004                 { 0x03, 0x00a1 },
2005                 { 0x02, 0x0008 },
2006                 { 0x01, 0x0120 },
2007                 { 0x00, 0x1000 },
2008                 { 0x04, 0x0800 },
2009                 { 0x04, 0x9000 },
2010                 { 0x03, 0x802f },
2011                 { 0x02, 0x4f02 },
2012                 { 0x01, 0x0409 },
2013                 { 0x00, 0xf099 },
2014                 { 0x04, 0x9800 },
2015                 { 0x04, 0xa000 },
2016                 { 0x03, 0xdf01 },
2017                 { 0x02, 0xdf20 },
2018                 { 0x01, 0xff95 },
2019                 { 0x00, 0xba00 },
2020                 { 0x04, 0xa800 },
2021                 { 0x04, 0xf000 },
2022                 { 0x03, 0xdf01 },
2023                 { 0x02, 0xdf20 },
2024                 { 0x01, 0x101a },
2025                 { 0x00, 0xa0ff },
2026                 { 0x04, 0xf800 },
2027                 { 0x04, 0x0000 },
2028                 { 0x1f, 0x0000 },
2029
2030                 { 0x1f, 0x0001 },
2031                 { 0x10, 0xf41b },
2032                 { 0x14, 0xfb54 },
2033                 { 0x18, 0xf5c7 },
2034                 { 0x1f, 0x0000 },
2035
2036                 { 0x1f, 0x0001 },
2037                 { 0x17, 0x0cc0 },
2038                 { 0x1f, 0x0000 }
2039         };
2040
2041         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2042
2043         rtl8169scd_hw_phy_config_quirk(tp);
2044 }
2045
2046 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2047 {
2048         static const struct phy_reg phy_reg_init[] = {
2049                 { 0x1f, 0x0001 },
2050                 { 0x04, 0x0000 },
2051                 { 0x03, 0x00a1 },
2052                 { 0x02, 0x0008 },
2053                 { 0x01, 0x0120 },
2054                 { 0x00, 0x1000 },
2055                 { 0x04, 0x0800 },
2056                 { 0x04, 0x9000 },
2057                 { 0x03, 0x802f },
2058                 { 0x02, 0x4f02 },
2059                 { 0x01, 0x0409 },
2060                 { 0x00, 0xf099 },
2061                 { 0x04, 0x9800 },
2062                 { 0x04, 0xa000 },
2063                 { 0x03, 0xdf01 },
2064                 { 0x02, 0xdf20 },
2065                 { 0x01, 0xff95 },
2066                 { 0x00, 0xba00 },
2067                 { 0x04, 0xa800 },
2068                 { 0x04, 0xf000 },
2069                 { 0x03, 0xdf01 },
2070                 { 0x02, 0xdf20 },
2071                 { 0x01, 0x101a },
2072                 { 0x00, 0xa0ff },
2073                 { 0x04, 0xf800 },
2074                 { 0x04, 0x0000 },
2075                 { 0x1f, 0x0000 },
2076
2077                 { 0x1f, 0x0001 },
2078                 { 0x0b, 0x8480 },
2079                 { 0x1f, 0x0000 },
2080
2081                 { 0x1f, 0x0001 },
2082                 { 0x18, 0x67c7 },
2083                 { 0x04, 0x2000 },
2084                 { 0x03, 0x002f },
2085                 { 0x02, 0x4360 },
2086                 { 0x01, 0x0109 },
2087                 { 0x00, 0x3022 },
2088                 { 0x04, 0x2800 },
2089                 { 0x1f, 0x0000 },
2090
2091                 { 0x1f, 0x0001 },
2092                 { 0x17, 0x0cc0 },
2093                 { 0x1f, 0x0000 }
2094         };
2095
2096         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2097 }
2098
2099 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2100 {
2101         static const struct phy_reg phy_reg_init[] = {
2102                 { 0x10, 0xf41b },
2103                 { 0x1f, 0x0000 }
2104         };
2105
2106         rtl_writephy(tp, 0x1f, 0x0001);
2107         rtl_patchphy(tp, 0x16, 1 << 0);
2108
2109         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2110 }
2111
2112 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2113 {
2114         static const struct phy_reg phy_reg_init[] = {
2115                 { 0x1f, 0x0001 },
2116                 { 0x10, 0xf41b },
2117                 { 0x1f, 0x0000 }
2118         };
2119
2120         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2121 }
2122
2123 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2124 {
2125         static const struct phy_reg phy_reg_init[] = {
2126                 { 0x1f, 0x0000 },
2127                 { 0x1d, 0x0f00 },
2128                 { 0x1f, 0x0002 },
2129                 { 0x0c, 0x1ec8 },
2130                 { 0x1f, 0x0000 }
2131         };
2132
2133         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2134 }
2135
2136 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2137 {
2138         static const struct phy_reg phy_reg_init[] = {
2139                 { 0x1f, 0x0001 },
2140                 { 0x1d, 0x3d98 },
2141                 { 0x1f, 0x0000 }
2142         };
2143
2144         rtl_writephy(tp, 0x1f, 0x0000);
2145         rtl_patchphy(tp, 0x14, 1 << 5);
2146         rtl_patchphy(tp, 0x0d, 1 << 5);
2147
2148         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2149 }
2150
2151 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2152 {
2153         static const struct phy_reg phy_reg_init[] = {
2154                 { 0x1f, 0x0001 },
2155                 { 0x12, 0x2300 },
2156                 { 0x1f, 0x0002 },
2157                 { 0x00, 0x88d4 },
2158                 { 0x01, 0x82b1 },
2159                 { 0x03, 0x7002 },
2160                 { 0x08, 0x9e30 },
2161                 { 0x09, 0x01f0 },
2162                 { 0x0a, 0x5500 },
2163                 { 0x0c, 0x00c8 },
2164                 { 0x1f, 0x0003 },
2165                 { 0x12, 0xc096 },
2166                 { 0x16, 0x000a },
2167                 { 0x1f, 0x0000 },
2168                 { 0x1f, 0x0000 },
2169                 { 0x09, 0x2000 },
2170                 { 0x09, 0x0000 }
2171         };
2172
2173         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2174
2175         rtl_patchphy(tp, 0x14, 1 << 5);
2176         rtl_patchphy(tp, 0x0d, 1 << 5);
2177         rtl_writephy(tp, 0x1f, 0x0000);
2178 }
2179
2180 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2181 {
2182         static const struct phy_reg phy_reg_init[] = {
2183                 { 0x1f, 0x0001 },
2184                 { 0x12, 0x2300 },
2185                 { 0x03, 0x802f },
2186                 { 0x02, 0x4f02 },
2187                 { 0x01, 0x0409 },
2188                 { 0x00, 0xf099 },
2189                 { 0x04, 0x9800 },
2190                 { 0x04, 0x9000 },
2191                 { 0x1d, 0x3d98 },
2192                 { 0x1f, 0x0002 },
2193                 { 0x0c, 0x7eb8 },
2194                 { 0x06, 0x0761 },
2195                 { 0x1f, 0x0003 },
2196                 { 0x16, 0x0f0a },
2197                 { 0x1f, 0x0000 }
2198         };
2199
2200         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2201
2202         rtl_patchphy(tp, 0x16, 1 << 0);
2203         rtl_patchphy(tp, 0x14, 1 << 5);
2204         rtl_patchphy(tp, 0x0d, 1 << 5);
2205         rtl_writephy(tp, 0x1f, 0x0000);
2206 }
2207
2208 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2209 {
2210         static const struct phy_reg phy_reg_init[] = {
2211                 { 0x1f, 0x0001 },
2212                 { 0x12, 0x2300 },
2213                 { 0x1d, 0x3d98 },
2214                 { 0x1f, 0x0002 },
2215                 { 0x0c, 0x7eb8 },
2216                 { 0x06, 0x5461 },
2217                 { 0x1f, 0x0003 },
2218                 { 0x16, 0x0f0a },
2219                 { 0x1f, 0x0000 }
2220         };
2221
2222         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2223
2224         rtl_patchphy(tp, 0x16, 1 << 0);
2225         rtl_patchphy(tp, 0x14, 1 << 5);
2226         rtl_patchphy(tp, 0x0d, 1 << 5);
2227         rtl_writephy(tp, 0x1f, 0x0000);
2228 }
2229
2230 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2231 {
2232         rtl8168c_3_hw_phy_config(tp);
2233 }
2234
2235 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2236 {
2237         static const struct phy_reg phy_reg_init_0[] = {
2238                 /* Channel Estimation */
2239                 { 0x1f, 0x0001 },
2240                 { 0x06, 0x4064 },
2241                 { 0x07, 0x2863 },
2242                 { 0x08, 0x059c },
2243                 { 0x09, 0x26b4 },
2244                 { 0x0a, 0x6a19 },
2245                 { 0x0b, 0xdcc8 },
2246                 { 0x10, 0xf06d },
2247                 { 0x14, 0x7f68 },
2248                 { 0x18, 0x7fd9 },
2249                 { 0x1c, 0xf0ff },
2250                 { 0x1d, 0x3d9c },
2251                 { 0x1f, 0x0003 },
2252                 { 0x12, 0xf49f },
2253                 { 0x13, 0x070b },
2254                 { 0x1a, 0x05ad },
2255                 { 0x14, 0x94c0 },
2256
2257                 /*
2258                  * Tx Error Issue
2259                  * Enhance line driver power
2260                  */
2261                 { 0x1f, 0x0002 },
2262                 { 0x06, 0x5561 },
2263                 { 0x1f, 0x0005 },
2264                 { 0x05, 0x8332 },
2265                 { 0x06, 0x5561 },
2266
2267                 /*
2268                  * Can not link to 1Gbps with bad cable
2269                  * Decrease SNR threshold form 21.07dB to 19.04dB
2270                  */
2271                 { 0x1f, 0x0001 },
2272                 { 0x17, 0x0cc0 },
2273
2274                 { 0x1f, 0x0000 },
2275                 { 0x0d, 0xf880 }
2276         };
2277         void __iomem *ioaddr = tp->mmio_addr;
2278
2279         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2280
2281         /*
2282          * Rx Error Issue
2283          * Fine Tune Switching regulator parameter
2284          */
2285         rtl_writephy(tp, 0x1f, 0x0002);
2286         rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2287         rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2288
2289         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2290                 static const struct phy_reg phy_reg_init[] = {
2291                         { 0x1f, 0x0002 },
2292                         { 0x05, 0x669a },
2293                         { 0x1f, 0x0005 },
2294                         { 0x05, 0x8330 },
2295                         { 0x06, 0x669a },
2296                         { 0x1f, 0x0002 }
2297                 };
2298                 int val;
2299
2300                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2301
2302                 val = rtl_readphy(tp, 0x0d);
2303
2304                 if ((val & 0x00ff) != 0x006c) {
2305                         static const u32 set[] = {
2306                                 0x0065, 0x0066, 0x0067, 0x0068,
2307                                 0x0069, 0x006a, 0x006b, 0x006c
2308                         };
2309                         int i;
2310
2311                         rtl_writephy(tp, 0x1f, 0x0002);
2312
2313                         val &= 0xff00;
2314                         for (i = 0; i < ARRAY_SIZE(set); i++)
2315                                 rtl_writephy(tp, 0x0d, val | set[i]);
2316                 }
2317         } else {
2318                 static const struct phy_reg phy_reg_init[] = {
2319                         { 0x1f, 0x0002 },
2320                         { 0x05, 0x6662 },
2321                         { 0x1f, 0x0005 },
2322                         { 0x05, 0x8330 },
2323                         { 0x06, 0x6662 }
2324                 };
2325
2326                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2327         }
2328
2329         /* RSET couple improve */
2330         rtl_writephy(tp, 0x1f, 0x0002);
2331         rtl_patchphy(tp, 0x0d, 0x0300);
2332         rtl_patchphy(tp, 0x0f, 0x0010);
2333
2334         /* Fine tune PLL performance */
2335         rtl_writephy(tp, 0x1f, 0x0002);
2336         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2337         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2338
2339         rtl_writephy(tp, 0x1f, 0x0005);
2340         rtl_writephy(tp, 0x05, 0x001b);
2341
2342         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2343
2344         rtl_writephy(tp, 0x1f, 0x0000);
2345 }
2346
2347 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2348 {
2349         static const struct phy_reg phy_reg_init_0[] = {
2350                 /* Channel Estimation */
2351                 { 0x1f, 0x0001 },
2352                 { 0x06, 0x4064 },
2353                 { 0x07, 0x2863 },
2354                 { 0x08, 0x059c },
2355                 { 0x09, 0x26b4 },
2356                 { 0x0a, 0x6a19 },
2357                 { 0x0b, 0xdcc8 },
2358                 { 0x10, 0xf06d },
2359                 { 0x14, 0x7f68 },
2360                 { 0x18, 0x7fd9 },
2361                 { 0x1c, 0xf0ff },
2362                 { 0x1d, 0x3d9c },
2363                 { 0x1f, 0x0003 },
2364                 { 0x12, 0xf49f },
2365                 { 0x13, 0x070b },
2366                 { 0x1a, 0x05ad },
2367                 { 0x14, 0x94c0 },
2368
2369                 /*
2370                  * Tx Error Issue
2371                  * Enhance line driver power
2372                  */
2373                 { 0x1f, 0x0002 },
2374                 { 0x06, 0x5561 },
2375                 { 0x1f, 0x0005 },
2376                 { 0x05, 0x8332 },
2377                 { 0x06, 0x5561 },
2378
2379                 /*
2380                  * Can not link to 1Gbps with bad cable
2381                  * Decrease SNR threshold form 21.07dB to 19.04dB
2382                  */
2383                 { 0x1f, 0x0001 },
2384                 { 0x17, 0x0cc0 },
2385
2386                 { 0x1f, 0x0000 },
2387                 { 0x0d, 0xf880 }
2388         };
2389         void __iomem *ioaddr = tp->mmio_addr;
2390
2391         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2392
2393         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2394                 static const struct phy_reg phy_reg_init[] = {
2395                         { 0x1f, 0x0002 },
2396                         { 0x05, 0x669a },
2397                         { 0x1f, 0x0005 },
2398                         { 0x05, 0x8330 },
2399                         { 0x06, 0x669a },
2400
2401                         { 0x1f, 0x0002 }
2402                 };
2403                 int val;
2404
2405                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2406
2407                 val = rtl_readphy(tp, 0x0d);
2408                 if ((val & 0x00ff) != 0x006c) {
2409                         static const u32 set[] = {
2410                                 0x0065, 0x0066, 0x0067, 0x0068,
2411                                 0x0069, 0x006a, 0x006b, 0x006c
2412                         };
2413                         int i;
2414
2415                         rtl_writephy(tp, 0x1f, 0x0002);
2416
2417                         val &= 0xff00;
2418                         for (i = 0; i < ARRAY_SIZE(set); i++)
2419                                 rtl_writephy(tp, 0x0d, val | set[i]);
2420                 }
2421         } else {
2422                 static const struct phy_reg phy_reg_init[] = {
2423                         { 0x1f, 0x0002 },
2424                         { 0x05, 0x2642 },
2425                         { 0x1f, 0x0005 },
2426                         { 0x05, 0x8330 },
2427                         { 0x06, 0x2642 }
2428                 };
2429
2430                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2431         }
2432
2433         /* Fine tune PLL performance */
2434         rtl_writephy(tp, 0x1f, 0x0002);
2435         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2436         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2437
2438         /* Switching regulator Slew rate */
2439         rtl_writephy(tp, 0x1f, 0x0002);
2440         rtl_patchphy(tp, 0x0f, 0x0017);
2441
2442         rtl_writephy(tp, 0x1f, 0x0005);
2443         rtl_writephy(tp, 0x05, 0x001b);
2444
2445         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2446
2447         rtl_writephy(tp, 0x1f, 0x0000);
2448 }
2449
2450 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2451 {
2452         static const struct phy_reg phy_reg_init[] = {
2453                 { 0x1f, 0x0002 },
2454                 { 0x10, 0x0008 },
2455                 { 0x0d, 0x006c },
2456
2457                 { 0x1f, 0x0000 },
2458                 { 0x0d, 0xf880 },
2459
2460                 { 0x1f, 0x0001 },
2461                 { 0x17, 0x0cc0 },
2462
2463                 { 0x1f, 0x0001 },
2464                 { 0x0b, 0xa4d8 },
2465                 { 0x09, 0x281c },
2466                 { 0x07, 0x2883 },
2467                 { 0x0a, 0x6b35 },
2468                 { 0x1d, 0x3da4 },
2469                 { 0x1c, 0xeffd },
2470                 { 0x14, 0x7f52 },
2471                 { 0x18, 0x7fc6 },
2472                 { 0x08, 0x0601 },
2473                 { 0x06, 0x4063 },
2474                 { 0x10, 0xf074 },
2475                 { 0x1f, 0x0003 },
2476                 { 0x13, 0x0789 },
2477                 { 0x12, 0xf4bd },
2478                 { 0x1a, 0x04fd },
2479                 { 0x14, 0x84b0 },
2480                 { 0x1f, 0x0000 },
2481                 { 0x00, 0x9200 },
2482
2483                 { 0x1f, 0x0005 },
2484                 { 0x01, 0x0340 },
2485                 { 0x1f, 0x0001 },
2486                 { 0x04, 0x4000 },
2487                 { 0x03, 0x1d21 },
2488                 { 0x02, 0x0c32 },
2489                 { 0x01, 0x0200 },
2490                 { 0x00, 0x5554 },
2491                 { 0x04, 0x4800 },
2492                 { 0x04, 0x4000 },
2493                 { 0x04, 0xf000 },
2494                 { 0x03, 0xdf01 },
2495                 { 0x02, 0xdf20 },
2496                 { 0x01, 0x101a },
2497                 { 0x00, 0xa0ff },
2498                 { 0x04, 0xf800 },
2499                 { 0x04, 0xf000 },
2500                 { 0x1f, 0x0000 },
2501
2502                 { 0x1f, 0x0007 },
2503                 { 0x1e, 0x0023 },
2504                 { 0x16, 0x0000 },
2505                 { 0x1f, 0x0000 }
2506         };
2507
2508         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2509 }
2510
2511 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2512 {
2513         static const struct phy_reg phy_reg_init[] = {
2514                 { 0x1f, 0x0001 },
2515                 { 0x17, 0x0cc0 },
2516
2517                 { 0x1f, 0x0007 },
2518                 { 0x1e, 0x002d },
2519                 { 0x18, 0x0040 },
2520                 { 0x1f, 0x0000 }
2521         };
2522
2523         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2524         rtl_patchphy(tp, 0x0d, 1 << 5);
2525 }
2526
2527 static void rtl8168e_hw_phy_config(struct rtl8169_private *tp)
2528 {
2529         static const struct phy_reg phy_reg_init[] = {
2530                 /* Enable Delay cap */
2531                 { 0x1f, 0x0005 },
2532                 { 0x05, 0x8b80 },
2533                 { 0x06, 0xc896 },
2534                 { 0x1f, 0x0000 },
2535
2536                 /* Channel estimation fine tune */
2537                 { 0x1f, 0x0001 },
2538                 { 0x0b, 0x6c20 },
2539                 { 0x07, 0x2872 },
2540                 { 0x1c, 0xefff },
2541                 { 0x1f, 0x0003 },
2542                 { 0x14, 0x6420 },
2543                 { 0x1f, 0x0000 },
2544
2545                 /* Update PFM & 10M TX idle timer */
2546                 { 0x1f, 0x0007 },
2547                 { 0x1e, 0x002f },
2548                 { 0x15, 0x1919 },
2549                 { 0x1f, 0x0000 },
2550
2551                 { 0x1f, 0x0007 },
2552                 { 0x1e, 0x00ac },
2553                 { 0x18, 0x0006 },
2554                 { 0x1f, 0x0000 }
2555         };
2556
2557         rtl_apply_firmware(tp);
2558
2559         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2560
2561         /* DCO enable for 10M IDLE Power */
2562         rtl_writephy(tp, 0x1f, 0x0007);
2563         rtl_writephy(tp, 0x1e, 0x0023);
2564         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2565         rtl_writephy(tp, 0x1f, 0x0000);
2566
2567         /* For impedance matching */
2568         rtl_writephy(tp, 0x1f, 0x0002);
2569         rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
2570         rtl_writephy(tp, 0x1f, 0x0000);
2571
2572         /* PHY auto speed down */
2573         rtl_writephy(tp, 0x1f, 0x0007);
2574         rtl_writephy(tp, 0x1e, 0x002d);
2575         rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2576         rtl_writephy(tp, 0x1f, 0x0000);
2577         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2578
2579         rtl_writephy(tp, 0x1f, 0x0005);
2580         rtl_writephy(tp, 0x05, 0x8b86);
2581         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2582         rtl_writephy(tp, 0x1f, 0x0000);
2583
2584         rtl_writephy(tp, 0x1f, 0x0005);
2585         rtl_writephy(tp, 0x05, 0x8b85);
2586         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2587         rtl_writephy(tp, 0x1f, 0x0007);
2588         rtl_writephy(tp, 0x1e, 0x0020);
2589         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2590         rtl_writephy(tp, 0x1f, 0x0006);
2591         rtl_writephy(tp, 0x00, 0x5a00);
2592         rtl_writephy(tp, 0x1f, 0x0000);
2593         rtl_writephy(tp, 0x0d, 0x0007);
2594         rtl_writephy(tp, 0x0e, 0x003c);
2595         rtl_writephy(tp, 0x0d, 0x4007);
2596         rtl_writephy(tp, 0x0e, 0x0000);
2597         rtl_writephy(tp, 0x0d, 0x0000);
2598 }
2599
2600 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2601 {
2602         static const struct phy_reg phy_reg_init[] = {
2603                 { 0x1f, 0x0003 },
2604                 { 0x08, 0x441d },
2605                 { 0x01, 0x9100 },
2606                 { 0x1f, 0x0000 }
2607         };
2608
2609         rtl_writephy(tp, 0x1f, 0x0000);
2610         rtl_patchphy(tp, 0x11, 1 << 12);
2611         rtl_patchphy(tp, 0x19, 1 << 13);
2612         rtl_patchphy(tp, 0x10, 1 << 15);
2613
2614         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2615 }
2616
2617 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
2618 {
2619         static const struct phy_reg phy_reg_init[] = {
2620                 { 0x1f, 0x0005 },
2621                 { 0x1a, 0x0000 },
2622                 { 0x1f, 0x0000 },
2623
2624                 { 0x1f, 0x0004 },
2625                 { 0x1c, 0x0000 },
2626                 { 0x1f, 0x0000 },
2627
2628                 { 0x1f, 0x0001 },
2629                 { 0x15, 0x7701 },
2630                 { 0x1f, 0x0000 }
2631         };
2632
2633         /* Disable ALDPS before ram code */
2634         rtl_writephy(tp, 0x1f, 0x0000);
2635         rtl_writephy(tp, 0x18, 0x0310);
2636         msleep(100);
2637
2638         rtl_apply_firmware(tp);
2639
2640         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2641 }
2642
2643 static void rtl_hw_phy_config(struct net_device *dev)
2644 {
2645         struct rtl8169_private *tp = netdev_priv(dev);
2646
2647         rtl8169_print_mac_version(tp);
2648
2649         switch (tp->mac_version) {
2650         case RTL_GIGA_MAC_VER_01:
2651                 break;
2652         case RTL_GIGA_MAC_VER_02:
2653         case RTL_GIGA_MAC_VER_03:
2654                 rtl8169s_hw_phy_config(tp);
2655                 break;
2656         case RTL_GIGA_MAC_VER_04:
2657                 rtl8169sb_hw_phy_config(tp);
2658                 break;
2659         case RTL_GIGA_MAC_VER_05:
2660                 rtl8169scd_hw_phy_config(tp);
2661                 break;
2662         case RTL_GIGA_MAC_VER_06:
2663                 rtl8169sce_hw_phy_config(tp);
2664                 break;
2665         case RTL_GIGA_MAC_VER_07:
2666         case RTL_GIGA_MAC_VER_08:
2667         case RTL_GIGA_MAC_VER_09:
2668                 rtl8102e_hw_phy_config(tp);
2669                 break;
2670         case RTL_GIGA_MAC_VER_11:
2671                 rtl8168bb_hw_phy_config(tp);
2672                 break;
2673         case RTL_GIGA_MAC_VER_12:
2674                 rtl8168bef_hw_phy_config(tp);
2675                 break;
2676         case RTL_GIGA_MAC_VER_17:
2677                 rtl8168bef_hw_phy_config(tp);
2678                 break;
2679         case RTL_GIGA_MAC_VER_18:
2680                 rtl8168cp_1_hw_phy_config(tp);
2681                 break;
2682         case RTL_GIGA_MAC_VER_19:
2683                 rtl8168c_1_hw_phy_config(tp);
2684                 break;
2685         case RTL_GIGA_MAC_VER_20:
2686                 rtl8168c_2_hw_phy_config(tp);
2687                 break;
2688         case RTL_GIGA_MAC_VER_21:
2689                 rtl8168c_3_hw_phy_config(tp);
2690                 break;
2691         case RTL_GIGA_MAC_VER_22:
2692                 rtl8168c_4_hw_phy_config(tp);
2693                 break;
2694         case RTL_GIGA_MAC_VER_23:
2695         case RTL_GIGA_MAC_VER_24:
2696                 rtl8168cp_2_hw_phy_config(tp);
2697                 break;
2698         case RTL_GIGA_MAC_VER_25:
2699                 rtl8168d_1_hw_phy_config(tp);
2700                 break;
2701         case RTL_GIGA_MAC_VER_26:
2702                 rtl8168d_2_hw_phy_config(tp);
2703                 break;
2704         case RTL_GIGA_MAC_VER_27:
2705                 rtl8168d_3_hw_phy_config(tp);
2706                 break;
2707         case RTL_GIGA_MAC_VER_28:
2708                 rtl8168d_4_hw_phy_config(tp);
2709                 break;
2710         case RTL_GIGA_MAC_VER_29:
2711         case RTL_GIGA_MAC_VER_30:
2712                 rtl8105e_hw_phy_config(tp);
2713                 break;
2714         case RTL_GIGA_MAC_VER_31:
2715                 /* None. */
2716                 break;
2717         case RTL_GIGA_MAC_VER_32:
2718         case RTL_GIGA_MAC_VER_33:
2719                 rtl8168e_hw_phy_config(tp);
2720                 break;
2721
2722         default:
2723                 break;
2724         }
2725 }
2726
2727 static void rtl8169_phy_timer(unsigned long __opaque)
2728 {
2729         struct net_device *dev = (struct net_device *)__opaque;
2730         struct rtl8169_private *tp = netdev_priv(dev);
2731         struct timer_list *timer = &tp->timer;
2732         void __iomem *ioaddr = tp->mmio_addr;
2733         unsigned long timeout = RTL8169_PHY_TIMEOUT;
2734
2735         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
2736
2737         spin_lock_irq(&tp->lock);
2738
2739         if (tp->phy_reset_pending(tp)) {
2740                 /*
2741                  * A busy loop could burn quite a few cycles on nowadays CPU.
2742                  * Let's delay the execution of the timer for a few ticks.
2743                  */
2744                 timeout = HZ/10;
2745                 goto out_mod_timer;
2746         }
2747
2748         if (tp->link_ok(ioaddr))
2749                 goto out_unlock;
2750
2751         netif_warn(tp, link, dev, "PHY reset until link up\n");
2752
2753         tp->phy_reset_enable(tp);
2754
2755 out_mod_timer:
2756         mod_timer(timer, jiffies + timeout);
2757 out_unlock:
2758         spin_unlock_irq(&tp->lock);
2759 }
2760
2761 #ifdef CONFIG_NET_POLL_CONTROLLER
2762 /*
2763  * Polling 'interrupt' - used by things like netconsole to send skbs
2764  * without having to re-enable interrupts. It's not called while
2765  * the interrupt routine is executing.
2766  */
2767 static void rtl8169_netpoll(struct net_device *dev)
2768 {
2769         struct rtl8169_private *tp = netdev_priv(dev);
2770         struct pci_dev *pdev = tp->pci_dev;
2771
2772         disable_irq(pdev->irq);
2773         rtl8169_interrupt(pdev->irq, dev);
2774         enable_irq(pdev->irq);
2775 }
2776 #endif
2777
2778 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
2779                                   void __iomem *ioaddr)
2780 {
2781         iounmap(ioaddr);
2782         pci_release_regions(pdev);
2783         pci_clear_mwi(pdev);
2784         pci_disable_device(pdev);
2785         free_netdev(dev);
2786 }
2787
2788 static void rtl8169_phy_reset(struct net_device *dev,
2789                               struct rtl8169_private *tp)
2790 {
2791         unsigned int i;
2792
2793         tp->phy_reset_enable(tp);
2794         for (i = 0; i < 100; i++) {
2795                 if (!tp->phy_reset_pending(tp))
2796                         return;
2797                 msleep(1);
2798         }
2799         netif_err(tp, link, dev, "PHY reset failed\n");
2800 }
2801
2802 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
2803 {
2804         void __iomem *ioaddr = tp->mmio_addr;
2805
2806         rtl_hw_phy_config(dev);
2807
2808         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2809                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2810                 RTL_W8(0x82, 0x01);
2811         }
2812
2813         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2814
2815         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
2816                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
2817
2818         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
2819                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2820                 RTL_W8(0x82, 0x01);
2821                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
2822                 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
2823         }
2824
2825         rtl8169_phy_reset(dev, tp);
2826
2827         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
2828                           ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
2829                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
2830                           (tp->mii.supports_gmii ?
2831                            ADVERTISED_1000baseT_Half |
2832                            ADVERTISED_1000baseT_Full : 0));
2833
2834         if (RTL_R8(PHYstatus) & TBI_Enable)
2835                 netif_info(tp, link, dev, "TBI auto-negotiating\n");
2836 }
2837
2838 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2839 {
2840         void __iomem *ioaddr = tp->mmio_addr;
2841         u32 high;
2842         u32 low;
2843
2844         low  = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
2845         high = addr[4] | (addr[5] << 8);
2846
2847         spin_lock_irq(&tp->lock);
2848
2849         RTL_W8(Cfg9346, Cfg9346_Unlock);
2850
2851         RTL_W32(MAC4, high);
2852         RTL_R32(MAC4);
2853
2854         RTL_W32(MAC0, low);
2855         RTL_R32(MAC0);
2856
2857         RTL_W8(Cfg9346, Cfg9346_Lock);
2858
2859         spin_unlock_irq(&tp->lock);
2860 }
2861
2862 static int rtl_set_mac_address(struct net_device *dev, void *p)
2863 {
2864         struct rtl8169_private *tp = netdev_priv(dev);
2865         struct sockaddr *addr = p;
2866
2867         if (!is_valid_ether_addr(addr->sa_data))
2868                 return -EADDRNOTAVAIL;
2869
2870         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2871
2872         rtl_rar_set(tp, dev->dev_addr);
2873
2874         return 0;
2875 }
2876
2877 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2878 {
2879         struct rtl8169_private *tp = netdev_priv(dev);
2880         struct mii_ioctl_data *data = if_mii(ifr);
2881
2882         return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
2883 }
2884
2885 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
2886                           struct mii_ioctl_data *data, int cmd)
2887 {
2888         switch (cmd) {
2889         case SIOCGMIIPHY:
2890                 data->phy_id = 32; /* Internal PHY */
2891                 return 0;
2892
2893         case SIOCGMIIREG:
2894                 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
2895                 return 0;
2896
2897         case SIOCSMIIREG:
2898                 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
2899                 return 0;
2900         }
2901         return -EOPNOTSUPP;
2902 }
2903
2904 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2905 {
2906         return -EOPNOTSUPP;
2907 }
2908
2909 static const struct rtl_cfg_info {
2910         void (*hw_start)(struct net_device *);
2911         unsigned int region;
2912         unsigned int align;
2913         u16 intr_event;
2914         u16 napi_event;
2915         unsigned features;
2916         u8 default_ver;
2917 } rtl_cfg_infos [] = {
2918         [RTL_CFG_0] = {
2919                 .hw_start       = rtl_hw_start_8169,
2920                 .region         = 1,
2921                 .align          = 0,
2922                 .intr_event     = SYSErr | LinkChg | RxOverflow |
2923                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2924                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2925                 .features       = RTL_FEATURE_GMII,
2926                 .default_ver    = RTL_GIGA_MAC_VER_01,
2927         },
2928         [RTL_CFG_1] = {
2929                 .hw_start       = rtl_hw_start_8168,
2930                 .region         = 2,
2931                 .align          = 8,
2932                 .intr_event     = SYSErr | LinkChg | RxOverflow |
2933                                   TxErr | TxOK | RxOK | RxErr,
2934                 .napi_event     = TxErr | TxOK | RxOK | RxOverflow,
2935                 .features       = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
2936                 .default_ver    = RTL_GIGA_MAC_VER_11,
2937         },
2938         [RTL_CFG_2] = {
2939                 .hw_start       = rtl_hw_start_8101,
2940                 .region         = 2,
2941                 .align          = 8,
2942                 .intr_event     = SYSErr | LinkChg | RxOverflow | PCSTimeout |
2943                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2944                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2945                 .features       = RTL_FEATURE_MSI,
2946                 .default_ver    = RTL_GIGA_MAC_VER_13,
2947         }
2948 };
2949
2950 /* Cfg9346_Unlock assumed. */
2951 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
2952                             const struct rtl_cfg_info *cfg)
2953 {
2954         unsigned msi = 0;
2955         u8 cfg2;
2956
2957         cfg2 = RTL_R8(Config2) & ~MSIEnable;
2958         if (cfg->features & RTL_FEATURE_MSI) {
2959                 if (pci_enable_msi(pdev)) {
2960                         dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
2961                 } else {
2962                         cfg2 |= MSIEnable;
2963                         msi = RTL_FEATURE_MSI;
2964                 }
2965         }
2966         RTL_W8(Config2, cfg2);
2967         return msi;
2968 }
2969
2970 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
2971 {
2972         if (tp->features & RTL_FEATURE_MSI) {
2973                 pci_disable_msi(pdev);
2974                 tp->features &= ~RTL_FEATURE_MSI;
2975         }
2976 }
2977
2978 static const struct net_device_ops rtl8169_netdev_ops = {
2979         .ndo_open               = rtl8169_open,
2980         .ndo_stop               = rtl8169_close,
2981         .ndo_get_stats          = rtl8169_get_stats,
2982         .ndo_start_xmit         = rtl8169_start_xmit,
2983         .ndo_tx_timeout         = rtl8169_tx_timeout,
2984         .ndo_validate_addr      = eth_validate_addr,
2985         .ndo_change_mtu         = rtl8169_change_mtu,
2986         .ndo_fix_features       = rtl8169_fix_features,
2987         .ndo_set_features       = rtl8169_set_features,
2988         .ndo_set_mac_address    = rtl_set_mac_address,
2989         .ndo_do_ioctl           = rtl8169_ioctl,
2990         .ndo_set_multicast_list = rtl_set_rx_mode,
2991 #ifdef CONFIG_NET_POLL_CONTROLLER
2992         .ndo_poll_controller    = rtl8169_netpoll,
2993 #endif
2994
2995 };
2996
2997 static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
2998 {
2999         struct mdio_ops *ops = &tp->mdio_ops;
3000
3001         switch (tp->mac_version) {
3002         case RTL_GIGA_MAC_VER_27:
3003                 ops->write      = r8168dp_1_mdio_write;
3004                 ops->read       = r8168dp_1_mdio_read;
3005                 break;
3006         case RTL_GIGA_MAC_VER_28:
3007         case RTL_GIGA_MAC_VER_31:
3008                 ops->write      = r8168dp_2_mdio_write;
3009                 ops->read       = r8168dp_2_mdio_read;
3010                 break;
3011         default:
3012                 ops->write      = r8169_mdio_write;
3013                 ops->read       = r8169_mdio_read;
3014                 break;
3015         }
3016 }
3017
3018 static void r810x_phy_power_down(struct rtl8169_private *tp)
3019 {
3020         rtl_writephy(tp, 0x1f, 0x0000);
3021         rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3022 }
3023
3024 static void r810x_phy_power_up(struct rtl8169_private *tp)
3025 {
3026         rtl_writephy(tp, 0x1f, 0x0000);
3027         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3028 }
3029
3030 static void r810x_pll_power_down(struct rtl8169_private *tp)
3031 {
3032         if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3033                 rtl_writephy(tp, 0x1f, 0x0000);
3034                 rtl_writephy(tp, MII_BMCR, 0x0000);
3035                 return;
3036         }
3037
3038         r810x_phy_power_down(tp);
3039 }
3040
3041 static void r810x_pll_power_up(struct rtl8169_private *tp)
3042 {
3043         r810x_phy_power_up(tp);
3044 }
3045
3046 static void r8168_phy_power_up(struct rtl8169_private *tp)
3047 {
3048         rtl_writephy(tp, 0x1f, 0x0000);
3049         switch (tp->mac_version) {
3050         case RTL_GIGA_MAC_VER_11:
3051         case RTL_GIGA_MAC_VER_12:
3052         case RTL_GIGA_MAC_VER_17:
3053         case RTL_GIGA_MAC_VER_18:
3054         case RTL_GIGA_MAC_VER_19:
3055         case RTL_GIGA_MAC_VER_20:
3056         case RTL_GIGA_MAC_VER_21:
3057         case RTL_GIGA_MAC_VER_22:
3058         case RTL_GIGA_MAC_VER_23:
3059         case RTL_GIGA_MAC_VER_24:
3060         case RTL_GIGA_MAC_VER_25:
3061         case RTL_GIGA_MAC_VER_26:
3062         case RTL_GIGA_MAC_VER_27:
3063         case RTL_GIGA_MAC_VER_28:
3064         case RTL_GIGA_MAC_VER_31:
3065                 rtl_writephy(tp, 0x0e, 0x0000);
3066                 break;
3067         default:
3068                 break;
3069         }
3070         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3071 }
3072
3073 static void r8168_phy_power_down(struct rtl8169_private *tp)
3074 {
3075         rtl_writephy(tp, 0x1f, 0x0000);
3076         switch (tp->mac_version) {
3077         case RTL_GIGA_MAC_VER_32:
3078         case RTL_GIGA_MAC_VER_33:
3079                 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3080                 break;
3081
3082         case RTL_GIGA_MAC_VER_11:
3083         case RTL_GIGA_MAC_VER_12:
3084         case RTL_GIGA_MAC_VER_17:
3085         case RTL_GIGA_MAC_VER_18:
3086         case RTL_GIGA_MAC_VER_19:
3087         case RTL_GIGA_MAC_VER_20:
3088         case RTL_GIGA_MAC_VER_21:
3089         case RTL_GIGA_MAC_VER_22:
3090         case RTL_GIGA_MAC_VER_23:
3091         case RTL_GIGA_MAC_VER_24:
3092         case RTL_GIGA_MAC_VER_25:
3093         case RTL_GIGA_MAC_VER_26:
3094         case RTL_GIGA_MAC_VER_27:
3095         case RTL_GIGA_MAC_VER_28:
3096         case RTL_GIGA_MAC_VER_31:
3097                 rtl_writephy(tp, 0x0e, 0x0200);
3098         default:
3099                 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3100                 break;
3101         }
3102 }
3103
3104 static void r8168_pll_power_down(struct rtl8169_private *tp)
3105 {
3106         void __iomem *ioaddr = tp->mmio_addr;
3107
3108         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3109              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3110              tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3111             r8168dp_check_dash(tp)) {
3112                 return;
3113         }
3114
3115         if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
3116              tp->mac_version == RTL_GIGA_MAC_VER_24) &&
3117             (RTL_R16(CPlusCmd) & ASF)) {
3118                 return;
3119         }
3120
3121         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3122             tp->mac_version == RTL_GIGA_MAC_VER_33)
3123                 rtl_ephy_write(ioaddr, 0x19, 0xff64);
3124
3125         if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3126                 rtl_writephy(tp, 0x1f, 0x0000);
3127                 rtl_writephy(tp, MII_BMCR, 0x0000);
3128
3129                 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3130                     tp->mac_version == RTL_GIGA_MAC_VER_33)
3131                         RTL_W32(RxConfig, RTL_R32(RxConfig) | AcceptBroadcast |
3132                                 AcceptMulticast | AcceptMyPhys);
3133                 return;
3134         }
3135
3136         r8168_phy_power_down(tp);
3137
3138         switch (tp->mac_version) {
3139         case RTL_GIGA_MAC_VER_25:
3140         case RTL_GIGA_MAC_VER_26:
3141         case RTL_GIGA_MAC_VER_27:
3142         case RTL_GIGA_MAC_VER_28:
3143         case RTL_GIGA_MAC_VER_31:
3144         case RTL_GIGA_MAC_VER_32:
3145         case RTL_GIGA_MAC_VER_33:
3146                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3147                 break;
3148         }
3149 }
3150
3151 static void r8168_pll_power_up(struct rtl8169_private *tp)
3152 {
3153         void __iomem *ioaddr = tp->mmio_addr;
3154
3155         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3156              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3157              tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3158             r8168dp_check_dash(tp)) {
3159                 return;
3160         }
3161
3162         switch (tp->mac_version) {
3163         case RTL_GIGA_MAC_VER_25:
3164         case RTL_GIGA_MAC_VER_26:
3165         case RTL_GIGA_MAC_VER_27:
3166         case RTL_GIGA_MAC_VER_28:
3167         case RTL_GIGA_MAC_VER_31:
3168         case RTL_GIGA_MAC_VER_32:
3169         case RTL_GIGA_MAC_VER_33:
3170                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3171                 break;
3172         }
3173
3174         r8168_phy_power_up(tp);
3175 }
3176
3177 static void rtl_pll_power_op(struct rtl8169_private *tp,
3178                              void (*op)(struct rtl8169_private *))
3179 {
3180         if (op)
3181                 op(tp);
3182 }
3183
3184 static void rtl_pll_power_down(struct rtl8169_private *tp)
3185 {
3186         rtl_pll_power_op(tp, tp->pll_power_ops.down);
3187 }
3188
3189 static void rtl_pll_power_up(struct rtl8169_private *tp)
3190 {
3191         rtl_pll_power_op(tp, tp->pll_power_ops.up);
3192 }
3193
3194 static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3195 {
3196         struct pll_power_ops *ops = &tp->pll_power_ops;
3197
3198         switch (tp->mac_version) {
3199         case RTL_GIGA_MAC_VER_07:
3200         case RTL_GIGA_MAC_VER_08:
3201         case RTL_GIGA_MAC_VER_09:
3202         case RTL_GIGA_MAC_VER_10:
3203         case RTL_GIGA_MAC_VER_16:
3204         case RTL_GIGA_MAC_VER_29:
3205         case RTL_GIGA_MAC_VER_30:
3206                 ops->down       = r810x_pll_power_down;
3207                 ops->up         = r810x_pll_power_up;
3208                 break;
3209
3210         case RTL_GIGA_MAC_VER_11:
3211         case RTL_GIGA_MAC_VER_12:
3212         case RTL_GIGA_MAC_VER_17:
3213         case RTL_GIGA_MAC_VER_18:
3214         case RTL_GIGA_MAC_VER_19:
3215         case RTL_GIGA_MAC_VER_20:
3216         case RTL_GIGA_MAC_VER_21:
3217         case RTL_GIGA_MAC_VER_22:
3218         case RTL_GIGA_MAC_VER_23:
3219         case RTL_GIGA_MAC_VER_24:
3220         case RTL_GIGA_MAC_VER_25:
3221         case RTL_GIGA_MAC_VER_26:
3222         case RTL_GIGA_MAC_VER_27:
3223         case RTL_GIGA_MAC_VER_28:
3224         case RTL_GIGA_MAC_VER_31:
3225         case RTL_GIGA_MAC_VER_32:
3226         case RTL_GIGA_MAC_VER_33:
3227                 ops->down       = r8168_pll_power_down;
3228                 ops->up         = r8168_pll_power_up;
3229                 break;
3230
3231         default:
3232                 ops->down       = NULL;
3233                 ops->up         = NULL;
3234                 break;
3235         }
3236 }
3237
3238 static void rtl_hw_reset(struct rtl8169_private *tp)
3239 {
3240         void __iomem *ioaddr = tp->mmio_addr;
3241         int i;
3242
3243         /* Soft reset the chip. */
3244         RTL_W8(ChipCmd, CmdReset);
3245
3246         /* Check that the chip has finished the reset. */
3247         for (i = 0; i < 100; i++) {
3248                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3249                         break;
3250                 msleep_interruptible(1);
3251         }
3252 }
3253
3254 static int __devinit
3255 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3256 {
3257         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
3258         const unsigned int region = cfg->region;
3259         struct rtl8169_private *tp;
3260         struct mii_if_info *mii;
3261         struct net_device *dev;
3262         void __iomem *ioaddr;
3263         int chipset, i;
3264         int rc;
3265
3266         if (netif_msg_drv(&debug)) {
3267                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
3268                        MODULENAME, RTL8169_VERSION);
3269         }
3270
3271         dev = alloc_etherdev(sizeof (*tp));
3272         if (!dev) {
3273                 if (netif_msg_drv(&debug))
3274                         dev_err(&pdev->dev, "unable to alloc new ethernet\n");
3275                 rc = -ENOMEM;
3276                 goto out;
3277         }
3278
3279         SET_NETDEV_DEV(dev, &pdev->dev);
3280         dev->netdev_ops = &rtl8169_netdev_ops;
3281         tp = netdev_priv(dev);
3282         tp->dev = dev;
3283         tp->pci_dev = pdev;
3284         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
3285
3286         mii = &tp->mii;
3287         mii->dev = dev;
3288         mii->mdio_read = rtl_mdio_read;
3289         mii->mdio_write = rtl_mdio_write;
3290         mii->phy_id_mask = 0x1f;
3291         mii->reg_num_mask = 0x1f;
3292         mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3293
3294         /* disable ASPM completely as that cause random device stop working
3295          * problems as well as full system hangs for some PCIe devices users */
3296         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3297                                      PCIE_LINK_STATE_CLKPM);
3298
3299         /* enable device (incl. PCI PM wakeup and hotplug setup) */
3300         rc = pci_enable_device(pdev);
3301         if (rc < 0) {
3302                 netif_err(tp, probe, dev, "enable failure\n");
3303                 goto err_out_free_dev_1;
3304         }
3305
3306         if (pci_set_mwi(pdev) < 0)
3307                 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
3308
3309         /* make sure PCI base addr 1 is MMIO */
3310         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
3311                 netif_err(tp, probe, dev,
3312                           "region #%d not an MMIO resource, aborting\n",
3313                           region);
3314                 rc = -ENODEV;
3315                 goto err_out_mwi_2;
3316         }
3317
3318         /* check for weird/broken PCI region reporting */
3319         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
3320                 netif_err(tp, probe, dev,
3321                           "Invalid PCI region size(s), aborting\n");
3322                 rc = -ENODEV;
3323                 goto err_out_mwi_2;
3324         }
3325
3326         rc = pci_request_regions(pdev, MODULENAME);
3327         if (rc < 0) {
3328                 netif_err(tp, probe, dev, "could not request regions\n");
3329                 goto err_out_mwi_2;
3330         }
3331
3332         tp->cp_cmd = RxChkSum;
3333
3334         if ((sizeof(dma_addr_t) > 4) &&
3335             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
3336                 tp->cp_cmd |= PCIDAC;
3337                 dev->features |= NETIF_F_HIGHDMA;
3338         } else {
3339                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3340                 if (rc < 0) {
3341                         netif_err(tp, probe, dev, "DMA configuration failed\n");
3342                         goto err_out_free_res_3;
3343                 }
3344         }
3345
3346         /* ioremap MMIO region */
3347         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
3348         if (!ioaddr) {
3349                 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
3350                 rc = -EIO;
3351                 goto err_out_free_res_3;
3352         }
3353         tp->mmio_addr = ioaddr;
3354
3355         tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3356         if (!tp->pcie_cap)
3357                 netif_info(tp, probe, dev, "no PCI Express capability\n");
3358
3359         RTL_W16(IntrMask, 0x0000);
3360
3361         rtl_hw_reset(tp);
3362
3363         RTL_W16(IntrStatus, 0xffff);
3364
3365         pci_set_master(pdev);
3366
3367         /* Identify chip attached to board */
3368         rtl8169_get_mac_version(tp, dev, cfg->default_ver);
3369
3370         /*
3371          * Pretend we are using VLANs; This bypasses a nasty bug where
3372          * Interrupts stop flowing on high load on 8110SCd controllers.
3373          */
3374         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3375                 tp->cp_cmd |= RxVlan;
3376
3377         rtl_init_mdio_ops(tp);
3378         rtl_init_pll_power_ops(tp);
3379
3380         rtl8169_print_mac_version(tp);
3381
3382         chipset = tp->mac_version;
3383         tp->txd_version = rtl_chip_infos[chipset].txd_version;
3384
3385         RTL_W8(Cfg9346, Cfg9346_Unlock);
3386         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3387         RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
3388         if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3389                 tp->features |= RTL_FEATURE_WOL;
3390         if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3391                 tp->features |= RTL_FEATURE_WOL;
3392         tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
3393         RTL_W8(Cfg9346, Cfg9346_Lock);
3394
3395         if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3396             (RTL_R8(PHYstatus) & TBI_Enable)) {
3397                 tp->set_speed = rtl8169_set_speed_tbi;
3398                 tp->get_settings = rtl8169_gset_tbi;
3399                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3400                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3401                 tp->link_ok = rtl8169_tbi_link_ok;
3402                 tp->do_ioctl = rtl_tbi_ioctl;
3403         } else {
3404                 tp->set_speed = rtl8169_set_speed_xmii;
3405                 tp->get_settings = rtl8169_gset_xmii;
3406                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3407                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3408                 tp->link_ok = rtl8169_xmii_link_ok;
3409                 tp->do_ioctl = rtl_xmii_ioctl;
3410         }
3411
3412         spin_lock_init(&tp->lock);
3413
3414         /* Get MAC address */
3415         for (i = 0; i < MAC_ADDR_LEN; i++)
3416                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
3417         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3418
3419         SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
3420         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3421         dev->irq = pdev->irq;
3422         dev->base_addr = (unsigned long) ioaddr;
3423
3424         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
3425
3426         /* don't enable SG, IP_CSUM and TSO by default - it might not work
3427          * properly for all devices */
3428         dev->features |= NETIF_F_RXCSUM |
3429                 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3430
3431         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3432                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3433         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3434                 NETIF_F_HIGHDMA;
3435
3436         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3437                 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
3438                 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
3439
3440         tp->intr_mask = 0xffff;
3441         tp->hw_start = cfg->hw_start;
3442         tp->intr_event = cfg->intr_event;
3443         tp->napi_event = cfg->napi_event;
3444
3445         init_timer(&tp->timer);
3446         tp->timer.data = (unsigned long) dev;
3447         tp->timer.function = rtl8169_phy_timer;
3448
3449         tp->fw = RTL_FIRMWARE_UNKNOWN;
3450
3451         rc = register_netdev(dev);
3452         if (rc < 0)
3453                 goto err_out_msi_4;
3454
3455         pci_set_drvdata(pdev, dev);
3456
3457         netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
3458                    rtl_chip_infos[chipset].name, dev->base_addr, dev->dev_addr,
3459                    (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
3460
3461         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3462             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3463             tp->mac_version == RTL_GIGA_MAC_VER_31) {
3464                 rtl8168_driver_start(tp);
3465         }
3466
3467         device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
3468
3469         if (pci_dev_run_wake(pdev))
3470                 pm_runtime_put_noidle(&pdev->dev);
3471
3472         netif_carrier_off(dev);
3473
3474 out:
3475         return rc;
3476
3477 err_out_msi_4:
3478         rtl_disable_msi(pdev, tp);
3479         iounmap(ioaddr);
3480 err_out_free_res_3:
3481         pci_release_regions(pdev);
3482 err_out_mwi_2:
3483         pci_clear_mwi(pdev);
3484         pci_disable_device(pdev);
3485 err_out_free_dev_1:
3486         free_netdev(dev);
3487         goto out;
3488 }
3489
3490 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
3491 {
3492         struct net_device *dev = pci_get_drvdata(pdev);
3493         struct rtl8169_private *tp = netdev_priv(dev);
3494
3495         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3496             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3497             tp->mac_version == RTL_GIGA_MAC_VER_31) {
3498                 rtl8168_driver_stop(tp);
3499         }
3500
3501         cancel_delayed_work_sync(&tp->task);
3502
3503         unregister_netdev(dev);
3504
3505         rtl_release_firmware(tp);
3506
3507         if (pci_dev_run_wake(pdev))
3508                 pm_runtime_get_noresume(&pdev->dev);
3509
3510         /* restore original MAC address */
3511         rtl_rar_set(tp, dev->perm_addr);
3512
3513         rtl_disable_msi(pdev, tp);
3514         rtl8169_release_board(pdev, dev, tp->mmio_addr);
3515         pci_set_drvdata(pdev, NULL);
3516 }
3517
3518 static void rtl_request_firmware(struct rtl8169_private *tp)
3519 {
3520         /* Return early if the firmware is already loaded / cached. */
3521         if (IS_ERR(tp->fw)) {
3522                 const char *name;
3523
3524                 name = rtl_lookup_firmware_name(tp);
3525                 if (name) {
3526                         int rc;
3527
3528                         rc = request_firmware(&tp->fw, name, &tp->pci_dev->dev);
3529                         if (rc >= 0)
3530                                 return;
3531
3532                         netif_warn(tp, ifup, tp->dev, "unable to load "
3533                                 "firmware patch %s (%d)\n", name, rc);
3534                 }
3535                 tp->fw = NULL;
3536         }
3537 }
3538
3539 static int rtl8169_open(struct net_device *dev)
3540 {
3541         struct rtl8169_private *tp = netdev_priv(dev);
3542         void __iomem *ioaddr = tp->mmio_addr;
3543         struct pci_dev *pdev = tp->pci_dev;
3544         int retval = -ENOMEM;
3545
3546         pm_runtime_get_sync(&pdev->dev);
3547
3548         /*
3549          * Rx and Tx desscriptors needs 256 bytes alignment.
3550          * dma_alloc_coherent provides more.
3551          */
3552         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
3553                                              &tp->TxPhyAddr, GFP_KERNEL);
3554         if (!tp->TxDescArray)
3555                 goto err_pm_runtime_put;
3556
3557         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
3558                                              &tp->RxPhyAddr, GFP_KERNEL);
3559         if (!tp->RxDescArray)
3560                 goto err_free_tx_0;
3561
3562         retval = rtl8169_init_ring(dev);
3563         if (retval < 0)
3564                 goto err_free_rx_1;
3565
3566         INIT_DELAYED_WORK(&tp->task, NULL);
3567
3568         smp_mb();
3569
3570         rtl_request_firmware(tp);
3571
3572         retval = request_irq(dev->irq, rtl8169_interrupt,
3573                              (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
3574                              dev->name, dev);
3575         if (retval < 0)
3576                 goto err_release_fw_2;
3577
3578         napi_enable(&tp->napi);
3579
3580         rtl8169_init_phy(dev, tp);
3581
3582         rtl8169_set_features(dev, dev->features);
3583
3584         rtl_pll_power_up(tp);
3585
3586         rtl_hw_start(dev);
3587
3588         tp->saved_wolopts = 0;
3589         pm_runtime_put_noidle(&pdev->dev);
3590
3591         rtl8169_check_link_status(dev, tp, ioaddr);
3592 out:
3593         return retval;
3594
3595 err_release_fw_2:
3596         rtl_release_firmware(tp);
3597         rtl8169_rx_clear(tp);
3598 err_free_rx_1:
3599         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
3600                           tp->RxPhyAddr);
3601         tp->RxDescArray = NULL;
3602 err_free_tx_0:
3603         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
3604                           tp->TxPhyAddr);
3605         tp->TxDescArray = NULL;
3606 err_pm_runtime_put:
3607         pm_runtime_put_noidle(&pdev->dev);
3608         goto out;
3609 }
3610
3611 static void rtl8169_hw_reset(struct rtl8169_private *tp)
3612 {
3613         void __iomem *ioaddr = tp->mmio_addr;
3614
3615         /* Disable interrupts */
3616         rtl8169_irq_mask_and_ack(ioaddr);
3617
3618         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3619             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3620             tp->mac_version == RTL_GIGA_MAC_VER_31) {
3621                 while (RTL_R8(TxPoll) & NPQ)
3622                         udelay(20);
3623
3624         }
3625
3626         /* Reset the chipset */
3627         RTL_W8(ChipCmd, CmdReset);
3628
3629         /* PCI commit */
3630         RTL_R8(ChipCmd);
3631 }
3632
3633 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
3634 {
3635         void __iomem *ioaddr = tp->mmio_addr;
3636         u32 cfg = rtl8169_rx_config;
3637
3638         cfg |= (RTL_R32(RxConfig) & RTL_RX_CONFIG_MASK);
3639         RTL_W32(RxConfig, cfg);
3640
3641         /* Set DMA burst size and Interframe Gap Time */
3642         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3643                 (InterFrameGap << TxInterFrameGapShift));
3644 }
3645
3646 static void rtl_hw_start(struct net_device *dev)
3647 {
3648         struct rtl8169_private *tp = netdev_priv(dev);
3649
3650         rtl_hw_reset(tp);
3651
3652         tp->hw_start(dev);
3653
3654         netif_start_queue(dev);
3655 }
3656
3657 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3658                                          void __iomem *ioaddr)
3659 {
3660         /*
3661          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3662          * register to be written before TxDescAddrLow to work.
3663          * Switching from MMIO to I/O access fixes the issue as well.
3664          */
3665         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
3666         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
3667         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
3668         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
3669 }
3670
3671 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
3672 {
3673         u16 cmd;
3674
3675         cmd = RTL_R16(CPlusCmd);
3676         RTL_W16(CPlusCmd, cmd);
3677         return cmd;
3678 }
3679
3680 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
3681 {
3682         /* Low hurts. Let's disable the filtering. */
3683         RTL_W16(RxMaxSize, rx_buf_sz + 1);
3684 }
3685
3686 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
3687 {
3688         static const struct rtl_cfg2_info {
3689                 u32 mac_version;
3690                 u32 clk;
3691                 u32 val;
3692         } cfg2_info [] = {
3693                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
3694                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
3695                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
3696                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3697         };
3698         const struct rtl_cfg2_info *p = cfg2_info;
3699         unsigned int i;
3700         u32 clk;
3701
3702         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
3703         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
3704                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
3705                         RTL_W32(0x7c, p->val);
3706                         break;
3707                 }
3708         }
3709 }
3710
3711 static void rtl_hw_start_8169(struct net_device *dev)
3712 {
3713         struct rtl8169_private *tp = netdev_priv(dev);
3714         void __iomem *ioaddr = tp->mmio_addr;
3715         struct pci_dev *pdev = tp->pci_dev;
3716
3717         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
3718                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
3719                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
3720         }
3721
3722         RTL_W8(Cfg9346, Cfg9346_Unlock);
3723         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
3724             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3725             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
3726             tp->mac_version == RTL_GIGA_MAC_VER_04)
3727                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3728
3729         RTL_W8(EarlyTxThres, NoEarlyTx);
3730
3731         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
3732
3733         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
3734             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3735             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
3736             tp->mac_version == RTL_GIGA_MAC_VER_04)
3737                 rtl_set_rx_tx_config_registers(tp);
3738
3739         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3740
3741         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3742             tp->mac_version == RTL_GIGA_MAC_VER_03) {
3743                 dprintk("Set MAC Reg C+CR Offset 0xE0. "
3744                         "Bit-3 and bit-14 MUST be 1\n");
3745                 tp->cp_cmd |= (1 << 14);
3746         }
3747
3748         RTL_W16(CPlusCmd, tp->cp_cmd);
3749
3750         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
3751
3752         /*
3753          * Undocumented corner. Supposedly:
3754          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3755          */
3756         RTL_W16(IntrMitigate, 0x0000);
3757
3758         rtl_set_rx_tx_desc_registers(tp, ioaddr);
3759
3760         if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
3761             tp->mac_version != RTL_GIGA_MAC_VER_02 &&
3762             tp->mac_version != RTL_GIGA_MAC_VER_03 &&
3763             tp->mac_version != RTL_GIGA_MAC_VER_04) {
3764                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3765                 rtl_set_rx_tx_config_registers(tp);
3766         }
3767
3768         RTL_W8(Cfg9346, Cfg9346_Lock);
3769
3770         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3771         RTL_R8(IntrMask);
3772
3773         RTL_W32(RxMissed, 0);
3774
3775         rtl_set_rx_mode(dev);
3776
3777         /* no early-rx interrupts */
3778         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
3779
3780         /* Enable all known interrupts by setting the interrupt mask. */
3781         RTL_W16(IntrMask, tp->intr_event);
3782 }
3783
3784 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
3785 {
3786         struct net_device *dev = pci_get_drvdata(pdev);
3787         struct rtl8169_private *tp = netdev_priv(dev);
3788         int cap = tp->pcie_cap;
3789
3790         if (cap) {
3791                 u16 ctl;
3792
3793                 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
3794                 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
3795                 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
3796         }
3797 }
3798
3799 static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
3800 {
3801         u32 csi;
3802
3803         csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
3804         rtl_csi_write(ioaddr, 0x070c, csi | bits);
3805 }
3806
3807 static void rtl_csi_access_enable_1(void __iomem *ioaddr)
3808 {
3809         rtl_csi_access_enable(ioaddr, 0x17000000);
3810 }
3811
3812 static void rtl_csi_access_enable_2(void __iomem *ioaddr)
3813 {
3814         rtl_csi_access_enable(ioaddr, 0x27000000);
3815 }
3816
3817 struct ephy_info {
3818         unsigned int offset;
3819         u16 mask;
3820         u16 bits;
3821 };
3822
3823 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
3824 {
3825         u16 w;
3826
3827         while (len-- > 0) {
3828                 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
3829                 rtl_ephy_write(ioaddr, e->offset, w);
3830                 e++;
3831         }
3832 }
3833
3834 static void rtl_disable_clock_request(struct pci_dev *pdev)
3835 {
3836         struct net_device *dev = pci_get_drvdata(pdev);
3837         struct rtl8169_private *tp = netdev_priv(dev);
3838         int cap = tp->pcie_cap;
3839
3840         if (cap) {
3841                 u16 ctl;
3842
3843                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3844                 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
3845                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3846         }
3847 }
3848
3849 static void rtl_enable_clock_request(struct pci_dev *pdev)
3850 {
3851         struct net_device *dev = pci_get_drvdata(pdev);
3852         struct rtl8169_private *tp = netdev_priv(dev);
3853         int cap = tp->pcie_cap;
3854
3855         if (cap) {
3856                 u16 ctl;
3857
3858                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3859                 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
3860                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3861         }
3862 }
3863
3864 #define R8168_CPCMD_QUIRK_MASK (\
3865         EnableBist | \
3866         Mac_dbgo_oe | \
3867         Force_half_dup | \
3868         Force_rxflow_en | \
3869         Force_txflow_en | \
3870         Cxpl_dbg_sel | \
3871         ASF | \
3872         PktCntrDisable | \
3873         Mac_dbgo_sel)
3874
3875 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
3876 {
3877         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3878
3879         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3880
3881         rtl_tx_performance_tweak(pdev,
3882                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3883 }
3884
3885 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
3886 {
3887         rtl_hw_start_8168bb(ioaddr, pdev);
3888
3889         RTL_W8(MaxTxPacketSize, TxPacketMax);
3890
3891         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
3892 }
3893
3894 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
3895 {
3896         RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
3897
3898         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3899
3900         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3901
3902         rtl_disable_clock_request(pdev);
3903
3904         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3905 }
3906
3907 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
3908 {
3909         static const struct ephy_info e_info_8168cp[] = {
3910                 { 0x01, 0,      0x0001 },
3911                 { 0x02, 0x0800, 0x1000 },
3912                 { 0x03, 0,      0x0042 },
3913                 { 0x06, 0x0080, 0x0000 },
3914                 { 0x07, 0,      0x2000 }
3915         };
3916
3917         rtl_csi_access_enable_2(ioaddr);
3918
3919         rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
3920
3921         __rtl_hw_start_8168cp(ioaddr, pdev);
3922 }
3923
3924 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
3925 {
3926         rtl_csi_access_enable_2(ioaddr);
3927
3928         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3929
3930         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3931
3932         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3933 }
3934
3935 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
3936 {
3937         rtl_csi_access_enable_2(ioaddr);
3938
3939         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3940
3941         /* Magic. */
3942         RTL_W8(DBG_REG, 0x20);
3943
3944         RTL_W8(MaxTxPacketSize, TxPacketMax);
3945
3946         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3947
3948         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3949 }
3950
3951 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
3952 {
3953         static const struct ephy_info e_info_8168c_1[] = {
3954                 { 0x02, 0x0800, 0x1000 },
3955                 { 0x03, 0,      0x0002 },
3956                 { 0x06, 0x0080, 0x0000 }
3957         };
3958
3959         rtl_csi_access_enable_2(ioaddr);
3960
3961         RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
3962
3963         rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
3964
3965         __rtl_hw_start_8168cp(ioaddr, pdev);
3966 }
3967
3968 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
3969 {
3970         static const struct ephy_info e_info_8168c_2[] = {
3971                 { 0x01, 0,      0x0001 },
3972                 { 0x03, 0x0400, 0x0220 }
3973         };
3974
3975         rtl_csi_access_enable_2(ioaddr);
3976
3977         rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
3978
3979         __rtl_hw_start_8168cp(ioaddr, pdev);
3980 }
3981
3982 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
3983 {
3984         rtl_hw_start_8168c_2(ioaddr, pdev);
3985 }
3986
3987 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
3988 {
3989         rtl_csi_access_enable_2(ioaddr);
3990
3991         __rtl_hw_start_8168cp(ioaddr, pdev);
3992 }
3993
3994 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
3995 {
3996         rtl_csi_access_enable_2(ioaddr);
3997
3998         rtl_disable_clock_request(pdev);
3999
4000         RTL_W8(MaxTxPacketSize, TxPacketMax);
4001
4002         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4003
4004         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4005 }
4006
4007 static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev)
4008 {
4009         rtl_csi_access_enable_1(ioaddr);
4010
4011         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4012
4013         RTL_W8(MaxTxPacketSize, TxPacketMax);
4014
4015         rtl_disable_clock_request(pdev);
4016 }
4017
4018 static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
4019 {
4020         static const struct ephy_info e_info_8168d_4[] = {
4021                 { 0x0b, ~0,     0x48 },
4022                 { 0x19, 0x20,   0x50 },
4023                 { 0x0c, ~0,     0x20 }
4024         };
4025         int i;
4026
4027         rtl_csi_access_enable_1(ioaddr);
4028
4029         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4030
4031         RTL_W8(MaxTxPacketSize, TxPacketMax);
4032
4033         for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4034                 const struct ephy_info *e = e_info_8168d_4 + i;
4035                 u16 w;
4036
4037                 w = rtl_ephy_read(ioaddr, e->offset);
4038                 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
4039         }
4040
4041         rtl_enable_clock_request(pdev);
4042 }
4043
4044 static void rtl_hw_start_8168e(void __iomem *ioaddr, struct pci_dev *pdev)
4045 {
4046         static const struct ephy_info e_info_8168e[] = {
4047                 { 0x00, 0x0200, 0x0100 },
4048                 { 0x00, 0x0000, 0x0004 },
4049                 { 0x06, 0x0002, 0x0001 },
4050                 { 0x06, 0x0000, 0x0030 },
4051                 { 0x07, 0x0000, 0x2000 },
4052                 { 0x00, 0x0000, 0x0020 },
4053                 { 0x03, 0x5800, 0x2000 },
4054                 { 0x03, 0x0000, 0x0001 },
4055                 { 0x01, 0x0800, 0x1000 },
4056                 { 0x07, 0x0000, 0x4000 },
4057                 { 0x1e, 0x0000, 0x2000 },
4058                 { 0x19, 0xffff, 0xfe6c },
4059                 { 0x0a, 0x0000, 0x0040 }
4060         };
4061
4062         rtl_csi_access_enable_2(ioaddr);
4063
4064         rtl_ephy_init(ioaddr, e_info_8168e, ARRAY_SIZE(e_info_8168e));
4065
4066         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4067
4068         RTL_W8(MaxTxPacketSize, TxPacketMax);
4069
4070         rtl_disable_clock_request(pdev);
4071
4072         /* Reset tx FIFO pointer */
4073         RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
4074         RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
4075
4076         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4077 }
4078
4079 static void rtl_hw_start_8168(struct net_device *dev)
4080 {
4081         struct rtl8169_private *tp = netdev_priv(dev);
4082         void __iomem *ioaddr = tp->mmio_addr;
4083         struct pci_dev *pdev = tp->pci_dev;
4084
4085         RTL_W8(Cfg9346, Cfg9346_Unlock);
4086
4087         RTL_W8(MaxTxPacketSize, TxPacketMax);
4088
4089         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4090
4091         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
4092
4093         RTL_W16(CPlusCmd, tp->cp_cmd);
4094
4095         RTL_W16(IntrMitigate, 0x5151);
4096
4097         /* Work around for RxFIFO overflow. */
4098         if (tp->mac_version == RTL_GIGA_MAC_VER_11 ||
4099             tp->mac_version == RTL_GIGA_MAC_VER_22) {
4100                 tp->intr_event |= RxFIFOOver | PCSTimeout;
4101                 tp->intr_event &= ~RxOverflow;
4102         }
4103
4104         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4105
4106         rtl_set_rx_mode(dev);
4107
4108         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4109                 (InterFrameGap << TxInterFrameGapShift));
4110
4111         RTL_R8(IntrMask);
4112
4113         switch (tp->mac_version) {
4114         case RTL_GIGA_MAC_VER_11:
4115                 rtl_hw_start_8168bb(ioaddr, pdev);
4116                 break;
4117
4118         case RTL_GIGA_MAC_VER_12:
4119         case RTL_GIGA_MAC_VER_17:
4120                 rtl_hw_start_8168bef(ioaddr, pdev);
4121                 break;
4122
4123         case RTL_GIGA_MAC_VER_18:
4124                 rtl_hw_start_8168cp_1(ioaddr, pdev);
4125                 break;
4126
4127         case RTL_GIGA_MAC_VER_19:
4128                 rtl_hw_start_8168c_1(ioaddr, pdev);
4129                 break;
4130
4131         case RTL_GIGA_MAC_VER_20:
4132                 rtl_hw_start_8168c_2(ioaddr, pdev);
4133                 break;
4134
4135         case RTL_GIGA_MAC_VER_21:
4136                 rtl_hw_start_8168c_3(ioaddr, pdev);
4137                 break;
4138
4139         case RTL_GIGA_MAC_VER_22:
4140                 rtl_hw_start_8168c_4(ioaddr, pdev);
4141                 break;
4142
4143         case RTL_GIGA_MAC_VER_23:
4144                 rtl_hw_start_8168cp_2(ioaddr, pdev);
4145                 break;
4146
4147         case RTL_GIGA_MAC_VER_24:
4148                 rtl_hw_start_8168cp_3(ioaddr, pdev);
4149                 break;
4150
4151         case RTL_GIGA_MAC_VER_25:
4152         case RTL_GIGA_MAC_VER_26:
4153         case RTL_GIGA_MAC_VER_27:
4154                 rtl_hw_start_8168d(ioaddr, pdev);
4155                 break;
4156
4157         case RTL_GIGA_MAC_VER_28:
4158                 rtl_hw_start_8168d_4(ioaddr, pdev);
4159                 break;
4160
4161         case RTL_GIGA_MAC_VER_31:
4162                 rtl_hw_start_8168dp(ioaddr, pdev);
4163                 break;
4164
4165         case RTL_GIGA_MAC_VER_32:
4166         case RTL_GIGA_MAC_VER_33:
4167                 rtl_hw_start_8168e(ioaddr, pdev);
4168                 break;
4169
4170         default:
4171                 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
4172                         dev->name, tp->mac_version);
4173                 break;
4174         }
4175
4176         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4177
4178         RTL_W8(Cfg9346, Cfg9346_Lock);
4179
4180         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4181
4182         RTL_W16(IntrMask, tp->intr_event);
4183 }
4184
4185 #define R810X_CPCMD_QUIRK_MASK (\
4186         EnableBist | \
4187         Mac_dbgo_oe | \
4188         Force_half_dup | \
4189         Force_rxflow_en | \
4190         Force_txflow_en | \
4191         Cxpl_dbg_sel | \
4192         ASF | \
4193         PktCntrDisable | \
4194         Mac_dbgo_sel)
4195
4196 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4197 {
4198         static const struct ephy_info e_info_8102e_1[] = {
4199                 { 0x01, 0, 0x6e65 },
4200                 { 0x02, 0, 0x091f },
4201                 { 0x03, 0, 0xc2f9 },
4202                 { 0x06, 0, 0xafb5 },
4203                 { 0x07, 0, 0x0e00 },
4204                 { 0x19, 0, 0xec80 },
4205                 { 0x01, 0, 0x2e65 },
4206                 { 0x01, 0, 0x6e65 }
4207         };
4208         u8 cfg1;
4209
4210         rtl_csi_access_enable_2(ioaddr);
4211
4212         RTL_W8(DBG_REG, FIX_NAK_1);
4213
4214         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4215
4216         RTL_W8(Config1,
4217                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
4218         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4219
4220         cfg1 = RTL_R8(Config1);
4221         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
4222                 RTL_W8(Config1, cfg1 & ~LEDS0);
4223
4224         rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
4225 }
4226
4227 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4228 {
4229         rtl_csi_access_enable_2(ioaddr);
4230
4231         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4232
4233         RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
4234         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4235 }
4236
4237 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
4238 {
4239         rtl_hw_start_8102e_2(ioaddr, pdev);
4240
4241         rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
4242 }
4243
4244 static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4245 {
4246         static const struct ephy_info e_info_8105e_1[] = {
4247                 { 0x07, 0, 0x4000 },
4248                 { 0x19, 0, 0x0200 },
4249                 { 0x19, 0, 0x0020 },
4250                 { 0x1e, 0, 0x2000 },
4251                 { 0x03, 0, 0x0001 },
4252                 { 0x19, 0, 0x0100 },
4253                 { 0x19, 0, 0x0004 },
4254                 { 0x0a, 0, 0x0020 }
4255         };
4256
4257         /* Force LAN exit from ASPM if Rx/Tx are not idle */
4258         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
4259
4260         /* Disable Early Tally Counter */
4261         RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
4262
4263         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4264         RTL_W8(DLLPR, RTL_R8(DLLPR) | PM_SWITCH);
4265
4266         rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
4267 }
4268
4269 static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4270 {
4271         rtl_hw_start_8105e_1(ioaddr, pdev);
4272         rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
4273 }
4274
4275 static void rtl_hw_start_8101(struct net_device *dev)
4276 {
4277         struct rtl8169_private *tp = netdev_priv(dev);
4278         void __iomem *ioaddr = tp->mmio_addr;
4279         struct pci_dev *pdev = tp->pci_dev;
4280
4281         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
4282             tp->mac_version == RTL_GIGA_MAC_VER_16) {
4283                 int cap = tp->pcie_cap;
4284
4285                 if (cap) {
4286                         pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
4287                                               PCI_EXP_DEVCTL_NOSNOOP_EN);
4288                 }
4289         }
4290
4291         RTL_W8(Cfg9346, Cfg9346_Unlock);
4292
4293         switch (tp->mac_version) {
4294         case RTL_GIGA_MAC_VER_07:
4295                 rtl_hw_start_8102e_1(ioaddr, pdev);
4296                 break;
4297
4298         case RTL_GIGA_MAC_VER_08:
4299                 rtl_hw_start_8102e_3(ioaddr, pdev);
4300                 break;
4301
4302         case RTL_GIGA_MAC_VER_09:
4303                 rtl_hw_start_8102e_2(ioaddr, pdev);
4304                 break;
4305
4306         case RTL_GIGA_MAC_VER_29:
4307                 rtl_hw_start_8105e_1(ioaddr, pdev);
4308                 break;
4309         case RTL_GIGA_MAC_VER_30:
4310                 rtl_hw_start_8105e_2(ioaddr, pdev);
4311                 break;
4312         }
4313
4314         RTL_W8(Cfg9346, Cfg9346_Lock);
4315
4316         RTL_W8(MaxTxPacketSize, TxPacketMax);
4317
4318         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4319
4320         tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
4321         RTL_W16(CPlusCmd, tp->cp_cmd);
4322
4323         RTL_W16(IntrMitigate, 0x0000);
4324
4325         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4326
4327         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4328         rtl_set_rx_tx_config_registers(tp);
4329
4330         RTL_R8(IntrMask);
4331
4332         rtl_set_rx_mode(dev);
4333
4334         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
4335
4336         RTL_W16(IntrMask, tp->intr_event);
4337 }
4338
4339 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
4340 {
4341         if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
4342                 return -EINVAL;
4343
4344         dev->mtu = new_mtu;
4345         netdev_update_features(dev);
4346
4347         return 0;
4348 }
4349
4350 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
4351 {
4352         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
4353         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
4354 }
4355
4356 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
4357                                      void **data_buff, struct RxDesc *desc)
4358 {
4359         dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
4360                          DMA_FROM_DEVICE);
4361
4362         kfree(*data_buff);
4363         *data_buff = NULL;
4364         rtl8169_make_unusable_by_asic(desc);
4365 }
4366
4367 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
4368 {
4369         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
4370
4371         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
4372 }
4373
4374 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
4375                                        u32 rx_buf_sz)
4376 {
4377         desc->addr = cpu_to_le64(mapping);
4378         wmb();
4379         rtl8169_mark_to_asic(desc, rx_buf_sz);
4380 }
4381
4382 static inline void *rtl8169_align(void *data)
4383 {
4384         return (void *)ALIGN((long)data, 16);
4385 }
4386
4387 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
4388                                              struct RxDesc *desc)
4389 {
4390         void *data;
4391         dma_addr_t mapping;
4392         struct device *d = &tp->pci_dev->dev;
4393         struct net_device *dev = tp->dev;
4394         int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
4395
4396         data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
4397         if (!data)
4398                 return NULL;
4399
4400         if (rtl8169_align(data) != data) {
4401                 kfree(data);
4402                 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
4403                 if (!data)
4404                         return NULL;
4405         }
4406
4407         mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
4408                                  DMA_FROM_DEVICE);
4409         if (unlikely(dma_mapping_error(d, mapping))) {
4410                 if (net_ratelimit())
4411                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
4412                 goto err_out;
4413         }
4414
4415         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
4416         return data;
4417
4418 err_out:
4419         kfree(data);
4420         return NULL;
4421 }
4422
4423 static void rtl8169_rx_clear(struct rtl8169_private *tp)
4424 {
4425         unsigned int i;
4426
4427         for (i = 0; i < NUM_RX_DESC; i++) {
4428                 if (tp->Rx_databuff[i]) {
4429                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
4430                                             tp->RxDescArray + i);
4431                 }
4432         }
4433 }
4434
4435 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
4436 {
4437         desc->opts1 |= cpu_to_le32(RingEnd);
4438 }
4439
4440 static int rtl8169_rx_fill(struct rtl8169_private *tp)
4441 {
4442         unsigned int i;
4443
4444         for (i = 0; i < NUM_RX_DESC; i++) {
4445                 void *data;
4446
4447                 if (tp->Rx_databuff[i])
4448                         continue;
4449
4450                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
4451                 if (!data) {
4452                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
4453                         goto err_out;
4454                 }
4455                 tp->Rx_databuff[i] = data;
4456         }
4457
4458         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4459         return 0;
4460
4461 err_out:
4462         rtl8169_rx_clear(tp);
4463         return -ENOMEM;
4464 }
4465
4466 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4467 {
4468         tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
4469 }
4470
4471 static int rtl8169_init_ring(struct net_device *dev)
4472 {
4473         struct rtl8169_private *tp = netdev_priv(dev);
4474
4475         rtl8169_init_ring_indexes(tp);
4476
4477         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
4478         memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
4479
4480         return rtl8169_rx_fill(tp);
4481 }
4482
4483 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
4484                                  struct TxDesc *desc)
4485 {
4486         unsigned int len = tx_skb->len;
4487
4488         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
4489
4490         desc->opts1 = 0x00;
4491         desc->opts2 = 0x00;
4492         desc->addr = 0x00;
4493         tx_skb->len = 0;
4494 }
4495
4496 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4497                                    unsigned int n)
4498 {
4499         unsigned int i;
4500
4501         for (i = 0; i < n; i++) {
4502                 unsigned int entry = (start + i) % NUM_TX_DESC;
4503                 struct ring_info *tx_skb = tp->tx_skb + entry;
4504                 unsigned int len = tx_skb->len;
4505
4506                 if (len) {
4507                         struct sk_buff *skb = tx_skb->skb;
4508
4509                         rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4510                                              tp->TxDescArray + entry);
4511                         if (skb) {
4512                                 tp->dev->stats.tx_dropped++;
4513                                 dev_kfree_skb(skb);
4514                                 tx_skb->skb = NULL;
4515                         }
4516                 }
4517         }
4518 }
4519
4520 static void rtl8169_tx_clear(struct rtl8169_private *tp)
4521 {
4522         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
4523         tp->cur_tx = tp->dirty_tx = 0;
4524 }
4525
4526 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
4527 {
4528         struct rtl8169_private *tp = netdev_priv(dev);
4529
4530         PREPARE_DELAYED_WORK(&tp->task, task);
4531         schedule_delayed_work(&tp->task, 4);
4532 }
4533
4534 static void rtl8169_wait_for_quiescence(struct net_device *dev)
4535 {
4536         struct rtl8169_private *tp = netdev_priv(dev);
4537         void __iomem *ioaddr = tp->mmio_addr;
4538
4539         synchronize_irq(dev->irq);
4540
4541         /* Wait for any pending NAPI task to complete */
4542         napi_disable(&tp->napi);
4543
4544         rtl8169_irq_mask_and_ack(ioaddr);
4545
4546         tp->intr_mask = 0xffff;
4547         RTL_W16(IntrMask, tp->intr_event);
4548         napi_enable(&tp->napi);
4549 }
4550
4551 static void rtl8169_reinit_task(struct work_struct *work)
4552 {
4553         struct rtl8169_private *tp =
4554                 container_of(work, struct rtl8169_private, task.work);
4555         struct net_device *dev = tp->dev;
4556         int ret;
4557
4558         rtnl_lock();
4559
4560         if (!netif_running(dev))
4561                 goto out_unlock;
4562
4563         rtl8169_wait_for_quiescence(dev);
4564         rtl8169_close(dev);
4565
4566         ret = rtl8169_open(dev);
4567         if (unlikely(ret < 0)) {
4568                 if (net_ratelimit())
4569                         netif_err(tp, drv, dev,
4570                                   "reinit failure (status = %d). Rescheduling\n",
4571                                   ret);
4572                 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4573         }
4574
4575 out_unlock:
4576         rtnl_unlock();
4577 }
4578
4579 static void rtl8169_reset_task(struct work_struct *work)
4580 {
4581         struct rtl8169_private *tp =
4582                 container_of(work, struct rtl8169_private, task.work);
4583         struct net_device *dev = tp->dev;
4584         int i;
4585
4586         rtnl_lock();
4587
4588         if (!netif_running(dev))
4589                 goto out_unlock;
4590
4591         rtl8169_wait_for_quiescence(dev);
4592
4593         for (i = 0; i < NUM_RX_DESC; i++)
4594                 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
4595
4596         rtl8169_tx_clear(tp);
4597
4598         rtl8169_init_ring_indexes(tp);
4599         rtl_hw_start(dev);
4600         netif_wake_queue(dev);
4601         rtl8169_check_link_status(dev, tp, tp->mmio_addr);
4602
4603 out_unlock:
4604         rtnl_unlock();
4605 }
4606
4607 static void rtl8169_tx_timeout(struct net_device *dev)
4608 {
4609         struct rtl8169_private *tp = netdev_priv(dev);
4610
4611         rtl8169_hw_reset(tp);
4612
4613         /* Let's wait a bit while any (async) irq lands on */
4614         rtl8169_schedule_work(dev, rtl8169_reset_task);
4615 }
4616
4617 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4618                               u32 *opts)
4619 {
4620         struct skb_shared_info *info = skb_shinfo(skb);
4621         unsigned int cur_frag, entry;
4622         struct TxDesc * uninitialized_var(txd);
4623         struct device *d = &tp->pci_dev->dev;
4624
4625         entry = tp->cur_tx;
4626         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4627                 skb_frag_t *frag = info->frags + cur_frag;
4628                 dma_addr_t mapping;
4629                 u32 status, len;
4630                 void *addr;
4631
4632                 entry = (entry + 1) % NUM_TX_DESC;
4633
4634                 txd = tp->TxDescArray + entry;
4635                 len = frag->size;
4636                 addr = ((void *) page_address(frag->page)) + frag->page_offset;
4637                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
4638                 if (unlikely(dma_mapping_error(d, mapping))) {
4639                         if (net_ratelimit())
4640                                 netif_err(tp, drv, tp->dev,
4641                                           "Failed to map TX fragments DMA!\n");
4642                         goto err_out;
4643                 }
4644
4645                 /* Anti gcc 2.95.3 bugware (sic) */
4646                 status = opts[0] | len |
4647                         (RingEnd * !((entry + 1) % NUM_TX_DESC));
4648
4649                 txd->opts1 = cpu_to_le32(status);
4650                 txd->opts2 = cpu_to_le32(opts[1]);
4651                 txd->addr = cpu_to_le64(mapping);
4652
4653                 tp->tx_skb[entry].len = len;
4654         }
4655
4656         if (cur_frag) {
4657                 tp->tx_skb[entry].skb = skb;
4658                 txd->opts1 |= cpu_to_le32(LastFrag);
4659         }
4660
4661         return cur_frag;
4662
4663 err_out:
4664         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4665         return -EIO;
4666 }
4667
4668 static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
4669                                     struct sk_buff *skb, u32 *opts)
4670 {
4671         const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
4672         u32 mss = skb_shinfo(skb)->gso_size;
4673         int offset = info->opts_offset;
4674
4675         if (mss) {
4676                 opts[0] |= TD_LSO;
4677                 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
4678         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4679                 const struct iphdr *ip = ip_hdr(skb);
4680
4681                 if (ip->protocol == IPPROTO_TCP)
4682                         opts[offset] |= info->checksum.tcp;
4683                 else if (ip->protocol == IPPROTO_UDP)
4684                         opts[offset] |= info->checksum.udp;
4685                 else
4686                         WARN_ON_ONCE(1);
4687         }
4688 }
4689
4690 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4691                                       struct net_device *dev)
4692 {
4693         struct rtl8169_private *tp = netdev_priv(dev);
4694         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
4695         struct TxDesc *txd = tp->TxDescArray + entry;
4696         void __iomem *ioaddr = tp->mmio_addr;
4697         struct device *d = &tp->pci_dev->dev;
4698         dma_addr_t mapping;
4699         u32 status, len;
4700         u32 opts[2];
4701         int frags;
4702
4703         if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
4704                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
4705                 goto err_stop_0;
4706         }
4707
4708         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
4709                 goto err_stop_0;
4710
4711         len = skb_headlen(skb);
4712         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
4713         if (unlikely(dma_mapping_error(d, mapping))) {
4714                 if (net_ratelimit())
4715                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
4716                 goto err_dma_0;
4717         }
4718
4719         tp->tx_skb[entry].len = len;
4720         txd->addr = cpu_to_le64(mapping);
4721
4722         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
4723         opts[0] = DescOwn;
4724
4725         rtl8169_tso_csum(tp, skb, opts);
4726
4727         frags = rtl8169_xmit_frags(tp, skb, opts);
4728         if (frags < 0)
4729                 goto err_dma_1;
4730         else if (frags)
4731                 opts[0] |= FirstFrag;
4732         else {
4733                 opts[0] |= FirstFrag | LastFrag;
4734                 tp->tx_skb[entry].skb = skb;
4735         }
4736
4737         txd->opts2 = cpu_to_le32(opts[1]);
4738
4739         wmb();
4740
4741         /* Anti gcc 2.95.3 bugware (sic) */
4742         status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4743         txd->opts1 = cpu_to_le32(status);
4744
4745         tp->cur_tx += frags + 1;
4746
4747         wmb();
4748
4749         RTL_W8(TxPoll, NPQ);
4750
4751         if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
4752                 netif_stop_queue(dev);
4753                 smp_rmb();
4754                 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
4755                         netif_wake_queue(dev);
4756         }
4757
4758         return NETDEV_TX_OK;
4759
4760 err_dma_1:
4761         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
4762 err_dma_0:
4763         dev_kfree_skb(skb);
4764         dev->stats.tx_dropped++;
4765         return NETDEV_TX_OK;
4766
4767 err_stop_0:
4768         netif_stop_queue(dev);
4769         dev->stats.tx_dropped++;
4770         return NETDEV_TX_BUSY;
4771 }
4772
4773 static void rtl8169_pcierr_interrupt(struct net_device *dev)
4774 {
4775         struct rtl8169_private *tp = netdev_priv(dev);
4776         struct pci_dev *pdev = tp->pci_dev;
4777         u16 pci_status, pci_cmd;
4778
4779         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4780         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
4781
4782         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
4783                   pci_cmd, pci_status);
4784
4785         /*
4786          * The recovery sequence below admits a very elaborated explanation:
4787          * - it seems to work;
4788          * - I did not see what else could be done;
4789          * - it makes iop3xx happy.
4790          *
4791          * Feel free to adjust to your needs.
4792          */
4793         if (pdev->broken_parity_status)
4794                 pci_cmd &= ~PCI_COMMAND_PARITY;
4795         else
4796                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
4797
4798         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
4799
4800         pci_write_config_word(pdev, PCI_STATUS,
4801                 pci_status & (PCI_STATUS_DETECTED_PARITY |
4802                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
4803                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
4804
4805         /* The infamous DAC f*ckup only happens at boot time */
4806         if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
4807                 void __iomem *ioaddr = tp->mmio_addr;
4808
4809                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
4810                 tp->cp_cmd &= ~PCIDAC;
4811                 RTL_W16(CPlusCmd, tp->cp_cmd);
4812                 dev->features &= ~NETIF_F_HIGHDMA;
4813         }
4814
4815         rtl8169_hw_reset(tp);
4816
4817         rtl8169_schedule_work(dev, rtl8169_reinit_task);
4818 }
4819
4820 static void rtl8169_tx_interrupt(struct net_device *dev,
4821                                  struct rtl8169_private *tp,
4822                                  void __iomem *ioaddr)
4823 {
4824         unsigned int dirty_tx, tx_left;
4825
4826         dirty_tx = tp->dirty_tx;
4827         smp_rmb();
4828         tx_left = tp->cur_tx - dirty_tx;
4829
4830         while (tx_left > 0) {
4831                 unsigned int entry = dirty_tx % NUM_TX_DESC;
4832                 struct ring_info *tx_skb = tp->tx_skb + entry;
4833                 u32 status;
4834
4835                 rmb();
4836                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4837                 if (status & DescOwn)
4838                         break;
4839
4840                 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4841                                      tp->TxDescArray + entry);
4842                 if (status & LastFrag) {
4843                         dev->stats.tx_packets++;
4844                         dev->stats.tx_bytes += tx_skb->skb->len;
4845                         dev_kfree_skb(tx_skb->skb);
4846                         tx_skb->skb = NULL;
4847                 }
4848                 dirty_tx++;
4849                 tx_left--;
4850         }
4851
4852         if (tp->dirty_tx != dirty_tx) {
4853                 tp->dirty_tx = dirty_tx;
4854                 smp_wmb();
4855                 if (netif_queue_stopped(dev) &&
4856                     (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
4857                         netif_wake_queue(dev);
4858                 }
4859                 /*
4860                  * 8168 hack: TxPoll requests are lost when the Tx packets are
4861                  * too close. Let's kick an extra TxPoll request when a burst
4862                  * of start_xmit activity is detected (if it is not detected,
4863                  * it is slow enough). -- FR
4864                  */
4865                 smp_rmb();
4866                 if (tp->cur_tx != dirty_tx)
4867                         RTL_W8(TxPoll, NPQ);
4868         }
4869 }
4870
4871 static inline int rtl8169_fragmented_frame(u32 status)
4872 {
4873         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4874 }
4875
4876 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
4877 {
4878         u32 status = opts1 & RxProtoMask;
4879
4880         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
4881             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
4882                 skb->ip_summed = CHECKSUM_UNNECESSARY;
4883         else
4884                 skb_checksum_none_assert(skb);
4885 }
4886
4887 static struct sk_buff *rtl8169_try_rx_copy(void *data,
4888                                            struct rtl8169_private *tp,
4889                                            int pkt_size,
4890                                            dma_addr_t addr)
4891 {
4892         struct sk_buff *skb;
4893         struct device *d = &tp->pci_dev->dev;
4894
4895         data = rtl8169_align(data);
4896         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
4897         prefetch(data);
4898         skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
4899         if (skb)
4900                 memcpy(skb->data, data, pkt_size);
4901         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
4902
4903         return skb;
4904 }
4905
4906 static int rtl8169_rx_interrupt(struct net_device *dev,
4907                                 struct rtl8169_private *tp,
4908                                 void __iomem *ioaddr, u32 budget)
4909 {
4910         unsigned int cur_rx, rx_left;
4911         unsigned int count;
4912
4913         cur_rx = tp->cur_rx;
4914         rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
4915         rx_left = min(rx_left, budget);
4916
4917         for (; rx_left > 0; rx_left--, cur_rx++) {
4918                 unsigned int entry = cur_rx % NUM_RX_DESC;
4919                 struct RxDesc *desc = tp->RxDescArray + entry;
4920                 u32 status;
4921
4922                 rmb();
4923                 status = le32_to_cpu(desc->opts1);
4924
4925                 if (status & DescOwn)
4926                         break;
4927                 if (unlikely(status & RxRES)) {
4928                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
4929                                    status);
4930                         dev->stats.rx_errors++;
4931                         if (status & (RxRWT | RxRUNT))
4932                                 dev->stats.rx_length_errors++;
4933                         if (status & RxCRC)
4934                                 dev->stats.rx_crc_errors++;
4935                         if (status & RxFOVF) {
4936                                 rtl8169_schedule_work(dev, rtl8169_reset_task);
4937                                 dev->stats.rx_fifo_errors++;
4938                         }
4939                         rtl8169_mark_to_asic(desc, rx_buf_sz);
4940                 } else {
4941                         struct sk_buff *skb;
4942                         dma_addr_t addr = le64_to_cpu(desc->addr);
4943                         int pkt_size = (status & 0x00001FFF) - 4;
4944
4945                         /*
4946                          * The driver does not support incoming fragmented
4947                          * frames. They are seen as a symptom of over-mtu
4948                          * sized frames.
4949                          */
4950                         if (unlikely(rtl8169_fragmented_frame(status))) {
4951                                 dev->stats.rx_dropped++;
4952                                 dev->stats.rx_length_errors++;
4953                                 rtl8169_mark_to_asic(desc, rx_buf_sz);
4954                                 continue;
4955                         }
4956
4957                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
4958                                                   tp, pkt_size, addr);
4959                         rtl8169_mark_to_asic(desc, rx_buf_sz);
4960                         if (!skb) {
4961                                 dev->stats.rx_dropped++;
4962                                 continue;
4963                         }
4964
4965                         rtl8169_rx_csum(skb, status);
4966                         skb_put(skb, pkt_size);
4967                         skb->protocol = eth_type_trans(skb, dev);
4968
4969                         rtl8169_rx_vlan_tag(desc, skb);
4970
4971                         napi_gro_receive(&tp->napi, skb);
4972
4973                         dev->stats.rx_bytes += pkt_size;
4974                         dev->stats.rx_packets++;
4975                 }
4976
4977                 /* Work around for AMD plateform. */
4978                 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
4979                     (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
4980                         desc->opts2 = 0;
4981                         cur_rx++;
4982                 }
4983         }
4984
4985         count = cur_rx - tp->cur_rx;
4986         tp->cur_rx = cur_rx;
4987
4988         tp->dirty_rx += count;
4989
4990         return count;
4991 }
4992
4993 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
4994 {
4995         struct net_device *dev = dev_instance;
4996         struct rtl8169_private *tp = netdev_priv(dev);
4997         void __iomem *ioaddr = tp->mmio_addr;
4998         int handled = 0;
4999         int status;
5000
5001         /* loop handling interrupts until we have no new ones or
5002          * we hit a invalid/hotplug case.
5003          */
5004         status = RTL_R16(IntrStatus);
5005         while (status && status != 0xffff) {
5006                 handled = 1;
5007
5008                 /* Handle all of the error cases first. These will reset
5009                  * the chip, so just exit the loop.
5010                  */
5011                 if (unlikely(!netif_running(dev))) {
5012                         rtl8169_asic_down(ioaddr);
5013                         break;
5014                 }
5015
5016                 if (unlikely(status & RxFIFOOver)) {
5017                         switch (tp->mac_version) {
5018                         /* Work around for rx fifo overflow */
5019                         case RTL_GIGA_MAC_VER_11:
5020                         case RTL_GIGA_MAC_VER_22:
5021                         case RTL_GIGA_MAC_VER_26:
5022                                 netif_stop_queue(dev);
5023                                 rtl8169_tx_timeout(dev);
5024                                 goto done;
5025                         /* Testers needed. */
5026                         case RTL_GIGA_MAC_VER_17:
5027                         case RTL_GIGA_MAC_VER_19:
5028                         case RTL_GIGA_MAC_VER_20:
5029                         case RTL_GIGA_MAC_VER_21:
5030                         case RTL_GIGA_MAC_VER_23:
5031                         case RTL_GIGA_MAC_VER_24:
5032                         case RTL_GIGA_MAC_VER_27:
5033                         case RTL_GIGA_MAC_VER_28:
5034                         case RTL_GIGA_MAC_VER_31:
5035                         /* Experimental science. Pktgen proof. */
5036                         case RTL_GIGA_MAC_VER_12:
5037                         case RTL_GIGA_MAC_VER_25:
5038                                 if (status == RxFIFOOver)
5039                                         goto done;
5040                                 break;
5041                         default:
5042                                 break;
5043                         }
5044                 }
5045
5046                 if (unlikely(status & SYSErr)) {
5047                         rtl8169_pcierr_interrupt(dev);
5048                         break;
5049                 }
5050
5051                 if (status & LinkChg)
5052                         __rtl8169_check_link_status(dev, tp, ioaddr, true);
5053
5054                 /* We need to see the lastest version of tp->intr_mask to
5055                  * avoid ignoring an MSI interrupt and having to wait for
5056                  * another event which may never come.
5057                  */
5058                 smp_rmb();
5059                 if (status & tp->intr_mask & tp->napi_event) {
5060                         RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
5061                         tp->intr_mask = ~tp->napi_event;
5062
5063                         if (likely(napi_schedule_prep(&tp->napi)))
5064                                 __napi_schedule(&tp->napi);
5065                         else
5066                                 netif_info(tp, intr, dev,
5067                                            "interrupt %04x in poll\n", status);
5068                 }
5069
5070                 /* We only get a new MSI interrupt when all active irq
5071                  * sources on the chip have been acknowledged. So, ack
5072                  * everything we've seen and check if new sources have become
5073                  * active to avoid blocking all interrupts from the chip.
5074                  */
5075                 RTL_W16(IntrStatus,
5076                         (status & RxFIFOOver) ? (status | RxOverflow) : status);
5077                 status = RTL_R16(IntrStatus);
5078         }
5079 done:
5080         return IRQ_RETVAL(handled);
5081 }
5082
5083 static int rtl8169_poll(struct napi_struct *napi, int budget)
5084 {
5085         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5086         struct net_device *dev = tp->dev;
5087         void __iomem *ioaddr = tp->mmio_addr;
5088         int work_done;
5089
5090         work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
5091         rtl8169_tx_interrupt(dev, tp, ioaddr);
5092
5093         if (work_done < budget) {
5094                 napi_complete(napi);
5095
5096                 /* We need for force the visibility of tp->intr_mask
5097                  * for other CPUs, as we can loose an MSI interrupt
5098                  * and potentially wait for a retransmit timeout if we don't.
5099                  * The posted write to IntrMask is safe, as it will
5100                  * eventually make it to the chip and we won't loose anything
5101                  * until it does.
5102                  */
5103                 tp->intr_mask = 0xffff;
5104                 wmb();
5105                 RTL_W16(IntrMask, tp->intr_event);
5106         }
5107
5108         return work_done;
5109 }
5110
5111 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
5112 {
5113         struct rtl8169_private *tp = netdev_priv(dev);
5114
5115         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5116                 return;
5117
5118         dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
5119         RTL_W32(RxMissed, 0);
5120 }
5121
5122 static void rtl8169_down(struct net_device *dev)
5123 {
5124         struct rtl8169_private *tp = netdev_priv(dev);
5125         void __iomem *ioaddr = tp->mmio_addr;
5126
5127         del_timer_sync(&tp->timer);
5128
5129         netif_stop_queue(dev);
5130
5131         napi_disable(&tp->napi);
5132
5133         spin_lock_irq(&tp->lock);
5134
5135         rtl8169_asic_down(ioaddr);
5136         /*
5137          * At this point device interrupts can not be enabled in any function,
5138          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
5139          * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
5140          */
5141         rtl8169_rx_missed(dev, ioaddr);
5142
5143         spin_unlock_irq(&tp->lock);
5144
5145         synchronize_irq(dev->irq);
5146
5147         /* Give a racing hard_start_xmit a few cycles to complete. */
5148         synchronize_sched();  /* FIXME: should this be synchronize_irq()? */
5149
5150         rtl8169_tx_clear(tp);
5151
5152         rtl8169_rx_clear(tp);
5153
5154         rtl_pll_power_down(tp);
5155 }
5156
5157 static int rtl8169_close(struct net_device *dev)
5158 {
5159         struct rtl8169_private *tp = netdev_priv(dev);
5160         struct pci_dev *pdev = tp->pci_dev;
5161
5162         pm_runtime_get_sync(&pdev->dev);
5163
5164         /* Update counters before going down */
5165         rtl8169_update_counters(dev);
5166
5167         rtl8169_down(dev);
5168
5169         free_irq(dev->irq, dev);
5170
5171         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5172                           tp->RxPhyAddr);
5173         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5174                           tp->TxPhyAddr);
5175         tp->TxDescArray = NULL;
5176         tp->RxDescArray = NULL;
5177
5178         pm_runtime_put_sync(&pdev->dev);
5179
5180         return 0;
5181 }
5182
5183 static void rtl_set_rx_mode(struct net_device *dev)
5184 {
5185         struct rtl8169_private *tp = netdev_priv(dev);
5186         void __iomem *ioaddr = tp->mmio_addr;
5187         unsigned long flags;
5188         u32 mc_filter[2];       /* Multicast hash filter */
5189         int rx_mode;
5190         u32 tmp = 0;
5191
5192         if (dev->flags & IFF_PROMISC) {
5193                 /* Unconditionally log net taps. */
5194                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
5195                 rx_mode =
5196                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5197                     AcceptAllPhys;
5198                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5199         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
5200                    (dev->flags & IFF_ALLMULTI)) {
5201                 /* Too many to filter perfectly -- accept all multicasts. */
5202                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5203                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5204         } else {
5205                 struct netdev_hw_addr *ha;
5206
5207                 rx_mode = AcceptBroadcast | AcceptMyPhys;
5208                 mc_filter[1] = mc_filter[0] = 0;
5209                 netdev_for_each_mc_addr(ha, dev) {
5210                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
5211                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5212                         rx_mode |= AcceptMulticast;
5213                 }
5214         }
5215
5216         spin_lock_irqsave(&tp->lock, flags);
5217
5218         tmp = rtl8169_rx_config | rx_mode |
5219               (RTL_R32(RxConfig) & RTL_RX_CONFIG_MASK);
5220
5221         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
5222                 u32 data = mc_filter[0];
5223
5224                 mc_filter[0] = swab32(mc_filter[1]);
5225                 mc_filter[1] = swab32(data);
5226         }
5227
5228         RTL_W32(MAR0 + 4, mc_filter[1]);
5229         RTL_W32(MAR0 + 0, mc_filter[0]);
5230
5231         RTL_W32(RxConfig, tmp);
5232
5233         spin_unlock_irqrestore(&tp->lock, flags);
5234 }
5235
5236 /**
5237  *  rtl8169_get_stats - Get rtl8169 read/write statistics
5238  *  @dev: The Ethernet Device to get statistics for
5239  *
5240  *  Get TX/RX statistics for rtl8169
5241  */
5242 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
5243 {
5244         struct rtl8169_private *tp = netdev_priv(dev);
5245         void __iomem *ioaddr = tp->mmio_addr;
5246         unsigned long flags;
5247
5248         if (netif_running(dev)) {
5249                 spin_lock_irqsave(&tp->lock, flags);
5250                 rtl8169_rx_missed(dev, ioaddr);
5251                 spin_unlock_irqrestore(&tp->lock, flags);
5252         }
5253
5254         return &dev->stats;
5255 }
5256
5257 static void rtl8169_net_suspend(struct net_device *dev)
5258 {
5259         struct rtl8169_private *tp = netdev_priv(dev);
5260
5261         if (!netif_running(dev))
5262                 return;
5263
5264         rtl_pll_power_down(tp);
5265
5266         netif_device_detach(dev);
5267         netif_stop_queue(dev);
5268 }
5269
5270 #ifdef CONFIG_PM
5271
5272 static int rtl8169_suspend(struct device *device)
5273 {
5274         struct pci_dev *pdev = to_pci_dev(device);
5275         struct net_device *dev = pci_get_drvdata(pdev);
5276
5277         rtl8169_net_suspend(dev);
5278
5279         return 0;
5280 }
5281
5282 static void __rtl8169_resume(struct net_device *dev)
5283 {
5284         struct rtl8169_private *tp = netdev_priv(dev);
5285
5286         netif_device_attach(dev);
5287
5288         rtl_pll_power_up(tp);
5289
5290         rtl8169_schedule_work(dev, rtl8169_reset_task);
5291 }
5292
5293 static int rtl8169_resume(struct device *device)
5294 {
5295         struct pci_dev *pdev = to_pci_dev(device);
5296         struct net_device *dev = pci_get_drvdata(pdev);
5297         struct rtl8169_private *tp = netdev_priv(dev);
5298
5299         rtl8169_init_phy(dev, tp);
5300
5301         if (netif_running(dev))
5302                 __rtl8169_resume(dev);
5303
5304         return 0;
5305 }
5306
5307 static int rtl8169_runtime_suspend(struct device *device)
5308 {
5309         struct pci_dev *pdev = to_pci_dev(device);
5310         struct net_device *dev = pci_get_drvdata(pdev);
5311         struct rtl8169_private *tp = netdev_priv(dev);
5312
5313         if (!tp->TxDescArray)
5314                 return 0;
5315
5316         spin_lock_irq(&tp->lock);
5317         tp->saved_wolopts = __rtl8169_get_wol(tp);
5318         __rtl8169_set_wol(tp, WAKE_ANY);
5319         spin_unlock_irq(&tp->lock);
5320
5321         rtl8169_net_suspend(dev);
5322
5323         return 0;
5324 }
5325
5326 static int rtl8169_runtime_resume(struct device *device)
5327 {
5328         struct pci_dev *pdev = to_pci_dev(device);
5329         struct net_device *dev = pci_get_drvdata(pdev);
5330         struct rtl8169_private *tp = netdev_priv(dev);
5331
5332         if (!tp->TxDescArray)
5333                 return 0;
5334
5335         spin_lock_irq(&tp->lock);
5336         __rtl8169_set_wol(tp, tp->saved_wolopts);
5337         tp->saved_wolopts = 0;
5338         spin_unlock_irq(&tp->lock);
5339
5340         rtl8169_init_phy(dev, tp);
5341
5342         __rtl8169_resume(dev);
5343
5344         return 0;
5345 }
5346
5347 static int rtl8169_runtime_idle(struct device *device)
5348 {
5349         struct pci_dev *pdev = to_pci_dev(device);
5350         struct net_device *dev = pci_get_drvdata(pdev);
5351         struct rtl8169_private *tp = netdev_priv(dev);
5352
5353         return tp->TxDescArray ? -EBUSY : 0;
5354 }
5355
5356 static const struct dev_pm_ops rtl8169_pm_ops = {
5357         .suspend                = rtl8169_suspend,
5358         .resume                 = rtl8169_resume,
5359         .freeze                 = rtl8169_suspend,
5360         .thaw                   = rtl8169_resume,
5361         .poweroff               = rtl8169_suspend,
5362         .restore                = rtl8169_resume,
5363         .runtime_suspend        = rtl8169_runtime_suspend,
5364         .runtime_resume         = rtl8169_runtime_resume,
5365         .runtime_idle           = rtl8169_runtime_idle,
5366 };
5367
5368 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
5369
5370 #else /* !CONFIG_PM */
5371
5372 #define RTL8169_PM_OPS  NULL
5373
5374 #endif /* !CONFIG_PM */
5375
5376 static void rtl_shutdown(struct pci_dev *pdev)
5377 {
5378         struct net_device *dev = pci_get_drvdata(pdev);
5379         struct rtl8169_private *tp = netdev_priv(dev);
5380         void __iomem *ioaddr = tp->mmio_addr;
5381
5382         rtl8169_net_suspend(dev);
5383
5384         /* Restore original MAC address */
5385         rtl_rar_set(tp, dev->perm_addr);
5386
5387         spin_lock_irq(&tp->lock);
5388
5389         rtl8169_asic_down(ioaddr);
5390
5391         spin_unlock_irq(&tp->lock);
5392
5393         if (system_state == SYSTEM_POWER_OFF) {
5394                 /* WoL fails with 8168b when the receiver is disabled. */
5395                 if ((tp->mac_version == RTL_GIGA_MAC_VER_11 ||
5396                      tp->mac_version == RTL_GIGA_MAC_VER_12 ||
5397                      tp->mac_version == RTL_GIGA_MAC_VER_17) &&
5398                     (tp->features & RTL_FEATURE_WOL)) {
5399                         pci_clear_master(pdev);
5400
5401                         RTL_W8(ChipCmd, CmdRxEnb);
5402                         /* PCI commit */
5403                         RTL_R8(ChipCmd);
5404                 }
5405
5406                 pci_wake_from_d3(pdev, true);
5407                 pci_set_power_state(pdev, PCI_D3hot);
5408         }
5409 }
5410
5411 static struct pci_driver rtl8169_pci_driver = {
5412         .name           = MODULENAME,
5413         .id_table       = rtl8169_pci_tbl,
5414         .probe          = rtl8169_init_one,
5415         .remove         = __devexit_p(rtl8169_remove_one),
5416         .shutdown       = rtl_shutdown,
5417         .driver.pm      = RTL8169_PM_OPS,
5418 };
5419
5420 static int __init rtl8169_init_module(void)
5421 {
5422         return pci_register_driver(&rtl8169_pci_driver);
5423 }
5424
5425 static void __exit rtl8169_cleanup_module(void)
5426 {
5427         pci_unregister_driver(&rtl8169_pci_driver);
5428 }
5429
5430 module_init(rtl8169_init_module);
5431 module_exit(rtl8169_cleanup_module);