drivers/net/sfc/falcon.c

   1 /****************************************************************************
   2  * Driver for Solarflare Solarstorm network controllers and boards
   3  * Copyright 2005-2006 Fen Systems Ltd.
   4  * Copyright 2006-2009 Solarflare Communications Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published
   8  * by the Free Software Foundation, incorporated herein by reference.
   9  */
  10
  11 #include <linux/bitops.h>
  12 #include <linux/delay.h>
  13 #include <linux/pci.h>
  14 #include <linux/module.h>
  15 #include <linux/seq_file.h>
  16 #include <linux/i2c.h>
  17 #include <linux/mii.h>
  18 #include <linux/slab.h>
  19 #include "net_driver.h"
  20 #include "bitfield.h"
  21 #include "efx.h"
  22 #include "mac.h"
  23 #include "spi.h"
  24 #include "nic.h"
  25 #include "regs.h"
  26 #include "io.h"
  27 #include "mdio_10g.h"
  28 #include "phy.h"
  29 #include "workarounds.h"
  30
  31 /* Hardware control for SFC4000 (aka Falcon). */
  32
  33 static const unsigned int
  34 /* "Large" EEPROM device: Atmel AT25640 or similar
  35  * 8 KB, 16-bit address, 32 B write block */
  36 large_eeprom_type = ((13 << SPI_DEV_TYPE_SIZE_LBN)
  37                      | (2 << SPI_DEV_TYPE_ADDR_LEN_LBN)
  38                      | (5 << SPI_DEV_TYPE_BLOCK_SIZE_LBN)),
  39 /* Default flash device: Atmel AT25F1024
  40  * 128 KB, 24-bit address, 32 KB erase block, 256 B write block */
  41 default_flash_type = ((17 << SPI_DEV_TYPE_SIZE_LBN)
  42                       | (3 << SPI_DEV_TYPE_ADDR_LEN_LBN)
  43                       | (0x52 << SPI_DEV_TYPE_ERASE_CMD_LBN)
  44                       | (15 << SPI_DEV_TYPE_ERASE_SIZE_LBN)
  45                       | (8 << SPI_DEV_TYPE_BLOCK_SIZE_LBN));
  46
  47 /**************************************************************************
  48  *
  49  * I2C bus - this is a bit-bashing interface using GPIO pins
  50  * Note that it uses the output enables to tristate the outputs
  51  * SDA is the data pin and SCL is the clock
  52  *
  53  **************************************************************************
  54  */
  55 static void falcon_setsda(void *data, int state)
  56 {
  57         struct efx_nic *efx = (struct efx_nic *)data;
  58         efx_oword_t reg;
  59
  60         efx_reado(efx, &reg, FR_AB_GPIO_CTL);
  61         EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO3_OEN, !state);
  62         efx_writeo(efx, &reg, FR_AB_GPIO_CTL);
  63 }
  64
  65 static void falcon_setscl(void *data, int state)
  66 {
  67         struct efx_nic *efx = (struct efx_nic *)data;
  68         efx_oword_t reg;
  69
  70         efx_reado(efx, &reg, FR_AB_GPIO_CTL);
  71         EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO0_OEN, !state);
  72         efx_writeo(efx, &reg, FR_AB_GPIO_CTL);
  73 }
  74
  75 static int falcon_getsda(void *data)
  76 {
  77         struct efx_nic *efx = (struct efx_nic *)data;
  78         efx_oword_t reg;
  79
  80         efx_reado(efx, &reg, FR_AB_GPIO_CTL);
  81         return EFX_OWORD_FIELD(reg, FRF_AB_GPIO3_IN);
  82 }
  83
  84 static int falcon_getscl(void *data)
  85 {
  86         struct efx_nic *efx = (struct efx_nic *)data;
  87         efx_oword_t reg;
  88
  89         efx_reado(efx, &reg, FR_AB_GPIO_CTL);
  90         return EFX_OWORD_FIELD(reg, FRF_AB_GPIO0_IN);
  91 }
  92
  93 static struct i2c_algo_bit_data falcon_i2c_bit_operations = {
  94         .setsda         = falcon_setsda,
  95         .setscl         = falcon_setscl,
  96         .getsda         = falcon_getsda,
  97         .getscl         = falcon_getscl,
  98         .udelay         = 5,
  99         /* Wait up to 50 ms for slave to let us pull SCL high */
 100         .timeout        = DIV_ROUND_UP(HZ, 20),
 101 };
 102
 103 static void falcon_push_irq_moderation(struct efx_channel *channel)
 104 {
 105         efx_dword_t timer_cmd;
 106         struct efx_nic *efx = channel->efx;
 107
 108         /* Set timer register */
 109         if (channel->irq_moderation) {
 110                 EFX_POPULATE_DWORD_2(timer_cmd,
 111                                      FRF_AB_TC_TIMER_MODE,
 112                                      FFE_BB_TIMER_MODE_INT_HLDOFF,
 113                                      FRF_AB_TC_TIMER_VAL,
 114                                      channel->irq_moderation - 1);
 115         } else {
 116                 EFX_POPULATE_DWORD_2(timer_cmd,
 117                                      FRF_AB_TC_TIMER_MODE,
 118                                      FFE_BB_TIMER_MODE_DIS,
 119                                      FRF_AB_TC_TIMER_VAL, 0);
 120         }
 121         BUILD_BUG_ON(FR_AA_TIMER_COMMAND_KER != FR_BZ_TIMER_COMMAND_P0);
 122         efx_writed_page_locked(efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0,
 123                                channel->channel);
 124 }
 125
 126 static void falcon_deconfigure_mac_wrapper(struct efx_nic *efx);
 127
 128 static void falcon_prepare_flush(struct efx_nic *efx)
 129 {
 130         falcon_deconfigure_mac_wrapper(efx);
 131
 132         /* Wait for the tx and rx fifo's to get to the next packet boundary
 133          * (~1ms without back-pressure), then to drain the remainder of the
 134          * fifo's at data path speeds (negligible), with a healthy margin. */
 135         msleep(10);
 136 }
 137
 138 /* Acknowledge a legacy interrupt from Falcon
 139  *
 140  * This acknowledges a legacy (not MSI) interrupt via INT_ACK_KER_REG.
 141  *
 142  * Due to SFC bug 3706 (silicon revision <=A1) reads can be duplicated in the
 143  * BIU. Interrupt acknowledge is read sensitive so must write instead
 144  * (then read to ensure the BIU collector is flushed)
 145  *
 146  * NB most hardware supports MSI interrupts
 147  */
 148 inline void falcon_irq_ack_a1(struct efx_nic *efx)
 149 {
 150         efx_dword_t reg;
 151
 152         EFX_POPULATE_DWORD_1(reg, FRF_AA_INT_ACK_KER_FIELD, 0xb7eb7e);
 153         efx_writed(efx, &reg, FR_AA_INT_ACK_KER);
 154         efx_readd(efx, &reg, FR_AA_WORK_AROUND_BROKEN_PCI_READS);
 155 }
 156
 157
 158 irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id)
 159 {
 160         struct efx_nic *efx = dev_id;
 161         efx_oword_t *int_ker = efx->irq_status.addr;
 162         struct efx_channel *channel;
 163         int syserr;
 164         int queues;
 165
 166         /* Check to see if this is our interrupt.  If it isn't, we
 167          * exit without having touched the hardware.
 168          */
 169         if (unlikely(EFX_OWORD_IS_ZERO(*int_ker))) {
 170                 EFX_TRACE(efx, "IRQ %d on CPU %d not for me\n", irq,
 171                           raw_smp_processor_id());
 172                 return IRQ_NONE;
 173         }
 174         efx->last_irq_cpu = raw_smp_processor_id();
 175         EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
 176                   irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
 177
 178         /* Determine interrupting queues, clear interrupt status
 179          * register and acknowledge the device interrupt.
 180          */
 181         BUILD_BUG_ON(FSF_AZ_NET_IVEC_INT_Q_WIDTH > EFX_MAX_CHANNELS);
 182         queues = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_INT_Q);
 183
 184         /* Check to see if we have a serious error condition */
 185         if (queues & (1U << efx->fatal_irq_level)) {
 186                 syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
 187                 if (unlikely(syserr))
 188                         return efx_nic_fatal_interrupt(efx);
 189         }
 190
 191         EFX_ZERO_OWORD(*int_ker);
 192         wmb(); /* Ensure the vector is cleared before interrupt ack */
 193         falcon_irq_ack_a1(efx);
 194
 195         /* Schedule processing of any interrupting queues */
 196         channel = &efx->channel[0];
 197         while (queues) {
 198                 if (queues & 0x01)
 199                         efx_schedule_channel(channel);
 200                 channel++;
 201                 queues >>= 1;
 202         }
 203
 204         return IRQ_HANDLED;
 205 }
 206 /**************************************************************************
 207  *
 208  * EEPROM/flash
 209  *
 210  **************************************************************************
 211  */
 212
 213 #define FALCON_SPI_MAX_LEN sizeof(efx_oword_t)
 214
 215 static int falcon_spi_poll(struct efx_nic *efx)
 216 {
 217         efx_oword_t reg;
 218         efx_reado(efx, &reg, FR_AB_EE_SPI_HCMD);
 219         return EFX_OWORD_FIELD(reg, FRF_AB_EE_SPI_HCMD_CMD_EN) ? -EBUSY : 0;
 220 }
 221
 222 /* Wait for SPI command completion */
 223 static int falcon_spi_wait(struct efx_nic *efx)
 224 {
 225         /* Most commands will finish quickly, so we start polling at
 226          * very short intervals.  Sometimes the command may have to
 227          * wait for VPD or expansion ROM access outside of our
 228          * control, so we allow up to 100 ms. */
 229         unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 10);
 230         int i;
 231
 232         for (i = 0; i < 10; i++) {
 233                 if (!falcon_spi_poll(efx))
 234                         return 0;
 235                 udelay(10);
 236         }
 237
 238         for (;;) {
 239                 if (!falcon_spi_poll(efx))
 240                         return 0;
 241                 if (time_after_eq(jiffies, timeout)) {
 242                         EFX_ERR(efx, "timed out waiting for SPI\n");
 243                         return -ETIMEDOUT;
 244                 }
 245                 schedule_timeout_uninterruptible(1);
 246         }
 247 }
 248
 249 int falcon_spi_cmd(struct efx_nic *efx, const struct efx_spi_device *spi,
 250                    unsigned int command, int address,
 251                    const void *in, void *out, size_t len)
 252 {
 253         bool addressed = (address >= 0);
 254         bool reading = (out != NULL);
 255         efx_oword_t reg;
 256         int rc;
 257
 258         /* Input validation */
 259         if (len > FALCON_SPI_MAX_LEN)
 260                 return -EINVAL;
 261         BUG_ON(!mutex_is_locked(&efx->spi_lock));
 262
 263         /* Check that previous command is not still running */
 264         rc = falcon_spi_poll(efx);
 265         if (rc)
 266                 return rc;
 267
 268         /* Program address register, if we have an address */
 269         if (addressed) {
 270                 EFX_POPULATE_OWORD_1(reg, FRF_AB_EE_SPI_HADR_ADR, address);
 271                 efx_writeo(efx, &reg, FR_AB_EE_SPI_HADR);
 272         }
 273
 274         /* Program data register, if we have data */
 275         if (in != NULL) {
 276                 memcpy(&reg, in, len);
 277                 efx_writeo(efx, &reg, FR_AB_EE_SPI_HDATA);
 278         }
 279
 280         /* Issue read/write command */
 281         EFX_POPULATE_OWORD_7(reg,
 282                              FRF_AB_EE_SPI_HCMD_CMD_EN, 1,
 283                              FRF_AB_EE_SPI_HCMD_SF_SEL, spi->device_id,
 284                              FRF_AB_EE_SPI_HCMD_DABCNT, len,
 285                              FRF_AB_EE_SPI_HCMD_READ, reading,
 286                              FRF_AB_EE_SPI_HCMD_DUBCNT, 0,
 287                              FRF_AB_EE_SPI_HCMD_ADBCNT,
 288                              (addressed ? spi->addr_len : 0),
 289                              FRF_AB_EE_SPI_HCMD_ENC, command);
 290         efx_writeo(efx, &reg, FR_AB_EE_SPI_HCMD);
 291
 292         /* Wait for read/write to complete */
 293         rc = falcon_spi_wait(efx);
 294         if (rc)
 295                 return rc;
 296
 297         /* Read data */
 298         if (out != NULL) {
 299                 efx_reado(efx, &reg, FR_AB_EE_SPI_HDATA);
 300                 memcpy(out, &reg, len);
 301         }
 302
 303         return 0;
 304 }
 305
 306 static size_t
 307 falcon_spi_write_limit(const struct efx_spi_device *spi, size_t start)
 308 {
 309         return min(FALCON_SPI_MAX_LEN,
 310                    (spi->block_size - (start & (spi->block_size - 1))));
 311 }
 312
 313 static inline u8
 314 efx_spi_munge_command(const struct efx_spi_device *spi,
 315                       const u8 command, const unsigned int address)
 316 {
 317         return command | (((address >> 8) & spi->munge_address) << 3);
 318 }
 319
 320 /* Wait up to 10 ms for buffered write completion */
 321 int
 322 falcon_spi_wait_write(struct efx_nic *efx, const struct efx_spi_device *spi)
 323 {
 324         unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 100);
 325         u8 status;
 326         int rc;
 327
 328         for (;;) {
 329                 rc = falcon_spi_cmd(efx, spi, SPI_RDSR, -1, NULL,
 330                                     &status, sizeof(status));
 331                 if (rc)
 332                         return rc;
 333                 if (!(status & SPI_STATUS_NRDY))
 334                         return 0;
 335                 if (time_after_eq(jiffies, timeout)) {
 336                         EFX_ERR(efx, "SPI write timeout on device %d"
 337                                 " last status=0x%02x\n",
 338                                 spi->device_id, status);
 339                         return -ETIMEDOUT;
 340                 }
 341                 schedule_timeout_uninterruptible(1);
 342         }
 343 }
 344
 345 int falcon_spi_read(struct efx_nic *efx, const struct efx_spi_device *spi,
 346                     loff_t start, size_t len, size_t *retlen, u8 *buffer)
 347 {
 348         size_t block_len, pos = 0;
 349         unsigned int command;
 350         int rc = 0;
 351
 352         while (pos < len) {
 353                 block_len = min(len - pos, FALCON_SPI_MAX_LEN);
 354
 355                 command = efx_spi_munge_command(spi, SPI_READ, start + pos);
 356                 rc = falcon_spi_cmd(efx, spi, command, start + pos, NULL,
 357                                     buffer + pos, block_len);
 358                 if (rc)
 359                         break;
 360                 pos += block_len;
 361
 362                 /* Avoid locking up the system */
 363                 cond_resched();
 364                 if (signal_pending(current)) {
 365                         rc = -EINTR;
 366                         break;
 367                 }
 368         }
 369
 370         if (retlen)
 371                 *retlen = pos;
 372         return rc;
 373 }
 374
 375 int
 376 falcon_spi_write(struct efx_nic *efx, const struct efx_spi_device *spi,
 377                  loff_t start, size_t len, size_t *retlen, const u8 *buffer)
 378 {
 379         u8 verify_buffer[FALCON_SPI_MAX_LEN];
 380         size_t block_len, pos = 0;
 381         unsigned int command;
 382         int rc = 0;
 383
 384         while (pos < len) {
 385                 rc = falcon_spi_cmd(efx, spi, SPI_WREN, -1, NULL, NULL, 0);
 386                 if (rc)
 387                         break;
 388
 389                 block_len = min(len - pos,
 390                                 falcon_spi_write_limit(spi, start + pos));
 391                 command = efx_spi_munge_command(spi, SPI_WRITE, start + pos);
 392                 rc = falcon_spi_cmd(efx, spi, command, start + pos,
 393                                     buffer + pos, NULL, block_len);
 394                 if (rc)
 395                         break;
 396
 397                 rc = falcon_spi_wait_write(efx, spi);
 398                 if (rc)
 399                         break;
 400
 401                 command = efx_spi_munge_command(spi, SPI_READ, start + pos);
 402                 rc = falcon_spi_cmd(efx, spi, command, start + pos,
 403                                     NULL, verify_buffer, block_len);
 404                 if (memcmp(verify_buffer, buffer + pos, block_len)) {
 405                         rc = -EIO;
 406                         break;
 407                 }
 408
 409                 pos += block_len;
 410
 411                 /* Avoid locking up the system */
 412                 cond_resched();
 413                 if (signal_pending(current)) {
 414                         rc = -EINTR;
 415                         break;
 416                 }
 417         }
 418
 419         if (retlen)
 420                 *retlen = pos;
 421         return rc;
 422 }
 423
 424 /**************************************************************************
 425  *
 426  * MAC wrapper
 427  *
 428  **************************************************************************
 429  */
 430
 431 static void falcon_push_multicast_hash(struct efx_nic *efx)
 432 {
 433         union efx_multicast_hash *mc_hash = &efx->multicast_hash;
 434
 435         WARN_ON(!mutex_is_locked(&efx->mac_lock));
 436
 437         efx_writeo(efx, &mc_hash->oword[0], FR_AB_MAC_MC_HASH_REG0);
 438         efx_writeo(efx, &mc_hash->oword[1], FR_AB_MAC_MC_HASH_REG1);
 439 }
 440
 441 static void falcon_reset_macs(struct efx_nic *efx)
 442 {
 443         struct falcon_nic_data *nic_data = efx->nic_data;
 444         efx_oword_t reg, mac_ctrl;
 445         int count;
 446
 447         if (efx_nic_rev(efx) < EFX_REV_FALCON_B0) {
 448                 /* It's not safe to use GLB_CTL_REG to reset the
 449                  * macs, so instead use the internal MAC resets
 450                  */
 451                 if (!EFX_IS10G(efx)) {
 452                         EFX_POPULATE_OWORD_1(reg, FRF_AB_GM_SW_RST, 1);
 453                         efx_writeo(efx, &reg, FR_AB_GM_CFG1);
 454                         udelay(1000);
 455
 456                         EFX_POPULATE_OWORD_1(reg, FRF_AB_GM_SW_RST, 0);
 457                         efx_writeo(efx, &reg, FR_AB_GM_CFG1);
 458                         udelay(1000);
 459                         return;
 460                 } else {
 461                         EFX_POPULATE_OWORD_1(reg, FRF_AB_XM_CORE_RST, 1);
 462                         efx_writeo(efx, &reg, FR_AB_XM_GLB_CFG);
 463
 464                         for (count = 0; count < 10000; count++) {
 465                                 efx_reado(efx, &reg, FR_AB_XM_GLB_CFG);
 466                                 if (EFX_OWORD_FIELD(reg, FRF_AB_XM_CORE_RST) ==
 467                                     0)
 468                                         return;
 469                                 udelay(10);
 470                         }
 471
 472                         EFX_ERR(efx, "timed out waiting for XMAC core reset\n");
 473                 }
 474         }
 475
 476         /* Mac stats will fail whist the TX fifo is draining */
 477         WARN_ON(nic_data->stats_disable_count == 0);
 478
 479         efx_reado(efx, &mac_ctrl, FR_AB_MAC_CTRL);
 480         EFX_SET_OWORD_FIELD(mac_ctrl, FRF_BB_TXFIFO_DRAIN_EN, 1);
 481         efx_writeo(efx, &mac_ctrl, FR_AB_MAC_CTRL);
 482
 483         efx_reado(efx, &reg, FR_AB_GLB_CTL);
 484         EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGTX, 1);
 485         EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGRX, 1);
 486         EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_EM, 1);
 487         efx_writeo(efx, &reg, FR_AB_GLB_CTL);
 488
 489         count = 0;
 490         while (1) {
 491                 efx_reado(efx, &reg, FR_AB_GLB_CTL);
 492                 if (!EFX_OWORD_FIELD(reg, FRF_AB_RST_XGTX) &&
 493                     !EFX_OWORD_FIELD(reg, FRF_AB_RST_XGRX) &&
 494                     !EFX_OWORD_FIELD(reg, FRF_AB_RST_EM)) {
 495                         EFX_LOG(efx, "Completed MAC reset after %d loops\n",
 496                                 count);
 497                         break;
 498                 }
 499                 if (count > 20) {
 500                         EFX_ERR(efx, "MAC reset failed\n");
 501                         break;
 502                 }
 503                 count++;
 504                 udelay(10);
 505         }
 506
 507         /* Ensure the correct MAC is selected before statistics
 508          * are re-enabled by the caller */
 509         efx_writeo(efx, &mac_ctrl, FR_AB_MAC_CTRL);
 510 }
 511
 512 void falcon_drain_tx_fifo(struct efx_nic *efx)
 513 {
 514         efx_oword_t reg;
 515
 516         if ((efx_nic_rev(efx) < EFX_REV_FALCON_B0) ||
 517             (efx->loopback_mode != LOOPBACK_NONE))
 518                 return;
 519
 520         efx_reado(efx, &reg, FR_AB_MAC_CTRL);
 521         /* There is no point in draining more than once */
 522         if (EFX_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN))
 523                 return;
 524
 525         falcon_reset_macs(efx);
 526 }
 527
 528 static void falcon_deconfigure_mac_wrapper(struct efx_nic *efx)
 529 {
 530         efx_oword_t reg;
 531
 532         if (efx_nic_rev(efx) < EFX_REV_FALCON_B0)
 533                 return;
 534
 535         /* Isolate the MAC -> RX */
 536         efx_reado(efx, &reg, FR_AZ_RX_CFG);
 537         EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 0);
 538         efx_writeo(efx, &reg, FR_AZ_RX_CFG);
 539
 540         /* Isolate TX -> MAC */
 541         falcon_drain_tx_fifo(efx);
 542 }
 543
 544 void falcon_reconfigure_mac_wrapper(struct efx_nic *efx)
 545 {
 546         struct efx_link_state *link_state = &efx->link_state;
 547         efx_oword_t reg;
 548         int link_speed;
 549
 550         switch (link_state->speed) {
 551         case 10000: link_speed = 3; break;
 552         case 1000:  link_speed = 2; break;
 553         case 100:   link_speed = 1; break;
 554         default:    link_speed = 0; break;
 555         }
 556         /* MAC_LINK_STATUS controls MAC backpressure but doesn't work
 557          * as advertised.  Disable to ensure packets are not
 558          * indefinitely held and TX queue can be flushed at any point
 559          * while the link is down. */
 560         EFX_POPULATE_OWORD_5(reg,
 561                              FRF_AB_MAC_XOFF_VAL, 0xffff /* max pause time */,
 562                              FRF_AB_MAC_BCAD_ACPT, 1,
 563                              FRF_AB_MAC_UC_PROM, efx->promiscuous,
 564                              FRF_AB_MAC_LINK_STATUS, 1, /* always set */
 565                              FRF_AB_MAC_SPEED, link_speed);
 566         /* On B0, MAC backpressure can be disabled and packets get
 567          * discarded. */
 568         if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
 569                 EFX_SET_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN,
 570                                     !link_state->up);
 571         }
 572
 573         efx_writeo(efx, &reg, FR_AB_MAC_CTRL);
 574
 575         /* Restore the multicast hash registers. */
 576         falcon_push_multicast_hash(efx);
 577
 578         efx_reado(efx, &reg, FR_AZ_RX_CFG);
 579         /* Enable XOFF signal from RX FIFO (we enabled it during NIC
 580          * initialisation but it may read back as 0) */
 581         EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, 1);
 582         /* Unisolate the MAC -> RX */
 583         if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
 584                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1);
 585         efx_writeo(efx, &reg, FR_AZ_RX_CFG);
 586 }
 587
 588 static void falcon_stats_request(struct efx_nic *efx)
 589 {
 590         struct falcon_nic_data *nic_data = efx->nic_data;
 591         efx_oword_t reg;
 592
 593         WARN_ON(nic_data->stats_pending);
 594         WARN_ON(nic_data->stats_disable_count);
 595
 596         if (nic_data->stats_dma_done == NULL)
 597                 return; /* no mac selected */
 598
 599         *nic_data->stats_dma_done = FALCON_STATS_NOT_DONE;
 600         nic_data->stats_pending = true;
 601         wmb(); /* ensure done flag is clear */
 602
 603         /* Initiate DMA transfer of stats */
 604         EFX_POPULATE_OWORD_2(reg,
 605                              FRF_AB_MAC_STAT_DMA_CMD, 1,
 606                              FRF_AB_MAC_STAT_DMA_ADR,
 607                              efx->stats_buffer.dma_addr);
 608         efx_writeo(efx, &reg, FR_AB_MAC_STAT_DMA);
 609
 610         mod_timer(&nic_data->stats_timer, round_jiffies_up(jiffies + HZ / 2));
 611 }
 612
 613 static void falcon_stats_complete(struct efx_nic *efx)
 614 {
 615         struct falcon_nic_data *nic_data = efx->nic_data;
 616
 617         if (!nic_data->stats_pending)
 618                 return;
 619
 620         nic_data->stats_pending = 0;
 621         if (*nic_data->stats_dma_done == FALCON_STATS_DONE) {
 622                 rmb(); /* read the done flag before the stats */
 623                 efx->mac_op->update_stats(efx);
 624         } else {
 625                 EFX_ERR(efx, "timed out waiting for statistics\n");
 626         }
 627 }
 628
 629 static void falcon_stats_timer_func(unsigned long context)
 630 {
 631         struct efx_nic *efx = (struct efx_nic *)context;
 632         struct falcon_nic_data *nic_data = efx->nic_data;
 633
 634         spin_lock(&efx->stats_lock);
 635
 636         falcon_stats_complete(efx);
 637         if (nic_data->stats_disable_count == 0)
 638                 falcon_stats_request(efx);
 639
 640         spin_unlock(&efx->stats_lock);
 641 }
 642
 643 static void falcon_switch_mac(struct efx_nic *efx);
 644
 645 static bool falcon_loopback_link_poll(struct efx_nic *efx)
 646 {
 647         struct efx_link_state old_state = efx->link_state;
 648
 649         WARN_ON(!mutex_is_locked(&efx->mac_lock));
 650         WARN_ON(!LOOPBACK_INTERNAL(efx));
 651
 652         efx->link_state.fd = true;
 653         efx->link_state.fc = efx->wanted_fc;
 654         efx->link_state.up = true;
 655
 656         if (efx->loopback_mode == LOOPBACK_GMAC)
 657                 efx->link_state.speed = 1000;
 658         else
 659                 efx->link_state.speed = 10000;
 660
 661         return !efx_link_state_equal(&efx->link_state, &old_state);
 662 }
 663
 664 static int falcon_reconfigure_port(struct efx_nic *efx)
 665 {
 666         int rc;
 667
 668         WARN_ON(efx_nic_rev(efx) > EFX_REV_FALCON_B0);
 669
 670         /* Poll the PHY link state *before* reconfiguring it. This means we
 671          * will pick up the correct speed (in loopback) to select the correct
 672          * MAC.
 673          */
 674         if (LOOPBACK_INTERNAL(efx))
 675                 falcon_loopback_link_poll(efx);
 676         else
 677                 efx->phy_op->poll(efx);
 678
 679         falcon_stop_nic_stats(efx);
 680         falcon_deconfigure_mac_wrapper(efx);
 681
 682         falcon_switch_mac(efx);
 683
 684         efx->phy_op->reconfigure(efx);
 685         rc = efx->mac_op->reconfigure(efx);
 686         BUG_ON(rc);
 687
 688         falcon_start_nic_stats(efx);
 689
 690         /* Synchronise efx->link_state with the kernel */
 691         efx_link_status_changed(efx);
 692
 693         return 0;
 694 }
 695
 696 /**************************************************************************
 697  *
 698  * PHY access via GMII
 699  *
 700  **************************************************************************
 701  */
 702
 703 /* Wait for GMII access to complete */
 704 static int falcon_gmii_wait(struct efx_nic *efx)
 705 {
 706         efx_oword_t md_stat;
 707         int count;
 708
 709         /* wait upto 50ms - taken max from datasheet */
 710         for (count = 0; count < 5000; count++) {
 711                 efx_reado(efx, &md_stat, FR_AB_MD_STAT);
 712                 if (EFX_OWORD_FIELD(md_stat, FRF_AB_MD_BSY) == 0) {
 713                         if (EFX_OWORD_FIELD(md_stat, FRF_AB_MD_LNFL) != 0 ||
 714                             EFX_OWORD_FIELD(md_stat, FRF_AB_MD_BSERR) != 0) {
 715                                 EFX_ERR(efx, "error from GMII access "
 716                                         EFX_OWORD_FMT"\n",
 717                                         EFX_OWORD_VAL(md_stat));
 718                                 return -EIO;
 719                         }
 720                         return 0;
 721                 }
 722                 udelay(10);
 723         }
 724         EFX_ERR(efx, "timed out waiting for GMII\n");
 725         return -ETIMEDOUT;
 726 }
 727
 728 /* Write an MDIO register of a PHY connected to Falcon. */
 729 static int falcon_mdio_write(struct net_device *net_dev,
 730                              int prtad, int devad, u16 addr, u16 value)
 731 {
 732         struct efx_nic *efx = netdev_priv(net_dev);
 733         efx_oword_t reg;
 734         int rc;
 735
 736         EFX_REGDUMP(efx, "writing MDIO %d register %d.%d with 0x%04x\n",
 737                     prtad, devad, addr, value);
 738
 739         mutex_lock(&efx->mdio_lock);
 740
 741         /* Check MDIO not currently being accessed */
 742         rc = falcon_gmii_wait(efx);
 743         if (rc)
 744                 goto out;
 745
 746         /* Write the address/ID register */
 747         EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr);
 748         efx_writeo(efx, &reg, FR_AB_MD_PHY_ADR);
 749
 750         EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad,
 751                              FRF_AB_MD_DEV_ADR, devad);
 752         efx_writeo(efx, &reg, FR_AB_MD_ID);
 753
 754         /* Write data */
 755         EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_TXD, value);
 756         efx_writeo(efx, &reg, FR_AB_MD_TXD);
 757
 758         EFX_POPULATE_OWORD_2(reg,
 759                              FRF_AB_MD_WRC, 1,
 760                              FRF_AB_MD_GC, 0);
 761         efx_writeo(efx, &reg, FR_AB_MD_CS);
 762
 763         /* Wait for data to be written */
 764         rc = falcon_gmii_wait(efx);
 765         if (rc) {
 766                 /* Abort the write operation */
 767                 EFX_POPULATE_OWORD_2(reg,
 768                                      FRF_AB_MD_WRC, 0,
 769                                      FRF_AB_MD_GC, 1);
 770                 efx_writeo(efx, &reg, FR_AB_MD_CS);
 771                 udelay(10);
 772         }
 773
 774 out:
 775         mutex_unlock(&efx->mdio_lock);
 776         return rc;
 777 }
 778
 779 /* Read an MDIO register of a PHY connected to Falcon. */
 780 static int falcon_mdio_read(struct net_device *net_dev,
 781                             int prtad, int devad, u16 addr)
 782 {
 783         struct efx_nic *efx = netdev_priv(net_dev);
 784         efx_oword_t reg;
 785         int rc;
 786
 787         mutex_lock(&efx->mdio_lock);
 788
 789         /* Check MDIO not currently being accessed */
 790         rc = falcon_gmii_wait(efx);
 791         if (rc)
 792                 goto out;
 793
 794         EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr);
 795         efx_writeo(efx, &reg, FR_AB_MD_PHY_ADR);
 796
 797         EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad,
 798                              FRF_AB_MD_DEV_ADR, devad);
 799         efx_writeo(efx, &reg, FR_AB_MD_ID);
 800
 801         /* Request data to be read */
 802         EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_RDC, 1, FRF_AB_MD_GC, 0);
 803         efx_writeo(efx, &reg, FR_AB_MD_CS);
 804
 805         /* Wait for data to become available */
 806         rc = falcon_gmii_wait(efx);
 807         if (rc == 0) {
 808                 efx_reado(efx, &reg, FR_AB_MD_RXD);
 809                 rc = EFX_OWORD_FIELD(reg, FRF_AB_MD_RXD);
 810                 EFX_REGDUMP(efx, "read from MDIO %d register %d.%d, got %04x\n",
 811                             prtad, devad, addr, rc);
 812         } else {
 813                 /* Abort the read operation */
 814                 EFX_POPULATE_OWORD_2(reg,
 815                                      FRF_AB_MD_RIC, 0,
 816                                      FRF_AB_MD_GC, 1);
 817                 efx_writeo(efx, &reg, FR_AB_MD_CS);
 818
 819                 EFX_LOG(efx, "read from MDIO %d register %d.%d, got error %d\n",
 820                         prtad, devad, addr, rc);
 821         }
 822
 823 out:
 824         mutex_unlock(&efx->mdio_lock);
 825         return rc;
 826 }
 827
 828 static void falcon_clock_mac(struct efx_nic *efx)
 829 {
 830         unsigned strap_val;
 831         efx_oword_t nic_stat;
 832
 833         /* Configure the NIC generated MAC clock correctly */
 834         efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
 835         strap_val = EFX_IS10G(efx) ? 5 : 3;
 836         if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
 837                 EFX_SET_OWORD_FIELD(nic_stat, FRF_BB_EE_STRAP_EN, 1);
 838                 EFX_SET_OWORD_FIELD(nic_stat, FRF_BB_EE_STRAP, strap_val);
 839                 efx_writeo(efx, &nic_stat, FR_AB_NIC_STAT);
 840         } else {
 841                 /* Falcon A1 does not support 1G/10G speed switching
 842                  * and must not be used with a PHY that does. */
 843                 BUG_ON(EFX_OWORD_FIELD(nic_stat, FRF_AB_STRAP_PINS) !=
 844                        strap_val);
 845         }
 846 }
 847
 848 static void falcon_switch_mac(struct efx_nic *efx)
 849 {
 850         struct efx_mac_operations *old_mac_op = efx->mac_op;
 851         struct falcon_nic_data *nic_data = efx->nic_data;
 852         unsigned int stats_done_offset;
 853
 854         WARN_ON(!mutex_is_locked(&efx->mac_lock));
 855         WARN_ON(nic_data->stats_disable_count == 0);
 856
 857         efx->mac_op = (EFX_IS10G(efx) ?
 858                        &falcon_xmac_operations : &falcon_gmac_operations);
 859
 860         if (EFX_IS10G(efx))
 861                 stats_done_offset = XgDmaDone_offset;
 862         else
 863                 stats_done_offset = GDmaDone_offset;
 864         nic_data->stats_dma_done = efx->stats_buffer.addr + stats_done_offset;
 865
 866         if (old_mac_op == efx->mac_op)
 867                 return;
 868
 869         falcon_clock_mac(efx);
 870
 871         EFX_LOG(efx, "selected %cMAC\n", EFX_IS10G(efx) ? 'X' : 'G');
 872         /* Not all macs support a mac-level link state */
 873         efx->xmac_poll_required = false;
 874         falcon_reset_macs(efx);
 875 }
 876
 877 /* This call is responsible for hooking in the MAC and PHY operations */
 878 static int falcon_probe_port(struct efx_nic *efx)
 879 {
 880         int rc;
 881
 882         switch (efx->phy_type) {
 883         case PHY_TYPE_SFX7101:
 884                 efx->phy_op = &falcon_sfx7101_phy_ops;
 885                 break;
 886         case PHY_TYPE_SFT9001A:
 887         case PHY_TYPE_SFT9001B:
 888                 efx->phy_op = &falcon_sft9001_phy_ops;
 889                 break;
 890         case PHY_TYPE_QT2022C2:
 891         case PHY_TYPE_QT2025C:
 892                 efx->phy_op = &falcon_qt202x_phy_ops;
 893                 break;
 894         default:
 895                 EFX_ERR(efx, "Unknown PHY type %d\n",
 896                         efx->phy_type);
 897                 return -ENODEV;
 898         }
 899
 900         /* Fill out MDIO structure and loopback modes */
 901         efx->mdio.mdio_read = falcon_mdio_read;
 902         efx->mdio.mdio_write = falcon_mdio_write;
 903         rc = efx->phy_op->probe(efx);
 904         if (rc != 0)
 905                 return rc;
 906
 907         /* Initial assumption */
 908         efx->link_state.speed = 10000;
 909         efx->link_state.fd = true;
 910
 911         /* Hardware flow ctrl. FalconA RX FIFO too small for pause generation */
 912         if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
 913                 efx->wanted_fc = EFX_FC_RX | EFX_FC_TX;
 914         else
 915                 efx->wanted_fc = EFX_FC_RX;
 916         if (efx->mdio.mmds & MDIO_DEVS_AN)
 917                 efx->wanted_fc |= EFX_FC_AUTO;
 918
 919         /* Allocate buffer for stats */
 920         rc = efx_nic_alloc_buffer(efx, &efx->stats_buffer,
 921                                   FALCON_MAC_STATS_SIZE);
 922         if (rc)
 923                 return rc;
 924         EFX_LOG(efx, "stats buffer at %llx (virt %p phys %llx)\n",
 925                 (u64)efx->stats_buffer.dma_addr,
 926                 efx->stats_buffer.addr,
 927                 (u64)virt_to_phys(efx->stats_buffer.addr));
 928
 929         return 0;
 930 }
 931
 932 static void falcon_remove_port(struct efx_nic *efx)
 933 {
 934         efx->phy_op->remove(efx);
 935         efx_nic_free_buffer(efx, &efx->stats_buffer);
 936 }
 937
 938 /**************************************************************************
 939  *
 940  * Falcon test code
 941  *
 942  **************************************************************************/
 943
 944 static int
 945 falcon_read_nvram(struct efx_nic *efx, struct falcon_nvconfig *nvconfig_out)
 946 {
 947         struct falcon_nvconfig *nvconfig;
 948         struct efx_spi_device *spi;
 949         void *region;
 950         int rc, magic_num, struct_ver;
 951         __le16 *word, *limit;
 952         u32 csum;
 953
 954         spi = efx->spi_flash ? efx->spi_flash : efx->spi_eeprom;
 955         if (!spi)
 956                 return -EINVAL;
 957
 958         region = kmalloc(FALCON_NVCONFIG_END, GFP_KERNEL);
 959         if (!region)
 960                 return -ENOMEM;
 961         nvconfig = region + FALCON_NVCONFIG_OFFSET;
 962
 963         mutex_lock(&efx->spi_lock);
 964         rc = falcon_spi_read(efx, spi, 0, FALCON_NVCONFIG_END, NULL, region);
 965         mutex_unlock(&efx->spi_lock);
 966         if (rc) {
 967                 EFX_ERR(efx, "Failed to read %s\n",
 968                         efx->spi_flash ? "flash" : "EEPROM");
 969                 rc = -EIO;
 970                 goto out;
 971         }
 972
 973         magic_num = le16_to_cpu(nvconfig->board_magic_num);
 974         struct_ver = le16_to_cpu(nvconfig->board_struct_ver);
 975
 976         rc = -EINVAL;
 977         if (magic_num != FALCON_NVCONFIG_BOARD_MAGIC_NUM) {
 978                 EFX_ERR(efx, "NVRAM bad magic 0x%x\n", magic_num);
 979                 goto out;
 980         }
 981         if (struct_ver < 2) {
 982                 EFX_ERR(efx, "NVRAM has ancient version 0x%x\n", struct_ver);
 983                 goto out;
 984         } else if (struct_ver < 4) {
 985                 word = &nvconfig->board_magic_num;
 986                 limit = (__le16 *) (nvconfig + 1);
 987         } else {
 988                 word = region;
 989                 limit = region + FALCON_NVCONFIG_END;
 990         }
 991         for (csum = 0; word < limit; ++word)
 992                 csum += le16_to_cpu(*word);
 993
 994         if (~csum & 0xffff) {
 995                 EFX_ERR(efx, "NVRAM has incorrect checksum\n");
 996                 goto out;
 997         }
 998
 999         rc = 0;
1000         if (nvconfig_out)
1001                 memcpy(nvconfig_out, nvconfig, sizeof(*nvconfig));
1002
1003  out:
1004         kfree(region);
1005         return rc;
1006 }
1007
1008 static int falcon_test_nvram(struct efx_nic *efx)
1009 {
1010         return falcon_read_nvram(efx, NULL);
1011 }
1012
1013 static const struct efx_nic_register_test falcon_b0_register_tests[] = {
1014         { FR_AZ_ADR_REGION,
1015           EFX_OWORD32(0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF) },
1016         { FR_AZ_RX_CFG,
1017           EFX_OWORD32(0xFFFFFFFE, 0x00017FFF, 0x00000000, 0x00000000) },
1018         { FR_AZ_TX_CFG,
1019           EFX_OWORD32(0x7FFF0037, 0x00000000, 0x00000000, 0x00000000) },
1020         { FR_AZ_TX_RESERVED,
1021           EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
1022         { FR_AB_MAC_CTRL,
1023           EFX_OWORD32(0xFFFF0000, 0x00000000, 0x00000000, 0x00000000) },
1024         { FR_AZ_SRM_TX_DC_CFG,
1025           EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
1026         { FR_AZ_RX_DC_CFG,
1027           EFX_OWORD32(0x0000000F, 0x00000000, 0x00000000, 0x00000000) },
1028         { FR_AZ_RX_DC_PF_WM,
1029           EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
1030         { FR_BZ_DP_CTRL,
1031           EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
1032         { FR_AB_GM_CFG2,
1033           EFX_OWORD32(0x00007337, 0x00000000, 0x00000000, 0x00000000) },
1034         { FR_AB_GMF_CFG0,
1035           EFX_OWORD32(0x00001F1F, 0x00000000, 0x00000000, 0x00000000) },
1036         { FR_AB_XM_GLB_CFG,
1037           EFX_OWORD32(0x00000C68, 0x00000000, 0x00000000, 0x00000000) },
1038         { FR_AB_XM_TX_CFG,
1039           EFX_OWORD32(0x00080164, 0x00000000, 0x00000000, 0x00000000) },
1040         { FR_AB_XM_RX_CFG,
1041           EFX_OWORD32(0x07100A0C, 0x00000000, 0x00000000, 0x00000000) },
1042         { FR_AB_XM_RX_PARAM,
1043           EFX_OWORD32(0x00001FF8, 0x00000000, 0x00000000, 0x00000000) },
1044         { FR_AB_XM_FC,
1045           EFX_OWORD32(0xFFFF0001, 0x00000000, 0x00000000, 0x00000000) },
1046         { FR_AB_XM_ADR_LO,
1047           EFX_OWORD32(0xFFFFFFFF, 0x00000000, 0x00000000, 0x00000000) },
1048         { FR_AB_XX_SD_CTL,
1049           EFX_OWORD32(0x0003FF0F, 0x00000000, 0x00000000, 0x00000000) },
1050 };
1051
1052 static int falcon_b0_test_registers(struct efx_nic *efx)
1053 {
1054         return efx_nic_test_registers(efx, falcon_b0_register_tests,
1055                                       ARRAY_SIZE(falcon_b0_register_tests));
1056 }
1057
1058 /**************************************************************************
1059  *
1060  * Device reset
1061  *
1062  **************************************************************************
1063  */
1064
1065 /* Resets NIC to known state.  This routine must be called in process
1066  * context and is allowed to sleep. */
1067 static int falcon_reset_hw(struct efx_nic *efx, enum reset_type method)
1068 {
1069         struct falcon_nic_data *nic_data = efx->nic_data;
1070         efx_oword_t glb_ctl_reg_ker;
1071         int rc;
1072
1073         EFX_LOG(efx, "performing %s hardware reset\n", RESET_TYPE(method));
1074
1075         /* Initiate device reset */
1076         if (method == RESET_TYPE_WORLD) {
1077                 rc = pci_save_state(efx->pci_dev);
1078                 if (rc) {
1079                         EFX_ERR(efx, "failed to backup PCI state of primary "
1080                                 "function prior to hardware reset\n");
1081                         goto fail1;
1082                 }
1083                 if (efx_nic_is_dual_func(efx)) {
1084                         rc = pci_save_state(nic_data->pci_dev2);
1085                         if (rc) {
1086                                 EFX_ERR(efx, "failed to backup PCI state of "
1087                                         "secondary function prior to "
1088                                         "hardware reset\n");
1089                                 goto fail2;
1090                         }
1091                 }
1092
1093                 EFX_POPULATE_OWORD_2(glb_ctl_reg_ker,
1094                                      FRF_AB_EXT_PHY_RST_DUR,
1095                                      FFE_AB_EXT_PHY_RST_DUR_10240US,
1096                                      FRF_AB_SWRST, 1);
1097         } else {
1098                 EFX_POPULATE_OWORD_7(glb_ctl_reg_ker,
1099                                      /* exclude PHY from "invisible" reset */
1100                                      FRF_AB_EXT_PHY_RST_CTL,
1101                                      method == RESET_TYPE_INVISIBLE,
1102                                      /* exclude EEPROM/flash and PCIe */
1103                                      FRF_AB_PCIE_CORE_RST_CTL, 1,
1104                                      FRF_AB_PCIE_NSTKY_RST_CTL, 1,
1105                                      FRF_AB_PCIE_SD_RST_CTL, 1,
1106                                      FRF_AB_EE_RST_CTL, 1,
1107                                      FRF_AB_EXT_PHY_RST_DUR,
1108                                      FFE_AB_EXT_PHY_RST_DUR_10240US,
1109                                      FRF_AB_SWRST, 1);
1110         }
1111         efx_writeo(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL);
1112
1113         EFX_LOG(efx, "waiting for hardware reset\n");
1114         schedule_timeout_uninterruptible(HZ / 20);
1115
1116         /* Restore PCI configuration if needed */
1117         if (method == RESET_TYPE_WORLD) {
1118                 if (efx_nic_is_dual_func(efx)) {
1119                         rc = pci_restore_state(nic_data->pci_dev2);
1120                         if (rc) {
1121                                 EFX_ERR(efx, "failed to restore PCI config for "
1122                                         "the secondary function\n");
1123                                 goto fail3;
1124                         }
1125                 }
1126                 rc = pci_restore_state(efx->pci_dev);
1127                 if (rc) {
1128                         EFX_ERR(efx, "failed to restore PCI config for the "
1129                                 "primary function\n");
1130                         goto fail4;
1131                 }
1132                 EFX_LOG(efx, "successfully restored PCI config\n");
1133         }
1134
1135         /* Assert that reset complete */
1136         efx_reado(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL);
1137         if (EFX_OWORD_FIELD(glb_ctl_reg_ker, FRF_AB_SWRST) != 0) {
1138                 rc = -ETIMEDOUT;
1139                 EFX_ERR(efx, "timed out waiting for hardware reset\n");
1140                 goto fail5;
1141         }
1142         EFX_LOG(efx, "hardware reset complete\n");
1143
1144         return 0;
1145
1146         /* pci_save_state() and pci_restore_state() MUST be called in pairs */
1147 fail2:
1148 fail3:
1149         pci_restore_state(efx->pci_dev);
1150 fail1:
1151 fail4:
1152 fail5:
1153         return rc;
1154 }
1155
1156 static void falcon_monitor(struct efx_nic *efx)
1157 {
1158         bool link_changed;
1159         int rc;
1160
1161         BUG_ON(!mutex_is_locked(&efx->mac_lock));
1162
1163         rc = falcon_board(efx)->type->monitor(efx);
1164         if (rc) {
1165                 EFX_ERR(efx, "Board sensor %s; shutting down PHY\n",
1166                         (rc == -ERANGE) ? "reported fault" : "failed");
1167                 efx->phy_mode |= PHY_MODE_LOW_POWER;
1168                 rc = __efx_reconfigure_port(efx);
1169                 WARN_ON(rc);
1170         }
1171
1172         if (LOOPBACK_INTERNAL(efx))
1173                 link_changed = falcon_loopback_link_poll(efx);
1174         else
1175                 link_changed = efx->phy_op->poll(efx);
1176
1177         if (link_changed) {
1178                 falcon_stop_nic_stats(efx);
1179                 falcon_deconfigure_mac_wrapper(efx);
1180
1181                 falcon_switch_mac(efx);
1182                 rc = efx->mac_op->reconfigure(efx);
1183                 BUG_ON(rc);
1184
1185                 falcon_start_nic_stats(efx);
1186
1187                 efx_link_status_changed(efx);
1188         }
1189
1190         if (EFX_IS10G(efx))
1191                 falcon_poll_xmac(efx);
1192 }
1193
1194 /* Zeroes out the SRAM contents.  This routine must be called in
1195  * process context and is allowed to sleep.
1196  */
1197 static int falcon_reset_sram(struct efx_nic *efx)
1198 {
1199         efx_oword_t srm_cfg_reg_ker, gpio_cfg_reg_ker;
1200         int count;
1201
1202         /* Set the SRAM wake/sleep GPIO appropriately. */
1203         efx_reado(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL);
1204         EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OEN, 1);
1205         EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OUT, 1);
1206         efx_writeo(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL);
1207
1208         /* Initiate SRAM reset */
1209         EFX_POPULATE_OWORD_2(srm_cfg_reg_ker,
1210                              FRF_AZ_SRM_INIT_EN, 1,
1211                              FRF_AZ_SRM_NB_SZ, 0);
1212         efx_writeo(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG);
1213
1214         /* Wait for SRAM reset to complete */
1215         count = 0;
1216         do {
1217                 EFX_LOG(efx, "waiting for SRAM reset (attempt %d)...\n", count);
1218
1219                 /* SRAM reset is slow; expect around 16ms */
1220                 schedule_timeout_uninterruptible(HZ / 50);
1221
1222                 /* Check for reset complete */
1223                 efx_reado(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG);
1224                 if (!EFX_OWORD_FIELD(srm_cfg_reg_ker, FRF_AZ_SRM_INIT_EN)) {
1225                         EFX_LOG(efx, "SRAM reset complete\n");
1226
1227                         return 0;
1228                 }
1229         } while (++count < 20); /* wait upto 0.4 sec */
1230
1231         EFX_ERR(efx, "timed out waiting for SRAM reset\n");
1232         return -ETIMEDOUT;
1233 }
1234
1235 static int falcon_spi_device_init(struct efx_nic *efx,
1236                                   struct efx_spi_device **spi_device_ret,
1237                                   unsigned int device_id, u32 device_type)
1238 {
1239         struct efx_spi_device *spi_device;
1240
1241         if (device_type != 0) {
1242                 spi_device = kzalloc(sizeof(*spi_device), GFP_KERNEL);
1243                 if (!spi_device)
1244                         return -ENOMEM;
1245                 spi_device->device_id = device_id;
1246                 spi_device->size =
1247                         1 << SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_SIZE);
1248                 spi_device->addr_len =
1249                         SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ADDR_LEN);
1250                 spi_device->munge_address = (spi_device->size == 1 << 9 &&
1251                                              spi_device->addr_len == 1);
1252                 spi_device->erase_command =
1253                         SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ERASE_CMD);
1254                 spi_device->erase_size =
1255                         1 << SPI_DEV_TYPE_FIELD(device_type,
1256                                                 SPI_DEV_TYPE_ERASE_SIZE);
1257                 spi_device->block_size =
1258                         1 << SPI_DEV_TYPE_FIELD(device_type,
1259                                                 SPI_DEV_TYPE_BLOCK_SIZE);
1260         } else {
1261                 spi_device = NULL;
1262         }
1263
1264         kfree(*spi_device_ret);
1265         *spi_device_ret = spi_device;
1266         return 0;
1267 }
1268
1269 static void falcon_remove_spi_devices(struct efx_nic *efx)
1270 {
1271         kfree(efx->spi_eeprom);
1272         efx->spi_eeprom = NULL;
1273         kfree(efx->spi_flash);
1274         efx->spi_flash = NULL;
1275 }
1276
1277 /* Extract non-volatile configuration */
1278 static int falcon_probe_nvconfig(struct efx_nic *efx)
1279 {
1280         struct falcon_nvconfig *nvconfig;
1281         int board_rev;
1282         int rc;
1283
1284         nvconfig = kmalloc(sizeof(*nvconfig), GFP_KERNEL);
1285         if (!nvconfig)
1286                 return -ENOMEM;
1287
1288         rc = falcon_read_nvram(efx, nvconfig);
1289         if (rc == -EINVAL) {
1290                 EFX_ERR(efx, "NVRAM is invalid therefore using defaults\n");
1291                 efx->phy_type = PHY_TYPE_NONE;
1292                 efx->mdio.prtad = MDIO_PRTAD_NONE;
1293                 board_rev = 0;
1294                 rc = 0;
1295         } else if (rc) {
1296                 goto fail1;
1297         } else {
1298                 struct falcon_nvconfig_board_v2 *v2 = &nvconfig->board_v2;
1299                 struct falcon_nvconfig_board_v3 *v3 = &nvconfig->board_v3;
1300
1301                 efx->phy_type = v2->port0_phy_type;
1302                 efx->mdio.prtad = v2->port0_phy_addr;
1303                 board_rev = le16_to_cpu(v2->board_revision);
1304
1305                 if (le16_to_cpu(nvconfig->board_struct_ver) >= 3) {
1306                         rc = falcon_spi_device_init(
1307                                 efx, &efx->spi_flash, FFE_AB_SPI_DEVICE_FLASH,
1308                                 le32_to_cpu(v3->spi_device_type
1309                                             [FFE_AB_SPI_DEVICE_FLASH]));
1310                         if (rc)
1311                                 goto fail2;
1312                         rc = falcon_spi_device_init(
1313                                 efx, &efx->spi_eeprom, FFE_AB_SPI_DEVICE_EEPROM,
1314                                 le32_to_cpu(v3->spi_device_type
1315                                             [FFE_AB_SPI_DEVICE_EEPROM]));
1316                         if (rc)
1317                                 goto fail2;
1318                 }
1319         }
1320
1321         /* Read the MAC addresses */
1322         memcpy(efx->mac_address, nvconfig->mac_address[0], ETH_ALEN);
1323
1324         EFX_LOG(efx, "PHY is %d phy_id %d\n", efx->phy_type, efx->mdio.prtad);
1325
1326         falcon_probe_board(efx, board_rev);
1327
1328         kfree(nvconfig);
1329         return 0;
1330
1331  fail2:
1332         falcon_remove_spi_devices(efx);
1333  fail1:
1334         kfree(nvconfig);
1335         return rc;
1336 }
1337
1338 /* Probe all SPI devices on the NIC */
1339 static void falcon_probe_spi_devices(struct efx_nic *efx)
1340 {
1341         efx_oword_t nic_stat, gpio_ctl, ee_vpd_cfg;
1342         int boot_dev;
1343
1344         efx_reado(efx, &gpio_ctl, FR_AB_GPIO_CTL);
1345         efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
1346         efx_reado(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0);
1347
1348         if (EFX_OWORD_FIELD(gpio_ctl, FRF_AB_GPIO3_PWRUP_VALUE)) {
1349                 boot_dev = (EFX_OWORD_FIELD(nic_stat, FRF_AB_SF_PRST) ?
1350                             FFE_AB_SPI_DEVICE_FLASH : FFE_AB_SPI_DEVICE_EEPROM);
1351                 EFX_LOG(efx, "Booted from %s\n",
1352                         boot_dev == FFE_AB_SPI_DEVICE_FLASH ? "flash" : "EEPROM");
1353         } else {
1354                 /* Disable VPD and set clock dividers to safe
1355                  * values for initial programming. */
1356                 boot_dev = -1;
1357                 EFX_LOG(efx, "Booted from internal ASIC settings;"
1358                         " setting SPI config\n");
1359                 EFX_POPULATE_OWORD_3(ee_vpd_cfg, FRF_AB_EE_VPD_EN, 0,
1360                                      /* 125 MHz / 7 ~= 20 MHz */
1361                                      FRF_AB_EE_SF_CLOCK_DIV, 7,
1362                                      /* 125 MHz / 63 ~= 2 MHz */
1363                                      FRF_AB_EE_EE_CLOCK_DIV, 63);
1364                 efx_writeo(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0);
1365         }
1366
1367         if (boot_dev == FFE_AB_SPI_DEVICE_FLASH)
1368                 falcon_spi_device_init(efx, &efx->spi_flash,
1369                                        FFE_AB_SPI_DEVICE_FLASH,
1370                                        default_flash_type);
1371         if (boot_dev == FFE_AB_SPI_DEVICE_EEPROM)
1372                 falcon_spi_device_init(efx, &efx->spi_eeprom,
1373                                        FFE_AB_SPI_DEVICE_EEPROM,
1374                                        large_eeprom_type);
1375 }
1376
1377 static int falcon_probe_nic(struct efx_nic *efx)
1378 {
1379         struct falcon_nic_data *nic_data;
1380         struct falcon_board *board;
1381         int rc;
1382
1383         /* Allocate storage for hardware specific data */
1384         nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
1385         if (!nic_data)
1386                 return -ENOMEM;
1387         efx->nic_data = nic_data;
1388
1389         rc = -ENODEV;
1390
1391         if (efx_nic_fpga_ver(efx) != 0) {
1392                 EFX_ERR(efx, "Falcon FPGA not supported\n");
1393                 goto fail1;
1394         }
1395
1396         if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1) {
1397                 efx_oword_t nic_stat;
1398                 struct pci_dev *dev;
1399                 u8 pci_rev = efx->pci_dev->revision;
1400
1401                 if ((pci_rev == 0xff) || (pci_rev == 0)) {
1402                         EFX_ERR(efx, "Falcon rev A0 not supported\n");
1403                         goto fail1;
1404                 }
1405                 efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
1406                 if (EFX_OWORD_FIELD(nic_stat, FRF_AB_STRAP_10G) == 0) {
1407                         EFX_ERR(efx, "Falcon rev A1 1G not supported\n");
1408                         goto fail1;
1409                 }
1410                 if (EFX_OWORD_FIELD(nic_stat, FRF_AA_STRAP_PCIE) == 0) {
1411                         EFX_ERR(efx, "Falcon rev A1 PCI-X not supported\n");
1412                         goto fail1;
1413                 }
1414
1415                 dev = pci_dev_get(efx->pci_dev);
1416                 while ((dev = pci_get_device(EFX_VENDID_SFC, FALCON_A_S_DEVID,
1417                                              dev))) {
1418                         if (dev->bus == efx->pci_dev->bus &&
1419                             dev->devfn == efx->pci_dev->devfn + 1) {
1420                                 nic_data->pci_dev2 = dev;
1421                                 break;
1422                         }
1423                 }
1424                 if (!nic_data->pci_dev2) {
1425                         EFX_ERR(efx, "failed to find secondary function\n");
1426                         rc = -ENODEV;
1427                         goto fail2;
1428                 }
1429         }
1430
1431         /* Now we can reset the NIC */
1432         rc = falcon_reset_hw(efx, RESET_TYPE_ALL);
1433         if (rc) {
1434                 EFX_ERR(efx, "failed to reset NIC\n");
1435                 goto fail3;
1436         }
1437
1438         /* Allocate memory for INT_KER */
1439         rc = efx_nic_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t));
1440         if (rc)
1441                 goto fail4;
1442         BUG_ON(efx->irq_status.dma_addr & 0x0f);
1443
1444         EFX_LOG(efx, "INT_KER at %llx (virt %p phys %llx)\n",
1445                 (u64)efx->irq_status.dma_addr,
1446                 efx->irq_status.addr, (u64)virt_to_phys(efx->irq_status.addr));
1447
1448         falcon_probe_spi_devices(efx);
1449
1450         /* Read in the non-volatile configuration */
1451         rc = falcon_probe_nvconfig(efx);
1452         if (rc)
1453                 goto fail5;
1454
1455         /* Initialise I2C adapter */
1456         board = falcon_board(efx);
1457         board->i2c_adap.owner = THIS_MODULE;
1458         board->i2c_data = falcon_i2c_bit_operations;
1459         board->i2c_data.data = efx;
1460         board->i2c_adap.algo_data = &board->i2c_data;
1461         board->i2c_adap.dev.parent = &efx->pci_dev->dev;
1462         strlcpy(board->i2c_adap.name, "SFC4000 GPIO",
1463                 sizeof(board->i2c_adap.name));
1464         rc = i2c_bit_add_bus(&board->i2c_adap);
1465         if (rc)
1466                 goto fail5;
1467
1468         rc = falcon_board(efx)->type->init(efx);
1469         if (rc) {
1470                 EFX_ERR(efx, "failed to initialise board\n");
1471                 goto fail6;
1472         }
1473
1474         nic_data->stats_disable_count = 1;
1475         setup_timer(&nic_data->stats_timer, &falcon_stats_timer_func,
1476                     (unsigned long)efx);
1477
1478         return 0;
1479
1480  fail6:
1481         BUG_ON(i2c_del_adapter(&board->i2c_adap));
1482         memset(&board->i2c_adap, 0, sizeof(board->i2c_adap));
1483  fail5:
1484         falcon_remove_spi_devices(efx);
1485         efx_nic_free_buffer(efx, &efx->irq_status);
1486  fail4:
1487  fail3:
1488         if (nic_data->pci_dev2) {
1489                 pci_dev_put(nic_data->pci_dev2);
1490                 nic_data->pci_dev2 = NULL;
1491         }
1492  fail2:
1493  fail1:
1494         kfree(efx->nic_data);
1495         return rc;
1496 }
1497
1498 static void falcon_init_rx_cfg(struct efx_nic *efx)
1499 {
1500         /* Prior to Siena the RX DMA engine will split each frame at
1501          * intervals of RX_USR_BUF_SIZE (32-byte units). We set it to
1502          * be so large that that never happens. */
1503         const unsigned huge_buf_size = (3 * 4096) >> 5;
1504         /* RX control FIFO thresholds (32 entries) */
1505         const unsigned ctrl_xon_thr = 20;
1506         const unsigned ctrl_xoff_thr = 25;
1507         /* RX data FIFO thresholds (256-byte units; size varies) */
1508         int data_xon_thr = efx_nic_rx_xon_thresh >> 8;
1509         int data_xoff_thr = efx_nic_rx_xoff_thresh >> 8;
1510         efx_oword_t reg;
1511
1512         efx_reado(efx, &reg, FR_AZ_RX_CFG);
1513         if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1) {
1514                 /* Data FIFO size is 5.5K */
1515                 if (data_xon_thr < 0)
1516                         data_xon_thr = 512 >> 8;
1517                 if (data_xoff_thr < 0)
1518                         data_xoff_thr = 2048 >> 8;
1519                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_DESC_PUSH_EN, 0);
1520                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_USR_BUF_SIZE,
1521                                     huge_buf_size);
1522                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_MAC_TH, data_xon_thr);
1523                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_MAC_TH, data_xoff_thr);
1524                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_TX_TH, ctrl_xon_thr);
1525                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_TX_TH, ctrl_xoff_thr);
1526         } else {
1527                 /* Data FIFO size is 80K; register fields moved */
1528                 if (data_xon_thr < 0)
1529                         data_xon_thr = 27648 >> 8; /* ~3*max MTU */
1530                 if (data_xoff_thr < 0)
1531                         data_xoff_thr = 54272 >> 8; /* ~80Kb - 3*max MTU */
1532                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_DESC_PUSH_EN, 0);
1533                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_USR_BUF_SIZE,
1534                                     huge_buf_size);
1535                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_MAC_TH, data_xon_thr);
1536                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_MAC_TH, data_xoff_thr);
1537                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_TX_TH, ctrl_xon_thr);
1538                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_TX_TH, ctrl_xoff_thr);
1539                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1);
1540         }
1541         /* Always enable XOFF signal from RX FIFO.  We enable
1542          * or disable transmission of pause frames at the MAC. */
1543         EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, 1);
1544         efx_writeo(efx, &reg, FR_AZ_RX_CFG);
1545 }
1546
1547 /* This call performs hardware-specific global initialisation, such as
1548  * defining the descriptor cache sizes and number of RSS channels.
1549  * It does not set up any buffers, descriptor rings or event queues.
1550  */
1551 static int falcon_init_nic(struct efx_nic *efx)
1552 {
1553         efx_oword_t temp;
1554         int rc;
1555
1556         /* Use on-chip SRAM */
1557         efx_reado(efx, &temp, FR_AB_NIC_STAT);
1558         EFX_SET_OWORD_FIELD(temp, FRF_AB_ONCHIP_SRAM, 1);
1559         efx_writeo(efx, &temp, FR_AB_NIC_STAT);
1560
1561         /* Set the source of the GMAC clock */
1562         if (efx_nic_rev(efx) == EFX_REV_FALCON_B0) {
1563                 efx_reado(efx, &temp, FR_AB_GPIO_CTL);
1564                 EFX_SET_OWORD_FIELD(temp, FRF_AB_USE_NIC_CLK, true);
1565                 efx_writeo(efx, &temp, FR_AB_GPIO_CTL);
1566         }
1567
1568         /* Select the correct MAC */
1569         falcon_clock_mac(efx);
1570
1571         rc = falcon_reset_sram(efx);
1572         if (rc)
1573                 return rc;
1574
1575         /* Clear the parity enables on the TX data fifos as
1576          * they produce false parity errors because of timing issues
1577          */
1578         if (EFX_WORKAROUND_5129(efx)) {
1579                 efx_reado(efx, &temp, FR_AZ_CSR_SPARE);
1580                 EFX_SET_OWORD_FIELD(temp, FRF_AB_MEM_PERR_EN_TX_DATA, 0);
1581                 efx_writeo(efx, &temp, FR_AZ_CSR_SPARE);
1582         }
1583
1584         if (EFX_WORKAROUND_7244(efx)) {
1585                 efx_reado(efx, &temp, FR_BZ_RX_FILTER_CTL);
1586                 EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_FULL_SRCH_LIMIT, 8);
1587                 EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_WILD_SRCH_LIMIT, 8);
1588                 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_FULL_SRCH_LIMIT, 8);
1589                 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_WILD_SRCH_LIMIT, 8);
1590                 efx_writeo(efx, &temp, FR_BZ_RX_FILTER_CTL);
1591         }
1592
1593         /* XXX This is documented only for Falcon A0/A1 */
1594         /* Setup RX.  Wait for descriptor is broken and must
1595          * be disabled.  RXDP recovery shouldn't be needed, but is.
1596          */
1597         efx_reado(efx, &temp, FR_AA_RX_SELF_RST);
1598         EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_NODESC_WAIT_DIS, 1);
1599         EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_SELF_RST_EN, 1);
1600         if (EFX_WORKAROUND_5583(efx))
1601                 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_ISCSI_DIS, 1);
1602         efx_writeo(efx, &temp, FR_AA_RX_SELF_RST);
1603
1604         /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
1605          * descriptors (which is bad).
1606          */
1607         efx_reado(efx, &temp, FR_AZ_TX_CFG);
1608         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0);
1609         efx_writeo(efx, &temp, FR_AZ_TX_CFG);
1610
1611         falcon_init_rx_cfg(efx);
1612
1613         /* Set destination of both TX and RX Flush events */
1614         if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
1615                 EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0);
1616                 efx_writeo(efx, &temp, FR_BZ_DP_CTRL);
1617         }
1618
1619         efx_nic_init_common(efx);
1620
1621         return 0;
1622 }
1623
1624 static void falcon_remove_nic(struct efx_nic *efx)
1625 {
1626         struct falcon_nic_data *nic_data = efx->nic_data;
1627         struct falcon_board *board = falcon_board(efx);
1628         int rc;
1629
1630         board->type->fini(efx);
1631
1632         /* Remove I2C adapter and clear it in preparation for a retry */
1633         rc = i2c_del_adapter(&board->i2c_adap);
1634         BUG_ON(rc);
1635         memset(&board->i2c_adap, 0, sizeof(board->i2c_adap));
1636
1637         falcon_remove_spi_devices(efx);
1638         efx_nic_free_buffer(efx, &efx->irq_status);
1639
1640         falcon_reset_hw(efx, RESET_TYPE_ALL);
1641
1642         /* Release the second function after the reset */
1643         if (nic_data->pci_dev2) {
1644                 pci_dev_put(nic_data->pci_dev2);
1645                 nic_data->pci_dev2 = NULL;
1646         }
1647
1648         /* Tear down the private nic state */
1649         kfree(efx->nic_data);
1650         efx->nic_data = NULL;
1651 }
1652
1653 static void falcon_update_nic_stats(struct efx_nic *efx)
1654 {
1655         struct falcon_nic_data *nic_data = efx->nic_data;
1656         efx_oword_t cnt;
1657
1658         if (nic_data->stats_disable_count)
1659                 return;
1660
1661         efx_reado(efx, &cnt, FR_AZ_RX_NODESC_DROP);
1662         efx->n_rx_nodesc_drop_cnt +=
1663                 EFX_OWORD_FIELD(cnt, FRF_AB_RX_NODESC_DROP_CNT);
1664
1665         if (nic_data->stats_pending &&
1666             *nic_data->stats_dma_done == FALCON_STATS_DONE) {
1667                 nic_data->stats_pending = false;
1668                 rmb(); /* read the done flag before the stats */
1669                 efx->mac_op->update_stats(efx);
1670         }
1671 }
1672
1673 void falcon_start_nic_stats(struct efx_nic *efx)
1674 {
1675         struct falcon_nic_data *nic_data = efx->nic_data;
1676
1677         spin_lock_bh(&efx->stats_lock);
1678         if (--nic_data->stats_disable_count == 0)
1679                 falcon_stats_request(efx);
1680         spin_unlock_bh(&efx->stats_lock);
1681 }
1682
1683 void falcon_stop_nic_stats(struct efx_nic *efx)
1684 {
1685         struct falcon_nic_data *nic_data = efx->nic_data;
1686         int i;
1687
1688         might_sleep();
1689
1690         spin_lock_bh(&efx->stats_lock);
1691         ++nic_data->stats_disable_count;
1692         spin_unlock_bh(&efx->stats_lock);
1693
1694         del_timer_sync(&nic_data->stats_timer);
1695
1696         /* Wait enough time for the most recent transfer to
1697          * complete. */
1698         for (i = 0; i < 4 && nic_data->stats_pending; i++) {
1699                 if (*nic_data->stats_dma_done == FALCON_STATS_DONE)
1700                         break;
1701                 msleep(1);
1702         }
1703
1704         spin_lock_bh(&efx->stats_lock);
1705         falcon_stats_complete(efx);
1706         spin_unlock_bh(&efx->stats_lock);
1707 }
1708
1709 static void falcon_set_id_led(struct efx_nic *efx, enum efx_led_mode mode)
1710 {
1711         falcon_board(efx)->type->set_id_led(efx, mode);
1712 }
1713
1714 /**************************************************************************
1715  *
1716  * Wake on LAN
1717  *
1718  **************************************************************************
1719  */
1720
1721 static void falcon_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
1722 {
1723         wol->supported = 0;
1724         wol->wolopts = 0;
1725         memset(&wol->sopass, 0, sizeof(wol->sopass));
1726 }
1727
1728 static int falcon_set_wol(struct efx_nic *efx, u32 type)
1729 {
1730         if (type != 0)
1731                 return -EINVAL;
1732         return 0;
1733 }
1734
1735 /**************************************************************************
1736  *
1737  * Revision-dependent attributes used by efx.c and nic.c
1738  *
1739  **************************************************************************
1740  */
1741
1742 struct efx_nic_type falcon_a1_nic_type = {
1743         .probe = falcon_probe_nic,
1744         .remove = falcon_remove_nic,
1745         .init = falcon_init_nic,
1746         .fini = efx_port_dummy_op_void,
1747         .monitor = falcon_monitor,
1748         .reset = falcon_reset_hw,
1749         .probe_port = falcon_probe_port,
1750         .remove_port = falcon_remove_port,
1751         .prepare_flush = falcon_prepare_flush,
1752         .update_stats = falcon_update_nic_stats,
1753         .start_stats = falcon_start_nic_stats,
1754         .stop_stats = falcon_stop_nic_stats,
1755         .set_id_led = falcon_set_id_led,
1756         .push_irq_moderation = falcon_push_irq_moderation,
1757         .push_multicast_hash = falcon_push_multicast_hash,
1758         .reconfigure_port = falcon_reconfigure_port,
1759         .get_wol = falcon_get_wol,
1760         .set_wol = falcon_set_wol,
1761         .resume_wol = efx_port_dummy_op_void,
1762         .test_nvram = falcon_test_nvram,
1763         .default_mac_ops = &falcon_xmac_operations,
1764
1765         .revision = EFX_REV_FALCON_A1,
1766         .mem_map_size = 0x20000,
1767         .txd_ptr_tbl_base = FR_AA_TX_DESC_PTR_TBL_KER,
1768         .rxd_ptr_tbl_base = FR_AA_RX_DESC_PTR_TBL_KER,
1769         .buf_tbl_base = FR_AA_BUF_FULL_TBL_KER,
1770         .evq_ptr_tbl_base = FR_AA_EVQ_PTR_TBL_KER,
1771         .evq_rptr_tbl_base = FR_AA_EVQ_RPTR_KER,
1772         .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
1773         .rx_buffer_padding = 0x24,
1774         .max_interrupt_mode = EFX_INT_MODE_MSI,
1775         .phys_addr_channels = 4,
1776         .tx_dc_base = 0x130000,
1777         .rx_dc_base = 0x100000,
1778         .offload_features = NETIF_F_IP_CSUM,
1779         .reset_world_flags = ETH_RESET_IRQ,
1780 };
1781
1782 struct efx_nic_type falcon_b0_nic_type = {
1783         .probe = falcon_probe_nic,
1784         .remove = falcon_remove_nic,
1785         .init = falcon_init_nic,
1786         .fini = efx_port_dummy_op_void,
1787         .monitor = falcon_monitor,
1788         .reset = falcon_reset_hw,
1789         .probe_port = falcon_probe_port,
1790         .remove_port = falcon_remove_port,
1791         .prepare_flush = falcon_prepare_flush,
1792         .update_stats = falcon_update_nic_stats,
1793         .start_stats = falcon_start_nic_stats,
1794         .stop_stats = falcon_stop_nic_stats,
1795         .set_id_led = falcon_set_id_led,
1796         .push_irq_moderation = falcon_push_irq_moderation,
1797         .push_multicast_hash = falcon_push_multicast_hash,
1798         .reconfigure_port = falcon_reconfigure_port,
1799         .get_wol = falcon_get_wol,
1800         .set_wol = falcon_set_wol,
1801         .resume_wol = efx_port_dummy_op_void,
1802         .test_registers = falcon_b0_test_registers,
1803         .test_nvram = falcon_test_nvram,
1804         .default_mac_ops = &falcon_xmac_operations,
1805
1806         .revision = EFX_REV_FALCON_B0,
1807         /* Map everything up to and including the RSS indirection
1808          * table.  Don't map MSI-X table, MSI-X PBA since Linux
1809          * requires that they not be mapped.  */
1810         .mem_map_size = (FR_BZ_RX_INDIRECTION_TBL +
1811                          FR_BZ_RX_INDIRECTION_TBL_STEP *
1812                          FR_BZ_RX_INDIRECTION_TBL_ROWS),
1813         .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL,
1814         .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL,
1815         .buf_tbl_base = FR_BZ_BUF_FULL_TBL,
1816         .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL,
1817         .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR,
1818         .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
1819         .rx_buffer_padding = 0,
1820         .max_interrupt_mode = EFX_INT_MODE_MSIX,
1821         .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy
1822                                    * interrupt handler only supports 32
1823                                    * channels */
1824         .tx_dc_base = 0x130000,
1825         .rx_dc_base = 0x100000,
1826         .offload_features = NETIF_F_IP_CSUM,
1827         .reset_world_flags = ETH_RESET_IRQ,
1828 };
1829