drivers/net/sfc/falcon.c

   1 /****************************************************************************
   2  * Driver for Solarflare Solarstorm network controllers and boards
   3  * Copyright 2005-2006 Fen Systems Ltd.
   4  * Copyright 2006-2009 Solarflare Communications Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published
   8  * by the Free Software Foundation, incorporated herein by reference.
   9  */
  10
  11 #include <linux/bitops.h>
  12 #include <linux/delay.h>
  13 #include <linux/pci.h>
  14 #include <linux/module.h>
  15 #include <linux/seq_file.h>
  16 #include <linux/i2c.h>
  17 #include <linux/mii.h>
  18 #include <linux/slab.h>
  19 #include "net_driver.h"
  20 #include "bitfield.h"
  21 #include "efx.h"
  22 #include "mac.h"
  23 #include "spi.h"
  24 #include "nic.h"
  25 #include "regs.h"
  26 #include "io.h"
  27 #include "phy.h"
  28 #include "workarounds.h"
  29
  30 /* Hardware control for SFC4000 (aka Falcon). */
  31
  32 static const unsigned int
  33 /* "Large" EEPROM device: Atmel AT25640 or similar
  34  * 8 KB, 16-bit address, 32 B write block */
  35 large_eeprom_type = ((13 << SPI_DEV_TYPE_SIZE_LBN)
  36                      | (2 << SPI_DEV_TYPE_ADDR_LEN_LBN)
  37                      | (5 << SPI_DEV_TYPE_BLOCK_SIZE_LBN)),
  38 /* Default flash device: Atmel AT25F1024
  39  * 128 KB, 24-bit address, 32 KB erase block, 256 B write block */
  40 default_flash_type = ((17 << SPI_DEV_TYPE_SIZE_LBN)
  41                       | (3 << SPI_DEV_TYPE_ADDR_LEN_LBN)
  42                       | (0x52 << SPI_DEV_TYPE_ERASE_CMD_LBN)
  43                       | (15 << SPI_DEV_TYPE_ERASE_SIZE_LBN)
  44                       | (8 << SPI_DEV_TYPE_BLOCK_SIZE_LBN));
  45
  46 /**************************************************************************
  47  *
  48  * I2C bus - this is a bit-bashing interface using GPIO pins
  49  * Note that it uses the output enables to tristate the outputs
  50  * SDA is the data pin and SCL is the clock
  51  *
  52  **************************************************************************
  53  */
  54 static void falcon_setsda(void *data, int state)
  55 {
  56         struct efx_nic *efx = (struct efx_nic *)data;
  57         efx_oword_t reg;
  58
  59         efx_reado(efx, &reg, FR_AB_GPIO_CTL);
  60         EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO3_OEN, !state);
  61         efx_writeo(efx, &reg, FR_AB_GPIO_CTL);
  62 }
  63
  64 static void falcon_setscl(void *data, int state)
  65 {
  66         struct efx_nic *efx = (struct efx_nic *)data;
  67         efx_oword_t reg;
  68
  69         efx_reado(efx, &reg, FR_AB_GPIO_CTL);
  70         EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO0_OEN, !state);
  71         efx_writeo(efx, &reg, FR_AB_GPIO_CTL);
  72 }
  73
  74 static int falcon_getsda(void *data)
  75 {
  76         struct efx_nic *efx = (struct efx_nic *)data;
  77         efx_oword_t reg;
  78
  79         efx_reado(efx, &reg, FR_AB_GPIO_CTL);
  80         return EFX_OWORD_FIELD(reg, FRF_AB_GPIO3_IN);
  81 }
  82
  83 static int falcon_getscl(void *data)
  84 {
  85         struct efx_nic *efx = (struct efx_nic *)data;
  86         efx_oword_t reg;
  87
  88         efx_reado(efx, &reg, FR_AB_GPIO_CTL);
  89         return EFX_OWORD_FIELD(reg, FRF_AB_GPIO0_IN);
  90 }
  91
  92 static struct i2c_algo_bit_data falcon_i2c_bit_operations = {
  93         .setsda         = falcon_setsda,
  94         .setscl         = falcon_setscl,
  95         .getsda         = falcon_getsda,
  96         .getscl         = falcon_getscl,
  97         .udelay         = 5,
  98         /* Wait up to 50 ms for slave to let us pull SCL high */
  99         .timeout        = DIV_ROUND_UP(HZ, 20),
 100 };
 101
 102 static void falcon_push_irq_moderation(struct efx_channel *channel)
 103 {
 104         efx_dword_t timer_cmd;
 105         struct efx_nic *efx = channel->efx;
 106
 107         /* Set timer register */
 108         if (channel->irq_moderation) {
 109                 EFX_POPULATE_DWORD_2(timer_cmd,
 110                                      FRF_AB_TC_TIMER_MODE,
 111                                      FFE_BB_TIMER_MODE_INT_HLDOFF,
 112                                      FRF_AB_TC_TIMER_VAL,
 113                                      channel->irq_moderation - 1);
 114         } else {
 115                 EFX_POPULATE_DWORD_2(timer_cmd,
 116                                      FRF_AB_TC_TIMER_MODE,
 117                                      FFE_BB_TIMER_MODE_DIS,
 118                                      FRF_AB_TC_TIMER_VAL, 0);
 119         }
 120         BUILD_BUG_ON(FR_AA_TIMER_COMMAND_KER != FR_BZ_TIMER_COMMAND_P0);
 121         efx_writed_page_locked(efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0,
 122                                channel->channel);
 123 }
 124
 125 static void falcon_deconfigure_mac_wrapper(struct efx_nic *efx);
 126
 127 static void falcon_prepare_flush(struct efx_nic *efx)
 128 {
 129         falcon_deconfigure_mac_wrapper(efx);
 130
 131         /* Wait for the tx and rx fifo's to get to the next packet boundary
 132          * (~1ms without back-pressure), then to drain the remainder of the
 133          * fifo's at data path speeds (negligible), with a healthy margin. */
 134         msleep(10);
 135 }
 136
 137 /* Acknowledge a legacy interrupt from Falcon
 138  *
 139  * This acknowledges a legacy (not MSI) interrupt via INT_ACK_KER_REG.
 140  *
 141  * Due to SFC bug 3706 (silicon revision <=A1) reads can be duplicated in the
 142  * BIU. Interrupt acknowledge is read sensitive so must write instead
 143  * (then read to ensure the BIU collector is flushed)
 144  *
 145  * NB most hardware supports MSI interrupts
 146  */
 147 inline void falcon_irq_ack_a1(struct efx_nic *efx)
 148 {
 149         efx_dword_t reg;
 150
 151         EFX_POPULATE_DWORD_1(reg, FRF_AA_INT_ACK_KER_FIELD, 0xb7eb7e);
 152         efx_writed(efx, &reg, FR_AA_INT_ACK_KER);
 153         efx_readd(efx, &reg, FR_AA_WORK_AROUND_BROKEN_PCI_READS);
 154 }
 155
 156
 157 irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id)
 158 {
 159         struct efx_nic *efx = dev_id;
 160         efx_oword_t *int_ker = efx->irq_status.addr;
 161         int syserr;
 162         int queues;
 163
 164         /* Check to see if this is our interrupt.  If it isn't, we
 165          * exit without having touched the hardware.
 166          */
 167         if (unlikely(EFX_OWORD_IS_ZERO(*int_ker))) {
 168                 netif_vdbg(efx, intr, efx->net_dev,
 169                            "IRQ %d on CPU %d not for me\n", irq,
 170                            raw_smp_processor_id());
 171                 return IRQ_NONE;
 172         }
 173         efx->last_irq_cpu = raw_smp_processor_id();
 174         netif_vdbg(efx, intr, efx->net_dev,
 175                    "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
 176                    irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
 177
 178         /* Determine interrupting queues, clear interrupt status
 179          * register and acknowledge the device interrupt.
 180          */
 181         BUILD_BUG_ON(FSF_AZ_NET_IVEC_INT_Q_WIDTH > EFX_MAX_CHANNELS);
 182         queues = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_INT_Q);
 183
 184         /* Check to see if we have a serious error condition */
 185         if (queues & (1U << efx->fatal_irq_level)) {
 186                 syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
 187                 if (unlikely(syserr))
 188                         return efx_nic_fatal_interrupt(efx);
 189         }
 190
 191         EFX_ZERO_OWORD(*int_ker);
 192         wmb(); /* Ensure the vector is cleared before interrupt ack */
 193         falcon_irq_ack_a1(efx);
 194
 195         if (queues & 1)
 196                 efx_schedule_channel(efx_get_channel(efx, 0));
 197         if (queues & 2)
 198                 efx_schedule_channel(efx_get_channel(efx, 1));
 199         return IRQ_HANDLED;
 200 }
 201 /**************************************************************************
 202  *
 203  * EEPROM/flash
 204  *
 205  **************************************************************************
 206  */
 207
 208 #define FALCON_SPI_MAX_LEN sizeof(efx_oword_t)
 209
 210 static int falcon_spi_poll(struct efx_nic *efx)
 211 {
 212         efx_oword_t reg;
 213         efx_reado(efx, &reg, FR_AB_EE_SPI_HCMD);
 214         return EFX_OWORD_FIELD(reg, FRF_AB_EE_SPI_HCMD_CMD_EN) ? -EBUSY : 0;
 215 }
 216
 217 /* Wait for SPI command completion */
 218 static int falcon_spi_wait(struct efx_nic *efx)
 219 {
 220         /* Most commands will finish quickly, so we start polling at
 221          * very short intervals.  Sometimes the command may have to
 222          * wait for VPD or expansion ROM access outside of our
 223          * control, so we allow up to 100 ms. */
 224         unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 10);
 225         int i;
 226
 227         for (i = 0; i < 10; i++) {
 228                 if (!falcon_spi_poll(efx))
 229                         return 0;
 230                 udelay(10);
 231         }
 232
 233         for (;;) {
 234                 if (!falcon_spi_poll(efx))
 235                         return 0;
 236                 if (time_after_eq(jiffies, timeout)) {
 237                         netif_err(efx, hw, efx->net_dev,
 238                                   "timed out waiting for SPI\n");
 239                         return -ETIMEDOUT;
 240                 }
 241                 schedule_timeout_uninterruptible(1);
 242         }
 243 }
 244
 245 int falcon_spi_cmd(struct efx_nic *efx, const struct efx_spi_device *spi,
 246                    unsigned int command, int address,
 247                    const void *in, void *out, size_t len)
 248 {
 249         bool addressed = (address >= 0);
 250         bool reading = (out != NULL);
 251         efx_oword_t reg;
 252         int rc;
 253
 254         /* Input validation */
 255         if (len > FALCON_SPI_MAX_LEN)
 256                 return -EINVAL;
 257
 258         /* Check that previous command is not still running */
 259         rc = falcon_spi_poll(efx);
 260         if (rc)
 261                 return rc;
 262
 263         /* Program address register, if we have an address */
 264         if (addressed) {
 265                 EFX_POPULATE_OWORD_1(reg, FRF_AB_EE_SPI_HADR_ADR, address);
 266                 efx_writeo(efx, &reg, FR_AB_EE_SPI_HADR);
 267         }
 268
 269         /* Program data register, if we have data */
 270         if (in != NULL) {
 271                 memcpy(&reg, in, len);
 272                 efx_writeo(efx, &reg, FR_AB_EE_SPI_HDATA);
 273         }
 274
 275         /* Issue read/write command */
 276         EFX_POPULATE_OWORD_7(reg,
 277                              FRF_AB_EE_SPI_HCMD_CMD_EN, 1,
 278                              FRF_AB_EE_SPI_HCMD_SF_SEL, spi->device_id,
 279                              FRF_AB_EE_SPI_HCMD_DABCNT, len,
 280                              FRF_AB_EE_SPI_HCMD_READ, reading,
 281                              FRF_AB_EE_SPI_HCMD_DUBCNT, 0,
 282                              FRF_AB_EE_SPI_HCMD_ADBCNT,
 283                              (addressed ? spi->addr_len : 0),
 284                              FRF_AB_EE_SPI_HCMD_ENC, command);
 285         efx_writeo(efx, &reg, FR_AB_EE_SPI_HCMD);
 286
 287         /* Wait for read/write to complete */
 288         rc = falcon_spi_wait(efx);
 289         if (rc)
 290                 return rc;
 291
 292         /* Read data */
 293         if (out != NULL) {
 294                 efx_reado(efx, &reg, FR_AB_EE_SPI_HDATA);
 295                 memcpy(out, &reg, len);
 296         }
 297
 298         return 0;
 299 }
 300
 301 static size_t
 302 falcon_spi_write_limit(const struct efx_spi_device *spi, size_t start)
 303 {
 304         return min(FALCON_SPI_MAX_LEN,
 305                    (spi->block_size - (start & (spi->block_size - 1))));
 306 }
 307
 308 static inline u8
 309 efx_spi_munge_command(const struct efx_spi_device *spi,
 310                       const u8 command, const unsigned int address)
 311 {
 312         return command | (((address >> 8) & spi->munge_address) << 3);
 313 }
 314
 315 /* Wait up to 10 ms for buffered write completion */
 316 int
 317 falcon_spi_wait_write(struct efx_nic *efx, const struct efx_spi_device *spi)
 318 {
 319         unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 100);
 320         u8 status;
 321         int rc;
 322
 323         for (;;) {
 324                 rc = falcon_spi_cmd(efx, spi, SPI_RDSR, -1, NULL,
 325                                     &status, sizeof(status));
 326                 if (rc)
 327                         return rc;
 328                 if (!(status & SPI_STATUS_NRDY))
 329                         return 0;
 330                 if (time_after_eq(jiffies, timeout)) {
 331                         netif_err(efx, hw, efx->net_dev,
 332                                   "SPI write timeout on device %d"
 333                                   " last status=0x%02x\n",
 334                                   spi->device_id, status);
 335                         return -ETIMEDOUT;
 336                 }
 337                 schedule_timeout_uninterruptible(1);
 338         }
 339 }
 340
 341 int falcon_spi_read(struct efx_nic *efx, const struct efx_spi_device *spi,
 342                     loff_t start, size_t len, size_t *retlen, u8 *buffer)
 343 {
 344         size_t block_len, pos = 0;
 345         unsigned int command;
 346         int rc = 0;
 347
 348         while (pos < len) {
 349                 block_len = min(len - pos, FALCON_SPI_MAX_LEN);
 350
 351                 command = efx_spi_munge_command(spi, SPI_READ, start + pos);
 352                 rc = falcon_spi_cmd(efx, spi, command, start + pos, NULL,
 353                                     buffer + pos, block_len);
 354                 if (rc)
 355                         break;
 356                 pos += block_len;
 357
 358                 /* Avoid locking up the system */
 359                 cond_resched();
 360                 if (signal_pending(current)) {
 361                         rc = -EINTR;
 362                         break;
 363                 }
 364         }
 365
 366         if (retlen)
 367                 *retlen = pos;
 368         return rc;
 369 }
 370
 371 int
 372 falcon_spi_write(struct efx_nic *efx, const struct efx_spi_device *spi,
 373                  loff_t start, size_t len, size_t *retlen, const u8 *buffer)
 374 {
 375         u8 verify_buffer[FALCON_SPI_MAX_LEN];
 376         size_t block_len, pos = 0;
 377         unsigned int command;
 378         int rc = 0;
 379
 380         while (pos < len) {
 381                 rc = falcon_spi_cmd(efx, spi, SPI_WREN, -1, NULL, NULL, 0);
 382                 if (rc)
 383                         break;
 384
 385                 block_len = min(len - pos,
 386                                 falcon_spi_write_limit(spi, start + pos));
 387                 command = efx_spi_munge_command(spi, SPI_WRITE, start + pos);
 388                 rc = falcon_spi_cmd(efx, spi, command, start + pos,
 389                                     buffer + pos, NULL, block_len);
 390                 if (rc)
 391                         break;
 392
 393                 rc = falcon_spi_wait_write(efx, spi);
 394                 if (rc)
 395                         break;
 396
 397                 command = efx_spi_munge_command(spi, SPI_READ, start + pos);
 398                 rc = falcon_spi_cmd(efx, spi, command, start + pos,
 399                                     NULL, verify_buffer, block_len);
 400                 if (memcmp(verify_buffer, buffer + pos, block_len)) {
 401                         rc = -EIO;
 402                         break;
 403                 }
 404
 405                 pos += block_len;
 406
 407                 /* Avoid locking up the system */
 408                 cond_resched();
 409                 if (signal_pending(current)) {
 410                         rc = -EINTR;
 411                         break;
 412                 }
 413         }
 414
 415         if (retlen)
 416                 *retlen = pos;
 417         return rc;
 418 }
 419
 420 /**************************************************************************
 421  *
 422  * MAC wrapper
 423  *
 424  **************************************************************************
 425  */
 426
 427 static void falcon_push_multicast_hash(struct efx_nic *efx)
 428 {
 429         union efx_multicast_hash *mc_hash = &efx->multicast_hash;
 430
 431         WARN_ON(!mutex_is_locked(&efx->mac_lock));
 432
 433         efx_writeo(efx, &mc_hash->oword[0], FR_AB_MAC_MC_HASH_REG0);
 434         efx_writeo(efx, &mc_hash->oword[1], FR_AB_MAC_MC_HASH_REG1);
 435 }
 436
 437 static void falcon_reset_macs(struct efx_nic *efx)
 438 {
 439         struct falcon_nic_data *nic_data = efx->nic_data;
 440         efx_oword_t reg, mac_ctrl;
 441         int count;
 442
 443         if (efx_nic_rev(efx) < EFX_REV_FALCON_B0) {
 444                 /* It's not safe to use GLB_CTL_REG to reset the
 445                  * macs, so instead use the internal MAC resets
 446                  */
 447                 EFX_POPULATE_OWORD_1(reg, FRF_AB_XM_CORE_RST, 1);
 448                 efx_writeo(efx, &reg, FR_AB_XM_GLB_CFG);
 449
 450                 for (count = 0; count < 10000; count++) {
 451                         efx_reado(efx, &reg, FR_AB_XM_GLB_CFG);
 452                         if (EFX_OWORD_FIELD(reg, FRF_AB_XM_CORE_RST) ==
 453                             0)
 454                                 return;
 455                         udelay(10);
 456                 }
 457
 458                 netif_err(efx, hw, efx->net_dev,
 459                           "timed out waiting for XMAC core reset\n");
 460         }
 461
 462         /* Mac stats will fail whist the TX fifo is draining */
 463         WARN_ON(nic_data->stats_disable_count == 0);
 464
 465         efx_reado(efx, &mac_ctrl, FR_AB_MAC_CTRL);
 466         EFX_SET_OWORD_FIELD(mac_ctrl, FRF_BB_TXFIFO_DRAIN_EN, 1);
 467         efx_writeo(efx, &mac_ctrl, FR_AB_MAC_CTRL);
 468
 469         efx_reado(efx, &reg, FR_AB_GLB_CTL);
 470         EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGTX, 1);
 471         EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGRX, 1);
 472         EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_EM, 1);
 473         efx_writeo(efx, &reg, FR_AB_GLB_CTL);
 474
 475         count = 0;
 476         while (1) {
 477                 efx_reado(efx, &reg, FR_AB_GLB_CTL);
 478                 if (!EFX_OWORD_FIELD(reg, FRF_AB_RST_XGTX) &&
 479                     !EFX_OWORD_FIELD(reg, FRF_AB_RST_XGRX) &&
 480                     !EFX_OWORD_FIELD(reg, FRF_AB_RST_EM)) {
 481                         netif_dbg(efx, hw, efx->net_dev,
 482                                   "Completed MAC reset after %d loops\n",
 483                                   count);
 484                         break;
 485                 }
 486                 if (count > 20) {
 487                         netif_err(efx, hw, efx->net_dev, "MAC reset failed\n");
 488                         break;
 489                 }
 490                 count++;
 491                 udelay(10);
 492         }
 493
 494         /* Ensure the correct MAC is selected before statistics
 495          * are re-enabled by the caller */
 496         efx_writeo(efx, &mac_ctrl, FR_AB_MAC_CTRL);
 497
 498         falcon_setup_xaui(efx);
 499 }
 500
 501 void falcon_drain_tx_fifo(struct efx_nic *efx)
 502 {
 503         efx_oword_t reg;
 504
 505         if ((efx_nic_rev(efx) < EFX_REV_FALCON_B0) ||
 506             (efx->loopback_mode != LOOPBACK_NONE))
 507                 return;
 508
 509         efx_reado(efx, &reg, FR_AB_MAC_CTRL);
 510         /* There is no point in draining more than once */
 511         if (EFX_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN))
 512                 return;
 513
 514         falcon_reset_macs(efx);
 515 }
 516
 517 static void falcon_deconfigure_mac_wrapper(struct efx_nic *efx)
 518 {
 519         efx_oword_t reg;
 520
 521         if (efx_nic_rev(efx) < EFX_REV_FALCON_B0)
 522                 return;
 523
 524         /* Isolate the MAC -> RX */
 525         efx_reado(efx, &reg, FR_AZ_RX_CFG);
 526         EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 0);
 527         efx_writeo(efx, &reg, FR_AZ_RX_CFG);
 528
 529         /* Isolate TX -> MAC */
 530         falcon_drain_tx_fifo(efx);
 531 }
 532
 533 void falcon_reconfigure_mac_wrapper(struct efx_nic *efx)
 534 {
 535         struct efx_link_state *link_state = &efx->link_state;
 536         efx_oword_t reg;
 537         int link_speed, isolate;
 538
 539         isolate = (efx->reset_pending != RESET_TYPE_NONE);
 540
 541         switch (link_state->speed) {
 542         case 10000: link_speed = 3; break;
 543         case 1000:  link_speed = 2; break;
 544         case 100:   link_speed = 1; break;
 545         default:    link_speed = 0; break;
 546         }
 547         /* MAC_LINK_STATUS controls MAC backpressure but doesn't work
 548          * as advertised.  Disable to ensure packets are not
 549          * indefinitely held and TX queue can be flushed at any point
 550          * while the link is down. */
 551         EFX_POPULATE_OWORD_5(reg,
 552                              FRF_AB_MAC_XOFF_VAL, 0xffff /* max pause time */,
 553                              FRF_AB_MAC_BCAD_ACPT, 1,
 554                              FRF_AB_MAC_UC_PROM, efx->promiscuous,
 555                              FRF_AB_MAC_LINK_STATUS, 1, /* always set */
 556                              FRF_AB_MAC_SPEED, link_speed);
 557         /* On B0, MAC backpressure can be disabled and packets get
 558          * discarded. */
 559         if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
 560                 EFX_SET_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN,
 561                                     !link_state->up || isolate);
 562         }
 563
 564         efx_writeo(efx, &reg, FR_AB_MAC_CTRL);
 565
 566         /* Restore the multicast hash registers. */
 567         falcon_push_multicast_hash(efx);
 568
 569         efx_reado(efx, &reg, FR_AZ_RX_CFG);
 570         /* Enable XOFF signal from RX FIFO (we enabled it during NIC
 571          * initialisation but it may read back as 0) */
 572         EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, 1);
 573         /* Unisolate the MAC -> RX */
 574         if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
 575                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, !isolate);
 576         efx_writeo(efx, &reg, FR_AZ_RX_CFG);
 577 }
 578
 579 static void falcon_stats_request(struct efx_nic *efx)
 580 {
 581         struct falcon_nic_data *nic_data = efx->nic_data;
 582         efx_oword_t reg;
 583
 584         WARN_ON(nic_data->stats_pending);
 585         WARN_ON(nic_data->stats_disable_count);
 586
 587         if (nic_data->stats_dma_done == NULL)
 588                 return; /* no mac selected */
 589
 590         *nic_data->stats_dma_done = FALCON_STATS_NOT_DONE;
 591         nic_data->stats_pending = true;
 592         wmb(); /* ensure done flag is clear */
 593
 594         /* Initiate DMA transfer of stats */
 595         EFX_POPULATE_OWORD_2(reg,
 596                              FRF_AB_MAC_STAT_DMA_CMD, 1,
 597                              FRF_AB_MAC_STAT_DMA_ADR,
 598                              efx->stats_buffer.dma_addr);
 599         efx_writeo(efx, &reg, FR_AB_MAC_STAT_DMA);
 600
 601         mod_timer(&nic_data->stats_timer, round_jiffies_up(jiffies + HZ / 2));
 602 }
 603
 604 static void falcon_stats_complete(struct efx_nic *efx)
 605 {
 606         struct falcon_nic_data *nic_data = efx->nic_data;
 607
 608         if (!nic_data->stats_pending)
 609                 return;
 610
 611         nic_data->stats_pending = 0;
 612         if (*nic_data->stats_dma_done == FALCON_STATS_DONE) {
 613                 rmb(); /* read the done flag before the stats */
 614                 efx->mac_op->update_stats(efx);
 615         } else {
 616                 netif_err(efx, hw, efx->net_dev,
 617                           "timed out waiting for statistics\n");
 618         }
 619 }
 620
 621 static void falcon_stats_timer_func(unsigned long context)
 622 {
 623         struct efx_nic *efx = (struct efx_nic *)context;
 624         struct falcon_nic_data *nic_data = efx->nic_data;
 625
 626         spin_lock(&efx->stats_lock);
 627
 628         falcon_stats_complete(efx);
 629         if (nic_data->stats_disable_count == 0)
 630                 falcon_stats_request(efx);
 631
 632         spin_unlock(&efx->stats_lock);
 633 }
 634
 635 static bool falcon_loopback_link_poll(struct efx_nic *efx)
 636 {
 637         struct efx_link_state old_state = efx->link_state;
 638
 639         WARN_ON(!mutex_is_locked(&efx->mac_lock));
 640         WARN_ON(!LOOPBACK_INTERNAL(efx));
 641
 642         efx->link_state.fd = true;
 643         efx->link_state.fc = efx->wanted_fc;
 644         efx->link_state.up = true;
 645         efx->link_state.speed = 10000;
 646
 647         return !efx_link_state_equal(&efx->link_state, &old_state);
 648 }
 649
 650 static int falcon_reconfigure_port(struct efx_nic *efx)
 651 {
 652         int rc;
 653
 654         WARN_ON(efx_nic_rev(efx) > EFX_REV_FALCON_B0);
 655
 656         /* Poll the PHY link state *before* reconfiguring it. This means we
 657          * will pick up the correct speed (in loopback) to select the correct
 658          * MAC.
 659          */
 660         if (LOOPBACK_INTERNAL(efx))
 661                 falcon_loopback_link_poll(efx);
 662         else
 663                 efx->phy_op->poll(efx);
 664
 665         falcon_stop_nic_stats(efx);
 666         falcon_deconfigure_mac_wrapper(efx);
 667
 668         falcon_reset_macs(efx);
 669
 670         efx->phy_op->reconfigure(efx);
 671         rc = efx->mac_op->reconfigure(efx);
 672         BUG_ON(rc);
 673
 674         falcon_start_nic_stats(efx);
 675
 676         /* Synchronise efx->link_state with the kernel */
 677         efx_link_status_changed(efx);
 678
 679         return 0;
 680 }
 681
 682 /**************************************************************************
 683  *
 684  * PHY access via GMII
 685  *
 686  **************************************************************************
 687  */
 688
 689 /* Wait for GMII access to complete */
 690 static int falcon_gmii_wait(struct efx_nic *efx)
 691 {
 692         efx_oword_t md_stat;
 693         int count;
 694
 695         /* wait upto 50ms - taken max from datasheet */
 696         for (count = 0; count < 5000; count++) {
 697                 efx_reado(efx, &md_stat, FR_AB_MD_STAT);
 698                 if (EFX_OWORD_FIELD(md_stat, FRF_AB_MD_BSY) == 0) {
 699                         if (EFX_OWORD_FIELD(md_stat, FRF_AB_MD_LNFL) != 0 ||
 700                             EFX_OWORD_FIELD(md_stat, FRF_AB_MD_BSERR) != 0) {
 701                                 netif_err(efx, hw, efx->net_dev,
 702                                           "error from GMII access "
 703                                           EFX_OWORD_FMT"\n",
 704                                           EFX_OWORD_VAL(md_stat));
 705                                 return -EIO;
 706                         }
 707                         return 0;
 708                 }
 709                 udelay(10);
 710         }
 711         netif_err(efx, hw, efx->net_dev, "timed out waiting for GMII\n");
 712         return -ETIMEDOUT;
 713 }
 714
 715 /* Write an MDIO register of a PHY connected to Falcon. */
 716 static int falcon_mdio_write(struct net_device *net_dev,
 717                              int prtad, int devad, u16 addr, u16 value)
 718 {
 719         struct efx_nic *efx = netdev_priv(net_dev);
 720         struct falcon_nic_data *nic_data = efx->nic_data;
 721         efx_oword_t reg;
 722         int rc;
 723
 724         netif_vdbg(efx, hw, efx->net_dev,
 725                    "writing MDIO %d register %d.%d with 0x%04x\n",
 726                     prtad, devad, addr, value);
 727
 728         mutex_lock(&nic_data->mdio_lock);
 729
 730         /* Check MDIO not currently being accessed */
 731         rc = falcon_gmii_wait(efx);
 732         if (rc)
 733                 goto out;
 734
 735         /* Write the address/ID register */
 736         EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr);
 737         efx_writeo(efx, &reg, FR_AB_MD_PHY_ADR);
 738
 739         EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad,
 740                              FRF_AB_MD_DEV_ADR, devad);
 741         efx_writeo(efx, &reg, FR_AB_MD_ID);
 742
 743         /* Write data */
 744         EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_TXD, value);
 745         efx_writeo(efx, &reg, FR_AB_MD_TXD);
 746
 747         EFX_POPULATE_OWORD_2(reg,
 748                              FRF_AB_MD_WRC, 1,
 749                              FRF_AB_MD_GC, 0);
 750         efx_writeo(efx, &reg, FR_AB_MD_CS);
 751
 752         /* Wait for data to be written */
 753         rc = falcon_gmii_wait(efx);
 754         if (rc) {
 755                 /* Abort the write operation */
 756                 EFX_POPULATE_OWORD_2(reg,
 757                                      FRF_AB_MD_WRC, 0,
 758                                      FRF_AB_MD_GC, 1);
 759                 efx_writeo(efx, &reg, FR_AB_MD_CS);
 760                 udelay(10);
 761         }
 762
 763 out:
 764         mutex_unlock(&nic_data->mdio_lock);
 765         return rc;
 766 }
 767
 768 /* Read an MDIO register of a PHY connected to Falcon. */
 769 static int falcon_mdio_read(struct net_device *net_dev,
 770                             int prtad, int devad, u16 addr)
 771 {
 772         struct efx_nic *efx = netdev_priv(net_dev);
 773         struct falcon_nic_data *nic_data = efx->nic_data;
 774         efx_oword_t reg;
 775         int rc;
 776
 777         mutex_lock(&nic_data->mdio_lock);
 778
 779         /* Check MDIO not currently being accessed */
 780         rc = falcon_gmii_wait(efx);
 781         if (rc)
 782                 goto out;
 783
 784         EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr);
 785         efx_writeo(efx, &reg, FR_AB_MD_PHY_ADR);
 786
 787         EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad,
 788                              FRF_AB_MD_DEV_ADR, devad);
 789         efx_writeo(efx, &reg, FR_AB_MD_ID);
 790
 791         /* Request data to be read */
 792         EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_RDC, 1, FRF_AB_MD_GC, 0);
 793         efx_writeo(efx, &reg, FR_AB_MD_CS);
 794
 795         /* Wait for data to become available */
 796         rc = falcon_gmii_wait(efx);
 797         if (rc == 0) {
 798                 efx_reado(efx, &reg, FR_AB_MD_RXD);
 799                 rc = EFX_OWORD_FIELD(reg, FRF_AB_MD_RXD);
 800                 netif_vdbg(efx, hw, efx->net_dev,
 801                            "read from MDIO %d register %d.%d, got %04x\n",
 802                            prtad, devad, addr, rc);
 803         } else {
 804                 /* Abort the read operation */
 805                 EFX_POPULATE_OWORD_2(reg,
 806                                      FRF_AB_MD_RIC, 0,
 807                                      FRF_AB_MD_GC, 1);
 808                 efx_writeo(efx, &reg, FR_AB_MD_CS);
 809
 810                 netif_dbg(efx, hw, efx->net_dev,
 811                           "read from MDIO %d register %d.%d, got error %d\n",
 812                           prtad, devad, addr, rc);
 813         }
 814
 815 out:
 816         mutex_unlock(&nic_data->mdio_lock);
 817         return rc;
 818 }
 819
 820 /* This call is responsible for hooking in the MAC and PHY operations */
 821 static int falcon_probe_port(struct efx_nic *efx)
 822 {
 823         struct falcon_nic_data *nic_data = efx->nic_data;
 824         int rc;
 825
 826         switch (efx->phy_type) {
 827         case PHY_TYPE_SFX7101:
 828                 efx->phy_op = &falcon_sfx7101_phy_ops;
 829                 break;
 830         case PHY_TYPE_QT2022C2:
 831         case PHY_TYPE_QT2025C:
 832                 efx->phy_op = &falcon_qt202x_phy_ops;
 833                 break;
 834         case PHY_TYPE_TXC43128:
 835                 efx->phy_op = &falcon_txc_phy_ops;
 836                 break;
 837         default:
 838                 netif_err(efx, probe, efx->net_dev, "Unknown PHY type %d\n",
 839                           efx->phy_type);
 840                 return -ENODEV;
 841         }
 842
 843         /* Fill out MDIO structure and loopback modes */
 844         mutex_init(&nic_data->mdio_lock);
 845         efx->mdio.mdio_read = falcon_mdio_read;
 846         efx->mdio.mdio_write = falcon_mdio_write;
 847         rc = efx->phy_op->probe(efx);
 848         if (rc != 0)
 849                 return rc;
 850
 851         /* Initial assumption */
 852         efx->link_state.speed = 10000;
 853         efx->link_state.fd = true;
 854
 855         /* Hardware flow ctrl. FalconA RX FIFO too small for pause generation */
 856         if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
 857                 efx->wanted_fc = EFX_FC_RX | EFX_FC_TX;
 858         else
 859                 efx->wanted_fc = EFX_FC_RX;
 860         if (efx->mdio.mmds & MDIO_DEVS_AN)
 861                 efx->wanted_fc |= EFX_FC_AUTO;
 862
 863         /* Allocate buffer for stats */
 864         rc = efx_nic_alloc_buffer(efx, &efx->stats_buffer,
 865                                   FALCON_MAC_STATS_SIZE);
 866         if (rc)
 867                 return rc;
 868         netif_dbg(efx, probe, efx->net_dev,
 869                   "stats buffer at %llx (virt %p phys %llx)\n",
 870                   (u64)efx->stats_buffer.dma_addr,
 871                   efx->stats_buffer.addr,
 872                   (u64)virt_to_phys(efx->stats_buffer.addr));
 873         nic_data->stats_dma_done = efx->stats_buffer.addr + XgDmaDone_offset;
 874
 875         return 0;
 876 }
 877
 878 static void falcon_remove_port(struct efx_nic *efx)
 879 {
 880         efx->phy_op->remove(efx);
 881         efx_nic_free_buffer(efx, &efx->stats_buffer);
 882 }
 883
 884 /* Global events are basically PHY events */
 885 static bool
 886 falcon_handle_global_event(struct efx_channel *channel, efx_qword_t *event)
 887 {
 888         struct efx_nic *efx = channel->efx;
 889
 890         if (EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_G_PHY0_INTR) ||
 891             EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XG_PHY0_INTR) ||
 892             EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XFP_PHY0_INTR))
 893                 /* Ignored */
 894                 return true;
 895
 896         if ((efx_nic_rev(efx) == EFX_REV_FALCON_B0) &&
 897             EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_XG_MGT_INTR)) {
 898                 efx->xmac_poll_required = true;
 899                 return true;
 900         }
 901
 902         if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1 ?
 903             EFX_QWORD_FIELD(*event, FSF_AA_GLB_EV_RX_RECOVERY) :
 904             EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_RX_RECOVERY)) {
 905                 netif_err(efx, rx_err, efx->net_dev,
 906                           "channel %d seen global RX_RESET event. Resetting.\n",
 907                           channel->channel);
 908
 909                 atomic_inc(&efx->rx_reset);
 910                 efx_schedule_reset(efx, EFX_WORKAROUND_6555(efx) ?
 911                                    RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
 912                 return true;
 913         }
 914
 915         return false;
 916 }
 917
 918 /**************************************************************************
 919  *
 920  * Falcon test code
 921  *
 922  **************************************************************************/
 923
 924 static int
 925 falcon_read_nvram(struct efx_nic *efx, struct falcon_nvconfig *nvconfig_out)
 926 {
 927         struct falcon_nic_data *nic_data = efx->nic_data;
 928         struct falcon_nvconfig *nvconfig;
 929         struct efx_spi_device *spi;
 930         void *region;
 931         int rc, magic_num, struct_ver;
 932         __le16 *word, *limit;
 933         u32 csum;
 934
 935         if (efx_spi_present(&nic_data->spi_flash))
 936                 spi = &nic_data->spi_flash;
 937         else if (efx_spi_present(&nic_data->spi_eeprom))
 938                 spi = &nic_data->spi_eeprom;
 939         else
 940                 return -EINVAL;
 941
 942         region = kmalloc(FALCON_NVCONFIG_END, GFP_KERNEL);
 943         if (!region)
 944                 return -ENOMEM;
 945         nvconfig = region + FALCON_NVCONFIG_OFFSET;
 946
 947         mutex_lock(&nic_data->spi_lock);
 948         rc = falcon_spi_read(efx, spi, 0, FALCON_NVCONFIG_END, NULL, region);
 949         mutex_unlock(&nic_data->spi_lock);
 950         if (rc) {
 951                 netif_err(efx, hw, efx->net_dev, "Failed to read %s\n",
 952                           efx_spi_present(&nic_data->spi_flash) ?
 953                           "flash" : "EEPROM");
 954                 rc = -EIO;
 955                 goto out;
 956         }
 957
 958         magic_num = le16_to_cpu(nvconfig->board_magic_num);
 959         struct_ver = le16_to_cpu(nvconfig->board_struct_ver);
 960
 961         rc = -EINVAL;
 962         if (magic_num != FALCON_NVCONFIG_BOARD_MAGIC_NUM) {
 963                 netif_err(efx, hw, efx->net_dev,
 964                           "NVRAM bad magic 0x%x\n", magic_num);
 965                 goto out;
 966         }
 967         if (struct_ver < 2) {
 968                 netif_err(efx, hw, efx->net_dev,
 969                           "NVRAM has ancient version 0x%x\n", struct_ver);
 970                 goto out;
 971         } else if (struct_ver < 4) {
 972                 word = &nvconfig->board_magic_num;
 973                 limit = (__le16 *) (nvconfig + 1);
 974         } else {
 975                 word = region;
 976                 limit = region + FALCON_NVCONFIG_END;
 977         }
 978         for (csum = 0; word < limit; ++word)
 979                 csum += le16_to_cpu(*word);
 980
 981         if (~csum & 0xffff) {
 982                 netif_err(efx, hw, efx->net_dev,
 983                           "NVRAM has incorrect checksum\n");
 984                 goto out;
 985         }
 986
 987         rc = 0;
 988         if (nvconfig_out)
 989                 memcpy(nvconfig_out, nvconfig, sizeof(*nvconfig));
 990
 991  out:
 992         kfree(region);
 993         return rc;
 994 }
 995
 996 static int falcon_test_nvram(struct efx_nic *efx)
 997 {
 998         return falcon_read_nvram(efx, NULL);
 999 }
1000
1001 static const struct efx_nic_register_test falcon_b0_register_tests[] = {
1002         { FR_AZ_ADR_REGION,
1003           EFX_OWORD32(0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF) },
1004         { FR_AZ_RX_CFG,
1005           EFX_OWORD32(0xFFFFFFFE, 0x00017FFF, 0x00000000, 0x00000000) },
1006         { FR_AZ_TX_CFG,
1007           EFX_OWORD32(0x7FFF0037, 0x00000000, 0x00000000, 0x00000000) },
1008         { FR_AZ_TX_RESERVED,
1009           EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
1010         { FR_AB_MAC_CTRL,
1011           EFX_OWORD32(0xFFFF0000, 0x00000000, 0x00000000, 0x00000000) },
1012         { FR_AZ_SRM_TX_DC_CFG,
1013           EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
1014         { FR_AZ_RX_DC_CFG,
1015           EFX_OWORD32(0x0000000F, 0x00000000, 0x00000000, 0x00000000) },
1016         { FR_AZ_RX_DC_PF_WM,
1017           EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
1018         { FR_BZ_DP_CTRL,
1019           EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
1020         { FR_AB_GM_CFG2,
1021           EFX_OWORD32(0x00007337, 0x00000000, 0x00000000, 0x00000000) },
1022         { FR_AB_GMF_CFG0,
1023           EFX_OWORD32(0x00001F1F, 0x00000000, 0x00000000, 0x00000000) },
1024         { FR_AB_XM_GLB_CFG,
1025           EFX_OWORD32(0x00000C68, 0x00000000, 0x00000000, 0x00000000) },
1026         { FR_AB_XM_TX_CFG,
1027           EFX_OWORD32(0x00080164, 0x00000000, 0x00000000, 0x00000000) },
1028         { FR_AB_XM_RX_CFG,
1029           EFX_OWORD32(0x07100A0C, 0x00000000, 0x00000000, 0x00000000) },
1030         { FR_AB_XM_RX_PARAM,
1031           EFX_OWORD32(0x00001FF8, 0x00000000, 0x00000000, 0x00000000) },
1032         { FR_AB_XM_FC,
1033           EFX_OWORD32(0xFFFF0001, 0x00000000, 0x00000000, 0x00000000) },
1034         { FR_AB_XM_ADR_LO,
1035           EFX_OWORD32(0xFFFFFFFF, 0x00000000, 0x00000000, 0x00000000) },
1036         { FR_AB_XX_SD_CTL,
1037           EFX_OWORD32(0x0003FF0F, 0x00000000, 0x00000000, 0x00000000) },
1038 };
1039
1040 static int falcon_b0_test_registers(struct efx_nic *efx)
1041 {
1042         return efx_nic_test_registers(efx, falcon_b0_register_tests,
1043                                       ARRAY_SIZE(falcon_b0_register_tests));
1044 }
1045
1046 /**************************************************************************
1047  *
1048  * Device reset
1049  *
1050  **************************************************************************
1051  */
1052
1053 /* Resets NIC to known state.  This routine must be called in process
1054  * context and is allowed to sleep. */
1055 static int __falcon_reset_hw(struct efx_nic *efx, enum reset_type method)
1056 {
1057         struct falcon_nic_data *nic_data = efx->nic_data;
1058         efx_oword_t glb_ctl_reg_ker;
1059         int rc;
1060
1061         netif_dbg(efx, hw, efx->net_dev, "performing %s hardware reset\n",
1062                   RESET_TYPE(method));
1063
1064         /* Initiate device reset */
1065         if (method == RESET_TYPE_WORLD) {
1066                 rc = pci_save_state(efx->pci_dev);
1067                 if (rc) {
1068                         netif_err(efx, drv, efx->net_dev,
1069                                   "failed to backup PCI state of primary "
1070                                   "function prior to hardware reset\n");
1071                         goto fail1;
1072                 }
1073                 if (efx_nic_is_dual_func(efx)) {
1074                         rc = pci_save_state(nic_data->pci_dev2);
1075                         if (rc) {
1076                                 netif_err(efx, drv, efx->net_dev,
1077                                           "failed to backup PCI state of "
1078                                           "secondary function prior to "
1079                                           "hardware reset\n");
1080                                 goto fail2;
1081                         }
1082                 }
1083
1084                 EFX_POPULATE_OWORD_2(glb_ctl_reg_ker,
1085                                      FRF_AB_EXT_PHY_RST_DUR,
1086                                      FFE_AB_EXT_PHY_RST_DUR_10240US,
1087                                      FRF_AB_SWRST, 1);
1088         } else {
1089                 EFX_POPULATE_OWORD_7(glb_ctl_reg_ker,
1090                                      /* exclude PHY from "invisible" reset */
1091                                      FRF_AB_EXT_PHY_RST_CTL,
1092                                      method == RESET_TYPE_INVISIBLE,
1093                                      /* exclude EEPROM/flash and PCIe */
1094                                      FRF_AB_PCIE_CORE_RST_CTL, 1,
1095                                      FRF_AB_PCIE_NSTKY_RST_CTL, 1,
1096                                      FRF_AB_PCIE_SD_RST_CTL, 1,
1097                                      FRF_AB_EE_RST_CTL, 1,
1098                                      FRF_AB_EXT_PHY_RST_DUR,
1099                                      FFE_AB_EXT_PHY_RST_DUR_10240US,
1100                                      FRF_AB_SWRST, 1);
1101         }
1102         efx_writeo(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL);
1103
1104         netif_dbg(efx, hw, efx->net_dev, "waiting for hardware reset\n");
1105         schedule_timeout_uninterruptible(HZ / 20);
1106
1107         /* Restore PCI configuration if needed */
1108         if (method == RESET_TYPE_WORLD) {
1109                 if (efx_nic_is_dual_func(efx)) {
1110                         rc = pci_restore_state(nic_data->pci_dev2);
1111                         if (rc) {
1112                                 netif_err(efx, drv, efx->net_dev,
1113                                           "failed to restore PCI config for "
1114                                           "the secondary function\n");
1115                                 goto fail3;
1116                         }
1117                 }
1118                 rc = pci_restore_state(efx->pci_dev);
1119                 if (rc) {
1120                         netif_err(efx, drv, efx->net_dev,
1121                                   "failed to restore PCI config for the "
1122                                   "primary function\n");
1123                         goto fail4;
1124                 }
1125                 netif_dbg(efx, drv, efx->net_dev,
1126                           "successfully restored PCI config\n");
1127         }
1128
1129         /* Assert that reset complete */
1130         efx_reado(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL);
1131         if (EFX_OWORD_FIELD(glb_ctl_reg_ker, FRF_AB_SWRST) != 0) {
1132                 rc = -ETIMEDOUT;
1133                 netif_err(efx, hw, efx->net_dev,
1134                           "timed out waiting for hardware reset\n");
1135                 goto fail5;
1136         }
1137         netif_dbg(efx, hw, efx->net_dev, "hardware reset complete\n");
1138
1139         return 0;
1140
1141         /* pci_save_state() and pci_restore_state() MUST be called in pairs */
1142 fail2:
1143 fail3:
1144         pci_restore_state(efx->pci_dev);
1145 fail1:
1146 fail4:
1147 fail5:
1148         return rc;
1149 }
1150
1151 static int falcon_reset_hw(struct efx_nic *efx, enum reset_type method)
1152 {
1153         struct falcon_nic_data *nic_data = efx->nic_data;
1154         int rc;
1155
1156         mutex_lock(&nic_data->spi_lock);
1157         rc = __falcon_reset_hw(efx, method);
1158         mutex_unlock(&nic_data->spi_lock);
1159
1160         return rc;
1161 }
1162
1163 static void falcon_monitor(struct efx_nic *efx)
1164 {
1165         bool link_changed;
1166         int rc;
1167
1168         BUG_ON(!mutex_is_locked(&efx->mac_lock));
1169
1170         rc = falcon_board(efx)->type->monitor(efx);
1171         if (rc) {
1172                 netif_err(efx, hw, efx->net_dev,
1173                           "Board sensor %s; shutting down PHY\n",
1174                           (rc == -ERANGE) ? "reported fault" : "failed");
1175                 efx->phy_mode |= PHY_MODE_LOW_POWER;
1176                 rc = __efx_reconfigure_port(efx);
1177                 WARN_ON(rc);
1178         }
1179
1180         if (LOOPBACK_INTERNAL(efx))
1181                 link_changed = falcon_loopback_link_poll(efx);
1182         else
1183                 link_changed = efx->phy_op->poll(efx);
1184
1185         if (link_changed) {
1186                 falcon_stop_nic_stats(efx);
1187                 falcon_deconfigure_mac_wrapper(efx);
1188
1189                 falcon_reset_macs(efx);
1190                 rc = efx->mac_op->reconfigure(efx);
1191                 BUG_ON(rc);
1192
1193                 falcon_start_nic_stats(efx);
1194
1195                 efx_link_status_changed(efx);
1196         }
1197
1198         falcon_poll_xmac(efx);
1199 }
1200
1201 /* Zeroes out the SRAM contents.  This routine must be called in
1202  * process context and is allowed to sleep.
1203  */
1204 static int falcon_reset_sram(struct efx_nic *efx)
1205 {
1206         efx_oword_t srm_cfg_reg_ker, gpio_cfg_reg_ker;
1207         int count;
1208
1209         /* Set the SRAM wake/sleep GPIO appropriately. */
1210         efx_reado(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL);
1211         EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OEN, 1);
1212         EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OUT, 1);
1213         efx_writeo(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL);
1214
1215         /* Initiate SRAM reset */
1216         EFX_POPULATE_OWORD_2(srm_cfg_reg_ker,
1217                              FRF_AZ_SRM_INIT_EN, 1,
1218                              FRF_AZ_SRM_NB_SZ, 0);
1219         efx_writeo(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG);
1220
1221         /* Wait for SRAM reset to complete */
1222         count = 0;
1223         do {
1224                 netif_dbg(efx, hw, efx->net_dev,
1225                           "waiting for SRAM reset (attempt %d)...\n", count);
1226
1227                 /* SRAM reset is slow; expect around 16ms */
1228                 schedule_timeout_uninterruptible(HZ / 50);
1229
1230                 /* Check for reset complete */
1231                 efx_reado(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG);
1232                 if (!EFX_OWORD_FIELD(srm_cfg_reg_ker, FRF_AZ_SRM_INIT_EN)) {
1233                         netif_dbg(efx, hw, efx->net_dev,
1234                                   "SRAM reset complete\n");
1235
1236                         return 0;
1237                 }
1238         } while (++count < 20); /* wait upto 0.4 sec */
1239
1240         netif_err(efx, hw, efx->net_dev, "timed out waiting for SRAM reset\n");
1241         return -ETIMEDOUT;
1242 }
1243
1244 static void falcon_spi_device_init(struct efx_nic *efx,
1245                                   struct efx_spi_device *spi_device,
1246                                   unsigned int device_id, u32 device_type)
1247 {
1248         if (device_type != 0) {
1249                 spi_device->device_id = device_id;
1250                 spi_device->size =
1251                         1 << SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_SIZE);
1252                 spi_device->addr_len =
1253                         SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ADDR_LEN);
1254                 spi_device->munge_address = (spi_device->size == 1 << 9 &&
1255                                              spi_device->addr_len == 1);
1256                 spi_device->erase_command =
1257                         SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ERASE_CMD);
1258                 spi_device->erase_size =
1259                         1 << SPI_DEV_TYPE_FIELD(device_type,
1260                                                 SPI_DEV_TYPE_ERASE_SIZE);
1261                 spi_device->block_size =
1262                         1 << SPI_DEV_TYPE_FIELD(device_type,
1263                                                 SPI_DEV_TYPE_BLOCK_SIZE);
1264         } else {
1265                 spi_device->size = 0;
1266         }
1267 }
1268
1269 /* Extract non-volatile configuration */
1270 static int falcon_probe_nvconfig(struct efx_nic *efx)
1271 {
1272         struct falcon_nic_data *nic_data = efx->nic_data;
1273         struct falcon_nvconfig *nvconfig;
1274         int rc;
1275
1276         nvconfig = kmalloc(sizeof(*nvconfig), GFP_KERNEL);
1277         if (!nvconfig)
1278                 return -ENOMEM;
1279
1280         rc = falcon_read_nvram(efx, nvconfig);
1281         if (rc)
1282                 goto out;
1283
1284         efx->phy_type = nvconfig->board_v2.port0_phy_type;
1285         efx->mdio.prtad = nvconfig->board_v2.port0_phy_addr;
1286
1287         if (le16_to_cpu(nvconfig->board_struct_ver) >= 3) {
1288                 falcon_spi_device_init(
1289                         efx, &nic_data->spi_flash, FFE_AB_SPI_DEVICE_FLASH,
1290                         le32_to_cpu(nvconfig->board_v3
1291                                     .spi_device_type[FFE_AB_SPI_DEVICE_FLASH]));
1292                 falcon_spi_device_init(
1293                         efx, &nic_data->spi_eeprom, FFE_AB_SPI_DEVICE_EEPROM,
1294                         le32_to_cpu(nvconfig->board_v3
1295                                     .spi_device_type[FFE_AB_SPI_DEVICE_EEPROM]));
1296         }
1297
1298         /* Read the MAC addresses */
1299         memcpy(efx->mac_address, nvconfig->mac_address[0], ETH_ALEN);
1300
1301         netif_dbg(efx, probe, efx->net_dev, "PHY is %d phy_id %d\n",
1302                   efx->phy_type, efx->mdio.prtad);
1303
1304         rc = falcon_probe_board(efx,
1305                                 le16_to_cpu(nvconfig->board_v2.board_revision));
1306 out:
1307         kfree(nvconfig);
1308         return rc;
1309 }
1310
1311 /* Probe all SPI devices on the NIC */
1312 static void falcon_probe_spi_devices(struct efx_nic *efx)
1313 {
1314         struct falcon_nic_data *nic_data = efx->nic_data;
1315         efx_oword_t nic_stat, gpio_ctl, ee_vpd_cfg;
1316         int boot_dev;
1317
1318         efx_reado(efx, &gpio_ctl, FR_AB_GPIO_CTL);
1319         efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
1320         efx_reado(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0);
1321
1322         if (EFX_OWORD_FIELD(gpio_ctl, FRF_AB_GPIO3_PWRUP_VALUE)) {
1323                 boot_dev = (EFX_OWORD_FIELD(nic_stat, FRF_AB_SF_PRST) ?
1324                             FFE_AB_SPI_DEVICE_FLASH : FFE_AB_SPI_DEVICE_EEPROM);
1325                 netif_dbg(efx, probe, efx->net_dev, "Booted from %s\n",
1326                           boot_dev == FFE_AB_SPI_DEVICE_FLASH ?
1327                           "flash" : "EEPROM");
1328         } else {
1329                 /* Disable VPD and set clock dividers to safe
1330                  * values for initial programming. */
1331                 boot_dev = -1;
1332                 netif_dbg(efx, probe, efx->net_dev,
1333                           "Booted from internal ASIC settings;"
1334                           " setting SPI config\n");
1335                 EFX_POPULATE_OWORD_3(ee_vpd_cfg, FRF_AB_EE_VPD_EN, 0,
1336                                      /* 125 MHz / 7 ~= 20 MHz */
1337                                      FRF_AB_EE_SF_CLOCK_DIV, 7,
1338                                      /* 125 MHz / 63 ~= 2 MHz */
1339                                      FRF_AB_EE_EE_CLOCK_DIV, 63);
1340                 efx_writeo(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0);
1341         }
1342
1343         mutex_init(&nic_data->spi_lock);
1344
1345         if (boot_dev == FFE_AB_SPI_DEVICE_FLASH)
1346                 falcon_spi_device_init(efx, &nic_data->spi_flash,
1347                                        FFE_AB_SPI_DEVICE_FLASH,
1348                                        default_flash_type);
1349         if (boot_dev == FFE_AB_SPI_DEVICE_EEPROM)
1350                 falcon_spi_device_init(efx, &nic_data->spi_eeprom,
1351                                        FFE_AB_SPI_DEVICE_EEPROM,
1352                                        large_eeprom_type);
1353 }
1354
1355 static int falcon_probe_nic(struct efx_nic *efx)
1356 {
1357         struct falcon_nic_data *nic_data;
1358         struct falcon_board *board;
1359         int rc;
1360
1361         /* Allocate storage for hardware specific data */
1362         nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
1363         if (!nic_data)
1364                 return -ENOMEM;
1365         efx->nic_data = nic_data;
1366
1367         rc = -ENODEV;
1368
1369         if (efx_nic_fpga_ver(efx) != 0) {
1370                 netif_err(efx, probe, efx->net_dev,
1371                           "Falcon FPGA not supported\n");
1372                 goto fail1;
1373         }
1374
1375         if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1) {
1376                 efx_oword_t nic_stat;
1377                 struct pci_dev *dev;
1378                 u8 pci_rev = efx->pci_dev->revision;
1379
1380                 if ((pci_rev == 0xff) || (pci_rev == 0)) {
1381                         netif_err(efx, probe, efx->net_dev,
1382                                   "Falcon rev A0 not supported\n");
1383                         goto fail1;
1384                 }
1385                 efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
1386                 if (EFX_OWORD_FIELD(nic_stat, FRF_AB_STRAP_10G) == 0) {
1387                         netif_err(efx, probe, efx->net_dev,
1388                                   "Falcon rev A1 1G not supported\n");
1389                         goto fail1;
1390                 }
1391                 if (EFX_OWORD_FIELD(nic_stat, FRF_AA_STRAP_PCIE) == 0) {
1392                         netif_err(efx, probe, efx->net_dev,
1393                                   "Falcon rev A1 PCI-X not supported\n");
1394                         goto fail1;
1395                 }
1396
1397                 dev = pci_dev_get(efx->pci_dev);
1398                 while ((dev = pci_get_device(EFX_VENDID_SFC, FALCON_A_S_DEVID,
1399                                              dev))) {
1400                         if (dev->bus == efx->pci_dev->bus &&
1401                             dev->devfn == efx->pci_dev->devfn + 1) {
1402                                 nic_data->pci_dev2 = dev;
1403                                 break;
1404                         }
1405                 }
1406                 if (!nic_data->pci_dev2) {
1407                         netif_err(efx, probe, efx->net_dev,
1408                                   "failed to find secondary function\n");
1409                         rc = -ENODEV;
1410                         goto fail2;
1411                 }
1412         }
1413
1414         /* Now we can reset the NIC */
1415         rc = __falcon_reset_hw(efx, RESET_TYPE_ALL);
1416         if (rc) {
1417                 netif_err(efx, probe, efx->net_dev, "failed to reset NIC\n");
1418                 goto fail3;
1419         }
1420
1421         /* Allocate memory for INT_KER */
1422         rc = efx_nic_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t));
1423         if (rc)
1424                 goto fail4;
1425         BUG_ON(efx->irq_status.dma_addr & 0x0f);
1426
1427         netif_dbg(efx, probe, efx->net_dev,
1428                   "INT_KER at %llx (virt %p phys %llx)\n",
1429                   (u64)efx->irq_status.dma_addr,
1430                   efx->irq_status.addr,
1431                   (u64)virt_to_phys(efx->irq_status.addr));
1432
1433         falcon_probe_spi_devices(efx);
1434
1435         /* Read in the non-volatile configuration */
1436         rc = falcon_probe_nvconfig(efx);
1437         if (rc) {
1438                 if (rc == -EINVAL)
1439                         netif_err(efx, probe, efx->net_dev, "NVRAM is invalid\n");
1440                 goto fail5;
1441         }
1442
1443         /* Initialise I2C adapter */
1444         board = falcon_board(efx);
1445         board->i2c_adap.owner = THIS_MODULE;
1446         board->i2c_data = falcon_i2c_bit_operations;
1447         board->i2c_data.data = efx;
1448         board->i2c_adap.algo_data = &board->i2c_data;
1449         board->i2c_adap.dev.parent = &efx->pci_dev->dev;
1450         strlcpy(board->i2c_adap.name, "SFC4000 GPIO",
1451                 sizeof(board->i2c_adap.name));
1452         rc = i2c_bit_add_bus(&board->i2c_adap);
1453         if (rc)
1454                 goto fail5;
1455
1456         rc = falcon_board(efx)->type->init(efx);
1457         if (rc) {
1458                 netif_err(efx, probe, efx->net_dev,
1459                           "failed to initialise board\n");
1460                 goto fail6;
1461         }
1462
1463         nic_data->stats_disable_count = 1;
1464         setup_timer(&nic_data->stats_timer, &falcon_stats_timer_func,
1465                     (unsigned long)efx);
1466
1467         return 0;
1468
1469  fail6:
1470         BUG_ON(i2c_del_adapter(&board->i2c_adap));
1471         memset(&board->i2c_adap, 0, sizeof(board->i2c_adap));
1472  fail5:
1473         efx_nic_free_buffer(efx, &efx->irq_status);
1474  fail4:
1475  fail3:
1476         if (nic_data->pci_dev2) {
1477                 pci_dev_put(nic_data->pci_dev2);
1478                 nic_data->pci_dev2 = NULL;
1479         }
1480  fail2:
1481  fail1:
1482         kfree(efx->nic_data);
1483         return rc;
1484 }
1485
1486 static void falcon_init_rx_cfg(struct efx_nic *efx)
1487 {
1488         /* Prior to Siena the RX DMA engine will split each frame at
1489          * intervals of RX_USR_BUF_SIZE (32-byte units). We set it to
1490          * be so large that that never happens. */
1491         const unsigned huge_buf_size = (3 * 4096) >> 5;
1492         /* RX control FIFO thresholds (32 entries) */
1493         const unsigned ctrl_xon_thr = 20;
1494         const unsigned ctrl_xoff_thr = 25;
1495         /* RX data FIFO thresholds (256-byte units; size varies) */
1496         int data_xon_thr = efx_nic_rx_xon_thresh >> 8;
1497         int data_xoff_thr = efx_nic_rx_xoff_thresh >> 8;
1498         efx_oword_t reg;
1499
1500         efx_reado(efx, &reg, FR_AZ_RX_CFG);
1501         if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1) {
1502                 /* Data FIFO size is 5.5K */
1503                 if (data_xon_thr < 0)
1504                         data_xon_thr = 512 >> 8;
1505                 if (data_xoff_thr < 0)
1506                         data_xoff_thr = 2048 >> 8;
1507                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_DESC_PUSH_EN, 0);
1508                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_USR_BUF_SIZE,
1509                                     huge_buf_size);
1510                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_MAC_TH, data_xon_thr);
1511                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_MAC_TH, data_xoff_thr);
1512                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_TX_TH, ctrl_xon_thr);
1513                 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_TX_TH, ctrl_xoff_thr);
1514         } else {
1515                 /* Data FIFO size is 80K; register fields moved */
1516                 if (data_xon_thr < 0)
1517                         data_xon_thr = 27648 >> 8; /* ~3*max MTU */
1518                 if (data_xoff_thr < 0)
1519                         data_xoff_thr = 54272 >> 8; /* ~80Kb - 3*max MTU */
1520                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_DESC_PUSH_EN, 0);
1521                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_USR_BUF_SIZE,
1522                                     huge_buf_size);
1523                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_MAC_TH, data_xon_thr);
1524                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_MAC_TH, data_xoff_thr);
1525                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_TX_TH, ctrl_xon_thr);
1526                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_TX_TH, ctrl_xoff_thr);
1527                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1);
1528
1529                 /* Enable hash insertion. This is broken for the
1530                  * 'Falcon' hash so also select Toeplitz TCP/IPv4 and
1531                  * IPv4 hashes. */
1532                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_HASH_INSRT_HDR, 1);
1533                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_HASH_ALG, 1);
1534                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_IP_HASH, 1);
1535         }
1536         /* Always enable XOFF signal from RX FIFO.  We enable
1537          * or disable transmission of pause frames at the MAC. */
1538         EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, 1);
1539         efx_writeo(efx, &reg, FR_AZ_RX_CFG);
1540 }
1541
1542 /* This call performs hardware-specific global initialisation, such as
1543  * defining the descriptor cache sizes and number of RSS channels.
1544  * It does not set up any buffers, descriptor rings or event queues.
1545  */
1546 static int falcon_init_nic(struct efx_nic *efx)
1547 {
1548         efx_oword_t temp;
1549         int rc;
1550
1551         /* Use on-chip SRAM */
1552         efx_reado(efx, &temp, FR_AB_NIC_STAT);
1553         EFX_SET_OWORD_FIELD(temp, FRF_AB_ONCHIP_SRAM, 1);
1554         efx_writeo(efx, &temp, FR_AB_NIC_STAT);
1555
1556         rc = falcon_reset_sram(efx);
1557         if (rc)
1558                 return rc;
1559
1560         /* Clear the parity enables on the TX data fifos as
1561          * they produce false parity errors because of timing issues
1562          */
1563         if (EFX_WORKAROUND_5129(efx)) {
1564                 efx_reado(efx, &temp, FR_AZ_CSR_SPARE);
1565                 EFX_SET_OWORD_FIELD(temp, FRF_AB_MEM_PERR_EN_TX_DATA, 0);
1566                 efx_writeo(efx, &temp, FR_AZ_CSR_SPARE);
1567         }
1568
1569         if (EFX_WORKAROUND_7244(efx)) {
1570                 efx_reado(efx, &temp, FR_BZ_RX_FILTER_CTL);
1571                 EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_FULL_SRCH_LIMIT, 8);
1572                 EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_WILD_SRCH_LIMIT, 8);
1573                 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_FULL_SRCH_LIMIT, 8);
1574                 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_WILD_SRCH_LIMIT, 8);
1575                 efx_writeo(efx, &temp, FR_BZ_RX_FILTER_CTL);
1576         }
1577
1578         /* XXX This is documented only for Falcon A0/A1 */
1579         /* Setup RX.  Wait for descriptor is broken and must
1580          * be disabled.  RXDP recovery shouldn't be needed, but is.
1581          */
1582         efx_reado(efx, &temp, FR_AA_RX_SELF_RST);
1583         EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_NODESC_WAIT_DIS, 1);
1584         EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_SELF_RST_EN, 1);
1585         if (EFX_WORKAROUND_5583(efx))
1586                 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_ISCSI_DIS, 1);
1587         efx_writeo(efx, &temp, FR_AA_RX_SELF_RST);
1588
1589         /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
1590          * descriptors (which is bad).
1591          */
1592         efx_reado(efx, &temp, FR_AZ_TX_CFG);
1593         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0);
1594         efx_writeo(efx, &temp, FR_AZ_TX_CFG);
1595
1596         falcon_init_rx_cfg(efx);
1597
1598         if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
1599                 /* Set hash key for IPv4 */
1600                 memcpy(&temp, efx->rx_hash_key, sizeof(temp));
1601                 efx_writeo(efx, &temp, FR_BZ_RX_RSS_TKEY);
1602
1603                 /* Set destination of both TX and RX Flush events */
1604                 EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0);
1605                 efx_writeo(efx, &temp, FR_BZ_DP_CTRL);
1606         }
1607
1608         efx_nic_init_common(efx);
1609
1610         return 0;
1611 }
1612
1613 static void falcon_remove_nic(struct efx_nic *efx)
1614 {
1615         struct falcon_nic_data *nic_data = efx->nic_data;
1616         struct falcon_board *board = falcon_board(efx);
1617         int rc;
1618
1619         board->type->fini(efx);
1620
1621         /* Remove I2C adapter and clear it in preparation for a retry */
1622         rc = i2c_del_adapter(&board->i2c_adap);
1623         BUG_ON(rc);
1624         memset(&board->i2c_adap, 0, sizeof(board->i2c_adap));
1625
1626         efx_nic_free_buffer(efx, &efx->irq_status);
1627
1628         __falcon_reset_hw(efx, RESET_TYPE_ALL);
1629
1630         /* Release the second function after the reset */
1631         if (nic_data->pci_dev2) {
1632                 pci_dev_put(nic_data->pci_dev2);
1633                 nic_data->pci_dev2 = NULL;
1634         }
1635
1636         /* Tear down the private nic state */
1637         kfree(efx->nic_data);
1638         efx->nic_data = NULL;
1639 }
1640
1641 static void falcon_update_nic_stats(struct efx_nic *efx)
1642 {
1643         struct falcon_nic_data *nic_data = efx->nic_data;
1644         efx_oword_t cnt;
1645
1646         if (nic_data->stats_disable_count)
1647                 return;
1648
1649         efx_reado(efx, &cnt, FR_AZ_RX_NODESC_DROP);
1650         efx->n_rx_nodesc_drop_cnt +=
1651                 EFX_OWORD_FIELD(cnt, FRF_AB_RX_NODESC_DROP_CNT);
1652
1653         if (nic_data->stats_pending &&
1654             *nic_data->stats_dma_done == FALCON_STATS_DONE) {
1655                 nic_data->stats_pending = false;
1656                 rmb(); /* read the done flag before the stats */
1657                 efx->mac_op->update_stats(efx);
1658         }
1659 }
1660
1661 void falcon_start_nic_stats(struct efx_nic *efx)
1662 {
1663         struct falcon_nic_data *nic_data = efx->nic_data;
1664
1665         spin_lock_bh(&efx->stats_lock);
1666         if (--nic_data->stats_disable_count == 0)
1667                 falcon_stats_request(efx);
1668         spin_unlock_bh(&efx->stats_lock);
1669 }
1670
1671 void falcon_stop_nic_stats(struct efx_nic *efx)
1672 {
1673         struct falcon_nic_data *nic_data = efx->nic_data;
1674         int i;
1675
1676         might_sleep();
1677
1678         spin_lock_bh(&efx->stats_lock);
1679         ++nic_data->stats_disable_count;
1680         spin_unlock_bh(&efx->stats_lock);
1681
1682         del_timer_sync(&nic_data->stats_timer);
1683
1684         /* Wait enough time for the most recent transfer to
1685          * complete. */
1686         for (i = 0; i < 4 && nic_data->stats_pending; i++) {
1687                 if (*nic_data->stats_dma_done == FALCON_STATS_DONE)
1688                         break;
1689                 msleep(1);
1690         }
1691
1692         spin_lock_bh(&efx->stats_lock);
1693         falcon_stats_complete(efx);
1694         spin_unlock_bh(&efx->stats_lock);
1695 }
1696
1697 static void falcon_set_id_led(struct efx_nic *efx, enum efx_led_mode mode)
1698 {
1699         falcon_board(efx)->type->set_id_led(efx, mode);
1700 }
1701
1702 /**************************************************************************
1703  *
1704  * Wake on LAN
1705  *
1706  **************************************************************************
1707  */
1708
1709 static void falcon_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
1710 {
1711         wol->supported = 0;
1712         wol->wolopts = 0;
1713         memset(&wol->sopass, 0, sizeof(wol->sopass));
1714 }
1715
1716 static int falcon_set_wol(struct efx_nic *efx, u32 type)
1717 {
1718         if (type != 0)
1719                 return -EINVAL;
1720         return 0;
1721 }
1722
1723 /**************************************************************************
1724  *
1725  * Revision-dependent attributes used by efx.c and nic.c
1726  *
1727  **************************************************************************
1728  */
1729
1730 struct efx_nic_type falcon_a1_nic_type = {
1731         .probe = falcon_probe_nic,
1732         .remove = falcon_remove_nic,
1733         .init = falcon_init_nic,
1734         .fini = efx_port_dummy_op_void,
1735         .monitor = falcon_monitor,
1736         .reset = falcon_reset_hw,
1737         .probe_port = falcon_probe_port,
1738         .remove_port = falcon_remove_port,
1739         .handle_global_event = falcon_handle_global_event,
1740         .prepare_flush = falcon_prepare_flush,
1741         .update_stats = falcon_update_nic_stats,
1742         .start_stats = falcon_start_nic_stats,
1743         .stop_stats = falcon_stop_nic_stats,
1744         .set_id_led = falcon_set_id_led,
1745         .push_irq_moderation = falcon_push_irq_moderation,
1746         .push_multicast_hash = falcon_push_multicast_hash,
1747         .reconfigure_port = falcon_reconfigure_port,
1748         .get_wol = falcon_get_wol,
1749         .set_wol = falcon_set_wol,
1750         .resume_wol = efx_port_dummy_op_void,
1751         .test_nvram = falcon_test_nvram,
1752         .default_mac_ops = &falcon_xmac_operations,
1753
1754         .revision = EFX_REV_FALCON_A1,
1755         .mem_map_size = 0x20000,
1756         .txd_ptr_tbl_base = FR_AA_TX_DESC_PTR_TBL_KER,
1757         .rxd_ptr_tbl_base = FR_AA_RX_DESC_PTR_TBL_KER,
1758         .buf_tbl_base = FR_AA_BUF_FULL_TBL_KER,
1759         .evq_ptr_tbl_base = FR_AA_EVQ_PTR_TBL_KER,
1760         .evq_rptr_tbl_base = FR_AA_EVQ_RPTR_KER,
1761         .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
1762         .rx_buffer_padding = 0x24,
1763         .max_interrupt_mode = EFX_INT_MODE_MSI,
1764         .phys_addr_channels = 4,
1765         .tx_dc_base = 0x130000,
1766         .rx_dc_base = 0x100000,
1767         .offload_features = NETIF_F_IP_CSUM,
1768         .reset_world_flags = ETH_RESET_IRQ,
1769 };
1770
1771 struct efx_nic_type falcon_b0_nic_type = {
1772         .probe = falcon_probe_nic,
1773         .remove = falcon_remove_nic,
1774         .init = falcon_init_nic,
1775         .fini = efx_port_dummy_op_void,
1776         .monitor = falcon_monitor,
1777         .reset = falcon_reset_hw,
1778         .probe_port = falcon_probe_port,
1779         .remove_port = falcon_remove_port,
1780         .handle_global_event = falcon_handle_global_event,
1781         .prepare_flush = falcon_prepare_flush,
1782         .update_stats = falcon_update_nic_stats,
1783         .start_stats = falcon_start_nic_stats,
1784         .stop_stats = falcon_stop_nic_stats,
1785         .set_id_led = falcon_set_id_led,
1786         .push_irq_moderation = falcon_push_irq_moderation,
1787         .push_multicast_hash = falcon_push_multicast_hash,
1788         .reconfigure_port = falcon_reconfigure_port,
1789         .get_wol = falcon_get_wol,
1790         .set_wol = falcon_set_wol,
1791         .resume_wol = efx_port_dummy_op_void,
1792         .test_registers = falcon_b0_test_registers,
1793         .test_nvram = falcon_test_nvram,
1794         .default_mac_ops = &falcon_xmac_operations,
1795
1796         .revision = EFX_REV_FALCON_B0,
1797         /* Map everything up to and including the RSS indirection
1798          * table.  Don't map MSI-X table, MSI-X PBA since Linux
1799          * requires that they not be mapped.  */
1800         .mem_map_size = (FR_BZ_RX_INDIRECTION_TBL +
1801                          FR_BZ_RX_INDIRECTION_TBL_STEP *
1802                          FR_BZ_RX_INDIRECTION_TBL_ROWS),
1803         .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL,
1804         .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL,
1805         .buf_tbl_base = FR_BZ_BUF_FULL_TBL,
1806         .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL,
1807         .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR,
1808         .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
1809         .rx_buffer_hash_size = 0x10,
1810         .rx_buffer_padding = 0,
1811         .max_interrupt_mode = EFX_INT_MODE_MSIX,
1812         .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy
1813                                    * interrupt handler only supports 32
1814                                    * channels */
1815         .tx_dc_base = 0x130000,
1816         .rx_dc_base = 0x100000,
1817         .offload_features = NETIF_F_IP_CSUM | NETIF_F_RXHASH | NETIF_F_NTUPLE,
1818         .reset_world_flags = ETH_RESET_IRQ,
1819 };
1820