drivers/net/sfc/falcon.c

   1 /****************************************************************************
   2  * Driver for Solarflare Solarstorm network controllers and boards
   3  * Copyright 2005-2006 Fen Systems Ltd.
   4  * Copyright 2006-2008 Solarflare Communications Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published
   8  * by the Free Software Foundation, incorporated herein by reference.
   9  */
  10
  11 #include <linux/bitops.h>
  12 #include <linux/delay.h>
  13 #include <linux/pci.h>
  14 #include <linux/module.h>
  15 #include <linux/seq_file.h>
  16 #include <linux/i2c.h>
  17 #include <linux/i2c-algo-bit.h>
  18 #include <linux/mii.h>
  19 #include "net_driver.h"
  20 #include "bitfield.h"
  21 #include "efx.h"
  22 #include "mac.h"
  23 #include "spi.h"
  24 #include "falcon.h"
  25 #include "falcon_hwdefs.h"
  26 #include "falcon_io.h"
  27 #include "mdio_10g.h"
  28 #include "phy.h"
  29 #include "boards.h"
  30 #include "workarounds.h"
  31
  32 /* Falcon hardware control.
  33  * Falcon is the internal codename for the SFC4000 controller that is
  34  * present in SFE400X evaluation boards
  35  */
  36
  37 /**
  38  * struct falcon_nic_data - Falcon NIC state
  39  * @next_buffer_table: First available buffer table id
  40  * @pci_dev2: The secondary PCI device if present
  41  * @i2c_data: Operations and state for I2C bit-bashing algorithm
  42  */
  43 struct falcon_nic_data {
  44         unsigned next_buffer_table;
  45         struct pci_dev *pci_dev2;
  46         struct i2c_algo_bit_data i2c_data;
  47 };
  48
  49 /**************************************************************************
  50  *
  51  * Configurable values
  52  *
  53  **************************************************************************
  54  */
  55
  56 static int disable_dma_stats;
  57
  58 /* This is set to 16 for a good reason.  In summary, if larger than
  59  * 16, the descriptor cache holds more than a default socket
  60  * buffer's worth of packets (for UDP we can only have at most one
  61  * socket buffer's worth outstanding).  This combined with the fact
  62  * that we only get 1 TX event per descriptor cache means the NIC
  63  * goes idle.
  64  */
  65 #define TX_DC_ENTRIES 16
  66 #define TX_DC_ENTRIES_ORDER 0
  67 #define TX_DC_BASE 0x130000
  68
  69 #define RX_DC_ENTRIES 64
  70 #define RX_DC_ENTRIES_ORDER 2
  71 #define RX_DC_BASE 0x100000
  72
  73 static const unsigned int
  74 /* "Large" EEPROM device: Atmel AT25640 or similar
  75  * 8 KB, 16-bit address, 32 B write block */
  76 large_eeprom_type = ((13 << SPI_DEV_TYPE_SIZE_LBN)
  77                      | (2 << SPI_DEV_TYPE_ADDR_LEN_LBN)
  78                      | (5 << SPI_DEV_TYPE_BLOCK_SIZE_LBN)),
  79 /* Default flash device: Atmel AT25F1024
  80  * 128 KB, 24-bit address, 32 KB erase block, 256 B write block */
  81 default_flash_type = ((17 << SPI_DEV_TYPE_SIZE_LBN)
  82                       | (3 << SPI_DEV_TYPE_ADDR_LEN_LBN)
  83                       | (0x52 << SPI_DEV_TYPE_ERASE_CMD_LBN)
  84                       | (15 << SPI_DEV_TYPE_ERASE_SIZE_LBN)
  85                       | (8 << SPI_DEV_TYPE_BLOCK_SIZE_LBN));
  86
  87 /* RX FIFO XOFF watermark
  88  *
  89  * When the amount of the RX FIFO increases used increases past this
  90  * watermark send XOFF. Only used if RX flow control is enabled (ethtool -A)
  91  * This also has an effect on RX/TX arbitration
  92  */
  93 static int rx_xoff_thresh_bytes = -1;
  94 module_param(rx_xoff_thresh_bytes, int, 0644);
  95 MODULE_PARM_DESC(rx_xoff_thresh_bytes, "RX fifo XOFF threshold");
  96
  97 /* RX FIFO XON watermark
  98  *
  99  * When the amount of the RX FIFO used decreases below this
 100  * watermark send XON. Only used if TX flow control is enabled (ethtool -A)
 101  * This also has an effect on RX/TX arbitration
 102  */
 103 static int rx_xon_thresh_bytes = -1;
 104 module_param(rx_xon_thresh_bytes, int, 0644);
 105 MODULE_PARM_DESC(rx_xon_thresh_bytes, "RX fifo XON threshold");
 106
 107 /* TX descriptor ring size - min 512 max 4k */
 108 #define FALCON_TXD_RING_ORDER TX_DESCQ_SIZE_1K
 109 #define FALCON_TXD_RING_SIZE 1024
 110 #define FALCON_TXD_RING_MASK (FALCON_TXD_RING_SIZE - 1)
 111
 112 /* RX descriptor ring size - min 512 max 4k */
 113 #define FALCON_RXD_RING_ORDER RX_DESCQ_SIZE_1K
 114 #define FALCON_RXD_RING_SIZE 1024
 115 #define FALCON_RXD_RING_MASK (FALCON_RXD_RING_SIZE - 1)
 116
 117 /* Event queue size - max 32k */
 118 #define FALCON_EVQ_ORDER EVQ_SIZE_4K
 119 #define FALCON_EVQ_SIZE 4096
 120 #define FALCON_EVQ_MASK (FALCON_EVQ_SIZE - 1)
 121
 122 /* Max number of internal errors. After this resets will not be performed */
 123 #define FALCON_MAX_INT_ERRORS 4
 124
 125 /* We poll for events every FLUSH_INTERVAL ms, and check FLUSH_POLL_COUNT times
 126  */
 127 #define FALCON_FLUSH_INTERVAL 10
 128 #define FALCON_FLUSH_POLL_COUNT 100
 129
 130 /**************************************************************************
 131  *
 132  * Falcon constants
 133  *
 134  **************************************************************************
 135  */
 136
 137 /* DMA address mask */
 138 #define FALCON_DMA_MASK DMA_BIT_MASK(46)
 139
 140 /* TX DMA length mask (13-bit) */
 141 #define FALCON_TX_DMA_MASK (4096 - 1)
 142
 143 /* Size and alignment of special buffers (4KB) */
 144 #define FALCON_BUF_SIZE 4096
 145
 146 /* Dummy SRAM size code */
 147 #define SRM_NB_BSZ_ONCHIP_ONLY (-1)
 148
 149 /* Be nice if these (or equiv.) were in linux/pci_regs.h, but they're not. */
 150 #define PCI_EXP_DEVCAP_PWR_VAL_LBN      18
 151 #define PCI_EXP_DEVCAP_PWR_SCL_LBN      26
 152 #define PCI_EXP_DEVCTL_PAYLOAD_LBN      5
 153 #define PCI_EXP_LNKSTA_LNK_WID          0x3f0
 154 #define PCI_EXP_LNKSTA_LNK_WID_LBN      4
 155
 156 #define FALCON_IS_DUAL_FUNC(efx)                \
 157         (falcon_rev(efx) < FALCON_REV_B0)
 158
 159 /**************************************************************************
 160  *
 161  * Falcon hardware access
 162  *
 163  **************************************************************************/
 164
 165 /* Read the current event from the event queue */
 166 static inline efx_qword_t *falcon_event(struct efx_channel *channel,
 167                                         unsigned int index)
 168 {
 169         return (((efx_qword_t *) (channel->eventq.addr)) + index);
 170 }
 171
 172 /* See if an event is present
 173  *
 174  * We check both the high and low dword of the event for all ones.  We
 175  * wrote all ones when we cleared the event, and no valid event can
 176  * have all ones in either its high or low dwords.  This approach is
 177  * robust against reordering.
 178  *
 179  * Note that using a single 64-bit comparison is incorrect; even
 180  * though the CPU read will be atomic, the DMA write may not be.
 181  */
 182 static inline int falcon_event_present(efx_qword_t *event)
 183 {
 184         return (!(EFX_DWORD_IS_ALL_ONES(event->dword[0]) |
 185                   EFX_DWORD_IS_ALL_ONES(event->dword[1])));
 186 }
 187
 188 /**************************************************************************
 189  *
 190  * I2C bus - this is a bit-bashing interface using GPIO pins
 191  * Note that it uses the output enables to tristate the outputs
 192  * SDA is the data pin and SCL is the clock
 193  *
 194  **************************************************************************
 195  */
 196 static void falcon_setsda(void *data, int state)
 197 {
 198         struct efx_nic *efx = (struct efx_nic *)data;
 199         efx_oword_t reg;
 200
 201         falcon_read(efx, &reg, GPIO_CTL_REG_KER);
 202         EFX_SET_OWORD_FIELD(reg, GPIO3_OEN, !state);
 203         falcon_write(efx, &reg, GPIO_CTL_REG_KER);
 204 }
 205
 206 static void falcon_setscl(void *data, int state)
 207 {
 208         struct efx_nic *efx = (struct efx_nic *)data;
 209         efx_oword_t reg;
 210
 211         falcon_read(efx, &reg, GPIO_CTL_REG_KER);
 212         EFX_SET_OWORD_FIELD(reg, GPIO0_OEN, !state);
 213         falcon_write(efx, &reg, GPIO_CTL_REG_KER);
 214 }
 215
 216 static int falcon_getsda(void *data)
 217 {
 218         struct efx_nic *efx = (struct efx_nic *)data;
 219         efx_oword_t reg;
 220
 221         falcon_read(efx, &reg, GPIO_CTL_REG_KER);
 222         return EFX_OWORD_FIELD(reg, GPIO3_IN);
 223 }
 224
 225 static int falcon_getscl(void *data)
 226 {
 227         struct efx_nic *efx = (struct efx_nic *)data;
 228         efx_oword_t reg;
 229
 230         falcon_read(efx, &reg, GPIO_CTL_REG_KER);
 231         return EFX_OWORD_FIELD(reg, GPIO0_IN);
 232 }
 233
 234 static struct i2c_algo_bit_data falcon_i2c_bit_operations = {
 235         .setsda         = falcon_setsda,
 236         .setscl         = falcon_setscl,
 237         .getsda         = falcon_getsda,
 238         .getscl         = falcon_getscl,
 239         .udelay         = 5,
 240         /* Wait up to 50 ms for slave to let us pull SCL high */
 241         .timeout        = DIV_ROUND_UP(HZ, 20),
 242 };
 243
 244 /**************************************************************************
 245  *
 246  * Falcon special buffer handling
 247  * Special buffers are used for event queues and the TX and RX
 248  * descriptor rings.
 249  *
 250  *************************************************************************/
 251
 252 /*
 253  * Initialise a Falcon special buffer
 254  *
 255  * This will define a buffer (previously allocated via
 256  * falcon_alloc_special_buffer()) in Falcon's buffer table, allowing
 257  * it to be used for event queues, descriptor rings etc.
 258  */
 259 static void
 260 falcon_init_special_buffer(struct efx_nic *efx,
 261                            struct efx_special_buffer *buffer)
 262 {
 263         efx_qword_t buf_desc;
 264         int index;
 265         dma_addr_t dma_addr;
 266         int i;
 267
 268         EFX_BUG_ON_PARANOID(!buffer->addr);
 269
 270         /* Write buffer descriptors to NIC */
 271         for (i = 0; i < buffer->entries; i++) {
 272                 index = buffer->index + i;
 273                 dma_addr = buffer->dma_addr + (i * 4096);
 274                 EFX_LOG(efx, "mapping special buffer %d at %llx\n",
 275                         index, (unsigned long long)dma_addr);
 276                 EFX_POPULATE_QWORD_4(buf_desc,
 277                                      IP_DAT_BUF_SIZE, IP_DAT_BUF_SIZE_4K,
 278                                      BUF_ADR_REGION, 0,
 279                                      BUF_ADR_FBUF, (dma_addr >> 12),
 280                                      BUF_OWNER_ID_FBUF, 0);
 281                 falcon_write_sram(efx, &buf_desc, index);
 282         }
 283 }
 284
 285 /* Unmaps a buffer from Falcon and clears the buffer table entries */
 286 static void
 287 falcon_fini_special_buffer(struct efx_nic *efx,
 288                            struct efx_special_buffer *buffer)
 289 {
 290         efx_oword_t buf_tbl_upd;
 291         unsigned int start = buffer->index;
 292         unsigned int end = (buffer->index + buffer->entries - 1);
 293
 294         if (!buffer->entries)
 295                 return;
 296
 297         EFX_LOG(efx, "unmapping special buffers %d-%d\n",
 298                 buffer->index, buffer->index + buffer->entries - 1);
 299
 300         EFX_POPULATE_OWORD_4(buf_tbl_upd,
 301                              BUF_UPD_CMD, 0,
 302                              BUF_CLR_CMD, 1,
 303                              BUF_CLR_END_ID, end,
 304                              BUF_CLR_START_ID, start);
 305         falcon_write(efx, &buf_tbl_upd, BUF_TBL_UPD_REG_KER);
 306 }
 307
 308 /*
 309  * Allocate a new Falcon special buffer
 310  *
 311  * This allocates memory for a new buffer, clears it and allocates a
 312  * new buffer ID range.  It does not write into Falcon's buffer table.
 313  *
 314  * This call will allocate 4KB buffers, since Falcon can't use 8KB
 315  * buffers for event queues and descriptor rings.
 316  */
 317 static int falcon_alloc_special_buffer(struct efx_nic *efx,
 318                                        struct efx_special_buffer *buffer,
 319                                        unsigned int len)
 320 {
 321         struct falcon_nic_data *nic_data = efx->nic_data;
 322
 323         len = ALIGN(len, FALCON_BUF_SIZE);
 324
 325         buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
 326                                             &buffer->dma_addr);
 327         if (!buffer->addr)
 328                 return -ENOMEM;
 329         buffer->len = len;
 330         buffer->entries = len / FALCON_BUF_SIZE;
 331         BUG_ON(buffer->dma_addr & (FALCON_BUF_SIZE - 1));
 332
 333         /* All zeros is a potentially valid event so memset to 0xff */
 334         memset(buffer->addr, 0xff, len);
 335
 336         /* Select new buffer ID */
 337         buffer->index = nic_data->next_buffer_table;
 338         nic_data->next_buffer_table += buffer->entries;
 339
 340         EFX_LOG(efx, "allocating special buffers %d-%d at %llx+%x "
 341                 "(virt %p phys %lx)\n", buffer->index,
 342                 buffer->index + buffer->entries - 1,
 343                 (unsigned long long)buffer->dma_addr, len,
 344                 buffer->addr, virt_to_phys(buffer->addr));
 345
 346         return 0;
 347 }
 348
 349 static void falcon_free_special_buffer(struct efx_nic *efx,
 350                                        struct efx_special_buffer *buffer)
 351 {
 352         if (!buffer->addr)
 353                 return;
 354
 355         EFX_LOG(efx, "deallocating special buffers %d-%d at %llx+%x "
 356                 "(virt %p phys %lx)\n", buffer->index,
 357                 buffer->index + buffer->entries - 1,
 358                 (unsigned long long)buffer->dma_addr, buffer->len,
 359                 buffer->addr, virt_to_phys(buffer->addr));
 360
 361         pci_free_consistent(efx->pci_dev, buffer->len, buffer->addr,
 362                             buffer->dma_addr);
 363         buffer->addr = NULL;
 364         buffer->entries = 0;
 365 }
 366
 367 /**************************************************************************
 368  *
 369  * Falcon generic buffer handling
 370  * These buffers are used for interrupt status and MAC stats
 371  *
 372  **************************************************************************/
 373
 374 static int falcon_alloc_buffer(struct efx_nic *efx,
 375                                struct efx_buffer *buffer, unsigned int len)
 376 {
 377         buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
 378                                             &buffer->dma_addr);
 379         if (!buffer->addr)
 380                 return -ENOMEM;
 381         buffer->len = len;
 382         memset(buffer->addr, 0, len);
 383         return 0;
 384 }
 385
 386 static void falcon_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer)
 387 {
 388         if (buffer->addr) {
 389                 pci_free_consistent(efx->pci_dev, buffer->len,
 390                                     buffer->addr, buffer->dma_addr);
 391                 buffer->addr = NULL;
 392         }
 393 }
 394
 395 /**************************************************************************
 396  *
 397  * Falcon TX path
 398  *
 399  **************************************************************************/
 400
 401 /* Returns a pointer to the specified transmit descriptor in the TX
 402  * descriptor queue belonging to the specified channel.
 403  */
 404 static inline efx_qword_t *falcon_tx_desc(struct efx_tx_queue *tx_queue,
 405                                                unsigned int index)
 406 {
 407         return (((efx_qword_t *) (tx_queue->txd.addr)) + index);
 408 }
 409
 410 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
 411 static inline void falcon_notify_tx_desc(struct efx_tx_queue *tx_queue)
 412 {
 413         unsigned write_ptr;
 414         efx_dword_t reg;
 415
 416         write_ptr = tx_queue->write_count & FALCON_TXD_RING_MASK;
 417         EFX_POPULATE_DWORD_1(reg, TX_DESC_WPTR_DWORD, write_ptr);
 418         falcon_writel_page(tx_queue->efx, &reg,
 419                            TX_DESC_UPD_REG_KER_DWORD, tx_queue->queue);
 420 }
 421
 422
 423 /* For each entry inserted into the software descriptor ring, create a
 424  * descriptor in the hardware TX descriptor ring (in host memory), and
 425  * write a doorbell.
 426  */
 427 void falcon_push_buffers(struct efx_tx_queue *tx_queue)
 428 {
 429
 430         struct efx_tx_buffer *buffer;
 431         efx_qword_t *txd;
 432         unsigned write_ptr;
 433
 434         BUG_ON(tx_queue->write_count == tx_queue->insert_count);
 435
 436         do {
 437                 write_ptr = tx_queue->write_count & FALCON_TXD_RING_MASK;
 438                 buffer = &tx_queue->buffer[write_ptr];
 439                 txd = falcon_tx_desc(tx_queue, write_ptr);
 440                 ++tx_queue->write_count;
 441
 442                 /* Create TX descriptor ring entry */
 443                 EFX_POPULATE_QWORD_5(*txd,
 444                                      TX_KER_PORT, 0,
 445                                      TX_KER_CONT, buffer->continuation,
 446                                      TX_KER_BYTE_CNT, buffer->len,
 447                                      TX_KER_BUF_REGION, 0,
 448                                      TX_KER_BUF_ADR, buffer->dma_addr);
 449         } while (tx_queue->write_count != tx_queue->insert_count);
 450
 451         wmb(); /* Ensure descriptors are written before they are fetched */
 452         falcon_notify_tx_desc(tx_queue);
 453 }
 454
 455 /* Allocate hardware resources for a TX queue */
 456 int falcon_probe_tx(struct efx_tx_queue *tx_queue)
 457 {
 458         struct efx_nic *efx = tx_queue->efx;
 459         return falcon_alloc_special_buffer(efx, &tx_queue->txd,
 460                                            FALCON_TXD_RING_SIZE *
 461                                            sizeof(efx_qword_t));
 462 }
 463
 464 void falcon_init_tx(struct efx_tx_queue *tx_queue)
 465 {
 466         efx_oword_t tx_desc_ptr;
 467         struct efx_nic *efx = tx_queue->efx;
 468
 469         tx_queue->flushed = false;
 470
 471         /* Pin TX descriptor ring */
 472         falcon_init_special_buffer(efx, &tx_queue->txd);
 473
 474         /* Push TX descriptor ring to card */
 475         EFX_POPULATE_OWORD_10(tx_desc_ptr,
 476                               TX_DESCQ_EN, 1,
 477                               TX_ISCSI_DDIG_EN, 0,
 478                               TX_ISCSI_HDIG_EN, 0,
 479                               TX_DESCQ_BUF_BASE_ID, tx_queue->txd.index,
 480                               TX_DESCQ_EVQ_ID, tx_queue->channel->channel,
 481                               TX_DESCQ_OWNER_ID, 0,
 482                               TX_DESCQ_LABEL, tx_queue->queue,
 483                               TX_DESCQ_SIZE, FALCON_TXD_RING_ORDER,
 484                               TX_DESCQ_TYPE, 0,
 485                               TX_NON_IP_DROP_DIS_B0, 1);
 486
 487         if (falcon_rev(efx) >= FALCON_REV_B0) {
 488                 int csum = tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM;
 489                 EFX_SET_OWORD_FIELD(tx_desc_ptr, TX_IP_CHKSM_DIS_B0, !csum);
 490                 EFX_SET_OWORD_FIELD(tx_desc_ptr, TX_TCP_CHKSM_DIS_B0, !csum);
 491         }
 492
 493         falcon_write_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
 494                            tx_queue->queue);
 495
 496         if (falcon_rev(efx) < FALCON_REV_B0) {
 497                 efx_oword_t reg;
 498
 499                 /* Only 128 bits in this register */
 500                 BUILD_BUG_ON(EFX_TX_QUEUE_COUNT >= 128);
 501
 502                 falcon_read(efx, &reg, TX_CHKSM_CFG_REG_KER_A1);
 503                 if (tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM)
 504                         clear_bit_le(tx_queue->queue, (void *)&reg);
 505                 else
 506                         set_bit_le(tx_queue->queue, (void *)&reg);
 507                 falcon_write(efx, &reg, TX_CHKSM_CFG_REG_KER_A1);
 508         }
 509 }
 510
 511 static void falcon_flush_tx_queue(struct efx_tx_queue *tx_queue)
 512 {
 513         struct efx_nic *efx = tx_queue->efx;
 514         efx_oword_t tx_flush_descq;
 515
 516         /* Post a flush command */
 517         EFX_POPULATE_OWORD_2(tx_flush_descq,
 518                              TX_FLUSH_DESCQ_CMD, 1,
 519                              TX_FLUSH_DESCQ, tx_queue->queue);
 520         falcon_write(efx, &tx_flush_descq, TX_FLUSH_DESCQ_REG_KER);
 521 }
 522
 523 void falcon_fini_tx(struct efx_tx_queue *tx_queue)
 524 {
 525         struct efx_nic *efx = tx_queue->efx;
 526         efx_oword_t tx_desc_ptr;
 527
 528         /* The queue should have been flushed */
 529         WARN_ON(!tx_queue->flushed);
 530
 531         /* Remove TX descriptor ring from card */
 532         EFX_ZERO_OWORD(tx_desc_ptr);
 533         falcon_write_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
 534                            tx_queue->queue);
 535
 536         /* Unpin TX descriptor ring */
 537         falcon_fini_special_buffer(efx, &tx_queue->txd);
 538 }
 539
 540 /* Free buffers backing TX queue */
 541 void falcon_remove_tx(struct efx_tx_queue *tx_queue)
 542 {
 543         falcon_free_special_buffer(tx_queue->efx, &tx_queue->txd);
 544 }
 545
 546 /**************************************************************************
 547  *
 548  * Falcon RX path
 549  *
 550  **************************************************************************/
 551
 552 /* Returns a pointer to the specified descriptor in the RX descriptor queue */
 553 static inline efx_qword_t *falcon_rx_desc(struct efx_rx_queue *rx_queue,
 554                                                unsigned int index)
 555 {
 556         return (((efx_qword_t *) (rx_queue->rxd.addr)) + index);
 557 }
 558
 559 /* This creates an entry in the RX descriptor queue */
 560 static inline void falcon_build_rx_desc(struct efx_rx_queue *rx_queue,
 561                                         unsigned index)
 562 {
 563         struct efx_rx_buffer *rx_buf;
 564         efx_qword_t *rxd;
 565
 566         rxd = falcon_rx_desc(rx_queue, index);
 567         rx_buf = efx_rx_buffer(rx_queue, index);
 568         EFX_POPULATE_QWORD_3(*rxd,
 569                              RX_KER_BUF_SIZE,
 570                              rx_buf->len -
 571                              rx_queue->efx->type->rx_buffer_padding,
 572                              RX_KER_BUF_REGION, 0,
 573                              RX_KER_BUF_ADR, rx_buf->dma_addr);
 574 }
 575
 576 /* This writes to the RX_DESC_WPTR register for the specified receive
 577  * descriptor ring.
 578  */
 579 void falcon_notify_rx_desc(struct efx_rx_queue *rx_queue)
 580 {
 581         efx_dword_t reg;
 582         unsigned write_ptr;
 583
 584         while (rx_queue->notified_count != rx_queue->added_count) {
 585                 falcon_build_rx_desc(rx_queue,
 586                                      rx_queue->notified_count &
 587                                      FALCON_RXD_RING_MASK);
 588                 ++rx_queue->notified_count;
 589         }
 590
 591         wmb();
 592         write_ptr = rx_queue->added_count & FALCON_RXD_RING_MASK;
 593         EFX_POPULATE_DWORD_1(reg, RX_DESC_WPTR_DWORD, write_ptr);
 594         falcon_writel_page(rx_queue->efx, &reg,
 595                            RX_DESC_UPD_REG_KER_DWORD, rx_queue->queue);
 596 }
 597
 598 int falcon_probe_rx(struct efx_rx_queue *rx_queue)
 599 {
 600         struct efx_nic *efx = rx_queue->efx;
 601         return falcon_alloc_special_buffer(efx, &rx_queue->rxd,
 602                                            FALCON_RXD_RING_SIZE *
 603                                            sizeof(efx_qword_t));
 604 }
 605
 606 void falcon_init_rx(struct efx_rx_queue *rx_queue)
 607 {
 608         efx_oword_t rx_desc_ptr;
 609         struct efx_nic *efx = rx_queue->efx;
 610         bool is_b0 = falcon_rev(efx) >= FALCON_REV_B0;
 611         bool iscsi_digest_en = is_b0;
 612
 613         EFX_LOG(efx, "RX queue %d ring in special buffers %d-%d\n",
 614                 rx_queue->queue, rx_queue->rxd.index,
 615                 rx_queue->rxd.index + rx_queue->rxd.entries - 1);
 616
 617         rx_queue->flushed = false;
 618
 619         /* Pin RX descriptor ring */
 620         falcon_init_special_buffer(efx, &rx_queue->rxd);
 621
 622         /* Push RX descriptor ring to card */
 623         EFX_POPULATE_OWORD_10(rx_desc_ptr,
 624                               RX_ISCSI_DDIG_EN, iscsi_digest_en,
 625                               RX_ISCSI_HDIG_EN, iscsi_digest_en,
 626                               RX_DESCQ_BUF_BASE_ID, rx_queue->rxd.index,
 627                               RX_DESCQ_EVQ_ID, rx_queue->channel->channel,
 628                               RX_DESCQ_OWNER_ID, 0,
 629                               RX_DESCQ_LABEL, rx_queue->queue,
 630                               RX_DESCQ_SIZE, FALCON_RXD_RING_ORDER,
 631                               RX_DESCQ_TYPE, 0 /* kernel queue */ ,
 632                               /* For >=B0 this is scatter so disable */
 633                               RX_DESCQ_JUMBO, !is_b0,
 634                               RX_DESCQ_EN, 1);
 635         falcon_write_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
 636                            rx_queue->queue);
 637 }
 638
 639 static void falcon_flush_rx_queue(struct efx_rx_queue *rx_queue)
 640 {
 641         struct efx_nic *efx = rx_queue->efx;
 642         efx_oword_t rx_flush_descq;
 643
 644         /* Post a flush command */
 645         EFX_POPULATE_OWORD_2(rx_flush_descq,
 646                              RX_FLUSH_DESCQ_CMD, 1,
 647                              RX_FLUSH_DESCQ, rx_queue->queue);
 648         falcon_write(efx, &rx_flush_descq, RX_FLUSH_DESCQ_REG_KER);
 649 }
 650
 651 void falcon_fini_rx(struct efx_rx_queue *rx_queue)
 652 {
 653         efx_oword_t rx_desc_ptr;
 654         struct efx_nic *efx = rx_queue->efx;
 655
 656         /* The queue should already have been flushed */
 657         WARN_ON(!rx_queue->flushed);
 658
 659         /* Remove RX descriptor ring from card */
 660         EFX_ZERO_OWORD(rx_desc_ptr);
 661         falcon_write_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
 662                            rx_queue->queue);
 663
 664         /* Unpin RX descriptor ring */
 665         falcon_fini_special_buffer(efx, &rx_queue->rxd);
 666 }
 667
 668 /* Free buffers backing RX queue */
 669 void falcon_remove_rx(struct efx_rx_queue *rx_queue)
 670 {
 671         falcon_free_special_buffer(rx_queue->efx, &rx_queue->rxd);
 672 }
 673
 674 /**************************************************************************
 675  *
 676  * Falcon event queue processing
 677  * Event queues are processed by per-channel tasklets.
 678  *
 679  **************************************************************************/
 680
 681 /* Update a channel's event queue's read pointer (RPTR) register
 682  *
 683  * This writes the EVQ_RPTR_REG register for the specified channel's
 684  * event queue.
 685  *
 686  * Note that EVQ_RPTR_REG contains the index of the "last read" event,
 687  * whereas channel->eventq_read_ptr contains the index of the "next to
 688  * read" event.
 689  */
 690 void falcon_eventq_read_ack(struct efx_channel *channel)
 691 {
 692         efx_dword_t reg;
 693         struct efx_nic *efx = channel->efx;
 694
 695         EFX_POPULATE_DWORD_1(reg, EVQ_RPTR_DWORD, channel->eventq_read_ptr);
 696         falcon_writel_table(efx, &reg, efx->type->evq_rptr_tbl_base,
 697                             channel->channel);
 698 }
 699
 700 /* Use HW to insert a SW defined event */
 701 void falcon_generate_event(struct efx_channel *channel, efx_qword_t *event)
 702 {
 703         efx_oword_t drv_ev_reg;
 704
 705         EFX_POPULATE_OWORD_2(drv_ev_reg,
 706                              DRV_EV_QID, channel->channel,
 707                              DRV_EV_DATA,
 708                              EFX_QWORD_FIELD64(*event, WHOLE_EVENT));
 709         falcon_write(channel->efx, &drv_ev_reg, DRV_EV_REG_KER);
 710 }
 711
 712 /* Handle a transmit completion event
 713  *
 714  * Falcon batches TX completion events; the message we receive is of
 715  * the form "complete all TX events up to this index".
 716  */
 717 static void falcon_handle_tx_event(struct efx_channel *channel,
 718                                    efx_qword_t *event)
 719 {
 720         unsigned int tx_ev_desc_ptr;
 721         unsigned int tx_ev_q_label;
 722         struct efx_tx_queue *tx_queue;
 723         struct efx_nic *efx = channel->efx;
 724
 725         if (likely(EFX_QWORD_FIELD(*event, TX_EV_COMP))) {
 726                 /* Transmit completion */
 727                 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, TX_EV_DESC_PTR);
 728                 tx_ev_q_label = EFX_QWORD_FIELD(*event, TX_EV_Q_LABEL);
 729                 tx_queue = &efx->tx_queue[tx_ev_q_label];
 730                 efx_xmit_done(tx_queue, tx_ev_desc_ptr);
 731         } else if (EFX_QWORD_FIELD(*event, TX_EV_WQ_FF_FULL)) {
 732                 /* Rewrite the FIFO write pointer */
 733                 tx_ev_q_label = EFX_QWORD_FIELD(*event, TX_EV_Q_LABEL);
 734                 tx_queue = &efx->tx_queue[tx_ev_q_label];
 735
 736                 if (efx_dev_registered(efx))
 737                         netif_tx_lock(efx->net_dev);
 738                 falcon_notify_tx_desc(tx_queue);
 739                 if (efx_dev_registered(efx))
 740                         netif_tx_unlock(efx->net_dev);
 741         } else if (EFX_QWORD_FIELD(*event, TX_EV_PKT_ERR) &&
 742                    EFX_WORKAROUND_10727(efx)) {
 743                 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
 744         } else {
 745                 EFX_ERR(efx, "channel %d unexpected TX event "
 746                         EFX_QWORD_FMT"\n", channel->channel,
 747                         EFX_QWORD_VAL(*event));
 748         }
 749 }
 750
 751 /* Detect errors included in the rx_evt_pkt_ok bit. */
 752 static void falcon_handle_rx_not_ok(struct efx_rx_queue *rx_queue,
 753                                     const efx_qword_t *event,
 754                                     bool *rx_ev_pkt_ok,
 755                                     bool *discard)
 756 {
 757         struct efx_nic *efx = rx_queue->efx;
 758         bool rx_ev_buf_owner_id_err, rx_ev_ip_hdr_chksum_err;
 759         bool rx_ev_tcp_udp_chksum_err, rx_ev_eth_crc_err;
 760         bool rx_ev_frm_trunc, rx_ev_drib_nib, rx_ev_tobe_disc;
 761         bool rx_ev_other_err, rx_ev_pause_frm;
 762         bool rx_ev_ip_frag_err, rx_ev_hdr_type, rx_ev_mcast_pkt;
 763         unsigned rx_ev_pkt_type;
 764
 765         rx_ev_hdr_type = EFX_QWORD_FIELD(*event, RX_EV_HDR_TYPE);
 766         rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, RX_EV_MCAST_PKT);
 767         rx_ev_tobe_disc = EFX_QWORD_FIELD(*event, RX_EV_TOBE_DISC);
 768         rx_ev_pkt_type = EFX_QWORD_FIELD(*event, RX_EV_PKT_TYPE);
 769         rx_ev_buf_owner_id_err = EFX_QWORD_FIELD(*event,
 770                                                  RX_EV_BUF_OWNER_ID_ERR);
 771         rx_ev_ip_frag_err = EFX_QWORD_FIELD(*event, RX_EV_IF_FRAG_ERR);
 772         rx_ev_ip_hdr_chksum_err = EFX_QWORD_FIELD(*event,
 773                                                   RX_EV_IP_HDR_CHKSUM_ERR);
 774         rx_ev_tcp_udp_chksum_err = EFX_QWORD_FIELD(*event,
 775                                                    RX_EV_TCP_UDP_CHKSUM_ERR);
 776         rx_ev_eth_crc_err = EFX_QWORD_FIELD(*event, RX_EV_ETH_CRC_ERR);
 777         rx_ev_frm_trunc = EFX_QWORD_FIELD(*event, RX_EV_FRM_TRUNC);
 778         rx_ev_drib_nib = ((falcon_rev(efx) >= FALCON_REV_B0) ?
 779                           0 : EFX_QWORD_FIELD(*event, RX_EV_DRIB_NIB));
 780         rx_ev_pause_frm = EFX_QWORD_FIELD(*event, RX_EV_PAUSE_FRM_ERR);
 781
 782         /* Every error apart from tobe_disc and pause_frm */
 783         rx_ev_other_err = (rx_ev_drib_nib | rx_ev_tcp_udp_chksum_err |
 784                            rx_ev_buf_owner_id_err | rx_ev_eth_crc_err |
 785                            rx_ev_frm_trunc | rx_ev_ip_hdr_chksum_err);
 786
 787         /* Count errors that are not in MAC stats.  Ignore expected
 788          * checksum errors during self-test. */
 789         if (rx_ev_frm_trunc)
 790                 ++rx_queue->channel->n_rx_frm_trunc;
 791         else if (rx_ev_tobe_disc)
 792                 ++rx_queue->channel->n_rx_tobe_disc;
 793         else if (!efx->loopback_selftest) {
 794                 if (rx_ev_ip_hdr_chksum_err)
 795                         ++rx_queue->channel->n_rx_ip_hdr_chksum_err;
 796                 else if (rx_ev_tcp_udp_chksum_err)
 797                         ++rx_queue->channel->n_rx_tcp_udp_chksum_err;
 798         }
 799         if (rx_ev_ip_frag_err)
 800                 ++rx_queue->channel->n_rx_ip_frag_err;
 801
 802         /* The frame must be discarded if any of these are true. */
 803         *discard = (rx_ev_eth_crc_err | rx_ev_frm_trunc | rx_ev_drib_nib |
 804                     rx_ev_tobe_disc | rx_ev_pause_frm);
 805
 806         /* TOBE_DISC is expected on unicast mismatches; don't print out an
 807          * error message.  FRM_TRUNC indicates RXDP dropped the packet due
 808          * to a FIFO overflow.
 809          */
 810 #ifdef EFX_ENABLE_DEBUG
 811         if (rx_ev_other_err) {
 812                 EFX_INFO_RL(efx, " RX queue %d unexpected RX event "
 813                             EFX_QWORD_FMT "%s%s%s%s%s%s%s%s\n",
 814                             rx_queue->queue, EFX_QWORD_VAL(*event),
 815                             rx_ev_buf_owner_id_err ? " [OWNER_ID_ERR]" : "",
 816                             rx_ev_ip_hdr_chksum_err ?
 817                             " [IP_HDR_CHKSUM_ERR]" : "",
 818                             rx_ev_tcp_udp_chksum_err ?
 819                             " [TCP_UDP_CHKSUM_ERR]" : "",
 820                             rx_ev_eth_crc_err ? " [ETH_CRC_ERR]" : "",
 821                             rx_ev_frm_trunc ? " [FRM_TRUNC]" : "",
 822                             rx_ev_drib_nib ? " [DRIB_NIB]" : "",
 823                             rx_ev_tobe_disc ? " [TOBE_DISC]" : "",
 824                             rx_ev_pause_frm ? " [PAUSE]" : "");
 825         }
 826 #endif
 827
 828         if (unlikely(rx_ev_eth_crc_err && EFX_WORKAROUND_10750(efx) &&
 829                      efx->phy_type == PHY_TYPE_SFX7101))
 830                 tenxpress_crc_err(efx);
 831 }
 832
 833 /* Handle receive events that are not in-order. */
 834 static void falcon_handle_rx_bad_index(struct efx_rx_queue *rx_queue,
 835                                        unsigned index)
 836 {
 837         struct efx_nic *efx = rx_queue->efx;
 838         unsigned expected, dropped;
 839
 840         expected = rx_queue->removed_count & FALCON_RXD_RING_MASK;
 841         dropped = ((index + FALCON_RXD_RING_SIZE - expected) &
 842                    FALCON_RXD_RING_MASK);
 843         EFX_INFO(efx, "dropped %d events (index=%d expected=%d)\n",
 844                 dropped, index, expected);
 845
 846         efx_schedule_reset(efx, EFX_WORKAROUND_5676(efx) ?
 847                            RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
 848 }
 849
 850 /* Handle a packet received event
 851  *
 852  * Falcon silicon gives a "discard" flag if it's a unicast packet with the
 853  * wrong destination address
 854  * Also "is multicast" and "matches multicast filter" flags can be used to
 855  * discard non-matching multicast packets.
 856  */
 857 static void falcon_handle_rx_event(struct efx_channel *channel,
 858                                    const efx_qword_t *event)
 859 {
 860         unsigned int rx_ev_desc_ptr, rx_ev_byte_cnt;
 861         unsigned int rx_ev_hdr_type, rx_ev_mcast_pkt;
 862         unsigned expected_ptr;
 863         bool rx_ev_pkt_ok, discard = false, checksummed;
 864         struct efx_rx_queue *rx_queue;
 865         struct efx_nic *efx = channel->efx;
 866
 867         /* Basic packet information */
 868         rx_ev_byte_cnt = EFX_QWORD_FIELD(*event, RX_EV_BYTE_CNT);
 869         rx_ev_pkt_ok = EFX_QWORD_FIELD(*event, RX_EV_PKT_OK);
 870         rx_ev_hdr_type = EFX_QWORD_FIELD(*event, RX_EV_HDR_TYPE);
 871         WARN_ON(EFX_QWORD_FIELD(*event, RX_EV_JUMBO_CONT));
 872         WARN_ON(EFX_QWORD_FIELD(*event, RX_EV_SOP) != 1);
 873         WARN_ON(EFX_QWORD_FIELD(*event, RX_EV_Q_LABEL) != channel->channel);
 874
 875         rx_queue = &efx->rx_queue[channel->channel];
 876
 877         rx_ev_desc_ptr = EFX_QWORD_FIELD(*event, RX_EV_DESC_PTR);
 878         expected_ptr = rx_queue->removed_count & FALCON_RXD_RING_MASK;
 879         if (unlikely(rx_ev_desc_ptr != expected_ptr))
 880                 falcon_handle_rx_bad_index(rx_queue, rx_ev_desc_ptr);
 881
 882         if (likely(rx_ev_pkt_ok)) {
 883                 /* If packet is marked as OK and packet type is TCP/IPv4 or
 884                  * UDP/IPv4, then we can rely on the hardware checksum.
 885                  */
 886                 checksummed = RX_EV_HDR_TYPE_HAS_CHECKSUMS(rx_ev_hdr_type);
 887         } else {
 888                 falcon_handle_rx_not_ok(rx_queue, event, &rx_ev_pkt_ok,
 889                                         &discard);
 890                 checksummed = false;
 891         }
 892
 893         /* Detect multicast packets that didn't match the filter */
 894         rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, RX_EV_MCAST_PKT);
 895         if (rx_ev_mcast_pkt) {
 896                 unsigned int rx_ev_mcast_hash_match =
 897                         EFX_QWORD_FIELD(*event, RX_EV_MCAST_HASH_MATCH);
 898
 899                 if (unlikely(!rx_ev_mcast_hash_match))
 900                         discard = true;
 901         }
 902
 903         /* Handle received packet */
 904         efx_rx_packet(rx_queue, rx_ev_desc_ptr, rx_ev_byte_cnt,
 905                       checksummed, discard);
 906 }
 907
 908 /* Global events are basically PHY events */
 909 static void falcon_handle_global_event(struct efx_channel *channel,
 910                                        efx_qword_t *event)
 911 {
 912         struct efx_nic *efx = channel->efx;
 913         bool handled = false;
 914
 915         if (EFX_QWORD_FIELD(*event, G_PHY0_INTR) ||
 916             EFX_QWORD_FIELD(*event, G_PHY1_INTR) ||
 917             EFX_QWORD_FIELD(*event, XG_PHY_INTR) ||
 918             EFX_QWORD_FIELD(*event, XFP_PHY_INTR)) {
 919                 efx->phy_op->clear_interrupt(efx);
 920                 queue_work(efx->workqueue, &efx->phy_work);
 921                 handled = true;
 922         }
 923
 924         if ((falcon_rev(efx) >= FALCON_REV_B0) &&
 925             EFX_QWORD_FIELD(*event, XG_MNT_INTR_B0)) {
 926                 queue_work(efx->workqueue, &efx->mac_work);
 927                 handled = true;
 928         }
 929
 930         if (EFX_QWORD_FIELD_VER(efx, *event, RX_RECOVERY)) {
 931                 EFX_ERR(efx, "channel %d seen global RX_RESET "
 932                         "event. Resetting.\n", channel->channel);
 933
 934                 atomic_inc(&efx->rx_reset);
 935                 efx_schedule_reset(efx, EFX_WORKAROUND_6555(efx) ?
 936                                    RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
 937                 handled = true;
 938         }
 939
 940         if (!handled)
 941                 EFX_ERR(efx, "channel %d unknown global event "
 942                         EFX_QWORD_FMT "\n", channel->channel,
 943                         EFX_QWORD_VAL(*event));
 944 }
 945
 946 static void falcon_handle_driver_event(struct efx_channel *channel,
 947                                        efx_qword_t *event)
 948 {
 949         struct efx_nic *efx = channel->efx;
 950         unsigned int ev_sub_code;
 951         unsigned int ev_sub_data;
 952
 953         ev_sub_code = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_CODE);
 954         ev_sub_data = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_DATA);
 955
 956         switch (ev_sub_code) {
 957         case TX_DESCQ_FLS_DONE_EV_DECODE:
 958                 EFX_TRACE(efx, "channel %d TXQ %d flushed\n",
 959                           channel->channel, ev_sub_data);
 960                 break;
 961         case RX_DESCQ_FLS_DONE_EV_DECODE:
 962                 EFX_TRACE(efx, "channel %d RXQ %d flushed\n",
 963                           channel->channel, ev_sub_data);
 964                 break;
 965         case EVQ_INIT_DONE_EV_DECODE:
 966                 EFX_LOG(efx, "channel %d EVQ %d initialised\n",
 967                         channel->channel, ev_sub_data);
 968                 break;
 969         case SRM_UPD_DONE_EV_DECODE:
 970                 EFX_TRACE(efx, "channel %d SRAM update done\n",
 971                           channel->channel);
 972                 break;
 973         case WAKE_UP_EV_DECODE:
 974                 EFX_TRACE(efx, "channel %d RXQ %d wakeup event\n",
 975                           channel->channel, ev_sub_data);
 976                 break;
 977         case TIMER_EV_DECODE:
 978                 EFX_TRACE(efx, "channel %d RX queue %d timer expired\n",
 979                           channel->channel, ev_sub_data);
 980                 break;
 981         case RX_RECOVERY_EV_DECODE:
 982                 EFX_ERR(efx, "channel %d seen DRIVER RX_RESET event. "
 983                         "Resetting.\n", channel->channel);
 984                 atomic_inc(&efx->rx_reset);
 985                 efx_schedule_reset(efx,
 986                                    EFX_WORKAROUND_6555(efx) ?
 987                                    RESET_TYPE_RX_RECOVERY :
 988                                    RESET_TYPE_DISABLE);
 989                 break;
 990         case RX_DSC_ERROR_EV_DECODE:
 991                 EFX_ERR(efx, "RX DMA Q %d reports descriptor fetch error."
 992                         " RX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
 993                 efx_schedule_reset(efx, RESET_TYPE_RX_DESC_FETCH);
 994                 break;
 995         case TX_DSC_ERROR_EV_DECODE:
 996                 EFX_ERR(efx, "TX DMA Q %d reports descriptor fetch error."
 997                         " TX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
 998                 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
 999                 break;
1000         default:
1001                 EFX_TRACE(efx, "channel %d unknown driver event code %d "
1002                           "data %04x\n", channel->channel, ev_sub_code,
1003                           ev_sub_data);
1004                 break;
1005         }
1006 }
1007
1008 int falcon_process_eventq(struct efx_channel *channel, int rx_quota)
1009 {
1010         unsigned int read_ptr;
1011         efx_qword_t event, *p_event;
1012         int ev_code;
1013         int rx_packets = 0;
1014
1015         read_ptr = channel->eventq_read_ptr;
1016
1017         do {
1018                 p_event = falcon_event(channel, read_ptr);
1019                 event = *p_event;
1020
1021                 if (!falcon_event_present(&event))
1022                         /* End of events */
1023                         break;
1024
1025                 EFX_TRACE(channel->efx, "channel %d event is "EFX_QWORD_FMT"\n",
1026                           channel->channel, EFX_QWORD_VAL(event));
1027
1028                 /* Clear this event by marking it all ones */
1029                 EFX_SET_QWORD(*p_event);
1030
1031                 ev_code = EFX_QWORD_FIELD(event, EV_CODE);
1032
1033                 switch (ev_code) {
1034                 case RX_IP_EV_DECODE:
1035                         falcon_handle_rx_event(channel, &event);
1036                         ++rx_packets;
1037                         break;
1038                 case TX_IP_EV_DECODE:
1039                         falcon_handle_tx_event(channel, &event);
1040                         break;
1041                 case DRV_GEN_EV_DECODE:
1042                         channel->eventq_magic
1043                                 = EFX_QWORD_FIELD(event, EVQ_MAGIC);
1044                         EFX_LOG(channel->efx, "channel %d received generated "
1045                                 "event "EFX_QWORD_FMT"\n", channel->channel,
1046                                 EFX_QWORD_VAL(event));
1047                         break;
1048                 case GLOBAL_EV_DECODE:
1049                         falcon_handle_global_event(channel, &event);
1050                         break;
1051                 case DRIVER_EV_DECODE:
1052                         falcon_handle_driver_event(channel, &event);
1053                         break;
1054                 default:
1055                         EFX_ERR(channel->efx, "channel %d unknown event type %d"
1056                                 " (data " EFX_QWORD_FMT ")\n", channel->channel,
1057                                 ev_code, EFX_QWORD_VAL(event));
1058                 }
1059
1060                 /* Increment read pointer */
1061                 read_ptr = (read_ptr + 1) & FALCON_EVQ_MASK;
1062
1063         } while (rx_packets < rx_quota);
1064
1065         channel->eventq_read_ptr = read_ptr;
1066         return rx_packets;
1067 }
1068
1069 void falcon_set_int_moderation(struct efx_channel *channel)
1070 {
1071         efx_dword_t timer_cmd;
1072         struct efx_nic *efx = channel->efx;
1073
1074         /* Set timer register */
1075         if (channel->irq_moderation) {
1076                 /* Round to resolution supported by hardware.  The value we
1077                  * program is based at 0.  So actual interrupt moderation
1078                  * achieved is ((x + 1) * res).
1079                  */
1080                 unsigned int res = 5;
1081                 channel->irq_moderation -= (channel->irq_moderation % res);
1082                 if (channel->irq_moderation < res)
1083                         channel->irq_moderation = res;
1084                 EFX_POPULATE_DWORD_2(timer_cmd,
1085                                      TIMER_MODE, TIMER_MODE_INT_HLDOFF,
1086                                      TIMER_VAL,
1087                                      (channel->irq_moderation / res) - 1);
1088         } else {
1089                 EFX_POPULATE_DWORD_2(timer_cmd,
1090                                      TIMER_MODE, TIMER_MODE_DIS,
1091                                      TIMER_VAL, 0);
1092         }
1093         falcon_writel_page_locked(efx, &timer_cmd, TIMER_CMD_REG_KER,
1094                                   channel->channel);
1095
1096 }
1097
1098 /* Allocate buffer table entries for event queue */
1099 int falcon_probe_eventq(struct efx_channel *channel)
1100 {
1101         struct efx_nic *efx = channel->efx;
1102         unsigned int evq_size;
1103
1104         evq_size = FALCON_EVQ_SIZE * sizeof(efx_qword_t);
1105         return falcon_alloc_special_buffer(efx, &channel->eventq, evq_size);
1106 }
1107
1108 void falcon_init_eventq(struct efx_channel *channel)
1109 {
1110         efx_oword_t evq_ptr;
1111         struct efx_nic *efx = channel->efx;
1112
1113         EFX_LOG(efx, "channel %d event queue in special buffers %d-%d\n",
1114                 channel->channel, channel->eventq.index,
1115                 channel->eventq.index + channel->eventq.entries - 1);
1116
1117         /* Pin event queue buffer */
1118         falcon_init_special_buffer(efx, &channel->eventq);
1119
1120         /* Fill event queue with all ones (i.e. empty events) */
1121         memset(channel->eventq.addr, 0xff, channel->eventq.len);
1122
1123         /* Push event queue to card */
1124         EFX_POPULATE_OWORD_3(evq_ptr,
1125                              EVQ_EN, 1,
1126                              EVQ_SIZE, FALCON_EVQ_ORDER,
1127                              EVQ_BUF_BASE_ID, channel->eventq.index);
1128         falcon_write_table(efx, &evq_ptr, efx->type->evq_ptr_tbl_base,
1129                            channel->channel);
1130
1131         falcon_set_int_moderation(channel);
1132 }
1133
1134 void falcon_fini_eventq(struct efx_channel *channel)
1135 {
1136         efx_oword_t eventq_ptr;
1137         struct efx_nic *efx = channel->efx;
1138
1139         /* Remove event queue from card */
1140         EFX_ZERO_OWORD(eventq_ptr);
1141         falcon_write_table(efx, &eventq_ptr, efx->type->evq_ptr_tbl_base,
1142                            channel->channel);
1143
1144         /* Unpin event queue */
1145         falcon_fini_special_buffer(efx, &channel->eventq);
1146 }
1147
1148 /* Free buffers backing event queue */
1149 void falcon_remove_eventq(struct efx_channel *channel)
1150 {
1151         falcon_free_special_buffer(channel->efx, &channel->eventq);
1152 }
1153
1154
1155 /* Generates a test event on the event queue.  A subsequent call to
1156  * process_eventq() should pick up the event and place the value of
1157  * "magic" into channel->eventq_magic;
1158  */
1159 void falcon_generate_test_event(struct efx_channel *channel, unsigned int magic)
1160 {
1161         efx_qword_t test_event;
1162
1163         EFX_POPULATE_QWORD_2(test_event,
1164                              EV_CODE, DRV_GEN_EV_DECODE,
1165                              EVQ_MAGIC, magic);
1166         falcon_generate_event(channel, &test_event);
1167 }
1168
1169 void falcon_sim_phy_event(struct efx_nic *efx)
1170 {
1171         efx_qword_t phy_event;
1172
1173         EFX_POPULATE_QWORD_1(phy_event, EV_CODE, GLOBAL_EV_DECODE);
1174         if (EFX_IS10G(efx))
1175                 EFX_SET_OWORD_FIELD(phy_event, XG_PHY_INTR, 1);
1176         else
1177                 EFX_SET_OWORD_FIELD(phy_event, G_PHY0_INTR, 1);
1178
1179         falcon_generate_event(&efx->channel[0], &phy_event);
1180 }
1181
1182 /**************************************************************************
1183  *
1184  * Flush handling
1185  *
1186  **************************************************************************/
1187
1188
1189 static void falcon_poll_flush_events(struct efx_nic *efx)
1190 {
1191         struct efx_channel *channel = &efx->channel[0];
1192         struct efx_tx_queue *tx_queue;
1193         struct efx_rx_queue *rx_queue;
1194         unsigned int read_ptr, i;
1195
1196         read_ptr = channel->eventq_read_ptr;
1197         for (i = 0; i < FALCON_EVQ_SIZE; ++i) {
1198                 efx_qword_t *event = falcon_event(channel, read_ptr);
1199                 int ev_code, ev_sub_code, ev_queue;
1200                 bool ev_failed;
1201                 if (!falcon_event_present(event))
1202                         break;
1203
1204                 ev_code = EFX_QWORD_FIELD(*event, EV_CODE);
1205                 if (ev_code != DRIVER_EV_DECODE)
1206                         continue;
1207
1208                 ev_sub_code = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_CODE);
1209                 switch (ev_sub_code) {
1210                 case TX_DESCQ_FLS_DONE_EV_DECODE:
1211                         ev_queue = EFX_QWORD_FIELD(*event,
1212                                                    DRIVER_EV_TX_DESCQ_ID);
1213                         if (ev_queue < EFX_TX_QUEUE_COUNT) {
1214                                 tx_queue = efx->tx_queue + ev_queue;
1215                                 tx_queue->flushed = true;
1216                         }
1217                         break;
1218                 case RX_DESCQ_FLS_DONE_EV_DECODE:
1219                         ev_queue = EFX_QWORD_FIELD(*event,
1220                                                    DRIVER_EV_RX_DESCQ_ID);
1221                         ev_failed = EFX_QWORD_FIELD(*event,
1222                                                     DRIVER_EV_RX_FLUSH_FAIL);
1223                         if (ev_queue < efx->n_rx_queues) {
1224                                 rx_queue = efx->rx_queue + ev_queue;
1225
1226                                 /* retry the rx flush */
1227                                 if (ev_failed)
1228                                         falcon_flush_rx_queue(rx_queue);
1229                                 else
1230                                         rx_queue->flushed = true;
1231                         }
1232                         break;
1233                 }
1234
1235                 read_ptr = (read_ptr + 1) & FALCON_EVQ_MASK;
1236         }
1237 }
1238
1239 /* Handle tx and rx flushes at the same time, since they run in
1240  * parallel in the hardware and there's no reason for us to
1241  * serialise them */
1242 int falcon_flush_queues(struct efx_nic *efx)
1243 {
1244         struct efx_rx_queue *rx_queue;
1245         struct efx_tx_queue *tx_queue;
1246         int i;
1247         bool outstanding;
1248
1249         /* Issue flush requests */
1250         efx_for_each_tx_queue(tx_queue, efx) {
1251                 tx_queue->flushed = false;
1252                 falcon_flush_tx_queue(tx_queue);
1253         }
1254         efx_for_each_rx_queue(rx_queue, efx) {
1255                 rx_queue->flushed = false;
1256                 falcon_flush_rx_queue(rx_queue);
1257         }
1258
1259         /* Poll the evq looking for flush completions. Since we're not pushing
1260          * any more rx or tx descriptors at this point, we're in no danger of
1261          * overflowing the evq whilst we wait */
1262         for (i = 0; i < FALCON_FLUSH_POLL_COUNT; ++i) {
1263                 msleep(FALCON_FLUSH_INTERVAL);
1264                 falcon_poll_flush_events(efx);
1265
1266                 /* Check if every queue has been succesfully flushed */
1267                 outstanding = false;
1268                 efx_for_each_tx_queue(tx_queue, efx)
1269                         outstanding |= !tx_queue->flushed;
1270                 efx_for_each_rx_queue(rx_queue, efx)
1271                         outstanding |= !rx_queue->flushed;
1272                 if (!outstanding)
1273                         return 0;
1274         }
1275
1276         /* Mark the queues as all flushed. We're going to return failure
1277          * leading to a reset, or fake up success anyway. "flushed" now
1278          * indicates that we tried to flush. */
1279         efx_for_each_tx_queue(tx_queue, efx) {
1280                 if (!tx_queue->flushed)
1281                         EFX_ERR(efx, "tx queue %d flush command timed out\n",
1282                                 tx_queue->queue);
1283                 tx_queue->flushed = true;
1284         }
1285         efx_for_each_rx_queue(rx_queue, efx) {
1286                 if (!rx_queue->flushed)
1287                         EFX_ERR(efx, "rx queue %d flush command timed out\n",
1288                                 rx_queue->queue);
1289                 rx_queue->flushed = true;
1290         }
1291
1292         if (EFX_WORKAROUND_7803(efx))
1293                 return 0;
1294
1295         return -ETIMEDOUT;
1296 }
1297
1298 /**************************************************************************
1299  *
1300  * Falcon hardware interrupts
1301  * The hardware interrupt handler does very little work; all the event
1302  * queue processing is carried out by per-channel tasklets.
1303  *
1304  **************************************************************************/
1305
1306 /* Enable/disable/generate Falcon interrupts */
1307 static inline void falcon_interrupts(struct efx_nic *efx, int enabled,
1308                                      int force)
1309 {
1310         efx_oword_t int_en_reg_ker;
1311
1312         EFX_POPULATE_OWORD_2(int_en_reg_ker,
1313                              KER_INT_KER, force,
1314                              DRV_INT_EN_KER, enabled);
1315         falcon_write(efx, &int_en_reg_ker, INT_EN_REG_KER);
1316 }
1317
1318 void falcon_enable_interrupts(struct efx_nic *efx)
1319 {
1320         efx_oword_t int_adr_reg_ker;
1321         struct efx_channel *channel;
1322
1323         EFX_ZERO_OWORD(*((efx_oword_t *) efx->irq_status.addr));
1324         wmb(); /* Ensure interrupt vector is clear before interrupts enabled */
1325
1326         /* Program address */
1327         EFX_POPULATE_OWORD_2(int_adr_reg_ker,
1328                              NORM_INT_VEC_DIS_KER, EFX_INT_MODE_USE_MSI(efx),
1329                              INT_ADR_KER, efx->irq_status.dma_addr);
1330         falcon_write(efx, &int_adr_reg_ker, INT_ADR_REG_KER);
1331
1332         /* Enable interrupts */
1333         falcon_interrupts(efx, 1, 0);
1334
1335         /* Force processing of all the channels to get the EVQ RPTRs up to
1336            date */
1337         efx_for_each_channel(channel, efx)
1338                 efx_schedule_channel(channel);
1339 }
1340
1341 void falcon_disable_interrupts(struct efx_nic *efx)
1342 {
1343         /* Disable interrupts */
1344         falcon_interrupts(efx, 0, 0);
1345 }
1346
1347 /* Generate a Falcon test interrupt
1348  * Interrupt must already have been enabled, otherwise nasty things
1349  * may happen.
1350  */
1351 void falcon_generate_interrupt(struct efx_nic *efx)
1352 {
1353         falcon_interrupts(efx, 1, 1);
1354 }
1355
1356 /* Acknowledge a legacy interrupt from Falcon
1357  *
1358  * This acknowledges a legacy (not MSI) interrupt via INT_ACK_KER_REG.
1359  *
1360  * Due to SFC bug 3706 (silicon revision <=A1) reads can be duplicated in the
1361  * BIU. Interrupt acknowledge is read sensitive so must write instead
1362  * (then read to ensure the BIU collector is flushed)
1363  *
1364  * NB most hardware supports MSI interrupts
1365  */
1366 static inline void falcon_irq_ack_a1(struct efx_nic *efx)
1367 {
1368         efx_dword_t reg;
1369
1370         EFX_POPULATE_DWORD_1(reg, INT_ACK_DUMMY_DATA, 0xb7eb7e);
1371         falcon_writel(efx, &reg, INT_ACK_REG_KER_A1);
1372         falcon_readl(efx, &reg, WORK_AROUND_BROKEN_PCI_READS_REG_KER_A1);
1373 }
1374
1375 /* Process a fatal interrupt
1376  * Disable bus mastering ASAP and schedule a reset
1377  */
1378 static irqreturn_t falcon_fatal_interrupt(struct efx_nic *efx)
1379 {
1380         struct falcon_nic_data *nic_data = efx->nic_data;
1381         efx_oword_t *int_ker = efx->irq_status.addr;
1382         efx_oword_t fatal_intr;
1383         int error, mem_perr;
1384         static int n_int_errors;
1385
1386         falcon_read(efx, &fatal_intr, FATAL_INTR_REG_KER);
1387         error = EFX_OWORD_FIELD(fatal_intr, INT_KER_ERROR);
1388
1389         EFX_ERR(efx, "SYSTEM ERROR " EFX_OWORD_FMT " status "
1390                 EFX_OWORD_FMT ": %s\n", EFX_OWORD_VAL(*int_ker),
1391                 EFX_OWORD_VAL(fatal_intr),
1392                 error ? "disabling bus mastering" : "no recognised error");
1393         if (error == 0)
1394                 goto out;
1395
1396         /* If this is a memory parity error dump which blocks are offending */
1397         mem_perr = EFX_OWORD_FIELD(fatal_intr, MEM_PERR_INT_KER);
1398         if (mem_perr) {
1399                 efx_oword_t reg;
1400                 falcon_read(efx, &reg, MEM_STAT_REG_KER);
1401                 EFX_ERR(efx, "SYSTEM ERROR: memory parity error "
1402                         EFX_OWORD_FMT "\n", EFX_OWORD_VAL(reg));
1403         }
1404
1405         /* Disable both devices */
1406         pci_disable_device(efx->pci_dev);
1407         if (FALCON_IS_DUAL_FUNC(efx))
1408                 pci_disable_device(nic_data->pci_dev2);
1409         falcon_disable_interrupts(efx);
1410
1411         if (++n_int_errors < FALCON_MAX_INT_ERRORS) {
1412                 EFX_ERR(efx, "SYSTEM ERROR - reset scheduled\n");
1413                 efx_schedule_reset(efx, RESET_TYPE_INT_ERROR);
1414         } else {
1415                 EFX_ERR(efx, "SYSTEM ERROR - max number of errors seen."
1416                         "NIC will be disabled\n");
1417                 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1418         }
1419 out:
1420         return IRQ_HANDLED;
1421 }
1422
1423 /* Handle a legacy interrupt from Falcon
1424  * Acknowledges the interrupt and schedule event queue processing.
1425  */
1426 static irqreturn_t falcon_legacy_interrupt_b0(int irq, void *dev_id)
1427 {
1428         struct efx_nic *efx = dev_id;
1429         efx_oword_t *int_ker = efx->irq_status.addr;
1430         struct efx_channel *channel;
1431         efx_dword_t reg;
1432         u32 queues;
1433         int syserr;
1434
1435         /* Read the ISR which also ACKs the interrupts */
1436         falcon_readl(efx, &reg, INT_ISR0_B0);
1437         queues = EFX_EXTRACT_DWORD(reg, 0, 31);
1438
1439         /* Check to see if we have a serious error condition */
1440         syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT);
1441         if (unlikely(syserr))
1442                 return falcon_fatal_interrupt(efx);
1443
1444         if (queues == 0)
1445                 return IRQ_NONE;
1446
1447         efx->last_irq_cpu = raw_smp_processor_id();
1448         EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
1449                   irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
1450
1451         /* Schedule processing of any interrupting queues */
1452         channel = &efx->channel[0];
1453         while (queues) {
1454                 if (queues & 0x01)
1455                         efx_schedule_channel(channel);
1456                 channel++;
1457                 queues >>= 1;
1458         }
1459
1460         return IRQ_HANDLED;
1461 }
1462
1463
1464 static irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id)
1465 {
1466         struct efx_nic *efx = dev_id;
1467         efx_oword_t *int_ker = efx->irq_status.addr;
1468         struct efx_channel *channel;
1469         int syserr;
1470         int queues;
1471
1472         /* Check to see if this is our interrupt.  If it isn't, we
1473          * exit without having touched the hardware.
1474          */
1475         if (unlikely(EFX_OWORD_IS_ZERO(*int_ker))) {
1476                 EFX_TRACE(efx, "IRQ %d on CPU %d not for me\n", irq,
1477                           raw_smp_processor_id());
1478                 return IRQ_NONE;
1479         }
1480         efx->last_irq_cpu = raw_smp_processor_id();
1481         EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1482                   irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1483
1484         /* Check to see if we have a serious error condition */
1485         syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT);
1486         if (unlikely(syserr))
1487                 return falcon_fatal_interrupt(efx);
1488
1489         /* Determine interrupting queues, clear interrupt status
1490          * register and acknowledge the device interrupt.
1491          */
1492         BUILD_BUG_ON(INT_EVQS_WIDTH > EFX_MAX_CHANNELS);
1493         queues = EFX_OWORD_FIELD(*int_ker, INT_EVQS);
1494         EFX_ZERO_OWORD(*int_ker);
1495         wmb(); /* Ensure the vector is cleared before interrupt ack */
1496         falcon_irq_ack_a1(efx);
1497
1498         /* Schedule processing of any interrupting queues */
1499         channel = &efx->channel[0];
1500         while (queues) {
1501                 if (queues & 0x01)
1502                         efx_schedule_channel(channel);
1503                 channel++;
1504                 queues >>= 1;
1505         }
1506
1507         return IRQ_HANDLED;
1508 }
1509
1510 /* Handle an MSI interrupt from Falcon
1511  *
1512  * Handle an MSI hardware interrupt.  This routine schedules event
1513  * queue processing.  No interrupt acknowledgement cycle is necessary.
1514  * Also, we never need to check that the interrupt is for us, since
1515  * MSI interrupts cannot be shared.
1516  */
1517 static irqreturn_t falcon_msi_interrupt(int irq, void *dev_id)
1518 {
1519         struct efx_channel *channel = dev_id;
1520         struct efx_nic *efx = channel->efx;
1521         efx_oword_t *int_ker = efx->irq_status.addr;
1522         int syserr;
1523
1524         efx->last_irq_cpu = raw_smp_processor_id();
1525         EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1526                   irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1527
1528         /* Check to see if we have a serious error condition */
1529         syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT);
1530         if (unlikely(syserr))
1531                 return falcon_fatal_interrupt(efx);
1532
1533         /* Schedule processing of the channel */
1534         efx_schedule_channel(channel);
1535
1536         return IRQ_HANDLED;
1537 }
1538
1539
1540 /* Setup RSS indirection table.
1541  * This maps from the hash value of the packet to RXQ
1542  */
1543 static void falcon_setup_rss_indir_table(struct efx_nic *efx)
1544 {
1545         int i = 0;
1546         unsigned long offset;
1547         efx_dword_t dword;
1548
1549         if (falcon_rev(efx) < FALCON_REV_B0)
1550                 return;
1551
1552         for (offset = RX_RSS_INDIR_TBL_B0;
1553              offset < RX_RSS_INDIR_TBL_B0 + 0x800;
1554              offset += 0x10) {
1555                 EFX_POPULATE_DWORD_1(dword, RX_RSS_INDIR_ENT_B0,
1556                                      i % efx->n_rx_queues);
1557                 falcon_writel(efx, &dword, offset);
1558                 i++;
1559         }
1560 }
1561
1562 /* Hook interrupt handler(s)
1563  * Try MSI and then legacy interrupts.
1564  */
1565 int falcon_init_interrupt(struct efx_nic *efx)
1566 {
1567         struct efx_channel *channel;
1568         int rc;
1569
1570         if (!EFX_INT_MODE_USE_MSI(efx)) {
1571                 irq_handler_t handler;
1572                 if (falcon_rev(efx) >= FALCON_REV_B0)
1573                         handler = falcon_legacy_interrupt_b0;
1574                 else
1575                         handler = falcon_legacy_interrupt_a1;
1576
1577                 rc = request_irq(efx->legacy_irq, handler, IRQF_SHARED,
1578                                  efx->name, efx);
1579                 if (rc) {
1580                         EFX_ERR(efx, "failed to hook legacy IRQ %d\n",
1581                                 efx->pci_dev->irq);
1582                         goto fail1;
1583                 }
1584                 return 0;
1585         }
1586
1587         /* Hook MSI or MSI-X interrupt */
1588         efx_for_each_channel(channel, efx) {
1589                 rc = request_irq(channel->irq, falcon_msi_interrupt,
1590                                  IRQF_PROBE_SHARED, /* Not shared */
1591                                  channel->name, channel);
1592                 if (rc) {
1593                         EFX_ERR(efx, "failed to hook IRQ %d\n", channel->irq);
1594                         goto fail2;
1595                 }
1596         }
1597
1598         return 0;
1599
1600  fail2:
1601         efx_for_each_channel(channel, efx)
1602                 free_irq(channel->irq, channel);
1603  fail1:
1604         return rc;
1605 }
1606
1607 void falcon_fini_interrupt(struct efx_nic *efx)
1608 {
1609         struct efx_channel *channel;
1610         efx_oword_t reg;
1611
1612         /* Disable MSI/MSI-X interrupts */
1613         efx_for_each_channel(channel, efx) {
1614                 if (channel->irq)
1615                         free_irq(channel->irq, channel);
1616         }
1617
1618         /* ACK legacy interrupt */
1619         if (falcon_rev(efx) >= FALCON_REV_B0)
1620                 falcon_read(efx, &reg, INT_ISR0_B0);
1621         else
1622                 falcon_irq_ack_a1(efx);
1623
1624         /* Disable legacy interrupt */
1625         if (efx->legacy_irq)
1626                 free_irq(efx->legacy_irq, efx);
1627 }
1628
1629 /**************************************************************************
1630  *
1631  * EEPROM/flash
1632  *
1633  **************************************************************************
1634  */
1635
1636 #define FALCON_SPI_MAX_LEN sizeof(efx_oword_t)
1637
1638 static int falcon_spi_poll(struct efx_nic *efx)
1639 {
1640         efx_oword_t reg;
1641         falcon_read(efx, &reg, EE_SPI_HCMD_REG_KER);
1642         return EFX_OWORD_FIELD(reg, EE_SPI_HCMD_CMD_EN) ? -EBUSY : 0;
1643 }
1644
1645 /* Wait for SPI command completion */
1646 static int falcon_spi_wait(struct efx_nic *efx)
1647 {
1648         /* Most commands will finish quickly, so we start polling at
1649          * very short intervals.  Sometimes the command may have to
1650          * wait for VPD or expansion ROM access outside of our
1651          * control, so we allow up to 100 ms. */
1652         unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 10);
1653         int i;
1654
1655         for (i = 0; i < 10; i++) {
1656                 if (!falcon_spi_poll(efx))
1657                         return 0;
1658                 udelay(10);
1659         }
1660
1661         for (;;) {
1662                 if (!falcon_spi_poll(efx))
1663                         return 0;
1664                 if (time_after_eq(jiffies, timeout)) {
1665                         EFX_ERR(efx, "timed out waiting for SPI\n");
1666                         return -ETIMEDOUT;
1667                 }
1668                 schedule_timeout_uninterruptible(1);
1669         }
1670 }
1671
1672 int falcon_spi_cmd(const struct efx_spi_device *spi,
1673                    unsigned int command, int address,
1674                    const void *in, void *out, size_t len)
1675 {
1676         struct efx_nic *efx = spi->efx;
1677         bool addressed = (address >= 0);
1678         bool reading = (out != NULL);
1679         efx_oword_t reg;
1680         int rc;
1681
1682         /* Input validation */
1683         if (len > FALCON_SPI_MAX_LEN)
1684                 return -EINVAL;
1685         BUG_ON(!mutex_is_locked(&efx->spi_lock));
1686
1687         /* Check that previous command is not still running */
1688         rc = falcon_spi_poll(efx);
1689         if (rc)
1690                 return rc;
1691
1692         /* Program address register, if we have an address */
1693         if (addressed) {
1694                 EFX_POPULATE_OWORD_1(reg, EE_SPI_HADR_ADR, address);
1695                 falcon_write(efx, &reg, EE_SPI_HADR_REG_KER);
1696         }
1697
1698         /* Program data register, if we have data */
1699         if (in != NULL) {
1700                 memcpy(&reg, in, len);
1701                 falcon_write(efx, &reg, EE_SPI_HDATA_REG_KER);
1702         }
1703
1704         /* Issue read/write command */
1705         EFX_POPULATE_OWORD_7(reg,
1706                              EE_SPI_HCMD_CMD_EN, 1,
1707                              EE_SPI_HCMD_SF_SEL, spi->device_id,
1708                              EE_SPI_HCMD_DABCNT, len,
1709                              EE_SPI_HCMD_READ, reading,
1710                              EE_SPI_HCMD_DUBCNT, 0,
1711                              EE_SPI_HCMD_ADBCNT,
1712                              (addressed ? spi->addr_len : 0),
1713                              EE_SPI_HCMD_ENC, command);
1714         falcon_write(efx, &reg, EE_SPI_HCMD_REG_KER);
1715
1716         /* Wait for read/write to complete */
1717         rc = falcon_spi_wait(efx);
1718         if (rc)
1719                 return rc;
1720
1721         /* Read data */
1722         if (out != NULL) {
1723                 falcon_read(efx, &reg, EE_SPI_HDATA_REG_KER);
1724                 memcpy(out, &reg, len);
1725         }
1726
1727         return 0;
1728 }
1729
1730 static size_t
1731 falcon_spi_write_limit(const struct efx_spi_device *spi, size_t start)
1732 {
1733         return min(FALCON_SPI_MAX_LEN,
1734                    (spi->block_size - (start & (spi->block_size - 1))));
1735 }
1736
1737 static inline u8
1738 efx_spi_munge_command(const struct efx_spi_device *spi,
1739                       const u8 command, const unsigned int address)
1740 {
1741         return command | (((address >> 8) & spi->munge_address) << 3);
1742 }
1743
1744 /* Wait up to 10 ms for buffered write completion */
1745 int falcon_spi_wait_write(const struct efx_spi_device *spi)
1746 {
1747         struct efx_nic *efx = spi->efx;
1748         unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 100);
1749         u8 status;
1750         int rc;
1751
1752         for (;;) {
1753                 rc = falcon_spi_cmd(spi, SPI_RDSR, -1, NULL,
1754                                     &status, sizeof(status));
1755                 if (rc)
1756                         return rc;
1757                 if (!(status & SPI_STATUS_NRDY))
1758                         return 0;
1759                 if (time_after_eq(jiffies, timeout)) {
1760                         EFX_ERR(efx, "SPI write timeout on device %d"
1761                                 " last status=0x%02x\n",
1762                                 spi->device_id, status);
1763                         return -ETIMEDOUT;
1764                 }
1765                 schedule_timeout_uninterruptible(1);
1766         }
1767 }
1768
1769 int falcon_spi_read(const struct efx_spi_device *spi, loff_t start,
1770                     size_t len, size_t *retlen, u8 *buffer)
1771 {
1772         size_t block_len, pos = 0;
1773         unsigned int command;
1774         int rc = 0;
1775
1776         while (pos < len) {
1777                 block_len = min(len - pos, FALCON_SPI_MAX_LEN);
1778
1779                 command = efx_spi_munge_command(spi, SPI_READ, start + pos);
1780                 rc = falcon_spi_cmd(spi, command, start + pos, NULL,
1781                                     buffer + pos, block_len);
1782                 if (rc)
1783                         break;
1784                 pos += block_len;
1785
1786                 /* Avoid locking up the system */
1787                 cond_resched();
1788                 if (signal_pending(current)) {
1789                         rc = -EINTR;
1790                         break;
1791                 }
1792         }
1793
1794         if (retlen)
1795                 *retlen = pos;
1796         return rc;
1797 }
1798
1799 int falcon_spi_write(const struct efx_spi_device *spi, loff_t start,
1800                      size_t len, size_t *retlen, const u8 *buffer)
1801 {
1802         u8 verify_buffer[FALCON_SPI_MAX_LEN];
1803         size_t block_len, pos = 0;
1804         unsigned int command;
1805         int rc = 0;
1806
1807         while (pos < len) {
1808                 rc = falcon_spi_cmd(spi, SPI_WREN, -1, NULL, NULL, 0);
1809                 if (rc)
1810                         break;
1811
1812                 block_len = min(len - pos,
1813                                 falcon_spi_write_limit(spi, start + pos));
1814                 command = efx_spi_munge_command(spi, SPI_WRITE, start + pos);
1815                 rc = falcon_spi_cmd(spi, command, start + pos,
1816                                     buffer + pos, NULL, block_len);
1817                 if (rc)
1818                         break;
1819
1820                 rc = falcon_spi_wait_write(spi);
1821                 if (rc)
1822                         break;
1823
1824                 command = efx_spi_munge_command(spi, SPI_READ, start + pos);
1825                 rc = falcon_spi_cmd(spi, command, start + pos,
1826                                     NULL, verify_buffer, block_len);
1827                 if (memcmp(verify_buffer, buffer + pos, block_len)) {
1828                         rc = -EIO;
1829                         break;
1830                 }
1831
1832                 pos += block_len;
1833
1834                 /* Avoid locking up the system */
1835                 cond_resched();
1836                 if (signal_pending(current)) {
1837                         rc = -EINTR;
1838                         break;
1839                 }
1840         }
1841
1842         if (retlen)
1843                 *retlen = pos;
1844         return rc;
1845 }
1846
1847 /**************************************************************************
1848  *
1849  * MAC wrapper
1850  *
1851  **************************************************************************
1852  */
1853
1854 static int falcon_reset_macs(struct efx_nic *efx)
1855 {
1856         efx_oword_t reg;
1857         int count;
1858
1859         if (falcon_rev(efx) < FALCON_REV_B0) {
1860                 /* It's not safe to use GLB_CTL_REG to reset the
1861                  * macs, so instead use the internal MAC resets
1862                  */
1863                 if (!EFX_IS10G(efx)) {
1864                         EFX_POPULATE_OWORD_1(reg, GM_SW_RST, 1);
1865                         falcon_write(efx, &reg, GM_CFG1_REG);
1866                         udelay(1000);
1867
1868                         EFX_POPULATE_OWORD_1(reg, GM_SW_RST, 0);
1869                         falcon_write(efx, &reg, GM_CFG1_REG);
1870                         udelay(1000);
1871                         return 0;
1872                 } else {
1873                         EFX_POPULATE_OWORD_1(reg, XM_CORE_RST, 1);
1874                         falcon_write(efx, &reg, XM_GLB_CFG_REG);
1875
1876                         for (count = 0; count < 10000; count++) {
1877                                 falcon_read(efx, &reg, XM_GLB_CFG_REG);
1878                                 if (EFX_OWORD_FIELD(reg, XM_CORE_RST) == 0)
1879                                         return 0;
1880                                 udelay(10);
1881                         }
1882
1883                         EFX_ERR(efx, "timed out waiting for XMAC core reset\n");
1884                         return -ETIMEDOUT;
1885                 }
1886         }
1887
1888         /* MAC stats will fail whilst the TX fifo is draining. Serialise
1889          * the drain sequence with the statistics fetch */
1890         spin_lock(&efx->stats_lock);
1891
1892         falcon_read(efx, &reg, MAC0_CTRL_REG_KER);
1893         EFX_SET_OWORD_FIELD(reg, TXFIFO_DRAIN_EN_B0, 1);
1894         falcon_write(efx, &reg, MAC0_CTRL_REG_KER);
1895
1896         falcon_read(efx, &reg, GLB_CTL_REG_KER);
1897         EFX_SET_OWORD_FIELD(reg, RST_XGTX, 1);
1898         EFX_SET_OWORD_FIELD(reg, RST_XGRX, 1);
1899         EFX_SET_OWORD_FIELD(reg, RST_EM, 1);
1900         falcon_write(efx, &reg, GLB_CTL_REG_KER);
1901
1902         count = 0;
1903         while (1) {
1904                 falcon_read(efx, &reg, GLB_CTL_REG_KER);
1905                 if (!EFX_OWORD_FIELD(reg, RST_XGTX) &&
1906                     !EFX_OWORD_FIELD(reg, RST_XGRX) &&
1907                     !EFX_OWORD_FIELD(reg, RST_EM)) {
1908                         EFX_LOG(efx, "Completed MAC reset after %d loops\n",
1909                                 count);
1910                         break;
1911                 }
1912                 if (count > 20) {
1913                         EFX_ERR(efx, "MAC reset failed\n");
1914                         break;
1915                 }
1916                 count++;
1917                 udelay(10);
1918         }
1919
1920         spin_unlock(&efx->stats_lock);
1921
1922         /* If we've reset the EM block and the link is up, then
1923          * we'll have to kick the XAUI link so the PHY can recover */
1924         if (efx->link_up && EFX_IS10G(efx) && EFX_WORKAROUND_5147(efx))
1925                 falcon_reset_xaui(efx);
1926
1927         return 0;
1928 }
1929
1930 void falcon_drain_tx_fifo(struct efx_nic *efx)
1931 {
1932         efx_oword_t reg;
1933
1934         if ((falcon_rev(efx) < FALCON_REV_B0) ||
1935             (efx->loopback_mode != LOOPBACK_NONE))
1936                 return;
1937
1938         falcon_read(efx, &reg, MAC0_CTRL_REG_KER);
1939         /* There is no point in draining more than once */
1940         if (EFX_OWORD_FIELD(reg, TXFIFO_DRAIN_EN_B0))
1941                 return;
1942
1943         falcon_reset_macs(efx);
1944 }
1945
1946 void falcon_deconfigure_mac_wrapper(struct efx_nic *efx)
1947 {
1948         efx_oword_t reg;
1949
1950         if (falcon_rev(efx) < FALCON_REV_B0)
1951                 return;
1952
1953         /* Isolate the MAC -> RX */
1954         falcon_read(efx, &reg, RX_CFG_REG_KER);
1955         EFX_SET_OWORD_FIELD(reg, RX_INGR_EN_B0, 0);
1956         falcon_write(efx, &reg, RX_CFG_REG_KER);
1957
1958         if (!efx->link_up)
1959                 falcon_drain_tx_fifo(efx);
1960 }
1961
1962 void falcon_reconfigure_mac_wrapper(struct efx_nic *efx)
1963 {
1964         efx_oword_t reg;
1965         int link_speed;
1966         bool tx_fc;
1967
1968         switch (efx->link_speed) {
1969         case 10000: link_speed = 3; break;
1970         case 1000:  link_speed = 2; break;
1971         case 100:   link_speed = 1; break;
1972         default:    link_speed = 0; break;
1973         }
1974         /* MAC_LINK_STATUS controls MAC backpressure but doesn't work
1975          * as advertised.  Disable to ensure packets are not
1976          * indefinitely held and TX queue can be flushed at any point
1977          * while the link is down. */
1978         EFX_POPULATE_OWORD_5(reg,
1979                              MAC_XOFF_VAL, 0xffff /* max pause time */,
1980                              MAC_BCAD_ACPT, 1,
1981                              MAC_UC_PROM, efx->promiscuous,
1982                              MAC_LINK_STATUS, 1, /* always set */
1983                              MAC_SPEED, link_speed);
1984         /* On B0, MAC backpressure can be disabled and packets get
1985          * discarded. */
1986         if (falcon_rev(efx) >= FALCON_REV_B0) {
1987                 EFX_SET_OWORD_FIELD(reg, TXFIFO_DRAIN_EN_B0,
1988                                     !efx->link_up);
1989         }
1990
1991         falcon_write(efx, &reg, MAC0_CTRL_REG_KER);
1992
1993         /* Restore the multicast hash registers. */
1994         falcon_set_multicast_hash(efx);
1995
1996         /* Transmission of pause frames when RX crosses the threshold is
1997          * covered by RX_XOFF_MAC_EN and XM_TX_CFG_REG:XM_FCNTL.
1998          * Action on receipt of pause frames is controller by XM_DIS_FCNTL */
1999         tx_fc = !!(efx->link_fc & EFX_FC_TX);
2000         falcon_read(efx, &reg, RX_CFG_REG_KER);
2001         EFX_SET_OWORD_FIELD_VER(efx, reg, RX_XOFF_MAC_EN, tx_fc);
2002
2003         /* Unisolate the MAC -> RX */
2004         if (falcon_rev(efx) >= FALCON_REV_B0)
2005                 EFX_SET_OWORD_FIELD(reg, RX_INGR_EN_B0, 1);
2006         falcon_write(efx, &reg, RX_CFG_REG_KER);
2007 }
2008
2009 int falcon_dma_stats(struct efx_nic *efx, unsigned int done_offset)
2010 {
2011         efx_oword_t reg;
2012         u32 *dma_done;
2013         int i;
2014
2015         if (disable_dma_stats)
2016                 return 0;
2017
2018         /* Statistics fetch will fail if the MAC is in TX drain */
2019         if (falcon_rev(efx) >= FALCON_REV_B0) {
2020                 efx_oword_t temp;
2021                 falcon_read(efx, &temp, MAC0_CTRL_REG_KER);
2022                 if (EFX_OWORD_FIELD(temp, TXFIFO_DRAIN_EN_B0))
2023                         return 0;
2024         }
2025
2026         dma_done = (efx->stats_buffer.addr + done_offset);
2027         *dma_done = FALCON_STATS_NOT_DONE;
2028         wmb(); /* ensure done flag is clear */
2029
2030         /* Initiate DMA transfer of stats */
2031         EFX_POPULATE_OWORD_2(reg,
2032                              MAC_STAT_DMA_CMD, 1,
2033                              MAC_STAT_DMA_ADR,
2034                              efx->stats_buffer.dma_addr);
2035         falcon_write(efx, &reg, MAC0_STAT_DMA_REG_KER);
2036
2037         /* Wait for transfer to complete */
2038         for (i = 0; i < 400; i++) {
2039                 if (*(volatile u32 *)dma_done == FALCON_STATS_DONE) {
2040                         rmb(); /* Ensure the stats are valid. */
2041                         return 0;
2042                 }
2043                 udelay(10);
2044         }
2045
2046         EFX_ERR(efx, "timed out waiting for statistics\n");
2047         return -ETIMEDOUT;
2048 }
2049
2050 /**************************************************************************
2051  *
2052  * PHY access via GMII
2053  *
2054  **************************************************************************
2055  */
2056
2057 /* Use the top bit of the MII PHY id to indicate the PHY type
2058  * (1G/10G), with the remaining bits as the actual PHY id.
2059  *
2060  * This allows us to avoid leaking information from the mii_if_info
2061  * structure into other data structures.
2062  */
2063 #define FALCON_PHY_ID_ID_WIDTH  EFX_WIDTH(MD_PRT_DEV_ADR)
2064 #define FALCON_PHY_ID_ID_MASK   ((1 << FALCON_PHY_ID_ID_WIDTH) - 1)
2065 #define FALCON_PHY_ID_WIDTH     (FALCON_PHY_ID_ID_WIDTH + 1)
2066 #define FALCON_PHY_ID_MASK      ((1 << FALCON_PHY_ID_WIDTH) - 1)
2067 #define FALCON_PHY_ID_10G       (1 << (FALCON_PHY_ID_WIDTH - 1))
2068
2069
2070 /* Packing the clause 45 port and device fields into a single value */
2071 #define MD_PRT_ADR_COMP_LBN   (MD_PRT_ADR_LBN - MD_DEV_ADR_LBN)
2072 #define MD_PRT_ADR_COMP_WIDTH  MD_PRT_ADR_WIDTH
2073 #define MD_DEV_ADR_COMP_LBN    0
2074 #define MD_DEV_ADR_COMP_WIDTH  MD_DEV_ADR_WIDTH
2075
2076
2077 /* Wait for GMII access to complete */
2078 static int falcon_gmii_wait(struct efx_nic *efx)
2079 {
2080         efx_dword_t md_stat;
2081         int count;
2082
2083         /* wait upto 50ms - taken max from datasheet */
2084         for (count = 0; count < 5000; count++) {
2085                 falcon_readl(efx, &md_stat, MD_STAT_REG_KER);
2086                 if (EFX_DWORD_FIELD(md_stat, MD_BSY) == 0) {
2087                         if (EFX_DWORD_FIELD(md_stat, MD_LNFL) != 0 ||
2088                             EFX_DWORD_FIELD(md_stat, MD_BSERR) != 0) {
2089                                 EFX_ERR(efx, "error from GMII access "
2090                                         EFX_DWORD_FMT"\n",
2091                                         EFX_DWORD_VAL(md_stat));
2092                                 return -EIO;
2093                         }
2094                         return 0;
2095                 }
2096                 udelay(10);
2097         }
2098         EFX_ERR(efx, "timed out waiting for GMII\n");
2099         return -ETIMEDOUT;
2100 }
2101
2102 /* Writes a GMII register of a PHY connected to Falcon using MDIO. */
2103 static void falcon_mdio_write(struct net_device *net_dev, int phy_id,
2104                               int addr, int value)
2105 {
2106         struct efx_nic *efx = netdev_priv(net_dev);
2107         unsigned int phy_id2 = phy_id & FALCON_PHY_ID_ID_MASK;
2108         efx_oword_t reg;
2109
2110         /* The 'generic' prt/dev packing in mdio_10g.h is conveniently
2111          * chosen so that the only current user, Falcon, can take the
2112          * packed value and use them directly.
2113          * Fail to build if this assumption is broken.
2114          */
2115         BUILD_BUG_ON(FALCON_PHY_ID_10G != MDIO45_XPRT_ID_IS10G);
2116         BUILD_BUG_ON(FALCON_PHY_ID_ID_WIDTH != MDIO45_PRT_DEV_WIDTH);
2117         BUILD_BUG_ON(MD_PRT_ADR_COMP_LBN != MDIO45_PRT_ID_COMP_LBN);
2118         BUILD_BUG_ON(MD_DEV_ADR_COMP_LBN != MDIO45_DEV_ID_COMP_LBN);
2119
2120         if (phy_id2 == PHY_ADDR_INVALID)
2121                 return;
2122
2123         /* See falcon_mdio_read for an explanation. */
2124         if (!(phy_id & FALCON_PHY_ID_10G)) {
2125                 int mmd = ffs(efx->phy_op->mmds) - 1;
2126                 EFX_TRACE(efx, "Fixing erroneous clause22 write\n");
2127                 phy_id2 = mdio_clause45_pack(phy_id2, mmd)
2128                         & FALCON_PHY_ID_ID_MASK;
2129         }
2130
2131         EFX_REGDUMP(efx, "writing GMII %d register %02x with %04x\n", phy_id,
2132                     addr, value);
2133
2134         spin_lock_bh(&efx->phy_lock);
2135
2136         /* Check MII not currently being accessed */
2137         if (falcon_gmii_wait(efx) != 0)
2138                 goto out;
2139
2140         /* Write the address/ID register */
2141         EFX_POPULATE_OWORD_1(reg, MD_PHY_ADR, addr);
2142         falcon_write(efx, &reg, MD_PHY_ADR_REG_KER);
2143
2144         EFX_POPULATE_OWORD_1(reg, MD_PRT_DEV_ADR, phy_id2);
2145         falcon_write(efx, &reg, MD_ID_REG_KER);
2146
2147         /* Write data */
2148         EFX_POPULATE_OWORD_1(reg, MD_TXD, value);
2149         falcon_write(efx, &reg, MD_TXD_REG_KER);
2150
2151         EFX_POPULATE_OWORD_2(reg,
2152                              MD_WRC, 1,
2153                              MD_GC, 0);
2154         falcon_write(efx, &reg, MD_CS_REG_KER);
2155
2156         /* Wait for data to be written */
2157         if (falcon_gmii_wait(efx) != 0) {
2158                 /* Abort the write operation */
2159                 EFX_POPULATE_OWORD_2(reg,
2160                                      MD_WRC, 0,
2161                                      MD_GC, 1);
2162                 falcon_write(efx, &reg, MD_CS_REG_KER);
2163                 udelay(10);
2164         }
2165
2166  out:
2167         spin_unlock_bh(&efx->phy_lock);
2168 }
2169
2170 /* Reads a GMII register from a PHY connected to Falcon.  If no value
2171  * could be read, -1 will be returned. */
2172 static int falcon_mdio_read(struct net_device *net_dev, int phy_id, int addr)
2173 {
2174         struct efx_nic *efx = netdev_priv(net_dev);
2175         unsigned int phy_addr = phy_id & FALCON_PHY_ID_ID_MASK;
2176         efx_oword_t reg;
2177         int value = -1;
2178
2179         if (phy_addr == PHY_ADDR_INVALID)
2180                 return -1;
2181
2182         /* Our PHY code knows whether it needs to talk clause 22(1G) or 45(10G)
2183          * but the generic Linux code does not make any distinction or have
2184          * any state for this.
2185          * We spot the case where someone tried to talk 22 to a 45 PHY and
2186          * redirect the request to the lowest numbered MMD as a clause45
2187          * request. This is enough to allow simple queries like id and link
2188          * state to succeed. TODO: We may need to do more in future.
2189          */
2190         if (!(phy_id & FALCON_PHY_ID_10G)) {
2191                 int mmd = ffs(efx->phy_op->mmds) - 1;
2192                 EFX_TRACE(efx, "Fixing erroneous clause22 read\n");
2193                 phy_addr = mdio_clause45_pack(phy_addr, mmd)
2194                         & FALCON_PHY_ID_ID_MASK;
2195         }
2196
2197         spin_lock_bh(&efx->phy_lock);
2198
2199         /* Check MII not currently being accessed */
2200         if (falcon_gmii_wait(efx) != 0)
2201                 goto out;
2202
2203         EFX_POPULATE_OWORD_1(reg, MD_PHY_ADR, addr);
2204         falcon_write(efx, &reg, MD_PHY_ADR_REG_KER);
2205
2206         EFX_POPULATE_OWORD_1(reg, MD_PRT_DEV_ADR, phy_addr);
2207         falcon_write(efx, &reg, MD_ID_REG_KER);
2208
2209         /* Request data to be read */
2210         EFX_POPULATE_OWORD_2(reg, MD_RDC, 1, MD_GC, 0);
2211         falcon_write(efx, &reg, MD_CS_REG_KER);
2212
2213         /* Wait for data to become available */
2214         value = falcon_gmii_wait(efx);
2215         if (value == 0) {
2216                 falcon_read(efx, &reg, MD_RXD_REG_KER);
2217                 value = EFX_OWORD_FIELD(reg, MD_RXD);
2218                 EFX_REGDUMP(efx, "read from GMII %d register %02x, got %04x\n",
2219                             phy_id, addr, value);
2220         } else {
2221                 /* Abort the read operation */
2222                 EFX_POPULATE_OWORD_2(reg,
2223                                      MD_RIC, 0,
2224                                      MD_GC, 1);
2225                 falcon_write(efx, &reg, MD_CS_REG_KER);
2226
2227                 EFX_LOG(efx, "read from GMII 0x%x register %02x, got "
2228                         "error %d\n", phy_id, addr, value);
2229         }
2230
2231  out:
2232         spin_unlock_bh(&efx->phy_lock);
2233
2234         return value;
2235 }
2236
2237 static void falcon_init_mdio(struct mii_if_info *gmii)
2238 {
2239         gmii->mdio_read = falcon_mdio_read;
2240         gmii->mdio_write = falcon_mdio_write;
2241         gmii->phy_id_mask = FALCON_PHY_ID_MASK;
2242         gmii->reg_num_mask = ((1 << EFX_WIDTH(MD_PHY_ADR)) - 1);
2243 }
2244
2245 static int falcon_probe_phy(struct efx_nic *efx)
2246 {
2247         switch (efx->phy_type) {
2248         case PHY_TYPE_SFX7101:
2249                 efx->phy_op = &falcon_sfx7101_phy_ops;
2250                 break;
2251         case PHY_TYPE_SFT9001A:
2252         case PHY_TYPE_SFT9001B:
2253                 efx->phy_op = &falcon_sft9001_phy_ops;
2254                 break;
2255         case PHY_TYPE_XFP:
2256                 efx->phy_op = &falcon_xfp_phy_ops;
2257                 break;
2258         default:
2259                 EFX_ERR(efx, "Unknown PHY type %d\n",
2260                         efx->phy_type);
2261                 return -1;
2262         }
2263
2264         if (efx->phy_op->macs & EFX_XMAC)
2265                 efx->loopback_modes |= ((1 << LOOPBACK_XGMII) |
2266                                         (1 << LOOPBACK_XGXS) |
2267                                         (1 << LOOPBACK_XAUI));
2268         if (efx->phy_op->macs & EFX_GMAC)
2269                 efx->loopback_modes |= (1 << LOOPBACK_GMAC);
2270         efx->loopback_modes |= efx->phy_op->loopbacks;
2271
2272         return 0;
2273 }
2274
2275 int falcon_switch_mac(struct efx_nic *efx)
2276 {
2277         struct efx_mac_operations *old_mac_op = efx->mac_op;
2278         efx_oword_t nic_stat;
2279         unsigned strap_val;
2280
2281         /* Internal loopbacks override the phy speed setting */
2282         if (efx->loopback_mode == LOOPBACK_GMAC) {
2283                 efx->link_speed = 1000;
2284                 efx->link_fd = true;
2285         } else if (LOOPBACK_INTERNAL(efx)) {
2286                 efx->link_speed = 10000;
2287                 efx->link_fd = true;
2288         }
2289
2290         efx->mac_op = (EFX_IS10G(efx) ?
2291                        &falcon_xmac_operations : &falcon_gmac_operations);
2292         if (old_mac_op == efx->mac_op)
2293                 return 0;
2294
2295         WARN_ON(!mutex_is_locked(&efx->mac_lock));
2296
2297         /* Not all macs support a mac-level link state */
2298         efx->mac_up = true;
2299
2300         falcon_read(efx, &nic_stat, NIC_STAT_REG);
2301         strap_val = EFX_IS10G(efx) ? 5 : 3;
2302         if (falcon_rev(efx) >= FALCON_REV_B0) {
2303                 EFX_SET_OWORD_FIELD(nic_stat, EE_STRAP_EN, 1);
2304                 EFX_SET_OWORD_FIELD(nic_stat, EE_STRAP_OVR, strap_val);
2305                 falcon_write(efx, &nic_stat, NIC_STAT_REG);
2306         } else {
2307                 /* Falcon A1 does not support 1G/10G speed switching
2308                  * and must not be used with a PHY that does. */
2309                 BUG_ON(EFX_OWORD_FIELD(nic_stat, STRAP_PINS) != strap_val);
2310         }
2311
2312
2313         EFX_LOG(efx, "selected %cMAC\n", EFX_IS10G(efx) ? 'X' : 'G');
2314         return falcon_reset_macs(efx);
2315 }
2316
2317 /* This call is responsible for hooking in the MAC and PHY operations */
2318 int falcon_probe_port(struct efx_nic *efx)
2319 {
2320         int rc;
2321
2322         /* Hook in PHY operations table */
2323         rc = falcon_probe_phy(efx);
2324         if (rc)
2325                 return rc;
2326
2327         /* Set up GMII structure for PHY */
2328         efx->mii.supports_gmii = true;
2329         falcon_init_mdio(&efx->mii);
2330
2331         /* Hardware flow ctrl. FalconA RX FIFO too small for pause generation */
2332         if (falcon_rev(efx) >= FALCON_REV_B0)
2333                 efx->wanted_fc = EFX_FC_RX | EFX_FC_TX;
2334         else
2335                 efx->wanted_fc = EFX_FC_RX;
2336
2337         /* Allocate buffer for stats */
2338         rc = falcon_alloc_buffer(efx, &efx->stats_buffer,
2339                                  FALCON_MAC_STATS_SIZE);
2340         if (rc)
2341                 return rc;
2342         EFX_LOG(efx, "stats buffer at %llx (virt %p phys %lx)\n",
2343                 (unsigned long long)efx->stats_buffer.dma_addr,
2344                 efx->stats_buffer.addr,
2345                 virt_to_phys(efx->stats_buffer.addr));
2346
2347         return 0;
2348 }
2349
2350 void falcon_remove_port(struct efx_nic *efx)
2351 {
2352         falcon_free_buffer(efx, &efx->stats_buffer);
2353 }
2354
2355 /**************************************************************************
2356  *
2357  * Multicast filtering
2358  *
2359  **************************************************************************
2360  */
2361
2362 void falcon_set_multicast_hash(struct efx_nic *efx)
2363 {
2364         union efx_multicast_hash *mc_hash = &efx->multicast_hash;
2365
2366         /* Broadcast packets go through the multicast hash filter.
2367          * ether_crc_le() of the broadcast address is 0xbe2612ff
2368          * so we always add bit 0xff to the mask.
2369          */
2370         set_bit_le(0xff, mc_hash->byte);
2371
2372         falcon_write(efx, &mc_hash->oword[0], MAC_MCAST_HASH_REG0_KER);
2373         falcon_write(efx, &mc_hash->oword[1], MAC_MCAST_HASH_REG1_KER);
2374 }
2375
2376
2377 /**************************************************************************
2378  *
2379  * Falcon test code
2380  *
2381  **************************************************************************/
2382
2383 int falcon_read_nvram(struct efx_nic *efx, struct falcon_nvconfig *nvconfig_out)
2384 {
2385         struct falcon_nvconfig *nvconfig;
2386         struct efx_spi_device *spi;
2387         void *region;
2388         int rc, magic_num, struct_ver;
2389         __le16 *word, *limit;
2390         u32 csum;
2391
2392         spi = efx->spi_flash ? efx->spi_flash : efx->spi_eeprom;
2393         if (!spi)
2394                 return -EINVAL;
2395
2396         region = kmalloc(FALCON_NVCONFIG_END, GFP_KERNEL);
2397         if (!region)
2398                 return -ENOMEM;
2399         nvconfig = region + NVCONFIG_OFFSET;
2400
2401         mutex_lock(&efx->spi_lock);
2402         rc = falcon_spi_read(spi, 0, FALCON_NVCONFIG_END, NULL, region);
2403         mutex_unlock(&efx->spi_lock);
2404         if (rc) {
2405                 EFX_ERR(efx, "Failed to read %s\n",
2406                         efx->spi_flash ? "flash" : "EEPROM");
2407                 rc = -EIO;
2408                 goto out;
2409         }
2410
2411         magic_num = le16_to_cpu(nvconfig->board_magic_num);
2412         struct_ver = le16_to_cpu(nvconfig->board_struct_ver);
2413
2414         rc = -EINVAL;
2415         if (magic_num != NVCONFIG_BOARD_MAGIC_NUM) {
2416                 EFX_ERR(efx, "NVRAM bad magic 0x%x\n", magic_num);
2417                 goto out;
2418         }
2419         if (struct_ver < 2) {
2420                 EFX_ERR(efx, "NVRAM has ancient version 0x%x\n", struct_ver);
2421                 goto out;
2422         } else if (struct_ver < 4) {
2423                 word = &nvconfig->board_magic_num;
2424                 limit = (__le16 *) (nvconfig + 1);
2425         } else {
2426                 word = region;
2427                 limit = region + FALCON_NVCONFIG_END;
2428         }
2429         for (csum = 0; word < limit; ++word)
2430                 csum += le16_to_cpu(*word);
2431
2432         if (~csum & 0xffff) {
2433                 EFX_ERR(efx, "NVRAM has incorrect checksum\n");
2434                 goto out;
2435         }
2436
2437         rc = 0;
2438         if (nvconfig_out)
2439                 memcpy(nvconfig_out, nvconfig, sizeof(*nvconfig));
2440
2441  out:
2442         kfree(region);
2443         return rc;
2444 }
2445
2446 /* Registers tested in the falcon register test */
2447 static struct {
2448         unsigned address;
2449         efx_oword_t mask;
2450 } efx_test_registers[] = {
2451         { ADR_REGION_REG_KER,
2452           EFX_OWORD32(0x0001FFFF, 0x0001FFFF, 0x0001FFFF, 0x0001FFFF) },
2453         { RX_CFG_REG_KER,
2454           EFX_OWORD32(0xFFFFFFFE, 0x00017FFF, 0x00000000, 0x00000000) },
2455         { TX_CFG_REG_KER,
2456           EFX_OWORD32(0x7FFF0037, 0x00000000, 0x00000000, 0x00000000) },
2457         { TX_CFG2_REG_KER,
2458           EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
2459         { MAC0_CTRL_REG_KER,
2460           EFX_OWORD32(0xFFFF0000, 0x00000000, 0x00000000, 0x00000000) },
2461         { SRM_TX_DC_CFG_REG_KER,
2462           EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
2463         { RX_DC_CFG_REG_KER,
2464           EFX_OWORD32(0x0000000F, 0x00000000, 0x00000000, 0x00000000) },
2465         { RX_DC_PF_WM_REG_KER,
2466           EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
2467         { DP_CTRL_REG,
2468           EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
2469         { GM_CFG2_REG,
2470           EFX_OWORD32(0x00007337, 0x00000000, 0x00000000, 0x00000000) },
2471         { GMF_CFG0_REG,
2472           EFX_OWORD32(0x00001F1F, 0x00000000, 0x00000000, 0x00000000) },
2473         { XM_GLB_CFG_REG,
2474           EFX_OWORD32(0x00000C68, 0x00000000, 0x00000000, 0x00000000) },
2475         { XM_TX_CFG_REG,
2476           EFX_OWORD32(0x00080164, 0x00000000, 0x00000000, 0x00000000) },
2477         { XM_RX_CFG_REG,
2478           EFX_OWORD32(0x07100A0C, 0x00000000, 0x00000000, 0x00000000) },
2479         { XM_RX_PARAM_REG,
2480           EFX_OWORD32(0x00001FF8, 0x00000000, 0x00000000, 0x00000000) },
2481         { XM_FC_REG,
2482           EFX_OWORD32(0xFFFF0001, 0x00000000, 0x00000000, 0x00000000) },
2483         { XM_ADR_LO_REG,
2484           EFX_OWORD32(0xFFFFFFFF, 0x00000000, 0x00000000, 0x00000000) },
2485         { XX_SD_CTL_REG,
2486           EFX_OWORD32(0x0003FF0F, 0x00000000, 0x00000000, 0x00000000) },
2487 };
2488
2489 static bool efx_masked_compare_oword(const efx_oword_t *a, const efx_oword_t *b,
2490                                      const efx_oword_t *mask)
2491 {
2492         return ((a->u64[0] ^ b->u64[0]) & mask->u64[0]) ||
2493                 ((a->u64[1] ^ b->u64[1]) & mask->u64[1]);
2494 }
2495
2496 int falcon_test_registers(struct efx_nic *efx)
2497 {
2498         unsigned address = 0, i, j;
2499         efx_oword_t mask, imask, original, reg, buf;
2500
2501         /* Falcon should be in loopback to isolate the XMAC from the PHY */
2502         WARN_ON(!LOOPBACK_INTERNAL(efx));
2503
2504         for (i = 0; i < ARRAY_SIZE(efx_test_registers); ++i) {
2505                 address = efx_test_registers[i].address;
2506                 mask = imask = efx_test_registers[i].mask;
2507                 EFX_INVERT_OWORD(imask);
2508
2509                 falcon_read(efx, &original, address);
2510
2511                 /* bit sweep on and off */
2512                 for (j = 0; j < 128; j++) {
2513                         if (!EFX_EXTRACT_OWORD32(mask, j, j))
2514                                 continue;
2515
2516                         /* Test this testable bit can be set in isolation */
2517                         EFX_AND_OWORD(reg, original, mask);
2518                         EFX_SET_OWORD32(reg, j, j, 1);
2519
2520                         falcon_write(efx, &reg, address);
2521                         falcon_read(efx, &buf, address);
2522
2523                         if (efx_masked_compare_oword(&reg, &buf, &mask))
2524                                 goto fail;
2525
2526                         /* Test this testable bit can be cleared in isolation */
2527                         EFX_OR_OWORD(reg, original, mask);
2528                         EFX_SET_OWORD32(reg, j, j, 0);
2529
2530                         falcon_write(efx, &reg, address);
2531                         falcon_read(efx, &buf, address);
2532
2533                         if (efx_masked_compare_oword(&reg, &buf, &mask))
2534                                 goto fail;
2535                 }
2536
2537                 falcon_write(efx, &original, address);
2538         }
2539
2540         return 0;
2541
2542 fail:
2543         EFX_ERR(efx, "wrote "EFX_OWORD_FMT" read "EFX_OWORD_FMT
2544                 " at address 0x%x mask "EFX_OWORD_FMT"\n", EFX_OWORD_VAL(reg),
2545                 EFX_OWORD_VAL(buf), address, EFX_OWORD_VAL(mask));
2546         return -EIO;
2547 }
2548
2549 /**************************************************************************
2550  *
2551  * Device reset
2552  *
2553  **************************************************************************
2554  */
2555
2556 /* Resets NIC to known state.  This routine must be called in process
2557  * context and is allowed to sleep. */
2558 int falcon_reset_hw(struct efx_nic *efx, enum reset_type method)
2559 {
2560         struct falcon_nic_data *nic_data = efx->nic_data;
2561         efx_oword_t glb_ctl_reg_ker;
2562         int rc;
2563
2564         EFX_LOG(efx, "performing hardware reset (%d)\n", method);
2565
2566         /* Initiate device reset */
2567         if (method == RESET_TYPE_WORLD) {
2568                 rc = pci_save_state(efx->pci_dev);
2569                 if (rc) {
2570                         EFX_ERR(efx, "failed to backup PCI state of primary "
2571                                 "function prior to hardware reset\n");
2572                         goto fail1;
2573                 }
2574                 if (FALCON_IS_DUAL_FUNC(efx)) {
2575                         rc = pci_save_state(nic_data->pci_dev2);
2576                         if (rc) {
2577                                 EFX_ERR(efx, "failed to backup PCI state of "
2578                                         "secondary function prior to "
2579                                         "hardware reset\n");
2580                                 goto fail2;
2581                         }
2582                 }
2583
2584                 EFX_POPULATE_OWORD_2(glb_ctl_reg_ker,
2585                                      EXT_PHY_RST_DUR, 0x7,
2586                                      SWRST, 1);
2587         } else {
2588                 int reset_phy = (method == RESET_TYPE_INVISIBLE ?
2589                                  EXCLUDE_FROM_RESET : 0);
2590
2591                 EFX_POPULATE_OWORD_7(glb_ctl_reg_ker,
2592                                      EXT_PHY_RST_CTL, reset_phy,
2593                                      PCIE_CORE_RST_CTL, EXCLUDE_FROM_RESET,
2594                                      PCIE_NSTCK_RST_CTL, EXCLUDE_FROM_RESET,
2595                                      PCIE_SD_RST_CTL, EXCLUDE_FROM_RESET,
2596                                      EE_RST_CTL, EXCLUDE_FROM_RESET,
2597                                      EXT_PHY_RST_DUR, 0x7 /* 10ms */,
2598                                      SWRST, 1);
2599         }
2600         falcon_write(efx, &glb_ctl_reg_ker, GLB_CTL_REG_KER);
2601
2602         EFX_LOG(efx, "waiting for hardware reset\n");
2603         schedule_timeout_uninterruptible(HZ / 20);
2604
2605         /* Restore PCI configuration if needed */
2606         if (method == RESET_TYPE_WORLD) {
2607                 if (FALCON_IS_DUAL_FUNC(efx)) {
2608                         rc = pci_restore_state(nic_data->pci_dev2);
2609                         if (rc) {
2610                                 EFX_ERR(efx, "failed to restore PCI config for "
2611                                         "the secondary function\n");
2612                                 goto fail3;
2613                         }
2614                 }
2615                 rc = pci_restore_state(efx->pci_dev);
2616                 if (rc) {
2617                         EFX_ERR(efx, "failed to restore PCI config for the "
2618                                 "primary function\n");
2619                         goto fail4;
2620                 }
2621                 EFX_LOG(efx, "successfully restored PCI config\n");
2622         }
2623
2624         /* Assert that reset complete */
2625         falcon_read(efx, &glb_ctl_reg_ker, GLB_CTL_REG_KER);
2626         if (EFX_OWORD_FIELD(glb_ctl_reg_ker, SWRST) != 0) {
2627                 rc = -ETIMEDOUT;
2628                 EFX_ERR(efx, "timed out waiting for hardware reset\n");
2629                 goto fail5;
2630         }
2631         EFX_LOG(efx, "hardware reset complete\n");
2632
2633         return 0;
2634
2635         /* pci_save_state() and pci_restore_state() MUST be called in pairs */
2636 fail2:
2637 fail3:
2638         pci_restore_state(efx->pci_dev);
2639 fail1:
2640 fail4:
2641 fail5:
2642         return rc;
2643 }
2644
2645 /* Zeroes out the SRAM contents.  This routine must be called in
2646  * process context and is allowed to sleep.
2647  */
2648 static int falcon_reset_sram(struct efx_nic *efx)
2649 {
2650         efx_oword_t srm_cfg_reg_ker, gpio_cfg_reg_ker;
2651         int count;
2652
2653         /* Set the SRAM wake/sleep GPIO appropriately. */
2654         falcon_read(efx, &gpio_cfg_reg_ker, GPIO_CTL_REG_KER);
2655         EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, GPIO1_OEN, 1);
2656         EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, GPIO1_OUT, 1);
2657         falcon_write(efx, &gpio_cfg_reg_ker, GPIO_CTL_REG_KER);
2658
2659         /* Initiate SRAM reset */
2660         EFX_POPULATE_OWORD_2(srm_cfg_reg_ker,
2661                              SRAM_OOB_BT_INIT_EN, 1,
2662                              SRM_NUM_BANKS_AND_BANK_SIZE, 0);
2663         falcon_write(efx, &srm_cfg_reg_ker, SRM_CFG_REG_KER);
2664
2665         /* Wait for SRAM reset to complete */
2666         count = 0;
2667         do {
2668                 EFX_LOG(efx, "waiting for SRAM reset (attempt %d)...\n", count);
2669
2670                 /* SRAM reset is slow; expect around 16ms */
2671                 schedule_timeout_uninterruptible(HZ / 50);
2672
2673                 /* Check for reset complete */
2674                 falcon_read(efx, &srm_cfg_reg_ker, SRM_CFG_REG_KER);
2675                 if (!EFX_OWORD_FIELD(srm_cfg_reg_ker, SRAM_OOB_BT_INIT_EN)) {
2676                         EFX_LOG(efx, "SRAM reset complete\n");
2677
2678                         return 0;
2679                 }
2680         } while (++count < 20); /* wait upto 0.4 sec */
2681
2682         EFX_ERR(efx, "timed out waiting for SRAM reset\n");
2683         return -ETIMEDOUT;
2684 }
2685
2686 static int falcon_spi_device_init(struct efx_nic *efx,
2687                                   struct efx_spi_device **spi_device_ret,
2688                                   unsigned int device_id, u32 device_type)
2689 {
2690         struct efx_spi_device *spi_device;
2691
2692         if (device_type != 0) {
2693                 spi_device = kmalloc(sizeof(*spi_device), GFP_KERNEL);
2694                 if (!spi_device)
2695                         return -ENOMEM;
2696                 spi_device->device_id = device_id;
2697                 spi_device->size =
2698                         1 << SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_SIZE);
2699                 spi_device->addr_len =
2700                         SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ADDR_LEN);
2701                 spi_device->munge_address = (spi_device->size == 1 << 9 &&
2702                                              spi_device->addr_len == 1);
2703                 spi_device->erase_command =
2704                         SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ERASE_CMD);
2705                 spi_device->erase_size =
2706                         1 << SPI_DEV_TYPE_FIELD(device_type,
2707                                                 SPI_DEV_TYPE_ERASE_SIZE);
2708                 spi_device->block_size =
2709                         1 << SPI_DEV_TYPE_FIELD(device_type,
2710                                                 SPI_DEV_TYPE_BLOCK_SIZE);
2711
2712                 spi_device->efx = efx;
2713         } else {
2714                 spi_device = NULL;
2715         }
2716
2717         kfree(*spi_device_ret);
2718         *spi_device_ret = spi_device;
2719         return 0;
2720 }
2721
2722
2723 static void falcon_remove_spi_devices(struct efx_nic *efx)
2724 {
2725         kfree(efx->spi_eeprom);
2726         efx->spi_eeprom = NULL;
2727         kfree(efx->spi_flash);
2728         efx->spi_flash = NULL;
2729 }
2730
2731 /* Extract non-volatile configuration */
2732 static int falcon_probe_nvconfig(struct efx_nic *efx)
2733 {
2734         struct falcon_nvconfig *nvconfig;
2735         int board_rev;
2736         int rc;
2737
2738         nvconfig = kmalloc(sizeof(*nvconfig), GFP_KERNEL);
2739         if (!nvconfig)
2740                 return -ENOMEM;
2741
2742         rc = falcon_read_nvram(efx, nvconfig);
2743         if (rc == -EINVAL) {
2744                 EFX_ERR(efx, "NVRAM is invalid therefore using defaults\n");
2745                 efx->phy_type = PHY_TYPE_NONE;
2746                 efx->mii.phy_id = PHY_ADDR_INVALID;
2747                 board_rev = 0;
2748                 rc = 0;
2749         } else if (rc) {
2750                 goto fail1;
2751         } else {
2752                 struct falcon_nvconfig_board_v2 *v2 = &nvconfig->board_v2;
2753                 struct falcon_nvconfig_board_v3 *v3 = &nvconfig->board_v3;
2754
2755                 efx->phy_type = v2->port0_phy_type;
2756                 efx->mii.phy_id = v2->port0_phy_addr;
2757                 board_rev = le16_to_cpu(v2->board_revision);
2758
2759                 if (le16_to_cpu(nvconfig->board_struct_ver) >= 3) {
2760                         __le32 fl = v3->spi_device_type[EE_SPI_FLASH];
2761                         __le32 ee = v3->spi_device_type[EE_SPI_EEPROM];
2762                         rc = falcon_spi_device_init(efx, &efx->spi_flash,
2763                                                     EE_SPI_FLASH,
2764                                                     le32_to_cpu(fl));
2765                         if (rc)
2766                                 goto fail2;
2767                         rc = falcon_spi_device_init(efx, &efx->spi_eeprom,
2768                                                     EE_SPI_EEPROM,
2769                                                     le32_to_cpu(ee));
2770                         if (rc)
2771                                 goto fail2;
2772                 }
2773         }
2774
2775         /* Read the MAC addresses */
2776         memcpy(efx->mac_address, nvconfig->mac_address[0], ETH_ALEN);
2777
2778         EFX_LOG(efx, "PHY is %d phy_id %d\n", efx->phy_type, efx->mii.phy_id);
2779
2780         efx_set_board_info(efx, board_rev);
2781
2782         kfree(nvconfig);
2783         return 0;
2784
2785  fail2:
2786         falcon_remove_spi_devices(efx);
2787  fail1:
2788         kfree(nvconfig);
2789         return rc;
2790 }
2791
2792 /* Probe the NIC variant (revision, ASIC vs FPGA, function count, port
2793  * count, port speed).  Set workaround and feature flags accordingly.
2794  */
2795 static int falcon_probe_nic_variant(struct efx_nic *efx)
2796 {
2797         efx_oword_t altera_build;
2798         efx_oword_t nic_stat;
2799
2800         falcon_read(efx, &altera_build, ALTERA_BUILD_REG_KER);
2801         if (EFX_OWORD_FIELD(altera_build, VER_ALL)) {
2802                 EFX_ERR(efx, "Falcon FPGA not supported\n");
2803                 return -ENODEV;
2804         }
2805
2806         falcon_read(efx, &nic_stat, NIC_STAT_REG);
2807
2808         switch (falcon_rev(efx)) {
2809         case FALCON_REV_A0:
2810         case 0xff:
2811                 EFX_ERR(efx, "Falcon rev A0 not supported\n");
2812                 return -ENODEV;
2813
2814         case FALCON_REV_A1:
2815                 if (EFX_OWORD_FIELD(nic_stat, STRAP_PCIE) == 0) {
2816                         EFX_ERR(efx, "Falcon rev A1 PCI-X not supported\n");
2817                         return -ENODEV;
2818                 }
2819                 break;
2820
2821         case FALCON_REV_B0:
2822                 break;
2823
2824         default:
2825                 EFX_ERR(efx, "Unknown Falcon rev %d\n", falcon_rev(efx));
2826                 return -ENODEV;
2827         }
2828
2829         /* Initial assumed speed */
2830         efx->link_speed = EFX_OWORD_FIELD(nic_stat, STRAP_10G) ? 10000 : 1000;
2831
2832         return 0;
2833 }
2834
2835 /* Probe all SPI devices on the NIC */
2836 static void falcon_probe_spi_devices(struct efx_nic *efx)
2837 {
2838         efx_oword_t nic_stat, gpio_ctl, ee_vpd_cfg;
2839         int boot_dev;
2840
2841         falcon_read(efx, &gpio_ctl, GPIO_CTL_REG_KER);
2842         falcon_read(efx, &nic_stat, NIC_STAT_REG);
2843         falcon_read(efx, &ee_vpd_cfg, EE_VPD_CFG_REG_KER);
2844
2845         if (EFX_OWORD_FIELD(gpio_ctl, BOOTED_USING_NVDEVICE)) {
2846                 boot_dev = (EFX_OWORD_FIELD(nic_stat, SF_PRST) ?
2847                             EE_SPI_FLASH : EE_SPI_EEPROM);
2848                 EFX_LOG(efx, "Booted from %s\n",
2849                         boot_dev == EE_SPI_FLASH ? "flash" : "EEPROM");
2850         } else {
2851                 /* Disable VPD and set clock dividers to safe
2852                  * values for initial programming. */
2853                 boot_dev = -1;
2854                 EFX_LOG(efx, "Booted from internal ASIC settings;"
2855                         " setting SPI config\n");
2856                 EFX_POPULATE_OWORD_3(ee_vpd_cfg, EE_VPD_EN, 0,
2857                                      /* 125 MHz / 7 ~= 20 MHz */
2858                                      EE_SF_CLOCK_DIV, 7,
2859                                      /* 125 MHz / 63 ~= 2 MHz */
2860                                      EE_EE_CLOCK_DIV, 63);
2861                 falcon_write(efx, &ee_vpd_cfg, EE_VPD_CFG_REG_KER);
2862         }
2863
2864         if (boot_dev == EE_SPI_FLASH)
2865                 falcon_spi_device_init(efx, &efx->spi_flash, EE_SPI_FLASH,
2866                                        default_flash_type);
2867         if (boot_dev == EE_SPI_EEPROM)
2868                 falcon_spi_device_init(efx, &efx->spi_eeprom, EE_SPI_EEPROM,
2869                                        large_eeprom_type);
2870 }
2871
2872 int falcon_probe_nic(struct efx_nic *efx)
2873 {
2874         struct falcon_nic_data *nic_data;
2875         int rc;
2876
2877         /* Allocate storage for hardware specific data */
2878         nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
2879         if (!nic_data)
2880                 return -ENOMEM;
2881         efx->nic_data = nic_data;
2882
2883         /* Determine number of ports etc. */
2884         rc = falcon_probe_nic_variant(efx);
2885         if (rc)
2886                 goto fail1;
2887
2888         /* Probe secondary function if expected */
2889         if (FALCON_IS_DUAL_FUNC(efx)) {
2890                 struct pci_dev *dev = pci_dev_get(efx->pci_dev);
2891
2892                 while ((dev = pci_get_device(EFX_VENDID_SFC, FALCON_A_S_DEVID,
2893                                              dev))) {
2894                         if (dev->bus == efx->pci_dev->bus &&
2895                             dev->devfn == efx->pci_dev->devfn + 1) {
2896                                 nic_data->pci_dev2 = dev;
2897                                 break;
2898                         }
2899                 }
2900                 if (!nic_data->pci_dev2) {
2901                         EFX_ERR(efx, "failed to find secondary function\n");
2902                         rc = -ENODEV;
2903                         goto fail2;
2904                 }
2905         }
2906
2907         /* Now we can reset the NIC */
2908         rc = falcon_reset_hw(efx, RESET_TYPE_ALL);
2909         if (rc) {
2910                 EFX_ERR(efx, "failed to reset NIC\n");
2911                 goto fail3;
2912         }
2913
2914         /* Allocate memory for INT_KER */
2915         rc = falcon_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t));
2916         if (rc)
2917                 goto fail4;
2918         BUG_ON(efx->irq_status.dma_addr & 0x0f);
2919
2920         EFX_LOG(efx, "INT_KER at %llx (virt %p phys %lx)\n",
2921                 (unsigned long long)efx->irq_status.dma_addr,
2922                 efx->irq_status.addr, virt_to_phys(efx->irq_status.addr));
2923
2924         falcon_probe_spi_devices(efx);
2925
2926         /* Read in the non-volatile configuration */
2927         rc = falcon_probe_nvconfig(efx);
2928         if (rc)
2929                 goto fail5;
2930
2931         /* Initialise I2C adapter */
2932         efx->i2c_adap.owner = THIS_MODULE;
2933         nic_data->i2c_data = falcon_i2c_bit_operations;
2934         nic_data->i2c_data.data = efx;
2935         efx->i2c_adap.algo_data = &nic_data->i2c_data;
2936         efx->i2c_adap.dev.parent = &efx->pci_dev->dev;
2937         strlcpy(efx->i2c_adap.name, "SFC4000 GPIO", sizeof(efx->i2c_adap.name));
2938         rc = i2c_bit_add_bus(&efx->i2c_adap);
2939         if (rc)
2940                 goto fail5;
2941
2942         return 0;
2943
2944  fail5:
2945         falcon_remove_spi_devices(efx);
2946         falcon_free_buffer(efx, &efx->irq_status);
2947  fail4:
2948  fail3:
2949         if (nic_data->pci_dev2) {
2950                 pci_dev_put(nic_data->pci_dev2);
2951                 nic_data->pci_dev2 = NULL;
2952         }
2953  fail2:
2954  fail1:
2955         kfree(efx->nic_data);
2956         return rc;
2957 }
2958
2959 /* This call performs hardware-specific global initialisation, such as
2960  * defining the descriptor cache sizes and number of RSS channels.
2961  * It does not set up any buffers, descriptor rings or event queues.
2962  */
2963 int falcon_init_nic(struct efx_nic *efx)
2964 {
2965         efx_oword_t temp;
2966         unsigned thresh;
2967         int rc;
2968
2969         /* Use on-chip SRAM */
2970         falcon_read(efx, &temp, NIC_STAT_REG);
2971         EFX_SET_OWORD_FIELD(temp, ONCHIP_SRAM, 1);
2972         falcon_write(efx, &temp, NIC_STAT_REG);
2973
2974         /* Set the source of the GMAC clock */
2975         if (falcon_rev(efx) == FALCON_REV_B0) {
2976                 falcon_read(efx, &temp, GPIO_CTL_REG_KER);
2977                 EFX_SET_OWORD_FIELD(temp, GPIO_USE_NIC_CLK, true);
2978                 falcon_write(efx, &temp, GPIO_CTL_REG_KER);
2979         }
2980
2981         /* Set buffer table mode */
2982         EFX_POPULATE_OWORD_1(temp, BUF_TBL_MODE, BUF_TBL_MODE_FULL);
2983         falcon_write(efx, &temp, BUF_TBL_CFG_REG_KER);
2984
2985         rc = falcon_reset_sram(efx);
2986         if (rc)
2987                 return rc;
2988
2989         /* Set positions of descriptor caches in SRAM. */
2990         EFX_POPULATE_OWORD_1(temp, SRM_TX_DC_BASE_ADR, TX_DC_BASE / 8);
2991         falcon_write(efx, &temp, SRM_TX_DC_CFG_REG_KER);
2992         EFX_POPULATE_OWORD_1(temp, SRM_RX_DC_BASE_ADR, RX_DC_BASE / 8);
2993         falcon_write(efx, &temp, SRM_RX_DC_CFG_REG_KER);
2994
2995         /* Set TX descriptor cache size. */
2996         BUILD_BUG_ON(TX_DC_ENTRIES != (16 << TX_DC_ENTRIES_ORDER));
2997         EFX_POPULATE_OWORD_1(temp, TX_DC_SIZE, TX_DC_ENTRIES_ORDER);
2998         falcon_write(efx, &temp, TX_DC_CFG_REG_KER);
2999
3000         /* Set RX descriptor cache size.  Set low watermark to size-8, as
3001          * this allows most efficient prefetching.
3002          */
3003         BUILD_BUG_ON(RX_DC_ENTRIES != (16 << RX_DC_ENTRIES_ORDER));
3004         EFX_POPULATE_OWORD_1(temp, RX_DC_SIZE, RX_DC_ENTRIES_ORDER);
3005         falcon_write(efx, &temp, RX_DC_CFG_REG_KER);
3006         EFX_POPULATE_OWORD_1(temp, RX_DC_PF_LWM, RX_DC_ENTRIES - 8);
3007         falcon_write(efx, &temp, RX_DC_PF_WM_REG_KER);
3008
3009         /* Clear the parity enables on the TX data fifos as
3010          * they produce false parity errors because of timing issues
3011          */
3012         if (EFX_WORKAROUND_5129(efx)) {
3013                 falcon_read(efx, &temp, SPARE_REG_KER);
3014                 EFX_SET_OWORD_FIELD(temp, MEM_PERR_EN_TX_DATA, 0);
3015                 falcon_write(efx, &temp, SPARE_REG_KER);
3016         }
3017
3018         /* Enable all the genuinely fatal interrupts.  (They are still
3019          * masked by the overall interrupt mask, controlled by
3020          * falcon_interrupts()).
3021          *
3022          * Note: All other fatal interrupts are enabled
3023          */
3024         EFX_POPULATE_OWORD_3(temp,
3025                              ILL_ADR_INT_KER_EN, 1,
3026                              RBUF_OWN_INT_KER_EN, 1,
3027                              TBUF_OWN_INT_KER_EN, 1);
3028         EFX_INVERT_OWORD(temp);
3029         falcon_write(efx, &temp, FATAL_INTR_REG_KER);
3030
3031         if (EFX_WORKAROUND_7244(efx)) {
3032                 falcon_read(efx, &temp, RX_FILTER_CTL_REG);
3033                 EFX_SET_OWORD_FIELD(temp, UDP_FULL_SRCH_LIMIT, 8);
3034                 EFX_SET_OWORD_FIELD(temp, UDP_WILD_SRCH_LIMIT, 8);
3035                 EFX_SET_OWORD_FIELD(temp, TCP_FULL_SRCH_LIMIT, 8);
3036                 EFX_SET_OWORD_FIELD(temp, TCP_WILD_SRCH_LIMIT, 8);
3037                 falcon_write(efx, &temp, RX_FILTER_CTL_REG);
3038         }
3039
3040         falcon_setup_rss_indir_table(efx);
3041
3042         /* Setup RX.  Wait for descriptor is broken and must
3043          * be disabled.  RXDP recovery shouldn't be needed, but is.
3044          */
3045         falcon_read(efx, &temp, RX_SELF_RST_REG_KER);
3046         EFX_SET_OWORD_FIELD(temp, RX_NODESC_WAIT_DIS, 1);
3047         EFX_SET_OWORD_FIELD(temp, RX_RECOVERY_EN, 1);
3048         if (EFX_WORKAROUND_5583(efx))
3049                 EFX_SET_OWORD_FIELD(temp, RX_ISCSI_DIS, 1);
3050         falcon_write(efx, &temp, RX_SELF_RST_REG_KER);
3051
3052         /* Disable the ugly timer-based TX DMA backoff and allow TX DMA to be
3053          * controlled by the RX FIFO fill level. Set arbitration to one pkt/Q.
3054          */
3055         falcon_read(efx, &temp, TX_CFG2_REG_KER);
3056         EFX_SET_OWORD_FIELD(temp, TX_RX_SPACER, 0xfe);
3057         EFX_SET_OWORD_FIELD(temp, TX_RX_SPACER_EN, 1);
3058         EFX_SET_OWORD_FIELD(temp, TX_ONE_PKT_PER_Q, 1);
3059         EFX_SET_OWORD_FIELD(temp, TX_CSR_PUSH_EN, 0);
3060         EFX_SET_OWORD_FIELD(temp, TX_DIS_NON_IP_EV, 1);
3061         /* Enable SW_EV to inherit in char driver - assume harmless here */
3062         EFX_SET_OWORD_FIELD(temp, TX_SW_EV_EN, 1);
3063         /* Prefetch threshold 2 => fetch when descriptor cache half empty */
3064         EFX_SET_OWORD_FIELD(temp, TX_PREF_THRESHOLD, 2);
3065         /* Squash TX of packets of 16 bytes or less */
3066         if (falcon_rev(efx) >= FALCON_REV_B0 && EFX_WORKAROUND_9141(efx))
3067                 EFX_SET_OWORD_FIELD(temp, TX_FLUSH_MIN_LEN_EN_B0, 1);
3068         falcon_write(efx, &temp, TX_CFG2_REG_KER);
3069
3070         /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
3071          * descriptors (which is bad).
3072          */
3073         falcon_read(efx, &temp, TX_CFG_REG_KER);
3074         EFX_SET_OWORD_FIELD(temp, TX_NO_EOP_DISC_EN, 0);
3075         falcon_write(efx, &temp, TX_CFG_REG_KER);
3076
3077         /* RX config */
3078         falcon_read(efx, &temp, RX_CFG_REG_KER);
3079         EFX_SET_OWORD_FIELD_VER(efx, temp, RX_DESC_PUSH_EN, 0);
3080         if (EFX_WORKAROUND_7575(efx))
3081                 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_USR_BUF_SIZE,
3082                                         (3 * 4096) / 32);
3083         if (falcon_rev(efx) >= FALCON_REV_B0)
3084                 EFX_SET_OWORD_FIELD(temp, RX_INGR_EN_B0, 1);
3085
3086         /* RX FIFO flow control thresholds */
3087         thresh = ((rx_xon_thresh_bytes >= 0) ?
3088                   rx_xon_thresh_bytes : efx->type->rx_xon_thresh);
3089         EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XON_MAC_TH, thresh / 256);
3090         thresh = ((rx_xoff_thresh_bytes >= 0) ?
3091                   rx_xoff_thresh_bytes : efx->type->rx_xoff_thresh);
3092         EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XOFF_MAC_TH, thresh / 256);
3093         /* RX control FIFO thresholds [32 entries] */
3094         EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XON_TX_TH, 20);
3095         EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XOFF_TX_TH, 25);
3096         falcon_write(efx, &temp, RX_CFG_REG_KER);
3097
3098         /* Set destination of both TX and RX Flush events */
3099         if (falcon_rev(efx) >= FALCON_REV_B0) {
3100                 EFX_POPULATE_OWORD_1(temp, FLS_EVQ_ID, 0);
3101                 falcon_write(efx, &temp, DP_CTRL_REG);
3102         }
3103
3104         return 0;
3105 }
3106
3107 void falcon_remove_nic(struct efx_nic *efx)
3108 {
3109         struct falcon_nic_data *nic_data = efx->nic_data;
3110         int rc;
3111
3112         rc = i2c_del_adapter(&efx->i2c_adap);
3113         BUG_ON(rc);
3114
3115         falcon_remove_spi_devices(efx);
3116         falcon_free_buffer(efx, &efx->irq_status);
3117
3118         falcon_reset_hw(efx, RESET_TYPE_ALL);
3119
3120         /* Release the second function after the reset */
3121         if (nic_data->pci_dev2) {
3122                 pci_dev_put(nic_data->pci_dev2);
3123                 nic_data->pci_dev2 = NULL;
3124         }
3125
3126         /* Tear down the private nic state */
3127         kfree(efx->nic_data);
3128         efx->nic_data = NULL;
3129 }
3130
3131 void falcon_update_nic_stats(struct efx_nic *efx)
3132 {
3133         efx_oword_t cnt;
3134
3135         falcon_read(efx, &cnt, RX_NODESC_DROP_REG_KER);
3136         efx->n_rx_nodesc_drop_cnt += EFX_OWORD_FIELD(cnt, RX_NODESC_DROP_CNT);
3137 }
3138
3139 /**************************************************************************
3140  *
3141  * Revision-dependent attributes used by efx.c
3142  *
3143  **************************************************************************
3144  */
3145
3146 struct efx_nic_type falcon_a_nic_type = {
3147         .mem_bar = 2,
3148         .mem_map_size = 0x20000,
3149         .txd_ptr_tbl_base = TX_DESC_PTR_TBL_KER_A1,
3150         .rxd_ptr_tbl_base = RX_DESC_PTR_TBL_KER_A1,
3151         .buf_tbl_base = BUF_TBL_KER_A1,
3152         .evq_ptr_tbl_base = EVQ_PTR_TBL_KER_A1,
3153         .evq_rptr_tbl_base = EVQ_RPTR_REG_KER_A1,
3154         .txd_ring_mask = FALCON_TXD_RING_MASK,
3155         .rxd_ring_mask = FALCON_RXD_RING_MASK,
3156         .evq_size = FALCON_EVQ_SIZE,
3157         .max_dma_mask = FALCON_DMA_MASK,
3158         .tx_dma_mask = FALCON_TX_DMA_MASK,
3159         .bug5391_mask = 0xf,
3160         .rx_xoff_thresh = 2048,
3161         .rx_xon_thresh = 512,
3162         .rx_buffer_padding = 0x24,
3163         .max_interrupt_mode = EFX_INT_MODE_MSI,
3164         .phys_addr_channels = 4,
3165 };
3166
3167 struct efx_nic_type falcon_b_nic_type = {
3168         .mem_bar = 2,
3169         /* Map everything up to and including the RSS indirection
3170          * table.  Don't map MSI-X table, MSI-X PBA since Linux
3171          * requires that they not be mapped.  */
3172         .mem_map_size = RX_RSS_INDIR_TBL_B0 + 0x800,
3173         .txd_ptr_tbl_base = TX_DESC_PTR_TBL_KER_B0,
3174         .rxd_ptr_tbl_base = RX_DESC_PTR_TBL_KER_B0,
3175         .buf_tbl_base = BUF_TBL_KER_B0,
3176         .evq_ptr_tbl_base = EVQ_PTR_TBL_KER_B0,
3177         .evq_rptr_tbl_base = EVQ_RPTR_REG_KER_B0,
3178         .txd_ring_mask = FALCON_TXD_RING_MASK,
3179         .rxd_ring_mask = FALCON_RXD_RING_MASK,
3180         .evq_size = FALCON_EVQ_SIZE,
3181         .max_dma_mask = FALCON_DMA_MASK,
3182         .tx_dma_mask = FALCON_TX_DMA_MASK,
3183         .bug5391_mask = 0,
3184         .rx_xoff_thresh = 54272, /* ~80Kb - 3*max MTU */
3185         .rx_xon_thresh = 27648,  /* ~3*max MTU */
3186         .rx_buffer_padding = 0,
3187         .max_interrupt_mode = EFX_INT_MODE_MSIX,
3188         .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy
3189                                    * interrupt handler only supports 32
3190                                    * channels */
3191 };
3192