1 /****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2005-2009 Solarflare Communications Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
11 /* Common definitions for all Efx net driver code */
13 #ifndef EFX_NET_DRIVER_H
14 #define EFX_NET_DRIVER_H
16 #include <linux/version.h>
17 #include <linux/netdevice.h>
18 #include <linux/etherdevice.h>
19 #include <linux/ethtool.h>
20 #include <linux/if_vlan.h>
21 #include <linux/timer.h>
22 #include <linux/mdio.h>
23 #include <linux/list.h>
24 #include <linux/pci.h>
25 #include <linux/device.h>
26 #include <linux/highmem.h>
27 #include <linux/workqueue.h>
28 #include <linux/i2c.h>
33 /**************************************************************************
37 **************************************************************************/
38 #ifndef EFX_DRIVER_NAME
39 #define EFX_DRIVER_NAME "sfc"
41 #define EFX_DRIVER_VERSION "3.0"
43 #ifdef EFX_ENABLE_DEBUG
44 #define EFX_BUG_ON_PARANOID(x) BUG_ON(x)
45 #define EFX_WARN_ON_PARANOID(x) WARN_ON(x)
47 #define EFX_BUG_ON_PARANOID(x) do {} while (0)
48 #define EFX_WARN_ON_PARANOID(x) do {} while (0)
51 /* Un-rate-limited logging */
52 #define EFX_ERR(efx, fmt, args...) \
53 dev_err(&((efx)->pci_dev->dev), "ERR: %s " fmt, efx_dev_name(efx), ##args)
55 #define EFX_INFO(efx, fmt, args...) \
56 dev_info(&((efx)->pci_dev->dev), "INFO: %s " fmt, efx_dev_name(efx), ##args)
58 #ifdef EFX_ENABLE_DEBUG
59 #define EFX_LOG(efx, fmt, args...) \
60 dev_info(&((efx)->pci_dev->dev), "DBG: %s " fmt, efx_dev_name(efx), ##args)
62 #define EFX_LOG(efx, fmt, args...) \
63 dev_dbg(&((efx)->pci_dev->dev), "DBG: %s " fmt, efx_dev_name(efx), ##args)
66 #define EFX_TRACE(efx, fmt, args...) do {} while (0)
68 #define EFX_REGDUMP(efx, fmt, args...) do {} while (0)
70 /* Rate-limited logging */
71 #define EFX_ERR_RL(efx, fmt, args...) \
72 do {if (net_ratelimit()) EFX_ERR(efx, fmt, ##args); } while (0)
74 #define EFX_INFO_RL(efx, fmt, args...) \
75 do {if (net_ratelimit()) EFX_INFO(efx, fmt, ##args); } while (0)
77 #define EFX_LOG_RL(efx, fmt, args...) \
78 do {if (net_ratelimit()) EFX_LOG(efx, fmt, ##args); } while (0)
80 /**************************************************************************
84 **************************************************************************/
86 #define EFX_MAX_CHANNELS 32
87 #define EFX_MAX_RX_QUEUES EFX_MAX_CHANNELS
89 /* Checksum generation is a per-queue option in hardware, so each
90 * queue visible to the networking core is backed by two hardware TX
92 #define EFX_MAX_CORE_TX_QUEUES EFX_MAX_CHANNELS
93 #define EFX_TXQ_TYPE_OFFLOAD 1
94 #define EFX_TXQ_TYPES 2
95 #define EFX_MAX_TX_QUEUES (EFX_TXQ_TYPES * EFX_MAX_CORE_TX_QUEUES)
98 * struct efx_special_buffer - An Efx special buffer
99 * @addr: CPU base address of the buffer
100 * @dma_addr: DMA base address of the buffer
101 * @len: Buffer length, in bytes
102 * @index: Buffer index within controller;s buffer table
103 * @entries: Number of buffer table entries
105 * Special buffers are used for the event queues and the TX and RX
106 * descriptor queues for each channel. They are *not* used for the
107 * actual transmit and receive buffers.
109 struct efx_special_buffer {
117 enum efx_flush_state {
125 * struct efx_tx_buffer - An Efx TX buffer
126 * @skb: The associated socket buffer.
127 * Set only on the final fragment of a packet; %NULL for all other
128 * fragments. When this fragment completes, then we can free this
130 * @tsoh: The associated TSO header structure, or %NULL if this
131 * buffer is not a TSO header.
132 * @dma_addr: DMA address of the fragment.
133 * @len: Length of this fragment.
134 * This field is zero when the queue slot is empty.
135 * @continuation: True if this fragment is not the end of a packet.
136 * @unmap_single: True if pci_unmap_single should be used.
137 * @unmap_len: Length of this fragment to unmap
139 struct efx_tx_buffer {
140 const struct sk_buff *skb;
141 struct efx_tso_header *tsoh;
146 unsigned short unmap_len;
150 * struct efx_tx_queue - An Efx TX queue
152 * This is a ring buffer of TX fragments.
153 * Since the TX completion path always executes on the same
154 * CPU and the xmit path can operate on different CPUs,
155 * performance is increased by ensuring that the completion
156 * path and the xmit path operate on different cache lines.
157 * This is particularly important if the xmit path is always
158 * executing on one CPU which is different from the completion
159 * path. There is also a cache line for members which are
160 * read but not written on the fast path.
162 * @efx: The associated Efx NIC
163 * @queue: DMA queue number
164 * @channel: The associated channel
165 * @buffer: The software buffer ring
166 * @txd: The hardware descriptor ring
167 * @flushed: Used when handling queue flushing
168 * @read_count: Current read pointer.
169 * This is the number of buffers that have been removed from both rings.
170 * @stopped: Stopped count.
171 * Set if this TX queue is currently stopping its port.
172 * @insert_count: Current insert pointer
173 * This is the number of buffers that have been added to the
175 * @write_count: Current write pointer
176 * This is the number of buffers that have been added to the
178 * @old_read_count: The value of read_count when last checked.
179 * This is here for performance reasons. The xmit path will
180 * only get the up-to-date value of read_count if this
181 * variable indicates that the queue is full. This is to
182 * avoid cache-line ping-pong between the xmit path and the
184 * @tso_headers_free: A list of TSO headers allocated for this TX queue
185 * that are not in use, and so available for new TSO sends. The list
186 * is protected by the TX queue lock.
187 * @tso_bursts: Number of times TSO xmit invoked by kernel
188 * @tso_long_headers: Number of packets with headers too long for standard
190 * @tso_packets: Number of packets via the TSO xmit path
192 struct efx_tx_queue {
193 /* Members which don't change on the fast path */
194 struct efx_nic *efx ____cacheline_aligned_in_smp;
196 struct efx_channel *channel;
198 struct efx_tx_buffer *buffer;
199 struct efx_special_buffer txd;
200 enum efx_flush_state flushed;
202 /* Members used mainly on the completion path */
203 unsigned int read_count ____cacheline_aligned_in_smp;
206 /* Members used only on the xmit path */
207 unsigned int insert_count ____cacheline_aligned_in_smp;
208 unsigned int write_count;
209 unsigned int old_read_count;
210 struct efx_tso_header *tso_headers_free;
211 unsigned int tso_bursts;
212 unsigned int tso_long_headers;
213 unsigned int tso_packets;
217 * struct efx_rx_buffer - An Efx RX data buffer
218 * @dma_addr: DMA base address of the buffer
219 * @skb: The associated socket buffer, if any.
220 * If both this and page are %NULL, the buffer slot is currently free.
221 * @page: The associated page buffer, if any.
222 * If both this and skb are %NULL, the buffer slot is currently free.
223 * @data: Pointer to ethernet header
224 * @len: Buffer length, in bytes.
225 * @unmap_addr: DMA address to unmap
227 struct efx_rx_buffer {
233 dma_addr_t unmap_addr;
237 * struct efx_rx_queue - An Efx RX queue
238 * @efx: The associated Efx NIC
239 * @queue: DMA queue number
240 * @channel: The associated channel
241 * @buffer: The software buffer ring
242 * @rxd: The hardware descriptor ring
243 * @added_count: Number of buffers added to the receive queue.
244 * @notified_count: Number of buffers given to NIC (<= @added_count).
245 * @removed_count: Number of buffers removed from the receive queue.
246 * @max_fill: RX descriptor maximum fill level (<= ring size)
247 * @fast_fill_trigger: RX descriptor fill level that will trigger a fast fill
249 * @fast_fill_limit: The level to which a fast fill will fill
250 * (@fast_fill_trigger <= @fast_fill_limit <= @max_fill)
251 * @min_fill: RX descriptor minimum non-zero fill level.
252 * This records the minimum fill level observed when a ring
253 * refill was triggered.
254 * @min_overfill: RX descriptor minimum overflow fill level.
255 * This records the minimum fill level at which RX queue
256 * overflow was observed. It should never be set.
257 * @alloc_page_count: RX allocation strategy counter.
258 * @alloc_skb_count: RX allocation strategy counter.
259 * @slow_fill: Timer used to defer efx_nic_generate_fill_event().
260 * @buf_page: Page for next RX buffer.
261 * We can use a single page for multiple RX buffers. This tracks
262 * the remaining space in the allocation.
263 * @buf_dma_addr: Page's DMA address.
264 * @buf_data: Page's host address.
265 * @flushed: Use when handling queue flushing
267 struct efx_rx_queue {
270 struct efx_channel *channel;
271 struct efx_rx_buffer *buffer;
272 struct efx_special_buffer rxd;
277 unsigned int max_fill;
278 unsigned int fast_fill_trigger;
279 unsigned int fast_fill_limit;
280 unsigned int min_fill;
281 unsigned int min_overfill;
282 unsigned int alloc_page_count;
283 unsigned int alloc_skb_count;
284 struct timer_list slow_fill;
285 unsigned int slow_fill_count;
287 struct page *buf_page;
288 dma_addr_t buf_dma_addr;
290 enum efx_flush_state flushed;
294 * struct efx_buffer - An Efx general-purpose buffer
295 * @addr: host base address of the buffer
296 * @dma_addr: DMA base address of the buffer
297 * @len: Buffer length, in bytes
299 * The NIC uses these buffers for its interrupt status registers and
309 enum efx_rx_alloc_method {
310 RX_ALLOC_METHOD_AUTO = 0,
311 RX_ALLOC_METHOD_SKB = 1,
312 RX_ALLOC_METHOD_PAGE = 2,
316 * struct efx_channel - An Efx channel
318 * A channel comprises an event queue, at least one TX queue, at least
319 * one RX queue, and an associated tasklet for processing the event
322 * @efx: Associated Efx NIC
323 * @channel: Channel instance number
324 * @name: Name for channel and IRQ
325 * @enabled: Channel enabled indicator
326 * @irq: IRQ number (MSI and MSI-X only)
327 * @irq_moderation: IRQ moderation value (in hardware ticks)
328 * @napi_dev: Net device used with NAPI
329 * @napi_str: NAPI control structure
330 * @reset_work: Scheduled reset work thread
331 * @work_pending: Is work pending via NAPI?
332 * @eventq: Event queue buffer
333 * @eventq_read_ptr: Event queue read pointer
334 * @last_eventq_read_ptr: Last event queue read pointer value.
335 * @magic_count: Event queue test event count
336 * @irq_count: Number of IRQs since last adaptive moderation decision
337 * @irq_mod_score: IRQ moderation score
338 * @rx_alloc_level: Watermark based heuristic counter for pushing descriptors
339 * and diagnostic counters
340 * @rx_alloc_push_pages: RX allocation method currently in use for pushing
342 * @n_rx_tobe_disc: Count of RX_TOBE_DISC errors
343 * @n_rx_ip_hdr_chksum_err: Count of RX IP header checksum errors
344 * @n_rx_tcp_udp_chksum_err: Count of RX TCP and UDP checksum errors
345 * @n_rx_mcast_mismatch: Count of unmatched multicast frames
346 * @n_rx_frm_trunc: Count of RX_FRM_TRUNC errors
347 * @n_rx_overlength: Count of RX_OVERLENGTH errors
348 * @n_skbuff_leaks: Count of skbuffs leaked due to RX overrun
349 * @tx_queue: Pointer to first TX queue, or %NULL if not used for TX
350 * @tx_stop_count: Core TX queue stop count
351 * @tx_stop_lock: Core TX queue stop lock
356 char name[IFNAMSIZ + 6];
359 unsigned int irq_moderation;
360 struct net_device *napi_dev;
361 struct napi_struct napi_str;
363 struct efx_special_buffer eventq;
364 unsigned int eventq_read_ptr;
365 unsigned int last_eventq_read_ptr;
366 unsigned int magic_count;
368 unsigned int irq_count;
369 unsigned int irq_mod_score;
372 int rx_alloc_push_pages;
374 unsigned n_rx_tobe_disc;
375 unsigned n_rx_ip_hdr_chksum_err;
376 unsigned n_rx_tcp_udp_chksum_err;
377 unsigned n_rx_mcast_mismatch;
378 unsigned n_rx_frm_trunc;
379 unsigned n_rx_overlength;
380 unsigned n_skbuff_leaks;
382 /* Used to pipeline received packets in order to optimise memory
383 * access with prefetches.
385 struct efx_rx_buffer *rx_pkt;
388 struct efx_tx_queue *tx_queue;
389 atomic_t tx_stop_count;
390 spinlock_t tx_stop_lock;
399 #define STRING_TABLE_LOOKUP(val, member) \
400 ((val) < member ## _max) ? member ## _names[val] : "(invalid)"
402 extern const char *efx_loopback_mode_names[];
403 extern const unsigned int efx_loopback_mode_max;
404 #define LOOPBACK_MODE(efx) \
405 STRING_TABLE_LOOKUP((efx)->loopback_mode, efx_loopback_mode)
407 extern const char *efx_interrupt_mode_names[];
408 extern const unsigned int efx_interrupt_mode_max;
409 #define INT_MODE(efx) \
410 STRING_TABLE_LOOKUP(efx->interrupt_mode, efx_interrupt_mode)
412 extern const char *efx_reset_type_names[];
413 extern const unsigned int efx_reset_type_max;
414 #define RESET_TYPE(type) \
415 STRING_TABLE_LOOKUP(type, efx_reset_type)
418 /* Be careful if altering to correct macro below */
419 EFX_INT_MODE_MSIX = 0,
420 EFX_INT_MODE_MSI = 1,
421 EFX_INT_MODE_LEGACY = 2,
422 EFX_INT_MODE_MAX /* Insert any new items before this */
424 #define EFX_INT_MODE_USE_MSI(x) (((x)->interrupt_mode) <= EFX_INT_MODE_MSI)
426 #define EFX_IS10G(efx) ((efx)->link_state.speed == 10000)
437 * Alignment of page-allocated RX buffers
439 * Controls the number of bytes inserted at the start of an RX buffer.
440 * This is the equivalent of NET_IP_ALIGN [which controls the alignment
441 * of the skb->head for hardware DMA].
443 #ifdef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
444 #define EFX_PAGE_IP_ALIGN 0
446 #define EFX_PAGE_IP_ALIGN NET_IP_ALIGN
450 * Alignment of the skb->head which wraps a page-allocated RX buffer
452 * The skb allocated to wrap an rx_buffer can have this alignment. Since
453 * the data is memcpy'd from the rx_buf, it does not need to be equal to
456 #define EFX_PAGE_SKB_ALIGN 2
458 /* Forward declaration */
461 /* Pseudo bit-mask flow control field */
463 EFX_FC_RX = FLOW_CTRL_RX,
464 EFX_FC_TX = FLOW_CTRL_TX,
469 * struct efx_link_state - Current state of the link
471 * @fd: Link is full-duplex
472 * @fc: Actual flow control flags
473 * @speed: Link speed (Mbps)
475 struct efx_link_state {
482 static inline bool efx_link_state_equal(const struct efx_link_state *left,
483 const struct efx_link_state *right)
485 return left->up == right->up && left->fd == right->fd &&
486 left->fc == right->fc && left->speed == right->speed;
490 * struct efx_mac_operations - Efx MAC operations table
491 * @reconfigure: Reconfigure MAC. Serialised by the mac_lock
492 * @update_stats: Update statistics
493 * @check_fault: Check fault state. True if fault present.
495 struct efx_mac_operations {
496 int (*reconfigure) (struct efx_nic *efx);
497 void (*update_stats) (struct efx_nic *efx);
498 bool (*check_fault)(struct efx_nic *efx);
502 * struct efx_phy_operations - Efx PHY operations table
503 * @probe: Probe PHY and initialise efx->mdio.mode_support, efx->mdio.mmds,
504 * efx->loopback_modes.
505 * @init: Initialise PHY
506 * @fini: Shut down PHY
507 * @reconfigure: Reconfigure PHY (e.g. for new link parameters)
508 * @poll: Update @link_state and report whether it changed.
509 * Serialised by the mac_lock.
510 * @get_settings: Get ethtool settings. Serialised by the mac_lock.
511 * @set_settings: Set ethtool settings. Serialised by the mac_lock.
512 * @set_npage_adv: Set abilities advertised in (Extended) Next Page
513 * (only needed where AN bit is set in mmds)
514 * @test_alive: Test that PHY is 'alive' (online)
515 * @test_name: Get the name of a PHY-specific test/result
516 * @run_tests: Run tests and record results as appropriate (offline).
517 * Flags are the ethtool tests flags.
519 struct efx_phy_operations {
520 int (*probe) (struct efx_nic *efx);
521 int (*init) (struct efx_nic *efx);
522 void (*fini) (struct efx_nic *efx);
523 void (*remove) (struct efx_nic *efx);
524 int (*reconfigure) (struct efx_nic *efx);
525 bool (*poll) (struct efx_nic *efx);
526 void (*get_settings) (struct efx_nic *efx,
527 struct ethtool_cmd *ecmd);
528 int (*set_settings) (struct efx_nic *efx,
529 struct ethtool_cmd *ecmd);
530 void (*set_npage_adv) (struct efx_nic *efx, u32);
531 int (*test_alive) (struct efx_nic *efx);
532 const char *(*test_name) (struct efx_nic *efx, unsigned int index);
533 int (*run_tests) (struct efx_nic *efx, int *results, unsigned flags);
537 * @enum efx_phy_mode - PHY operating mode flags
538 * @PHY_MODE_NORMAL: on and should pass traffic
539 * @PHY_MODE_TX_DISABLED: on with TX disabled
540 * @PHY_MODE_LOW_POWER: set to low power through MDIO
541 * @PHY_MODE_OFF: switched off through external control
542 * @PHY_MODE_SPECIAL: on but will not pass traffic
546 PHY_MODE_TX_DISABLED = 1,
547 PHY_MODE_LOW_POWER = 2,
549 PHY_MODE_SPECIAL = 8,
552 static inline bool efx_phy_mode_disabled(enum efx_phy_mode mode)
554 return !!(mode & ~PHY_MODE_TX_DISABLED);
558 * Efx extended statistics
560 * Not all statistics are provided by all supported MACs. The purpose
561 * is this structure is to contain the raw statistics provided by each
564 struct efx_mac_stats {
568 unsigned long tx_packets;
569 unsigned long tx_bad;
570 unsigned long tx_pause;
571 unsigned long tx_control;
572 unsigned long tx_unicast;
573 unsigned long tx_multicast;
574 unsigned long tx_broadcast;
575 unsigned long tx_lt64;
577 unsigned long tx_65_to_127;
578 unsigned long tx_128_to_255;
579 unsigned long tx_256_to_511;
580 unsigned long tx_512_to_1023;
581 unsigned long tx_1024_to_15xx;
582 unsigned long tx_15xx_to_jumbo;
583 unsigned long tx_gtjumbo;
584 unsigned long tx_collision;
585 unsigned long tx_single_collision;
586 unsigned long tx_multiple_collision;
587 unsigned long tx_excessive_collision;
588 unsigned long tx_deferred;
589 unsigned long tx_late_collision;
590 unsigned long tx_excessive_deferred;
591 unsigned long tx_non_tcpudp;
592 unsigned long tx_mac_src_error;
593 unsigned long tx_ip_src_error;
597 unsigned long rx_packets;
598 unsigned long rx_good;
599 unsigned long rx_bad;
600 unsigned long rx_pause;
601 unsigned long rx_control;
602 unsigned long rx_unicast;
603 unsigned long rx_multicast;
604 unsigned long rx_broadcast;
605 unsigned long rx_lt64;
607 unsigned long rx_65_to_127;
608 unsigned long rx_128_to_255;
609 unsigned long rx_256_to_511;
610 unsigned long rx_512_to_1023;
611 unsigned long rx_1024_to_15xx;
612 unsigned long rx_15xx_to_jumbo;
613 unsigned long rx_gtjumbo;
614 unsigned long rx_bad_lt64;
615 unsigned long rx_bad_64_to_15xx;
616 unsigned long rx_bad_15xx_to_jumbo;
617 unsigned long rx_bad_gtjumbo;
618 unsigned long rx_overflow;
619 unsigned long rx_missed;
620 unsigned long rx_false_carrier;
621 unsigned long rx_symbol_error;
622 unsigned long rx_align_error;
623 unsigned long rx_length_error;
624 unsigned long rx_internal_error;
625 unsigned long rx_good_lt64;
628 /* Number of bits used in a multicast filter hash address */
629 #define EFX_MCAST_HASH_BITS 8
631 /* Number of (single-bit) entries in a multicast filter hash */
632 #define EFX_MCAST_HASH_ENTRIES (1 << EFX_MCAST_HASH_BITS)
634 /* An Efx multicast filter hash */
635 union efx_multicast_hash {
636 u8 byte[EFX_MCAST_HASH_ENTRIES / 8];
637 efx_oword_t oword[EFX_MCAST_HASH_ENTRIES / sizeof(efx_oword_t) / 8];
641 * struct efx_nic - an Efx NIC
642 * @name: Device name (net device name or bus id before net device registered)
643 * @pci_dev: The PCI device
644 * @type: Controller type attributes
645 * @legacy_irq: IRQ number
646 * @workqueue: Workqueue for port reconfigures and the HW monitor.
647 * Work items do not hold and must not acquire RTNL.
648 * @workqueue_name: Name of workqueue
649 * @reset_work: Scheduled reset workitem
650 * @monitor_work: Hardware monitor workitem
651 * @membase_phys: Memory BAR value as physical address
652 * @membase: Memory BAR value
653 * @biu_lock: BIU (bus interface unit) lock
654 * @interrupt_mode: Interrupt mode
655 * @irq_rx_adaptive: Adaptive IRQ moderation enabled for RX event queues
656 * @irq_rx_moderation: IRQ moderation time for RX event queues
657 * @state: Device state flag. Serialised by the rtnl_lock.
658 * @reset_pending: Pending reset method (normally RESET_TYPE_NONE)
659 * @tx_queue: TX DMA queues
660 * @rx_queue: RX DMA queues
662 * @next_buffer_table: First available buffer table id
663 * @n_channels: Number of channels in use
664 * @n_rx_channels: Number of channels used for RX (= number of RX queues)
665 * @n_tx_channels: Number of channels used for TX
666 * @rx_buffer_len: RX buffer length
667 * @rx_buffer_order: Order (log2) of number of pages for each RX buffer
668 * @int_error_count: Number of internal errors seen recently
669 * @int_error_expire: Time at which error count will be expired
670 * @irq_status: Interrupt status buffer
671 * @last_irq_cpu: Last CPU to handle interrupt.
672 * This register is written with the SMP processor ID whenever an
673 * interrupt is handled. It is used by efx_nic_test_interrupt()
674 * to verify that an interrupt has occurred.
675 * @irq_zero_count: Number of legacy IRQs seen with queue flags == 0
676 * @fatal_irq_level: IRQ level (bit number) used for serious errors
677 * @spi_flash: SPI flash device
678 * This field will be %NULL if no flash device is present (or for Siena).
679 * @spi_eeprom: SPI EEPROM device
680 * This field will be %NULL if no EEPROM device is present (or for Siena).
681 * @spi_lock: SPI bus lock
682 * @mtd_list: List of MTDs attached to the NIC
683 * @n_rx_nodesc_drop_cnt: RX no descriptor drop count
684 * @nic_data: Hardware dependant state
685 * @mac_lock: MAC access lock. Protects @port_enabled, @phy_mode,
686 * @port_inhibited, efx_monitor() and efx_reconfigure_port()
687 * @port_enabled: Port enabled indicator.
688 * Serialises efx_stop_all(), efx_start_all(), efx_monitor() and
689 * efx_mac_work() with kernel interfaces. Safe to read under any
690 * one of the rtnl_lock, mac_lock, or netif_tx_lock, but all three must
691 * be held to modify it.
692 * @port_inhibited: If set, the netif_carrier is always off. Hold the mac_lock
693 * @port_initialized: Port initialized?
694 * @net_dev: Operating system network device. Consider holding the rtnl lock
695 * @rx_checksum_enabled: RX checksumming enabled
696 * @mac_stats: MAC statistics. These include all statistics the MACs
697 * can provide. Generic code converts these into a standard
698 * &struct net_device_stats.
699 * @stats_buffer: DMA buffer for statistics
700 * @stats_lock: Statistics update lock. Serialises statistics fetches
701 * @mac_op: MAC interface
702 * @mac_address: Permanent MAC address
703 * @phy_type: PHY type
704 * @mdio_lock: MDIO lock
705 * @phy_op: PHY interface
706 * @phy_data: PHY private data (including PHY-specific stats)
707 * @mdio: PHY MDIO interface
708 * @mdio_bus: PHY MDIO bus ID (only used by Siena)
709 * @phy_mode: PHY operating mode. Serialised by @mac_lock.
710 * @xmac_poll_required: XMAC link state needs polling
711 * @link_advertising: Autonegotiation advertising flags
712 * @link_state: Current state of the link
713 * @n_link_state_changes: Number of times the link has changed state
714 * @promiscuous: Promiscuous flag. Protected by netif_tx_lock.
715 * @multicast_hash: Multicast hash table
716 * @wanted_fc: Wanted flow control flags
717 * @mac_work: Work item for changing MAC promiscuity and multicast hash
718 * @loopback_mode: Loopback status
719 * @loopback_modes: Supported loopback mode bitmask
720 * @loopback_selftest: Offline self-test private state
722 * This is stored in the private area of the &struct net_device.
726 struct pci_dev *pci_dev;
727 const struct efx_nic_type *type;
729 struct workqueue_struct *workqueue;
730 char workqueue_name[16];
731 struct work_struct reset_work;
732 struct delayed_work monitor_work;
733 resource_size_t membase_phys;
734 void __iomem *membase;
736 enum efx_int_mode interrupt_mode;
737 bool irq_rx_adaptive;
738 unsigned int irq_rx_moderation;
740 enum nic_state state;
741 enum reset_type reset_pending;
743 struct efx_tx_queue tx_queue[EFX_MAX_TX_QUEUES];
744 struct efx_rx_queue rx_queue[EFX_MAX_RX_QUEUES];
745 struct efx_channel channel[EFX_MAX_CHANNELS];
747 unsigned next_buffer_table;
749 unsigned n_rx_channels;
750 unsigned n_tx_channels;
751 unsigned int rx_buffer_len;
752 unsigned int rx_buffer_order;
754 unsigned int_error_count;
755 unsigned long int_error_expire;
757 struct efx_buffer irq_status;
758 volatile signed int last_irq_cpu;
759 unsigned irq_zero_count;
760 unsigned fatal_irq_level;
762 struct efx_spi_device *spi_flash;
763 struct efx_spi_device *spi_eeprom;
764 struct mutex spi_lock;
765 #ifdef CONFIG_SFC_MTD
766 struct list_head mtd_list;
769 unsigned n_rx_nodesc_drop_cnt;
773 struct mutex mac_lock;
774 struct work_struct mac_work;
778 bool port_initialized;
779 struct net_device *net_dev;
780 bool rx_checksum_enabled;
782 struct efx_mac_stats mac_stats;
783 struct efx_buffer stats_buffer;
784 spinlock_t stats_lock;
786 struct efx_mac_operations *mac_op;
787 unsigned char mac_address[ETH_ALEN];
789 unsigned int phy_type;
790 struct mutex mdio_lock;
791 struct efx_phy_operations *phy_op;
793 struct mdio_if_info mdio;
794 unsigned int mdio_bus;
795 enum efx_phy_mode phy_mode;
797 bool xmac_poll_required;
798 u32 link_advertising;
799 struct efx_link_state link_state;
800 unsigned int n_link_state_changes;
803 union efx_multicast_hash multicast_hash;
804 enum efx_fc_type wanted_fc;
807 enum efx_loopback_mode loopback_mode;
810 void *loopback_selftest;
813 static inline int efx_dev_registered(struct efx_nic *efx)
815 return efx->net_dev->reg_state == NETREG_REGISTERED;
818 /* Net device name, for inclusion in log messages if it has been registered.
819 * Use efx->name not efx->net_dev->name so that races with (un)registration
822 static inline const char *efx_dev_name(struct efx_nic *efx)
824 return efx_dev_registered(efx) ? efx->name : "";
827 static inline unsigned int efx_port_num(struct efx_nic *efx)
829 return PCI_FUNC(efx->pci_dev->devfn);
833 * struct efx_nic_type - Efx device type definition
834 * @probe: Probe the controller
835 * @remove: Free resources allocated by probe()
836 * @init: Initialise the controller
837 * @fini: Shut down the controller
838 * @monitor: Periodic function for polling link state and hardware monitor
839 * @reset: Reset the controller hardware and possibly the PHY. This will
840 * be called while the controller is uninitialised.
841 * @probe_port: Probe the MAC and PHY
842 * @remove_port: Free resources allocated by probe_port()
843 * @prepare_flush: Prepare the hardware for flushing the DMA queues
844 * @update_stats: Update statistics not provided by event handling
845 * @start_stats: Start the regular fetching of statistics
846 * @stop_stats: Stop the regular fetching of statistics
847 * @set_id_led: Set state of identifying LED or revert to automatic function
848 * @push_irq_moderation: Apply interrupt moderation value
849 * @push_multicast_hash: Apply multicast hash table
850 * @reconfigure_port: Push loopback/power/txdis changes to the MAC and PHY
851 * @get_wol: Get WoL configuration from driver state
852 * @set_wol: Push WoL configuration to the NIC
853 * @resume_wol: Synchronise WoL state between driver and MC (e.g. after resume)
854 * @test_registers: Test read/write functionality of control registers
855 * @test_nvram: Test validity of NVRAM contents
856 * @default_mac_ops: efx_mac_operations to set at startup
857 * @revision: Hardware architecture revision
858 * @mem_map_size: Memory BAR mapped size
859 * @txd_ptr_tbl_base: TX descriptor ring base address
860 * @rxd_ptr_tbl_base: RX descriptor ring base address
861 * @buf_tbl_base: Buffer table base address
862 * @evq_ptr_tbl_base: Event queue pointer table base address
863 * @evq_rptr_tbl_base: Event queue read-pointer table base address
864 * @max_dma_mask: Maximum possible DMA mask
865 * @rx_buffer_padding: Padding added to each RX buffer
866 * @max_interrupt_mode: Highest capability interrupt mode supported
867 * from &enum efx_init_mode.
868 * @phys_addr_channels: Number of channels with physically addressed
870 * @tx_dc_base: Base address in SRAM of TX queue descriptor caches
871 * @rx_dc_base: Base address in SRAM of RX queue descriptor caches
872 * @offload_features: net_device feature flags for protocol offload
873 * features implemented in hardware
874 * @reset_world_flags: Flags for additional components covered by
875 * reset method RESET_TYPE_WORLD
877 struct efx_nic_type {
878 int (*probe)(struct efx_nic *efx);
879 void (*remove)(struct efx_nic *efx);
880 int (*init)(struct efx_nic *efx);
881 void (*fini)(struct efx_nic *efx);
882 void (*monitor)(struct efx_nic *efx);
883 int (*reset)(struct efx_nic *efx, enum reset_type method);
884 int (*probe_port)(struct efx_nic *efx);
885 void (*remove_port)(struct efx_nic *efx);
886 void (*prepare_flush)(struct efx_nic *efx);
887 void (*update_stats)(struct efx_nic *efx);
888 void (*start_stats)(struct efx_nic *efx);
889 void (*stop_stats)(struct efx_nic *efx);
890 void (*set_id_led)(struct efx_nic *efx, enum efx_led_mode mode);
891 void (*push_irq_moderation)(struct efx_channel *channel);
892 void (*push_multicast_hash)(struct efx_nic *efx);
893 int (*reconfigure_port)(struct efx_nic *efx);
894 void (*get_wol)(struct efx_nic *efx, struct ethtool_wolinfo *wol);
895 int (*set_wol)(struct efx_nic *efx, u32 type);
896 void (*resume_wol)(struct efx_nic *efx);
897 int (*test_registers)(struct efx_nic *efx);
898 int (*test_nvram)(struct efx_nic *efx);
899 struct efx_mac_operations *default_mac_ops;
902 unsigned int mem_map_size;
903 unsigned int txd_ptr_tbl_base;
904 unsigned int rxd_ptr_tbl_base;
905 unsigned int buf_tbl_base;
906 unsigned int evq_ptr_tbl_base;
907 unsigned int evq_rptr_tbl_base;
909 unsigned int rx_buffer_padding;
910 unsigned int max_interrupt_mode;
911 unsigned int phys_addr_channels;
912 unsigned int tx_dc_base;
913 unsigned int rx_dc_base;
914 unsigned long offload_features;
915 u32 reset_world_flags;
918 /**************************************************************************
920 * Prototypes and inline functions
922 *************************************************************************/
924 /* Iterate over all used channels */
925 #define efx_for_each_channel(_channel, _efx) \
926 for (_channel = &((_efx)->channel[0]); \
927 _channel < &((_efx)->channel[(efx)->n_channels]); \
930 /* Iterate over all used TX queues */
931 #define efx_for_each_tx_queue(_tx_queue, _efx) \
932 for (_tx_queue = &((_efx)->tx_queue[0]); \
933 _tx_queue < &((_efx)->tx_queue[EFX_TXQ_TYPES * \
934 (_efx)->n_tx_channels]); \
937 /* Iterate over all TX queues belonging to a channel */
938 #define efx_for_each_channel_tx_queue(_tx_queue, _channel) \
939 for (_tx_queue = (_channel)->tx_queue; \
940 _tx_queue && _tx_queue < (_channel)->tx_queue + EFX_TXQ_TYPES; \
943 /* Iterate over all used RX queues */
944 #define efx_for_each_rx_queue(_rx_queue, _efx) \
945 for (_rx_queue = &((_efx)->rx_queue[0]); \
946 _rx_queue < &((_efx)->rx_queue[(_efx)->n_rx_channels]); \
949 /* Iterate over all RX queues belonging to a channel */
950 #define efx_for_each_channel_rx_queue(_rx_queue, _channel) \
951 for (_rx_queue = &((_channel)->efx->rx_queue[(_channel)->channel]); \
954 if (_rx_queue->channel != (_channel)) \
958 /* Returns a pointer to the specified receive buffer in the RX
961 static inline struct efx_rx_buffer *efx_rx_buffer(struct efx_rx_queue *rx_queue,
964 return (&rx_queue->buffer[index]);
967 /* Set bit in a little-endian bitfield */
968 static inline void set_bit_le(unsigned nr, unsigned char *addr)
970 addr[nr / 8] |= (1 << (nr % 8));
973 /* Clear bit in a little-endian bitfield */
974 static inline void clear_bit_le(unsigned nr, unsigned char *addr)
976 addr[nr / 8] &= ~(1 << (nr % 8));
981 * EFX_MAX_FRAME_LEN - calculate maximum frame length
983 * This calculates the maximum frame length that will be used for a
984 * given MTU. The frame length will be equal to the MTU plus a
985 * constant amount of header space and padding. This is the quantity
986 * that the net driver will program into the MAC as the maximum frame
989 * The 10G MAC requires 8-byte alignment on the frame
990 * length, so we round up to the nearest 8.
992 * Re-clocking by the XGXS on RX can reduce an IPG to 32 bits (half an
993 * XGMII cycle). If the frame length reaches the maximum value in the
994 * same cycle, the XMAC can miss the IPG altogether. We work around
995 * this by adding a further 16 bytes.
997 #define EFX_MAX_FRAME_LEN(mtu) \
998 ((((mtu) + ETH_HLEN + VLAN_HLEN + 4/* FCS */ + 7) & ~7) + 16)
1001 #endif /* EFX_NET_DRIVER_H */