2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
10 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/moduleparam.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/ethtool.h>
34 #include <linux/pci.h>
35 #include <linux/if_vlan.h>
37 #include <linux/delay.h>
38 #include <linux/crc32.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/mii.h>
45 #define DRV_NAME "skge"
46 #define DRV_VERSION "1.8"
47 #define PFX DRV_NAME " "
49 #define DEFAULT_TX_RING_SIZE 128
50 #define DEFAULT_RX_RING_SIZE 512
51 #define MAX_TX_RING_SIZE 1024
52 #define TX_LOW_WATER (MAX_SKB_FRAGS + 1)
53 #define MAX_RX_RING_SIZE 4096
54 #define RX_COPY_THRESHOLD 128
55 #define RX_BUF_SIZE 1536
56 #define PHY_RETRIES 1000
57 #define ETH_JUMBO_MTU 9000
58 #define TX_WATCHDOG (5 * HZ)
59 #define NAPI_WEIGHT 64
61 #define LINK_HZ (HZ/2)
63 MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
64 MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
65 MODULE_LICENSE("GPL");
66 MODULE_VERSION(DRV_VERSION);
68 static const u32 default_msg
69 = NETIF_MSG_DRV| NETIF_MSG_PROBE| NETIF_MSG_LINK
70 | NETIF_MSG_IFUP| NETIF_MSG_IFDOWN;
72 static int debug = -1; /* defaults above */
73 module_param(debug, int, 0);
74 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
76 static const struct pci_device_id skge_id_table[] = {
77 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },
78 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },
79 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },
80 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },
81 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T), },
82 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) }, /* DGE-530T */
83 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },
84 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
85 { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },
86 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },
87 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015, },
90 MODULE_DEVICE_TABLE(pci, skge_id_table);
92 static int skge_up(struct net_device *dev);
93 static int skge_down(struct net_device *dev);
94 static void skge_phy_reset(struct skge_port *skge);
95 static void skge_tx_clean(struct net_device *dev);
96 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
97 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
98 static void genesis_get_stats(struct skge_port *skge, u64 *data);
99 static void yukon_get_stats(struct skge_port *skge, u64 *data);
100 static void yukon_init(struct skge_hw *hw, int port);
101 static void genesis_mac_init(struct skge_hw *hw, int port);
102 static void genesis_link_up(struct skge_port *skge);
104 /* Avoid conditionals by using array */
105 static const int txqaddr[] = { Q_XA1, Q_XA2 };
106 static const int rxqaddr[] = { Q_R1, Q_R2 };
107 static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
108 static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
109 static const u32 irqmask[] = { IS_R1_F|IS_XA1_F, IS_R2_F|IS_XA2_F };
111 static int skge_get_regs_len(struct net_device *dev)
117 * Returns copy of whole control register region
118 * Note: skip RAM address register because accessing it will
121 static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
124 const struct skge_port *skge = netdev_priv(dev);
125 const void __iomem *io = skge->hw->regs;
128 memset(p, 0, regs->len);
129 memcpy_fromio(p, io, B3_RAM_ADDR);
131 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,
132 regs->len - B3_RI_WTO_R1);
135 /* Wake on Lan only supported on Yukon chips with rev 1 or above */
136 static int wol_supported(const struct skge_hw *hw)
138 return !((hw->chip_id == CHIP_ID_GENESIS ||
139 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)));
142 static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
144 struct skge_port *skge = netdev_priv(dev);
146 wol->supported = wol_supported(skge->hw) ? WAKE_MAGIC : 0;
147 wol->wolopts = skge->wol ? WAKE_MAGIC : 0;
150 static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
152 struct skge_port *skge = netdev_priv(dev);
153 struct skge_hw *hw = skge->hw;
155 if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
158 if (wol->wolopts == WAKE_MAGIC && !wol_supported(hw))
161 skge->wol = wol->wolopts == WAKE_MAGIC;
164 memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
166 skge_write16(hw, WOL_CTRL_STAT,
167 WOL_CTL_ENA_PME_ON_MAGIC_PKT |
168 WOL_CTL_ENA_MAGIC_PKT_UNIT);
170 skge_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
175 /* Determine supported/advertised modes based on hardware.
176 * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
178 static u32 skge_supported_modes(const struct skge_hw *hw)
183 supported = SUPPORTED_10baseT_Half
184 | SUPPORTED_10baseT_Full
185 | SUPPORTED_100baseT_Half
186 | SUPPORTED_100baseT_Full
187 | SUPPORTED_1000baseT_Half
188 | SUPPORTED_1000baseT_Full
189 | SUPPORTED_Autoneg| SUPPORTED_TP;
191 if (hw->chip_id == CHIP_ID_GENESIS)
192 supported &= ~(SUPPORTED_10baseT_Half
193 | SUPPORTED_10baseT_Full
194 | SUPPORTED_100baseT_Half
195 | SUPPORTED_100baseT_Full);
197 else if (hw->chip_id == CHIP_ID_YUKON)
198 supported &= ~SUPPORTED_1000baseT_Half;
200 supported = SUPPORTED_1000baseT_Full | SUPPORTED_1000baseT_Half
201 | SUPPORTED_FIBRE | SUPPORTED_Autoneg;
206 static int skge_get_settings(struct net_device *dev,
207 struct ethtool_cmd *ecmd)
209 struct skge_port *skge = netdev_priv(dev);
210 struct skge_hw *hw = skge->hw;
212 ecmd->transceiver = XCVR_INTERNAL;
213 ecmd->supported = skge_supported_modes(hw);
216 ecmd->port = PORT_TP;
217 ecmd->phy_address = hw->phy_addr;
219 ecmd->port = PORT_FIBRE;
221 ecmd->advertising = skge->advertising;
222 ecmd->autoneg = skge->autoneg;
223 ecmd->speed = skge->speed;
224 ecmd->duplex = skge->duplex;
228 static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
230 struct skge_port *skge = netdev_priv(dev);
231 const struct skge_hw *hw = skge->hw;
232 u32 supported = skge_supported_modes(hw);
234 if (ecmd->autoneg == AUTONEG_ENABLE) {
235 ecmd->advertising = supported;
241 switch (ecmd->speed) {
243 if (ecmd->duplex == DUPLEX_FULL)
244 setting = SUPPORTED_1000baseT_Full;
245 else if (ecmd->duplex == DUPLEX_HALF)
246 setting = SUPPORTED_1000baseT_Half;
251 if (ecmd->duplex == DUPLEX_FULL)
252 setting = SUPPORTED_100baseT_Full;
253 else if (ecmd->duplex == DUPLEX_HALF)
254 setting = SUPPORTED_100baseT_Half;
260 if (ecmd->duplex == DUPLEX_FULL)
261 setting = SUPPORTED_10baseT_Full;
262 else if (ecmd->duplex == DUPLEX_HALF)
263 setting = SUPPORTED_10baseT_Half;
271 if ((setting & supported) == 0)
274 skge->speed = ecmd->speed;
275 skge->duplex = ecmd->duplex;
278 skge->autoneg = ecmd->autoneg;
279 skge->advertising = ecmd->advertising;
281 if (netif_running(dev))
282 skge_phy_reset(skge);
287 static void skge_get_drvinfo(struct net_device *dev,
288 struct ethtool_drvinfo *info)
290 struct skge_port *skge = netdev_priv(dev);
292 strcpy(info->driver, DRV_NAME);
293 strcpy(info->version, DRV_VERSION);
294 strcpy(info->fw_version, "N/A");
295 strcpy(info->bus_info, pci_name(skge->hw->pdev));
298 static const struct skge_stat {
299 char name[ETH_GSTRING_LEN];
303 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
304 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
306 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
307 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
308 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
309 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
310 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
311 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
312 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
313 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
315 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
316 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
317 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
318 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
319 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
320 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
322 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
323 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
324 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
325 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
326 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
329 static int skge_get_stats_count(struct net_device *dev)
331 return ARRAY_SIZE(skge_stats);
334 static void skge_get_ethtool_stats(struct net_device *dev,
335 struct ethtool_stats *stats, u64 *data)
337 struct skge_port *skge = netdev_priv(dev);
339 if (skge->hw->chip_id == CHIP_ID_GENESIS)
340 genesis_get_stats(skge, data);
342 yukon_get_stats(skge, data);
345 /* Use hardware MIB variables for critical path statistics and
346 * transmit feedback not reported at interrupt.
347 * Other errors are accounted for in interrupt handler.
349 static struct net_device_stats *skge_get_stats(struct net_device *dev)
351 struct skge_port *skge = netdev_priv(dev);
352 u64 data[ARRAY_SIZE(skge_stats)];
354 if (skge->hw->chip_id == CHIP_ID_GENESIS)
355 genesis_get_stats(skge, data);
357 yukon_get_stats(skge, data);
359 skge->net_stats.tx_bytes = data[0];
360 skge->net_stats.rx_bytes = data[1];
361 skge->net_stats.tx_packets = data[2] + data[4] + data[6];
362 skge->net_stats.rx_packets = data[3] + data[5] + data[7];
363 skge->net_stats.multicast = data[3] + data[5];
364 skge->net_stats.collisions = data[10];
365 skge->net_stats.tx_aborted_errors = data[12];
367 return &skge->net_stats;
370 static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
376 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
377 memcpy(data + i * ETH_GSTRING_LEN,
378 skge_stats[i].name, ETH_GSTRING_LEN);
383 static void skge_get_ring_param(struct net_device *dev,
384 struct ethtool_ringparam *p)
386 struct skge_port *skge = netdev_priv(dev);
388 p->rx_max_pending = MAX_RX_RING_SIZE;
389 p->tx_max_pending = MAX_TX_RING_SIZE;
390 p->rx_mini_max_pending = 0;
391 p->rx_jumbo_max_pending = 0;
393 p->rx_pending = skge->rx_ring.count;
394 p->tx_pending = skge->tx_ring.count;
395 p->rx_mini_pending = 0;
396 p->rx_jumbo_pending = 0;
399 static int skge_set_ring_param(struct net_device *dev,
400 struct ethtool_ringparam *p)
402 struct skge_port *skge = netdev_priv(dev);
405 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
406 p->tx_pending < TX_LOW_WATER || p->tx_pending > MAX_TX_RING_SIZE)
409 skge->rx_ring.count = p->rx_pending;
410 skge->tx_ring.count = p->tx_pending;
412 if (netif_running(dev)) {
422 static u32 skge_get_msglevel(struct net_device *netdev)
424 struct skge_port *skge = netdev_priv(netdev);
425 return skge->msg_enable;
428 static void skge_set_msglevel(struct net_device *netdev, u32 value)
430 struct skge_port *skge = netdev_priv(netdev);
431 skge->msg_enable = value;
434 static int skge_nway_reset(struct net_device *dev)
436 struct skge_port *skge = netdev_priv(dev);
438 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
441 skge_phy_reset(skge);
445 static int skge_set_sg(struct net_device *dev, u32 data)
447 struct skge_port *skge = netdev_priv(dev);
448 struct skge_hw *hw = skge->hw;
450 if (hw->chip_id == CHIP_ID_GENESIS && data)
452 return ethtool_op_set_sg(dev, data);
455 static int skge_set_tx_csum(struct net_device *dev, u32 data)
457 struct skge_port *skge = netdev_priv(dev);
458 struct skge_hw *hw = skge->hw;
460 if (hw->chip_id == CHIP_ID_GENESIS && data)
463 return ethtool_op_set_tx_csum(dev, data);
466 static u32 skge_get_rx_csum(struct net_device *dev)
468 struct skge_port *skge = netdev_priv(dev);
470 return skge->rx_csum;
473 /* Only Yukon supports checksum offload. */
474 static int skge_set_rx_csum(struct net_device *dev, u32 data)
476 struct skge_port *skge = netdev_priv(dev);
478 if (skge->hw->chip_id == CHIP_ID_GENESIS && data)
481 skge->rx_csum = data;
485 static void skge_get_pauseparam(struct net_device *dev,
486 struct ethtool_pauseparam *ecmd)
488 struct skge_port *skge = netdev_priv(dev);
490 ecmd->tx_pause = (skge->flow_control == FLOW_MODE_LOC_SEND)
491 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
492 ecmd->rx_pause = (skge->flow_control == FLOW_MODE_REM_SEND)
493 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
495 ecmd->autoneg = skge->autoneg;
498 static int skge_set_pauseparam(struct net_device *dev,
499 struct ethtool_pauseparam *ecmd)
501 struct skge_port *skge = netdev_priv(dev);
503 skge->autoneg = ecmd->autoneg;
504 if (ecmd->rx_pause && ecmd->tx_pause)
505 skge->flow_control = FLOW_MODE_SYMMETRIC;
506 else if (ecmd->rx_pause && !ecmd->tx_pause)
507 skge->flow_control = FLOW_MODE_REM_SEND;
508 else if (!ecmd->rx_pause && ecmd->tx_pause)
509 skge->flow_control = FLOW_MODE_LOC_SEND;
511 skge->flow_control = FLOW_MODE_NONE;
513 if (netif_running(dev))
514 skge_phy_reset(skge);
518 /* Chip internal frequency for clock calculations */
519 static inline u32 hwkhz(const struct skge_hw *hw)
521 return (hw->chip_id == CHIP_ID_GENESIS) ? 53125 : 78125;
524 /* Chip HZ to microseconds */
525 static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
527 return (ticks * 1000) / hwkhz(hw);
530 /* Microseconds to chip HZ */
531 static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
533 return hwkhz(hw) * usec / 1000;
536 static int skge_get_coalesce(struct net_device *dev,
537 struct ethtool_coalesce *ecmd)
539 struct skge_port *skge = netdev_priv(dev);
540 struct skge_hw *hw = skge->hw;
541 int port = skge->port;
543 ecmd->rx_coalesce_usecs = 0;
544 ecmd->tx_coalesce_usecs = 0;
546 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
547 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
548 u32 msk = skge_read32(hw, B2_IRQM_MSK);
550 if (msk & rxirqmask[port])
551 ecmd->rx_coalesce_usecs = delay;
552 if (msk & txirqmask[port])
553 ecmd->tx_coalesce_usecs = delay;
559 /* Note: interrupt timer is per board, but can turn on/off per port */
560 static int skge_set_coalesce(struct net_device *dev,
561 struct ethtool_coalesce *ecmd)
563 struct skge_port *skge = netdev_priv(dev);
564 struct skge_hw *hw = skge->hw;
565 int port = skge->port;
566 u32 msk = skge_read32(hw, B2_IRQM_MSK);
569 if (ecmd->rx_coalesce_usecs == 0)
570 msk &= ~rxirqmask[port];
571 else if (ecmd->rx_coalesce_usecs < 25 ||
572 ecmd->rx_coalesce_usecs > 33333)
575 msk |= rxirqmask[port];
576 delay = ecmd->rx_coalesce_usecs;
579 if (ecmd->tx_coalesce_usecs == 0)
580 msk &= ~txirqmask[port];
581 else if (ecmd->tx_coalesce_usecs < 25 ||
582 ecmd->tx_coalesce_usecs > 33333)
585 msk |= txirqmask[port];
586 delay = min(delay, ecmd->rx_coalesce_usecs);
589 skge_write32(hw, B2_IRQM_MSK, msk);
591 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
593 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
594 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
599 enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
600 static void skge_led(struct skge_port *skge, enum led_mode mode)
602 struct skge_hw *hw = skge->hw;
603 int port = skge->port;
605 mutex_lock(&hw->phy_mutex);
606 if (hw->chip_id == CHIP_ID_GENESIS) {
609 if (hw->phy_type == SK_PHY_BCOM)
610 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
612 skge_write32(hw, SK_REG(port, TX_LED_VAL), 0);
613 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_T_OFF);
615 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
616 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
617 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
621 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
622 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
624 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
625 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
630 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
631 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
632 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
634 if (hw->phy_type == SK_PHY_BCOM)
635 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
637 skge_write8(hw, SK_REG(port, TX_LED_TST), LED_T_ON);
638 skge_write32(hw, SK_REG(port, TX_LED_VAL), 100);
639 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
646 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
647 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
648 PHY_M_LED_MO_DUP(MO_LED_OFF) |
649 PHY_M_LED_MO_10(MO_LED_OFF) |
650 PHY_M_LED_MO_100(MO_LED_OFF) |
651 PHY_M_LED_MO_1000(MO_LED_OFF) |
652 PHY_M_LED_MO_RX(MO_LED_OFF));
655 gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
656 PHY_M_LED_PULS_DUR(PULS_170MS) |
657 PHY_M_LED_BLINK_RT(BLINK_84MS) |
661 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
662 PHY_M_LED_MO_RX(MO_LED_OFF) |
663 (skge->speed == SPEED_100 ?
664 PHY_M_LED_MO_100(MO_LED_ON) : 0));
667 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
668 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
669 PHY_M_LED_MO_DUP(MO_LED_ON) |
670 PHY_M_LED_MO_10(MO_LED_ON) |
671 PHY_M_LED_MO_100(MO_LED_ON) |
672 PHY_M_LED_MO_1000(MO_LED_ON) |
673 PHY_M_LED_MO_RX(MO_LED_ON));
676 mutex_unlock(&hw->phy_mutex);
679 /* blink LED's for finding board */
680 static int skge_phys_id(struct net_device *dev, u32 data)
682 struct skge_port *skge = netdev_priv(dev);
684 enum led_mode mode = LED_MODE_TST;
686 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
687 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT / HZ) * 1000;
692 skge_led(skge, mode);
693 mode ^= LED_MODE_TST;
695 if (msleep_interruptible(BLINK_MS))
700 /* back to regular LED state */
701 skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
706 static const struct ethtool_ops skge_ethtool_ops = {
707 .get_settings = skge_get_settings,
708 .set_settings = skge_set_settings,
709 .get_drvinfo = skge_get_drvinfo,
710 .get_regs_len = skge_get_regs_len,
711 .get_regs = skge_get_regs,
712 .get_wol = skge_get_wol,
713 .set_wol = skge_set_wol,
714 .get_msglevel = skge_get_msglevel,
715 .set_msglevel = skge_set_msglevel,
716 .nway_reset = skge_nway_reset,
717 .get_link = ethtool_op_get_link,
718 .get_ringparam = skge_get_ring_param,
719 .set_ringparam = skge_set_ring_param,
720 .get_pauseparam = skge_get_pauseparam,
721 .set_pauseparam = skge_set_pauseparam,
722 .get_coalesce = skge_get_coalesce,
723 .set_coalesce = skge_set_coalesce,
724 .get_sg = ethtool_op_get_sg,
725 .set_sg = skge_set_sg,
726 .get_tx_csum = ethtool_op_get_tx_csum,
727 .set_tx_csum = skge_set_tx_csum,
728 .get_rx_csum = skge_get_rx_csum,
729 .set_rx_csum = skge_set_rx_csum,
730 .get_strings = skge_get_strings,
731 .phys_id = skge_phys_id,
732 .get_stats_count = skge_get_stats_count,
733 .get_ethtool_stats = skge_get_ethtool_stats,
734 .get_perm_addr = ethtool_op_get_perm_addr,
738 * Allocate ring elements and chain them together
739 * One-to-one association of board descriptors with ring elements
741 static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u32 base)
743 struct skge_tx_desc *d;
744 struct skge_element *e;
747 ring->start = kcalloc(sizeof(*e), ring->count, GFP_KERNEL);
751 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
753 if (i == ring->count - 1) {
754 e->next = ring->start;
755 d->next_offset = base;
758 d->next_offset = base + (i+1) * sizeof(*d);
761 ring->to_use = ring->to_clean = ring->start;
766 /* Allocate and setup a new buffer for receiving */
767 static void skge_rx_setup(struct skge_port *skge, struct skge_element *e,
768 struct sk_buff *skb, unsigned int bufsize)
770 struct skge_rx_desc *rd = e->desc;
773 map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
777 rd->dma_hi = map >> 32;
779 rd->csum1_start = ETH_HLEN;
780 rd->csum2_start = ETH_HLEN;
786 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
787 pci_unmap_addr_set(e, mapaddr, map);
788 pci_unmap_len_set(e, maplen, bufsize);
791 /* Resume receiving using existing skb,
792 * Note: DMA address is not changed by chip.
793 * MTU not changed while receiver active.
795 static inline void skge_rx_reuse(struct skge_element *e, unsigned int size)
797 struct skge_rx_desc *rd = e->desc;
800 rd->csum2_start = ETH_HLEN;
804 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
808 /* Free all buffers in receive ring, assumes receiver stopped */
809 static void skge_rx_clean(struct skge_port *skge)
811 struct skge_hw *hw = skge->hw;
812 struct skge_ring *ring = &skge->rx_ring;
813 struct skge_element *e;
817 struct skge_rx_desc *rd = e->desc;
820 pci_unmap_single(hw->pdev,
821 pci_unmap_addr(e, mapaddr),
822 pci_unmap_len(e, maplen),
824 dev_kfree_skb(e->skb);
827 } while ((e = e->next) != ring->start);
831 /* Allocate buffers for receive ring
832 * For receive: to_clean is next received frame.
834 static int skge_rx_fill(struct net_device *dev)
836 struct skge_port *skge = netdev_priv(dev);
837 struct skge_ring *ring = &skge->rx_ring;
838 struct skge_element *e;
844 skb = __netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN,
849 skb_reserve(skb, NET_IP_ALIGN);
850 skge_rx_setup(skge, e, skb, skge->rx_buf_size);
851 } while ( (e = e->next) != ring->start);
853 ring->to_clean = ring->start;
857 static void skge_link_up(struct skge_port *skge)
859 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
860 LED_BLK_OFF|LED_SYNC_OFF|LED_ON);
862 netif_carrier_on(skge->netdev);
863 netif_wake_queue(skge->netdev);
865 if (netif_msg_link(skge))
867 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
868 skge->netdev->name, skge->speed,
869 skge->duplex == DUPLEX_FULL ? "full" : "half",
870 (skge->flow_control == FLOW_MODE_NONE) ? "none" :
871 (skge->flow_control == FLOW_MODE_LOC_SEND) ? "tx only" :
872 (skge->flow_control == FLOW_MODE_REM_SEND) ? "rx only" :
873 (skge->flow_control == FLOW_MODE_SYMMETRIC) ? "tx and rx" :
877 static void skge_link_down(struct skge_port *skge)
879 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
880 netif_carrier_off(skge->netdev);
881 netif_stop_queue(skge->netdev);
883 if (netif_msg_link(skge))
884 printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name);
888 static void xm_link_down(struct skge_hw *hw, int port)
890 struct net_device *dev = hw->dev[port];
891 struct skge_port *skge = netdev_priv(dev);
894 if (hw->phy_type == SK_PHY_XMAC) {
895 msk = xm_read16(hw, port, XM_IMSK);
896 msk |= XM_IS_INP_ASS | XM_IS_LIPA_RC | XM_IS_RX_PAGE | XM_IS_AND;
897 xm_write16(hw, port, XM_IMSK, msk);
900 cmd = xm_read16(hw, port, XM_MMU_CMD);
901 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
902 xm_write16(hw, port, XM_MMU_CMD, cmd);
903 /* dummy read to ensure writing */
904 (void) xm_read16(hw, port, XM_MMU_CMD);
906 if (netif_carrier_ok(dev))
907 skge_link_down(skge);
910 static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
914 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
915 *val = xm_read16(hw, port, XM_PHY_DATA);
917 if (hw->phy_type == SK_PHY_XMAC)
920 for (i = 0; i < PHY_RETRIES; i++) {
921 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
928 *val = xm_read16(hw, port, XM_PHY_DATA);
933 static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
936 if (__xm_phy_read(hw, port, reg, &v))
937 printk(KERN_WARNING PFX "%s: phy read timed out\n",
938 hw->dev[port]->name);
942 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
946 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
947 for (i = 0; i < PHY_RETRIES; i++) {
948 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
955 xm_write16(hw, port, XM_PHY_DATA, val);
956 for (i = 0; i < PHY_RETRIES; i++) {
957 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
964 static void genesis_init(struct skge_hw *hw)
966 /* set blink source counter */
967 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
968 skge_write8(hw, B2_BSC_CTRL, BSC_START);
970 /* configure mac arbiter */
971 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
973 /* configure mac arbiter timeout values */
974 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
975 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
976 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
977 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
979 skge_write8(hw, B3_MA_RCINI_RX1, 0);
980 skge_write8(hw, B3_MA_RCINI_RX2, 0);
981 skge_write8(hw, B3_MA_RCINI_TX1, 0);
982 skge_write8(hw, B3_MA_RCINI_TX2, 0);
984 /* configure packet arbiter timeout */
985 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
986 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
987 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
988 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
989 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
992 static void genesis_reset(struct skge_hw *hw, int port)
994 const u8 zero[8] = { 0 };
996 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
998 /* reset the statistics module */
999 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
1000 xm_write16(hw, port, XM_IMSK, 0xffff); /* disable XMAC IRQs */
1001 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
1002 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
1003 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
1005 /* disable Broadcom PHY IRQ */
1006 if (hw->phy_type == SK_PHY_BCOM)
1007 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
1009 xm_outhash(hw, port, XM_HSM, zero);
1013 /* Convert mode to MII values */
1014 static const u16 phy_pause_map[] = {
1015 [FLOW_MODE_NONE] = 0,
1016 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
1017 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
1018 [FLOW_MODE_REM_SEND] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
1021 /* special defines for FIBER (88E1011S only) */
1022 static const u16 fiber_pause_map[] = {
1023 [FLOW_MODE_NONE] = PHY_X_P_NO_PAUSE,
1024 [FLOW_MODE_LOC_SEND] = PHY_X_P_ASYM_MD,
1025 [FLOW_MODE_SYMMETRIC] = PHY_X_P_SYM_MD,
1026 [FLOW_MODE_REM_SEND] = PHY_X_P_BOTH_MD,
1030 /* Check status of Broadcom phy link */
1031 static void bcom_check_link(struct skge_hw *hw, int port)
1033 struct net_device *dev = hw->dev[port];
1034 struct skge_port *skge = netdev_priv(dev);
1037 /* read twice because of latch */
1038 (void) xm_phy_read(hw, port, PHY_BCOM_STAT);
1039 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
1041 if ((status & PHY_ST_LSYNC) == 0) {
1042 xm_link_down(hw, port);
1046 if (skge->autoneg == AUTONEG_ENABLE) {
1049 if (!(status & PHY_ST_AN_OVER))
1052 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1053 if (lpa & PHY_B_AN_RF) {
1054 printk(KERN_NOTICE PFX "%s: remote fault\n",
1059 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1061 /* Check Duplex mismatch */
1062 switch (aux & PHY_B_AS_AN_RES_MSK) {
1063 case PHY_B_RES_1000FD:
1064 skge->duplex = DUPLEX_FULL;
1066 case PHY_B_RES_1000HD:
1067 skge->duplex = DUPLEX_HALF;
1070 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1076 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1077 switch (aux & PHY_B_AS_PAUSE_MSK) {
1078 case PHY_B_AS_PAUSE_MSK:
1079 skge->flow_control = FLOW_MODE_SYMMETRIC;
1082 skge->flow_control = FLOW_MODE_REM_SEND;
1085 skge->flow_control = FLOW_MODE_LOC_SEND;
1088 skge->flow_control = FLOW_MODE_NONE;
1090 skge->speed = SPEED_1000;
1093 if (!netif_carrier_ok(dev))
1094 genesis_link_up(skge);
1097 /* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1098 * Phy on for 100 or 10Mbit operation
1100 static void bcom_phy_init(struct skge_port *skge)
1102 struct skge_hw *hw = skge->hw;
1103 int port = skge->port;
1105 u16 id1, r, ext, ctl;
1107 /* magic workaround patterns for Broadcom */
1108 static const struct {
1112 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1113 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1114 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1115 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1117 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1118 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1121 /* read Id from external PHY (all have the same address) */
1122 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1124 /* Optimize MDIO transfer by suppressing preamble. */
1125 r = xm_read16(hw, port, XM_MMU_CMD);
1127 xm_write16(hw, port, XM_MMU_CMD,r);
1130 case PHY_BCOM_ID1_C0:
1132 * Workaround BCOM Errata for the C0 type.
1133 * Write magic patterns to reserved registers.
1135 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1136 xm_phy_write(hw, port,
1137 C0hack[i].reg, C0hack[i].val);
1140 case PHY_BCOM_ID1_A1:
1142 * Workaround BCOM Errata for the A1 type.
1143 * Write magic patterns to reserved registers.
1145 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1146 xm_phy_write(hw, port,
1147 A1hack[i].reg, A1hack[i].val);
1152 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1153 * Disable Power Management after reset.
1155 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1156 r |= PHY_B_AC_DIS_PM;
1157 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1160 xm_read16(hw, port, XM_ISRC);
1162 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1163 ctl = PHY_CT_SP1000; /* always 1000mbit */
1165 if (skge->autoneg == AUTONEG_ENABLE) {
1167 * Workaround BCOM Errata #1 for the C5 type.
1168 * 1000Base-T Link Acquisition Failure in Slave Mode
1169 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1171 u16 adv = PHY_B_1000C_RD;
1172 if (skge->advertising & ADVERTISED_1000baseT_Half)
1173 adv |= PHY_B_1000C_AHD;
1174 if (skge->advertising & ADVERTISED_1000baseT_Full)
1175 adv |= PHY_B_1000C_AFD;
1176 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1178 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1180 if (skge->duplex == DUPLEX_FULL)
1181 ctl |= PHY_CT_DUP_MD;
1182 /* Force to slave */
1183 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1186 /* Set autonegotiation pause parameters */
1187 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1188 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1190 /* Handle Jumbo frames */
1191 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
1192 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1193 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1195 ext |= PHY_B_PEC_HIGH_LA;
1199 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1200 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1202 /* Use link status change interrupt */
1203 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1206 static void xm_phy_init(struct skge_port *skge)
1208 struct skge_hw *hw = skge->hw;
1209 int port = skge->port;
1212 if (skge->autoneg == AUTONEG_ENABLE) {
1213 if (skge->advertising & ADVERTISED_1000baseT_Half)
1214 ctrl |= PHY_X_AN_HD;
1215 if (skge->advertising & ADVERTISED_1000baseT_Full)
1216 ctrl |= PHY_X_AN_FD;
1218 ctrl |= fiber_pause_map[skge->flow_control];
1220 xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl);
1222 /* Restart Auto-negotiation */
1223 ctrl = PHY_CT_ANE | PHY_CT_RE_CFG;
1225 /* Set DuplexMode in Config register */
1226 if (skge->duplex == DUPLEX_FULL)
1227 ctrl |= PHY_CT_DUP_MD;
1229 * Do NOT enable Auto-negotiation here. This would hold
1230 * the link down because no IDLEs are transmitted
1234 xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl);
1236 /* Poll PHY for status changes */
1237 schedule_delayed_work(&skge->link_thread, LINK_HZ);
1240 static void xm_check_link(struct net_device *dev)
1242 struct skge_port *skge = netdev_priv(dev);
1243 struct skge_hw *hw = skge->hw;
1244 int port = skge->port;
1247 /* read twice because of latch */
1248 (void) xm_phy_read(hw, port, PHY_XMAC_STAT);
1249 status = xm_phy_read(hw, port, PHY_XMAC_STAT);
1251 if ((status & PHY_ST_LSYNC) == 0) {
1252 xm_link_down(hw, port);
1256 if (skge->autoneg == AUTONEG_ENABLE) {
1259 if (!(status & PHY_ST_AN_OVER))
1262 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1263 if (lpa & PHY_B_AN_RF) {
1264 printk(KERN_NOTICE PFX "%s: remote fault\n",
1269 res = xm_phy_read(hw, port, PHY_XMAC_RES_ABI);
1271 /* Check Duplex mismatch */
1272 switch (res & (PHY_X_RS_HD | PHY_X_RS_FD)) {
1274 skge->duplex = DUPLEX_FULL;
1277 skge->duplex = DUPLEX_HALF;
1280 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1285 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1286 if (lpa & PHY_X_P_SYM_MD)
1287 skge->flow_control = FLOW_MODE_SYMMETRIC;
1288 else if ((lpa & PHY_X_RS_PAUSE) == PHY_X_P_ASYM_MD)
1289 skge->flow_control = FLOW_MODE_REM_SEND;
1290 else if ((lpa & PHY_X_RS_PAUSE) == PHY_X_P_BOTH_MD)
1291 skge->flow_control = FLOW_MODE_LOC_SEND;
1293 skge->flow_control = FLOW_MODE_NONE;
1296 skge->speed = SPEED_1000;
1299 if (!netif_carrier_ok(dev))
1300 genesis_link_up(skge);
1303 /* Poll to check for link coming up.
1304 * Since internal PHY is wired to a level triggered pin, can't
1305 * get an interrupt when carrier is detected.
1307 static void xm_link_timer(void *arg)
1309 struct net_device *dev = arg;
1310 struct skge_port *skge = netdev_priv(arg);
1311 struct skge_hw *hw = skge->hw;
1312 int port = skge->port;
1314 if (!netif_running(dev))
1317 if (netif_carrier_ok(dev)) {
1318 xm_read16(hw, port, XM_ISRC);
1319 if (!(xm_read16(hw, port, XM_ISRC) & XM_IS_INP_ASS))
1322 if (xm_read32(hw, port, XM_GP_PORT) & XM_GP_INP_ASS)
1324 xm_read16(hw, port, XM_ISRC);
1325 if (xm_read16(hw, port, XM_ISRC) & XM_IS_INP_ASS)
1329 mutex_lock(&hw->phy_mutex);
1331 mutex_unlock(&hw->phy_mutex);
1334 schedule_delayed_work(&skge->link_thread, LINK_HZ);
1337 static void genesis_mac_init(struct skge_hw *hw, int port)
1339 struct net_device *dev = hw->dev[port];
1340 struct skge_port *skge = netdev_priv(dev);
1341 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1344 const u8 zero[6] = { 0 };
1346 for (i = 0; i < 10; i++) {
1347 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
1349 if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)
1354 printk(KERN_WARNING PFX "%s: genesis reset failed\n", dev->name);
1357 /* Unreset the XMAC. */
1358 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1361 * Perform additional initialization for external PHYs,
1362 * namely for the 1000baseTX cards that use the XMAC's
1365 if (hw->phy_type != SK_PHY_XMAC) {
1366 /* Take external Phy out of reset */
1367 r = skge_read32(hw, B2_GP_IO);
1369 r |= GP_DIR_0|GP_IO_0;
1371 r |= GP_DIR_2|GP_IO_2;
1373 skge_write32(hw, B2_GP_IO, r);
1375 /* Enable GMII interface */
1376 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1380 switch(hw->phy_type) {
1385 bcom_phy_init(skge);
1386 bcom_check_link(hw, port);
1389 /* Set Station Address */
1390 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
1392 /* We don't use match addresses so clear */
1393 for (i = 1; i < 16; i++)
1394 xm_outaddr(hw, port, XM_EXM(i), zero);
1396 /* Clear MIB counters */
1397 xm_write16(hw, port, XM_STAT_CMD,
1398 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1399 /* Clear two times according to Errata #3 */
1400 xm_write16(hw, port, XM_STAT_CMD,
1401 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1403 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1404 xm_write16(hw, port, XM_RX_HI_WM, 1450);
1406 /* We don't need the FCS appended to the packet. */
1407 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1409 r |= XM_RX_BIG_PK_OK;
1411 if (skge->duplex == DUPLEX_HALF) {
1413 * If in manual half duplex mode the other side might be in
1414 * full duplex mode, so ignore if a carrier extension is not seen
1415 * on frames received
1417 r |= XM_RX_DIS_CEXT;
1419 xm_write16(hw, port, XM_RX_CMD, r);
1422 /* We want short frames padded to 60 bytes. */
1423 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1426 * Bump up the transmit threshold. This helps hold off transmit
1427 * underruns when we're blasting traffic from both ports at once.
1429 xm_write16(hw, port, XM_TX_THR, 512);
1432 * Enable the reception of all error frames. This is is
1433 * a necessary evil due to the design of the XMAC. The
1434 * XMAC's receive FIFO is only 8K in size, however jumbo
1435 * frames can be up to 9000 bytes in length. When bad
1436 * frame filtering is enabled, the XMAC's RX FIFO operates
1437 * in 'store and forward' mode. For this to work, the
1438 * entire frame has to fit into the FIFO, but that means
1439 * that jumbo frames larger than 8192 bytes will be
1440 * truncated. Disabling all bad frame filtering causes
1441 * the RX FIFO to operate in streaming mode, in which
1442 * case the XMAC will start transferring frames out of the
1443 * RX FIFO as soon as the FIFO threshold is reached.
1445 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
1449 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1450 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1451 * and 'Octets Rx OK Hi Cnt Ov'.
1453 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1456 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1457 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1458 * and 'Octets Tx OK Hi Cnt Ov'.
1460 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
1462 /* Configure MAC arbiter */
1463 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1465 /* configure timeout values */
1466 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1467 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1468 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1469 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1471 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1472 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1473 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1474 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1476 /* Configure Rx MAC FIFO */
1477 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1478 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1479 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
1481 /* Configure Tx MAC FIFO */
1482 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1483 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1484 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
1487 /* Enable frame flushing if jumbo frames used */
1488 skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);
1490 /* enable timeout timers if normal frames */
1491 skge_write16(hw, B3_PA_CTRL,
1492 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
1496 static void genesis_stop(struct skge_port *skge)
1498 struct skge_hw *hw = skge->hw;
1499 int port = skge->port;
1502 genesis_reset(hw, port);
1504 /* Clear Tx packet arbiter timeout IRQ */
1505 skge_write16(hw, B3_PA_CTRL,
1506 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1509 * If the transfer sticks at the MAC the STOP command will not
1510 * terminate if we don't flush the XMAC's transmit FIFO !
1512 xm_write32(hw, port, XM_MODE,
1513 xm_read32(hw, port, XM_MODE)|XM_MD_FTF);
1517 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
1519 /* For external PHYs there must be special handling */
1520 if (hw->phy_type != SK_PHY_XMAC) {
1521 reg = skge_read32(hw, B2_GP_IO);
1529 skge_write32(hw, B2_GP_IO, reg);
1530 skge_read32(hw, B2_GP_IO);
1533 xm_write16(hw, port, XM_MMU_CMD,
1534 xm_read16(hw, port, XM_MMU_CMD)
1535 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1537 xm_read16(hw, port, XM_MMU_CMD);
1541 static void genesis_get_stats(struct skge_port *skge, u64 *data)
1543 struct skge_hw *hw = skge->hw;
1544 int port = skge->port;
1546 unsigned long timeout = jiffies + HZ;
1548 xm_write16(hw, port,
1549 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1551 /* wait for update to complete */
1552 while (xm_read16(hw, port, XM_STAT_CMD)
1553 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1554 if (time_after(jiffies, timeout))
1559 /* special case for 64 bit octet counter */
1560 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1561 | xm_read32(hw, port, XM_TXO_OK_LO);
1562 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1563 | xm_read32(hw, port, XM_RXO_OK_LO);
1565 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1566 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
1569 static void genesis_mac_intr(struct skge_hw *hw, int port)
1571 struct skge_port *skge = netdev_priv(hw->dev[port]);
1572 u16 status = xm_read16(hw, port, XM_ISRC);
1574 if (netif_msg_intr(skge))
1575 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1576 skge->netdev->name, status);
1578 if (hw->phy_type == SK_PHY_XMAC &&
1579 (status & (XM_IS_INP_ASS | XM_IS_LIPA_RC)))
1580 xm_link_down(hw, port);
1582 if (status & XM_IS_TXF_UR) {
1583 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
1584 ++skge->net_stats.tx_fifo_errors;
1586 if (status & XM_IS_RXF_OV) {
1587 xm_write32(hw, port, XM_MODE, XM_MD_FRF);
1588 ++skge->net_stats.rx_fifo_errors;
1592 static void genesis_link_up(struct skge_port *skge)
1594 struct skge_hw *hw = skge->hw;
1595 int port = skge->port;
1599 cmd = xm_read16(hw, port, XM_MMU_CMD);
1602 * enabling pause frame reception is required for 1000BT
1603 * because the XMAC is not reset if the link is going down
1605 if (skge->flow_control == FLOW_MODE_NONE ||
1606 skge->flow_control == FLOW_MODE_LOC_SEND)
1607 /* Disable Pause Frame Reception */
1608 cmd |= XM_MMU_IGN_PF;
1610 /* Enable Pause Frame Reception */
1611 cmd &= ~XM_MMU_IGN_PF;
1613 xm_write16(hw, port, XM_MMU_CMD, cmd);
1615 mode = xm_read32(hw, port, XM_MODE);
1616 if (skge->flow_control == FLOW_MODE_SYMMETRIC ||
1617 skge->flow_control == FLOW_MODE_LOC_SEND) {
1619 * Configure Pause Frame Generation
1620 * Use internal and external Pause Frame Generation.
1621 * Sending pause frames is edge triggered.
1622 * Send a Pause frame with the maximum pause time if
1623 * internal oder external FIFO full condition occurs.
1624 * Send a zero pause time frame to re-start transmission.
1626 /* XM_PAUSE_DA = '010000C28001' (default) */
1627 /* XM_MAC_PTIME = 0xffff (maximum) */
1628 /* remember this value is defined in big endian (!) */
1629 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
1631 mode |= XM_PAUSE_MODE;
1632 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
1635 * disable pause frame generation is required for 1000BT
1636 * because the XMAC is not reset if the link is going down
1638 /* Disable Pause Mode in Mode Register */
1639 mode &= ~XM_PAUSE_MODE;
1641 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
1644 xm_write32(hw, port, XM_MODE, mode);
1646 if (hw->phy_type != SK_PHY_XMAC)
1647 msk |= XM_IS_INP_ASS; /* disable GP0 interrupt bit */
1649 xm_write16(hw, port, XM_IMSK, msk);
1650 xm_read16(hw, port, XM_ISRC);
1652 /* get MMU Command Reg. */
1653 cmd = xm_read16(hw, port, XM_MMU_CMD);
1654 if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL)
1655 cmd |= XM_MMU_GMII_FD;
1658 * Workaround BCOM Errata (#10523) for all BCom Phys
1659 * Enable Power Management after link up
1661 if (hw->phy_type == SK_PHY_BCOM) {
1662 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1663 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1664 & ~PHY_B_AC_DIS_PM);
1665 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1669 xm_write16(hw, port, XM_MMU_CMD,
1670 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1675 static inline void bcom_phy_intr(struct skge_port *skge)
1677 struct skge_hw *hw = skge->hw;
1678 int port = skge->port;
1681 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
1682 if (netif_msg_intr(skge))
1683 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x\n",
1684 skge->netdev->name, isrc);
1686 if (isrc & PHY_B_IS_PSE)
1687 printk(KERN_ERR PFX "%s: uncorrectable pair swap error\n",
1688 hw->dev[port]->name);
1690 /* Workaround BCom Errata:
1691 * enable and disable loopback mode if "NO HCD" occurs.
1693 if (isrc & PHY_B_IS_NO_HDCL) {
1694 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1695 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1696 ctrl | PHY_CT_LOOP);
1697 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1698 ctrl & ~PHY_CT_LOOP);
1701 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1702 bcom_check_link(hw, port);
1706 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1710 gma_write16(hw, port, GM_SMI_DATA, val);
1711 gma_write16(hw, port, GM_SMI_CTRL,
1712 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1713 for (i = 0; i < PHY_RETRIES; i++) {
1716 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1720 printk(KERN_WARNING PFX "%s: phy write timeout\n",
1721 hw->dev[port]->name);
1725 static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1729 gma_write16(hw, port, GM_SMI_CTRL,
1730 GM_SMI_CT_PHY_AD(hw->phy_addr)
1731 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1733 for (i = 0; i < PHY_RETRIES; i++) {
1735 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1741 *val = gma_read16(hw, port, GM_SMI_DATA);
1745 static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1748 if (__gm_phy_read(hw, port, reg, &v))
1749 printk(KERN_WARNING PFX "%s: phy read timeout\n",
1750 hw->dev[port]->name);
1754 /* Marvell Phy Initialization */
1755 static void yukon_init(struct skge_hw *hw, int port)
1757 struct skge_port *skge = netdev_priv(hw->dev[port]);
1758 u16 ctrl, ct1000, adv;
1760 if (skge->autoneg == AUTONEG_ENABLE) {
1761 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
1763 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1764 PHY_M_EC_MAC_S_MSK);
1765 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1767 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
1769 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
1772 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1773 if (skge->autoneg == AUTONEG_DISABLE)
1774 ctrl &= ~PHY_CT_ANE;
1776 ctrl |= PHY_CT_RESET;
1777 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1783 if (skge->autoneg == AUTONEG_ENABLE) {
1785 if (skge->advertising & ADVERTISED_1000baseT_Full)
1786 ct1000 |= PHY_M_1000C_AFD;
1787 if (skge->advertising & ADVERTISED_1000baseT_Half)
1788 ct1000 |= PHY_M_1000C_AHD;
1789 if (skge->advertising & ADVERTISED_100baseT_Full)
1790 adv |= PHY_M_AN_100_FD;
1791 if (skge->advertising & ADVERTISED_100baseT_Half)
1792 adv |= PHY_M_AN_100_HD;
1793 if (skge->advertising & ADVERTISED_10baseT_Full)
1794 adv |= PHY_M_AN_10_FD;
1795 if (skge->advertising & ADVERTISED_10baseT_Half)
1796 adv |= PHY_M_AN_10_HD;
1798 /* Set Flow-control capabilities */
1799 adv |= phy_pause_map[skge->flow_control];
1801 if (skge->advertising & ADVERTISED_1000baseT_Full)
1802 adv |= PHY_M_AN_1000X_AFD;
1803 if (skge->advertising & ADVERTISED_1000baseT_Half)
1804 adv |= PHY_M_AN_1000X_AHD;
1806 adv |= fiber_pause_map[skge->flow_control];
1809 /* Restart Auto-negotiation */
1810 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1812 /* forced speed/duplex settings */
1813 ct1000 = PHY_M_1000C_MSE;
1815 if (skge->duplex == DUPLEX_FULL)
1816 ctrl |= PHY_CT_DUP_MD;
1818 switch (skge->speed) {
1820 ctrl |= PHY_CT_SP1000;
1823 ctrl |= PHY_CT_SP100;
1827 ctrl |= PHY_CT_RESET;
1830 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
1832 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
1833 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1835 /* Enable phy interrupt on autonegotiation complete (or link up) */
1836 if (skge->autoneg == AUTONEG_ENABLE)
1837 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
1839 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
1842 static void yukon_reset(struct skge_hw *hw, int port)
1844 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
1845 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
1846 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
1847 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
1848 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
1850 gma_write16(hw, port, GM_RX_CTRL,
1851 gma_read16(hw, port, GM_RX_CTRL)
1852 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
1855 /* Apparently, early versions of Yukon-Lite had wrong chip_id? */
1856 static int is_yukon_lite_a0(struct skge_hw *hw)
1861 if (hw->chip_id != CHIP_ID_YUKON)
1864 reg = skge_read32(hw, B2_FAR);
1865 skge_write8(hw, B2_FAR + 3, 0xff);
1866 ret = (skge_read8(hw, B2_FAR + 3) != 0);
1867 skge_write32(hw, B2_FAR, reg);
1871 static void yukon_mac_init(struct skge_hw *hw, int port)
1873 struct skge_port *skge = netdev_priv(hw->dev[port]);
1876 const u8 *addr = hw->dev[port]->dev_addr;
1878 /* WA code for COMA mode -- set PHY reset */
1879 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1880 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1881 reg = skge_read32(hw, B2_GP_IO);
1882 reg |= GP_DIR_9 | GP_IO_9;
1883 skge_write32(hw, B2_GP_IO, reg);
1887 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1888 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1890 /* WA code for COMA mode -- clear PHY reset */
1891 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1892 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1893 reg = skge_read32(hw, B2_GP_IO);
1896 skge_write32(hw, B2_GP_IO, reg);
1899 /* Set hardware config mode */
1900 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
1901 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
1902 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
1904 /* Clear GMC reset */
1905 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
1906 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
1907 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
1909 if (skge->autoneg == AUTONEG_DISABLE) {
1910 reg = GM_GPCR_AU_ALL_DIS;
1911 gma_write16(hw, port, GM_GP_CTRL,
1912 gma_read16(hw, port, GM_GP_CTRL) | reg);
1914 switch (skge->speed) {
1916 reg &= ~GM_GPCR_SPEED_100;
1917 reg |= GM_GPCR_SPEED_1000;
1920 reg &= ~GM_GPCR_SPEED_1000;
1921 reg |= GM_GPCR_SPEED_100;
1924 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
1928 if (skge->duplex == DUPLEX_FULL)
1929 reg |= GM_GPCR_DUP_FULL;
1931 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
1933 switch (skge->flow_control) {
1934 case FLOW_MODE_NONE:
1935 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1936 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1938 case FLOW_MODE_LOC_SEND:
1939 /* disable Rx flow-control */
1940 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1943 gma_write16(hw, port, GM_GP_CTRL, reg);
1944 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
1946 yukon_init(hw, port);
1949 reg = gma_read16(hw, port, GM_PHY_ADDR);
1950 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
1952 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
1953 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
1954 gma_write16(hw, port, GM_PHY_ADDR, reg);
1956 /* transmit control */
1957 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
1959 /* receive control reg: unicast + multicast + no FCS */
1960 gma_write16(hw, port, GM_RX_CTRL,
1961 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
1963 /* transmit flow control */
1964 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
1966 /* transmit parameter */
1967 gma_write16(hw, port, GM_TX_PARAM,
1968 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
1969 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
1970 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
1972 /* serial mode register */
1973 reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1974 if (hw->dev[port]->mtu > 1500)
1975 reg |= GM_SMOD_JUMBO_ENA;
1977 gma_write16(hw, port, GM_SERIAL_MODE, reg);
1979 /* physical address: used for pause frames */
1980 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
1981 /* virtual address for data */
1982 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
1984 /* enable interrupt mask for counter overflows */
1985 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
1986 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
1987 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
1989 /* Initialize Mac Fifo */
1991 /* Configure Rx MAC FIFO */
1992 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
1993 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
1995 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
1996 if (is_yukon_lite_a0(hw))
1997 reg &= ~GMF_RX_F_FL_ON;
1999 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
2000 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
2002 * because Pause Packet Truncation in GMAC is not working
2003 * we have to increase the Flush Threshold to 64 bytes
2004 * in order to flush pause packets in Rx FIFO on Yukon-1
2006 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
2008 /* Configure Tx MAC FIFO */
2009 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
2010 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
2013 /* Go into power down mode */
2014 static void yukon_suspend(struct skge_hw *hw, int port)
2018 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2019 ctrl |= PHY_M_PC_POL_R_DIS;
2020 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
2022 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2023 ctrl |= PHY_CT_RESET;
2024 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2026 /* switch IEEE compatible power down mode on */
2027 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2028 ctrl |= PHY_CT_PDOWN;
2029 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2032 static void yukon_stop(struct skge_port *skge)
2034 struct skge_hw *hw = skge->hw;
2035 int port = skge->port;
2037 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
2038 yukon_reset(hw, port);
2040 gma_write16(hw, port, GM_GP_CTRL,
2041 gma_read16(hw, port, GM_GP_CTRL)
2042 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
2043 gma_read16(hw, port, GM_GP_CTRL);
2045 yukon_suspend(hw, port);
2047 /* set GPHY Control reset */
2048 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2049 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
2052 static void yukon_get_stats(struct skge_port *skge, u64 *data)
2054 struct skge_hw *hw = skge->hw;
2055 int port = skge->port;
2058 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2059 | gma_read32(hw, port, GM_TXO_OK_LO);
2060 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2061 | gma_read32(hw, port, GM_RXO_OK_LO);
2063 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
2064 data[i] = gma_read32(hw, port,
2065 skge_stats[i].gma_offset);
2068 static void yukon_mac_intr(struct skge_hw *hw, int port)
2070 struct net_device *dev = hw->dev[port];
2071 struct skge_port *skge = netdev_priv(dev);
2072 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2074 if (netif_msg_intr(skge))
2075 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
2078 if (status & GM_IS_RX_FF_OR) {
2079 ++skge->net_stats.rx_fifo_errors;
2080 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2083 if (status & GM_IS_TX_FF_UR) {
2084 ++skge->net_stats.tx_fifo_errors;
2085 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2090 static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
2092 switch (aux & PHY_M_PS_SPEED_MSK) {
2093 case PHY_M_PS_SPEED_1000:
2095 case PHY_M_PS_SPEED_100:
2102 static void yukon_link_up(struct skge_port *skge)
2104 struct skge_hw *hw = skge->hw;
2105 int port = skge->port;
2108 /* Enable Transmit FIFO Underrun */
2109 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
2111 reg = gma_read16(hw, port, GM_GP_CTRL);
2112 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
2113 reg |= GM_GPCR_DUP_FULL;
2116 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
2117 gma_write16(hw, port, GM_GP_CTRL, reg);
2119 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
2123 static void yukon_link_down(struct skge_port *skge)
2125 struct skge_hw *hw = skge->hw;
2126 int port = skge->port;
2129 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
2131 ctrl = gma_read16(hw, port, GM_GP_CTRL);
2132 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2133 gma_write16(hw, port, GM_GP_CTRL, ctrl);
2135 if (skge->flow_control == FLOW_MODE_REM_SEND) {
2136 /* restore Asymmetric Pause bit */
2137 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
2138 gm_phy_read(hw, port,
2144 yukon_reset(hw, port);
2145 skge_link_down(skge);
2147 yukon_init(hw, port);
2150 static void yukon_phy_intr(struct skge_port *skge)
2152 struct skge_hw *hw = skge->hw;
2153 int port = skge->port;
2154 const char *reason = NULL;
2155 u16 istatus, phystat;
2157 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2158 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2160 if (netif_msg_intr(skge))
2161 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x 0x%x\n",
2162 skge->netdev->name, istatus, phystat);
2164 if (istatus & PHY_M_IS_AN_COMPL) {
2165 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
2167 reason = "remote fault";
2171 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
2172 reason = "master/slave fault";
2176 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
2177 reason = "speed/duplex";
2181 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
2182 ? DUPLEX_FULL : DUPLEX_HALF;
2183 skge->speed = yukon_speed(hw, phystat);
2185 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
2186 switch (phystat & PHY_M_PS_PAUSE_MSK) {
2187 case PHY_M_PS_PAUSE_MSK:
2188 skge->flow_control = FLOW_MODE_SYMMETRIC;
2190 case PHY_M_PS_RX_P_EN:
2191 skge->flow_control = FLOW_MODE_REM_SEND;
2193 case PHY_M_PS_TX_P_EN:
2194 skge->flow_control = FLOW_MODE_LOC_SEND;
2197 skge->flow_control = FLOW_MODE_NONE;
2200 if (skge->flow_control == FLOW_MODE_NONE ||
2201 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
2202 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2204 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2205 yukon_link_up(skge);
2209 if (istatus & PHY_M_IS_LSP_CHANGE)
2210 skge->speed = yukon_speed(hw, phystat);
2212 if (istatus & PHY_M_IS_DUP_CHANGE)
2213 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2214 if (istatus & PHY_M_IS_LST_CHANGE) {
2215 if (phystat & PHY_M_PS_LINK_UP)
2216 yukon_link_up(skge);
2218 yukon_link_down(skge);
2222 printk(KERN_ERR PFX "%s: autonegotiation failed (%s)\n",
2223 skge->netdev->name, reason);
2225 /* XXX restart autonegotiation? */
2228 static void skge_phy_reset(struct skge_port *skge)
2230 struct skge_hw *hw = skge->hw;
2231 int port = skge->port;
2233 netif_stop_queue(skge->netdev);
2234 netif_carrier_off(skge->netdev);
2236 mutex_lock(&hw->phy_mutex);
2237 if (hw->chip_id == CHIP_ID_GENESIS) {
2238 genesis_reset(hw, port);
2239 genesis_mac_init(hw, port);
2241 yukon_reset(hw, port);
2242 yukon_init(hw, port);
2244 mutex_unlock(&hw->phy_mutex);
2247 /* Basic MII support */
2248 static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2250 struct mii_ioctl_data *data = if_mii(ifr);
2251 struct skge_port *skge = netdev_priv(dev);
2252 struct skge_hw *hw = skge->hw;
2253 int err = -EOPNOTSUPP;
2255 if (!netif_running(dev))
2256 return -ENODEV; /* Phy still in reset */
2260 data->phy_id = hw->phy_addr;
2265 mutex_lock(&hw->phy_mutex);
2266 if (hw->chip_id == CHIP_ID_GENESIS)
2267 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2269 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2270 mutex_unlock(&hw->phy_mutex);
2271 data->val_out = val;
2276 if (!capable(CAP_NET_ADMIN))
2279 mutex_lock(&hw->phy_mutex);
2280 if (hw->chip_id == CHIP_ID_GENESIS)
2281 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2284 err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2286 mutex_unlock(&hw->phy_mutex);
2292 static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
2298 end = start + len - 1;
2300 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2301 skge_write32(hw, RB_ADDR(q, RB_START), start);
2302 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2303 skge_write32(hw, RB_ADDR(q, RB_RP), start);
2304 skge_write32(hw, RB_ADDR(q, RB_END), end);
2306 if (q == Q_R1 || q == Q_R2) {
2307 /* Set thresholds on receive queue's */
2308 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2310 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2313 /* Enable store & forward on Tx queue's because
2314 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2316 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
2319 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2322 /* Setup Bus Memory Interface */
2323 static void skge_qset(struct skge_port *skge, u16 q,
2324 const struct skge_element *e)
2326 struct skge_hw *hw = skge->hw;
2327 u32 watermark = 0x600;
2328 u64 base = skge->dma + (e->desc - skge->mem);
2330 /* optimization to reduce window on 32bit/33mhz */
2331 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2334 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2335 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2336 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2337 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2340 static int skge_up(struct net_device *dev)
2342 struct skge_port *skge = netdev_priv(dev);
2343 struct skge_hw *hw = skge->hw;
2344 int port = skge->port;
2345 u32 chunk, ram_addr;
2346 size_t rx_size, tx_size;
2349 if (netif_msg_ifup(skge))
2350 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
2352 if (dev->mtu > RX_BUF_SIZE)
2353 skge->rx_buf_size = dev->mtu + ETH_HLEN;
2355 skge->rx_buf_size = RX_BUF_SIZE;
2358 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2359 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2360 skge->mem_size = tx_size + rx_size;
2361 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2365 BUG_ON(skge->dma & 7);
2367 if ((u64)skge->dma >> 32 != ((u64) skge->dma + skge->mem_size) >> 32) {
2368 printk(KERN_ERR PFX "pci_alloc_consistent region crosses 4G boundary\n");
2373 memset(skge->mem, 0, skge->mem_size);
2375 err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma);
2379 err = skge_rx_fill(dev);
2383 err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2384 skge->dma + rx_size);
2388 /* Initialize MAC */
2389 mutex_lock(&hw->phy_mutex);
2390 if (hw->chip_id == CHIP_ID_GENESIS)
2391 genesis_mac_init(hw, port);
2393 yukon_mac_init(hw, port);
2394 mutex_unlock(&hw->phy_mutex);
2396 /* Configure RAMbuffers */
2397 chunk = hw->ram_size / ((hw->ports + 1)*2);
2398 ram_addr = hw->ram_offset + 2 * chunk * port;
2400 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
2401 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
2403 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
2404 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
2405 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2407 /* Start receiver BMU */
2409 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
2410 skge_led(skge, LED_MODE_ON);
2412 netif_poll_enable(dev);
2416 skge_rx_clean(skge);
2417 kfree(skge->rx_ring.start);
2419 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2425 static int skge_down(struct net_device *dev)
2427 struct skge_port *skge = netdev_priv(dev);
2428 struct skge_hw *hw = skge->hw;
2429 int port = skge->port;
2431 if (skge->mem == NULL)
2434 if (netif_msg_ifdown(skge))
2435 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
2437 netif_stop_queue(dev);
2438 if (hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC)
2439 cancel_rearming_delayed_work(&skge->link_thread);
2441 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
2442 if (hw->chip_id == CHIP_ID_GENESIS)
2447 /* Stop transmitter */
2448 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2449 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2450 RB_RST_SET|RB_DIS_OP_MD);
2453 /* Disable Force Sync bit and Enable Alloc bit */
2454 skge_write8(hw, SK_REG(port, TXA_CTRL),
2455 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2457 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
2458 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2459 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
2461 /* Reset PCI FIFO */
2462 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2463 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2465 /* Reset the RAM Buffer async Tx queue */
2466 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
2468 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2469 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2470 RB_RST_SET|RB_DIS_OP_MD);
2471 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2473 if (hw->chip_id == CHIP_ID_GENESIS) {
2474 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2475 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
2477 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2478 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
2481 skge_led(skge, LED_MODE_OFF);
2483 netif_poll_disable(dev);
2485 skge_rx_clean(skge);
2487 kfree(skge->rx_ring.start);
2488 kfree(skge->tx_ring.start);
2489 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2494 static inline int skge_avail(const struct skge_ring *ring)
2496 return ((ring->to_clean > ring->to_use) ? 0 : ring->count)
2497 + (ring->to_clean - ring->to_use) - 1;
2500 static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
2502 struct skge_port *skge = netdev_priv(dev);
2503 struct skge_hw *hw = skge->hw;
2504 struct skge_element *e;
2505 struct skge_tx_desc *td;
2510 if (skb_padto(skb, ETH_ZLEN))
2511 return NETDEV_TX_OK;
2513 if (unlikely(skge_avail(&skge->tx_ring) < skb_shinfo(skb)->nr_frags + 1))
2514 return NETDEV_TX_BUSY;
2516 e = skge->tx_ring.to_use;
2518 BUG_ON(td->control & BMU_OWN);
2520 len = skb_headlen(skb);
2521 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
2522 pci_unmap_addr_set(e, mapaddr, map);
2523 pci_unmap_len_set(e, maplen, len);
2526 td->dma_hi = map >> 32;
2528 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2529 int offset = skb->h.raw - skb->data;
2531 /* This seems backwards, but it is what the sk98lin
2532 * does. Looks like hardware is wrong?
2534 if (skb->h.ipiph->protocol == IPPROTO_UDP
2535 && hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
2536 control = BMU_TCP_CHECK;
2538 control = BMU_UDP_CHECK;
2541 td->csum_start = offset;
2542 td->csum_write = offset + skb->csum;
2544 control = BMU_CHECK;
2546 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
2547 control |= BMU_EOF| BMU_IRQ_EOF;
2549 struct skge_tx_desc *tf = td;
2551 control |= BMU_STFWD;
2552 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2553 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2555 map = pci_map_page(hw->pdev, frag->page, frag->page_offset,
2556 frag->size, PCI_DMA_TODEVICE);
2561 BUG_ON(tf->control & BMU_OWN);
2564 tf->dma_hi = (u64) map >> 32;
2565 pci_unmap_addr_set(e, mapaddr, map);
2566 pci_unmap_len_set(e, maplen, frag->size);
2568 tf->control = BMU_OWN | BMU_SW | control | frag->size;
2570 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2572 /* Make sure all the descriptors written */
2574 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2577 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2579 if (unlikely(netif_msg_tx_queued(skge)))
2580 printk(KERN_DEBUG "%s: tx queued, slot %td, len %d\n",
2581 dev->name, e - skge->tx_ring.start, skb->len);
2583 skge->tx_ring.to_use = e->next;
2584 if (skge_avail(&skge->tx_ring) <= TX_LOW_WATER) {
2585 pr_debug("%s: transmit queue full\n", dev->name);
2586 netif_stop_queue(dev);
2589 dev->trans_start = jiffies;
2591 return NETDEV_TX_OK;
2595 /* Free resources associated with this reing element */
2596 static void skge_tx_free(struct skge_port *skge, struct skge_element *e,
2599 struct pci_dev *pdev = skge->hw->pdev;
2603 /* skb header vs. fragment */
2604 if (control & BMU_STF)
2605 pci_unmap_single(pdev, pci_unmap_addr(e, mapaddr),
2606 pci_unmap_len(e, maplen),
2609 pci_unmap_page(pdev, pci_unmap_addr(e, mapaddr),
2610 pci_unmap_len(e, maplen),
2613 if (control & BMU_EOF) {
2614 if (unlikely(netif_msg_tx_done(skge)))
2615 printk(KERN_DEBUG PFX "%s: tx done slot %td\n",
2616 skge->netdev->name, e - skge->tx_ring.start);
2618 dev_kfree_skb(e->skb);
2623 /* Free all buffers in transmit ring */
2624 static void skge_tx_clean(struct net_device *dev)
2626 struct skge_port *skge = netdev_priv(dev);
2627 struct skge_element *e;
2629 netif_tx_lock_bh(dev);
2630 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
2631 struct skge_tx_desc *td = e->desc;
2632 skge_tx_free(skge, e, td->control);
2636 skge->tx_ring.to_clean = e;
2637 netif_wake_queue(dev);
2638 netif_tx_unlock_bh(dev);
2641 static void skge_tx_timeout(struct net_device *dev)
2643 struct skge_port *skge = netdev_priv(dev);
2645 if (netif_msg_timer(skge))
2646 printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name);
2648 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
2652 static int skge_change_mtu(struct net_device *dev, int new_mtu)
2656 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2659 if (!netif_running(dev)) {
2675 static void genesis_set_multicast(struct net_device *dev)
2677 struct skge_port *skge = netdev_priv(dev);
2678 struct skge_hw *hw = skge->hw;
2679 int port = skge->port;
2680 int i, count = dev->mc_count;
2681 struct dev_mc_list *list = dev->mc_list;
2685 mode = xm_read32(hw, port, XM_MODE);
2686 mode |= XM_MD_ENA_HASH;
2687 if (dev->flags & IFF_PROMISC)
2688 mode |= XM_MD_ENA_PROM;
2690 mode &= ~XM_MD_ENA_PROM;
2692 if (dev->flags & IFF_ALLMULTI)
2693 memset(filter, 0xff, sizeof(filter));
2695 memset(filter, 0, sizeof(filter));
2696 for (i = 0; list && i < count; i++, list = list->next) {
2698 crc = ether_crc_le(ETH_ALEN, list->dmi_addr);
2700 filter[bit/8] |= 1 << (bit%8);
2704 xm_write32(hw, port, XM_MODE, mode);
2705 xm_outhash(hw, port, XM_HSM, filter);
2708 static void yukon_set_multicast(struct net_device *dev)
2710 struct skge_port *skge = netdev_priv(dev);
2711 struct skge_hw *hw = skge->hw;
2712 int port = skge->port;
2713 struct dev_mc_list *list = dev->mc_list;
2717 memset(filter, 0, sizeof(filter));
2719 reg = gma_read16(hw, port, GM_RX_CTRL);
2720 reg |= GM_RXCR_UCF_ENA;
2722 if (dev->flags & IFF_PROMISC) /* promiscuous */
2723 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2724 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
2725 memset(filter, 0xff, sizeof(filter));
2726 else if (dev->mc_count == 0) /* no multicast */
2727 reg &= ~GM_RXCR_MCF_ENA;
2730 reg |= GM_RXCR_MCF_ENA;
2732 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2733 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2734 filter[bit/8] |= 1 << (bit%8);
2739 gma_write16(hw, port, GM_MC_ADDR_H1,
2740 (u16)filter[0] | ((u16)filter[1] << 8));
2741 gma_write16(hw, port, GM_MC_ADDR_H2,
2742 (u16)filter[2] | ((u16)filter[3] << 8));
2743 gma_write16(hw, port, GM_MC_ADDR_H3,
2744 (u16)filter[4] | ((u16)filter[5] << 8));
2745 gma_write16(hw, port, GM_MC_ADDR_H4,
2746 (u16)filter[6] | ((u16)filter[7] << 8));
2748 gma_write16(hw, port, GM_RX_CTRL, reg);
2751 static inline u16 phy_length(const struct skge_hw *hw, u32 status)
2753 if (hw->chip_id == CHIP_ID_GENESIS)
2754 return status >> XMR_FS_LEN_SHIFT;
2756 return status >> GMR_FS_LEN_SHIFT;
2759 static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
2761 if (hw->chip_id == CHIP_ID_GENESIS)
2762 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
2764 return (status & GMR_FS_ANY_ERR) ||
2765 (status & GMR_FS_RX_OK) == 0;
2769 /* Get receive buffer from descriptor.
2770 * Handles copy of small buffers and reallocation failures
2772 static struct sk_buff *skge_rx_get(struct net_device *dev,
2773 struct skge_element *e,
2774 u32 control, u32 status, u16 csum)
2776 struct skge_port *skge = netdev_priv(dev);
2777 struct sk_buff *skb;
2778 u16 len = control & BMU_BBC;
2780 if (unlikely(netif_msg_rx_status(skge)))
2781 printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n",
2782 dev->name, e - skge->rx_ring.start,
2785 if (len > skge->rx_buf_size)
2788 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
2791 if (bad_phy_status(skge->hw, status))
2794 if (phy_length(skge->hw, status) != len)
2797 if (len < RX_COPY_THRESHOLD) {
2798 skb = netdev_alloc_skb(dev, len + 2);
2802 skb_reserve(skb, 2);
2803 pci_dma_sync_single_for_cpu(skge->hw->pdev,
2804 pci_unmap_addr(e, mapaddr),
2805 len, PCI_DMA_FROMDEVICE);
2806 memcpy(skb->data, e->skb->data, len);
2807 pci_dma_sync_single_for_device(skge->hw->pdev,
2808 pci_unmap_addr(e, mapaddr),
2809 len, PCI_DMA_FROMDEVICE);
2810 skge_rx_reuse(e, skge->rx_buf_size);
2812 struct sk_buff *nskb;
2813 nskb = netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN);
2817 skb_reserve(nskb, NET_IP_ALIGN);
2818 pci_unmap_single(skge->hw->pdev,
2819 pci_unmap_addr(e, mapaddr),
2820 pci_unmap_len(e, maplen),
2821 PCI_DMA_FROMDEVICE);
2823 prefetch(skb->data);
2824 skge_rx_setup(skge, e, nskb, skge->rx_buf_size);
2828 if (skge->rx_csum) {
2830 skb->ip_summed = CHECKSUM_COMPLETE;
2833 skb->protocol = eth_type_trans(skb, dev);
2838 if (netif_msg_rx_err(skge))
2839 printk(KERN_DEBUG PFX "%s: rx err, slot %td control 0x%x status 0x%x\n",
2840 dev->name, e - skge->rx_ring.start,
2843 if (skge->hw->chip_id == CHIP_ID_GENESIS) {
2844 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
2845 skge->net_stats.rx_length_errors++;
2846 if (status & XMR_FS_FRA_ERR)
2847 skge->net_stats.rx_frame_errors++;
2848 if (status & XMR_FS_FCS_ERR)
2849 skge->net_stats.rx_crc_errors++;
2851 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
2852 skge->net_stats.rx_length_errors++;
2853 if (status & GMR_FS_FRAGMENT)
2854 skge->net_stats.rx_frame_errors++;
2855 if (status & GMR_FS_CRC_ERR)
2856 skge->net_stats.rx_crc_errors++;
2860 skge_rx_reuse(e, skge->rx_buf_size);
2864 /* Free all buffers in Tx ring which are no longer owned by device */
2865 static void skge_tx_done(struct net_device *dev)
2867 struct skge_port *skge = netdev_priv(dev);
2868 struct skge_ring *ring = &skge->tx_ring;
2869 struct skge_element *e;
2871 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
2874 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
2875 struct skge_tx_desc *td = e->desc;
2877 if (td->control & BMU_OWN)
2880 skge_tx_free(skge, e, td->control);
2882 skge->tx_ring.to_clean = e;
2884 if (skge_avail(&skge->tx_ring) > TX_LOW_WATER)
2885 netif_wake_queue(dev);
2887 netif_tx_unlock(dev);
2890 static int skge_poll(struct net_device *dev, int *budget)
2892 struct skge_port *skge = netdev_priv(dev);
2893 struct skge_hw *hw = skge->hw;
2894 struct skge_ring *ring = &skge->rx_ring;
2895 struct skge_element *e;
2896 int to_do = min(dev->quota, *budget);
2901 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
2903 for (e = ring->to_clean; prefetch(e->next), work_done < to_do; e = e->next) {
2904 struct skge_rx_desc *rd = e->desc;
2905 struct sk_buff *skb;
2909 control = rd->control;
2910 if (control & BMU_OWN)
2913 skb = skge_rx_get(dev, e, control, rd->status, rd->csum2);
2915 dev->last_rx = jiffies;
2916 netif_receive_skb(skb);
2923 /* restart receiver */
2925 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START);
2927 *budget -= work_done;
2928 dev->quota -= work_done;
2930 if (work_done >= to_do)
2931 return 1; /* not done */
2933 spin_lock_irq(&hw->hw_lock);
2934 __netif_rx_complete(dev);
2935 hw->intr_mask |= irqmask[skge->port];
2936 skge_write32(hw, B0_IMSK, hw->intr_mask);
2937 skge_read32(hw, B0_IMSK);
2938 spin_unlock_irq(&hw->hw_lock);
2943 /* Parity errors seem to happen when Genesis is connected to a switch
2944 * with no other ports present. Heartbeat error??
2946 static void skge_mac_parity(struct skge_hw *hw, int port)
2948 struct net_device *dev = hw->dev[port];
2951 struct skge_port *skge = netdev_priv(dev);
2952 ++skge->net_stats.tx_heartbeat_errors;
2955 if (hw->chip_id == CHIP_ID_GENESIS)
2956 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
2959 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
2960 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
2961 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
2962 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
2965 static void skge_mac_intr(struct skge_hw *hw, int port)
2967 if (hw->chip_id == CHIP_ID_GENESIS)
2968 genesis_mac_intr(hw, port);
2970 yukon_mac_intr(hw, port);
2973 /* Handle device specific framing and timeout interrupts */
2974 static void skge_error_irq(struct skge_hw *hw)
2976 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2978 if (hw->chip_id == CHIP_ID_GENESIS) {
2979 /* clear xmac errors */
2980 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
2981 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);
2982 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
2983 skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);
2985 /* Timestamp (unused) overflow */
2986 if (hwstatus & IS_IRQ_TIST_OV)
2987 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2990 if (hwstatus & IS_RAM_RD_PAR) {
2991 printk(KERN_ERR PFX "Ram read data parity error\n");
2992 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
2995 if (hwstatus & IS_RAM_WR_PAR) {
2996 printk(KERN_ERR PFX "Ram write data parity error\n");
2997 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
3000 if (hwstatus & IS_M1_PAR_ERR)
3001 skge_mac_parity(hw, 0);
3003 if (hwstatus & IS_M2_PAR_ERR)
3004 skge_mac_parity(hw, 1);
3006 if (hwstatus & IS_R1_PAR_ERR) {
3007 printk(KERN_ERR PFX "%s: receive queue parity error\n",
3009 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
3012 if (hwstatus & IS_R2_PAR_ERR) {
3013 printk(KERN_ERR PFX "%s: receive queue parity error\n",
3015 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
3018 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
3019 u16 pci_status, pci_cmd;
3021 pci_read_config_word(hw->pdev, PCI_COMMAND, &pci_cmd);
3022 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status);
3024 printk(KERN_ERR PFX "%s: PCI error cmd=%#x status=%#x\n",
3025 pci_name(hw->pdev), pci_cmd, pci_status);
3027 /* Write the error bits back to clear them. */
3028 pci_status &= PCI_STATUS_ERROR_BITS;
3029 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3030 pci_write_config_word(hw->pdev, PCI_COMMAND,
3031 pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
3032 pci_write_config_word(hw->pdev, PCI_STATUS, pci_status);
3033 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3035 /* if error still set then just ignore it */
3036 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3037 if (hwstatus & IS_IRQ_STAT) {
3038 printk(KERN_INFO PFX "unable to clear error (so ignoring them)\n");
3039 hw->intr_mask &= ~IS_HW_ERR;
3045 * Interrupt from PHY are handled in work queue
3046 * because accessing phy registers requires spin wait which might
3047 * cause excess interrupt latency.
3049 static void skge_extirq(void *arg)
3051 struct skge_hw *hw = arg;
3054 mutex_lock(&hw->phy_mutex);
3055 for (port = 0; port < hw->ports; port++) {
3056 struct net_device *dev = hw->dev[port];
3057 struct skge_port *skge = netdev_priv(dev);
3059 if (netif_running(dev)) {
3060 if (hw->chip_id != CHIP_ID_GENESIS)
3061 yukon_phy_intr(skge);
3062 else if (hw->phy_type == SK_PHY_BCOM)
3063 bcom_phy_intr(skge);
3066 mutex_unlock(&hw->phy_mutex);
3068 spin_lock_irq(&hw->hw_lock);
3069 hw->intr_mask |= IS_EXT_REG;
3070 skge_write32(hw, B0_IMSK, hw->intr_mask);
3071 skge_read32(hw, B0_IMSK);
3072 spin_unlock_irq(&hw->hw_lock);
3075 static irqreturn_t skge_intr(int irq, void *dev_id)
3077 struct skge_hw *hw = dev_id;
3081 spin_lock(&hw->hw_lock);
3082 /* Reading this register masks IRQ */
3083 status = skge_read32(hw, B0_SP_ISRC);
3084 if (status == 0 || status == ~0)
3088 status &= hw->intr_mask;
3089 if (status & IS_EXT_REG) {
3090 hw->intr_mask &= ~IS_EXT_REG;
3091 schedule_work(&hw->phy_work);
3094 if (status & (IS_XA1_F|IS_R1_F)) {
3095 hw->intr_mask &= ~(IS_XA1_F|IS_R1_F);
3096 netif_rx_schedule(hw->dev[0]);
3099 if (status & IS_PA_TO_TX1)
3100 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
3102 if (status & IS_PA_TO_RX1) {
3103 struct skge_port *skge = netdev_priv(hw->dev[0]);
3105 ++skge->net_stats.rx_over_errors;
3106 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
3110 if (status & IS_MAC1)
3111 skge_mac_intr(hw, 0);
3114 if (status & (IS_XA2_F|IS_R2_F)) {
3115 hw->intr_mask &= ~(IS_XA2_F|IS_R2_F);
3116 netif_rx_schedule(hw->dev[1]);
3119 if (status & IS_PA_TO_RX2) {
3120 struct skge_port *skge = netdev_priv(hw->dev[1]);
3121 ++skge->net_stats.rx_over_errors;
3122 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
3125 if (status & IS_PA_TO_TX2)
3126 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
3128 if (status & IS_MAC2)
3129 skge_mac_intr(hw, 1);
3132 if (status & IS_HW_ERR)
3135 skge_write32(hw, B0_IMSK, hw->intr_mask);
3136 skge_read32(hw, B0_IMSK);
3138 spin_unlock(&hw->hw_lock);
3140 return IRQ_RETVAL(handled);
3143 #ifdef CONFIG_NET_POLL_CONTROLLER
3144 static void skge_netpoll(struct net_device *dev)
3146 struct skge_port *skge = netdev_priv(dev);
3148 disable_irq(dev->irq);
3149 skge_intr(dev->irq, skge->hw);
3150 enable_irq(dev->irq);
3154 static int skge_set_mac_address(struct net_device *dev, void *p)
3156 struct skge_port *skge = netdev_priv(dev);
3157 struct skge_hw *hw = skge->hw;
3158 unsigned port = skge->port;
3159 const struct sockaddr *addr = p;
3161 if (!is_valid_ether_addr(addr->sa_data))
3162 return -EADDRNOTAVAIL;
3164 mutex_lock(&hw->phy_mutex);
3165 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3166 memcpy_toio(hw->regs + B2_MAC_1 + port*8,
3167 dev->dev_addr, ETH_ALEN);
3168 memcpy_toio(hw->regs + B2_MAC_2 + port*8,
3169 dev->dev_addr, ETH_ALEN);
3171 if (hw->chip_id == CHIP_ID_GENESIS)
3172 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
3174 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3175 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3177 mutex_unlock(&hw->phy_mutex);
3182 static const struct {
3186 { CHIP_ID_GENESIS, "Genesis" },
3187 { CHIP_ID_YUKON, "Yukon" },
3188 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
3189 { CHIP_ID_YUKON_LP, "Yukon-LP"},
3192 static const char *skge_board_name(const struct skge_hw *hw)
3195 static char buf[16];
3197 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
3198 if (skge_chips[i].id == hw->chip_id)
3199 return skge_chips[i].name;
3201 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
3207 * Setup the board data structure, but don't bring up
3210 static int skge_reset(struct skge_hw *hw)
3213 u16 ctst, pci_status;
3214 u8 t8, mac_cfg, pmd_type;
3217 ctst = skge_read16(hw, B0_CTST);
3220 skge_write8(hw, B0_CTST, CS_RST_SET);
3221 skge_write8(hw, B0_CTST, CS_RST_CLR);
3223 /* clear PCI errors, if any */
3224 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3225 skge_write8(hw, B2_TST_CTRL2, 0);
3227 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status);
3228 pci_write_config_word(hw->pdev, PCI_STATUS,
3229 pci_status | PCI_STATUS_ERROR_BITS);
3230 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3231 skge_write8(hw, B0_CTST, CS_MRST_CLR);
3233 /* restore CLK_RUN bits (for Yukon-Lite) */
3234 skge_write16(hw, B0_CTST,
3235 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
3237 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
3238 hw->phy_type = skge_read8(hw, B2_E_1) & 0xf;
3239 pmd_type = skge_read8(hw, B2_PMD_TYP);
3240 hw->copper = (pmd_type == 'T' || pmd_type == '1');
3242 switch (hw->chip_id) {
3243 case CHIP_ID_GENESIS:
3244 switch (hw->phy_type) {
3246 hw->phy_addr = PHY_ADDR_XMAC;
3249 hw->phy_addr = PHY_ADDR_BCOM;
3252 printk(KERN_ERR PFX "%s: unsupported phy type 0x%x\n",
3253 pci_name(hw->pdev), hw->phy_type);
3259 case CHIP_ID_YUKON_LITE:
3260 case CHIP_ID_YUKON_LP:
3261 if (hw->phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
3264 hw->phy_addr = PHY_ADDR_MARV;
3268 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
3269 pci_name(hw->pdev), hw->chip_id);
3273 mac_cfg = skge_read8(hw, B2_MAC_CFG);
3274 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
3275 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
3277 /* read the adapters RAM size */
3278 t8 = skge_read8(hw, B2_E_0);
3279 if (hw->chip_id == CHIP_ID_GENESIS) {
3281 /* special case: 4 x 64k x 36, offset = 0x80000 */
3282 hw->ram_size = 0x100000;
3283 hw->ram_offset = 0x80000;
3285 hw->ram_size = t8 * 512;
3288 hw->ram_size = 0x20000;
3290 hw->ram_size = t8 * 4096;
3292 hw->intr_mask = IS_HW_ERR | IS_PORT_1;
3294 hw->intr_mask |= IS_PORT_2;
3296 if (!(hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC))
3297 hw->intr_mask |= IS_EXT_REG;
3299 if (hw->chip_id == CHIP_ID_GENESIS)
3302 /* switch power to VCC (WA for VAUX problem) */
3303 skge_write8(hw, B0_POWER_CTRL,
3304 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
3306 /* avoid boards with stuck Hardware error bits */
3307 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
3308 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
3309 printk(KERN_WARNING PFX "stuck hardware sensor bit\n");
3310 hw->intr_mask &= ~IS_HW_ERR;
3313 /* Clear PHY COMA */
3314 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3315 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, ®);
3316 reg &= ~PCI_PHY_COMA;
3317 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);
3318 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3321 for (i = 0; i < hw->ports; i++) {
3322 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3323 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
3327 /* turn off hardware timer (unused) */
3328 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
3329 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3330 skge_write8(hw, B0_LED, LED_STAT_ON);
3332 /* enable the Tx Arbiters */
3333 for (i = 0; i < hw->ports; i++)
3334 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3336 /* Initialize ram interface */
3337 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
3339 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
3340 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
3341 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
3342 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
3343 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
3344 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
3345 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
3346 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
3347 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
3348 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
3349 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
3350 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
3352 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
3354 /* Set interrupt moderation for Transmit only
3355 * Receive interrupts avoided by NAPI
3357 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3358 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3359 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3361 skge_write32(hw, B0_IMSK, hw->intr_mask);
3363 mutex_lock(&hw->phy_mutex);
3364 for (i = 0; i < hw->ports; i++) {
3365 if (hw->chip_id == CHIP_ID_GENESIS)
3366 genesis_reset(hw, i);
3370 mutex_unlock(&hw->phy_mutex);
3375 /* Initialize network device */
3376 static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3379 struct skge_port *skge;
3380 struct net_device *dev = alloc_etherdev(sizeof(*skge));
3383 printk(KERN_ERR "skge etherdev alloc failed");
3387 SET_MODULE_OWNER(dev);
3388 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3389 dev->open = skge_up;
3390 dev->stop = skge_down;
3391 dev->do_ioctl = skge_ioctl;
3392 dev->hard_start_xmit = skge_xmit_frame;
3393 dev->get_stats = skge_get_stats;
3394 if (hw->chip_id == CHIP_ID_GENESIS)
3395 dev->set_multicast_list = genesis_set_multicast;
3397 dev->set_multicast_list = yukon_set_multicast;
3399 dev->set_mac_address = skge_set_mac_address;
3400 dev->change_mtu = skge_change_mtu;
3401 SET_ETHTOOL_OPS(dev, &skge_ethtool_ops);
3402 dev->tx_timeout = skge_tx_timeout;
3403 dev->watchdog_timeo = TX_WATCHDOG;
3404 dev->poll = skge_poll;
3405 dev->weight = NAPI_WEIGHT;
3406 #ifdef CONFIG_NET_POLL_CONTROLLER
3407 dev->poll_controller = skge_netpoll;
3409 dev->irq = hw->pdev->irq;
3412 dev->features |= NETIF_F_HIGHDMA;
3414 skge = netdev_priv(dev);
3417 skge->msg_enable = netif_msg_init(debug, default_msg);
3418 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3419 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3421 /* Auto speed and flow control */
3422 skge->autoneg = AUTONEG_ENABLE;
3423 skge->flow_control = FLOW_MODE_SYMMETRIC;
3426 skge->advertising = skge_supported_modes(hw);
3428 hw->dev[port] = dev;
3432 /* Only used for Genesis XMAC */
3433 INIT_WORK(&skge->link_thread, xm_link_timer, dev);
3435 if (hw->chip_id != CHIP_ID_GENESIS) {
3436 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3440 /* read the mac address */
3441 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
3442 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3444 /* device is off until link detection */
3445 netif_carrier_off(dev);
3446 netif_stop_queue(dev);
3451 static void __devinit skge_show_addr(struct net_device *dev)
3453 const struct skge_port *skge = netdev_priv(dev);
3455 if (netif_msg_probe(skge))
3456 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3458 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3459 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3462 static int __devinit skge_probe(struct pci_dev *pdev,
3463 const struct pci_device_id *ent)
3465 struct net_device *dev, *dev1;
3467 int err, using_dac = 0;
3469 err = pci_enable_device(pdev);
3471 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3476 err = pci_request_regions(pdev, DRV_NAME);
3478 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3480 goto err_out_disable_pdev;
3483 pci_set_master(pdev);
3485 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3487 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3488 } else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
3490 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3494 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3496 goto err_out_free_regions;
3500 /* byte swap descriptors in hardware */
3504 pci_read_config_dword(pdev, PCI_DEV_REG2, ®);
3505 reg |= PCI_REV_DESC;
3506 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3511 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
3513 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3515 goto err_out_free_regions;
3519 mutex_init(&hw->phy_mutex);
3520 INIT_WORK(&hw->phy_work, skge_extirq, hw);
3521 spin_lock_init(&hw->hw_lock);
3523 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3525 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3527 goto err_out_free_hw;
3530 err = skge_reset(hw);
3532 goto err_out_iounmap;
3534 printk(KERN_INFO PFX DRV_VERSION " addr 0x%llx irq %d chip %s rev %d\n",
3535 (unsigned long long)pci_resource_start(pdev, 0), pdev->irq,
3536 skge_board_name(hw), hw->chip_rev);
3538 dev = skge_devinit(hw, 0, using_dac);
3540 goto err_out_led_off;
3542 if (!is_valid_ether_addr(dev->dev_addr)) {
3543 printk(KERN_ERR PFX "%s: bad (zero?) ethernet address in rom\n",
3546 goto err_out_free_netdev;
3549 err = register_netdev(dev);
3551 printk(KERN_ERR PFX "%s: cannot register net device\n",
3553 goto err_out_free_netdev;
3556 err = request_irq(pdev->irq, skge_intr, IRQF_SHARED, dev->name, hw);
3558 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3559 dev->name, pdev->irq);
3560 goto err_out_unregister;
3562 skge_show_addr(dev);
3564 if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) {
3565 if (register_netdev(dev1) == 0)
3566 skge_show_addr(dev1);
3568 /* Failure to register second port need not be fatal */
3569 printk(KERN_WARNING PFX "register of second port failed\n");
3574 pci_set_drvdata(pdev, hw);
3579 unregister_netdev(dev);
3580 err_out_free_netdev:
3583 skge_write16(hw, B0_LED, LED_STAT_OFF);
3588 err_out_free_regions:
3589 pci_release_regions(pdev);
3590 err_out_disable_pdev:
3591 pci_disable_device(pdev);
3592 pci_set_drvdata(pdev, NULL);
3597 static void __devexit skge_remove(struct pci_dev *pdev)
3599 struct skge_hw *hw = pci_get_drvdata(pdev);
3600 struct net_device *dev0, *dev1;
3605 if ((dev1 = hw->dev[1]))
3606 unregister_netdev(dev1);
3608 unregister_netdev(dev0);
3610 spin_lock_irq(&hw->hw_lock);
3612 skge_write32(hw, B0_IMSK, 0);
3613 skge_read32(hw, B0_IMSK);
3614 spin_unlock_irq(&hw->hw_lock);
3616 skge_write16(hw, B0_LED, LED_STAT_OFF);
3617 skge_write8(hw, B0_CTST, CS_RST_SET);
3619 flush_scheduled_work();
3621 free_irq(pdev->irq, hw);
3622 pci_release_regions(pdev);
3623 pci_disable_device(pdev);
3630 pci_set_drvdata(pdev, NULL);
3634 static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
3636 struct skge_hw *hw = pci_get_drvdata(pdev);
3639 pci_save_state(pdev);
3640 for (i = 0; i < hw->ports; i++) {
3641 struct net_device *dev = hw->dev[i];
3643 if (netif_running(dev)) {
3644 struct skge_port *skge = netdev_priv(dev);
3646 netif_carrier_off(dev);
3648 netif_stop_queue(dev);
3653 netif_device_detach(dev);
3656 skge_write32(hw, B0_IMSK, 0);
3657 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
3658 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3663 static int skge_resume(struct pci_dev *pdev)
3665 struct skge_hw *hw = pci_get_drvdata(pdev);
3668 pci_set_power_state(pdev, PCI_D0);
3669 pci_restore_state(pdev);
3670 pci_enable_wake(pdev, PCI_D0, 0);
3672 err = skge_reset(hw);
3676 for (i = 0; i < hw->ports; i++) {
3677 struct net_device *dev = hw->dev[i];
3679 netif_device_attach(dev);
3680 if (netif_running(dev)) {
3684 printk(KERN_ERR PFX "%s: could not up: %d\n",
3696 static struct pci_driver skge_driver = {
3698 .id_table = skge_id_table,
3699 .probe = skge_probe,
3700 .remove = __devexit_p(skge_remove),
3702 .suspend = skge_suspend,
3703 .resume = skge_resume,
3707 static int __init skge_init_module(void)
3709 return pci_register_driver(&skge_driver);
3712 static void __exit skge_cleanup_module(void)
3714 pci_unregister_driver(&skge_driver);
3717 module_init(skge_init_module);
3718 module_exit(skge_cleanup_module);