2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
10 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/moduleparam.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/pci.h>
34 #include <linux/if_vlan.h>
36 #include <linux/delay.h>
37 #include <linux/crc32.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/mii.h>
44 #define DRV_NAME "skge"
45 #define DRV_VERSION "1.11"
46 #define PFX DRV_NAME " "
48 #define DEFAULT_TX_RING_SIZE 128
49 #define DEFAULT_RX_RING_SIZE 512
50 #define MAX_TX_RING_SIZE 1024
51 #define TX_LOW_WATER (MAX_SKB_FRAGS + 1)
52 #define MAX_RX_RING_SIZE 4096
53 #define RX_COPY_THRESHOLD 128
54 #define RX_BUF_SIZE 1536
55 #define PHY_RETRIES 1000
56 #define ETH_JUMBO_MTU 9000
57 #define TX_WATCHDOG (5 * HZ)
58 #define NAPI_WEIGHT 64
62 #define SKGE_EEPROM_MAGIC 0x9933aabb
65 MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
66 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
67 MODULE_LICENSE("GPL");
68 MODULE_VERSION(DRV_VERSION);
70 static const u32 default_msg
71 = NETIF_MSG_DRV| NETIF_MSG_PROBE| NETIF_MSG_LINK
72 | NETIF_MSG_IFUP| NETIF_MSG_IFDOWN;
74 static int debug = -1; /* defaults above */
75 module_param(debug, int, 0);
76 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
78 static const struct pci_device_id skge_id_table[] = {
79 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },
80 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },
81 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },
82 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },
83 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T) },
84 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) }, /* DGE-530T */
85 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },
86 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
87 { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },
88 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },
89 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015 },
92 MODULE_DEVICE_TABLE(pci, skge_id_table);
94 static int skge_up(struct net_device *dev);
95 static int skge_down(struct net_device *dev);
96 static void skge_phy_reset(struct skge_port *skge);
97 static void skge_tx_clean(struct net_device *dev);
98 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
99 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
100 static void genesis_get_stats(struct skge_port *skge, u64 *data);
101 static void yukon_get_stats(struct skge_port *skge, u64 *data);
102 static void yukon_init(struct skge_hw *hw, int port);
103 static void genesis_mac_init(struct skge_hw *hw, int port);
104 static void genesis_link_up(struct skge_port *skge);
106 /* Avoid conditionals by using array */
107 static const int txqaddr[] = { Q_XA1, Q_XA2 };
108 static const int rxqaddr[] = { Q_R1, Q_R2 };
109 static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
110 static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
111 static const u32 napimask[] = { IS_R1_F|IS_XA1_F, IS_R2_F|IS_XA2_F };
112 static const u32 portmask[] = { IS_PORT_1, IS_PORT_2 };
114 static int skge_get_regs_len(struct net_device *dev)
120 * Returns copy of whole control register region
121 * Note: skip RAM address register because accessing it will
124 static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
127 const struct skge_port *skge = netdev_priv(dev);
128 const void __iomem *io = skge->hw->regs;
131 memset(p, 0, regs->len);
132 memcpy_fromio(p, io, B3_RAM_ADDR);
134 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,
135 regs->len - B3_RI_WTO_R1);
138 /* Wake on Lan only supported on Yukon chips with rev 1 or above */
139 static u32 wol_supported(const struct skge_hw *hw)
141 if (hw->chip_id == CHIP_ID_GENESIS)
144 if (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
147 return WAKE_MAGIC | WAKE_PHY;
150 static u32 pci_wake_enabled(struct pci_dev *dev)
152 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
155 /* If device doesn't support PM Capabilities, but request is to disable
156 * wake events, it's a nop; otherwise fail */
160 pci_read_config_word(dev, pm + PCI_PM_PMC, &value);
162 value &= PCI_PM_CAP_PME_MASK;
163 value >>= ffs(PCI_PM_CAP_PME_MASK) - 1; /* First bit of mask */
168 static void skge_wol_init(struct skge_port *skge)
170 struct skge_hw *hw = skge->hw;
171 int port = skge->port;
174 skge_write16(hw, B0_CTST, CS_RST_CLR);
175 skge_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
178 skge_write8(hw, B0_POWER_CTRL,
179 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF);
181 /* WA code for COMA mode -- clear PHY reset */
182 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
183 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
184 u32 reg = skge_read32(hw, B2_GP_IO);
187 skge_write32(hw, B2_GP_IO, reg);
190 skge_write32(hw, SK_REG(port, GPHY_CTRL),
192 GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
193 GPC_ANEG_1 | GPC_RST_SET);
195 skge_write32(hw, SK_REG(port, GPHY_CTRL),
197 GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
198 GPC_ANEG_1 | GPC_RST_CLR);
200 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
202 /* Force to 10/100 skge_reset will re-enable on resume */
203 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
204 PHY_AN_100FULL | PHY_AN_100HALF |
205 PHY_AN_10FULL | PHY_AN_10HALF| PHY_AN_CSMA);
207 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, 0);
208 gm_phy_write(hw, port, PHY_MARV_CTRL,
209 PHY_CT_RESET | PHY_CT_SPS_LSB | PHY_CT_ANE |
210 PHY_CT_RE_CFG | PHY_CT_DUP_MD);
213 /* Set GMAC to no flow control and auto update for speed/duplex */
214 gma_write16(hw, port, GM_GP_CTRL,
215 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
216 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
218 /* Set WOL address */
219 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
220 skge->netdev->dev_addr, ETH_ALEN);
222 /* Turn on appropriate WOL control bits */
223 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
225 if (skge->wol & WAKE_PHY)
226 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
228 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
230 if (skge->wol & WAKE_MAGIC)
231 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
233 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
235 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
236 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
239 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
242 static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
244 struct skge_port *skge = netdev_priv(dev);
246 wol->supported = wol_supported(skge->hw);
247 wol->wolopts = skge->wol;
250 static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
252 struct skge_port *skge = netdev_priv(dev);
253 struct skge_hw *hw = skge->hw;
255 if (wol->wolopts & ~wol_supported(hw))
258 skge->wol = wol->wolopts;
262 /* Determine supported/advertised modes based on hardware.
263 * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
265 static u32 skge_supported_modes(const struct skge_hw *hw)
270 supported = SUPPORTED_10baseT_Half
271 | SUPPORTED_10baseT_Full
272 | SUPPORTED_100baseT_Half
273 | SUPPORTED_100baseT_Full
274 | SUPPORTED_1000baseT_Half
275 | SUPPORTED_1000baseT_Full
276 | SUPPORTED_Autoneg| SUPPORTED_TP;
278 if (hw->chip_id == CHIP_ID_GENESIS)
279 supported &= ~(SUPPORTED_10baseT_Half
280 | SUPPORTED_10baseT_Full
281 | SUPPORTED_100baseT_Half
282 | SUPPORTED_100baseT_Full);
284 else if (hw->chip_id == CHIP_ID_YUKON)
285 supported &= ~SUPPORTED_1000baseT_Half;
287 supported = SUPPORTED_1000baseT_Full | SUPPORTED_1000baseT_Half
288 | SUPPORTED_FIBRE | SUPPORTED_Autoneg;
293 static int skge_get_settings(struct net_device *dev,
294 struct ethtool_cmd *ecmd)
296 struct skge_port *skge = netdev_priv(dev);
297 struct skge_hw *hw = skge->hw;
299 ecmd->transceiver = XCVR_INTERNAL;
300 ecmd->supported = skge_supported_modes(hw);
303 ecmd->port = PORT_TP;
304 ecmd->phy_address = hw->phy_addr;
306 ecmd->port = PORT_FIBRE;
308 ecmd->advertising = skge->advertising;
309 ecmd->autoneg = skge->autoneg;
310 ecmd->speed = skge->speed;
311 ecmd->duplex = skge->duplex;
315 static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
317 struct skge_port *skge = netdev_priv(dev);
318 const struct skge_hw *hw = skge->hw;
319 u32 supported = skge_supported_modes(hw);
321 if (ecmd->autoneg == AUTONEG_ENABLE) {
322 ecmd->advertising = supported;
328 switch (ecmd->speed) {
330 if (ecmd->duplex == DUPLEX_FULL)
331 setting = SUPPORTED_1000baseT_Full;
332 else if (ecmd->duplex == DUPLEX_HALF)
333 setting = SUPPORTED_1000baseT_Half;
338 if (ecmd->duplex == DUPLEX_FULL)
339 setting = SUPPORTED_100baseT_Full;
340 else if (ecmd->duplex == DUPLEX_HALF)
341 setting = SUPPORTED_100baseT_Half;
347 if (ecmd->duplex == DUPLEX_FULL)
348 setting = SUPPORTED_10baseT_Full;
349 else if (ecmd->duplex == DUPLEX_HALF)
350 setting = SUPPORTED_10baseT_Half;
358 if ((setting & supported) == 0)
361 skge->speed = ecmd->speed;
362 skge->duplex = ecmd->duplex;
365 skge->autoneg = ecmd->autoneg;
366 skge->advertising = ecmd->advertising;
368 if (netif_running(dev))
369 skge_phy_reset(skge);
374 static void skge_get_drvinfo(struct net_device *dev,
375 struct ethtool_drvinfo *info)
377 struct skge_port *skge = netdev_priv(dev);
379 strcpy(info->driver, DRV_NAME);
380 strcpy(info->version, DRV_VERSION);
381 strcpy(info->fw_version, "N/A");
382 strcpy(info->bus_info, pci_name(skge->hw->pdev));
385 static const struct skge_stat {
386 char name[ETH_GSTRING_LEN];
390 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
391 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
393 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
394 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
395 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
396 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
397 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
398 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
399 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
400 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
402 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
403 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
404 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
405 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
406 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
407 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
409 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
410 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
411 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
412 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
413 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
416 static int skge_get_sset_count(struct net_device *dev, int sset)
420 return ARRAY_SIZE(skge_stats);
426 static void skge_get_ethtool_stats(struct net_device *dev,
427 struct ethtool_stats *stats, u64 *data)
429 struct skge_port *skge = netdev_priv(dev);
431 if (skge->hw->chip_id == CHIP_ID_GENESIS)
432 genesis_get_stats(skge, data);
434 yukon_get_stats(skge, data);
437 /* Use hardware MIB variables for critical path statistics and
438 * transmit feedback not reported at interrupt.
439 * Other errors are accounted for in interrupt handler.
441 static struct net_device_stats *skge_get_stats(struct net_device *dev)
443 struct skge_port *skge = netdev_priv(dev);
444 u64 data[ARRAY_SIZE(skge_stats)];
446 if (skge->hw->chip_id == CHIP_ID_GENESIS)
447 genesis_get_stats(skge, data);
449 yukon_get_stats(skge, data);
451 dev->stats.tx_bytes = data[0];
452 dev->stats.rx_bytes = data[1];
453 dev->stats.tx_packets = data[2] + data[4] + data[6];
454 dev->stats.rx_packets = data[3] + data[5] + data[7];
455 dev->stats.multicast = data[3] + data[5];
456 dev->stats.collisions = data[10];
457 dev->stats.tx_aborted_errors = data[12];
462 static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
468 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
469 memcpy(data + i * ETH_GSTRING_LEN,
470 skge_stats[i].name, ETH_GSTRING_LEN);
475 static void skge_get_ring_param(struct net_device *dev,
476 struct ethtool_ringparam *p)
478 struct skge_port *skge = netdev_priv(dev);
480 p->rx_max_pending = MAX_RX_RING_SIZE;
481 p->tx_max_pending = MAX_TX_RING_SIZE;
482 p->rx_mini_max_pending = 0;
483 p->rx_jumbo_max_pending = 0;
485 p->rx_pending = skge->rx_ring.count;
486 p->tx_pending = skge->tx_ring.count;
487 p->rx_mini_pending = 0;
488 p->rx_jumbo_pending = 0;
491 static int skge_set_ring_param(struct net_device *dev,
492 struct ethtool_ringparam *p)
494 struct skge_port *skge = netdev_priv(dev);
497 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
498 p->tx_pending < TX_LOW_WATER || p->tx_pending > MAX_TX_RING_SIZE)
501 skge->rx_ring.count = p->rx_pending;
502 skge->tx_ring.count = p->tx_pending;
504 if (netif_running(dev)) {
514 static u32 skge_get_msglevel(struct net_device *netdev)
516 struct skge_port *skge = netdev_priv(netdev);
517 return skge->msg_enable;
520 static void skge_set_msglevel(struct net_device *netdev, u32 value)
522 struct skge_port *skge = netdev_priv(netdev);
523 skge->msg_enable = value;
526 static int skge_nway_reset(struct net_device *dev)
528 struct skge_port *skge = netdev_priv(dev);
530 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
533 skge_phy_reset(skge);
537 static int skge_set_sg(struct net_device *dev, u32 data)
539 struct skge_port *skge = netdev_priv(dev);
540 struct skge_hw *hw = skge->hw;
542 if (hw->chip_id == CHIP_ID_GENESIS && data)
544 return ethtool_op_set_sg(dev, data);
547 static int skge_set_tx_csum(struct net_device *dev, u32 data)
549 struct skge_port *skge = netdev_priv(dev);
550 struct skge_hw *hw = skge->hw;
552 if (hw->chip_id == CHIP_ID_GENESIS && data)
555 return ethtool_op_set_tx_csum(dev, data);
558 static u32 skge_get_rx_csum(struct net_device *dev)
560 struct skge_port *skge = netdev_priv(dev);
562 return skge->rx_csum;
565 /* Only Yukon supports checksum offload. */
566 static int skge_set_rx_csum(struct net_device *dev, u32 data)
568 struct skge_port *skge = netdev_priv(dev);
570 if (skge->hw->chip_id == CHIP_ID_GENESIS && data)
573 skge->rx_csum = data;
577 static void skge_get_pauseparam(struct net_device *dev,
578 struct ethtool_pauseparam *ecmd)
580 struct skge_port *skge = netdev_priv(dev);
582 ecmd->rx_pause = (skge->flow_control == FLOW_MODE_SYMMETRIC)
583 || (skge->flow_control == FLOW_MODE_SYM_OR_REM);
584 ecmd->tx_pause = ecmd->rx_pause || (skge->flow_control == FLOW_MODE_LOC_SEND);
586 ecmd->autoneg = ecmd->rx_pause || ecmd->tx_pause;
589 static int skge_set_pauseparam(struct net_device *dev,
590 struct ethtool_pauseparam *ecmd)
592 struct skge_port *skge = netdev_priv(dev);
593 struct ethtool_pauseparam old;
595 skge_get_pauseparam(dev, &old);
597 if (ecmd->autoneg != old.autoneg)
598 skge->flow_control = ecmd->autoneg ? FLOW_MODE_NONE : FLOW_MODE_SYMMETRIC;
600 if (ecmd->rx_pause && ecmd->tx_pause)
601 skge->flow_control = FLOW_MODE_SYMMETRIC;
602 else if (ecmd->rx_pause && !ecmd->tx_pause)
603 skge->flow_control = FLOW_MODE_SYM_OR_REM;
604 else if (!ecmd->rx_pause && ecmd->tx_pause)
605 skge->flow_control = FLOW_MODE_LOC_SEND;
607 skge->flow_control = FLOW_MODE_NONE;
610 if (netif_running(dev))
611 skge_phy_reset(skge);
616 /* Chip internal frequency for clock calculations */
617 static inline u32 hwkhz(const struct skge_hw *hw)
619 return (hw->chip_id == CHIP_ID_GENESIS) ? 53125 : 78125;
622 /* Chip HZ to microseconds */
623 static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
625 return (ticks * 1000) / hwkhz(hw);
628 /* Microseconds to chip HZ */
629 static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
631 return hwkhz(hw) * usec / 1000;
634 static int skge_get_coalesce(struct net_device *dev,
635 struct ethtool_coalesce *ecmd)
637 struct skge_port *skge = netdev_priv(dev);
638 struct skge_hw *hw = skge->hw;
639 int port = skge->port;
641 ecmd->rx_coalesce_usecs = 0;
642 ecmd->tx_coalesce_usecs = 0;
644 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
645 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
646 u32 msk = skge_read32(hw, B2_IRQM_MSK);
648 if (msk & rxirqmask[port])
649 ecmd->rx_coalesce_usecs = delay;
650 if (msk & txirqmask[port])
651 ecmd->tx_coalesce_usecs = delay;
657 /* Note: interrupt timer is per board, but can turn on/off per port */
658 static int skge_set_coalesce(struct net_device *dev,
659 struct ethtool_coalesce *ecmd)
661 struct skge_port *skge = netdev_priv(dev);
662 struct skge_hw *hw = skge->hw;
663 int port = skge->port;
664 u32 msk = skge_read32(hw, B2_IRQM_MSK);
667 if (ecmd->rx_coalesce_usecs == 0)
668 msk &= ~rxirqmask[port];
669 else if (ecmd->rx_coalesce_usecs < 25 ||
670 ecmd->rx_coalesce_usecs > 33333)
673 msk |= rxirqmask[port];
674 delay = ecmd->rx_coalesce_usecs;
677 if (ecmd->tx_coalesce_usecs == 0)
678 msk &= ~txirqmask[port];
679 else if (ecmd->tx_coalesce_usecs < 25 ||
680 ecmd->tx_coalesce_usecs > 33333)
683 msk |= txirqmask[port];
684 delay = min(delay, ecmd->rx_coalesce_usecs);
687 skge_write32(hw, B2_IRQM_MSK, msk);
689 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
691 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
692 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
697 enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
698 static void skge_led(struct skge_port *skge, enum led_mode mode)
700 struct skge_hw *hw = skge->hw;
701 int port = skge->port;
703 spin_lock_bh(&hw->phy_lock);
704 if (hw->chip_id == CHIP_ID_GENESIS) {
707 if (hw->phy_type == SK_PHY_BCOM)
708 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
710 skge_write32(hw, SK_REG(port, TX_LED_VAL), 0);
711 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_T_OFF);
713 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
714 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
715 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
719 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
720 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
722 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
723 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
728 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
729 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
730 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
732 if (hw->phy_type == SK_PHY_BCOM)
733 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
735 skge_write8(hw, SK_REG(port, TX_LED_TST), LED_T_ON);
736 skge_write32(hw, SK_REG(port, TX_LED_VAL), 100);
737 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
744 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
745 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
746 PHY_M_LED_MO_DUP(MO_LED_OFF) |
747 PHY_M_LED_MO_10(MO_LED_OFF) |
748 PHY_M_LED_MO_100(MO_LED_OFF) |
749 PHY_M_LED_MO_1000(MO_LED_OFF) |
750 PHY_M_LED_MO_RX(MO_LED_OFF));
753 gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
754 PHY_M_LED_PULS_DUR(PULS_170MS) |
755 PHY_M_LED_BLINK_RT(BLINK_84MS) |
759 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
760 PHY_M_LED_MO_RX(MO_LED_OFF) |
761 (skge->speed == SPEED_100 ?
762 PHY_M_LED_MO_100(MO_LED_ON) : 0));
765 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
766 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
767 PHY_M_LED_MO_DUP(MO_LED_ON) |
768 PHY_M_LED_MO_10(MO_LED_ON) |
769 PHY_M_LED_MO_100(MO_LED_ON) |
770 PHY_M_LED_MO_1000(MO_LED_ON) |
771 PHY_M_LED_MO_RX(MO_LED_ON));
774 spin_unlock_bh(&hw->phy_lock);
777 /* blink LED's for finding board */
778 static int skge_phys_id(struct net_device *dev, u32 data)
780 struct skge_port *skge = netdev_priv(dev);
782 enum led_mode mode = LED_MODE_TST;
784 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
785 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT / HZ) * 1000;
790 skge_led(skge, mode);
791 mode ^= LED_MODE_TST;
793 if (msleep_interruptible(BLINK_MS))
798 /* back to regular LED state */
799 skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
804 static int skge_get_eeprom_len(struct net_device *dev)
806 struct skge_port *skge = netdev_priv(dev);
809 pci_read_config_dword(skge->hw->pdev, PCI_DEV_REG2, ®2);
810 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
813 static u32 skge_vpd_read(struct pci_dev *pdev, int cap, u16 offset)
817 pci_write_config_word(pdev, cap + PCI_VPD_ADDR, offset);
820 pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
821 } while (!(offset & PCI_VPD_ADDR_F));
823 pci_read_config_dword(pdev, cap + PCI_VPD_DATA, &val);
827 static void skge_vpd_write(struct pci_dev *pdev, int cap, u16 offset, u32 val)
829 pci_write_config_dword(pdev, cap + PCI_VPD_DATA, val);
830 pci_write_config_word(pdev, cap + PCI_VPD_ADDR,
831 offset | PCI_VPD_ADDR_F);
834 pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
835 } while (offset & PCI_VPD_ADDR_F);
838 static int skge_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
841 struct skge_port *skge = netdev_priv(dev);
842 struct pci_dev *pdev = skge->hw->pdev;
843 int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
844 int length = eeprom->len;
845 u16 offset = eeprom->offset;
850 eeprom->magic = SKGE_EEPROM_MAGIC;
853 u32 val = skge_vpd_read(pdev, cap, offset);
854 int n = min_t(int, length, sizeof(val));
856 memcpy(data, &val, n);
864 static int skge_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
867 struct skge_port *skge = netdev_priv(dev);
868 struct pci_dev *pdev = skge->hw->pdev;
869 int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
870 int length = eeprom->len;
871 u16 offset = eeprom->offset;
876 if (eeprom->magic != SKGE_EEPROM_MAGIC)
881 int n = min_t(int, length, sizeof(val));
884 val = skge_vpd_read(pdev, cap, offset);
885 memcpy(&val, data, n);
887 skge_vpd_write(pdev, cap, offset, val);
896 static const struct ethtool_ops skge_ethtool_ops = {
897 .get_settings = skge_get_settings,
898 .set_settings = skge_set_settings,
899 .get_drvinfo = skge_get_drvinfo,
900 .get_regs_len = skge_get_regs_len,
901 .get_regs = skge_get_regs,
902 .get_wol = skge_get_wol,
903 .set_wol = skge_set_wol,
904 .get_msglevel = skge_get_msglevel,
905 .set_msglevel = skge_set_msglevel,
906 .nway_reset = skge_nway_reset,
907 .get_link = ethtool_op_get_link,
908 .get_eeprom_len = skge_get_eeprom_len,
909 .get_eeprom = skge_get_eeprom,
910 .set_eeprom = skge_set_eeprom,
911 .get_ringparam = skge_get_ring_param,
912 .set_ringparam = skge_set_ring_param,
913 .get_pauseparam = skge_get_pauseparam,
914 .set_pauseparam = skge_set_pauseparam,
915 .get_coalesce = skge_get_coalesce,
916 .set_coalesce = skge_set_coalesce,
917 .set_sg = skge_set_sg,
918 .set_tx_csum = skge_set_tx_csum,
919 .get_rx_csum = skge_get_rx_csum,
920 .set_rx_csum = skge_set_rx_csum,
921 .get_strings = skge_get_strings,
922 .phys_id = skge_phys_id,
923 .get_sset_count = skge_get_sset_count,
924 .get_ethtool_stats = skge_get_ethtool_stats,
928 * Allocate ring elements and chain them together
929 * One-to-one association of board descriptors with ring elements
931 static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u32 base)
933 struct skge_tx_desc *d;
934 struct skge_element *e;
937 ring->start = kcalloc(ring->count, sizeof(*e), GFP_KERNEL);
941 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
943 if (i == ring->count - 1) {
944 e->next = ring->start;
945 d->next_offset = base;
948 d->next_offset = base + (i+1) * sizeof(*d);
951 ring->to_use = ring->to_clean = ring->start;
956 /* Allocate and setup a new buffer for receiving */
957 static void skge_rx_setup(struct skge_port *skge, struct skge_element *e,
958 struct sk_buff *skb, unsigned int bufsize)
960 struct skge_rx_desc *rd = e->desc;
963 map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
967 rd->dma_hi = map >> 32;
969 rd->csum1_start = ETH_HLEN;
970 rd->csum2_start = ETH_HLEN;
976 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
977 pci_unmap_addr_set(e, mapaddr, map);
978 pci_unmap_len_set(e, maplen, bufsize);
981 /* Resume receiving using existing skb,
982 * Note: DMA address is not changed by chip.
983 * MTU not changed while receiver active.
985 static inline void skge_rx_reuse(struct skge_element *e, unsigned int size)
987 struct skge_rx_desc *rd = e->desc;
990 rd->csum2_start = ETH_HLEN;
994 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
998 /* Free all buffers in receive ring, assumes receiver stopped */
999 static void skge_rx_clean(struct skge_port *skge)
1001 struct skge_hw *hw = skge->hw;
1002 struct skge_ring *ring = &skge->rx_ring;
1003 struct skge_element *e;
1007 struct skge_rx_desc *rd = e->desc;
1010 pci_unmap_single(hw->pdev,
1011 pci_unmap_addr(e, mapaddr),
1012 pci_unmap_len(e, maplen),
1013 PCI_DMA_FROMDEVICE);
1014 dev_kfree_skb(e->skb);
1017 } while ((e = e->next) != ring->start);
1021 /* Allocate buffers for receive ring
1022 * For receive: to_clean is next received frame.
1024 static int skge_rx_fill(struct net_device *dev)
1026 struct skge_port *skge = netdev_priv(dev);
1027 struct skge_ring *ring = &skge->rx_ring;
1028 struct skge_element *e;
1032 struct sk_buff *skb;
1034 skb = __netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN,
1039 skb_reserve(skb, NET_IP_ALIGN);
1040 skge_rx_setup(skge, e, skb, skge->rx_buf_size);
1041 } while ( (e = e->next) != ring->start);
1043 ring->to_clean = ring->start;
1047 static const char *skge_pause(enum pause_status status)
1050 case FLOW_STAT_NONE:
1052 case FLOW_STAT_REM_SEND:
1054 case FLOW_STAT_LOC_SEND:
1056 case FLOW_STAT_SYMMETRIC: /* Both station may send PAUSE */
1059 return "indeterminated";
1064 static void skge_link_up(struct skge_port *skge)
1066 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
1067 LED_BLK_OFF|LED_SYNC_OFF|LED_ON);
1069 netif_carrier_on(skge->netdev);
1070 netif_wake_queue(skge->netdev);
1072 if (netif_msg_link(skge)) {
1073 printk(KERN_INFO PFX
1074 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1075 skge->netdev->name, skge->speed,
1076 skge->duplex == DUPLEX_FULL ? "full" : "half",
1077 skge_pause(skge->flow_status));
1081 static void skge_link_down(struct skge_port *skge)
1083 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
1084 netif_carrier_off(skge->netdev);
1085 netif_stop_queue(skge->netdev);
1087 if (netif_msg_link(skge))
1088 printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name);
1092 static void xm_link_down(struct skge_hw *hw, int port)
1094 struct net_device *dev = hw->dev[port];
1095 struct skge_port *skge = netdev_priv(dev);
1096 u16 cmd = xm_read16(hw, port, XM_MMU_CMD);
1098 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
1100 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1101 xm_write16(hw, port, XM_MMU_CMD, cmd);
1103 /* dummy read to ensure writing */
1104 xm_read16(hw, port, XM_MMU_CMD);
1106 if (netif_carrier_ok(dev))
1107 skge_link_down(skge);
1110 static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1114 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
1115 *val = xm_read16(hw, port, XM_PHY_DATA);
1117 if (hw->phy_type == SK_PHY_XMAC)
1120 for (i = 0; i < PHY_RETRIES; i++) {
1121 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
1128 *val = xm_read16(hw, port, XM_PHY_DATA);
1133 static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
1136 if (__xm_phy_read(hw, port, reg, &v))
1137 printk(KERN_WARNING PFX "%s: phy read timed out\n",
1138 hw->dev[port]->name);
1142 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1146 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
1147 for (i = 0; i < PHY_RETRIES; i++) {
1148 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
1155 xm_write16(hw, port, XM_PHY_DATA, val);
1156 for (i = 0; i < PHY_RETRIES; i++) {
1157 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
1164 static void genesis_init(struct skge_hw *hw)
1166 /* set blink source counter */
1167 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
1168 skge_write8(hw, B2_BSC_CTRL, BSC_START);
1170 /* configure mac arbiter */
1171 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1173 /* configure mac arbiter timeout values */
1174 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
1175 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
1176 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
1177 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
1179 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1180 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1181 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1182 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1184 /* configure packet arbiter timeout */
1185 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
1186 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
1187 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
1188 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
1189 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
1192 static void genesis_reset(struct skge_hw *hw, int port)
1194 const u8 zero[8] = { 0 };
1196 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
1198 /* reset the statistics module */
1199 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
1200 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
1201 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
1202 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
1203 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
1205 /* disable Broadcom PHY IRQ */
1206 if (hw->phy_type == SK_PHY_BCOM)
1207 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
1209 xm_outhash(hw, port, XM_HSM, zero);
1213 /* Convert mode to MII values */
1214 static const u16 phy_pause_map[] = {
1215 [FLOW_MODE_NONE] = 0,
1216 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
1217 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
1218 [FLOW_MODE_SYM_OR_REM] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
1221 /* special defines for FIBER (88E1011S only) */
1222 static const u16 fiber_pause_map[] = {
1223 [FLOW_MODE_NONE] = PHY_X_P_NO_PAUSE,
1224 [FLOW_MODE_LOC_SEND] = PHY_X_P_ASYM_MD,
1225 [FLOW_MODE_SYMMETRIC] = PHY_X_P_SYM_MD,
1226 [FLOW_MODE_SYM_OR_REM] = PHY_X_P_BOTH_MD,
1230 /* Check status of Broadcom phy link */
1231 static void bcom_check_link(struct skge_hw *hw, int port)
1233 struct net_device *dev = hw->dev[port];
1234 struct skge_port *skge = netdev_priv(dev);
1237 /* read twice because of latch */
1238 xm_phy_read(hw, port, PHY_BCOM_STAT);
1239 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
1241 if ((status & PHY_ST_LSYNC) == 0) {
1242 xm_link_down(hw, port);
1246 if (skge->autoneg == AUTONEG_ENABLE) {
1249 if (!(status & PHY_ST_AN_OVER))
1252 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1253 if (lpa & PHY_B_AN_RF) {
1254 printk(KERN_NOTICE PFX "%s: remote fault\n",
1259 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1261 /* Check Duplex mismatch */
1262 switch (aux & PHY_B_AS_AN_RES_MSK) {
1263 case PHY_B_RES_1000FD:
1264 skge->duplex = DUPLEX_FULL;
1266 case PHY_B_RES_1000HD:
1267 skge->duplex = DUPLEX_HALF;
1270 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1275 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1276 switch (aux & PHY_B_AS_PAUSE_MSK) {
1277 case PHY_B_AS_PAUSE_MSK:
1278 skge->flow_status = FLOW_STAT_SYMMETRIC;
1281 skge->flow_status = FLOW_STAT_REM_SEND;
1284 skge->flow_status = FLOW_STAT_LOC_SEND;
1287 skge->flow_status = FLOW_STAT_NONE;
1289 skge->speed = SPEED_1000;
1292 if (!netif_carrier_ok(dev))
1293 genesis_link_up(skge);
1296 /* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1297 * Phy on for 100 or 10Mbit operation
1299 static void bcom_phy_init(struct skge_port *skge)
1301 struct skge_hw *hw = skge->hw;
1302 int port = skge->port;
1304 u16 id1, r, ext, ctl;
1306 /* magic workaround patterns for Broadcom */
1307 static const struct {
1311 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1312 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1313 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1314 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1316 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1317 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1320 /* read Id from external PHY (all have the same address) */
1321 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1323 /* Optimize MDIO transfer by suppressing preamble. */
1324 r = xm_read16(hw, port, XM_MMU_CMD);
1326 xm_write16(hw, port, XM_MMU_CMD,r);
1329 case PHY_BCOM_ID1_C0:
1331 * Workaround BCOM Errata for the C0 type.
1332 * Write magic patterns to reserved registers.
1334 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1335 xm_phy_write(hw, port,
1336 C0hack[i].reg, C0hack[i].val);
1339 case PHY_BCOM_ID1_A1:
1341 * Workaround BCOM Errata for the A1 type.
1342 * Write magic patterns to reserved registers.
1344 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1345 xm_phy_write(hw, port,
1346 A1hack[i].reg, A1hack[i].val);
1351 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1352 * Disable Power Management after reset.
1354 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1355 r |= PHY_B_AC_DIS_PM;
1356 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1359 xm_read16(hw, port, XM_ISRC);
1361 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1362 ctl = PHY_CT_SP1000; /* always 1000mbit */
1364 if (skge->autoneg == AUTONEG_ENABLE) {
1366 * Workaround BCOM Errata #1 for the C5 type.
1367 * 1000Base-T Link Acquisition Failure in Slave Mode
1368 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1370 u16 adv = PHY_B_1000C_RD;
1371 if (skge->advertising & ADVERTISED_1000baseT_Half)
1372 adv |= PHY_B_1000C_AHD;
1373 if (skge->advertising & ADVERTISED_1000baseT_Full)
1374 adv |= PHY_B_1000C_AFD;
1375 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1377 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1379 if (skge->duplex == DUPLEX_FULL)
1380 ctl |= PHY_CT_DUP_MD;
1381 /* Force to slave */
1382 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1385 /* Set autonegotiation pause parameters */
1386 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1387 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1389 /* Handle Jumbo frames */
1390 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
1391 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1392 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1394 ext |= PHY_B_PEC_HIGH_LA;
1398 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1399 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1401 /* Use link status change interrupt */
1402 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1405 static void xm_phy_init(struct skge_port *skge)
1407 struct skge_hw *hw = skge->hw;
1408 int port = skge->port;
1411 if (skge->autoneg == AUTONEG_ENABLE) {
1412 if (skge->advertising & ADVERTISED_1000baseT_Half)
1413 ctrl |= PHY_X_AN_HD;
1414 if (skge->advertising & ADVERTISED_1000baseT_Full)
1415 ctrl |= PHY_X_AN_FD;
1417 ctrl |= fiber_pause_map[skge->flow_control];
1419 xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl);
1421 /* Restart Auto-negotiation */
1422 ctrl = PHY_CT_ANE | PHY_CT_RE_CFG;
1424 /* Set DuplexMode in Config register */
1425 if (skge->duplex == DUPLEX_FULL)
1426 ctrl |= PHY_CT_DUP_MD;
1428 * Do NOT enable Auto-negotiation here. This would hold
1429 * the link down because no IDLEs are transmitted
1433 xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl);
1435 /* Poll PHY for status changes */
1436 mod_timer(&skge->link_timer, jiffies + LINK_HZ);
1439 static int xm_check_link(struct net_device *dev)
1441 struct skge_port *skge = netdev_priv(dev);
1442 struct skge_hw *hw = skge->hw;
1443 int port = skge->port;
1446 /* read twice because of latch */
1447 xm_phy_read(hw, port, PHY_XMAC_STAT);
1448 status = xm_phy_read(hw, port, PHY_XMAC_STAT);
1450 if ((status & PHY_ST_LSYNC) == 0) {
1451 xm_link_down(hw, port);
1455 if (skge->autoneg == AUTONEG_ENABLE) {
1458 if (!(status & PHY_ST_AN_OVER))
1461 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1462 if (lpa & PHY_B_AN_RF) {
1463 printk(KERN_NOTICE PFX "%s: remote fault\n",
1468 res = xm_phy_read(hw, port, PHY_XMAC_RES_ABI);
1470 /* Check Duplex mismatch */
1471 switch (res & (PHY_X_RS_HD | PHY_X_RS_FD)) {
1473 skge->duplex = DUPLEX_FULL;
1476 skge->duplex = DUPLEX_HALF;
1479 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1484 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1485 if ((skge->flow_control == FLOW_MODE_SYMMETRIC ||
1486 skge->flow_control == FLOW_MODE_SYM_OR_REM) &&
1487 (lpa & PHY_X_P_SYM_MD))
1488 skge->flow_status = FLOW_STAT_SYMMETRIC;
1489 else if (skge->flow_control == FLOW_MODE_SYM_OR_REM &&
1490 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_ASYM_MD)
1491 /* Enable PAUSE receive, disable PAUSE transmit */
1492 skge->flow_status = FLOW_STAT_REM_SEND;
1493 else if (skge->flow_control == FLOW_MODE_LOC_SEND &&
1494 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_BOTH_MD)
1495 /* Disable PAUSE receive, enable PAUSE transmit */
1496 skge->flow_status = FLOW_STAT_LOC_SEND;
1498 skge->flow_status = FLOW_STAT_NONE;
1500 skge->speed = SPEED_1000;
1503 if (!netif_carrier_ok(dev))
1504 genesis_link_up(skge);
1508 /* Poll to check for link coming up.
1510 * Since internal PHY is wired to a level triggered pin, can't
1511 * get an interrupt when carrier is detected, need to poll for
1514 static void xm_link_timer(unsigned long arg)
1516 struct skge_port *skge = (struct skge_port *) arg;
1517 struct net_device *dev = skge->netdev;
1518 struct skge_hw *hw = skge->hw;
1519 int port = skge->port;
1521 unsigned long flags;
1523 if (!netif_running(dev))
1526 spin_lock_irqsave(&hw->phy_lock, flags);
1529 * Verify that the link by checking GPIO register three times.
1530 * This pin has the signal from the link_sync pin connected to it.
1532 for (i = 0; i < 3; i++) {
1533 if (xm_read16(hw, port, XM_GP_PORT) & XM_GP_INP_ASS)
1537 /* Re-enable interrupt to detect link down */
1538 if (xm_check_link(dev)) {
1539 u16 msk = xm_read16(hw, port, XM_IMSK);
1540 msk &= ~XM_IS_INP_ASS;
1541 xm_write16(hw, port, XM_IMSK, msk);
1542 xm_read16(hw, port, XM_ISRC);
1545 mod_timer(&skge->link_timer,
1546 round_jiffies(jiffies + LINK_HZ));
1548 spin_unlock_irqrestore(&hw->phy_lock, flags);
1551 static void genesis_mac_init(struct skge_hw *hw, int port)
1553 struct net_device *dev = hw->dev[port];
1554 struct skge_port *skge = netdev_priv(dev);
1555 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1558 const u8 zero[6] = { 0 };
1560 for (i = 0; i < 10; i++) {
1561 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
1563 if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)
1568 printk(KERN_WARNING PFX "%s: genesis reset failed\n", dev->name);
1571 /* Unreset the XMAC. */
1572 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1575 * Perform additional initialization for external PHYs,
1576 * namely for the 1000baseTX cards that use the XMAC's
1579 if (hw->phy_type != SK_PHY_XMAC) {
1580 /* Take external Phy out of reset */
1581 r = skge_read32(hw, B2_GP_IO);
1583 r |= GP_DIR_0|GP_IO_0;
1585 r |= GP_DIR_2|GP_IO_2;
1587 skge_write32(hw, B2_GP_IO, r);
1589 /* Enable GMII interface */
1590 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1594 switch(hw->phy_type) {
1599 bcom_phy_init(skge);
1600 bcom_check_link(hw, port);
1603 /* Set Station Address */
1604 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
1606 /* We don't use match addresses so clear */
1607 for (i = 1; i < 16; i++)
1608 xm_outaddr(hw, port, XM_EXM(i), zero);
1610 /* Clear MIB counters */
1611 xm_write16(hw, port, XM_STAT_CMD,
1612 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1613 /* Clear two times according to Errata #3 */
1614 xm_write16(hw, port, XM_STAT_CMD,
1615 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1617 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1618 xm_write16(hw, port, XM_RX_HI_WM, 1450);
1620 /* We don't need the FCS appended to the packet. */
1621 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1623 r |= XM_RX_BIG_PK_OK;
1625 if (skge->duplex == DUPLEX_HALF) {
1627 * If in manual half duplex mode the other side might be in
1628 * full duplex mode, so ignore if a carrier extension is not seen
1629 * on frames received
1631 r |= XM_RX_DIS_CEXT;
1633 xm_write16(hw, port, XM_RX_CMD, r);
1636 /* We want short frames padded to 60 bytes. */
1637 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1640 * Bump up the transmit threshold. This helps hold off transmit
1641 * underruns when we're blasting traffic from both ports at once.
1643 xm_write16(hw, port, XM_TX_THR, 512);
1646 * Enable the reception of all error frames. This is is
1647 * a necessary evil due to the design of the XMAC. The
1648 * XMAC's receive FIFO is only 8K in size, however jumbo
1649 * frames can be up to 9000 bytes in length. When bad
1650 * frame filtering is enabled, the XMAC's RX FIFO operates
1651 * in 'store and forward' mode. For this to work, the
1652 * entire frame has to fit into the FIFO, but that means
1653 * that jumbo frames larger than 8192 bytes will be
1654 * truncated. Disabling all bad frame filtering causes
1655 * the RX FIFO to operate in streaming mode, in which
1656 * case the XMAC will start transferring frames out of the
1657 * RX FIFO as soon as the FIFO threshold is reached.
1659 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
1663 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1664 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1665 * and 'Octets Rx OK Hi Cnt Ov'.
1667 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1670 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1671 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1672 * and 'Octets Tx OK Hi Cnt Ov'.
1674 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
1676 /* Configure MAC arbiter */
1677 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1679 /* configure timeout values */
1680 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1681 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1682 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1683 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1685 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1686 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1687 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1688 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1690 /* Configure Rx MAC FIFO */
1691 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1692 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1693 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
1695 /* Configure Tx MAC FIFO */
1696 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1697 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1698 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
1701 /* Enable frame flushing if jumbo frames used */
1702 skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);
1704 /* enable timeout timers if normal frames */
1705 skge_write16(hw, B3_PA_CTRL,
1706 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
1710 static void genesis_stop(struct skge_port *skge)
1712 struct skge_hw *hw = skge->hw;
1713 int port = skge->port;
1716 genesis_reset(hw, port);
1718 /* Clear Tx packet arbiter timeout IRQ */
1719 skge_write16(hw, B3_PA_CTRL,
1720 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1723 * If the transfer sticks at the MAC the STOP command will not
1724 * terminate if we don't flush the XMAC's transmit FIFO !
1726 xm_write32(hw, port, XM_MODE,
1727 xm_read32(hw, port, XM_MODE)|XM_MD_FTF);
1731 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
1733 /* For external PHYs there must be special handling */
1734 if (hw->phy_type != SK_PHY_XMAC) {
1735 reg = skge_read32(hw, B2_GP_IO);
1743 skge_write32(hw, B2_GP_IO, reg);
1744 skge_read32(hw, B2_GP_IO);
1747 xm_write16(hw, port, XM_MMU_CMD,
1748 xm_read16(hw, port, XM_MMU_CMD)
1749 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1751 xm_read16(hw, port, XM_MMU_CMD);
1755 static void genesis_get_stats(struct skge_port *skge, u64 *data)
1757 struct skge_hw *hw = skge->hw;
1758 int port = skge->port;
1760 unsigned long timeout = jiffies + HZ;
1762 xm_write16(hw, port,
1763 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1765 /* wait for update to complete */
1766 while (xm_read16(hw, port, XM_STAT_CMD)
1767 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1768 if (time_after(jiffies, timeout))
1773 /* special case for 64 bit octet counter */
1774 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1775 | xm_read32(hw, port, XM_TXO_OK_LO);
1776 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1777 | xm_read32(hw, port, XM_RXO_OK_LO);
1779 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1780 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
1783 static void genesis_mac_intr(struct skge_hw *hw, int port)
1785 struct net_device *dev = hw->dev[port];
1786 struct skge_port *skge = netdev_priv(dev);
1787 u16 status = xm_read16(hw, port, XM_ISRC);
1789 if (netif_msg_intr(skge))
1790 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1793 if (hw->phy_type == SK_PHY_XMAC && (status & XM_IS_INP_ASS)) {
1794 xm_link_down(hw, port);
1795 mod_timer(&skge->link_timer, jiffies + 1);
1798 if (status & XM_IS_TXF_UR) {
1799 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
1800 ++dev->stats.tx_fifo_errors;
1803 if (status & XM_IS_RXF_OV) {
1804 xm_write32(hw, port, XM_MODE, XM_MD_FRF);
1805 ++dev->stats.rx_fifo_errors;
1809 static void genesis_link_up(struct skge_port *skge)
1811 struct skge_hw *hw = skge->hw;
1812 int port = skge->port;
1816 cmd = xm_read16(hw, port, XM_MMU_CMD);
1819 * enabling pause frame reception is required for 1000BT
1820 * because the XMAC is not reset if the link is going down
1822 if (skge->flow_status == FLOW_STAT_NONE ||
1823 skge->flow_status == FLOW_STAT_LOC_SEND)
1824 /* Disable Pause Frame Reception */
1825 cmd |= XM_MMU_IGN_PF;
1827 /* Enable Pause Frame Reception */
1828 cmd &= ~XM_MMU_IGN_PF;
1830 xm_write16(hw, port, XM_MMU_CMD, cmd);
1832 mode = xm_read32(hw, port, XM_MODE);
1833 if (skge->flow_status== FLOW_STAT_SYMMETRIC ||
1834 skge->flow_status == FLOW_STAT_LOC_SEND) {
1836 * Configure Pause Frame Generation
1837 * Use internal and external Pause Frame Generation.
1838 * Sending pause frames is edge triggered.
1839 * Send a Pause frame with the maximum pause time if
1840 * internal oder external FIFO full condition occurs.
1841 * Send a zero pause time frame to re-start transmission.
1843 /* XM_PAUSE_DA = '010000C28001' (default) */
1844 /* XM_MAC_PTIME = 0xffff (maximum) */
1845 /* remember this value is defined in big endian (!) */
1846 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
1848 mode |= XM_PAUSE_MODE;
1849 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
1852 * disable pause frame generation is required for 1000BT
1853 * because the XMAC is not reset if the link is going down
1855 /* Disable Pause Mode in Mode Register */
1856 mode &= ~XM_PAUSE_MODE;
1858 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
1861 xm_write32(hw, port, XM_MODE, mode);
1863 /* Turn on detection of Tx underrun, Rx overrun */
1864 msk = xm_read16(hw, port, XM_IMSK);
1865 msk &= ~(XM_IS_RXF_OV | XM_IS_TXF_UR);
1866 xm_write16(hw, port, XM_IMSK, msk);
1868 xm_read16(hw, port, XM_ISRC);
1870 /* get MMU Command Reg. */
1871 cmd = xm_read16(hw, port, XM_MMU_CMD);
1872 if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL)
1873 cmd |= XM_MMU_GMII_FD;
1876 * Workaround BCOM Errata (#10523) for all BCom Phys
1877 * Enable Power Management after link up
1879 if (hw->phy_type == SK_PHY_BCOM) {
1880 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1881 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1882 & ~PHY_B_AC_DIS_PM);
1883 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1887 xm_write16(hw, port, XM_MMU_CMD,
1888 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1893 static inline void bcom_phy_intr(struct skge_port *skge)
1895 struct skge_hw *hw = skge->hw;
1896 int port = skge->port;
1899 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
1900 if (netif_msg_intr(skge))
1901 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x\n",
1902 skge->netdev->name, isrc);
1904 if (isrc & PHY_B_IS_PSE)
1905 printk(KERN_ERR PFX "%s: uncorrectable pair swap error\n",
1906 hw->dev[port]->name);
1908 /* Workaround BCom Errata:
1909 * enable and disable loopback mode if "NO HCD" occurs.
1911 if (isrc & PHY_B_IS_NO_HDCL) {
1912 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1913 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1914 ctrl | PHY_CT_LOOP);
1915 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1916 ctrl & ~PHY_CT_LOOP);
1919 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1920 bcom_check_link(hw, port);
1924 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1928 gma_write16(hw, port, GM_SMI_DATA, val);
1929 gma_write16(hw, port, GM_SMI_CTRL,
1930 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1931 for (i = 0; i < PHY_RETRIES; i++) {
1934 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1938 printk(KERN_WARNING PFX "%s: phy write timeout\n",
1939 hw->dev[port]->name);
1943 static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1947 gma_write16(hw, port, GM_SMI_CTRL,
1948 GM_SMI_CT_PHY_AD(hw->phy_addr)
1949 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1951 for (i = 0; i < PHY_RETRIES; i++) {
1953 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1959 *val = gma_read16(hw, port, GM_SMI_DATA);
1963 static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1966 if (__gm_phy_read(hw, port, reg, &v))
1967 printk(KERN_WARNING PFX "%s: phy read timeout\n",
1968 hw->dev[port]->name);
1972 /* Marvell Phy Initialization */
1973 static void yukon_init(struct skge_hw *hw, int port)
1975 struct skge_port *skge = netdev_priv(hw->dev[port]);
1976 u16 ctrl, ct1000, adv;
1978 if (skge->autoneg == AUTONEG_ENABLE) {
1979 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
1981 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1982 PHY_M_EC_MAC_S_MSK);
1983 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1985 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
1987 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
1990 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1991 if (skge->autoneg == AUTONEG_DISABLE)
1992 ctrl &= ~PHY_CT_ANE;
1994 ctrl |= PHY_CT_RESET;
1995 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2001 if (skge->autoneg == AUTONEG_ENABLE) {
2003 if (skge->advertising & ADVERTISED_1000baseT_Full)
2004 ct1000 |= PHY_M_1000C_AFD;
2005 if (skge->advertising & ADVERTISED_1000baseT_Half)
2006 ct1000 |= PHY_M_1000C_AHD;
2007 if (skge->advertising & ADVERTISED_100baseT_Full)
2008 adv |= PHY_M_AN_100_FD;
2009 if (skge->advertising & ADVERTISED_100baseT_Half)
2010 adv |= PHY_M_AN_100_HD;
2011 if (skge->advertising & ADVERTISED_10baseT_Full)
2012 adv |= PHY_M_AN_10_FD;
2013 if (skge->advertising & ADVERTISED_10baseT_Half)
2014 adv |= PHY_M_AN_10_HD;
2016 /* Set Flow-control capabilities */
2017 adv |= phy_pause_map[skge->flow_control];
2019 if (skge->advertising & ADVERTISED_1000baseT_Full)
2020 adv |= PHY_M_AN_1000X_AFD;
2021 if (skge->advertising & ADVERTISED_1000baseT_Half)
2022 adv |= PHY_M_AN_1000X_AHD;
2024 adv |= fiber_pause_map[skge->flow_control];
2027 /* Restart Auto-negotiation */
2028 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
2030 /* forced speed/duplex settings */
2031 ct1000 = PHY_M_1000C_MSE;
2033 if (skge->duplex == DUPLEX_FULL)
2034 ctrl |= PHY_CT_DUP_MD;
2036 switch (skge->speed) {
2038 ctrl |= PHY_CT_SP1000;
2041 ctrl |= PHY_CT_SP100;
2045 ctrl |= PHY_CT_RESET;
2048 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
2050 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
2051 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2053 /* Enable phy interrupt on autonegotiation complete (or link up) */
2054 if (skge->autoneg == AUTONEG_ENABLE)
2055 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
2057 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
2060 static void yukon_reset(struct skge_hw *hw, int port)
2062 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
2063 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
2064 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
2065 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
2066 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
2068 gma_write16(hw, port, GM_RX_CTRL,
2069 gma_read16(hw, port, GM_RX_CTRL)
2070 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2073 /* Apparently, early versions of Yukon-Lite had wrong chip_id? */
2074 static int is_yukon_lite_a0(struct skge_hw *hw)
2079 if (hw->chip_id != CHIP_ID_YUKON)
2082 reg = skge_read32(hw, B2_FAR);
2083 skge_write8(hw, B2_FAR + 3, 0xff);
2084 ret = (skge_read8(hw, B2_FAR + 3) != 0);
2085 skge_write32(hw, B2_FAR, reg);
2089 static void yukon_mac_init(struct skge_hw *hw, int port)
2091 struct skge_port *skge = netdev_priv(hw->dev[port]);
2094 const u8 *addr = hw->dev[port]->dev_addr;
2096 /* WA code for COMA mode -- set PHY reset */
2097 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
2098 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
2099 reg = skge_read32(hw, B2_GP_IO);
2100 reg |= GP_DIR_9 | GP_IO_9;
2101 skge_write32(hw, B2_GP_IO, reg);
2105 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2106 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
2108 /* WA code for COMA mode -- clear PHY reset */
2109 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
2110 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
2111 reg = skge_read32(hw, B2_GP_IO);
2114 skge_write32(hw, B2_GP_IO, reg);
2117 /* Set hardware config mode */
2118 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
2119 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
2120 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
2122 /* Clear GMC reset */
2123 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
2124 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
2125 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
2127 if (skge->autoneg == AUTONEG_DISABLE) {
2128 reg = GM_GPCR_AU_ALL_DIS;
2129 gma_write16(hw, port, GM_GP_CTRL,
2130 gma_read16(hw, port, GM_GP_CTRL) | reg);
2132 switch (skge->speed) {
2134 reg &= ~GM_GPCR_SPEED_100;
2135 reg |= GM_GPCR_SPEED_1000;
2138 reg &= ~GM_GPCR_SPEED_1000;
2139 reg |= GM_GPCR_SPEED_100;
2142 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
2146 if (skge->duplex == DUPLEX_FULL)
2147 reg |= GM_GPCR_DUP_FULL;
2149 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
2151 switch (skge->flow_control) {
2152 case FLOW_MODE_NONE:
2153 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2154 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
2156 case FLOW_MODE_LOC_SEND:
2157 /* disable Rx flow-control */
2158 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
2160 case FLOW_MODE_SYMMETRIC:
2161 case FLOW_MODE_SYM_OR_REM:
2162 /* enable Tx & Rx flow-control */
2166 gma_write16(hw, port, GM_GP_CTRL, reg);
2167 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
2169 yukon_init(hw, port);
2172 reg = gma_read16(hw, port, GM_PHY_ADDR);
2173 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
2175 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
2176 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
2177 gma_write16(hw, port, GM_PHY_ADDR, reg);
2179 /* transmit control */
2180 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
2182 /* receive control reg: unicast + multicast + no FCS */
2183 gma_write16(hw, port, GM_RX_CTRL,
2184 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
2186 /* transmit flow control */
2187 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
2189 /* transmit parameter */
2190 gma_write16(hw, port, GM_TX_PARAM,
2191 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
2192 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
2193 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
2195 /* serial mode register */
2196 reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2197 if (hw->dev[port]->mtu > 1500)
2198 reg |= GM_SMOD_JUMBO_ENA;
2200 gma_write16(hw, port, GM_SERIAL_MODE, reg);
2202 /* physical address: used for pause frames */
2203 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
2204 /* virtual address for data */
2205 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
2207 /* enable interrupt mask for counter overflows */
2208 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
2209 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
2210 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
2212 /* Initialize Mac Fifo */
2214 /* Configure Rx MAC FIFO */
2215 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
2216 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
2218 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
2219 if (is_yukon_lite_a0(hw))
2220 reg &= ~GMF_RX_F_FL_ON;
2222 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
2223 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
2225 * because Pause Packet Truncation in GMAC is not working
2226 * we have to increase the Flush Threshold to 64 bytes
2227 * in order to flush pause packets in Rx FIFO on Yukon-1
2229 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
2231 /* Configure Tx MAC FIFO */
2232 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
2233 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
2236 /* Go into power down mode */
2237 static void yukon_suspend(struct skge_hw *hw, int port)
2241 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2242 ctrl |= PHY_M_PC_POL_R_DIS;
2243 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
2245 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2246 ctrl |= PHY_CT_RESET;
2247 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2249 /* switch IEEE compatible power down mode on */
2250 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2251 ctrl |= PHY_CT_PDOWN;
2252 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2255 static void yukon_stop(struct skge_port *skge)
2257 struct skge_hw *hw = skge->hw;
2258 int port = skge->port;
2260 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
2261 yukon_reset(hw, port);
2263 gma_write16(hw, port, GM_GP_CTRL,
2264 gma_read16(hw, port, GM_GP_CTRL)
2265 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
2266 gma_read16(hw, port, GM_GP_CTRL);
2268 yukon_suspend(hw, port);
2270 /* set GPHY Control reset */
2271 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2272 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
2275 static void yukon_get_stats(struct skge_port *skge, u64 *data)
2277 struct skge_hw *hw = skge->hw;
2278 int port = skge->port;
2281 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2282 | gma_read32(hw, port, GM_TXO_OK_LO);
2283 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2284 | gma_read32(hw, port, GM_RXO_OK_LO);
2286 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
2287 data[i] = gma_read32(hw, port,
2288 skge_stats[i].gma_offset);
2291 static void yukon_mac_intr(struct skge_hw *hw, int port)
2293 struct net_device *dev = hw->dev[port];
2294 struct skge_port *skge = netdev_priv(dev);
2295 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2297 if (netif_msg_intr(skge))
2298 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
2301 if (status & GM_IS_RX_FF_OR) {
2302 ++dev->stats.rx_fifo_errors;
2303 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2306 if (status & GM_IS_TX_FF_UR) {
2307 ++dev->stats.tx_fifo_errors;
2308 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2313 static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
2315 switch (aux & PHY_M_PS_SPEED_MSK) {
2316 case PHY_M_PS_SPEED_1000:
2318 case PHY_M_PS_SPEED_100:
2325 static void yukon_link_up(struct skge_port *skge)
2327 struct skge_hw *hw = skge->hw;
2328 int port = skge->port;
2331 /* Enable Transmit FIFO Underrun */
2332 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
2334 reg = gma_read16(hw, port, GM_GP_CTRL);
2335 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
2336 reg |= GM_GPCR_DUP_FULL;
2339 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
2340 gma_write16(hw, port, GM_GP_CTRL, reg);
2342 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
2346 static void yukon_link_down(struct skge_port *skge)
2348 struct skge_hw *hw = skge->hw;
2349 int port = skge->port;
2352 ctrl = gma_read16(hw, port, GM_GP_CTRL);
2353 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2354 gma_write16(hw, port, GM_GP_CTRL, ctrl);
2356 if (skge->flow_status == FLOW_STAT_REM_SEND) {
2357 ctrl = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2358 ctrl |= PHY_M_AN_ASP;
2359 /* restore Asymmetric Pause bit */
2360 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, ctrl);
2363 skge_link_down(skge);
2365 yukon_init(hw, port);
2368 static void yukon_phy_intr(struct skge_port *skge)
2370 struct skge_hw *hw = skge->hw;
2371 int port = skge->port;
2372 const char *reason = NULL;
2373 u16 istatus, phystat;
2375 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2376 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2378 if (netif_msg_intr(skge))
2379 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x 0x%x\n",
2380 skge->netdev->name, istatus, phystat);
2382 if (istatus & PHY_M_IS_AN_COMPL) {
2383 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
2385 reason = "remote fault";
2389 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
2390 reason = "master/slave fault";
2394 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
2395 reason = "speed/duplex";
2399 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
2400 ? DUPLEX_FULL : DUPLEX_HALF;
2401 skge->speed = yukon_speed(hw, phystat);
2403 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
2404 switch (phystat & PHY_M_PS_PAUSE_MSK) {
2405 case PHY_M_PS_PAUSE_MSK:
2406 skge->flow_status = FLOW_STAT_SYMMETRIC;
2408 case PHY_M_PS_RX_P_EN:
2409 skge->flow_status = FLOW_STAT_REM_SEND;
2411 case PHY_M_PS_TX_P_EN:
2412 skge->flow_status = FLOW_STAT_LOC_SEND;
2415 skge->flow_status = FLOW_STAT_NONE;
2418 if (skge->flow_status == FLOW_STAT_NONE ||
2419 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
2420 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2422 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2423 yukon_link_up(skge);
2427 if (istatus & PHY_M_IS_LSP_CHANGE)
2428 skge->speed = yukon_speed(hw, phystat);
2430 if (istatus & PHY_M_IS_DUP_CHANGE)
2431 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2432 if (istatus & PHY_M_IS_LST_CHANGE) {
2433 if (phystat & PHY_M_PS_LINK_UP)
2434 yukon_link_up(skge);
2436 yukon_link_down(skge);
2440 printk(KERN_ERR PFX "%s: autonegotiation failed (%s)\n",
2441 skge->netdev->name, reason);
2443 /* XXX restart autonegotiation? */
2446 static void skge_phy_reset(struct skge_port *skge)
2448 struct skge_hw *hw = skge->hw;
2449 int port = skge->port;
2450 struct net_device *dev = hw->dev[port];
2452 netif_stop_queue(skge->netdev);
2453 netif_carrier_off(skge->netdev);
2455 spin_lock_bh(&hw->phy_lock);
2456 if (hw->chip_id == CHIP_ID_GENESIS) {
2457 genesis_reset(hw, port);
2458 genesis_mac_init(hw, port);
2460 yukon_reset(hw, port);
2461 yukon_init(hw, port);
2463 spin_unlock_bh(&hw->phy_lock);
2465 dev->set_multicast_list(dev);
2468 /* Basic MII support */
2469 static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2471 struct mii_ioctl_data *data = if_mii(ifr);
2472 struct skge_port *skge = netdev_priv(dev);
2473 struct skge_hw *hw = skge->hw;
2474 int err = -EOPNOTSUPP;
2476 if (!netif_running(dev))
2477 return -ENODEV; /* Phy still in reset */
2481 data->phy_id = hw->phy_addr;
2486 spin_lock_bh(&hw->phy_lock);
2487 if (hw->chip_id == CHIP_ID_GENESIS)
2488 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2490 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2491 spin_unlock_bh(&hw->phy_lock);
2492 data->val_out = val;
2497 if (!capable(CAP_NET_ADMIN))
2500 spin_lock_bh(&hw->phy_lock);
2501 if (hw->chip_id == CHIP_ID_GENESIS)
2502 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2505 err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2507 spin_unlock_bh(&hw->phy_lock);
2513 /* Assign Ram Buffer allocation to queue */
2514 static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, u32 space)
2518 /* convert from K bytes to qwords used for hw register */
2521 end = start + space - 1;
2523 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2524 skge_write32(hw, RB_ADDR(q, RB_START), start);
2525 skge_write32(hw, RB_ADDR(q, RB_END), end);
2526 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2527 skge_write32(hw, RB_ADDR(q, RB_RP), start);
2529 if (q == Q_R1 || q == Q_R2) {
2530 u32 tp = space - space/4;
2532 /* Set thresholds on receive queue's */
2533 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
2534 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
2535 } else if (hw->chip_id != CHIP_ID_GENESIS)
2536 /* Genesis Tx Fifo is too small for normal store/forward */
2537 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
2539 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2542 /* Setup Bus Memory Interface */
2543 static void skge_qset(struct skge_port *skge, u16 q,
2544 const struct skge_element *e)
2546 struct skge_hw *hw = skge->hw;
2547 u32 watermark = 0x600;
2548 u64 base = skge->dma + (e->desc - skge->mem);
2550 /* optimization to reduce window on 32bit/33mhz */
2551 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2554 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2555 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2556 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2557 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2560 static int skge_up(struct net_device *dev)
2562 struct skge_port *skge = netdev_priv(dev);
2563 struct skge_hw *hw = skge->hw;
2564 int port = skge->port;
2565 u32 ramaddr, ramsize, rxspace;
2566 size_t rx_size, tx_size;
2569 if (!is_valid_ether_addr(dev->dev_addr))
2572 if (netif_msg_ifup(skge))
2573 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
2575 if (dev->mtu > RX_BUF_SIZE)
2576 skge->rx_buf_size = dev->mtu + ETH_HLEN;
2578 skge->rx_buf_size = RX_BUF_SIZE;
2581 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2582 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2583 skge->mem_size = tx_size + rx_size;
2584 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2588 BUG_ON(skge->dma & 7);
2590 if ((u64)skge->dma >> 32 != ((u64) skge->dma + skge->mem_size) >> 32) {
2591 dev_err(&hw->pdev->dev, "pci_alloc_consistent region crosses 4G boundary\n");
2596 memset(skge->mem, 0, skge->mem_size);
2598 err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma);
2602 err = skge_rx_fill(dev);
2606 err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2607 skge->dma + rx_size);
2611 /* Initialize MAC */
2612 spin_lock_bh(&hw->phy_lock);
2613 if (hw->chip_id == CHIP_ID_GENESIS)
2614 genesis_mac_init(hw, port);
2616 yukon_mac_init(hw, port);
2617 spin_unlock_bh(&hw->phy_lock);
2619 /* Configure RAMbuffers */
2620 ramsize = (hw->ram_size - hw->ram_offset) / hw->ports;
2621 ramaddr = hw->ram_offset + port * ramsize;
2622 rxspace = 8 + (2*(ramsize - 16))/3;
2624 skge_ramset(hw, rxqaddr[port], ramaddr, rxspace);
2625 skge_ramset(hw, txqaddr[port], ramaddr + rxspace, ramsize - rxspace);
2627 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
2628 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
2629 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2631 /* Start receiver BMU */
2633 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
2634 skge_led(skge, LED_MODE_ON);
2636 spin_lock_irq(&hw->hw_lock);
2637 hw->intr_mask |= portmask[port];
2638 skge_write32(hw, B0_IMSK, hw->intr_mask);
2639 spin_unlock_irq(&hw->hw_lock);
2641 napi_enable(&skge->napi);
2645 skge_rx_clean(skge);
2646 kfree(skge->rx_ring.start);
2648 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2655 static void skge_rx_stop(struct skge_hw *hw, int port)
2657 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2658 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2659 RB_RST_SET|RB_DIS_OP_MD);
2660 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2663 static int skge_down(struct net_device *dev)
2665 struct skge_port *skge = netdev_priv(dev);
2666 struct skge_hw *hw = skge->hw;
2667 int port = skge->port;
2669 if (skge->mem == NULL)
2672 if (netif_msg_ifdown(skge))
2673 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
2675 netif_stop_queue(dev);
2677 if (hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC)
2678 del_timer_sync(&skge->link_timer);
2680 napi_disable(&skge->napi);
2681 netif_carrier_off(dev);
2683 spin_lock_irq(&hw->hw_lock);
2684 hw->intr_mask &= ~portmask[port];
2685 skge_write32(hw, B0_IMSK, hw->intr_mask);
2686 spin_unlock_irq(&hw->hw_lock);
2688 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
2689 if (hw->chip_id == CHIP_ID_GENESIS)
2694 /* Stop transmitter */
2695 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2696 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2697 RB_RST_SET|RB_DIS_OP_MD);
2700 /* Disable Force Sync bit and Enable Alloc bit */
2701 skge_write8(hw, SK_REG(port, TXA_CTRL),
2702 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2704 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
2705 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2706 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
2708 /* Reset PCI FIFO */
2709 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2710 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2712 /* Reset the RAM Buffer async Tx queue */
2713 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
2715 skge_rx_stop(hw, port);
2717 if (hw->chip_id == CHIP_ID_GENESIS) {
2718 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2719 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
2721 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2722 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
2725 skge_led(skge, LED_MODE_OFF);
2727 netif_tx_lock_bh(dev);
2729 netif_tx_unlock_bh(dev);
2731 skge_rx_clean(skge);
2733 kfree(skge->rx_ring.start);
2734 kfree(skge->tx_ring.start);
2735 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2740 static inline int skge_avail(const struct skge_ring *ring)
2743 return ((ring->to_clean > ring->to_use) ? 0 : ring->count)
2744 + (ring->to_clean - ring->to_use) - 1;
2747 static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
2749 struct skge_port *skge = netdev_priv(dev);
2750 struct skge_hw *hw = skge->hw;
2751 struct skge_element *e;
2752 struct skge_tx_desc *td;
2757 if (skb_padto(skb, ETH_ZLEN))
2758 return NETDEV_TX_OK;
2760 if (unlikely(skge_avail(&skge->tx_ring) < skb_shinfo(skb)->nr_frags + 1))
2761 return NETDEV_TX_BUSY;
2763 e = skge->tx_ring.to_use;
2765 BUG_ON(td->control & BMU_OWN);
2767 len = skb_headlen(skb);
2768 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
2769 pci_unmap_addr_set(e, mapaddr, map);
2770 pci_unmap_len_set(e, maplen, len);
2773 td->dma_hi = map >> 32;
2775 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2776 const int offset = skb_transport_offset(skb);
2778 /* This seems backwards, but it is what the sk98lin
2779 * does. Looks like hardware is wrong?
2781 if (ipip_hdr(skb)->protocol == IPPROTO_UDP
2782 && hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
2783 control = BMU_TCP_CHECK;
2785 control = BMU_UDP_CHECK;
2788 td->csum_start = offset;
2789 td->csum_write = offset + skb->csum_offset;
2791 control = BMU_CHECK;
2793 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
2794 control |= BMU_EOF| BMU_IRQ_EOF;
2796 struct skge_tx_desc *tf = td;
2798 control |= BMU_STFWD;
2799 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2800 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2802 map = pci_map_page(hw->pdev, frag->page, frag->page_offset,
2803 frag->size, PCI_DMA_TODEVICE);
2808 BUG_ON(tf->control & BMU_OWN);
2811 tf->dma_hi = (u64) map >> 32;
2812 pci_unmap_addr_set(e, mapaddr, map);
2813 pci_unmap_len_set(e, maplen, frag->size);
2815 tf->control = BMU_OWN | BMU_SW | control | frag->size;
2817 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2819 /* Make sure all the descriptors written */
2821 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2824 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2826 if (unlikely(netif_msg_tx_queued(skge)))
2827 printk(KERN_DEBUG "%s: tx queued, slot %td, len %d\n",
2828 dev->name, e - skge->tx_ring.start, skb->len);
2830 skge->tx_ring.to_use = e->next;
2833 if (skge_avail(&skge->tx_ring) <= TX_LOW_WATER) {
2834 pr_debug("%s: transmit queue full\n", dev->name);
2835 netif_stop_queue(dev);
2838 dev->trans_start = jiffies;
2840 return NETDEV_TX_OK;
2844 /* Free resources associated with this reing element */
2845 static void skge_tx_free(struct skge_port *skge, struct skge_element *e,
2848 struct pci_dev *pdev = skge->hw->pdev;
2850 /* skb header vs. fragment */
2851 if (control & BMU_STF)
2852 pci_unmap_single(pdev, pci_unmap_addr(e, mapaddr),
2853 pci_unmap_len(e, maplen),
2856 pci_unmap_page(pdev, pci_unmap_addr(e, mapaddr),
2857 pci_unmap_len(e, maplen),
2860 if (control & BMU_EOF) {
2861 if (unlikely(netif_msg_tx_done(skge)))
2862 printk(KERN_DEBUG PFX "%s: tx done slot %td\n",
2863 skge->netdev->name, e - skge->tx_ring.start);
2865 dev_kfree_skb(e->skb);
2869 /* Free all buffers in transmit ring */
2870 static void skge_tx_clean(struct net_device *dev)
2872 struct skge_port *skge = netdev_priv(dev);
2873 struct skge_element *e;
2875 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
2876 struct skge_tx_desc *td = e->desc;
2877 skge_tx_free(skge, e, td->control);
2881 skge->tx_ring.to_clean = e;
2882 netif_wake_queue(dev);
2885 static void skge_tx_timeout(struct net_device *dev)
2887 struct skge_port *skge = netdev_priv(dev);
2889 if (netif_msg_timer(skge))
2890 printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name);
2892 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
2896 static int skge_change_mtu(struct net_device *dev, int new_mtu)
2898 struct skge_port *skge = netdev_priv(dev);
2899 struct skge_hw *hw = skge->hw;
2900 int port = skge->port;
2904 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2907 if (!netif_running(dev)) {
2912 skge_write32(hw, B0_IMSK, 0);
2913 dev->trans_start = jiffies; /* prevent tx timeout */
2914 netif_stop_queue(dev);
2915 napi_disable(&skge->napi);
2917 ctl = gma_read16(hw, port, GM_GP_CTRL);
2918 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
2920 skge_rx_clean(skge);
2921 skge_rx_stop(hw, port);
2925 reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2927 reg |= GM_SMOD_JUMBO_ENA;
2928 gma_write16(hw, port, GM_SERIAL_MODE, reg);
2930 skge_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
2932 err = skge_rx_fill(dev);
2935 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
2936 skge_write32(hw, B0_IMSK, hw->intr_mask);
2941 gma_write16(hw, port, GM_GP_CTRL, ctl);
2943 napi_enable(&skge->napi);
2944 netif_wake_queue(dev);
2950 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
2952 static void genesis_add_filter(u8 filter[8], const u8 *addr)
2956 crc = ether_crc_le(ETH_ALEN, addr);
2958 filter[bit/8] |= 1 << (bit%8);
2961 static void genesis_set_multicast(struct net_device *dev)
2963 struct skge_port *skge = netdev_priv(dev);
2964 struct skge_hw *hw = skge->hw;
2965 int port = skge->port;
2966 int i, count = dev->mc_count;
2967 struct dev_mc_list *list = dev->mc_list;
2971 mode = xm_read32(hw, port, XM_MODE);
2972 mode |= XM_MD_ENA_HASH;
2973 if (dev->flags & IFF_PROMISC)
2974 mode |= XM_MD_ENA_PROM;
2976 mode &= ~XM_MD_ENA_PROM;
2978 if (dev->flags & IFF_ALLMULTI)
2979 memset(filter, 0xff, sizeof(filter));
2981 memset(filter, 0, sizeof(filter));
2983 if (skge->flow_status == FLOW_STAT_REM_SEND
2984 || skge->flow_status == FLOW_STAT_SYMMETRIC)
2985 genesis_add_filter(filter, pause_mc_addr);
2987 for (i = 0; list && i < count; i++, list = list->next)
2988 genesis_add_filter(filter, list->dmi_addr);
2991 xm_write32(hw, port, XM_MODE, mode);
2992 xm_outhash(hw, port, XM_HSM, filter);
2995 static void yukon_add_filter(u8 filter[8], const u8 *addr)
2997 u32 bit = ether_crc(ETH_ALEN, addr) & 0x3f;
2998 filter[bit/8] |= 1 << (bit%8);
3001 static void yukon_set_multicast(struct net_device *dev)
3003 struct skge_port *skge = netdev_priv(dev);
3004 struct skge_hw *hw = skge->hw;
3005 int port = skge->port;
3006 struct dev_mc_list *list = dev->mc_list;
3007 int rx_pause = (skge->flow_status == FLOW_STAT_REM_SEND
3008 || skge->flow_status == FLOW_STAT_SYMMETRIC);
3012 memset(filter, 0, sizeof(filter));
3014 reg = gma_read16(hw, port, GM_RX_CTRL);
3015 reg |= GM_RXCR_UCF_ENA;
3017 if (dev->flags & IFF_PROMISC) /* promiscuous */
3018 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
3019 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
3020 memset(filter, 0xff, sizeof(filter));
3021 else if (dev->mc_count == 0 && !rx_pause)/* no multicast */
3022 reg &= ~GM_RXCR_MCF_ENA;
3025 reg |= GM_RXCR_MCF_ENA;
3028 yukon_add_filter(filter, pause_mc_addr);
3030 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3031 yukon_add_filter(filter, list->dmi_addr);
3035 gma_write16(hw, port, GM_MC_ADDR_H1,
3036 (u16)filter[0] | ((u16)filter[1] << 8));
3037 gma_write16(hw, port, GM_MC_ADDR_H2,
3038 (u16)filter[2] | ((u16)filter[3] << 8));
3039 gma_write16(hw, port, GM_MC_ADDR_H3,
3040 (u16)filter[4] | ((u16)filter[5] << 8));
3041 gma_write16(hw, port, GM_MC_ADDR_H4,
3042 (u16)filter[6] | ((u16)filter[7] << 8));
3044 gma_write16(hw, port, GM_RX_CTRL, reg);
3047 static inline u16 phy_length(const struct skge_hw *hw, u32 status)
3049 if (hw->chip_id == CHIP_ID_GENESIS)
3050 return status >> XMR_FS_LEN_SHIFT;
3052 return status >> GMR_FS_LEN_SHIFT;
3055 static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
3057 if (hw->chip_id == CHIP_ID_GENESIS)
3058 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
3060 return (status & GMR_FS_ANY_ERR) ||
3061 (status & GMR_FS_RX_OK) == 0;
3065 /* Get receive buffer from descriptor.
3066 * Handles copy of small buffers and reallocation failures
3068 static struct sk_buff *skge_rx_get(struct net_device *dev,
3069 struct skge_element *e,
3070 u32 control, u32 status, u16 csum)
3072 struct skge_port *skge = netdev_priv(dev);
3073 struct sk_buff *skb;
3074 u16 len = control & BMU_BBC;
3076 if (unlikely(netif_msg_rx_status(skge)))
3077 printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n",
3078 dev->name, e - skge->rx_ring.start,
3081 if (len > skge->rx_buf_size)
3084 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
3087 if (bad_phy_status(skge->hw, status))
3090 if (phy_length(skge->hw, status) != len)
3093 if (len < RX_COPY_THRESHOLD) {
3094 skb = netdev_alloc_skb(dev, len + 2);
3098 skb_reserve(skb, 2);
3099 pci_dma_sync_single_for_cpu(skge->hw->pdev,
3100 pci_unmap_addr(e, mapaddr),
3101 len, PCI_DMA_FROMDEVICE);
3102 skb_copy_from_linear_data(e->skb, skb->data, len);
3103 pci_dma_sync_single_for_device(skge->hw->pdev,
3104 pci_unmap_addr(e, mapaddr),
3105 len, PCI_DMA_FROMDEVICE);
3106 skge_rx_reuse(e, skge->rx_buf_size);
3108 struct sk_buff *nskb;
3109 nskb = netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN);
3113 skb_reserve(nskb, NET_IP_ALIGN);
3114 pci_unmap_single(skge->hw->pdev,
3115 pci_unmap_addr(e, mapaddr),
3116 pci_unmap_len(e, maplen),
3117 PCI_DMA_FROMDEVICE);
3119 prefetch(skb->data);
3120 skge_rx_setup(skge, e, nskb, skge->rx_buf_size);
3124 if (skge->rx_csum) {
3126 skb->ip_summed = CHECKSUM_COMPLETE;
3129 skb->protocol = eth_type_trans(skb, dev);
3134 if (netif_msg_rx_err(skge))
3135 printk(KERN_DEBUG PFX "%s: rx err, slot %td control 0x%x status 0x%x\n",
3136 dev->name, e - skge->rx_ring.start,
3139 if (skge->hw->chip_id == CHIP_ID_GENESIS) {
3140 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
3141 dev->stats.rx_length_errors++;
3142 if (status & XMR_FS_FRA_ERR)
3143 dev->stats.rx_frame_errors++;
3144 if (status & XMR_FS_FCS_ERR)
3145 dev->stats.rx_crc_errors++;
3147 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
3148 dev->stats.rx_length_errors++;
3149 if (status & GMR_FS_FRAGMENT)
3150 dev->stats.rx_frame_errors++;
3151 if (status & GMR_FS_CRC_ERR)
3152 dev->stats.rx_crc_errors++;
3156 skge_rx_reuse(e, skge->rx_buf_size);
3160 /* Free all buffers in Tx ring which are no longer owned by device */
3161 static void skge_tx_done(struct net_device *dev)
3163 struct skge_port *skge = netdev_priv(dev);
3164 struct skge_ring *ring = &skge->tx_ring;
3165 struct skge_element *e;
3167 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
3169 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
3170 u32 control = ((const struct skge_tx_desc *) e->desc)->control;
3172 if (control & BMU_OWN)
3175 skge_tx_free(skge, e, control);
3177 skge->tx_ring.to_clean = e;
3179 /* Can run lockless until we need to synchronize to restart queue. */
3182 if (unlikely(netif_queue_stopped(dev) &&
3183 skge_avail(&skge->tx_ring) > TX_LOW_WATER)) {
3185 if (unlikely(netif_queue_stopped(dev) &&
3186 skge_avail(&skge->tx_ring) > TX_LOW_WATER)) {
3187 netif_wake_queue(dev);
3190 netif_tx_unlock(dev);
3194 static int skge_poll(struct napi_struct *napi, int to_do)
3196 struct skge_port *skge = container_of(napi, struct skge_port, napi);
3197 struct net_device *dev = skge->netdev;
3198 struct skge_hw *hw = skge->hw;
3199 struct skge_ring *ring = &skge->rx_ring;
3200 struct skge_element *e;
3205 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
3207 for (e = ring->to_clean; prefetch(e->next), work_done < to_do; e = e->next) {
3208 struct skge_rx_desc *rd = e->desc;
3209 struct sk_buff *skb;
3213 control = rd->control;
3214 if (control & BMU_OWN)
3217 skb = skge_rx_get(dev, e, control, rd->status, rd->csum2);
3219 dev->last_rx = jiffies;
3220 netif_receive_skb(skb);
3227 /* restart receiver */
3229 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START);
3231 if (work_done < to_do) {
3232 spin_lock_irq(&hw->hw_lock);
3233 __netif_rx_complete(dev, napi);
3234 hw->intr_mask |= napimask[skge->port];
3235 skge_write32(hw, B0_IMSK, hw->intr_mask);
3236 skge_read32(hw, B0_IMSK);
3237 spin_unlock_irq(&hw->hw_lock);
3243 /* Parity errors seem to happen when Genesis is connected to a switch
3244 * with no other ports present. Heartbeat error??
3246 static void skge_mac_parity(struct skge_hw *hw, int port)
3248 struct net_device *dev = hw->dev[port];
3250 ++dev->stats.tx_heartbeat_errors;
3252 if (hw->chip_id == CHIP_ID_GENESIS)
3253 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
3256 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
3257 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
3258 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
3259 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
3262 static void skge_mac_intr(struct skge_hw *hw, int port)
3264 if (hw->chip_id == CHIP_ID_GENESIS)
3265 genesis_mac_intr(hw, port);
3267 yukon_mac_intr(hw, port);
3270 /* Handle device specific framing and timeout interrupts */
3271 static void skge_error_irq(struct skge_hw *hw)
3273 struct pci_dev *pdev = hw->pdev;
3274 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3276 if (hw->chip_id == CHIP_ID_GENESIS) {
3277 /* clear xmac errors */
3278 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
3279 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);
3280 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
3281 skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);
3283 /* Timestamp (unused) overflow */
3284 if (hwstatus & IS_IRQ_TIST_OV)
3285 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
3288 if (hwstatus & IS_RAM_RD_PAR) {
3289 dev_err(&pdev->dev, "Ram read data parity error\n");
3290 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
3293 if (hwstatus & IS_RAM_WR_PAR) {
3294 dev_err(&pdev->dev, "Ram write data parity error\n");
3295 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
3298 if (hwstatus & IS_M1_PAR_ERR)
3299 skge_mac_parity(hw, 0);
3301 if (hwstatus & IS_M2_PAR_ERR)
3302 skge_mac_parity(hw, 1);
3304 if (hwstatus & IS_R1_PAR_ERR) {
3305 dev_err(&pdev->dev, "%s: receive queue parity error\n",
3307 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
3310 if (hwstatus & IS_R2_PAR_ERR) {
3311 dev_err(&pdev->dev, "%s: receive queue parity error\n",
3313 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
3316 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
3317 u16 pci_status, pci_cmd;
3319 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
3320 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
3322 dev_err(&pdev->dev, "PCI error cmd=%#x status=%#x\n",
3323 pci_cmd, pci_status);
3325 /* Write the error bits back to clear them. */
3326 pci_status &= PCI_STATUS_ERROR_BITS;
3327 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3328 pci_write_config_word(pdev, PCI_COMMAND,
3329 pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
3330 pci_write_config_word(pdev, PCI_STATUS, pci_status);
3331 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3333 /* if error still set then just ignore it */
3334 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3335 if (hwstatus & IS_IRQ_STAT) {
3336 dev_warn(&hw->pdev->dev, "unable to clear error (so ignoring them)\n");
3337 hw->intr_mask &= ~IS_HW_ERR;
3343 * Interrupt from PHY are handled in tasklet (softirq)
3344 * because accessing phy registers requires spin wait which might
3345 * cause excess interrupt latency.
3347 static void skge_extirq(unsigned long arg)
3349 struct skge_hw *hw = (struct skge_hw *) arg;
3352 for (port = 0; port < hw->ports; port++) {
3353 struct net_device *dev = hw->dev[port];
3355 if (netif_running(dev)) {
3356 struct skge_port *skge = netdev_priv(dev);
3358 spin_lock(&hw->phy_lock);
3359 if (hw->chip_id != CHIP_ID_GENESIS)
3360 yukon_phy_intr(skge);
3361 else if (hw->phy_type == SK_PHY_BCOM)
3362 bcom_phy_intr(skge);
3363 spin_unlock(&hw->phy_lock);
3367 spin_lock_irq(&hw->hw_lock);
3368 hw->intr_mask |= IS_EXT_REG;
3369 skge_write32(hw, B0_IMSK, hw->intr_mask);
3370 skge_read32(hw, B0_IMSK);
3371 spin_unlock_irq(&hw->hw_lock);
3374 static irqreturn_t skge_intr(int irq, void *dev_id)
3376 struct skge_hw *hw = dev_id;
3380 spin_lock(&hw->hw_lock);
3381 /* Reading this register masks IRQ */
3382 status = skge_read32(hw, B0_SP_ISRC);
3383 if (status == 0 || status == ~0)
3387 status &= hw->intr_mask;
3388 if (status & IS_EXT_REG) {
3389 hw->intr_mask &= ~IS_EXT_REG;
3390 tasklet_schedule(&hw->phy_task);
3393 if (status & (IS_XA1_F|IS_R1_F)) {
3394 struct skge_port *skge = netdev_priv(hw->dev[0]);
3395 hw->intr_mask &= ~(IS_XA1_F|IS_R1_F);
3396 netif_rx_schedule(hw->dev[0], &skge->napi);
3399 if (status & IS_PA_TO_TX1)
3400 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
3402 if (status & IS_PA_TO_RX1) {
3403 ++hw->dev[0]->stats.rx_over_errors;
3404 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
3408 if (status & IS_MAC1)
3409 skge_mac_intr(hw, 0);
3412 struct skge_port *skge = netdev_priv(hw->dev[1]);
3414 if (status & (IS_XA2_F|IS_R2_F)) {
3415 hw->intr_mask &= ~(IS_XA2_F|IS_R2_F);
3416 netif_rx_schedule(hw->dev[1], &skge->napi);
3419 if (status & IS_PA_TO_RX2) {
3420 ++hw->dev[1]->stats.rx_over_errors;
3421 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
3424 if (status & IS_PA_TO_TX2)
3425 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
3427 if (status & IS_MAC2)
3428 skge_mac_intr(hw, 1);
3431 if (status & IS_HW_ERR)
3434 skge_write32(hw, B0_IMSK, hw->intr_mask);
3435 skge_read32(hw, B0_IMSK);
3437 spin_unlock(&hw->hw_lock);
3439 return IRQ_RETVAL(handled);
3442 #ifdef CONFIG_NET_POLL_CONTROLLER
3443 static void skge_netpoll(struct net_device *dev)
3445 struct skge_port *skge = netdev_priv(dev);
3447 disable_irq(dev->irq);
3448 skge_intr(dev->irq, skge->hw);
3449 enable_irq(dev->irq);
3453 static int skge_set_mac_address(struct net_device *dev, void *p)
3455 struct skge_port *skge = netdev_priv(dev);
3456 struct skge_hw *hw = skge->hw;
3457 unsigned port = skge->port;
3458 const struct sockaddr *addr = p;
3461 if (!is_valid_ether_addr(addr->sa_data))
3462 return -EADDRNOTAVAIL;
3464 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3466 if (!netif_running(dev)) {
3467 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3468 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
3471 spin_lock_bh(&hw->phy_lock);
3472 ctrl = gma_read16(hw, port, GM_GP_CTRL);
3473 gma_write16(hw, port, GM_GP_CTRL, ctrl & ~GM_GPCR_RX_ENA);
3475 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3476 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
3478 if (hw->chip_id == CHIP_ID_GENESIS)
3479 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
3481 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3482 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3485 gma_write16(hw, port, GM_GP_CTRL, ctrl);
3486 spin_unlock_bh(&hw->phy_lock);
3492 static const struct {
3496 { CHIP_ID_GENESIS, "Genesis" },
3497 { CHIP_ID_YUKON, "Yukon" },
3498 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
3499 { CHIP_ID_YUKON_LP, "Yukon-LP"},
3502 static const char *skge_board_name(const struct skge_hw *hw)
3505 static char buf[16];
3507 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
3508 if (skge_chips[i].id == hw->chip_id)
3509 return skge_chips[i].name;
3511 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
3517 * Setup the board data structure, but don't bring up
3520 static int skge_reset(struct skge_hw *hw)
3523 u16 ctst, pci_status;
3524 u8 t8, mac_cfg, pmd_type;
3527 ctst = skge_read16(hw, B0_CTST);
3530 skge_write8(hw, B0_CTST, CS_RST_SET);
3531 skge_write8(hw, B0_CTST, CS_RST_CLR);
3533 /* clear PCI errors, if any */
3534 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3535 skge_write8(hw, B2_TST_CTRL2, 0);
3537 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status);
3538 pci_write_config_word(hw->pdev, PCI_STATUS,
3539 pci_status | PCI_STATUS_ERROR_BITS);
3540 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3541 skge_write8(hw, B0_CTST, CS_MRST_CLR);
3543 /* restore CLK_RUN bits (for Yukon-Lite) */
3544 skge_write16(hw, B0_CTST,
3545 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
3547 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
3548 hw->phy_type = skge_read8(hw, B2_E_1) & 0xf;
3549 pmd_type = skge_read8(hw, B2_PMD_TYP);
3550 hw->copper = (pmd_type == 'T' || pmd_type == '1');
3552 switch (hw->chip_id) {
3553 case CHIP_ID_GENESIS:
3554 switch (hw->phy_type) {
3556 hw->phy_addr = PHY_ADDR_XMAC;
3559 hw->phy_addr = PHY_ADDR_BCOM;
3562 dev_err(&hw->pdev->dev, "unsupported phy type 0x%x\n",
3569 case CHIP_ID_YUKON_LITE:
3570 case CHIP_ID_YUKON_LP:
3571 if (hw->phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
3574 hw->phy_addr = PHY_ADDR_MARV;
3578 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3583 mac_cfg = skge_read8(hw, B2_MAC_CFG);
3584 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
3585 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
3587 /* read the adapters RAM size */
3588 t8 = skge_read8(hw, B2_E_0);
3589 if (hw->chip_id == CHIP_ID_GENESIS) {
3591 /* special case: 4 x 64k x 36, offset = 0x80000 */
3592 hw->ram_size = 1024;
3593 hw->ram_offset = 512;
3595 hw->ram_size = t8 * 512;
3597 hw->ram_size = t8 ? t8 * 4 : 128;
3599 hw->intr_mask = IS_HW_ERR;
3601 /* Use PHY IRQ for all but fiber based Genesis board */
3602 if (!(hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC))
3603 hw->intr_mask |= IS_EXT_REG;
3605 if (hw->chip_id == CHIP_ID_GENESIS)
3608 /* switch power to VCC (WA for VAUX problem) */
3609 skge_write8(hw, B0_POWER_CTRL,
3610 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
3612 /* avoid boards with stuck Hardware error bits */
3613 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
3614 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
3615 dev_warn(&hw->pdev->dev, "stuck hardware sensor bit\n");
3616 hw->intr_mask &= ~IS_HW_ERR;
3619 /* Clear PHY COMA */
3620 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3621 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, ®);
3622 reg &= ~PCI_PHY_COMA;
3623 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);
3624 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3627 for (i = 0; i < hw->ports; i++) {
3628 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3629 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
3633 /* turn off hardware timer (unused) */
3634 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
3635 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3636 skge_write8(hw, B0_LED, LED_STAT_ON);
3638 /* enable the Tx Arbiters */
3639 for (i = 0; i < hw->ports; i++)
3640 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3642 /* Initialize ram interface */
3643 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
3645 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
3646 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
3647 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
3648 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
3649 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
3650 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
3651 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
3652 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
3653 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
3654 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
3655 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
3656 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
3658 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
3660 /* Set interrupt moderation for Transmit only
3661 * Receive interrupts avoided by NAPI
3663 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3664 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3665 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3667 skge_write32(hw, B0_IMSK, hw->intr_mask);
3669 for (i = 0; i < hw->ports; i++) {
3670 if (hw->chip_id == CHIP_ID_GENESIS)
3671 genesis_reset(hw, i);
3679 /* Initialize network device */
3680 static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3683 struct skge_port *skge;
3684 struct net_device *dev = alloc_etherdev(sizeof(*skge));
3687 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
3691 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3692 dev->open = skge_up;
3693 dev->stop = skge_down;
3694 dev->do_ioctl = skge_ioctl;
3695 dev->hard_start_xmit = skge_xmit_frame;
3696 dev->get_stats = skge_get_stats;
3697 if (hw->chip_id == CHIP_ID_GENESIS)
3698 dev->set_multicast_list = genesis_set_multicast;
3700 dev->set_multicast_list = yukon_set_multicast;
3702 dev->set_mac_address = skge_set_mac_address;
3703 dev->change_mtu = skge_change_mtu;
3704 SET_ETHTOOL_OPS(dev, &skge_ethtool_ops);
3705 dev->tx_timeout = skge_tx_timeout;
3706 dev->watchdog_timeo = TX_WATCHDOG;
3707 #ifdef CONFIG_NET_POLL_CONTROLLER
3708 dev->poll_controller = skge_netpoll;
3710 dev->irq = hw->pdev->irq;
3713 dev->features |= NETIF_F_HIGHDMA;
3715 skge = netdev_priv(dev);
3716 netif_napi_add(dev, &skge->napi, skge_poll, NAPI_WEIGHT);
3719 skge->msg_enable = netif_msg_init(debug, default_msg);
3721 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3722 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3724 /* Auto speed and flow control */
3725 skge->autoneg = AUTONEG_ENABLE;
3726 skge->flow_control = FLOW_MODE_SYM_OR_REM;
3729 skge->advertising = skge_supported_modes(hw);
3731 if (pci_wake_enabled(hw->pdev))
3732 skge->wol = wol_supported(hw) & WAKE_MAGIC;
3734 hw->dev[port] = dev;
3738 /* Only used for Genesis XMAC */
3739 setup_timer(&skge->link_timer, xm_link_timer, (unsigned long) skge);
3741 if (hw->chip_id != CHIP_ID_GENESIS) {
3742 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3746 /* read the mac address */
3747 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
3748 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3750 /* device is off until link detection */
3751 netif_carrier_off(dev);
3752 netif_stop_queue(dev);
3757 static void __devinit skge_show_addr(struct net_device *dev)
3759 const struct skge_port *skge = netdev_priv(dev);
3760 DECLARE_MAC_BUF(mac);
3762 if (netif_msg_probe(skge))
3763 printk(KERN_INFO PFX "%s: addr %s\n",
3764 dev->name, print_mac(mac, dev->dev_addr));
3767 static int __devinit skge_probe(struct pci_dev *pdev,
3768 const struct pci_device_id *ent)
3770 struct net_device *dev, *dev1;
3772 int err, using_dac = 0;
3774 err = pci_enable_device(pdev);
3776 dev_err(&pdev->dev, "cannot enable PCI device\n");
3780 err = pci_request_regions(pdev, DRV_NAME);
3782 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
3783 goto err_out_disable_pdev;
3786 pci_set_master(pdev);
3788 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3790 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3791 } else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
3793 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3797 dev_err(&pdev->dev, "no usable DMA configuration\n");
3798 goto err_out_free_regions;
3802 /* byte swap descriptors in hardware */
3806 pci_read_config_dword(pdev, PCI_DEV_REG2, ®);
3807 reg |= PCI_REV_DESC;
3808 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3813 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
3815 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
3816 goto err_out_free_regions;
3820 spin_lock_init(&hw->hw_lock);
3821 spin_lock_init(&hw->phy_lock);
3822 tasklet_init(&hw->phy_task, &skge_extirq, (unsigned long) hw);
3824 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3826 dev_err(&pdev->dev, "cannot map device registers\n");
3827 goto err_out_free_hw;
3830 err = skge_reset(hw);
3832 goto err_out_iounmap;
3834 printk(KERN_INFO PFX DRV_VERSION " addr 0x%llx irq %d chip %s rev %d\n",
3835 (unsigned long long)pci_resource_start(pdev, 0), pdev->irq,
3836 skge_board_name(hw), hw->chip_rev);
3838 dev = skge_devinit(hw, 0, using_dac);
3840 goto err_out_led_off;
3842 /* Some motherboards are broken and has zero in ROM. */
3843 if (!is_valid_ether_addr(dev->dev_addr))
3844 dev_warn(&pdev->dev, "bad (zero?) ethernet address in rom\n");
3846 err = register_netdev(dev);
3848 dev_err(&pdev->dev, "cannot register net device\n");
3849 goto err_out_free_netdev;
3852 err = request_irq(pdev->irq, skge_intr, IRQF_SHARED, dev->name, hw);
3854 dev_err(&pdev->dev, "%s: cannot assign irq %d\n",
3855 dev->name, pdev->irq);
3856 goto err_out_unregister;
3858 skge_show_addr(dev);
3860 if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) {
3861 if (register_netdev(dev1) == 0)
3862 skge_show_addr(dev1);
3864 /* Failure to register second port need not be fatal */
3865 dev_warn(&pdev->dev, "register of second port failed\n");
3870 pci_set_drvdata(pdev, hw);
3875 unregister_netdev(dev);
3876 err_out_free_netdev:
3879 skge_write16(hw, B0_LED, LED_STAT_OFF);
3884 err_out_free_regions:
3885 pci_release_regions(pdev);
3886 err_out_disable_pdev:
3887 pci_disable_device(pdev);
3888 pci_set_drvdata(pdev, NULL);
3893 static void __devexit skge_remove(struct pci_dev *pdev)
3895 struct skge_hw *hw = pci_get_drvdata(pdev);
3896 struct net_device *dev0, *dev1;
3901 flush_scheduled_work();
3903 if ((dev1 = hw->dev[1]))
3904 unregister_netdev(dev1);
3906 unregister_netdev(dev0);
3908 tasklet_disable(&hw->phy_task);
3910 spin_lock_irq(&hw->hw_lock);
3912 skge_write32(hw, B0_IMSK, 0);
3913 skge_read32(hw, B0_IMSK);
3914 spin_unlock_irq(&hw->hw_lock);
3916 skge_write16(hw, B0_LED, LED_STAT_OFF);
3917 skge_write8(hw, B0_CTST, CS_RST_SET);
3919 free_irq(pdev->irq, hw);
3920 pci_release_regions(pdev);
3921 pci_disable_device(pdev);
3928 pci_set_drvdata(pdev, NULL);
3932 static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
3934 struct skge_hw *hw = pci_get_drvdata(pdev);
3935 int i, err, wol = 0;
3940 err = pci_save_state(pdev);
3944 for (i = 0; i < hw->ports; i++) {
3945 struct net_device *dev = hw->dev[i];
3946 struct skge_port *skge = netdev_priv(dev);
3948 if (netif_running(dev))
3951 skge_wol_init(skge);
3956 skge_write32(hw, B0_IMSK, 0);
3957 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
3958 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3963 static int skge_resume(struct pci_dev *pdev)
3965 struct skge_hw *hw = pci_get_drvdata(pdev);
3971 err = pci_set_power_state(pdev, PCI_D0);
3975 err = pci_restore_state(pdev);
3979 pci_enable_wake(pdev, PCI_D0, 0);
3981 err = skge_reset(hw);
3985 for (i = 0; i < hw->ports; i++) {
3986 struct net_device *dev = hw->dev[i];
3988 if (netif_running(dev)) {
3992 printk(KERN_ERR PFX "%s: could not up: %d\n",
4004 static void skge_shutdown(struct pci_dev *pdev)
4006 struct skge_hw *hw = pci_get_drvdata(pdev);
4012 for (i = 0; i < hw->ports; i++) {
4013 struct net_device *dev = hw->dev[i];
4014 struct skge_port *skge = netdev_priv(dev);
4017 skge_wol_init(skge);
4021 pci_enable_wake(pdev, PCI_D3hot, wol);
4022 pci_enable_wake(pdev, PCI_D3cold, wol);
4024 pci_disable_device(pdev);
4025 pci_set_power_state(pdev, PCI_D3hot);
4029 static struct pci_driver skge_driver = {
4031 .id_table = skge_id_table,
4032 .probe = skge_probe,
4033 .remove = __devexit_p(skge_remove),
4035 .suspend = skge_suspend,
4036 .resume = skge_resume,
4038 .shutdown = skge_shutdown,
4041 static int __init skge_init_module(void)
4043 return pci_register_driver(&skge_driver);
4046 static void __exit skge_cleanup_module(void)
4048 pci_unregister_driver(&skge_driver);
4051 module_init(skge_init_module);
4052 module_exit(skge_cleanup_module);