2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
27 #include <linux/crc32.h>
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/netdevice.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/etherdevice.h>
33 #include <linux/ethtool.h>
34 #include <linux/pci.h>
35 #include <linux/interrupt.h>
37 #include <linux/slab.h>
39 #include <linux/tcp.h>
41 #include <linux/delay.h>
42 #include <linux/workqueue.h>
43 #include <linux/if_vlan.h>
44 #include <linux/prefetch.h>
45 #include <linux/debugfs.h>
46 #include <linux/mii.h>
52 #define DRV_NAME "sky2"
53 #define DRV_VERSION "1.28"
56 * The Yukon II chipset takes 64 bit command blocks (called list elements)
57 * that are organized into three (receive, transmit, status) different rings
61 #define RX_LE_SIZE 1024
62 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
63 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
64 #define RX_DEF_PENDING RX_MAX_PENDING
66 /* This is the worst case number of transmit list elements for a single skb:
67 VLAN:GSO + CKSUM + Data + skb_frags * DMA */
68 #define MAX_SKB_TX_LE (2 + (sizeof(dma_addr_t)/sizeof(u32))*(MAX_SKB_FRAGS+1))
69 #define TX_MIN_PENDING (MAX_SKB_TX_LE+1)
70 #define TX_MAX_PENDING 1024
71 #define TX_DEF_PENDING 127
73 #define TX_WATCHDOG (5 * HZ)
74 #define NAPI_WEIGHT 64
75 #define PHY_RETRIES 1000
77 #define SKY2_EEPROM_MAGIC 0x9955aabb
79 #define RING_NEXT(x, s) (((x)+1) & ((s)-1))
81 static const u32 default_msg =
82 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
83 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
84 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
86 static int debug = -1; /* defaults above */
87 module_param(debug, int, 0);
88 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
90 static int copybreak __read_mostly = 128;
91 module_param(copybreak, int, 0);
92 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
94 static int disable_msi = 0;
95 module_param(disable_msi, int, 0);
96 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
98 static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
99 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
100 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
101 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E01) }, /* SK-9E21M */
102 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
103 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
104 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
106 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
107 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4381) }, /* 88E8059 */
143 MODULE_DEVICE_TABLE(pci, sky2_id_table);
145 /* Avoid conditionals by using array */
146 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
147 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
148 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
150 static void sky2_set_multicast(struct net_device *dev);
152 /* Access to PHY via serial interconnect */
153 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
157 gma_write16(hw, port, GM_SMI_DATA, val);
158 gma_write16(hw, port, GM_SMI_CTRL,
159 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
161 for (i = 0; i < PHY_RETRIES; i++) {
162 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
166 if (!(ctrl & GM_SMI_CT_BUSY))
172 dev_warn(&hw->pdev->dev, "%s: phy write timeout\n", hw->dev[port]->name);
176 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
180 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
184 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
185 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
187 for (i = 0; i < PHY_RETRIES; i++) {
188 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
192 if (ctrl & GM_SMI_CT_RD_VAL) {
193 *val = gma_read16(hw, port, GM_SMI_DATA);
200 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
203 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
207 static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
210 __gm_phy_read(hw, port, reg, &v);
215 static void sky2_power_on(struct sky2_hw *hw)
217 /* switch power to VCC (WA for VAUX problem) */
218 sky2_write8(hw, B0_POWER_CTRL,
219 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
221 /* disable Core Clock Division, */
222 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
224 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
225 /* enable bits are inverted */
226 sky2_write8(hw, B2_Y2_CLK_GATE,
227 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
228 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
229 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
231 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
233 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
236 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
238 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
239 /* set all bits to 0 except bits 15..12 and 8 */
240 reg &= P_ASPM_CONTROL_MSK;
241 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
243 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
244 /* set all bits to 0 except bits 28 & 27 */
245 reg &= P_CTL_TIM_VMAIN_AV_MSK;
246 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
248 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
250 sky2_write16(hw, B0_CTST, Y2_HW_WOL_ON);
252 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
253 reg = sky2_read32(hw, B2_GP_IO);
254 reg |= GLB_GPIO_STAT_RACE_DIS;
255 sky2_write32(hw, B2_GP_IO, reg);
257 sky2_read32(hw, B2_GP_IO);
260 /* Turn on "driver loaded" LED */
261 sky2_write16(hw, B0_CTST, Y2_LED_STAT_ON);
264 static void sky2_power_aux(struct sky2_hw *hw)
266 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
267 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
269 /* enable bits are inverted */
270 sky2_write8(hw, B2_Y2_CLK_GATE,
271 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
272 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
273 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
275 /* switch power to VAUX if supported and PME from D3cold */
276 if ( (sky2_read32(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
277 pci_pme_capable(hw->pdev, PCI_D3cold))
278 sky2_write8(hw, B0_POWER_CTRL,
279 (PC_VAUX_ENA | PC_VCC_ENA |
280 PC_VAUX_ON | PC_VCC_OFF));
282 /* turn off "driver loaded LED" */
283 sky2_write16(hw, B0_CTST, Y2_LED_STAT_OFF);
286 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
290 /* disable all GMAC IRQ's */
291 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
293 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
294 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
295 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
296 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
298 reg = gma_read16(hw, port, GM_RX_CTRL);
299 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
300 gma_write16(hw, port, GM_RX_CTRL, reg);
303 /* flow control to advertise bits */
304 static const u16 copper_fc_adv[] = {
306 [FC_TX] = PHY_M_AN_ASP,
307 [FC_RX] = PHY_M_AN_PC,
308 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
311 /* flow control to advertise bits when using 1000BaseX */
312 static const u16 fiber_fc_adv[] = {
313 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
314 [FC_TX] = PHY_M_P_ASYM_MD_X,
315 [FC_RX] = PHY_M_P_SYM_MD_X,
316 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
319 /* flow control to GMA disable bits */
320 static const u16 gm_fc_disable[] = {
321 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
322 [FC_TX] = GM_GPCR_FC_RX_DIS,
323 [FC_RX] = GM_GPCR_FC_TX_DIS,
328 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
330 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
331 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
333 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
334 !(hw->flags & SKY2_HW_NEWER_PHY)) {
335 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
337 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
339 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
341 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
342 if (hw->chip_id == CHIP_ID_YUKON_EC)
343 /* set downshift counter to 3x and enable downshift */
344 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
346 /* set master & slave downshift counter to 1x */
347 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
349 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
352 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
353 if (sky2_is_copper(hw)) {
354 if (!(hw->flags & SKY2_HW_GIGABIT)) {
355 /* enable automatic crossover */
356 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
358 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
359 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
362 /* Enable Class A driver for FE+ A0 */
363 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
364 spec |= PHY_M_FESC_SEL_CL_A;
365 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
368 /* disable energy detect */
369 ctrl &= ~PHY_M_PC_EN_DET_MSK;
371 /* enable automatic crossover */
372 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
374 /* downshift on PHY 88E1112 and 88E1149 is changed */
375 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
376 (hw->flags & SKY2_HW_NEWER_PHY)) {
377 /* set downshift counter to 3x and enable downshift */
378 ctrl &= ~PHY_M_PC_DSC_MSK;
379 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
383 /* workaround for deviation #4.88 (CRC errors) */
384 /* disable Automatic Crossover */
386 ctrl &= ~PHY_M_PC_MDIX_MSK;
389 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
391 /* special setup for PHY 88E1112 Fiber */
392 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
393 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
395 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
396 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
397 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
398 ctrl &= ~PHY_M_MAC_MD_MSK;
399 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
400 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
402 if (hw->pmd_type == 'P') {
403 /* select page 1 to access Fiber registers */
404 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
406 /* for SFP-module set SIGDET polarity to low */
407 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
408 ctrl |= PHY_M_FIB_SIGD_POL;
409 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
412 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
420 if (sky2->flags & SKY2_FLAG_AUTO_SPEED) {
421 if (sky2_is_copper(hw)) {
422 if (sky2->advertising & ADVERTISED_1000baseT_Full)
423 ct1000 |= PHY_M_1000C_AFD;
424 if (sky2->advertising & ADVERTISED_1000baseT_Half)
425 ct1000 |= PHY_M_1000C_AHD;
426 if (sky2->advertising & ADVERTISED_100baseT_Full)
427 adv |= PHY_M_AN_100_FD;
428 if (sky2->advertising & ADVERTISED_100baseT_Half)
429 adv |= PHY_M_AN_100_HD;
430 if (sky2->advertising & ADVERTISED_10baseT_Full)
431 adv |= PHY_M_AN_10_FD;
432 if (sky2->advertising & ADVERTISED_10baseT_Half)
433 adv |= PHY_M_AN_10_HD;
435 } else { /* special defines for FIBER (88E1040S only) */
436 if (sky2->advertising & ADVERTISED_1000baseT_Full)
437 adv |= PHY_M_AN_1000X_AFD;
438 if (sky2->advertising & ADVERTISED_1000baseT_Half)
439 adv |= PHY_M_AN_1000X_AHD;
442 /* Restart Auto-negotiation */
443 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
445 /* forced speed/duplex settings */
446 ct1000 = PHY_M_1000C_MSE;
448 /* Disable auto update for duplex flow control and duplex */
449 reg |= GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_SPD_DIS;
451 switch (sky2->speed) {
453 ctrl |= PHY_CT_SP1000;
454 reg |= GM_GPCR_SPEED_1000;
457 ctrl |= PHY_CT_SP100;
458 reg |= GM_GPCR_SPEED_100;
462 if (sky2->duplex == DUPLEX_FULL) {
463 reg |= GM_GPCR_DUP_FULL;
464 ctrl |= PHY_CT_DUP_MD;
465 } else if (sky2->speed < SPEED_1000)
466 sky2->flow_mode = FC_NONE;
469 if (sky2->flags & SKY2_FLAG_AUTO_PAUSE) {
470 if (sky2_is_copper(hw))
471 adv |= copper_fc_adv[sky2->flow_mode];
473 adv |= fiber_fc_adv[sky2->flow_mode];
475 reg |= GM_GPCR_AU_FCT_DIS;
476 reg |= gm_fc_disable[sky2->flow_mode];
478 /* Forward pause packets to GMAC? */
479 if (sky2->flow_mode & FC_RX)
480 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
482 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
485 gma_write16(hw, port, GM_GP_CTRL, reg);
487 if (hw->flags & SKY2_HW_GIGABIT)
488 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
490 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
491 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
493 /* Setup Phy LED's */
494 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
497 switch (hw->chip_id) {
498 case CHIP_ID_YUKON_FE:
499 /* on 88E3082 these bits are at 11..9 (shifted left) */
500 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
502 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
504 /* delete ACT LED control bits */
505 ctrl &= ~PHY_M_FELP_LED1_MSK;
506 /* change ACT LED control to blink mode */
507 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
508 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
511 case CHIP_ID_YUKON_FE_P:
512 /* Enable Link Partner Next Page */
513 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
514 ctrl |= PHY_M_PC_ENA_LIP_NP;
516 /* disable Energy Detect and enable scrambler */
517 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
518 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
520 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
521 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
522 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
523 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
525 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
528 case CHIP_ID_YUKON_XL:
529 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
531 /* select page 3 to access LED control register */
532 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
534 /* set LED Function Control register */
535 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
536 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
537 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
538 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
539 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
541 /* set Polarity Control register */
542 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
543 (PHY_M_POLC_LS1_P_MIX(4) |
544 PHY_M_POLC_IS0_P_MIX(4) |
545 PHY_M_POLC_LOS_CTRL(2) |
546 PHY_M_POLC_INIT_CTRL(2) |
547 PHY_M_POLC_STA1_CTRL(2) |
548 PHY_M_POLC_STA0_CTRL(2)));
550 /* restore page register */
551 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
554 case CHIP_ID_YUKON_EC_U:
555 case CHIP_ID_YUKON_EX:
556 case CHIP_ID_YUKON_SUPR:
557 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
559 /* select page 3 to access LED control register */
560 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
562 /* set LED Function Control register */
563 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
564 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
565 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
566 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
567 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
569 /* set Blink Rate in LED Timer Control Register */
570 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
571 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
572 /* restore page register */
573 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
577 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
578 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
580 /* turn off the Rx LED (LED_RX) */
581 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
584 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
585 /* apply fixes in PHY AFE */
586 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
588 /* increase differential signal amplitude in 10BASE-T */
589 gm_phy_write(hw, port, 0x18, 0xaa99);
590 gm_phy_write(hw, port, 0x17, 0x2011);
592 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
593 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
594 gm_phy_write(hw, port, 0x18, 0xa204);
595 gm_phy_write(hw, port, 0x17, 0x2002);
598 /* set page register to 0 */
599 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
600 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
601 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
602 /* apply workaround for integrated resistors calibration */
603 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
604 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
605 } else if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) {
606 /* apply fixes in PHY AFE */
607 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff);
609 /* apply RDAC termination workaround */
610 gm_phy_write(hw, port, 24, 0x2800);
611 gm_phy_write(hw, port, 23, 0x2001);
613 /* set page register back to 0 */
614 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
615 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
616 hw->chip_id < CHIP_ID_YUKON_SUPR) {
617 /* no effect on Yukon-XL */
618 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
620 if (!(sky2->flags & SKY2_FLAG_AUTO_SPEED) ||
621 sky2->speed == SPEED_100) {
622 /* turn on 100 Mbps LED (LED_LINK100) */
623 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
627 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
631 /* Enable phy interrupt on auto-negotiation complete (or link up) */
632 if (sky2->flags & SKY2_FLAG_AUTO_SPEED)
633 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
635 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
638 static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
639 static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
641 static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
645 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
646 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
647 reg1 &= ~phy_power[port];
649 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
650 reg1 |= coma_mode[port];
652 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
653 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
654 sky2_pci_read32(hw, PCI_DEV_REG1);
656 if (hw->chip_id == CHIP_ID_YUKON_FE)
657 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
658 else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
659 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
662 static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
667 /* release GPHY Control reset */
668 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
670 /* release GMAC reset */
671 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
673 if (hw->flags & SKY2_HW_NEWER_PHY) {
674 /* select page 2 to access MAC control register */
675 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
677 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
678 /* allow GMII Power Down */
679 ctrl &= ~PHY_M_MAC_GMIF_PUP;
680 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
682 /* set page register back to 0 */
683 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
686 /* setup General Purpose Control Register */
687 gma_write16(hw, port, GM_GP_CTRL,
688 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 |
689 GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |
692 if (hw->chip_id != CHIP_ID_YUKON_EC) {
693 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
694 /* select page 2 to access MAC control register */
695 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
697 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
698 /* enable Power Down */
699 ctrl |= PHY_M_PC_POW_D_ENA;
700 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
702 /* set page register back to 0 */
703 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
706 /* set IEEE compatible Power Down Mode (dev. #4.99) */
707 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
710 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
711 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
712 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
713 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
714 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
718 static void sky2_enable_rx_tx(struct sky2_port *sky2)
720 struct sky2_hw *hw = sky2->hw;
721 unsigned port = sky2->port;
724 reg = gma_read16(hw, port, GM_GP_CTRL);
725 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
726 gma_write16(hw, port, GM_GP_CTRL, reg);
729 /* Force a renegotiation */
730 static void sky2_phy_reinit(struct sky2_port *sky2)
732 spin_lock_bh(&sky2->phy_lock);
733 sky2_phy_init(sky2->hw, sky2->port);
734 sky2_enable_rx_tx(sky2);
735 spin_unlock_bh(&sky2->phy_lock);
738 /* Put device in state to listen for Wake On Lan */
739 static void sky2_wol_init(struct sky2_port *sky2)
741 struct sky2_hw *hw = sky2->hw;
742 unsigned port = sky2->port;
743 enum flow_control save_mode;
746 /* Bring hardware out of reset */
747 sky2_write16(hw, B0_CTST, CS_RST_CLR);
748 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
750 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
751 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
754 * sky2_reset will re-enable on resume
756 save_mode = sky2->flow_mode;
757 ctrl = sky2->advertising;
759 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
760 sky2->flow_mode = FC_NONE;
762 spin_lock_bh(&sky2->phy_lock);
763 sky2_phy_power_up(hw, port);
764 sky2_phy_init(hw, port);
765 spin_unlock_bh(&sky2->phy_lock);
767 sky2->flow_mode = save_mode;
768 sky2->advertising = ctrl;
770 /* Set GMAC to no flow control and auto update for speed/duplex */
771 gma_write16(hw, port, GM_GP_CTRL,
772 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
773 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
775 /* Set WOL address */
776 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
777 sky2->netdev->dev_addr, ETH_ALEN);
779 /* Turn on appropriate WOL control bits */
780 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
782 if (sky2->wol & WAKE_PHY)
783 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
785 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
787 if (sky2->wol & WAKE_MAGIC)
788 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
790 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;
792 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
793 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
795 /* Disable PiG firmware */
796 sky2_write16(hw, B0_CTST, Y2_HW_WOL_OFF);
799 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
802 static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
804 struct net_device *dev = hw->dev[port];
806 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
807 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
808 hw->chip_id >= CHIP_ID_YUKON_FE_P) {
809 /* Yukon-Extreme B0 and further Extreme devices */
810 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
811 } else if (dev->mtu > ETH_DATA_LEN) {
812 /* set Tx GMAC FIFO Almost Empty Threshold */
813 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
814 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
816 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
818 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
821 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
823 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
827 const u8 *addr = hw->dev[port]->dev_addr;
829 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
830 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
832 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
834 if (hw->chip_id == CHIP_ID_YUKON_XL &&
835 hw->chip_rev == CHIP_REV_YU_XL_A0 &&
837 /* WA DEV_472 -- looks like crossed wires on port 2 */
838 /* clear GMAC 1 Control reset */
839 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
841 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
842 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
843 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
844 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
845 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
848 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
850 /* Enable Transmit FIFO Underrun */
851 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
853 spin_lock_bh(&sky2->phy_lock);
854 sky2_phy_power_up(hw, port);
855 sky2_phy_init(hw, port);
856 spin_unlock_bh(&sky2->phy_lock);
859 reg = gma_read16(hw, port, GM_PHY_ADDR);
860 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
862 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
863 gma_read16(hw, port, i);
864 gma_write16(hw, port, GM_PHY_ADDR, reg);
866 /* transmit control */
867 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
869 /* receive control reg: unicast + multicast + no FCS */
870 gma_write16(hw, port, GM_RX_CTRL,
871 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
873 /* transmit flow control */
874 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
876 /* transmit parameter */
877 gma_write16(hw, port, GM_TX_PARAM,
878 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
879 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
880 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
881 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
883 /* serial mode register */
884 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
885 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
887 if (hw->dev[port]->mtu > ETH_DATA_LEN)
888 reg |= GM_SMOD_JUMBO_ENA;
890 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
891 hw->chip_rev == CHIP_REV_YU_EC_U_B1)
892 reg |= GM_NEW_FLOW_CTRL;
894 gma_write16(hw, port, GM_SERIAL_MODE, reg);
896 /* virtual address for data */
897 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
899 /* physical address: used for pause frames */
900 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
902 /* ignore counter overflows */
903 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
904 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
905 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
907 /* Configure Rx MAC FIFO */
908 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
909 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
910 if (hw->chip_id == CHIP_ID_YUKON_EX ||
911 hw->chip_id == CHIP_ID_YUKON_FE_P)
912 rx_reg |= GMF_RX_OVER_ON;
914 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
916 if (hw->chip_id == CHIP_ID_YUKON_XL) {
917 /* Hardware errata - clear flush mask */
918 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
920 /* Flush Rx MAC FIFO on any flow control or error */
921 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
924 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
925 reg = RX_GMF_FL_THR_DEF + 1;
926 /* Another magic mystery workaround from sk98lin */
927 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
928 hw->chip_rev == CHIP_REV_YU_FE2_A0)
930 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
932 /* Configure Tx MAC FIFO */
933 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
934 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
936 /* On chips without ram buffer, pause is controlled by MAC level */
937 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
938 /* Pause threshold is scaled by 8 in bytes */
939 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
940 hw->chip_rev == CHIP_REV_YU_FE2_A0)
944 sky2_write16(hw, SK_REG(port, RX_GMF_UP_THR), reg);
945 sky2_write16(hw, SK_REG(port, RX_GMF_LP_THR), 768 / 8);
947 sky2_set_tx_stfwd(hw, port);
950 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
951 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
952 /* disable dynamic watermark */
953 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
954 reg &= ~TX_DYN_WM_ENA;
955 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
959 /* Assign Ram Buffer allocation to queue */
960 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
964 /* convert from K bytes to qwords used for hw register */
967 end = start + space - 1;
969 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
970 sky2_write32(hw, RB_ADDR(q, RB_START), start);
971 sky2_write32(hw, RB_ADDR(q, RB_END), end);
972 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
973 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
975 if (q == Q_R1 || q == Q_R2) {
976 u32 tp = space - space/4;
978 /* On receive queue's set the thresholds
979 * give receiver priority when > 3/4 full
980 * send pause when down to 2K
982 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
983 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
986 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
987 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
989 /* Enable store & forward on Tx queue's because
990 * Tx FIFO is only 1K on Yukon
992 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
995 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
996 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
999 /* Setup Bus Memory Interface */
1000 static void sky2_qset(struct sky2_hw *hw, u16 q)
1002 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
1003 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
1004 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
1005 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
1008 /* Setup prefetch unit registers. This is the interface between
1009 * hardware and driver list elements
1011 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
1012 dma_addr_t addr, u32 last)
1014 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1015 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
1016 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), upper_32_bits(addr));
1017 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), lower_32_bits(addr));
1018 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
1019 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
1021 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
1024 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2, u16 *slot)
1026 struct sky2_tx_le *le = sky2->tx_le + *slot;
1028 *slot = RING_NEXT(*slot, sky2->tx_ring_size);
1033 static void tx_init(struct sky2_port *sky2)
1035 struct sky2_tx_le *le;
1037 sky2->tx_prod = sky2->tx_cons = 0;
1038 sky2->tx_tcpsum = 0;
1039 sky2->tx_last_mss = 0;
1041 le = get_tx_le(sky2, &sky2->tx_prod);
1043 le->opcode = OP_ADDR64 | HW_OWNER;
1044 sky2->tx_last_upper = 0;
1047 /* Update chip's next pointer */
1048 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
1050 /* Make sure write' to descriptors are complete before we tell hardware */
1052 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1054 /* Synchronize I/O on since next processor may write to tail */
1059 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1061 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
1062 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
1067 static unsigned sky2_get_rx_threshold(struct sky2_port *sky2)
1071 /* Space needed for frame data + headers rounded up */
1072 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1074 /* Stopping point for hardware truncation */
1075 return (size - 8) / sizeof(u32);
1078 static unsigned sky2_get_rx_data_size(struct sky2_port *sky2)
1080 struct rx_ring_info *re;
1083 /* Space needed for frame data + headers rounded up */
1084 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1086 sky2->rx_nfrags = size >> PAGE_SHIFT;
1087 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1089 /* Compute residue after pages */
1090 size -= sky2->rx_nfrags << PAGE_SHIFT;
1092 /* Optimize to handle small packets and headers */
1093 if (size < copybreak)
1095 if (size < ETH_HLEN)
1101 /* Build description to hardware for one receive segment */
1102 static void sky2_rx_add(struct sky2_port *sky2, u8 op,
1103 dma_addr_t map, unsigned len)
1105 struct sky2_rx_le *le;
1107 if (sizeof(dma_addr_t) > sizeof(u32)) {
1108 le = sky2_next_rx(sky2);
1109 le->addr = cpu_to_le32(upper_32_bits(map));
1110 le->opcode = OP_ADDR64 | HW_OWNER;
1113 le = sky2_next_rx(sky2);
1114 le->addr = cpu_to_le32(lower_32_bits(map));
1115 le->length = cpu_to_le16(len);
1116 le->opcode = op | HW_OWNER;
1119 /* Build description to hardware for one possibly fragmented skb */
1120 static void sky2_rx_submit(struct sky2_port *sky2,
1121 const struct rx_ring_info *re)
1125 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1127 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1128 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1132 static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
1135 struct sk_buff *skb = re->skb;
1138 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
1139 if (pci_dma_mapping_error(pdev, re->data_addr))
1142 dma_unmap_len_set(re, data_size, size);
1144 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1145 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1147 re->frag_addr[i] = pci_map_page(pdev, frag->page,
1150 PCI_DMA_FROMDEVICE);
1152 if (pci_dma_mapping_error(pdev, re->frag_addr[i]))
1153 goto map_page_error;
1159 pci_unmap_page(pdev, re->frag_addr[i],
1160 skb_shinfo(skb)->frags[i].size,
1161 PCI_DMA_FROMDEVICE);
1164 pci_unmap_single(pdev, re->data_addr, dma_unmap_len(re, data_size),
1165 PCI_DMA_FROMDEVICE);
1168 if (net_ratelimit())
1169 dev_warn(&pdev->dev, "%s: rx mapping error\n",
1174 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1176 struct sk_buff *skb = re->skb;
1179 pci_unmap_single(pdev, re->data_addr, dma_unmap_len(re, data_size),
1180 PCI_DMA_FROMDEVICE);
1182 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1183 pci_unmap_page(pdev, re->frag_addr[i],
1184 skb_shinfo(skb)->frags[i].size,
1185 PCI_DMA_FROMDEVICE);
1188 /* Tell chip where to start receive checksum.
1189 * Actually has two checksums, but set both same to avoid possible byte
1192 static void rx_set_checksum(struct sky2_port *sky2)
1194 struct sky2_rx_le *le = sky2_next_rx(sky2);
1196 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1198 le->opcode = OP_TCPSTART | HW_OWNER;
1200 sky2_write32(sky2->hw,
1201 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1202 (sky2->netdev->features & NETIF_F_RXCSUM)
1203 ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
1206 /* Enable/disable receive hash calculation (RSS) */
1207 static void rx_set_rss(struct net_device *dev, u32 features)
1209 struct sky2_port *sky2 = netdev_priv(dev);
1210 struct sky2_hw *hw = sky2->hw;
1213 /* Supports IPv6 and other modes */
1214 if (hw->flags & SKY2_HW_NEW_LE) {
1216 sky2_write32(hw, SK_REG(sky2->port, RSS_CFG), HASH_ALL);
1219 /* Program RSS initial values */
1220 if (features & NETIF_F_RXHASH) {
1223 get_random_bytes(key, nkeys * sizeof(u32));
1224 for (i = 0; i < nkeys; i++)
1225 sky2_write32(hw, SK_REG(sky2->port, RSS_KEY + i * 4),
1228 /* Need to turn on (undocumented) flag to make hashing work */
1229 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T),
1232 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1233 BMU_ENA_RX_RSS_HASH);
1235 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1236 BMU_DIS_RX_RSS_HASH);
1240 * The RX Stop command will not work for Yukon-2 if the BMU does not
1241 * reach the end of packet and since we can't make sure that we have
1242 * incoming data, we must reset the BMU while it is not doing a DMA
1243 * transfer. Since it is possible that the RX path is still active,
1244 * the RX RAM buffer will be stopped first, so any possible incoming
1245 * data will not trigger a DMA. After the RAM buffer is stopped, the
1246 * BMU is polled until any DMA in progress is ended and only then it
1249 static void sky2_rx_stop(struct sky2_port *sky2)
1251 struct sky2_hw *hw = sky2->hw;
1252 unsigned rxq = rxqaddr[sky2->port];
1255 /* disable the RAM Buffer receive queue */
1256 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1258 for (i = 0; i < 0xffff; i++)
1259 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1260 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1263 netdev_warn(sky2->netdev, "receiver stop failed\n");
1265 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1267 /* reset the Rx prefetch unit */
1268 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1272 /* Clean out receive buffer area, assumes receiver hardware stopped */
1273 static void sky2_rx_clean(struct sky2_port *sky2)
1277 memset(sky2->rx_le, 0, RX_LE_BYTES);
1278 for (i = 0; i < sky2->rx_pending; i++) {
1279 struct rx_ring_info *re = sky2->rx_ring + i;
1282 sky2_rx_unmap_skb(sky2->hw->pdev, re);
1289 /* Basic MII support */
1290 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1292 struct mii_ioctl_data *data = if_mii(ifr);
1293 struct sky2_port *sky2 = netdev_priv(dev);
1294 struct sky2_hw *hw = sky2->hw;
1295 int err = -EOPNOTSUPP;
1297 if (!netif_running(dev))
1298 return -ENODEV; /* Phy still in reset */
1302 data->phy_id = PHY_ADDR_MARV;
1308 spin_lock_bh(&sky2->phy_lock);
1309 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
1310 spin_unlock_bh(&sky2->phy_lock);
1312 data->val_out = val;
1317 spin_lock_bh(&sky2->phy_lock);
1318 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1320 spin_unlock_bh(&sky2->phy_lock);
1326 #define SKY2_VLAN_OFFLOADS (NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO)
1328 static void sky2_vlan_mode(struct net_device *dev, u32 features)
1330 struct sky2_port *sky2 = netdev_priv(dev);
1331 struct sky2_hw *hw = sky2->hw;
1332 u16 port = sky2->port;
1334 if (features & NETIF_F_HW_VLAN_RX)
1335 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1338 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1341 if (features & NETIF_F_HW_VLAN_TX) {
1342 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1345 dev->vlan_features |= SKY2_VLAN_OFFLOADS;
1347 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1350 /* Can't do transmit offload of vlan without hw vlan */
1351 dev->vlan_features &= ~SKY2_VLAN_OFFLOADS;
1355 /* Amount of required worst case padding in rx buffer */
1356 static inline unsigned sky2_rx_pad(const struct sky2_hw *hw)
1358 return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2;
1362 * Allocate an skb for receiving. If the MTU is large enough
1363 * make the skb non-linear with a fragment list of pages.
1365 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2, gfp_t gfp)
1367 struct sk_buff *skb;
1370 skb = __netdev_alloc_skb(sky2->netdev,
1371 sky2->rx_data_size + sky2_rx_pad(sky2->hw),
1376 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
1377 unsigned char *start;
1379 * Workaround for a bug in FIFO that cause hang
1380 * if the FIFO if the receive buffer is not 64 byte aligned.
1381 * The buffer returned from netdev_alloc_skb is
1382 * aligned except if slab debugging is enabled.
1384 start = PTR_ALIGN(skb->data, 8);
1385 skb_reserve(skb, start - skb->data);
1387 skb_reserve(skb, NET_IP_ALIGN);
1389 for (i = 0; i < sky2->rx_nfrags; i++) {
1390 struct page *page = alloc_page(gfp);
1394 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
1404 static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1406 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1409 static int sky2_alloc_rx_skbs(struct sky2_port *sky2)
1411 struct sky2_hw *hw = sky2->hw;
1414 sky2->rx_data_size = sky2_get_rx_data_size(sky2);
1417 for (i = 0; i < sky2->rx_pending; i++) {
1418 struct rx_ring_info *re = sky2->rx_ring + i;
1420 re->skb = sky2_rx_alloc(sky2, GFP_KERNEL);
1424 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) {
1425 dev_kfree_skb(re->skb);
1434 * Setup receiver buffer pool.
1435 * Normal case this ends up creating one list element for skb
1436 * in the receive ring. Worst case if using large MTU and each
1437 * allocation falls on a different 64 bit region, that results
1438 * in 6 list elements per ring entry.
1439 * One element is used for checksum enable/disable, and one
1440 * extra to avoid wrap.
1442 static void sky2_rx_start(struct sky2_port *sky2)
1444 struct sky2_hw *hw = sky2->hw;
1445 struct rx_ring_info *re;
1446 unsigned rxq = rxqaddr[sky2->port];
1449 sky2->rx_put = sky2->rx_next = 0;
1452 /* On PCI express lowering the watermark gives better performance */
1453 if (pci_is_pcie(hw->pdev))
1454 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1456 /* These chips have no ram buffer?
1457 * MAC Rx RAM Read is controlled by hardware */
1458 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1459 hw->chip_rev > CHIP_REV_YU_EC_U_A0)
1460 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
1462 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1464 if (!(hw->flags & SKY2_HW_NEW_LE))
1465 rx_set_checksum(sky2);
1467 if (!(hw->flags & SKY2_HW_RSS_BROKEN))
1468 rx_set_rss(sky2->netdev, sky2->netdev->features);
1470 /* submit Rx ring */
1471 for (i = 0; i < sky2->rx_pending; i++) {
1472 re = sky2->rx_ring + i;
1473 sky2_rx_submit(sky2, re);
1477 * The receiver hangs if it receives frames larger than the
1478 * packet buffer. As a workaround, truncate oversize frames, but
1479 * the register is limited to 9 bits, so if you do frames > 2052
1480 * you better get the MTU right!
1482 thresh = sky2_get_rx_threshold(sky2);
1484 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1486 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1487 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1490 /* Tell chip about available buffers */
1491 sky2_rx_update(sky2, rxq);
1493 if (hw->chip_id == CHIP_ID_YUKON_EX ||
1494 hw->chip_id == CHIP_ID_YUKON_SUPR) {
1496 * Disable flushing of non ASF packets;
1497 * must be done after initializing the BMUs;
1498 * drivers without ASF support should do this too, otherwise
1499 * it may happen that they cannot run on ASF devices;
1500 * remember that the MAC FIFO isn't reset during initialization.
1502 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_MACSEC_FLUSH_OFF);
1505 if (hw->chip_id >= CHIP_ID_YUKON_SUPR) {
1506 /* Enable RX Home Address & Routing Header checksum fix */
1507 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_FL_CTRL),
1508 RX_IPV6_SA_MOB_ENA | RX_IPV6_DA_MOB_ENA);
1510 /* Enable TX Home Address & Routing Header checksum fix */
1511 sky2_write32(hw, Q_ADDR(txqaddr[sky2->port], Q_TEST),
1512 TBMU_TEST_HOME_ADD_FIX_EN | TBMU_TEST_ROUTING_ADD_FIX_EN);
1516 static int sky2_alloc_buffers(struct sky2_port *sky2)
1518 struct sky2_hw *hw = sky2->hw;
1520 /* must be power of 2 */
1521 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1522 sky2->tx_ring_size *
1523 sizeof(struct sky2_tx_le),
1528 sky2->tx_ring = kcalloc(sky2->tx_ring_size, sizeof(struct tx_ring_info),
1533 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1537 memset(sky2->rx_le, 0, RX_LE_BYTES);
1539 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1544 return sky2_alloc_rx_skbs(sky2);
1549 static void sky2_free_buffers(struct sky2_port *sky2)
1551 struct sky2_hw *hw = sky2->hw;
1553 sky2_rx_clean(sky2);
1556 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1557 sky2->rx_le, sky2->rx_le_map);
1561 pci_free_consistent(hw->pdev,
1562 sky2->tx_ring_size * sizeof(struct sky2_tx_le),
1563 sky2->tx_le, sky2->tx_le_map);
1566 kfree(sky2->tx_ring);
1567 kfree(sky2->rx_ring);
1569 sky2->tx_ring = NULL;
1570 sky2->rx_ring = NULL;
1573 static void sky2_hw_up(struct sky2_port *sky2)
1575 struct sky2_hw *hw = sky2->hw;
1576 unsigned port = sky2->port;
1579 struct net_device *otherdev = hw->dev[sky2->port^1];
1584 * On dual port PCI-X card, there is an problem where status
1585 * can be received out of order due to split transactions
1587 if (otherdev && netif_running(otherdev) &&
1588 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1591 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1592 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1593 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1596 sky2_mac_init(hw, port);
1598 /* Register is number of 4K blocks on internal RAM buffer. */
1599 ramsize = sky2_read8(hw, B2_E_0) * 4;
1603 netdev_dbg(sky2->netdev, "ram buffer %dK\n", ramsize);
1605 rxspace = ramsize / 2;
1607 rxspace = 8 + (2*(ramsize - 16))/3;
1609 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1610 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1612 /* Make sure SyncQ is disabled */
1613 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1617 sky2_qset(hw, txqaddr[port]);
1619 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1620 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1621 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1623 /* Set almost empty threshold */
1624 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1625 hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1626 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
1628 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1629 sky2->tx_ring_size - 1);
1631 sky2_vlan_mode(sky2->netdev, sky2->netdev->features);
1632 netdev_update_features(sky2->netdev);
1634 sky2_rx_start(sky2);
1637 /* Bring up network interface. */
1638 static int sky2_up(struct net_device *dev)
1640 struct sky2_port *sky2 = netdev_priv(dev);
1641 struct sky2_hw *hw = sky2->hw;
1642 unsigned port = sky2->port;
1646 netif_carrier_off(dev);
1648 err = sky2_alloc_buffers(sky2);
1654 /* Enable interrupts from phy/mac for port */
1655 imask = sky2_read32(hw, B0_IMSK);
1656 imask |= portirq_msk[port];
1657 sky2_write32(hw, B0_IMSK, imask);
1658 sky2_read32(hw, B0_IMSK);
1660 netif_info(sky2, ifup, dev, "enabling interface\n");
1665 sky2_free_buffers(sky2);
1669 /* Modular subtraction in ring */
1670 static inline int tx_inuse(const struct sky2_port *sky2)
1672 return (sky2->tx_prod - sky2->tx_cons) & (sky2->tx_ring_size - 1);
1675 /* Number of list elements available for next tx */
1676 static inline int tx_avail(const struct sky2_port *sky2)
1678 return sky2->tx_pending - tx_inuse(sky2);
1681 /* Estimate of number of transmit list elements required */
1682 static unsigned tx_le_req(const struct sk_buff *skb)
1686 count = (skb_shinfo(skb)->nr_frags + 1)
1687 * (sizeof(dma_addr_t) / sizeof(u32));
1689 if (skb_is_gso(skb))
1691 else if (sizeof(dma_addr_t) == sizeof(u32))
1692 ++count; /* possible vlan */
1694 if (skb->ip_summed == CHECKSUM_PARTIAL)
1700 static void sky2_tx_unmap(struct pci_dev *pdev, struct tx_ring_info *re)
1702 if (re->flags & TX_MAP_SINGLE)
1703 pci_unmap_single(pdev, dma_unmap_addr(re, mapaddr),
1704 dma_unmap_len(re, maplen),
1706 else if (re->flags & TX_MAP_PAGE)
1707 pci_unmap_page(pdev, dma_unmap_addr(re, mapaddr),
1708 dma_unmap_len(re, maplen),
1714 * Put one packet in ring for transmit.
1715 * A single packet can generate multiple list elements, and
1716 * the number of ring elements will probably be less than the number
1717 * of list elements used.
1719 static netdev_tx_t sky2_xmit_frame(struct sk_buff *skb,
1720 struct net_device *dev)
1722 struct sky2_port *sky2 = netdev_priv(dev);
1723 struct sky2_hw *hw = sky2->hw;
1724 struct sky2_tx_le *le = NULL;
1725 struct tx_ring_info *re;
1733 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1734 return NETDEV_TX_BUSY;
1736 len = skb_headlen(skb);
1737 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1739 if (pci_dma_mapping_error(hw->pdev, mapping))
1742 slot = sky2->tx_prod;
1743 netif_printk(sky2, tx_queued, KERN_DEBUG, dev,
1744 "tx queued, slot %u, len %d\n", slot, skb->len);
1746 /* Send high bits if needed */
1747 upper = upper_32_bits(mapping);
1748 if (upper != sky2->tx_last_upper) {
1749 le = get_tx_le(sky2, &slot);
1750 le->addr = cpu_to_le32(upper);
1751 sky2->tx_last_upper = upper;
1752 le->opcode = OP_ADDR64 | HW_OWNER;
1755 /* Check for TCP Segmentation Offload */
1756 mss = skb_shinfo(skb)->gso_size;
1759 if (!(hw->flags & SKY2_HW_NEW_LE))
1760 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1762 if (mss != sky2->tx_last_mss) {
1763 le = get_tx_le(sky2, &slot);
1764 le->addr = cpu_to_le32(mss);
1766 if (hw->flags & SKY2_HW_NEW_LE)
1767 le->opcode = OP_MSS | HW_OWNER;
1769 le->opcode = OP_LRGLEN | HW_OWNER;
1770 sky2->tx_last_mss = mss;
1776 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1777 if (vlan_tx_tag_present(skb)) {
1779 le = get_tx_le(sky2, &slot);
1781 le->opcode = OP_VLAN|HW_OWNER;
1783 le->opcode |= OP_VLAN;
1784 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1788 /* Handle TCP checksum offload */
1789 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1790 /* On Yukon EX (some versions) encoding change. */
1791 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
1792 ctrl |= CALSUM; /* auto checksum */
1794 const unsigned offset = skb_transport_offset(skb);
1797 tcpsum = offset << 16; /* sum start */
1798 tcpsum |= offset + skb->csum_offset; /* sum write */
1800 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1801 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1804 if (tcpsum != sky2->tx_tcpsum) {
1805 sky2->tx_tcpsum = tcpsum;
1807 le = get_tx_le(sky2, &slot);
1808 le->addr = cpu_to_le32(tcpsum);
1809 le->length = 0; /* initial checksum value */
1810 le->ctrl = 1; /* one packet */
1811 le->opcode = OP_TCPLISW | HW_OWNER;
1816 re = sky2->tx_ring + slot;
1817 re->flags = TX_MAP_SINGLE;
1818 dma_unmap_addr_set(re, mapaddr, mapping);
1819 dma_unmap_len_set(re, maplen, len);
1821 le = get_tx_le(sky2, &slot);
1822 le->addr = cpu_to_le32(lower_32_bits(mapping));
1823 le->length = cpu_to_le16(len);
1825 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1828 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1829 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1831 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1832 frag->size, PCI_DMA_TODEVICE);
1834 if (pci_dma_mapping_error(hw->pdev, mapping))
1835 goto mapping_unwind;
1837 upper = upper_32_bits(mapping);
1838 if (upper != sky2->tx_last_upper) {
1839 le = get_tx_le(sky2, &slot);
1840 le->addr = cpu_to_le32(upper);
1841 sky2->tx_last_upper = upper;
1842 le->opcode = OP_ADDR64 | HW_OWNER;
1845 re = sky2->tx_ring + slot;
1846 re->flags = TX_MAP_PAGE;
1847 dma_unmap_addr_set(re, mapaddr, mapping);
1848 dma_unmap_len_set(re, maplen, frag->size);
1850 le = get_tx_le(sky2, &slot);
1851 le->addr = cpu_to_le32(lower_32_bits(mapping));
1852 le->length = cpu_to_le16(frag->size);
1854 le->opcode = OP_BUFFER | HW_OWNER;
1860 sky2->tx_prod = slot;
1862 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1863 netif_stop_queue(dev);
1865 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1867 return NETDEV_TX_OK;
1870 for (i = sky2->tx_prod; i != slot; i = RING_NEXT(i, sky2->tx_ring_size)) {
1871 re = sky2->tx_ring + i;
1873 sky2_tx_unmap(hw->pdev, re);
1877 if (net_ratelimit())
1878 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
1880 return NETDEV_TX_OK;
1884 * Free ring elements from starting at tx_cons until "done"
1887 * 1. The hardware will tell us about partial completion of multi-part
1888 * buffers so make sure not to free skb to early.
1889 * 2. This may run in parallel start_xmit because the it only
1890 * looks at the tail of the queue of FIFO (tx_cons), not
1891 * the head (tx_prod)
1893 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1895 struct net_device *dev = sky2->netdev;
1898 BUG_ON(done >= sky2->tx_ring_size);
1900 for (idx = sky2->tx_cons; idx != done;
1901 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
1902 struct tx_ring_info *re = sky2->tx_ring + idx;
1903 struct sk_buff *skb = re->skb;
1905 sky2_tx_unmap(sky2->hw->pdev, re);
1908 netif_printk(sky2, tx_done, KERN_DEBUG, dev,
1909 "tx done %u\n", idx);
1911 u64_stats_update_begin(&sky2->tx_stats.syncp);
1912 ++sky2->tx_stats.packets;
1913 sky2->tx_stats.bytes += skb->len;
1914 u64_stats_update_end(&sky2->tx_stats.syncp);
1917 dev_kfree_skb_any(skb);
1919 sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size);
1923 sky2->tx_cons = idx;
1927 static void sky2_tx_reset(struct sky2_hw *hw, unsigned port)
1929 /* Disable Force Sync bit and Enable Alloc bit */
1930 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1931 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1933 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1934 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1935 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1937 /* Reset the PCI FIFO of the async Tx queue */
1938 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1939 BMU_RST_SET | BMU_FIFO_RST);
1941 /* Reset the Tx prefetch units */
1942 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1945 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1946 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1949 static void sky2_hw_down(struct sky2_port *sky2)
1951 struct sky2_hw *hw = sky2->hw;
1952 unsigned port = sky2->port;
1955 /* Force flow control off */
1956 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1958 /* Stop transmitter */
1959 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1960 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1962 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1963 RB_RST_SET | RB_DIS_OP_MD);
1965 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1966 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1967 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1969 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1971 /* Workaround shared GMAC reset */
1972 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 &&
1973 port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1974 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1976 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1978 /* Force any delayed status interrrupt and NAPI */
1979 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0);
1980 sky2_write32(hw, STAT_TX_TIMER_CNT, 0);
1981 sky2_write32(hw, STAT_ISR_TIMER_CNT, 0);
1982 sky2_read8(hw, STAT_ISR_TIMER_CTRL);
1986 spin_lock_bh(&sky2->phy_lock);
1987 sky2_phy_power_down(hw, port);
1988 spin_unlock_bh(&sky2->phy_lock);
1990 sky2_tx_reset(hw, port);
1992 /* Free any pending frames stuck in HW queue */
1993 sky2_tx_complete(sky2, sky2->tx_prod);
1996 /* Network shutdown */
1997 static int sky2_down(struct net_device *dev)
1999 struct sky2_port *sky2 = netdev_priv(dev);
2000 struct sky2_hw *hw = sky2->hw;
2002 /* Never really got started! */
2006 netif_info(sky2, ifdown, dev, "disabling interface\n");
2008 /* Disable port IRQ */
2009 sky2_write32(hw, B0_IMSK,
2010 sky2_read32(hw, B0_IMSK) & ~portirq_msk[sky2->port]);
2011 sky2_read32(hw, B0_IMSK);
2013 synchronize_irq(hw->pdev->irq);
2014 napi_synchronize(&hw->napi);
2018 sky2_free_buffers(sky2);
2023 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
2025 if (hw->flags & SKY2_HW_FIBRE_PHY)
2028 if (!(hw->flags & SKY2_HW_GIGABIT)) {
2029 if (aux & PHY_M_PS_SPEED_100)
2035 switch (aux & PHY_M_PS_SPEED_MSK) {
2036 case PHY_M_PS_SPEED_1000:
2038 case PHY_M_PS_SPEED_100:
2045 static void sky2_link_up(struct sky2_port *sky2)
2047 struct sky2_hw *hw = sky2->hw;
2048 unsigned port = sky2->port;
2049 static const char *fc_name[] = {
2056 sky2_enable_rx_tx(sky2);
2058 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
2060 netif_carrier_on(sky2->netdev);
2062 mod_timer(&hw->watchdog_timer, jiffies + 1);
2064 /* Turn on link LED */
2065 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
2066 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
2068 netif_info(sky2, link, sky2->netdev,
2069 "Link is up at %d Mbps, %s duplex, flow control %s\n",
2071 sky2->duplex == DUPLEX_FULL ? "full" : "half",
2072 fc_name[sky2->flow_status]);
2075 static void sky2_link_down(struct sky2_port *sky2)
2077 struct sky2_hw *hw = sky2->hw;
2078 unsigned port = sky2->port;
2081 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
2083 reg = gma_read16(hw, port, GM_GP_CTRL);
2084 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2085 gma_write16(hw, port, GM_GP_CTRL, reg);
2087 netif_carrier_off(sky2->netdev);
2089 /* Turn off link LED */
2090 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
2092 netif_info(sky2, link, sky2->netdev, "Link is down\n");
2094 sky2_phy_init(hw, port);
2097 static enum flow_control sky2_flow(int rx, int tx)
2100 return tx ? FC_BOTH : FC_RX;
2102 return tx ? FC_TX : FC_NONE;
2105 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
2107 struct sky2_hw *hw = sky2->hw;
2108 unsigned port = sky2->port;
2111 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2112 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
2113 if (lpa & PHY_M_AN_RF) {
2114 netdev_err(sky2->netdev, "remote fault\n");
2118 if (!(aux & PHY_M_PS_SPDUP_RES)) {
2119 netdev_err(sky2->netdev, "speed/duplex mismatch\n");
2123 sky2->speed = sky2_phy_speed(hw, aux);
2124 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2126 /* Since the pause result bits seem to in different positions on
2127 * different chips. look at registers.
2129 if (hw->flags & SKY2_HW_FIBRE_PHY) {
2130 /* Shift for bits in fiber PHY */
2131 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
2132 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
2134 if (advert & ADVERTISE_1000XPAUSE)
2135 advert |= ADVERTISE_PAUSE_CAP;
2136 if (advert & ADVERTISE_1000XPSE_ASYM)
2137 advert |= ADVERTISE_PAUSE_ASYM;
2138 if (lpa & LPA_1000XPAUSE)
2139 lpa |= LPA_PAUSE_CAP;
2140 if (lpa & LPA_1000XPAUSE_ASYM)
2141 lpa |= LPA_PAUSE_ASYM;
2144 sky2->flow_status = FC_NONE;
2145 if (advert & ADVERTISE_PAUSE_CAP) {
2146 if (lpa & LPA_PAUSE_CAP)
2147 sky2->flow_status = FC_BOTH;
2148 else if (advert & ADVERTISE_PAUSE_ASYM)
2149 sky2->flow_status = FC_RX;
2150 } else if (advert & ADVERTISE_PAUSE_ASYM) {
2151 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
2152 sky2->flow_status = FC_TX;
2155 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000 &&
2156 !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
2157 sky2->flow_status = FC_NONE;
2159 if (sky2->flow_status & FC_TX)
2160 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2162 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2167 /* Interrupt from PHY */
2168 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
2170 struct net_device *dev = hw->dev[port];
2171 struct sky2_port *sky2 = netdev_priv(dev);
2172 u16 istatus, phystat;
2174 if (!netif_running(dev))
2177 spin_lock(&sky2->phy_lock);
2178 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2179 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2181 netif_info(sky2, intr, sky2->netdev, "phy interrupt status 0x%x 0x%x\n",
2184 if (istatus & PHY_M_IS_AN_COMPL) {
2185 if (sky2_autoneg_done(sky2, phystat) == 0 &&
2186 !netif_carrier_ok(dev))
2191 if (istatus & PHY_M_IS_LSP_CHANGE)
2192 sky2->speed = sky2_phy_speed(hw, phystat);
2194 if (istatus & PHY_M_IS_DUP_CHANGE)
2196 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2198 if (istatus & PHY_M_IS_LST_CHANGE) {
2199 if (phystat & PHY_M_PS_LINK_UP)
2202 sky2_link_down(sky2);
2205 spin_unlock(&sky2->phy_lock);
2208 /* Special quick link interrupt (Yukon-2 Optima only) */
2209 static void sky2_qlink_intr(struct sky2_hw *hw)
2211 struct sky2_port *sky2 = netdev_priv(hw->dev[0]);
2216 imask = sky2_read32(hw, B0_IMSK);
2217 imask &= ~Y2_IS_PHY_QLNK;
2218 sky2_write32(hw, B0_IMSK, imask);
2220 /* reset PHY Link Detect */
2221 phy = sky2_pci_read16(hw, PSM_CONFIG_REG4);
2222 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2223 sky2_pci_write16(hw, PSM_CONFIG_REG4, phy | 1);
2224 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2229 /* Transmit timeout is only called if we are running, carrier is up
2230 * and tx queue is full (stopped).
2232 static void sky2_tx_timeout(struct net_device *dev)
2234 struct sky2_port *sky2 = netdev_priv(dev);
2235 struct sky2_hw *hw = sky2->hw;
2237 netif_err(sky2, timer, dev, "tx timeout\n");
2239 netdev_printk(KERN_DEBUG, dev, "transmit ring %u .. %u report=%u done=%u\n",
2240 sky2->tx_cons, sky2->tx_prod,
2241 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2242 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
2244 /* can't restart safely under softirq */
2245 schedule_work(&hw->restart_work);
2248 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2250 struct sky2_port *sky2 = netdev_priv(dev);
2251 struct sky2_hw *hw = sky2->hw;
2252 unsigned port = sky2->port;
2257 /* MTU size outside the spec */
2258 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2261 /* MTU > 1500 on yukon FE and FE+ not allowed */
2262 if (new_mtu > ETH_DATA_LEN &&
2263 (hw->chip_id == CHIP_ID_YUKON_FE ||
2264 hw->chip_id == CHIP_ID_YUKON_FE_P))
2267 if (!netif_running(dev)) {
2269 netdev_update_features(dev);
2273 imask = sky2_read32(hw, B0_IMSK);
2274 sky2_write32(hw, B0_IMSK, 0);
2276 dev->trans_start = jiffies; /* prevent tx timeout */
2277 napi_disable(&hw->napi);
2278 netif_tx_disable(dev);
2280 synchronize_irq(hw->pdev->irq);
2282 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
2283 sky2_set_tx_stfwd(hw, port);
2285 ctl = gma_read16(hw, port, GM_GP_CTRL);
2286 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
2288 sky2_rx_clean(sky2);
2291 netdev_update_features(dev);
2293 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2294 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2296 if (dev->mtu > ETH_DATA_LEN)
2297 mode |= GM_SMOD_JUMBO_ENA;
2299 gma_write16(hw, port, GM_SERIAL_MODE, mode);
2301 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
2303 err = sky2_alloc_rx_skbs(sky2);
2305 sky2_rx_start(sky2);
2307 sky2_rx_clean(sky2);
2308 sky2_write32(hw, B0_IMSK, imask);
2310 sky2_read32(hw, B0_Y2_SP_LISR);
2311 napi_enable(&hw->napi);
2316 gma_write16(hw, port, GM_GP_CTRL, ctl);
2318 netif_wake_queue(dev);
2324 /* For small just reuse existing skb for next receive */
2325 static struct sk_buff *receive_copy(struct sky2_port *sky2,
2326 const struct rx_ring_info *re,
2329 struct sk_buff *skb;
2331 skb = netdev_alloc_skb_ip_align(sky2->netdev, length);
2333 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2334 length, PCI_DMA_FROMDEVICE);
2335 skb_copy_from_linear_data(re->skb, skb->data, length);
2336 skb->ip_summed = re->skb->ip_summed;
2337 skb->csum = re->skb->csum;
2338 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2339 length, PCI_DMA_FROMDEVICE);
2340 re->skb->ip_summed = CHECKSUM_NONE;
2341 skb_put(skb, length);
2346 /* Adjust length of skb with fragments to match received data */
2347 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2348 unsigned int length)
2353 /* put header into skb */
2354 size = min(length, hdr_space);
2359 num_frags = skb_shinfo(skb)->nr_frags;
2360 for (i = 0; i < num_frags; i++) {
2361 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2364 /* don't need this page */
2365 __free_page(frag->page);
2366 --skb_shinfo(skb)->nr_frags;
2368 size = min(length, (unsigned) PAGE_SIZE);
2371 skb->data_len += size;
2372 skb->truesize += size;
2379 /* Normal packet - take skb from ring element and put in a new one */
2380 static struct sk_buff *receive_new(struct sky2_port *sky2,
2381 struct rx_ring_info *re,
2382 unsigned int length)
2384 struct sk_buff *skb;
2385 struct rx_ring_info nre;
2386 unsigned hdr_space = sky2->rx_data_size;
2388 nre.skb = sky2_rx_alloc(sky2, GFP_ATOMIC);
2389 if (unlikely(!nre.skb))
2392 if (sky2_rx_map_skb(sky2->hw->pdev, &nre, hdr_space))
2396 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2397 prefetch(skb->data);
2400 if (skb_shinfo(skb)->nr_frags)
2401 skb_put_frags(skb, hdr_space, length);
2403 skb_put(skb, length);
2407 dev_kfree_skb(nre.skb);
2413 * Receive one packet.
2414 * For larger packets, get new buffer.
2416 static struct sk_buff *sky2_receive(struct net_device *dev,
2417 u16 length, u32 status)
2419 struct sky2_port *sky2 = netdev_priv(dev);
2420 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
2421 struct sk_buff *skb = NULL;
2422 u16 count = (status & GMR_FS_LEN) >> 16;
2424 if (status & GMR_FS_VLAN)
2425 count -= VLAN_HLEN; /* Account for vlan tag */
2427 netif_printk(sky2, rx_status, KERN_DEBUG, dev,
2428 "rx slot %u status 0x%x len %d\n",
2429 sky2->rx_next, status, length);
2431 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
2432 prefetch(sky2->rx_ring + sky2->rx_next);
2434 /* This chip has hardware problems that generates bogus status.
2435 * So do only marginal checking and expect higher level protocols
2436 * to handle crap frames.
2438 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2439 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2443 if (status & GMR_FS_ANY_ERR)
2446 if (!(status & GMR_FS_RX_OK))
2449 /* if length reported by DMA does not match PHY, packet was truncated */
2450 if (length != count)
2454 if (length < copybreak)
2455 skb = receive_copy(sky2, re, length);
2457 skb = receive_new(sky2, re, length);
2459 dev->stats.rx_dropped += (skb == NULL);
2462 sky2_rx_submit(sky2, re);
2467 ++dev->stats.rx_errors;
2469 if (net_ratelimit())
2470 netif_info(sky2, rx_err, dev,
2471 "rx error, status 0x%x length %d\n", status, length);
2476 /* Transmit complete */
2477 static inline void sky2_tx_done(struct net_device *dev, u16 last)
2479 struct sky2_port *sky2 = netdev_priv(dev);
2481 if (netif_running(dev)) {
2482 sky2_tx_complete(sky2, last);
2484 /* Wake unless it's detached, and called e.g. from sky2_down() */
2485 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
2486 netif_wake_queue(dev);
2490 static inline void sky2_skb_rx(const struct sky2_port *sky2,
2491 u32 status, struct sk_buff *skb)
2493 if (status & GMR_FS_VLAN)
2494 __vlan_hwaccel_put_tag(skb, be16_to_cpu(sky2->rx_tag));
2496 if (skb->ip_summed == CHECKSUM_NONE)
2497 netif_receive_skb(skb);
2499 napi_gro_receive(&sky2->hw->napi, skb);
2502 static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port,
2503 unsigned packets, unsigned bytes)
2505 struct net_device *dev = hw->dev[port];
2506 struct sky2_port *sky2 = netdev_priv(dev);
2511 u64_stats_update_begin(&sky2->rx_stats.syncp);
2512 sky2->rx_stats.packets += packets;
2513 sky2->rx_stats.bytes += bytes;
2514 u64_stats_update_end(&sky2->rx_stats.syncp);
2516 dev->last_rx = jiffies;
2517 sky2_rx_update(netdev_priv(dev), rxqaddr[port]);
2520 static void sky2_rx_checksum(struct sky2_port *sky2, u32 status)
2522 /* If this happens then driver assuming wrong format for chip type */
2523 BUG_ON(sky2->hw->flags & SKY2_HW_NEW_LE);
2525 /* Both checksum counters are programmed to start at
2526 * the same offset, so unless there is a problem they
2527 * should match. This failure is an early indication that
2528 * hardware receive checksumming won't work.
2530 if (likely((u16)(status >> 16) == (u16)status)) {
2531 struct sk_buff *skb = sky2->rx_ring[sky2->rx_next].skb;
2532 skb->ip_summed = CHECKSUM_COMPLETE;
2533 skb->csum = le16_to_cpu(status);
2535 dev_notice(&sky2->hw->pdev->dev,
2536 "%s: receive checksum problem (status = %#x)\n",
2537 sky2->netdev->name, status);
2539 /* Disable checksum offload
2540 * It will be reenabled on next ndo_set_features, but if it's
2541 * really broken, will get disabled again
2543 sky2->netdev->features &= ~NETIF_F_RXCSUM;
2544 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2549 static void sky2_rx_hash(struct sky2_port *sky2, u32 status)
2551 struct sk_buff *skb;
2553 skb = sky2->rx_ring[sky2->rx_next].skb;
2554 skb->rxhash = le32_to_cpu(status);
2557 /* Process status response ring */
2558 static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
2561 unsigned int total_bytes[2] = { 0 };
2562 unsigned int total_packets[2] = { 0 };
2566 struct sky2_port *sky2;
2567 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2569 struct net_device *dev;
2570 struct sk_buff *skb;
2573 u8 opcode = le->opcode;
2575 if (!(opcode & HW_OWNER))
2578 hw->st_idx = RING_NEXT(hw->st_idx, hw->st_size);
2580 port = le->css & CSS_LINK_BIT;
2581 dev = hw->dev[port];
2582 sky2 = netdev_priv(dev);
2583 length = le16_to_cpu(le->length);
2584 status = le32_to_cpu(le->status);
2587 switch (opcode & ~HW_OWNER) {
2589 total_packets[port]++;
2590 total_bytes[port] += length;
2592 skb = sky2_receive(dev, length, status);
2596 /* This chip reports checksum status differently */
2597 if (hw->flags & SKY2_HW_NEW_LE) {
2598 if ((dev->features & NETIF_F_RXCSUM) &&
2599 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2600 (le->css & CSS_TCPUDPCSOK))
2601 skb->ip_summed = CHECKSUM_UNNECESSARY;
2603 skb->ip_summed = CHECKSUM_NONE;
2606 skb->protocol = eth_type_trans(skb, dev);
2608 sky2_skb_rx(sky2, status, skb);
2610 /* Stop after net poll weight */
2611 if (++work_done >= to_do)
2616 sky2->rx_tag = length;
2620 sky2->rx_tag = length;
2623 if (likely(dev->features & NETIF_F_RXCSUM))
2624 sky2_rx_checksum(sky2, status);
2628 sky2_rx_hash(sky2, status);
2632 /* TX index reports status for both ports */
2633 sky2_tx_done(hw->dev[0], status & 0xfff);
2635 sky2_tx_done(hw->dev[1],
2636 ((status >> 24) & 0xff)
2637 | (u16)(length & 0xf) << 8);
2641 if (net_ratelimit())
2642 pr_warning("unknown status opcode 0x%x\n", opcode);
2644 } while (hw->st_idx != idx);
2646 /* Fully processed status ring so clear irq */
2647 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2650 sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]);
2651 sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]);
2656 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2658 struct net_device *dev = hw->dev[port];
2660 if (net_ratelimit())
2661 netdev_info(dev, "hw error interrupt status 0x%x\n", status);
2663 if (status & Y2_IS_PAR_RD1) {
2664 if (net_ratelimit())
2665 netdev_err(dev, "ram data read parity error\n");
2667 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2670 if (status & Y2_IS_PAR_WR1) {
2671 if (net_ratelimit())
2672 netdev_err(dev, "ram data write parity error\n");
2674 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2677 if (status & Y2_IS_PAR_MAC1) {
2678 if (net_ratelimit())
2679 netdev_err(dev, "MAC parity error\n");
2680 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2683 if (status & Y2_IS_PAR_RX1) {
2684 if (net_ratelimit())
2685 netdev_err(dev, "RX parity error\n");
2686 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2689 if (status & Y2_IS_TCP_TXA1) {
2690 if (net_ratelimit())
2691 netdev_err(dev, "TCP segmentation error\n");
2692 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2696 static void sky2_hw_intr(struct sky2_hw *hw)
2698 struct pci_dev *pdev = hw->pdev;
2699 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2700 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2704 if (status & Y2_IS_TIST_OV)
2705 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2707 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2710 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2711 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2712 if (net_ratelimit())
2713 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
2716 sky2_pci_write16(hw, PCI_STATUS,
2717 pci_err | PCI_STATUS_ERROR_BITS);
2718 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2721 if (status & Y2_IS_PCI_EXP) {
2722 /* PCI-Express uncorrectable Error occurred */
2725 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2726 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2727 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2729 if (net_ratelimit())
2730 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
2732 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2733 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2736 if (status & Y2_HWE_L1_MASK)
2737 sky2_hw_error(hw, 0, status);
2739 if (status & Y2_HWE_L1_MASK)
2740 sky2_hw_error(hw, 1, status);
2743 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2745 struct net_device *dev = hw->dev[port];
2746 struct sky2_port *sky2 = netdev_priv(dev);
2747 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2749 netif_info(sky2, intr, dev, "mac interrupt status 0x%x\n", status);
2751 if (status & GM_IS_RX_CO_OV)
2752 gma_read16(hw, port, GM_RX_IRQ_SRC);
2754 if (status & GM_IS_TX_CO_OV)
2755 gma_read16(hw, port, GM_TX_IRQ_SRC);
2757 if (status & GM_IS_RX_FF_OR) {
2758 ++dev->stats.rx_fifo_errors;
2759 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2762 if (status & GM_IS_TX_FF_UR) {
2763 ++dev->stats.tx_fifo_errors;
2764 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2768 /* This should never happen it is a bug. */
2769 static void sky2_le_error(struct sky2_hw *hw, unsigned port, u16 q)
2771 struct net_device *dev = hw->dev[port];
2772 u16 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2774 dev_err(&hw->pdev->dev, "%s: descriptor error q=%#x get=%u put=%u\n",
2775 dev->name, (unsigned) q, (unsigned) idx,
2776 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
2778 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
2781 static int sky2_rx_hung(struct net_device *dev)
2783 struct sky2_port *sky2 = netdev_priv(dev);
2784 struct sky2_hw *hw = sky2->hw;
2785 unsigned port = sky2->port;
2786 unsigned rxq = rxqaddr[port];
2787 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2788 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2789 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2790 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2792 /* If idle and MAC or PCI is stuck */
2793 if (sky2->check.last == dev->last_rx &&
2794 ((mac_rp == sky2->check.mac_rp &&
2795 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2796 /* Check if the PCI RX hang */
2797 (fifo_rp == sky2->check.fifo_rp &&
2798 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2799 netdev_printk(KERN_DEBUG, dev,
2800 "hung mac %d:%d fifo %d (%d:%d)\n",
2801 mac_lev, mac_rp, fifo_lev,
2802 fifo_rp, sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2805 sky2->check.last = dev->last_rx;
2806 sky2->check.mac_rp = mac_rp;
2807 sky2->check.mac_lev = mac_lev;
2808 sky2->check.fifo_rp = fifo_rp;
2809 sky2->check.fifo_lev = fifo_lev;
2814 static void sky2_watchdog(unsigned long arg)
2816 struct sky2_hw *hw = (struct sky2_hw *) arg;
2818 /* Check for lost IRQ once a second */
2819 if (sky2_read32(hw, B0_ISRC)) {
2820 napi_schedule(&hw->napi);
2824 for (i = 0; i < hw->ports; i++) {
2825 struct net_device *dev = hw->dev[i];
2826 if (!netif_running(dev))
2830 /* For chips with Rx FIFO, check if stuck */
2831 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
2832 sky2_rx_hung(dev)) {
2833 netdev_info(dev, "receiver hang detected\n");
2834 schedule_work(&hw->restart_work);
2843 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
2846 /* Hardware/software error handling */
2847 static void sky2_err_intr(struct sky2_hw *hw, u32 status)
2849 if (net_ratelimit())
2850 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
2852 if (status & Y2_IS_HW_ERR)
2855 if (status & Y2_IS_IRQ_MAC1)
2856 sky2_mac_intr(hw, 0);
2858 if (status & Y2_IS_IRQ_MAC2)
2859 sky2_mac_intr(hw, 1);
2861 if (status & Y2_IS_CHK_RX1)
2862 sky2_le_error(hw, 0, Q_R1);
2864 if (status & Y2_IS_CHK_RX2)
2865 sky2_le_error(hw, 1, Q_R2);
2867 if (status & Y2_IS_CHK_TXA1)
2868 sky2_le_error(hw, 0, Q_XA1);
2870 if (status & Y2_IS_CHK_TXA2)
2871 sky2_le_error(hw, 1, Q_XA2);
2874 static int sky2_poll(struct napi_struct *napi, int work_limit)
2876 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
2877 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2881 if (unlikely(status & Y2_IS_ERROR))
2882 sky2_err_intr(hw, status);
2884 if (status & Y2_IS_IRQ_PHY1)
2885 sky2_phy_intr(hw, 0);
2887 if (status & Y2_IS_IRQ_PHY2)
2888 sky2_phy_intr(hw, 1);
2890 if (status & Y2_IS_PHY_QLNK)
2891 sky2_qlink_intr(hw);
2893 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2894 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
2896 if (work_done >= work_limit)
2900 napi_complete(napi);
2901 sky2_read32(hw, B0_Y2_SP_LISR);
2907 static irqreturn_t sky2_intr(int irq, void *dev_id)
2909 struct sky2_hw *hw = dev_id;
2912 /* Reading this mask interrupts as side effect */
2913 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2914 if (status == 0 || status == ~0)
2917 prefetch(&hw->st_le[hw->st_idx]);
2919 napi_schedule(&hw->napi);
2924 #ifdef CONFIG_NET_POLL_CONTROLLER
2925 static void sky2_netpoll(struct net_device *dev)
2927 struct sky2_port *sky2 = netdev_priv(dev);
2929 napi_schedule(&sky2->hw->napi);
2933 /* Chip internal frequency for clock calculations */
2934 static u32 sky2_mhz(const struct sky2_hw *hw)
2936 switch (hw->chip_id) {
2937 case CHIP_ID_YUKON_EC:
2938 case CHIP_ID_YUKON_EC_U:
2939 case CHIP_ID_YUKON_EX:
2940 case CHIP_ID_YUKON_SUPR:
2941 case CHIP_ID_YUKON_UL_2:
2942 case CHIP_ID_YUKON_OPT:
2945 case CHIP_ID_YUKON_FE:
2948 case CHIP_ID_YUKON_FE_P:
2951 case CHIP_ID_YUKON_XL:
2959 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2961 return sky2_mhz(hw) * us;
2964 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2966 return clk / sky2_mhz(hw);
2970 static int __devinit sky2_init(struct sky2_hw *hw)
2974 /* Enable all clocks and check for bad PCI access */
2975 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2977 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2979 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2980 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2982 switch (hw->chip_id) {
2983 case CHIP_ID_YUKON_XL:
2984 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
2985 if (hw->chip_rev < CHIP_REV_YU_XL_A2)
2986 hw->flags |= SKY2_HW_RSS_BROKEN;
2989 case CHIP_ID_YUKON_EC_U:
2990 hw->flags = SKY2_HW_GIGABIT
2992 | SKY2_HW_ADV_POWER_CTL;
2995 case CHIP_ID_YUKON_EX:
2996 hw->flags = SKY2_HW_GIGABIT
2999 | SKY2_HW_ADV_POWER_CTL;
3001 /* New transmit checksum */
3002 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
3003 hw->flags |= SKY2_HW_AUTO_TX_SUM;
3006 case CHIP_ID_YUKON_EC:
3007 /* This rev is really old, and requires untested workarounds */
3008 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
3009 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
3012 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_RSS_BROKEN;
3015 case CHIP_ID_YUKON_FE:
3016 hw->flags = SKY2_HW_RSS_BROKEN;
3019 case CHIP_ID_YUKON_FE_P:
3020 hw->flags = SKY2_HW_NEWER_PHY
3022 | SKY2_HW_AUTO_TX_SUM
3023 | SKY2_HW_ADV_POWER_CTL;
3025 /* The workaround for status conflicts VLAN tag detection. */
3026 if (hw->chip_rev == CHIP_REV_YU_FE2_A0)
3027 hw->flags |= SKY2_HW_VLAN_BROKEN;
3030 case CHIP_ID_YUKON_SUPR:
3031 hw->flags = SKY2_HW_GIGABIT
3034 | SKY2_HW_AUTO_TX_SUM
3035 | SKY2_HW_ADV_POWER_CTL;
3038 case CHIP_ID_YUKON_UL_2:
3039 hw->flags = SKY2_HW_GIGABIT
3040 | SKY2_HW_ADV_POWER_CTL;
3043 case CHIP_ID_YUKON_OPT:
3044 hw->flags = SKY2_HW_GIGABIT
3046 | SKY2_HW_ADV_POWER_CTL;
3050 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3055 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
3056 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
3057 hw->flags |= SKY2_HW_FIBRE_PHY;
3060 t8 = sky2_read8(hw, B2_Y2_HW_RES);
3061 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
3062 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
3066 if (sky2_read8(hw, B2_E_0))
3067 hw->flags |= SKY2_HW_RAM_BUFFER;
3072 static void sky2_reset(struct sky2_hw *hw)
3074 struct pci_dev *pdev = hw->pdev;
3077 u32 hwe_mask = Y2_HWE_ALL_MASK;
3080 if (hw->chip_id == CHIP_ID_YUKON_EX
3081 || hw->chip_id == CHIP_ID_YUKON_SUPR) {
3082 sky2_write32(hw, CPU_WDOG, 0);
3083 status = sky2_read16(hw, HCU_CCSR);
3084 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
3085 HCU_CCSR_UC_STATE_MSK);
3087 * CPU clock divider shouldn't be used because
3088 * - ASF firmware may malfunction
3089 * - Yukon-Supreme: Parallel FLASH doesn't support divided clocks
3091 status &= ~HCU_CCSR_CPU_CLK_DIVIDE_MSK;
3092 sky2_write16(hw, HCU_CCSR, status);
3093 sky2_write32(hw, CPU_WDOG, 0);
3095 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
3096 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
3099 sky2_write8(hw, B0_CTST, CS_RST_SET);
3100 sky2_write8(hw, B0_CTST, CS_RST_CLR);
3102 /* allow writes to PCI config */
3103 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3105 /* clear PCI errors, if any */
3106 status = sky2_pci_read16(hw, PCI_STATUS);
3107 status |= PCI_STATUS_ERROR_BITS;
3108 sky2_pci_write16(hw, PCI_STATUS, status);
3110 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
3112 if (pci_is_pcie(pdev)) {
3113 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
3116 /* If error bit is stuck on ignore it */
3117 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
3118 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
3120 hwe_mask |= Y2_IS_PCI_EXP;
3124 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3126 for (i = 0; i < hw->ports; i++) {
3127 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3128 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
3130 if (hw->chip_id == CHIP_ID_YUKON_EX ||
3131 hw->chip_id == CHIP_ID_YUKON_SUPR)
3132 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
3133 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
3138 if (hw->chip_id == CHIP_ID_YUKON_SUPR && hw->chip_rev > CHIP_REV_YU_SU_B0) {
3139 /* enable MACSec clock gating */
3140 sky2_pci_write32(hw, PCI_DEV_REG3, P_CLK_MACSEC_DIS);
3143 if (hw->chip_id == CHIP_ID_YUKON_OPT) {
3147 if (hw->chip_rev == 0) {
3148 /* disable PCI-E PHY power down (set PHY reg 0x80, bit 7 */
3149 sky2_write32(hw, Y2_PEX_PHY_DATA, (0x80UL << 16) | (1 << 7));
3151 /* set PHY Link Detect Timer to 1.1 second (11x 100ms) */
3154 /* set PHY Link Detect Timer to 0.4 second (4x 100ms) */
3158 reg <<= PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE;
3160 /* reset PHY Link Detect */
3161 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3162 sky2_pci_write16(hw, PSM_CONFIG_REG4,
3163 reg | PSM_CONFIG_REG4_RST_PHY_LINK_DETECT);
3164 sky2_pci_write16(hw, PSM_CONFIG_REG4, reg);
3167 /* enable PHY Quick Link */
3168 msk = sky2_read32(hw, B0_IMSK);
3169 msk |= Y2_IS_PHY_QLNK;
3170 sky2_write32(hw, B0_IMSK, msk);
3172 /* check if PSMv2 was running before */
3173 reg = sky2_pci_read16(hw, PSM_CONFIG_REG3);
3174 if (reg & PCI_EXP_LNKCTL_ASPMC)
3175 /* restore the PCIe Link Control register */
3176 sky2_pci_write16(hw, pdev->pcie_cap + PCI_EXP_LNKCTL,
3179 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3181 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
3182 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
3185 /* Clear I2C IRQ noise */
3186 sky2_write32(hw, B2_I2C_IRQ, 1);
3188 /* turn off hardware timer (unused) */
3189 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
3190 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3192 /* Turn off descriptor polling */
3193 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
3195 /* Turn off receive timestamp */
3196 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
3197 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
3199 /* enable the Tx Arbiters */
3200 for (i = 0; i < hw->ports; i++)
3201 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3203 /* Initialize ram interface */
3204 for (i = 0; i < hw->ports; i++) {
3205 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
3207 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
3208 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
3209 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
3210 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
3211 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
3212 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
3213 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
3214 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
3215 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
3216 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
3217 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
3218 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
3221 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
3223 for (i = 0; i < hw->ports; i++)
3224 sky2_gmac_reset(hw, i);
3226 memset(hw->st_le, 0, hw->st_size * sizeof(struct sky2_status_le));
3229 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
3230 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
3232 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
3233 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
3235 /* Set the list last index */
3236 sky2_write16(hw, STAT_LAST_IDX, hw->st_size - 1);
3238 sky2_write16(hw, STAT_TX_IDX_TH, 10);
3239 sky2_write8(hw, STAT_FIFO_WM, 16);
3241 /* set Status-FIFO ISR watermark */
3242 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
3243 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
3245 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
3247 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
3248 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3249 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
3251 /* enable status unit */
3252 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3254 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3255 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3256 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3259 /* Take device down (offline).
3260 * Equivalent to doing dev_stop() but this does not
3261 * inform upper layers of the transition.
3263 static void sky2_detach(struct net_device *dev)
3265 if (netif_running(dev)) {
3267 netif_device_detach(dev); /* stop txq */
3268 netif_tx_unlock(dev);
3273 /* Bring device back after doing sky2_detach */
3274 static int sky2_reattach(struct net_device *dev)
3278 if (netif_running(dev)) {
3281 netdev_info(dev, "could not restart %d\n", err);
3284 netif_device_attach(dev);
3285 sky2_set_multicast(dev);
3292 static void sky2_all_down(struct sky2_hw *hw)
3296 sky2_read32(hw, B0_IMSK);
3297 sky2_write32(hw, B0_IMSK, 0);
3298 synchronize_irq(hw->pdev->irq);
3299 napi_disable(&hw->napi);
3301 for (i = 0; i < hw->ports; i++) {
3302 struct net_device *dev = hw->dev[i];
3303 struct sky2_port *sky2 = netdev_priv(dev);
3305 if (!netif_running(dev))
3308 netif_carrier_off(dev);
3309 netif_tx_disable(dev);
3314 static void sky2_all_up(struct sky2_hw *hw)
3316 u32 imask = Y2_IS_BASE;
3319 for (i = 0; i < hw->ports; i++) {
3320 struct net_device *dev = hw->dev[i];
3321 struct sky2_port *sky2 = netdev_priv(dev);
3323 if (!netif_running(dev))
3327 sky2_set_multicast(dev);
3328 imask |= portirq_msk[i];
3329 netif_wake_queue(dev);
3332 sky2_write32(hw, B0_IMSK, imask);
3333 sky2_read32(hw, B0_IMSK);
3335 sky2_read32(hw, B0_Y2_SP_LISR);
3336 napi_enable(&hw->napi);
3339 static void sky2_restart(struct work_struct *work)
3341 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
3352 static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3354 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3357 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3359 const struct sky2_port *sky2 = netdev_priv(dev);
3361 wol->supported = sky2_wol_supported(sky2->hw);
3362 wol->wolopts = sky2->wol;
3365 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3367 struct sky2_port *sky2 = netdev_priv(dev);
3368 struct sky2_hw *hw = sky2->hw;
3369 bool enable_wakeup = false;
3372 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw)) ||
3373 !device_can_wakeup(&hw->pdev->dev))
3376 sky2->wol = wol->wolopts;
3378 for (i = 0; i < hw->ports; i++) {
3379 struct net_device *dev = hw->dev[i];
3380 struct sky2_port *sky2 = netdev_priv(dev);
3383 enable_wakeup = true;
3385 device_set_wakeup_enable(&hw->pdev->dev, enable_wakeup);
3390 static u32 sky2_supported_modes(const struct sky2_hw *hw)
3392 if (sky2_is_copper(hw)) {
3393 u32 modes = SUPPORTED_10baseT_Half
3394 | SUPPORTED_10baseT_Full
3395 | SUPPORTED_100baseT_Half
3396 | SUPPORTED_100baseT_Full;
3398 if (hw->flags & SKY2_HW_GIGABIT)
3399 modes |= SUPPORTED_1000baseT_Half
3400 | SUPPORTED_1000baseT_Full;
3403 return SUPPORTED_1000baseT_Half
3404 | SUPPORTED_1000baseT_Full;
3407 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3409 struct sky2_port *sky2 = netdev_priv(dev);
3410 struct sky2_hw *hw = sky2->hw;
3412 ecmd->transceiver = XCVR_INTERNAL;
3413 ecmd->supported = sky2_supported_modes(hw);
3414 ecmd->phy_address = PHY_ADDR_MARV;
3415 if (sky2_is_copper(hw)) {
3416 ecmd->port = PORT_TP;
3417 ethtool_cmd_speed_set(ecmd, sky2->speed);
3418 ecmd->supported |= SUPPORTED_Autoneg | SUPPORTED_TP;
3420 ethtool_cmd_speed_set(ecmd, SPEED_1000);
3421 ecmd->port = PORT_FIBRE;
3422 ecmd->supported |= SUPPORTED_Autoneg | SUPPORTED_FIBRE;
3425 ecmd->advertising = sky2->advertising;
3426 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_SPEED)
3427 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
3428 ecmd->duplex = sky2->duplex;
3432 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3434 struct sky2_port *sky2 = netdev_priv(dev);
3435 const struct sky2_hw *hw = sky2->hw;
3436 u32 supported = sky2_supported_modes(hw);
3438 if (ecmd->autoneg == AUTONEG_ENABLE) {
3439 if (ecmd->advertising & ~supported)
3442 if (sky2_is_copper(hw))
3443 sky2->advertising = ecmd->advertising |
3447 sky2->advertising = ecmd->advertising |
3451 sky2->flags |= SKY2_FLAG_AUTO_SPEED;
3456 u32 speed = ethtool_cmd_speed(ecmd);
3460 if (ecmd->duplex == DUPLEX_FULL)
3461 setting = SUPPORTED_1000baseT_Full;
3462 else if (ecmd->duplex == DUPLEX_HALF)
3463 setting = SUPPORTED_1000baseT_Half;
3468 if (ecmd->duplex == DUPLEX_FULL)
3469 setting = SUPPORTED_100baseT_Full;
3470 else if (ecmd->duplex == DUPLEX_HALF)
3471 setting = SUPPORTED_100baseT_Half;
3477 if (ecmd->duplex == DUPLEX_FULL)
3478 setting = SUPPORTED_10baseT_Full;
3479 else if (ecmd->duplex == DUPLEX_HALF)
3480 setting = SUPPORTED_10baseT_Half;
3488 if ((setting & supported) == 0)
3491 sky2->speed = speed;
3492 sky2->duplex = ecmd->duplex;
3493 sky2->flags &= ~SKY2_FLAG_AUTO_SPEED;
3496 if (netif_running(dev)) {
3497 sky2_phy_reinit(sky2);
3498 sky2_set_multicast(dev);
3504 static void sky2_get_drvinfo(struct net_device *dev,
3505 struct ethtool_drvinfo *info)
3507 struct sky2_port *sky2 = netdev_priv(dev);
3509 strcpy(info->driver, DRV_NAME);
3510 strcpy(info->version, DRV_VERSION);
3511 strcpy(info->fw_version, "N/A");
3512 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3515 static const struct sky2_stat {
3516 char name[ETH_GSTRING_LEN];
3519 { "tx_bytes", GM_TXO_OK_HI },
3520 { "rx_bytes", GM_RXO_OK_HI },
3521 { "tx_broadcast", GM_TXF_BC_OK },
3522 { "rx_broadcast", GM_RXF_BC_OK },
3523 { "tx_multicast", GM_TXF_MC_OK },
3524 { "rx_multicast", GM_RXF_MC_OK },
3525 { "tx_unicast", GM_TXF_UC_OK },
3526 { "rx_unicast", GM_RXF_UC_OK },
3527 { "tx_mac_pause", GM_TXF_MPAUSE },
3528 { "rx_mac_pause", GM_RXF_MPAUSE },
3529 { "collisions", GM_TXF_COL },
3530 { "late_collision",GM_TXF_LAT_COL },
3531 { "aborted", GM_TXF_ABO_COL },
3532 { "single_collisions", GM_TXF_SNG_COL },
3533 { "multi_collisions", GM_TXF_MUL_COL },
3535 { "rx_short", GM_RXF_SHT },
3536 { "rx_runt", GM_RXE_FRAG },
3537 { "rx_64_byte_packets", GM_RXF_64B },
3538 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3539 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3540 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3541 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3542 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3543 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
3544 { "rx_too_long", GM_RXF_LNG_ERR },
3545 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3546 { "rx_jabber", GM_RXF_JAB_PKT },
3547 { "rx_fcs_error", GM_RXF_FCS_ERR },
3549 { "tx_64_byte_packets", GM_TXF_64B },
3550 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3551 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3552 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3553 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3554 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3555 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3556 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
3559 static u32 sky2_get_msglevel(struct net_device *netdev)
3561 struct sky2_port *sky2 = netdev_priv(netdev);
3562 return sky2->msg_enable;
3565 static int sky2_nway_reset(struct net_device *dev)
3567 struct sky2_port *sky2 = netdev_priv(dev);
3569 if (!netif_running(dev) || !(sky2->flags & SKY2_FLAG_AUTO_SPEED))
3572 sky2_phy_reinit(sky2);
3573 sky2_set_multicast(dev);
3578 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
3580 struct sky2_hw *hw = sky2->hw;
3581 unsigned port = sky2->port;
3584 data[0] = get_stats64(hw, port, GM_TXO_OK_LO);
3585 data[1] = get_stats64(hw, port, GM_RXO_OK_LO);
3587 for (i = 2; i < count; i++)
3588 data[i] = get_stats32(hw, port, sky2_stats[i].offset);
3591 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3593 struct sky2_port *sky2 = netdev_priv(netdev);
3594 sky2->msg_enable = value;
3597 static int sky2_get_sset_count(struct net_device *dev, int sset)
3601 return ARRAY_SIZE(sky2_stats);
3607 static void sky2_get_ethtool_stats(struct net_device *dev,
3608 struct ethtool_stats *stats, u64 * data)
3610 struct sky2_port *sky2 = netdev_priv(dev);
3612 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
3615 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
3619 switch (stringset) {
3621 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3622 memcpy(data + i * ETH_GSTRING_LEN,
3623 sky2_stats[i].name, ETH_GSTRING_LEN);
3628 static int sky2_set_mac_address(struct net_device *dev, void *p)
3630 struct sky2_port *sky2 = netdev_priv(dev);
3631 struct sky2_hw *hw = sky2->hw;
3632 unsigned port = sky2->port;
3633 const struct sockaddr *addr = p;
3635 if (!is_valid_ether_addr(addr->sa_data))
3636 return -EADDRNOTAVAIL;
3638 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3639 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
3640 dev->dev_addr, ETH_ALEN);
3641 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
3642 dev->dev_addr, ETH_ALEN);
3644 /* virtual address for data */
3645 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3647 /* physical address: used for pause frames */
3648 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3653 static inline void sky2_add_filter(u8 filter[8], const u8 *addr)
3657 bit = ether_crc(ETH_ALEN, addr) & 63;
3658 filter[bit >> 3] |= 1 << (bit & 7);
3661 static void sky2_set_multicast(struct net_device *dev)
3663 struct sky2_port *sky2 = netdev_priv(dev);
3664 struct sky2_hw *hw = sky2->hw;
3665 unsigned port = sky2->port;
3666 struct netdev_hw_addr *ha;
3670 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3672 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
3673 memset(filter, 0, sizeof(filter));
3675 reg = gma_read16(hw, port, GM_RX_CTRL);
3676 reg |= GM_RXCR_UCF_ENA;
3678 if (dev->flags & IFF_PROMISC) /* promiscuous */
3679 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
3680 else if (dev->flags & IFF_ALLMULTI)
3681 memset(filter, 0xff, sizeof(filter));
3682 else if (netdev_mc_empty(dev) && !rx_pause)
3683 reg &= ~GM_RXCR_MCF_ENA;
3685 reg |= GM_RXCR_MCF_ENA;
3688 sky2_add_filter(filter, pause_mc_addr);
3690 netdev_for_each_mc_addr(ha, dev)
3691 sky2_add_filter(filter, ha->addr);
3694 gma_write16(hw, port, GM_MC_ADDR_H1,
3695 (u16) filter[0] | ((u16) filter[1] << 8));
3696 gma_write16(hw, port, GM_MC_ADDR_H2,
3697 (u16) filter[2] | ((u16) filter[3] << 8));
3698 gma_write16(hw, port, GM_MC_ADDR_H3,
3699 (u16) filter[4] | ((u16) filter[5] << 8));
3700 gma_write16(hw, port, GM_MC_ADDR_H4,
3701 (u16) filter[6] | ((u16) filter[7] << 8));
3703 gma_write16(hw, port, GM_RX_CTRL, reg);
3706 static struct rtnl_link_stats64 *sky2_get_stats(struct net_device *dev,
3707 struct rtnl_link_stats64 *stats)
3709 struct sky2_port *sky2 = netdev_priv(dev);
3710 struct sky2_hw *hw = sky2->hw;
3711 unsigned port = sky2->port;
3713 u64 _bytes, _packets;
3716 start = u64_stats_fetch_begin_bh(&sky2->rx_stats.syncp);
3717 _bytes = sky2->rx_stats.bytes;
3718 _packets = sky2->rx_stats.packets;
3719 } while (u64_stats_fetch_retry_bh(&sky2->rx_stats.syncp, start));
3721 stats->rx_packets = _packets;
3722 stats->rx_bytes = _bytes;
3725 start = u64_stats_fetch_begin_bh(&sky2->tx_stats.syncp);
3726 _bytes = sky2->tx_stats.bytes;
3727 _packets = sky2->tx_stats.packets;
3728 } while (u64_stats_fetch_retry_bh(&sky2->tx_stats.syncp, start));
3730 stats->tx_packets = _packets;
3731 stats->tx_bytes = _bytes;
3733 stats->multicast = get_stats32(hw, port, GM_RXF_MC_OK)
3734 + get_stats32(hw, port, GM_RXF_BC_OK);
3736 stats->collisions = get_stats32(hw, port, GM_TXF_COL);
3738 stats->rx_length_errors = get_stats32(hw, port, GM_RXF_LNG_ERR);
3739 stats->rx_crc_errors = get_stats32(hw, port, GM_RXF_FCS_ERR);
3740 stats->rx_frame_errors = get_stats32(hw, port, GM_RXF_SHT)
3741 + get_stats32(hw, port, GM_RXE_FRAG);
3742 stats->rx_over_errors = get_stats32(hw, port, GM_RXE_FIFO_OV);
3744 stats->rx_dropped = dev->stats.rx_dropped;
3745 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
3746 stats->tx_fifo_errors = dev->stats.tx_fifo_errors;
3751 /* Can have one global because blinking is controlled by
3752 * ethtool and that is always under RTNL mutex
3754 static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
3756 struct sky2_hw *hw = sky2->hw;
3757 unsigned port = sky2->port;
3759 spin_lock_bh(&sky2->phy_lock);
3760 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3761 hw->chip_id == CHIP_ID_YUKON_EX ||
3762 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3764 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3765 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3769 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3770 PHY_M_LEDC_LOS_CTRL(8) |
3771 PHY_M_LEDC_INIT_CTRL(8) |
3772 PHY_M_LEDC_STA1_CTRL(8) |
3773 PHY_M_LEDC_STA0_CTRL(8));
3776 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3777 PHY_M_LEDC_LOS_CTRL(9) |
3778 PHY_M_LEDC_INIT_CTRL(9) |
3779 PHY_M_LEDC_STA1_CTRL(9) |
3780 PHY_M_LEDC_STA0_CTRL(9));
3783 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3784 PHY_M_LEDC_LOS_CTRL(0xa) |
3785 PHY_M_LEDC_INIT_CTRL(0xa) |
3786 PHY_M_LEDC_STA1_CTRL(0xa) |
3787 PHY_M_LEDC_STA0_CTRL(0xa));
3790 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3791 PHY_M_LEDC_LOS_CTRL(1) |
3792 PHY_M_LEDC_INIT_CTRL(8) |
3793 PHY_M_LEDC_STA1_CTRL(7) |
3794 PHY_M_LEDC_STA0_CTRL(7));
3797 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3799 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3800 PHY_M_LED_MO_DUP(mode) |
3801 PHY_M_LED_MO_10(mode) |
3802 PHY_M_LED_MO_100(mode) |
3803 PHY_M_LED_MO_1000(mode) |
3804 PHY_M_LED_MO_RX(mode) |
3805 PHY_M_LED_MO_TX(mode));
3807 spin_unlock_bh(&sky2->phy_lock);
3810 /* blink LED's for finding board */
3811 static int sky2_set_phys_id(struct net_device *dev,
3812 enum ethtool_phys_id_state state)
3814 struct sky2_port *sky2 = netdev_priv(dev);
3817 case ETHTOOL_ID_ACTIVE:
3818 return 1; /* cycle on/off once per second */
3819 case ETHTOOL_ID_INACTIVE:
3820 sky2_led(sky2, MO_LED_NORM);
3823 sky2_led(sky2, MO_LED_ON);
3825 case ETHTOOL_ID_OFF:
3826 sky2_led(sky2, MO_LED_OFF);
3833 static void sky2_get_pauseparam(struct net_device *dev,
3834 struct ethtool_pauseparam *ecmd)
3836 struct sky2_port *sky2 = netdev_priv(dev);
3838 switch (sky2->flow_mode) {
3840 ecmd->tx_pause = ecmd->rx_pause = 0;
3843 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3846 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3849 ecmd->tx_pause = ecmd->rx_pause = 1;
3852 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_PAUSE)
3853 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
3856 static int sky2_set_pauseparam(struct net_device *dev,
3857 struct ethtool_pauseparam *ecmd)
3859 struct sky2_port *sky2 = netdev_priv(dev);
3861 if (ecmd->autoneg == AUTONEG_ENABLE)
3862 sky2->flags |= SKY2_FLAG_AUTO_PAUSE;
3864 sky2->flags &= ~SKY2_FLAG_AUTO_PAUSE;
3866 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
3868 if (netif_running(dev))
3869 sky2_phy_reinit(sky2);
3874 static int sky2_get_coalesce(struct net_device *dev,
3875 struct ethtool_coalesce *ecmd)
3877 struct sky2_port *sky2 = netdev_priv(dev);
3878 struct sky2_hw *hw = sky2->hw;
3880 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3881 ecmd->tx_coalesce_usecs = 0;
3883 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3884 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3886 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3888 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3889 ecmd->rx_coalesce_usecs = 0;
3891 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3892 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3894 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3896 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3897 ecmd->rx_coalesce_usecs_irq = 0;
3899 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3900 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3903 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3908 /* Note: this affect both ports */
3909 static int sky2_set_coalesce(struct net_device *dev,
3910 struct ethtool_coalesce *ecmd)
3912 struct sky2_port *sky2 = netdev_priv(dev);
3913 struct sky2_hw *hw = sky2->hw;
3914 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
3916 if (ecmd->tx_coalesce_usecs > tmax ||
3917 ecmd->rx_coalesce_usecs > tmax ||
3918 ecmd->rx_coalesce_usecs_irq > tmax)
3921 if (ecmd->tx_max_coalesced_frames >= sky2->tx_ring_size-1)
3923 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
3925 if (ecmd->rx_max_coalesced_frames_irq > RX_MAX_PENDING)
3928 if (ecmd->tx_coalesce_usecs == 0)
3929 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3931 sky2_write32(hw, STAT_TX_TIMER_INI,
3932 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3933 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3935 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3937 if (ecmd->rx_coalesce_usecs == 0)
3938 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3940 sky2_write32(hw, STAT_LEV_TIMER_INI,
3941 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3942 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3944 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3946 if (ecmd->rx_coalesce_usecs_irq == 0)
3947 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3949 sky2_write32(hw, STAT_ISR_TIMER_INI,
3950 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3951 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3953 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3957 static void sky2_get_ringparam(struct net_device *dev,
3958 struct ethtool_ringparam *ering)
3960 struct sky2_port *sky2 = netdev_priv(dev);
3962 ering->rx_max_pending = RX_MAX_PENDING;
3963 ering->rx_mini_max_pending = 0;
3964 ering->rx_jumbo_max_pending = 0;
3965 ering->tx_max_pending = TX_MAX_PENDING;
3967 ering->rx_pending = sky2->rx_pending;
3968 ering->rx_mini_pending = 0;
3969 ering->rx_jumbo_pending = 0;
3970 ering->tx_pending = sky2->tx_pending;
3973 static int sky2_set_ringparam(struct net_device *dev,
3974 struct ethtool_ringparam *ering)
3976 struct sky2_port *sky2 = netdev_priv(dev);
3978 if (ering->rx_pending > RX_MAX_PENDING ||
3979 ering->rx_pending < 8 ||
3980 ering->tx_pending < TX_MIN_PENDING ||
3981 ering->tx_pending > TX_MAX_PENDING)
3986 sky2->rx_pending = ering->rx_pending;
3987 sky2->tx_pending = ering->tx_pending;
3988 sky2->tx_ring_size = roundup_pow_of_two(sky2->tx_pending+1);
3990 return sky2_reattach(dev);
3993 static int sky2_get_regs_len(struct net_device *dev)
3998 static int sky2_reg_access_ok(struct sky2_hw *hw, unsigned int b)
4000 /* This complicated switch statement is to make sure and
4001 * only access regions that are unreserved.
4002 * Some blocks are only valid on dual port cards.
4006 case 5: /* Tx Arbiter 2 */
4008 case 14 ... 15: /* TX2 */
4009 case 17: case 19: /* Ram Buffer 2 */
4010 case 22 ... 23: /* Tx Ram Buffer 2 */
4011 case 25: /* Rx MAC Fifo 1 */
4012 case 27: /* Tx MAC Fifo 2 */
4013 case 31: /* GPHY 2 */
4014 case 40 ... 47: /* Pattern Ram 2 */
4015 case 52: case 54: /* TCP Segmentation 2 */
4016 case 112 ... 116: /* GMAC 2 */
4017 return hw->ports > 1;
4019 case 0: /* Control */
4020 case 2: /* Mac address */
4021 case 4: /* Tx Arbiter 1 */
4022 case 7: /* PCI express reg */
4024 case 12 ... 13: /* TX1 */
4025 case 16: case 18:/* Rx Ram Buffer 1 */
4026 case 20 ... 21: /* Tx Ram Buffer 1 */
4027 case 24: /* Rx MAC Fifo 1 */
4028 case 26: /* Tx MAC Fifo 1 */
4029 case 28 ... 29: /* Descriptor and status unit */
4030 case 30: /* GPHY 1*/
4031 case 32 ... 39: /* Pattern Ram 1 */
4032 case 48: case 50: /* TCP Segmentation 1 */
4033 case 56 ... 60: /* PCI space */
4034 case 80 ... 84: /* GMAC 1 */
4043 * Returns copy of control register region
4044 * Note: ethtool_get_regs always provides full size (16k) buffer
4046 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
4049 const struct sky2_port *sky2 = netdev_priv(dev);
4050 const void __iomem *io = sky2->hw->regs;
4055 for (b = 0; b < 128; b++) {
4056 /* skip poisonous diagnostic ram region in block 3 */
4058 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
4059 else if (sky2_reg_access_ok(sky2->hw, b))
4060 memcpy_fromio(p, io, 128);
4069 static int sky2_get_eeprom_len(struct net_device *dev)
4071 struct sky2_port *sky2 = netdev_priv(dev);
4072 struct sky2_hw *hw = sky2->hw;
4075 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
4076 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4079 static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy)
4081 unsigned long start = jiffies;
4083 while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) {
4084 /* Can take up to 10.6 ms for write */
4085 if (time_after(jiffies, start + HZ/4)) {
4086 dev_err(&hw->pdev->dev, "VPD cycle timed out\n");
4095 static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data,
4096 u16 offset, size_t length)
4100 while (length > 0) {
4103 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
4104 rc = sky2_vpd_wait(hw, cap, 0);
4108 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
4110 memcpy(data, &val, min(sizeof(val), length));
4111 offset += sizeof(u32);
4112 data += sizeof(u32);
4113 length -= sizeof(u32);
4119 static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data,
4120 u16 offset, unsigned int length)
4125 for (i = 0; i < length; i += sizeof(u32)) {
4126 u32 val = *(u32 *)(data + i);
4128 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
4129 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
4131 rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F);
4138 static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4141 struct sky2_port *sky2 = netdev_priv(dev);
4142 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
4147 eeprom->magic = SKY2_EEPROM_MAGIC;
4149 return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len);
4152 static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4155 struct sky2_port *sky2 = netdev_priv(dev);
4156 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
4161 if (eeprom->magic != SKY2_EEPROM_MAGIC)
4164 /* Partial writes not supported */
4165 if ((eeprom->offset & 3) || (eeprom->len & 3))
4168 return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len);
4171 static u32 sky2_fix_features(struct net_device *dev, u32 features)
4173 const struct sky2_port *sky2 = netdev_priv(dev);
4174 const struct sky2_hw *hw = sky2->hw;
4176 /* In order to do Jumbo packets on these chips, need to turn off the
4177 * transmit store/forward. Therefore checksum offload won't work.
4179 if (dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U)
4180 features &= ~(NETIF_F_TSO|NETIF_F_SG|NETIF_F_ALL_CSUM);
4185 static int sky2_set_features(struct net_device *dev, u32 features)
4187 struct sky2_port *sky2 = netdev_priv(dev);
4188 u32 changed = dev->features ^ features;
4190 if (changed & NETIF_F_RXCSUM) {
4191 u32 on = features & NETIF_F_RXCSUM;
4192 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
4193 on ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
4196 if (changed & NETIF_F_RXHASH)
4197 rx_set_rss(dev, features);
4199 if (changed & (NETIF_F_HW_VLAN_TX|NETIF_F_HW_VLAN_RX))
4200 sky2_vlan_mode(dev, features);
4205 static const struct ethtool_ops sky2_ethtool_ops = {
4206 .get_settings = sky2_get_settings,
4207 .set_settings = sky2_set_settings,
4208 .get_drvinfo = sky2_get_drvinfo,
4209 .get_wol = sky2_get_wol,
4210 .set_wol = sky2_set_wol,
4211 .get_msglevel = sky2_get_msglevel,
4212 .set_msglevel = sky2_set_msglevel,
4213 .nway_reset = sky2_nway_reset,
4214 .get_regs_len = sky2_get_regs_len,
4215 .get_regs = sky2_get_regs,
4216 .get_link = ethtool_op_get_link,
4217 .get_eeprom_len = sky2_get_eeprom_len,
4218 .get_eeprom = sky2_get_eeprom,
4219 .set_eeprom = sky2_set_eeprom,
4220 .get_strings = sky2_get_strings,
4221 .get_coalesce = sky2_get_coalesce,
4222 .set_coalesce = sky2_set_coalesce,
4223 .get_ringparam = sky2_get_ringparam,
4224 .set_ringparam = sky2_set_ringparam,
4225 .get_pauseparam = sky2_get_pauseparam,
4226 .set_pauseparam = sky2_set_pauseparam,
4227 .set_phys_id = sky2_set_phys_id,
4228 .get_sset_count = sky2_get_sset_count,
4229 .get_ethtool_stats = sky2_get_ethtool_stats,
4232 #ifdef CONFIG_SKY2_DEBUG
4234 static struct dentry *sky2_debug;
4238 * Read and parse the first part of Vital Product Data
4240 #define VPD_SIZE 128
4241 #define VPD_MAGIC 0x82
4243 static const struct vpd_tag {
4247 { "PN", "Part Number" },
4248 { "EC", "Engineering Level" },
4249 { "MN", "Manufacturer" },
4250 { "SN", "Serial Number" },
4251 { "YA", "Asset Tag" },
4252 { "VL", "First Error Log Message" },
4253 { "VF", "Second Error Log Message" },
4254 { "VB", "Boot Agent ROM Configuration" },
4255 { "VE", "EFI UNDI Configuration" },
4258 static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw)
4266 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
4267 vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4269 seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev));
4270 buf = kmalloc(vpd_size, GFP_KERNEL);
4272 seq_puts(seq, "no memory!\n");
4276 if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) {
4277 seq_puts(seq, "VPD read failed\n");
4281 if (buf[0] != VPD_MAGIC) {
4282 seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]);
4286 if (len == 0 || len > vpd_size - 4) {
4287 seq_printf(seq, "Invalid id length: %d\n", len);
4291 seq_printf(seq, "%.*s\n", len, buf + 3);
4294 while (offs < vpd_size - 4) {
4297 if (!memcmp("RW", buf + offs, 2)) /* end marker */
4299 len = buf[offs + 2];
4300 if (offs + len + 3 >= vpd_size)
4303 for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) {
4304 if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) {
4305 seq_printf(seq, " %s: %.*s\n",
4306 vpd_tags[i].label, len, buf + offs + 3);
4316 static int sky2_debug_show(struct seq_file *seq, void *v)
4318 struct net_device *dev = seq->private;
4319 const struct sky2_port *sky2 = netdev_priv(dev);
4320 struct sky2_hw *hw = sky2->hw;
4321 unsigned port = sky2->port;
4325 sky2_show_vpd(seq, hw);
4327 seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n",
4328 sky2_read32(hw, B0_ISRC),
4329 sky2_read32(hw, B0_IMSK),
4330 sky2_read32(hw, B0_Y2_SP_ICR));
4332 if (!netif_running(dev)) {
4333 seq_printf(seq, "network not running\n");
4337 napi_disable(&hw->napi);
4338 last = sky2_read16(hw, STAT_PUT_IDX);
4340 seq_printf(seq, "Status ring %u\n", hw->st_size);
4341 if (hw->st_idx == last)
4342 seq_puts(seq, "Status ring (empty)\n");
4344 seq_puts(seq, "Status ring\n");
4345 for (idx = hw->st_idx; idx != last && idx < hw->st_size;
4346 idx = RING_NEXT(idx, hw->st_size)) {
4347 const struct sky2_status_le *le = hw->st_le + idx;
4348 seq_printf(seq, "[%d] %#x %d %#x\n",
4349 idx, le->opcode, le->length, le->status);
4351 seq_puts(seq, "\n");
4354 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
4355 sky2->tx_cons, sky2->tx_prod,
4356 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
4357 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
4359 /* Dump contents of tx ring */
4361 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < sky2->tx_ring_size;
4362 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
4363 const struct sky2_tx_le *le = sky2->tx_le + idx;
4364 u32 a = le32_to_cpu(le->addr);
4367 seq_printf(seq, "%u:", idx);
4370 switch (le->opcode & ~HW_OWNER) {
4372 seq_printf(seq, " %#x:", a);
4375 seq_printf(seq, " mtu=%d", a);
4378 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
4381 seq_printf(seq, " csum=%#x", a);
4384 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
4387 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
4390 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
4393 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
4394 a, le16_to_cpu(le->length));
4397 if (le->ctrl & EOP) {
4398 seq_putc(seq, '\n');
4403 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
4404 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
4405 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
4406 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
4408 sky2_read32(hw, B0_Y2_SP_LISR);
4409 napi_enable(&hw->napi);
4413 static int sky2_debug_open(struct inode *inode, struct file *file)
4415 return single_open(file, sky2_debug_show, inode->i_private);
4418 static const struct file_operations sky2_debug_fops = {
4419 .owner = THIS_MODULE,
4420 .open = sky2_debug_open,
4422 .llseek = seq_lseek,
4423 .release = single_release,
4427 * Use network device events to create/remove/rename
4428 * debugfs file entries
4430 static int sky2_device_event(struct notifier_block *unused,
4431 unsigned long event, void *ptr)
4433 struct net_device *dev = ptr;
4434 struct sky2_port *sky2 = netdev_priv(dev);
4436 if (dev->netdev_ops->ndo_open != sky2_up || !sky2_debug)
4440 case NETDEV_CHANGENAME:
4441 if (sky2->debugfs) {
4442 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
4443 sky2_debug, dev->name);
4447 case NETDEV_GOING_DOWN:
4448 if (sky2->debugfs) {
4449 netdev_printk(KERN_DEBUG, dev, "remove debugfs\n");
4450 debugfs_remove(sky2->debugfs);
4451 sky2->debugfs = NULL;
4456 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
4459 if (IS_ERR(sky2->debugfs))
4460 sky2->debugfs = NULL;
4466 static struct notifier_block sky2_notifier = {
4467 .notifier_call = sky2_device_event,
4471 static __init void sky2_debug_init(void)
4475 ent = debugfs_create_dir("sky2", NULL);
4476 if (!ent || IS_ERR(ent))
4480 register_netdevice_notifier(&sky2_notifier);
4483 static __exit void sky2_debug_cleanup(void)
4486 unregister_netdevice_notifier(&sky2_notifier);
4487 debugfs_remove(sky2_debug);
4493 #define sky2_debug_init()
4494 #define sky2_debug_cleanup()
4497 /* Two copies of network device operations to handle special case of
4498 not allowing netpoll on second port */
4499 static const struct net_device_ops sky2_netdev_ops[2] = {
4501 .ndo_open = sky2_up,
4502 .ndo_stop = sky2_down,
4503 .ndo_start_xmit = sky2_xmit_frame,
4504 .ndo_do_ioctl = sky2_ioctl,
4505 .ndo_validate_addr = eth_validate_addr,
4506 .ndo_set_mac_address = sky2_set_mac_address,
4507 .ndo_set_multicast_list = sky2_set_multicast,
4508 .ndo_change_mtu = sky2_change_mtu,
4509 .ndo_fix_features = sky2_fix_features,
4510 .ndo_set_features = sky2_set_features,
4511 .ndo_tx_timeout = sky2_tx_timeout,
4512 .ndo_get_stats64 = sky2_get_stats,
4513 #ifdef CONFIG_NET_POLL_CONTROLLER
4514 .ndo_poll_controller = sky2_netpoll,
4518 .ndo_open = sky2_up,
4519 .ndo_stop = sky2_down,
4520 .ndo_start_xmit = sky2_xmit_frame,
4521 .ndo_do_ioctl = sky2_ioctl,
4522 .ndo_validate_addr = eth_validate_addr,
4523 .ndo_set_mac_address = sky2_set_mac_address,
4524 .ndo_set_multicast_list = sky2_set_multicast,
4525 .ndo_change_mtu = sky2_change_mtu,
4526 .ndo_fix_features = sky2_fix_features,
4527 .ndo_set_features = sky2_set_features,
4528 .ndo_tx_timeout = sky2_tx_timeout,
4529 .ndo_get_stats64 = sky2_get_stats,
4533 /* Initialize network device */
4534 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
4536 int highmem, int wol)
4538 struct sky2_port *sky2;
4539 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4542 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
4546 SET_NETDEV_DEV(dev, &hw->pdev->dev);
4547 dev->irq = hw->pdev->irq;
4548 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
4549 dev->watchdog_timeo = TX_WATCHDOG;
4550 dev->netdev_ops = &sky2_netdev_ops[port];
4552 sky2 = netdev_priv(dev);
4555 sky2->msg_enable = netif_msg_init(debug, default_msg);
4557 /* Auto speed and flow control */
4558 sky2->flags = SKY2_FLAG_AUTO_SPEED | SKY2_FLAG_AUTO_PAUSE;
4559 if (hw->chip_id != CHIP_ID_YUKON_XL)
4560 dev->hw_features |= NETIF_F_RXCSUM;
4562 sky2->flow_mode = FC_BOTH;
4566 sky2->advertising = sky2_supported_modes(hw);
4569 spin_lock_init(&sky2->phy_lock);
4571 sky2->tx_pending = TX_DEF_PENDING;
4572 sky2->tx_ring_size = roundup_pow_of_two(TX_DEF_PENDING+1);
4573 sky2->rx_pending = RX_DEF_PENDING;
4575 hw->dev[port] = dev;
4579 dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO;
4582 dev->features |= NETIF_F_HIGHDMA;
4584 /* Enable receive hashing unless hardware is known broken */
4585 if (!(hw->flags & SKY2_HW_RSS_BROKEN))
4586 dev->hw_features |= NETIF_F_RXHASH;
4588 if (!(hw->flags & SKY2_HW_VLAN_BROKEN)) {
4589 dev->hw_features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4590 dev->vlan_features |= SKY2_VLAN_OFFLOADS;
4593 dev->features |= dev->hw_features;
4595 /* read the mac address */
4596 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
4597 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
4602 static void __devinit sky2_show_addr(struct net_device *dev)
4604 const struct sky2_port *sky2 = netdev_priv(dev);
4606 netif_info(sky2, probe, dev, "addr %pM\n", dev->dev_addr);
4609 /* Handle software interrupt used during MSI test */
4610 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
4612 struct sky2_hw *hw = dev_id;
4613 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4618 if (status & Y2_IS_IRQ_SW) {
4619 hw->flags |= SKY2_HW_USE_MSI;
4620 wake_up(&hw->msi_wait);
4621 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4623 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4628 /* Test interrupt path by forcing a a software IRQ */
4629 static int __devinit sky2_test_msi(struct sky2_hw *hw)
4631 struct pci_dev *pdev = hw->pdev;
4634 init_waitqueue_head(&hw->msi_wait);
4636 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4638 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
4640 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4644 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
4645 sky2_read8(hw, B0_CTST);
4647 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
4649 if (!(hw->flags & SKY2_HW_USE_MSI)) {
4650 /* MSI test failed, go back to INTx mode */
4651 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4652 "switching to INTx mode.\n");
4655 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4658 sky2_write32(hw, B0_IMSK, 0);
4659 sky2_read32(hw, B0_IMSK);
4661 free_irq(pdev->irq, hw);
4666 /* This driver supports yukon2 chipset only */
4667 static const char *sky2_name(u8 chipid, char *buf, int sz)
4669 const char *name[] = {
4671 "EC Ultra", /* 0xb4 */
4672 "Extreme", /* 0xb5 */
4676 "Supreme", /* 0xb9 */
4678 "Unknown", /* 0xbb */
4679 "Optima", /* 0xbc */
4682 if (chipid >= CHIP_ID_YUKON_XL && chipid <= CHIP_ID_YUKON_OPT)
4683 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
4685 snprintf(buf, sz, "(chip %#x)", chipid);
4689 static int __devinit sky2_probe(struct pci_dev *pdev,
4690 const struct pci_device_id *ent)
4692 struct net_device *dev;
4694 int err, using_dac = 0, wol_default;
4698 err = pci_enable_device(pdev);
4700 dev_err(&pdev->dev, "cannot enable PCI device\n");
4704 /* Get configuration information
4705 * Note: only regular PCI config access once to test for HW issues
4706 * other PCI access through shared memory for speed and to
4707 * avoid MMCONFIG problems.
4709 err = pci_read_config_dword(pdev, PCI_DEV_REG2, ®);
4711 dev_err(&pdev->dev, "PCI read config failed\n");
4716 dev_err(&pdev->dev, "PCI configuration read error\n");
4720 err = pci_request_regions(pdev, DRV_NAME);
4722 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
4723 goto err_out_disable;
4726 pci_set_master(pdev);
4728 if (sizeof(dma_addr_t) > sizeof(u32) &&
4729 !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) {
4731 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
4733 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4734 "for consistent allocations\n");
4735 goto err_out_free_regions;
4738 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4740 dev_err(&pdev->dev, "no usable DMA configuration\n");
4741 goto err_out_free_regions;
4747 /* The sk98lin vendor driver uses hardware byte swapping but
4748 * this driver uses software swapping.
4750 reg &= ~PCI_REV_DESC;
4751 err = pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
4753 dev_err(&pdev->dev, "PCI write config failed\n");
4754 goto err_out_free_regions;
4758 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0;
4762 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:")
4763 + strlen(pci_name(pdev)) + 1, GFP_KERNEL);
4765 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
4766 goto err_out_free_regions;
4770 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev));
4772 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4774 dev_err(&pdev->dev, "cannot map device registers\n");
4775 goto err_out_free_hw;
4778 err = sky2_init(hw);
4780 goto err_out_iounmap;
4782 /* ring for status responses */
4783 hw->st_size = hw->ports * roundup_pow_of_two(3*RX_MAX_PENDING + TX_MAX_PENDING);
4784 hw->st_le = pci_alloc_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le),
4789 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n",
4790 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev);
4794 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
4797 goto err_out_free_pci;
4800 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4801 err = sky2_test_msi(hw);
4802 if (err == -EOPNOTSUPP)
4803 pci_disable_msi(pdev);
4805 goto err_out_free_netdev;
4808 err = register_netdev(dev);
4810 dev_err(&pdev->dev, "cannot register net device\n");
4811 goto err_out_free_netdev;
4814 netif_carrier_off(dev);
4816 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4818 err = request_irq(pdev->irq, sky2_intr,
4819 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
4822 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4823 goto err_out_unregister;
4825 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4826 napi_enable(&hw->napi);
4828 sky2_show_addr(dev);
4830 if (hw->ports > 1) {
4831 struct net_device *dev1;
4834 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
4835 if (dev1 && (err = register_netdev(dev1)) == 0)
4836 sky2_show_addr(dev1);
4838 dev_warn(&pdev->dev,
4839 "register of second port failed (%d)\n", err);
4847 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
4848 INIT_WORK(&hw->restart_work, sky2_restart);
4850 pci_set_drvdata(pdev, hw);
4851 pdev->d3_delay = 150;
4856 if (hw->flags & SKY2_HW_USE_MSI)
4857 pci_disable_msi(pdev);
4858 unregister_netdev(dev);
4859 err_out_free_netdev:
4862 pci_free_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le),
4863 hw->st_le, hw->st_dma);
4865 sky2_write8(hw, B0_CTST, CS_RST_SET);
4870 err_out_free_regions:
4871 pci_release_regions(pdev);
4873 pci_disable_device(pdev);
4875 pci_set_drvdata(pdev, NULL);
4879 static void __devexit sky2_remove(struct pci_dev *pdev)
4881 struct sky2_hw *hw = pci_get_drvdata(pdev);
4887 del_timer_sync(&hw->watchdog_timer);
4888 cancel_work_sync(&hw->restart_work);
4890 for (i = hw->ports-1; i >= 0; --i)
4891 unregister_netdev(hw->dev[i]);
4893 sky2_write32(hw, B0_IMSK, 0);
4897 sky2_write8(hw, B0_CTST, CS_RST_SET);
4898 sky2_read8(hw, B0_CTST);
4900 free_irq(pdev->irq, hw);
4901 if (hw->flags & SKY2_HW_USE_MSI)
4902 pci_disable_msi(pdev);
4903 pci_free_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le),
4904 hw->st_le, hw->st_dma);
4905 pci_release_regions(pdev);
4906 pci_disable_device(pdev);
4908 for (i = hw->ports-1; i >= 0; --i)
4909 free_netdev(hw->dev[i]);
4914 pci_set_drvdata(pdev, NULL);
4917 static int sky2_suspend(struct device *dev)
4919 struct pci_dev *pdev = to_pci_dev(dev);
4920 struct sky2_hw *hw = pci_get_drvdata(pdev);
4926 del_timer_sync(&hw->watchdog_timer);
4927 cancel_work_sync(&hw->restart_work);
4932 for (i = 0; i < hw->ports; i++) {
4933 struct net_device *dev = hw->dev[i];
4934 struct sky2_port *sky2 = netdev_priv(dev);
4937 sky2_wol_init(sky2);
4946 #ifdef CONFIG_PM_SLEEP
4947 static int sky2_resume(struct device *dev)
4949 struct pci_dev *pdev = to_pci_dev(dev);
4950 struct sky2_hw *hw = pci_get_drvdata(pdev);
4956 /* Re-enable all clocks */
4957 err = pci_write_config_dword(pdev, PCI_DEV_REG3, 0);
4959 dev_err(&pdev->dev, "PCI write config failed\n");
4971 dev_err(&pdev->dev, "resume failed (%d)\n", err);
4972 pci_disable_device(pdev);
4976 static SIMPLE_DEV_PM_OPS(sky2_pm_ops, sky2_suspend, sky2_resume);
4977 #define SKY2_PM_OPS (&sky2_pm_ops)
4981 #define SKY2_PM_OPS NULL
4984 static void sky2_shutdown(struct pci_dev *pdev)
4986 sky2_suspend(&pdev->dev);
4987 pci_wake_from_d3(pdev, device_may_wakeup(&pdev->dev));
4988 pci_set_power_state(pdev, PCI_D3hot);
4991 static struct pci_driver sky2_driver = {
4993 .id_table = sky2_id_table,
4994 .probe = sky2_probe,
4995 .remove = __devexit_p(sky2_remove),
4996 .shutdown = sky2_shutdown,
4997 .driver.pm = SKY2_PM_OPS,
5000 static int __init sky2_init_module(void)
5002 pr_info("driver version " DRV_VERSION "\n");
5005 return pci_register_driver(&sky2_driver);
5008 static void __exit sky2_cleanup_module(void)
5010 pci_unregister_driver(&sky2_driver);
5011 sky2_debug_cleanup();
5014 module_init(sky2_init_module);
5015 module_exit(sky2_cleanup_module);
5017 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
5018 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
5019 MODULE_LICENSE("GPL");
5020 MODULE_VERSION(DRV_VERSION);