2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <linux/crc32.h>
26 #include <linux/kernel.h>
27 #include <linux/version.h>
28 #include <linux/module.h>
29 #include <linux/netdevice.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/pci.h>
36 #include <linux/tcp.h>
38 #include <linux/delay.h>
39 #include <linux/workqueue.h>
40 #include <linux/if_vlan.h>
41 #include <linux/prefetch.h>
42 #include <linux/debugfs.h>
43 #include <linux/mii.h>
47 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48 #define SKY2_VLAN_TAG_USED 1
53 #define DRV_NAME "sky2"
54 #define DRV_VERSION "1.21"
55 #define PFX DRV_NAME " "
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
63 #define RX_LE_SIZE 1024
64 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
65 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
66 #define RX_DEF_PENDING RX_MAX_PENDING
68 #define TX_RING_SIZE 512
69 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
70 #define TX_MIN_PENDING 64
71 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
73 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
74 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
75 #define TX_WATCHDOG (5 * HZ)
76 #define NAPI_WEIGHT 64
77 #define PHY_RETRIES 1000
79 #define SKY2_EEPROM_MAGIC 0x9955aabb
82 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
84 static const u32 default_msg =
85 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
86 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
87 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
89 static int debug = -1; /* defaults above */
90 module_param(debug, int, 0);
91 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
93 static int copybreak __read_mostly = 128;
94 module_param(copybreak, int, 0);
95 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
97 static int disable_msi = 0;
98 module_param(disable_msi, int, 0);
99 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
101 static const struct pci_device_id sky2_id_table[] = {
102 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
104 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
142 MODULE_DEVICE_TABLE(pci, sky2_id_table);
144 /* Avoid conditionals by using array */
145 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
146 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
147 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
149 static void sky2_set_multicast(struct net_device *dev);
151 /* Access to PHY via serial interconnect */
152 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
156 gma_write16(hw, port, GM_SMI_DATA, val);
157 gma_write16(hw, port, GM_SMI_CTRL,
158 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
160 for (i = 0; i < PHY_RETRIES; i++) {
161 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
165 if (!(ctrl & GM_SMI_CT_BUSY))
171 dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
175 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
179 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
183 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
184 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
186 for (i = 0; i < PHY_RETRIES; i++) {
187 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
191 if (ctrl & GM_SMI_CT_RD_VAL) {
192 *val = gma_read16(hw, port, GM_SMI_DATA);
199 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
202 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
206 static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
209 __gm_phy_read(hw, port, reg, &v);
214 static void sky2_power_on(struct sky2_hw *hw)
216 /* switch power to VCC (WA for VAUX problem) */
217 sky2_write8(hw, B0_POWER_CTRL,
218 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
220 /* disable Core Clock Division, */
221 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
223 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
224 /* enable bits are inverted */
225 sky2_write8(hw, B2_Y2_CLK_GATE,
226 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
227 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
228 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
230 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
232 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
235 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
237 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
238 /* set all bits to 0 except bits 15..12 and 8 */
239 reg &= P_ASPM_CONTROL_MSK;
240 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
242 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
243 /* set all bits to 0 except bits 28 & 27 */
244 reg &= P_CTL_TIM_VMAIN_AV_MSK;
245 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
247 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
249 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
250 reg = sky2_read32(hw, B2_GP_IO);
251 reg |= GLB_GPIO_STAT_RACE_DIS;
252 sky2_write32(hw, B2_GP_IO, reg);
254 sky2_read32(hw, B2_GP_IO);
258 static void sky2_power_aux(struct sky2_hw *hw)
260 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
261 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
263 /* enable bits are inverted */
264 sky2_write8(hw, B2_Y2_CLK_GATE,
265 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
266 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
267 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
269 /* switch power to VAUX */
270 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
271 sky2_write8(hw, B0_POWER_CTRL,
272 (PC_VAUX_ENA | PC_VCC_ENA |
273 PC_VAUX_ON | PC_VCC_OFF));
276 static void sky2_power_state(struct sky2_hw *hw, pci_power_t state)
278 u16 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_CTRL);
279 int pex = pci_find_capability(hw->pdev, PCI_CAP_ID_EXP);
282 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
299 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
300 /* additional power saving measurements */
301 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
303 /* set gating core clock for LTSSM in L1 state */
304 reg |= P_PEX_LTSSM_STAT(P_PEX_LTSSM_L1_STAT) |
305 /* auto clock gated scheme controlled by CLKREQ */
306 P_ASPM_A1_MODE_SELECT |
307 /* enable Gate Root Core Clock */
308 P_CLK_GATE_ROOT_COR_ENA;
310 if (pex && (hw->flags & SKY2_HW_CLK_POWER)) {
311 /* enable Clock Power Management (CLKREQ) */
312 u16 ctrl = sky2_pci_read16(hw, pex + PCI_EXP_DEVCTL);
314 ctrl |= PCI_EXP_DEVCTL_AUX_PME;
315 sky2_pci_write16(hw, pex + PCI_EXP_DEVCTL, ctrl);
317 /* force CLKREQ Enable in Our4 (A1b only) */
318 reg |= P_ASPM_FORCE_CLKREQ_ENA;
320 /* set Mask Register for Release/Gate Clock */
321 sky2_pci_write32(hw, PCI_DEV_REG5,
322 P_REL_PCIE_EXIT_L1_ST | P_GAT_PCIE_ENTER_L1_ST |
323 P_REL_PCIE_RX_EX_IDLE | P_GAT_PCIE_RX_EL_IDLE |
324 P_REL_GPHY_LINK_UP | P_GAT_GPHY_LINK_DOWN);
326 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_CLK_HALT);
328 /* put CPU into reset state */
329 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, HCU_CCSR_ASF_RESET);
330 if (hw->chip_id == CHIP_ID_YUKON_SUPR && hw->chip_rev == CHIP_REV_YU_SU_A0)
331 /* put CPU into halt state */
332 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, HCU_CCSR_ASF_HALTED);
334 if (pex && !(hw->flags & SKY2_HW_RAM_BUFFER)) {
335 reg = sky2_pci_read32(hw, PCI_DEV_REG1);
336 /* force to PCIe L1 */
337 reg |= PCI_FORCE_PEX_L1;
338 sky2_pci_write32(hw, PCI_DEV_REG1, reg);
343 dev_warn(&hw->pdev->dev, PFX "Invalid power state (%d) ",
348 power_control |= PCI_PM_CTRL_PME_ENABLE;
349 /* Finally, set the new power state. */
350 sky2_pci_write32(hw, hw->pm_cap + PCI_PM_CTRL, power_control);
352 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
353 sky2_pci_read32(hw, B0_CTST);
356 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
360 /* disable all GMAC IRQ's */
361 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
363 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
364 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
365 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
366 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
368 reg = gma_read16(hw, port, GM_RX_CTRL);
369 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
370 gma_write16(hw, port, GM_RX_CTRL, reg);
373 /* flow control to advertise bits */
374 static const u16 copper_fc_adv[] = {
376 [FC_TX] = PHY_M_AN_ASP,
377 [FC_RX] = PHY_M_AN_PC,
378 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
381 /* flow control to advertise bits when using 1000BaseX */
382 static const u16 fiber_fc_adv[] = {
383 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
384 [FC_TX] = PHY_M_P_ASYM_MD_X,
385 [FC_RX] = PHY_M_P_SYM_MD_X,
386 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
389 /* flow control to GMA disable bits */
390 static const u16 gm_fc_disable[] = {
391 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
392 [FC_TX] = GM_GPCR_FC_RX_DIS,
393 [FC_RX] = GM_GPCR_FC_TX_DIS,
398 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
400 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
401 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
403 if (sky2->autoneg == AUTONEG_ENABLE &&
404 !(hw->flags & SKY2_HW_NEWER_PHY)) {
405 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
407 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
409 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
411 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
412 if (hw->chip_id == CHIP_ID_YUKON_EC)
413 /* set downshift counter to 3x and enable downshift */
414 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
416 /* set master & slave downshift counter to 1x */
417 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
419 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
422 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
423 if (sky2_is_copper(hw)) {
424 if (!(hw->flags & SKY2_HW_GIGABIT)) {
425 /* enable automatic crossover */
426 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
428 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
429 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
432 /* Enable Class A driver for FE+ A0 */
433 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
434 spec |= PHY_M_FESC_SEL_CL_A;
435 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
438 /* disable energy detect */
439 ctrl &= ~PHY_M_PC_EN_DET_MSK;
441 /* enable automatic crossover */
442 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
444 /* downshift on PHY 88E1112 and 88E1149 is changed */
445 if (sky2->autoneg == AUTONEG_ENABLE
446 && (hw->flags & SKY2_HW_NEWER_PHY)) {
447 /* set downshift counter to 3x and enable downshift */
448 ctrl &= ~PHY_M_PC_DSC_MSK;
449 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
453 /* workaround for deviation #4.88 (CRC errors) */
454 /* disable Automatic Crossover */
456 ctrl &= ~PHY_M_PC_MDIX_MSK;
459 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
461 /* special setup for PHY 88E1112 Fiber */
462 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
463 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
465 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
466 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
467 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
468 ctrl &= ~PHY_M_MAC_MD_MSK;
469 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
470 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
472 if (hw->pmd_type == 'P') {
473 /* select page 1 to access Fiber registers */
474 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
476 /* for SFP-module set SIGDET polarity to low */
477 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
478 ctrl |= PHY_M_FIB_SIGD_POL;
479 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
482 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
490 if (sky2->autoneg == AUTONEG_ENABLE) {
491 if (sky2_is_copper(hw)) {
492 if (sky2->advertising & ADVERTISED_1000baseT_Full)
493 ct1000 |= PHY_M_1000C_AFD;
494 if (sky2->advertising & ADVERTISED_1000baseT_Half)
495 ct1000 |= PHY_M_1000C_AHD;
496 if (sky2->advertising & ADVERTISED_100baseT_Full)
497 adv |= PHY_M_AN_100_FD;
498 if (sky2->advertising & ADVERTISED_100baseT_Half)
499 adv |= PHY_M_AN_100_HD;
500 if (sky2->advertising & ADVERTISED_10baseT_Full)
501 adv |= PHY_M_AN_10_FD;
502 if (sky2->advertising & ADVERTISED_10baseT_Half)
503 adv |= PHY_M_AN_10_HD;
505 adv |= copper_fc_adv[sky2->flow_mode];
506 } else { /* special defines for FIBER (88E1040S only) */
507 if (sky2->advertising & ADVERTISED_1000baseT_Full)
508 adv |= PHY_M_AN_1000X_AFD;
509 if (sky2->advertising & ADVERTISED_1000baseT_Half)
510 adv |= PHY_M_AN_1000X_AHD;
512 adv |= fiber_fc_adv[sky2->flow_mode];
515 /* Restart Auto-negotiation */
516 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
518 /* forced speed/duplex settings */
519 ct1000 = PHY_M_1000C_MSE;
521 /* Disable auto update for duplex flow control and speed */
522 reg |= GM_GPCR_AU_ALL_DIS;
524 switch (sky2->speed) {
526 ctrl |= PHY_CT_SP1000;
527 reg |= GM_GPCR_SPEED_1000;
530 ctrl |= PHY_CT_SP100;
531 reg |= GM_GPCR_SPEED_100;
535 if (sky2->duplex == DUPLEX_FULL) {
536 reg |= GM_GPCR_DUP_FULL;
537 ctrl |= PHY_CT_DUP_MD;
538 } else if (sky2->speed < SPEED_1000)
539 sky2->flow_mode = FC_NONE;
542 reg |= gm_fc_disable[sky2->flow_mode];
544 /* Forward pause packets to GMAC? */
545 if (sky2->flow_mode & FC_RX)
546 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
548 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
551 gma_write16(hw, port, GM_GP_CTRL, reg);
553 if (hw->flags & SKY2_HW_GIGABIT)
554 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
556 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
557 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
559 /* Setup Phy LED's */
560 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
563 switch (hw->chip_id) {
564 case CHIP_ID_YUKON_FE:
565 /* on 88E3082 these bits are at 11..9 (shifted left) */
566 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
568 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
570 /* delete ACT LED control bits */
571 ctrl &= ~PHY_M_FELP_LED1_MSK;
572 /* change ACT LED control to blink mode */
573 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
574 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
577 case CHIP_ID_YUKON_FE_P:
578 /* Enable Link Partner Next Page */
579 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
580 ctrl |= PHY_M_PC_ENA_LIP_NP;
582 /* disable Energy Detect and enable scrambler */
583 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
584 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
586 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
587 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
588 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
589 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
591 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
594 case CHIP_ID_YUKON_XL:
595 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
597 /* select page 3 to access LED control register */
598 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
600 /* set LED Function Control register */
601 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
602 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
603 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
604 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
605 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
607 /* set Polarity Control register */
608 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
609 (PHY_M_POLC_LS1_P_MIX(4) |
610 PHY_M_POLC_IS0_P_MIX(4) |
611 PHY_M_POLC_LOS_CTRL(2) |
612 PHY_M_POLC_INIT_CTRL(2) |
613 PHY_M_POLC_STA1_CTRL(2) |
614 PHY_M_POLC_STA0_CTRL(2)));
616 /* restore page register */
617 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
620 case CHIP_ID_YUKON_EC_U:
621 case CHIP_ID_YUKON_EX:
622 case CHIP_ID_YUKON_SUPR:
623 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
625 /* select page 3 to access LED control register */
626 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
628 /* set LED Function Control register */
629 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
630 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
631 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
632 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
633 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
635 /* set Blink Rate in LED Timer Control Register */
636 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
637 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
638 /* restore page register */
639 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
643 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
644 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
646 /* turn off the Rx LED (LED_RX) */
647 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
650 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
651 /* apply fixes in PHY AFE */
652 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
654 /* increase differential signal amplitude in 10BASE-T */
655 gm_phy_write(hw, port, 0x18, 0xaa99);
656 gm_phy_write(hw, port, 0x17, 0x2011);
658 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
659 gm_phy_write(hw, port, 0x18, 0xa204);
660 gm_phy_write(hw, port, 0x17, 0x2002);
662 /* set page register to 0 */
663 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
664 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
665 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
666 /* apply workaround for integrated resistors calibration */
667 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
668 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
669 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
670 hw->chip_id < CHIP_ID_YUKON_SUPR) {
671 /* no effect on Yukon-XL */
672 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
674 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
675 /* turn on 100 Mbps LED (LED_LINK100) */
676 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
680 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
684 /* Enable phy interrupt on auto-negotiation complete (or link up) */
685 if (sky2->autoneg == AUTONEG_ENABLE)
686 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
688 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
691 static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
692 static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
694 static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
698 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
699 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
700 reg1 &= ~phy_power[port];
702 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
703 reg1 |= coma_mode[port];
705 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
706 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
707 sky2_pci_read32(hw, PCI_DEV_REG1);
710 static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
715 /* release GPHY Control reset */
716 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
718 /* release GMAC reset */
719 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
721 if (hw->flags & SKY2_HW_NEWER_PHY) {
722 /* select page 2 to access MAC control register */
723 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
725 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
726 /* allow GMII Power Down */
727 ctrl &= ~PHY_M_MAC_GMIF_PUP;
728 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
730 /* set page register back to 0 */
731 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
734 /* setup General Purpose Control Register */
735 gma_write16(hw, port, GM_GP_CTRL,
736 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 | GM_GPCR_AU_ALL_DIS);
738 if (hw->chip_id != CHIP_ID_YUKON_EC) {
739 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
740 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
742 /* enable Power Down */
743 ctrl |= PHY_M_PC_POW_D_ENA;
744 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
747 /* set IEEE compatible Power Down Mode (dev. #4.99) */
748 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
751 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
752 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
753 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
754 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
755 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
758 /* Force a renegotiation */
759 static void sky2_phy_reinit(struct sky2_port *sky2)
761 spin_lock_bh(&sky2->phy_lock);
762 sky2_phy_init(sky2->hw, sky2->port);
763 spin_unlock_bh(&sky2->phy_lock);
766 /* Put device in state to listen for Wake On Lan */
767 static void sky2_wol_init(struct sky2_port *sky2)
769 struct sky2_hw *hw = sky2->hw;
770 unsigned port = sky2->port;
771 enum flow_control save_mode;
775 /* Bring hardware out of reset */
776 sky2_write16(hw, B0_CTST, CS_RST_CLR);
777 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
779 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
780 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
783 * sky2_reset will re-enable on resume
785 save_mode = sky2->flow_mode;
786 ctrl = sky2->advertising;
788 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
789 sky2->flow_mode = FC_NONE;
791 spin_lock_bh(&sky2->phy_lock);
792 sky2_phy_power_up(hw, port);
793 sky2_phy_init(hw, port);
794 spin_unlock_bh(&sky2->phy_lock);
796 sky2->flow_mode = save_mode;
797 sky2->advertising = ctrl;
799 /* Set GMAC to no flow control and auto update for speed/duplex */
800 gma_write16(hw, port, GM_GP_CTRL,
801 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
802 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
804 /* Set WOL address */
805 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
806 sky2->netdev->dev_addr, ETH_ALEN);
808 /* Turn on appropriate WOL control bits */
809 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
811 if (sky2->wol & WAKE_PHY)
812 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
814 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
816 if (sky2->wol & WAKE_MAGIC)
817 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
819 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
821 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
822 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
824 /* Turn on legacy PCI-Express PME mode */
825 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
826 reg1 |= PCI_Y2_PME_LEGACY;
827 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
830 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
834 static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
836 struct net_device *dev = hw->dev[port];
838 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
839 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
840 hw->chip_id == CHIP_ID_YUKON_FE_P ||
841 hw->chip_id == CHIP_ID_YUKON_SUPR) {
842 /* Yukon-Extreme B0 and further Extreme devices */
843 /* enable Store & Forward mode for TX */
845 if (dev->mtu <= ETH_DATA_LEN)
846 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
847 TX_JUMBO_DIS | TX_STFW_ENA);
850 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
851 TX_JUMBO_ENA| TX_STFW_ENA);
853 if (dev->mtu <= ETH_DATA_LEN)
854 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
856 /* set Tx GMAC FIFO Almost Empty Threshold */
857 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
858 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
860 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
862 /* Can't do offload because of lack of store/forward */
863 dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM);
868 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
870 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
874 const u8 *addr = hw->dev[port]->dev_addr;
876 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
877 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
879 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
881 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
882 /* WA DEV_472 -- looks like crossed wires on port 2 */
883 /* clear GMAC 1 Control reset */
884 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
886 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
887 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
888 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
889 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
890 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
893 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
895 /* Enable Transmit FIFO Underrun */
896 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
898 spin_lock_bh(&sky2->phy_lock);
899 sky2_phy_power_up(hw, port);
900 sky2_phy_init(hw, port);
901 spin_unlock_bh(&sky2->phy_lock);
904 reg = gma_read16(hw, port, GM_PHY_ADDR);
905 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
907 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
908 gma_read16(hw, port, i);
909 gma_write16(hw, port, GM_PHY_ADDR, reg);
911 /* transmit control */
912 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
914 /* receive control reg: unicast + multicast + no FCS */
915 gma_write16(hw, port, GM_RX_CTRL,
916 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
918 /* transmit flow control */
919 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
921 /* transmit parameter */
922 gma_write16(hw, port, GM_TX_PARAM,
923 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
924 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
925 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
926 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
928 /* serial mode register */
929 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
930 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
932 if (hw->dev[port]->mtu > ETH_DATA_LEN)
933 reg |= GM_SMOD_JUMBO_ENA;
935 gma_write16(hw, port, GM_SERIAL_MODE, reg);
937 /* virtual address for data */
938 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
940 /* physical address: used for pause frames */
941 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
943 /* ignore counter overflows */
944 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
945 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
946 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
948 /* Configure Rx MAC FIFO */
949 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
950 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
951 if (hw->chip_id == CHIP_ID_YUKON_EX ||
952 hw->chip_id == CHIP_ID_YUKON_FE_P)
953 rx_reg |= GMF_RX_OVER_ON;
955 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
957 if (hw->chip_id == CHIP_ID_YUKON_XL) {
958 /* Hardware errata - clear flush mask */
959 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
961 /* Flush Rx MAC FIFO on any flow control or error */
962 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
965 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
966 reg = RX_GMF_FL_THR_DEF + 1;
967 /* Another magic mystery workaround from sk98lin */
968 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
969 hw->chip_rev == CHIP_REV_YU_FE2_A0)
971 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
973 /* Configure Tx MAC FIFO */
974 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
975 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
977 /* On chips without ram buffer, pause is controled by MAC level */
978 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
979 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
980 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
982 sky2_set_tx_stfwd(hw, port);
985 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
986 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
987 /* disable dynamic watermark */
988 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
989 reg &= ~TX_DYN_WM_ENA;
990 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
994 /* Assign Ram Buffer allocation to queue */
995 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
999 /* convert from K bytes to qwords used for hw register */
1002 end = start + space - 1;
1004 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
1005 sky2_write32(hw, RB_ADDR(q, RB_START), start);
1006 sky2_write32(hw, RB_ADDR(q, RB_END), end);
1007 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
1008 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
1010 if (q == Q_R1 || q == Q_R2) {
1011 u32 tp = space - space/4;
1013 /* On receive queue's set the thresholds
1014 * give receiver priority when > 3/4 full
1015 * send pause when down to 2K
1017 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
1018 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
1020 tp = space - 2048/8;
1021 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
1022 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
1024 /* Enable store & forward on Tx queue's because
1025 * Tx FIFO is only 1K on Yukon
1027 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
1030 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
1031 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
1034 /* Setup Bus Memory Interface */
1035 static void sky2_qset(struct sky2_hw *hw, u16 q)
1037 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
1038 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
1039 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
1040 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
1043 /* Setup prefetch unit registers. This is the interface between
1044 * hardware and driver list elements
1046 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
1049 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1050 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
1051 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
1052 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
1053 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
1054 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
1056 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
1059 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
1061 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
1063 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
1068 static void tx_init(struct sky2_port *sky2)
1070 struct sky2_tx_le *le;
1072 sky2->tx_prod = sky2->tx_cons = 0;
1073 sky2->tx_tcpsum = 0;
1074 sky2->tx_last_mss = 0;
1076 le = get_tx_le(sky2);
1078 le->opcode = OP_ADDR64 | HW_OWNER;
1081 static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
1082 struct sky2_tx_le *le)
1084 return sky2->tx_ring + (le - sky2->tx_le);
1087 /* Update chip's next pointer */
1088 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
1090 /* Make sure write' to descriptors are complete before we tell hardware */
1092 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1094 /* Synchronize I/O on since next processor may write to tail */
1099 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1101 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
1102 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
1107 /* Build description to hardware for one receive segment */
1108 static void sky2_rx_add(struct sky2_port *sky2, u8 op,
1109 dma_addr_t map, unsigned len)
1111 struct sky2_rx_le *le;
1113 if (sizeof(dma_addr_t) > sizeof(u32)) {
1114 le = sky2_next_rx(sky2);
1115 le->addr = cpu_to_le32(upper_32_bits(map));
1116 le->opcode = OP_ADDR64 | HW_OWNER;
1119 le = sky2_next_rx(sky2);
1120 le->addr = cpu_to_le32((u32) map);
1121 le->length = cpu_to_le16(len);
1122 le->opcode = op | HW_OWNER;
1125 /* Build description to hardware for one possibly fragmented skb */
1126 static void sky2_rx_submit(struct sky2_port *sky2,
1127 const struct rx_ring_info *re)
1131 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1133 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1134 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1138 static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
1141 struct sk_buff *skb = re->skb;
1144 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
1145 pci_unmap_len_set(re, data_size, size);
1147 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1148 re->frag_addr[i] = pci_map_page(pdev,
1149 skb_shinfo(skb)->frags[i].page,
1150 skb_shinfo(skb)->frags[i].page_offset,
1151 skb_shinfo(skb)->frags[i].size,
1152 PCI_DMA_FROMDEVICE);
1155 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1157 struct sk_buff *skb = re->skb;
1160 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1161 PCI_DMA_FROMDEVICE);
1163 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1164 pci_unmap_page(pdev, re->frag_addr[i],
1165 skb_shinfo(skb)->frags[i].size,
1166 PCI_DMA_FROMDEVICE);
1169 /* Tell chip where to start receive checksum.
1170 * Actually has two checksums, but set both same to avoid possible byte
1173 static void rx_set_checksum(struct sky2_port *sky2)
1175 struct sky2_rx_le *le = sky2_next_rx(sky2);
1177 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1179 le->opcode = OP_TCPSTART | HW_OWNER;
1181 sky2_write32(sky2->hw,
1182 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1183 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
1187 * The RX Stop command will not work for Yukon-2 if the BMU does not
1188 * reach the end of packet and since we can't make sure that we have
1189 * incoming data, we must reset the BMU while it is not doing a DMA
1190 * transfer. Since it is possible that the RX path is still active,
1191 * the RX RAM buffer will be stopped first, so any possible incoming
1192 * data will not trigger a DMA. After the RAM buffer is stopped, the
1193 * BMU is polled until any DMA in progress is ended and only then it
1196 static void sky2_rx_stop(struct sky2_port *sky2)
1198 struct sky2_hw *hw = sky2->hw;
1199 unsigned rxq = rxqaddr[sky2->port];
1202 /* disable the RAM Buffer receive queue */
1203 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1205 for (i = 0; i < 0xffff; i++)
1206 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1207 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1210 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1211 sky2->netdev->name);
1213 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1215 /* reset the Rx prefetch unit */
1216 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1220 /* Clean out receive buffer area, assumes receiver hardware stopped */
1221 static void sky2_rx_clean(struct sky2_port *sky2)
1225 memset(sky2->rx_le, 0, RX_LE_BYTES);
1226 for (i = 0; i < sky2->rx_pending; i++) {
1227 struct rx_ring_info *re = sky2->rx_ring + i;
1230 sky2_rx_unmap_skb(sky2->hw->pdev, re);
1237 /* Basic MII support */
1238 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1240 struct mii_ioctl_data *data = if_mii(ifr);
1241 struct sky2_port *sky2 = netdev_priv(dev);
1242 struct sky2_hw *hw = sky2->hw;
1243 int err = -EOPNOTSUPP;
1245 if (!netif_running(dev))
1246 return -ENODEV; /* Phy still in reset */
1250 data->phy_id = PHY_ADDR_MARV;
1256 spin_lock_bh(&sky2->phy_lock);
1257 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
1258 spin_unlock_bh(&sky2->phy_lock);
1260 data->val_out = val;
1265 if (!capable(CAP_NET_ADMIN))
1268 spin_lock_bh(&sky2->phy_lock);
1269 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1271 spin_unlock_bh(&sky2->phy_lock);
1277 #ifdef SKY2_VLAN_TAG_USED
1278 static void sky2_set_vlan_mode(struct sky2_hw *hw, u16 port, bool onoff)
1281 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1283 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1286 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1288 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1293 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1295 struct sky2_port *sky2 = netdev_priv(dev);
1296 struct sky2_hw *hw = sky2->hw;
1297 u16 port = sky2->port;
1299 netif_tx_lock_bh(dev);
1300 napi_disable(&hw->napi);
1303 sky2_set_vlan_mode(hw, port, grp != NULL);
1305 sky2_read32(hw, B0_Y2_SP_LISR);
1306 napi_enable(&hw->napi);
1307 netif_tx_unlock_bh(dev);
1312 * Allocate an skb for receiving. If the MTU is large enough
1313 * make the skb non-linear with a fragment list of pages.
1315 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
1317 struct sk_buff *skb;
1320 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
1321 unsigned char *start;
1323 * Workaround for a bug in FIFO that cause hang
1324 * if the FIFO if the receive buffer is not 64 byte aligned.
1325 * The buffer returned from netdev_alloc_skb is
1326 * aligned except if slab debugging is enabled.
1328 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + 8);
1331 start = PTR_ALIGN(skb->data, 8);
1332 skb_reserve(skb, start - skb->data);
1334 skb = netdev_alloc_skb(sky2->netdev,
1335 sky2->rx_data_size + NET_IP_ALIGN);
1338 skb_reserve(skb, NET_IP_ALIGN);
1341 for (i = 0; i < sky2->rx_nfrags; i++) {
1342 struct page *page = alloc_page(GFP_ATOMIC);
1346 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
1356 static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1358 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1362 * Allocate and setup receiver buffer pool.
1363 * Normal case this ends up creating one list element for skb
1364 * in the receive ring. Worst case if using large MTU and each
1365 * allocation falls on a different 64 bit region, that results
1366 * in 6 list elements per ring entry.
1367 * One element is used for checksum enable/disable, and one
1368 * extra to avoid wrap.
1370 static int sky2_rx_start(struct sky2_port *sky2)
1372 struct sky2_hw *hw = sky2->hw;
1373 struct rx_ring_info *re;
1374 unsigned rxq = rxqaddr[sky2->port];
1375 unsigned i, size, thresh;
1377 sky2->rx_put = sky2->rx_next = 0;
1380 /* On PCI express lowering the watermark gives better performance */
1381 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1382 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1384 /* These chips have no ram buffer?
1385 * MAC Rx RAM Read is controlled by hardware */
1386 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1387 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1388 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
1389 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
1391 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1393 if (!(hw->flags & SKY2_HW_NEW_LE))
1394 rx_set_checksum(sky2);
1396 /* Space needed for frame data + headers rounded up */
1397 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1399 /* Stopping point for hardware truncation */
1400 thresh = (size - 8) / sizeof(u32);
1402 sky2->rx_nfrags = size >> PAGE_SHIFT;
1403 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1405 /* Compute residue after pages */
1406 size -= sky2->rx_nfrags << PAGE_SHIFT;
1408 /* Optimize to handle small packets and headers */
1409 if (size < copybreak)
1411 if (size < ETH_HLEN)
1414 sky2->rx_data_size = size;
1417 for (i = 0; i < sky2->rx_pending; i++) {
1418 re = sky2->rx_ring + i;
1420 re->skb = sky2_rx_alloc(sky2);
1424 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1425 sky2_rx_submit(sky2, re);
1429 * The receiver hangs if it receives frames larger than the
1430 * packet buffer. As a workaround, truncate oversize frames, but
1431 * the register is limited to 9 bits, so if you do frames > 2052
1432 * you better get the MTU right!
1435 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1437 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1438 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1441 /* Tell chip about available buffers */
1442 sky2_rx_update(sky2, rxq);
1445 sky2_rx_clean(sky2);
1449 /* Bring up network interface. */
1450 static int sky2_up(struct net_device *dev)
1452 struct sky2_port *sky2 = netdev_priv(dev);
1453 struct sky2_hw *hw = sky2->hw;
1454 unsigned port = sky2->port;
1456 int cap, err = -ENOMEM;
1457 struct net_device *otherdev = hw->dev[sky2->port^1];
1460 * On dual port PCI-X card, there is an problem where status
1461 * can be received out of order due to split transactions
1463 if (otherdev && netif_running(otherdev) &&
1464 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1467 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1468 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1469 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1473 if (netif_msg_ifup(sky2))
1474 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1476 netif_carrier_off(dev);
1478 /* must be power of 2 */
1479 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1481 sizeof(struct sky2_tx_le),
1486 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
1493 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1497 memset(sky2->rx_le, 0, RX_LE_BYTES);
1499 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1504 sky2_mac_init(hw, port);
1506 /* Register is number of 4K blocks on internal RAM buffer. */
1507 ramsize = sky2_read8(hw, B2_E_0) * 4;
1511 hw->flags |= SKY2_HW_RAM_BUFFER;
1512 pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
1514 rxspace = ramsize / 2;
1516 rxspace = 8 + (2*(ramsize - 16))/3;
1518 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1519 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1521 /* Make sure SyncQ is disabled */
1522 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1526 sky2_qset(hw, txqaddr[port]);
1528 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1529 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1530 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1532 /* Set almost empty threshold */
1533 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1534 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1535 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
1537 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1540 #ifdef SKY2_VLAN_TAG_USED
1541 sky2_set_vlan_mode(hw, port, sky2->vlgrp != NULL);
1544 err = sky2_rx_start(sky2);
1548 /* Enable interrupts from phy/mac for port */
1549 imask = sky2_read32(hw, B0_IMSK);
1550 imask |= portirq_msk[port];
1551 sky2_write32(hw, B0_IMSK, imask);
1553 sky2_set_multicast(dev);
1558 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1559 sky2->rx_le, sky2->rx_le_map);
1563 pci_free_consistent(hw->pdev,
1564 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1565 sky2->tx_le, sky2->tx_le_map);
1568 kfree(sky2->tx_ring);
1569 kfree(sky2->rx_ring);
1571 sky2->tx_ring = NULL;
1572 sky2->rx_ring = NULL;
1576 /* Modular subtraction in ring */
1577 static inline int tx_dist(unsigned tail, unsigned head)
1579 return (head - tail) & (TX_RING_SIZE - 1);
1582 /* Number of list elements available for next tx */
1583 static inline int tx_avail(const struct sky2_port *sky2)
1585 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
1588 /* Estimate of number of transmit list elements required */
1589 static unsigned tx_le_req(const struct sk_buff *skb)
1593 count = sizeof(dma_addr_t) / sizeof(u32);
1594 count += skb_shinfo(skb)->nr_frags * count;
1596 if (skb_is_gso(skb))
1599 if (skb->ip_summed == CHECKSUM_PARTIAL)
1606 * Put one packet in ring for transmit.
1607 * A single packet can generate multiple list elements, and
1608 * the number of ring elements will probably be less than the number
1609 * of list elements used.
1611 static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1613 struct sky2_port *sky2 = netdev_priv(dev);
1614 struct sky2_hw *hw = sky2->hw;
1615 struct sky2_tx_le *le = NULL;
1616 struct tx_ring_info *re;
1622 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1623 return NETDEV_TX_BUSY;
1625 if (unlikely(netif_msg_tx_queued(sky2)))
1626 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1627 dev->name, sky2->tx_prod, skb->len);
1629 len = skb_headlen(skb);
1630 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1632 /* Send high bits if needed */
1633 if (sizeof(dma_addr_t) > sizeof(u32)) {
1634 le = get_tx_le(sky2);
1635 le->addr = cpu_to_le32(upper_32_bits(mapping));
1636 le->opcode = OP_ADDR64 | HW_OWNER;
1639 /* Check for TCP Segmentation Offload */
1640 mss = skb_shinfo(skb)->gso_size;
1643 if (!(hw->flags & SKY2_HW_NEW_LE))
1644 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1646 if (mss != sky2->tx_last_mss) {
1647 le = get_tx_le(sky2);
1648 le->addr = cpu_to_le32(mss);
1650 if (hw->flags & SKY2_HW_NEW_LE)
1651 le->opcode = OP_MSS | HW_OWNER;
1653 le->opcode = OP_LRGLEN | HW_OWNER;
1654 sky2->tx_last_mss = mss;
1659 #ifdef SKY2_VLAN_TAG_USED
1660 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1661 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1663 le = get_tx_le(sky2);
1665 le->opcode = OP_VLAN|HW_OWNER;
1667 le->opcode |= OP_VLAN;
1668 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1673 /* Handle TCP checksum offload */
1674 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1675 /* On Yukon EX (some versions) encoding change. */
1676 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
1677 ctrl |= CALSUM; /* auto checksum */
1679 const unsigned offset = skb_transport_offset(skb);
1682 tcpsum = offset << 16; /* sum start */
1683 tcpsum |= offset + skb->csum_offset; /* sum write */
1685 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1686 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1689 if (tcpsum != sky2->tx_tcpsum) {
1690 sky2->tx_tcpsum = tcpsum;
1692 le = get_tx_le(sky2);
1693 le->addr = cpu_to_le32(tcpsum);
1694 le->length = 0; /* initial checksum value */
1695 le->ctrl = 1; /* one packet */
1696 le->opcode = OP_TCPLISW | HW_OWNER;
1701 le = get_tx_le(sky2);
1702 le->addr = cpu_to_le32((u32) mapping);
1703 le->length = cpu_to_le16(len);
1705 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1707 re = tx_le_re(sky2, le);
1709 pci_unmap_addr_set(re, mapaddr, mapping);
1710 pci_unmap_len_set(re, maplen, len);
1712 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1713 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1715 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1716 frag->size, PCI_DMA_TODEVICE);
1718 if (sizeof(dma_addr_t) > sizeof(u32)) {
1719 le = get_tx_le(sky2);
1720 le->addr = cpu_to_le32(upper_32_bits(mapping));
1722 le->opcode = OP_ADDR64 | HW_OWNER;
1725 le = get_tx_le(sky2);
1726 le->addr = cpu_to_le32((u32) mapping);
1727 le->length = cpu_to_le16(frag->size);
1729 le->opcode = OP_BUFFER | HW_OWNER;
1731 re = tx_le_re(sky2, le);
1733 pci_unmap_addr_set(re, mapaddr, mapping);
1734 pci_unmap_len_set(re, maplen, frag->size);
1739 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1740 netif_stop_queue(dev);
1742 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1744 dev->trans_start = jiffies;
1745 return NETDEV_TX_OK;
1749 * Free ring elements from starting at tx_cons until "done"
1751 * NB: the hardware will tell us about partial completion of multi-part
1752 * buffers so make sure not to free skb to early.
1754 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1756 struct net_device *dev = sky2->netdev;
1757 struct pci_dev *pdev = sky2->hw->pdev;
1760 BUG_ON(done >= TX_RING_SIZE);
1762 for (idx = sky2->tx_cons; idx != done;
1763 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1764 struct sky2_tx_le *le = sky2->tx_le + idx;
1765 struct tx_ring_info *re = sky2->tx_ring + idx;
1767 switch(le->opcode & ~HW_OWNER) {
1770 pci_unmap_single(pdev,
1771 pci_unmap_addr(re, mapaddr),
1772 pci_unmap_len(re, maplen),
1776 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1777 pci_unmap_len(re, maplen),
1782 if (le->ctrl & EOP) {
1783 if (unlikely(netif_msg_tx_done(sky2)))
1784 printk(KERN_DEBUG "%s: tx done %u\n",
1787 dev->stats.tx_packets++;
1788 dev->stats.tx_bytes += re->skb->len;
1790 dev_kfree_skb_any(re->skb);
1791 sky2->tx_next = RING_NEXT(idx, TX_RING_SIZE);
1795 sky2->tx_cons = idx;
1798 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
1799 netif_wake_queue(dev);
1802 /* Cleanup all untransmitted buffers, assume transmitter not running */
1803 static void sky2_tx_clean(struct net_device *dev)
1805 struct sky2_port *sky2 = netdev_priv(dev);
1807 netif_tx_lock_bh(dev);
1808 sky2_tx_complete(sky2, sky2->tx_prod);
1809 netif_tx_unlock_bh(dev);
1812 /* Network shutdown */
1813 static int sky2_down(struct net_device *dev)
1815 struct sky2_port *sky2 = netdev_priv(dev);
1816 struct sky2_hw *hw = sky2->hw;
1817 unsigned port = sky2->port;
1821 /* Never really got started! */
1825 if (netif_msg_ifdown(sky2))
1826 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1828 /* Stop more packets from being queued */
1829 netif_stop_queue(dev);
1831 /* Disable port IRQ */
1832 imask = sky2_read32(hw, B0_IMSK);
1833 imask &= ~portirq_msk[port];
1834 sky2_write32(hw, B0_IMSK, imask);
1836 synchronize_irq(hw->pdev->irq);
1838 sky2_gmac_reset(hw, port);
1840 /* Stop transmitter */
1841 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1842 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1844 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1845 RB_RST_SET | RB_DIS_OP_MD);
1847 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1848 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1849 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1851 /* Make sure no packets are pending */
1852 napi_synchronize(&hw->napi);
1854 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1856 /* Workaround shared GMAC reset */
1857 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1858 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1859 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1861 /* Disable Force Sync bit and Enable Alloc bit */
1862 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1863 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1865 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1866 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1867 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1869 /* Reset the PCI FIFO of the async Tx queue */
1870 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1871 BMU_RST_SET | BMU_FIFO_RST);
1873 /* Reset the Tx prefetch units */
1874 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1877 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1881 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1882 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1884 sky2_phy_power_down(hw, port);
1886 netif_carrier_off(dev);
1888 /* turn off LED's */
1889 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1892 sky2_rx_clean(sky2);
1894 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1895 sky2->rx_le, sky2->rx_le_map);
1896 kfree(sky2->rx_ring);
1898 pci_free_consistent(hw->pdev,
1899 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1900 sky2->tx_le, sky2->tx_le_map);
1901 kfree(sky2->tx_ring);
1906 sky2->rx_ring = NULL;
1907 sky2->tx_ring = NULL;
1912 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1914 if (hw->flags & SKY2_HW_FIBRE_PHY)
1917 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1918 if (aux & PHY_M_PS_SPEED_100)
1924 switch (aux & PHY_M_PS_SPEED_MSK) {
1925 case PHY_M_PS_SPEED_1000:
1927 case PHY_M_PS_SPEED_100:
1934 static void sky2_link_up(struct sky2_port *sky2)
1936 struct sky2_hw *hw = sky2->hw;
1937 unsigned port = sky2->port;
1939 static const char *fc_name[] = {
1947 reg = gma_read16(hw, port, GM_GP_CTRL);
1948 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1949 gma_write16(hw, port, GM_GP_CTRL, reg);
1951 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1953 netif_carrier_on(sky2->netdev);
1955 mod_timer(&hw->watchdog_timer, jiffies + 1);
1957 /* Turn on link LED */
1958 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1959 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1961 if (netif_msg_link(sky2))
1962 printk(KERN_INFO PFX
1963 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1964 sky2->netdev->name, sky2->speed,
1965 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1966 fc_name[sky2->flow_status]);
1969 static void sky2_link_down(struct sky2_port *sky2)
1971 struct sky2_hw *hw = sky2->hw;
1972 unsigned port = sky2->port;
1975 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1977 reg = gma_read16(hw, port, GM_GP_CTRL);
1978 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1979 gma_write16(hw, port, GM_GP_CTRL, reg);
1981 netif_carrier_off(sky2->netdev);
1983 /* Turn on link LED */
1984 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1986 if (netif_msg_link(sky2))
1987 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1989 sky2_phy_init(hw, port);
1992 static enum flow_control sky2_flow(int rx, int tx)
1995 return tx ? FC_BOTH : FC_RX;
1997 return tx ? FC_TX : FC_NONE;
2000 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
2002 struct sky2_hw *hw = sky2->hw;
2003 unsigned port = sky2->port;
2006 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2007 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
2008 if (lpa & PHY_M_AN_RF) {
2009 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
2013 if (!(aux & PHY_M_PS_SPDUP_RES)) {
2014 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
2015 sky2->netdev->name);
2019 sky2->speed = sky2_phy_speed(hw, aux);
2020 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2022 /* Since the pause result bits seem to in different positions on
2023 * different chips. look at registers.
2025 if (hw->flags & SKY2_HW_FIBRE_PHY) {
2026 /* Shift for bits in fiber PHY */
2027 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
2028 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
2030 if (advert & ADVERTISE_1000XPAUSE)
2031 advert |= ADVERTISE_PAUSE_CAP;
2032 if (advert & ADVERTISE_1000XPSE_ASYM)
2033 advert |= ADVERTISE_PAUSE_ASYM;
2034 if (lpa & LPA_1000XPAUSE)
2035 lpa |= LPA_PAUSE_CAP;
2036 if (lpa & LPA_1000XPAUSE_ASYM)
2037 lpa |= LPA_PAUSE_ASYM;
2040 sky2->flow_status = FC_NONE;
2041 if (advert & ADVERTISE_PAUSE_CAP) {
2042 if (lpa & LPA_PAUSE_CAP)
2043 sky2->flow_status = FC_BOTH;
2044 else if (advert & ADVERTISE_PAUSE_ASYM)
2045 sky2->flow_status = FC_RX;
2046 } else if (advert & ADVERTISE_PAUSE_ASYM) {
2047 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
2048 sky2->flow_status = FC_TX;
2051 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
2052 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
2053 sky2->flow_status = FC_NONE;
2055 if (sky2->flow_status & FC_TX)
2056 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2058 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2063 /* Interrupt from PHY */
2064 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
2066 struct net_device *dev = hw->dev[port];
2067 struct sky2_port *sky2 = netdev_priv(dev);
2068 u16 istatus, phystat;
2070 if (!netif_running(dev))
2073 spin_lock(&sky2->phy_lock);
2074 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2075 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2077 if (netif_msg_intr(sky2))
2078 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
2079 sky2->netdev->name, istatus, phystat);
2081 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
2082 if (sky2_autoneg_done(sky2, phystat) == 0)
2087 if (istatus & PHY_M_IS_LSP_CHANGE)
2088 sky2->speed = sky2_phy_speed(hw, phystat);
2090 if (istatus & PHY_M_IS_DUP_CHANGE)
2092 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2094 if (istatus & PHY_M_IS_LST_CHANGE) {
2095 if (phystat & PHY_M_PS_LINK_UP)
2098 sky2_link_down(sky2);
2101 spin_unlock(&sky2->phy_lock);
2104 /* Transmit timeout is only called if we are running, carrier is up
2105 * and tx queue is full (stopped).
2107 static void sky2_tx_timeout(struct net_device *dev)
2109 struct sky2_port *sky2 = netdev_priv(dev);
2110 struct sky2_hw *hw = sky2->hw;
2112 if (netif_msg_timer(sky2))
2113 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
2115 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
2116 dev->name, sky2->tx_cons, sky2->tx_prod,
2117 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2118 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
2120 /* can't restart safely under softirq */
2121 schedule_work(&hw->restart_work);
2124 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2126 struct sky2_port *sky2 = netdev_priv(dev);
2127 struct sky2_hw *hw = sky2->hw;
2128 unsigned port = sky2->port;
2133 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2136 if (new_mtu > ETH_DATA_LEN &&
2137 (hw->chip_id == CHIP_ID_YUKON_FE ||
2138 hw->chip_id == CHIP_ID_YUKON_FE_P))
2141 if (!netif_running(dev)) {
2146 imask = sky2_read32(hw, B0_IMSK);
2147 sky2_write32(hw, B0_IMSK, 0);
2149 dev->trans_start = jiffies; /* prevent tx timeout */
2150 netif_stop_queue(dev);
2151 napi_disable(&hw->napi);
2153 synchronize_irq(hw->pdev->irq);
2155 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
2156 sky2_set_tx_stfwd(hw, port);
2158 ctl = gma_read16(hw, port, GM_GP_CTRL);
2159 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
2161 sky2_rx_clean(sky2);
2165 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2166 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2168 if (dev->mtu > ETH_DATA_LEN)
2169 mode |= GM_SMOD_JUMBO_ENA;
2171 gma_write16(hw, port, GM_SERIAL_MODE, mode);
2173 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
2175 err = sky2_rx_start(sky2);
2176 sky2_write32(hw, B0_IMSK, imask);
2178 sky2_read32(hw, B0_Y2_SP_LISR);
2179 napi_enable(&hw->napi);
2184 gma_write16(hw, port, GM_GP_CTRL, ctl);
2186 netif_wake_queue(dev);
2192 /* For small just reuse existing skb for next receive */
2193 static struct sk_buff *receive_copy(struct sky2_port *sky2,
2194 const struct rx_ring_info *re,
2197 struct sk_buff *skb;
2199 skb = netdev_alloc_skb(sky2->netdev, length + 2);
2201 skb_reserve(skb, 2);
2202 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2203 length, PCI_DMA_FROMDEVICE);
2204 skb_copy_from_linear_data(re->skb, skb->data, length);
2205 skb->ip_summed = re->skb->ip_summed;
2206 skb->csum = re->skb->csum;
2207 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2208 length, PCI_DMA_FROMDEVICE);
2209 re->skb->ip_summed = CHECKSUM_NONE;
2210 skb_put(skb, length);
2215 /* Adjust length of skb with fragments to match received data */
2216 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2217 unsigned int length)
2222 /* put header into skb */
2223 size = min(length, hdr_space);
2228 num_frags = skb_shinfo(skb)->nr_frags;
2229 for (i = 0; i < num_frags; i++) {
2230 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2233 /* don't need this page */
2234 __free_page(frag->page);
2235 --skb_shinfo(skb)->nr_frags;
2237 size = min(length, (unsigned) PAGE_SIZE);
2240 skb->data_len += size;
2241 skb->truesize += size;
2248 /* Normal packet - take skb from ring element and put in a new one */
2249 static struct sk_buff *receive_new(struct sky2_port *sky2,
2250 struct rx_ring_info *re,
2251 unsigned int length)
2253 struct sk_buff *skb, *nskb;
2254 unsigned hdr_space = sky2->rx_data_size;
2256 /* Don't be tricky about reusing pages (yet) */
2257 nskb = sky2_rx_alloc(sky2);
2258 if (unlikely(!nskb))
2262 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2264 prefetch(skb->data);
2266 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
2268 if (skb_shinfo(skb)->nr_frags)
2269 skb_put_frags(skb, hdr_space, length);
2271 skb_put(skb, length);
2276 * Receive one packet.
2277 * For larger packets, get new buffer.
2279 static struct sk_buff *sky2_receive(struct net_device *dev,
2280 u16 length, u32 status)
2282 struct sky2_port *sky2 = netdev_priv(dev);
2283 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
2284 struct sk_buff *skb = NULL;
2285 u16 count = (status & GMR_FS_LEN) >> 16;
2287 #ifdef SKY2_VLAN_TAG_USED
2288 /* Account for vlan tag */
2289 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2293 if (unlikely(netif_msg_rx_status(sky2)))
2294 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
2295 dev->name, sky2->rx_next, status, length);
2297 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
2298 prefetch(sky2->rx_ring + sky2->rx_next);
2300 /* This chip has hardware problems that generates bogus status.
2301 * So do only marginal checking and expect higher level protocols
2302 * to handle crap frames.
2304 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2305 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2309 if (status & GMR_FS_ANY_ERR)
2312 if (!(status & GMR_FS_RX_OK))
2315 /* if length reported by DMA does not match PHY, packet was truncated */
2316 if (length != count)
2320 if (length < copybreak)
2321 skb = receive_copy(sky2, re, length);
2323 skb = receive_new(sky2, re, length);
2325 sky2_rx_submit(sky2, re);
2330 /* Truncation of overlength packets
2331 causes PHY length to not match MAC length */
2332 ++dev->stats.rx_length_errors;
2333 if (netif_msg_rx_err(sky2) && net_ratelimit())
2334 pr_info(PFX "%s: rx length error: status %#x length %d\n",
2335 dev->name, status, length);
2339 ++dev->stats.rx_errors;
2340 if (status & GMR_FS_RX_FF_OV) {
2341 dev->stats.rx_over_errors++;
2345 if (netif_msg_rx_err(sky2) && net_ratelimit())
2346 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
2347 dev->name, status, length);
2349 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
2350 dev->stats.rx_length_errors++;
2351 if (status & GMR_FS_FRAGMENT)
2352 dev->stats.rx_frame_errors++;
2353 if (status & GMR_FS_CRC_ERR)
2354 dev->stats.rx_crc_errors++;
2359 /* Transmit complete */
2360 static inline void sky2_tx_done(struct net_device *dev, u16 last)
2362 struct sky2_port *sky2 = netdev_priv(dev);
2364 if (netif_running(dev)) {
2366 sky2_tx_complete(sky2, last);
2367 netif_tx_unlock(dev);
2371 /* Process status response ring */
2372 static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
2375 unsigned rx[2] = { 0, 0 };
2379 struct sky2_port *sky2;
2380 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2382 struct net_device *dev;
2383 struct sk_buff *skb;
2386 u8 opcode = le->opcode;
2388 if (!(opcode & HW_OWNER))
2391 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
2393 port = le->css & CSS_LINK_BIT;
2394 dev = hw->dev[port];
2395 sky2 = netdev_priv(dev);
2396 length = le16_to_cpu(le->length);
2397 status = le32_to_cpu(le->status);
2400 switch (opcode & ~HW_OWNER) {
2403 skb = sky2_receive(dev, length, status);
2404 if (unlikely(!skb)) {
2405 dev->stats.rx_dropped++;
2409 /* This chip reports checksum status differently */
2410 if (hw->flags & SKY2_HW_NEW_LE) {
2411 if (sky2->rx_csum &&
2412 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2413 (le->css & CSS_TCPUDPCSOK))
2414 skb->ip_summed = CHECKSUM_UNNECESSARY;
2416 skb->ip_summed = CHECKSUM_NONE;
2419 skb->protocol = eth_type_trans(skb, dev);
2420 dev->stats.rx_packets++;
2421 dev->stats.rx_bytes += skb->len;
2422 dev->last_rx = jiffies;
2424 #ifdef SKY2_VLAN_TAG_USED
2425 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2426 vlan_hwaccel_receive_skb(skb,
2428 be16_to_cpu(sky2->rx_tag));
2431 netif_receive_skb(skb);
2433 /* Stop after net poll weight */
2434 if (++work_done >= to_do)
2438 #ifdef SKY2_VLAN_TAG_USED
2440 sky2->rx_tag = length;
2444 sky2->rx_tag = length;
2451 /* If this happens then driver assuming wrong format */
2452 if (unlikely(hw->flags & SKY2_HW_NEW_LE)) {
2453 if (net_ratelimit())
2454 printk(KERN_NOTICE "%s: unexpected"
2455 " checksum status\n",
2460 /* Both checksum counters are programmed to start at
2461 * the same offset, so unless there is a problem they
2462 * should match. This failure is an early indication that
2463 * hardware receive checksumming won't work.
2465 if (likely(status >> 16 == (status & 0xffff))) {
2466 skb = sky2->rx_ring[sky2->rx_next].skb;
2467 skb->ip_summed = CHECKSUM_COMPLETE;
2468 skb->csum = status & 0xffff;
2470 printk(KERN_NOTICE PFX "%s: hardware receive "
2471 "checksum problem (status = %#x)\n",
2474 sky2_write32(sky2->hw,
2475 Q_ADDR(rxqaddr[port], Q_CSR),
2481 /* TX index reports status for both ports */
2482 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2483 sky2_tx_done(hw->dev[0], status & 0xfff);
2485 sky2_tx_done(hw->dev[1],
2486 ((status >> 24) & 0xff)
2487 | (u16)(length & 0xf) << 8);
2491 if (net_ratelimit())
2492 printk(KERN_WARNING PFX
2493 "unknown status opcode 0x%x\n", opcode);
2495 } while (hw->st_idx != idx);
2497 /* Fully processed status ring so clear irq */
2498 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2502 sky2_rx_update(netdev_priv(hw->dev[0]), Q_R1);
2505 sky2_rx_update(netdev_priv(hw->dev[1]), Q_R2);
2510 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2512 struct net_device *dev = hw->dev[port];
2514 if (net_ratelimit())
2515 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2518 if (status & Y2_IS_PAR_RD1) {
2519 if (net_ratelimit())
2520 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2523 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2526 if (status & Y2_IS_PAR_WR1) {
2527 if (net_ratelimit())
2528 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2531 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2534 if (status & Y2_IS_PAR_MAC1) {
2535 if (net_ratelimit())
2536 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
2537 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2540 if (status & Y2_IS_PAR_RX1) {
2541 if (net_ratelimit())
2542 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
2543 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2546 if (status & Y2_IS_TCP_TXA1) {
2547 if (net_ratelimit())
2548 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2550 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2554 static void sky2_hw_intr(struct sky2_hw *hw)
2556 struct pci_dev *pdev = hw->pdev;
2557 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2558 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2562 if (status & Y2_IS_TIST_OV)
2563 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2565 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2568 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2569 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2570 if (net_ratelimit())
2571 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
2574 sky2_pci_write16(hw, PCI_STATUS,
2575 pci_err | PCI_STATUS_ERROR_BITS);
2576 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2579 if (status & Y2_IS_PCI_EXP) {
2580 /* PCI-Express uncorrectable Error occurred */
2583 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2584 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2585 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2587 if (net_ratelimit())
2588 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
2590 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2591 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2594 if (status & Y2_HWE_L1_MASK)
2595 sky2_hw_error(hw, 0, status);
2597 if (status & Y2_HWE_L1_MASK)
2598 sky2_hw_error(hw, 1, status);
2601 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2603 struct net_device *dev = hw->dev[port];
2604 struct sky2_port *sky2 = netdev_priv(dev);
2605 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2607 if (netif_msg_intr(sky2))
2608 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2611 if (status & GM_IS_RX_CO_OV)
2612 gma_read16(hw, port, GM_RX_IRQ_SRC);
2614 if (status & GM_IS_TX_CO_OV)
2615 gma_read16(hw, port, GM_TX_IRQ_SRC);
2617 if (status & GM_IS_RX_FF_OR) {
2618 ++dev->stats.rx_fifo_errors;
2619 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2622 if (status & GM_IS_TX_FF_UR) {
2623 ++dev->stats.tx_fifo_errors;
2624 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2628 /* This should never happen it is a bug. */
2629 static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2630 u16 q, unsigned ring_size)
2632 struct net_device *dev = hw->dev[port];
2633 struct sky2_port *sky2 = netdev_priv(dev);
2635 const u64 *le = (q == Q_R1 || q == Q_R2)
2636 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
2638 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2639 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2640 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2641 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
2643 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
2646 static int sky2_rx_hung(struct net_device *dev)
2648 struct sky2_port *sky2 = netdev_priv(dev);
2649 struct sky2_hw *hw = sky2->hw;
2650 unsigned port = sky2->port;
2651 unsigned rxq = rxqaddr[port];
2652 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2653 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2654 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2655 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2657 /* If idle and MAC or PCI is stuck */
2658 if (sky2->check.last == dev->last_rx &&
2659 ((mac_rp == sky2->check.mac_rp &&
2660 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2661 /* Check if the PCI RX hang */
2662 (fifo_rp == sky2->check.fifo_rp &&
2663 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2664 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2665 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2666 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2669 sky2->check.last = dev->last_rx;
2670 sky2->check.mac_rp = mac_rp;
2671 sky2->check.mac_lev = mac_lev;
2672 sky2->check.fifo_rp = fifo_rp;
2673 sky2->check.fifo_lev = fifo_lev;
2678 static void sky2_watchdog(unsigned long arg)
2680 struct sky2_hw *hw = (struct sky2_hw *) arg;
2682 /* Check for lost IRQ once a second */
2683 if (sky2_read32(hw, B0_ISRC)) {
2684 napi_schedule(&hw->napi);
2688 for (i = 0; i < hw->ports; i++) {
2689 struct net_device *dev = hw->dev[i];
2690 if (!netif_running(dev))
2694 /* For chips with Rx FIFO, check if stuck */
2695 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
2696 sky2_rx_hung(dev)) {
2697 pr_info(PFX "%s: receiver hang detected\n",
2699 schedule_work(&hw->restart_work);
2708 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
2711 /* Hardware/software error handling */
2712 static void sky2_err_intr(struct sky2_hw *hw, u32 status)
2714 if (net_ratelimit())
2715 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
2717 if (status & Y2_IS_HW_ERR)
2720 if (status & Y2_IS_IRQ_MAC1)
2721 sky2_mac_intr(hw, 0);
2723 if (status & Y2_IS_IRQ_MAC2)
2724 sky2_mac_intr(hw, 1);
2726 if (status & Y2_IS_CHK_RX1)
2727 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
2729 if (status & Y2_IS_CHK_RX2)
2730 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
2732 if (status & Y2_IS_CHK_TXA1)
2733 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
2735 if (status & Y2_IS_CHK_TXA2)
2736 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2739 static int sky2_poll(struct napi_struct *napi, int work_limit)
2741 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
2742 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2746 if (unlikely(status & Y2_IS_ERROR))
2747 sky2_err_intr(hw, status);
2749 if (status & Y2_IS_IRQ_PHY1)
2750 sky2_phy_intr(hw, 0);
2752 if (status & Y2_IS_IRQ_PHY2)
2753 sky2_phy_intr(hw, 1);
2755 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2756 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
2758 if (work_done >= work_limit)
2762 /* Bug/Errata workaround?
2763 * Need to kick the TX irq moderation timer.
2765 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_START) {
2766 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2767 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2769 napi_complete(napi);
2770 sky2_read32(hw, B0_Y2_SP_LISR);
2776 static irqreturn_t sky2_intr(int irq, void *dev_id)
2778 struct sky2_hw *hw = dev_id;
2781 /* Reading this mask interrupts as side effect */
2782 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2783 if (status == 0 || status == ~0)
2786 prefetch(&hw->st_le[hw->st_idx]);
2788 napi_schedule(&hw->napi);
2793 #ifdef CONFIG_NET_POLL_CONTROLLER
2794 static void sky2_netpoll(struct net_device *dev)
2796 struct sky2_port *sky2 = netdev_priv(dev);
2798 napi_schedule(&sky2->hw->napi);
2802 /* Chip internal frequency for clock calculations */
2803 static u32 sky2_mhz(const struct sky2_hw *hw)
2805 switch (hw->chip_id) {
2806 case CHIP_ID_YUKON_EC:
2807 case CHIP_ID_YUKON_EC_U:
2808 case CHIP_ID_YUKON_EX:
2809 case CHIP_ID_YUKON_SUPR:
2812 case CHIP_ID_YUKON_FE:
2815 case CHIP_ID_YUKON_FE_P:
2818 case CHIP_ID_YUKON_XL:
2826 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2828 return sky2_mhz(hw) * us;
2831 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2833 return clk / sky2_mhz(hw);
2837 static int __devinit sky2_init(struct sky2_hw *hw)
2841 /* Enable all clocks and check for bad PCI access */
2842 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2844 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2846 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2847 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2849 switch(hw->chip_id) {
2850 case CHIP_ID_YUKON_XL:
2851 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
2854 case CHIP_ID_YUKON_EC_U:
2855 hw->flags = SKY2_HW_GIGABIT
2857 | SKY2_HW_ADV_POWER_CTL;
2859 /* check for Rev. A1 dev 4200 */
2860 if (sky2_read16(hw, Q_ADDR(Q_XA1, Q_WM)) == 0)
2861 hw->flags |= SKY2_HW_CLK_POWER;
2864 case CHIP_ID_YUKON_EX:
2865 hw->flags = SKY2_HW_GIGABIT
2868 | SKY2_HW_ADV_POWER_CTL;
2870 /* New transmit checksum */
2871 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2872 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2875 case CHIP_ID_YUKON_EC:
2876 /* This rev is really old, and requires untested workarounds */
2877 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2878 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2881 hw->flags = SKY2_HW_GIGABIT;
2884 case CHIP_ID_YUKON_FE:
2887 case CHIP_ID_YUKON_FE_P:
2888 hw->flags = SKY2_HW_NEWER_PHY
2890 | SKY2_HW_AUTO_TX_SUM
2891 | SKY2_HW_ADV_POWER_CTL;
2894 case CHIP_ID_YUKON_SUPR:
2895 hw->flags = SKY2_HW_GIGABIT
2898 | SKY2_HW_AUTO_TX_SUM
2899 | SKY2_HW_ADV_POWER_CTL;
2903 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2908 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2909 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
2910 hw->flags |= SKY2_HW_FIBRE_PHY;
2912 hw->pm_cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PM);
2913 if (hw->pm_cap == 0) {
2914 dev_err(&hw->pdev->dev, "cannot find PowerManagement capability\n");
2919 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2920 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2921 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2928 static void sky2_reset(struct sky2_hw *hw)
2930 struct pci_dev *pdev = hw->pdev;
2933 u32 hwe_mask = Y2_HWE_ALL_MASK;
2936 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2937 status = sky2_read16(hw, HCU_CCSR);
2938 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2939 HCU_CCSR_UC_STATE_MSK);
2940 sky2_write16(hw, HCU_CCSR, status);
2942 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2943 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2946 sky2_write8(hw, B0_CTST, CS_RST_SET);
2947 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2949 /* allow writes to PCI config */
2950 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2952 /* clear PCI errors, if any */
2953 status = sky2_pci_read16(hw, PCI_STATUS);
2954 status |= PCI_STATUS_ERROR_BITS;
2955 sky2_pci_write16(hw, PCI_STATUS, status);
2957 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2959 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2961 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2964 /* If error bit is stuck on ignore it */
2965 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
2966 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
2968 hwe_mask |= Y2_IS_PCI_EXP;
2972 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2974 for (i = 0; i < hw->ports; i++) {
2975 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2976 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2978 if (hw->chip_id == CHIP_ID_YUKON_EX ||
2979 hw->chip_id == CHIP_ID_YUKON_SUPR)
2980 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
2981 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
2985 /* Clear I2C IRQ noise */
2986 sky2_write32(hw, B2_I2C_IRQ, 1);
2988 /* turn off hardware timer (unused) */
2989 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2990 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2992 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2994 /* Turn off descriptor polling */
2995 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
2997 /* Turn off receive timestamp */
2998 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
2999 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
3001 /* enable the Tx Arbiters */
3002 for (i = 0; i < hw->ports; i++)
3003 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3005 /* Initialize ram interface */
3006 for (i = 0; i < hw->ports; i++) {
3007 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
3009 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
3010 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
3011 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
3012 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
3013 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
3014 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
3015 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
3016 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
3017 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
3018 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
3019 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
3020 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
3023 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
3025 for (i = 0; i < hw->ports; i++)
3026 sky2_gmac_reset(hw, i);
3028 memset(hw->st_le, 0, STATUS_LE_BYTES);
3031 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
3032 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
3034 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
3035 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
3037 /* Set the list last index */
3038 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
3040 sky2_write16(hw, STAT_TX_IDX_TH, 10);
3041 sky2_write8(hw, STAT_FIFO_WM, 16);
3043 /* set Status-FIFO ISR watermark */
3044 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
3045 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
3047 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
3049 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
3050 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3051 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
3053 /* enable status unit */
3054 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3056 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3057 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3058 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3061 static void sky2_restart(struct work_struct *work)
3063 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
3064 struct net_device *dev;
3068 for (i = 0; i < hw->ports; i++) {
3070 if (netif_running(dev))
3074 napi_disable(&hw->napi);
3075 sky2_write32(hw, B0_IMSK, 0);
3077 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3078 napi_enable(&hw->napi);
3080 for (i = 0; i < hw->ports; i++) {
3082 if (netif_running(dev)) {
3085 printk(KERN_INFO PFX "%s: could not restart %d\n",
3095 static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3097 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3100 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3102 const struct sky2_port *sky2 = netdev_priv(dev);
3104 wol->supported = sky2_wol_supported(sky2->hw);
3105 wol->wolopts = sky2->wol;
3108 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3110 struct sky2_port *sky2 = netdev_priv(dev);
3111 struct sky2_hw *hw = sky2->hw;
3113 if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
3116 sky2->wol = wol->wolopts;
3118 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3119 hw->chip_id == CHIP_ID_YUKON_EX ||
3120 hw->chip_id == CHIP_ID_YUKON_FE_P)
3121 sky2_write32(hw, B0_CTST, sky2->wol
3122 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
3124 if (!netif_running(dev))
3125 sky2_wol_init(sky2);
3129 static u32 sky2_supported_modes(const struct sky2_hw *hw)
3131 if (sky2_is_copper(hw)) {
3132 u32 modes = SUPPORTED_10baseT_Half
3133 | SUPPORTED_10baseT_Full
3134 | SUPPORTED_100baseT_Half
3135 | SUPPORTED_100baseT_Full
3136 | SUPPORTED_Autoneg | SUPPORTED_TP;
3138 if (hw->flags & SKY2_HW_GIGABIT)
3139 modes |= SUPPORTED_1000baseT_Half
3140 | SUPPORTED_1000baseT_Full;
3143 return SUPPORTED_1000baseT_Half
3144 | SUPPORTED_1000baseT_Full
3149 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3151 struct sky2_port *sky2 = netdev_priv(dev);
3152 struct sky2_hw *hw = sky2->hw;
3154 ecmd->transceiver = XCVR_INTERNAL;
3155 ecmd->supported = sky2_supported_modes(hw);
3156 ecmd->phy_address = PHY_ADDR_MARV;
3157 if (sky2_is_copper(hw)) {
3158 ecmd->port = PORT_TP;
3159 ecmd->speed = sky2->speed;
3161 ecmd->speed = SPEED_1000;
3162 ecmd->port = PORT_FIBRE;
3165 ecmd->advertising = sky2->advertising;
3166 ecmd->autoneg = sky2->autoneg;
3167 ecmd->duplex = sky2->duplex;
3171 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3173 struct sky2_port *sky2 = netdev_priv(dev);
3174 const struct sky2_hw *hw = sky2->hw;
3175 u32 supported = sky2_supported_modes(hw);
3177 if (ecmd->autoneg == AUTONEG_ENABLE) {
3178 ecmd->advertising = supported;
3184 switch (ecmd->speed) {
3186 if (ecmd->duplex == DUPLEX_FULL)
3187 setting = SUPPORTED_1000baseT_Full;
3188 else if (ecmd->duplex == DUPLEX_HALF)
3189 setting = SUPPORTED_1000baseT_Half;
3194 if (ecmd->duplex == DUPLEX_FULL)
3195 setting = SUPPORTED_100baseT_Full;
3196 else if (ecmd->duplex == DUPLEX_HALF)
3197 setting = SUPPORTED_100baseT_Half;
3203 if (ecmd->duplex == DUPLEX_FULL)
3204 setting = SUPPORTED_10baseT_Full;
3205 else if (ecmd->duplex == DUPLEX_HALF)
3206 setting = SUPPORTED_10baseT_Half;
3214 if ((setting & supported) == 0)
3217 sky2->speed = ecmd->speed;
3218 sky2->duplex = ecmd->duplex;
3221 sky2->autoneg = ecmd->autoneg;
3222 sky2->advertising = ecmd->advertising;
3224 if (netif_running(dev)) {
3225 sky2_phy_reinit(sky2);
3226 sky2_set_multicast(dev);
3232 static void sky2_get_drvinfo(struct net_device *dev,
3233 struct ethtool_drvinfo *info)
3235 struct sky2_port *sky2 = netdev_priv(dev);
3237 strcpy(info->driver, DRV_NAME);
3238 strcpy(info->version, DRV_VERSION);
3239 strcpy(info->fw_version, "N/A");
3240 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3243 static const struct sky2_stat {
3244 char name[ETH_GSTRING_LEN];
3247 { "tx_bytes", GM_TXO_OK_HI },
3248 { "rx_bytes", GM_RXO_OK_HI },
3249 { "tx_broadcast", GM_TXF_BC_OK },
3250 { "rx_broadcast", GM_RXF_BC_OK },
3251 { "tx_multicast", GM_TXF_MC_OK },
3252 { "rx_multicast", GM_RXF_MC_OK },
3253 { "tx_unicast", GM_TXF_UC_OK },
3254 { "rx_unicast", GM_RXF_UC_OK },
3255 { "tx_mac_pause", GM_TXF_MPAUSE },
3256 { "rx_mac_pause", GM_RXF_MPAUSE },
3257 { "collisions", GM_TXF_COL },
3258 { "late_collision",GM_TXF_LAT_COL },
3259 { "aborted", GM_TXF_ABO_COL },
3260 { "single_collisions", GM_TXF_SNG_COL },
3261 { "multi_collisions", GM_TXF_MUL_COL },
3263 { "rx_short", GM_RXF_SHT },
3264 { "rx_runt", GM_RXE_FRAG },
3265 { "rx_64_byte_packets", GM_RXF_64B },
3266 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3267 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3268 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3269 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3270 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3271 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
3272 { "rx_too_long", GM_RXF_LNG_ERR },
3273 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3274 { "rx_jabber", GM_RXF_JAB_PKT },
3275 { "rx_fcs_error", GM_RXF_FCS_ERR },
3277 { "tx_64_byte_packets", GM_TXF_64B },
3278 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3279 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3280 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3281 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3282 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3283 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3284 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
3287 static u32 sky2_get_rx_csum(struct net_device *dev)
3289 struct sky2_port *sky2 = netdev_priv(dev);
3291 return sky2->rx_csum;
3294 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3296 struct sky2_port *sky2 = netdev_priv(dev);
3298 sky2->rx_csum = data;
3300 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3301 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3306 static u32 sky2_get_msglevel(struct net_device *netdev)
3308 struct sky2_port *sky2 = netdev_priv(netdev);
3309 return sky2->msg_enable;
3312 static int sky2_nway_reset(struct net_device *dev)
3314 struct sky2_port *sky2 = netdev_priv(dev);
3316 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
3319 sky2_phy_reinit(sky2);
3320 sky2_set_multicast(dev);
3325 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
3327 struct sky2_hw *hw = sky2->hw;
3328 unsigned port = sky2->port;
3331 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
3332 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
3333 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
3334 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
3336 for (i = 2; i < count; i++)
3337 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3340 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3342 struct sky2_port *sky2 = netdev_priv(netdev);
3343 sky2->msg_enable = value;
3346 static int sky2_get_sset_count(struct net_device *dev, int sset)
3350 return ARRAY_SIZE(sky2_stats);
3356 static void sky2_get_ethtool_stats(struct net_device *dev,
3357 struct ethtool_stats *stats, u64 * data)
3359 struct sky2_port *sky2 = netdev_priv(dev);
3361 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
3364 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
3368 switch (stringset) {
3370 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3371 memcpy(data + i * ETH_GSTRING_LEN,
3372 sky2_stats[i].name, ETH_GSTRING_LEN);
3377 static int sky2_set_mac_address(struct net_device *dev, void *p)
3379 struct sky2_port *sky2 = netdev_priv(dev);
3380 struct sky2_hw *hw = sky2->hw;
3381 unsigned port = sky2->port;
3382 const struct sockaddr *addr = p;
3384 if (!is_valid_ether_addr(addr->sa_data))
3385 return -EADDRNOTAVAIL;
3387 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3388 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
3389 dev->dev_addr, ETH_ALEN);
3390 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
3391 dev->dev_addr, ETH_ALEN);
3393 /* virtual address for data */
3394 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3396 /* physical address: used for pause frames */
3397 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3402 static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3406 bit = ether_crc(ETH_ALEN, addr) & 63;
3407 filter[bit >> 3] |= 1 << (bit & 7);
3410 static void sky2_set_multicast(struct net_device *dev)
3412 struct sky2_port *sky2 = netdev_priv(dev);
3413 struct sky2_hw *hw = sky2->hw;
3414 unsigned port = sky2->port;
3415 struct dev_mc_list *list = dev->mc_list;
3419 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3421 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
3422 memset(filter, 0, sizeof(filter));
3424 reg = gma_read16(hw, port, GM_RX_CTRL);
3425 reg |= GM_RXCR_UCF_ENA;
3427 if (dev->flags & IFF_PROMISC) /* promiscuous */
3428 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
3429 else if (dev->flags & IFF_ALLMULTI)
3430 memset(filter, 0xff, sizeof(filter));
3431 else if (dev->mc_count == 0 && !rx_pause)
3432 reg &= ~GM_RXCR_MCF_ENA;
3435 reg |= GM_RXCR_MCF_ENA;
3438 sky2_add_filter(filter, pause_mc_addr);
3440 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3441 sky2_add_filter(filter, list->dmi_addr);
3444 gma_write16(hw, port, GM_MC_ADDR_H1,
3445 (u16) filter[0] | ((u16) filter[1] << 8));
3446 gma_write16(hw, port, GM_MC_ADDR_H2,
3447 (u16) filter[2] | ((u16) filter[3] << 8));
3448 gma_write16(hw, port, GM_MC_ADDR_H3,
3449 (u16) filter[4] | ((u16) filter[5] << 8));
3450 gma_write16(hw, port, GM_MC_ADDR_H4,
3451 (u16) filter[6] | ((u16) filter[7] << 8));
3453 gma_write16(hw, port, GM_RX_CTRL, reg);
3456 /* Can have one global because blinking is controlled by
3457 * ethtool and that is always under RTNL mutex
3459 static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
3461 struct sky2_hw *hw = sky2->hw;
3462 unsigned port = sky2->port;
3464 spin_lock_bh(&sky2->phy_lock);
3465 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3466 hw->chip_id == CHIP_ID_YUKON_EX ||
3467 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3469 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3470 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3474 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3475 PHY_M_LEDC_LOS_CTRL(8) |
3476 PHY_M_LEDC_INIT_CTRL(8) |
3477 PHY_M_LEDC_STA1_CTRL(8) |
3478 PHY_M_LEDC_STA0_CTRL(8));
3481 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3482 PHY_M_LEDC_LOS_CTRL(9) |
3483 PHY_M_LEDC_INIT_CTRL(9) |
3484 PHY_M_LEDC_STA1_CTRL(9) |
3485 PHY_M_LEDC_STA0_CTRL(9));
3488 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3489 PHY_M_LEDC_LOS_CTRL(0xa) |
3490 PHY_M_LEDC_INIT_CTRL(0xa) |
3491 PHY_M_LEDC_STA1_CTRL(0xa) |
3492 PHY_M_LEDC_STA0_CTRL(0xa));
3495 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3496 PHY_M_LEDC_LOS_CTRL(1) |
3497 PHY_M_LEDC_INIT_CTRL(8) |
3498 PHY_M_LEDC_STA1_CTRL(7) |
3499 PHY_M_LEDC_STA0_CTRL(7));
3502 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3504 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3505 PHY_M_LED_MO_DUP(mode) |
3506 PHY_M_LED_MO_10(mode) |
3507 PHY_M_LED_MO_100(mode) |
3508 PHY_M_LED_MO_1000(mode) |
3509 PHY_M_LED_MO_RX(mode) |
3510 PHY_M_LED_MO_TX(mode));
3512 spin_unlock_bh(&sky2->phy_lock);
3515 /* blink LED's for finding board */
3516 static int sky2_phys_id(struct net_device *dev, u32 data)
3518 struct sky2_port *sky2 = netdev_priv(dev);
3524 for (i = 0; i < data; i++) {
3525 sky2_led(sky2, MO_LED_ON);
3526 if (msleep_interruptible(500))
3528 sky2_led(sky2, MO_LED_OFF);
3529 if (msleep_interruptible(500))
3532 sky2_led(sky2, MO_LED_NORM);
3537 static void sky2_get_pauseparam(struct net_device *dev,
3538 struct ethtool_pauseparam *ecmd)
3540 struct sky2_port *sky2 = netdev_priv(dev);
3542 switch (sky2->flow_mode) {
3544 ecmd->tx_pause = ecmd->rx_pause = 0;
3547 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3550 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3553 ecmd->tx_pause = ecmd->rx_pause = 1;
3556 ecmd->autoneg = sky2->autoneg;
3559 static int sky2_set_pauseparam(struct net_device *dev,
3560 struct ethtool_pauseparam *ecmd)
3562 struct sky2_port *sky2 = netdev_priv(dev);
3564 sky2->autoneg = ecmd->autoneg;
3565 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
3567 if (netif_running(dev))
3568 sky2_phy_reinit(sky2);
3573 static int sky2_get_coalesce(struct net_device *dev,
3574 struct ethtool_coalesce *ecmd)
3576 struct sky2_port *sky2 = netdev_priv(dev);
3577 struct sky2_hw *hw = sky2->hw;
3579 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3580 ecmd->tx_coalesce_usecs = 0;
3582 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3583 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3585 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3587 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3588 ecmd->rx_coalesce_usecs = 0;
3590 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3591 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3593 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3595 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3596 ecmd->rx_coalesce_usecs_irq = 0;
3598 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3599 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3602 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3607 /* Note: this affect both ports */
3608 static int sky2_set_coalesce(struct net_device *dev,
3609 struct ethtool_coalesce *ecmd)
3611 struct sky2_port *sky2 = netdev_priv(dev);
3612 struct sky2_hw *hw = sky2->hw;
3613 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
3615 if (ecmd->tx_coalesce_usecs > tmax ||
3616 ecmd->rx_coalesce_usecs > tmax ||
3617 ecmd->rx_coalesce_usecs_irq > tmax)
3620 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
3622 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
3624 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
3627 if (ecmd->tx_coalesce_usecs == 0)
3628 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3630 sky2_write32(hw, STAT_TX_TIMER_INI,
3631 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3632 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3634 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3636 if (ecmd->rx_coalesce_usecs == 0)
3637 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3639 sky2_write32(hw, STAT_LEV_TIMER_INI,
3640 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3641 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3643 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3645 if (ecmd->rx_coalesce_usecs_irq == 0)
3646 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3648 sky2_write32(hw, STAT_ISR_TIMER_INI,
3649 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3650 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3652 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3656 static void sky2_get_ringparam(struct net_device *dev,
3657 struct ethtool_ringparam *ering)
3659 struct sky2_port *sky2 = netdev_priv(dev);
3661 ering->rx_max_pending = RX_MAX_PENDING;
3662 ering->rx_mini_max_pending = 0;
3663 ering->rx_jumbo_max_pending = 0;
3664 ering->tx_max_pending = TX_RING_SIZE - 1;
3666 ering->rx_pending = sky2->rx_pending;
3667 ering->rx_mini_pending = 0;
3668 ering->rx_jumbo_pending = 0;
3669 ering->tx_pending = sky2->tx_pending;
3672 static int sky2_set_ringparam(struct net_device *dev,
3673 struct ethtool_ringparam *ering)
3675 struct sky2_port *sky2 = netdev_priv(dev);
3678 if (ering->rx_pending > RX_MAX_PENDING ||
3679 ering->rx_pending < 8 ||
3680 ering->tx_pending < MAX_SKB_TX_LE ||
3681 ering->tx_pending > TX_RING_SIZE - 1)
3684 if (netif_running(dev))
3687 sky2->rx_pending = ering->rx_pending;
3688 sky2->tx_pending = ering->tx_pending;
3690 if (netif_running(dev)) {
3699 static int sky2_get_regs_len(struct net_device *dev)
3705 * Returns copy of control register region
3706 * Note: ethtool_get_regs always provides full size (16k) buffer
3708 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3711 const struct sky2_port *sky2 = netdev_priv(dev);
3712 const void __iomem *io = sky2->hw->regs;
3717 for (b = 0; b < 128; b++) {
3718 /* This complicated switch statement is to make sure and
3719 * only access regions that are unreserved.
3720 * Some blocks are only valid on dual port cards.
3721 * and block 3 has some special diagnostic registers that
3726 /* skip diagnostic ram region */
3727 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
3730 /* dual port cards only */
3731 case 5: /* Tx Arbiter 2 */
3733 case 14 ... 15: /* TX2 */
3734 case 17: case 19: /* Ram Buffer 2 */
3735 case 22 ... 23: /* Tx Ram Buffer 2 */
3736 case 25: /* Rx MAC Fifo 1 */
3737 case 27: /* Tx MAC Fifo 2 */
3738 case 31: /* GPHY 2 */
3739 case 40 ... 47: /* Pattern Ram 2 */
3740 case 52: case 54: /* TCP Segmentation 2 */
3741 case 112 ... 116: /* GMAC 2 */
3742 if (sky2->hw->ports == 1)
3745 case 0: /* Control */
3746 case 2: /* Mac address */
3747 case 4: /* Tx Arbiter 1 */
3748 case 7: /* PCI express reg */
3750 case 12 ... 13: /* TX1 */
3751 case 16: case 18:/* Rx Ram Buffer 1 */
3752 case 20 ... 21: /* Tx Ram Buffer 1 */
3753 case 24: /* Rx MAC Fifo 1 */
3754 case 26: /* Tx MAC Fifo 1 */
3755 case 28 ... 29: /* Descriptor and status unit */
3756 case 30: /* GPHY 1*/
3757 case 32 ... 39: /* Pattern Ram 1 */
3758 case 48: case 50: /* TCP Segmentation 1 */
3759 case 56 ... 60: /* PCI space */
3760 case 80 ... 84: /* GMAC 1 */
3761 memcpy_fromio(p, io, 128);
3773 /* In order to do Jumbo packets on these chips, need to turn off the
3774 * transmit store/forward. Therefore checksum offload won't work.
3776 static int no_tx_offload(struct net_device *dev)
3778 const struct sky2_port *sky2 = netdev_priv(dev);
3779 const struct sky2_hw *hw = sky2->hw;
3781 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
3784 static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3786 if (data && no_tx_offload(dev))
3789 return ethtool_op_set_tx_csum(dev, data);
3793 static int sky2_set_tso(struct net_device *dev, u32 data)
3795 if (data && no_tx_offload(dev))
3798 return ethtool_op_set_tso(dev, data);
3801 static int sky2_get_eeprom_len(struct net_device *dev)
3803 struct sky2_port *sky2 = netdev_priv(dev);
3804 struct sky2_hw *hw = sky2->hw;
3807 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
3808 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3811 static u32 sky2_vpd_read(struct sky2_hw *hw, int cap, u16 offset)
3815 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
3818 offset = sky2_pci_read16(hw, cap + PCI_VPD_ADDR);
3819 } while (!(offset & PCI_VPD_ADDR_F));
3821 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
3825 static void sky2_vpd_write(struct sky2_hw *hw, int cap, u16 offset, u32 val)
3827 sky2_pci_write16(hw, cap + PCI_VPD_DATA, val);
3828 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
3830 offset = sky2_pci_read16(hw, cap + PCI_VPD_ADDR);
3831 } while (offset & PCI_VPD_ADDR_F);
3834 static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3837 struct sky2_port *sky2 = netdev_priv(dev);
3838 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3839 int length = eeprom->len;
3840 u16 offset = eeprom->offset;
3845 eeprom->magic = SKY2_EEPROM_MAGIC;
3847 while (length > 0) {
3848 u32 val = sky2_vpd_read(sky2->hw, cap, offset);
3849 int n = min_t(int, length, sizeof(val));
3851 memcpy(data, &val, n);
3859 static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3862 struct sky2_port *sky2 = netdev_priv(dev);
3863 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3864 int length = eeprom->len;
3865 u16 offset = eeprom->offset;
3870 if (eeprom->magic != SKY2_EEPROM_MAGIC)
3873 while (length > 0) {
3875 int n = min_t(int, length, sizeof(val));
3877 if (n < sizeof(val))
3878 val = sky2_vpd_read(sky2->hw, cap, offset);
3879 memcpy(&val, data, n);
3881 sky2_vpd_write(sky2->hw, cap, offset, val);
3891 static const struct ethtool_ops sky2_ethtool_ops = {
3892 .get_settings = sky2_get_settings,
3893 .set_settings = sky2_set_settings,
3894 .get_drvinfo = sky2_get_drvinfo,
3895 .get_wol = sky2_get_wol,
3896 .set_wol = sky2_set_wol,
3897 .get_msglevel = sky2_get_msglevel,
3898 .set_msglevel = sky2_set_msglevel,
3899 .nway_reset = sky2_nway_reset,
3900 .get_regs_len = sky2_get_regs_len,
3901 .get_regs = sky2_get_regs,
3902 .get_link = ethtool_op_get_link,
3903 .get_eeprom_len = sky2_get_eeprom_len,
3904 .get_eeprom = sky2_get_eeprom,
3905 .set_eeprom = sky2_set_eeprom,
3906 .set_sg = ethtool_op_set_sg,
3907 .set_tx_csum = sky2_set_tx_csum,
3908 .set_tso = sky2_set_tso,
3909 .get_rx_csum = sky2_get_rx_csum,
3910 .set_rx_csum = sky2_set_rx_csum,
3911 .get_strings = sky2_get_strings,
3912 .get_coalesce = sky2_get_coalesce,
3913 .set_coalesce = sky2_set_coalesce,
3914 .get_ringparam = sky2_get_ringparam,
3915 .set_ringparam = sky2_set_ringparam,
3916 .get_pauseparam = sky2_get_pauseparam,
3917 .set_pauseparam = sky2_set_pauseparam,
3918 .phys_id = sky2_phys_id,
3919 .get_sset_count = sky2_get_sset_count,
3920 .get_ethtool_stats = sky2_get_ethtool_stats,
3923 #ifdef CONFIG_SKY2_DEBUG
3925 static struct dentry *sky2_debug;
3927 static int sky2_debug_show(struct seq_file *seq, void *v)
3929 struct net_device *dev = seq->private;
3930 const struct sky2_port *sky2 = netdev_priv(dev);
3931 struct sky2_hw *hw = sky2->hw;
3932 unsigned port = sky2->port;
3936 if (!netif_running(dev))
3939 seq_printf(seq, "IRQ src=%x mask=%x control=%x\n",
3940 sky2_read32(hw, B0_ISRC),
3941 sky2_read32(hw, B0_IMSK),
3942 sky2_read32(hw, B0_Y2_SP_ICR));
3944 napi_disable(&hw->napi);
3945 last = sky2_read16(hw, STAT_PUT_IDX);
3947 if (hw->st_idx == last)
3948 seq_puts(seq, "Status ring (empty)\n");
3950 seq_puts(seq, "Status ring\n");
3951 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
3952 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
3953 const struct sky2_status_le *le = hw->st_le + idx;
3954 seq_printf(seq, "[%d] %#x %d %#x\n",
3955 idx, le->opcode, le->length, le->status);
3957 seq_puts(seq, "\n");
3960 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
3961 sky2->tx_cons, sky2->tx_prod,
3962 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
3963 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
3965 /* Dump contents of tx ring */
3967 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < TX_RING_SIZE;
3968 idx = RING_NEXT(idx, TX_RING_SIZE)) {
3969 const struct sky2_tx_le *le = sky2->tx_le + idx;
3970 u32 a = le32_to_cpu(le->addr);
3973 seq_printf(seq, "%u:", idx);
3976 switch(le->opcode & ~HW_OWNER) {
3978 seq_printf(seq, " %#x:", a);
3981 seq_printf(seq, " mtu=%d", a);
3984 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
3987 seq_printf(seq, " csum=%#x", a);
3990 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
3993 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
3996 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
3999 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
4000 a, le16_to_cpu(le->length));
4003 if (le->ctrl & EOP) {
4004 seq_putc(seq, '\n');
4009 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
4010 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
4011 last = sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
4012 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
4014 sky2_read32(hw, B0_Y2_SP_LISR);
4015 napi_enable(&hw->napi);
4019 static int sky2_debug_open(struct inode *inode, struct file *file)
4021 return single_open(file, sky2_debug_show, inode->i_private);
4024 static const struct file_operations sky2_debug_fops = {
4025 .owner = THIS_MODULE,
4026 .open = sky2_debug_open,
4028 .llseek = seq_lseek,
4029 .release = single_release,
4033 * Use network device events to create/remove/rename
4034 * debugfs file entries
4036 static int sky2_device_event(struct notifier_block *unused,
4037 unsigned long event, void *ptr)
4039 struct net_device *dev = ptr;
4040 struct sky2_port *sky2 = netdev_priv(dev);
4042 if (dev->open != sky2_up || !sky2_debug)
4046 case NETDEV_CHANGENAME:
4047 if (sky2->debugfs) {
4048 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
4049 sky2_debug, dev->name);
4053 case NETDEV_GOING_DOWN:
4054 if (sky2->debugfs) {
4055 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
4057 debugfs_remove(sky2->debugfs);
4058 sky2->debugfs = NULL;
4063 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
4066 if (IS_ERR(sky2->debugfs))
4067 sky2->debugfs = NULL;
4073 static struct notifier_block sky2_notifier = {
4074 .notifier_call = sky2_device_event,
4078 static __init void sky2_debug_init(void)
4082 ent = debugfs_create_dir("sky2", NULL);
4083 if (!ent || IS_ERR(ent))
4087 register_netdevice_notifier(&sky2_notifier);
4090 static __exit void sky2_debug_cleanup(void)
4093 unregister_netdevice_notifier(&sky2_notifier);
4094 debugfs_remove(sky2_debug);
4100 #define sky2_debug_init()
4101 #define sky2_debug_cleanup()
4105 /* Initialize network device */
4106 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
4108 int highmem, int wol)
4110 struct sky2_port *sky2;
4111 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4114 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
4118 SET_NETDEV_DEV(dev, &hw->pdev->dev);
4119 dev->irq = hw->pdev->irq;
4120 dev->open = sky2_up;
4121 dev->stop = sky2_down;
4122 dev->do_ioctl = sky2_ioctl;
4123 dev->hard_start_xmit = sky2_xmit_frame;
4124 dev->set_multicast_list = sky2_set_multicast;
4125 dev->set_mac_address = sky2_set_mac_address;
4126 dev->change_mtu = sky2_change_mtu;
4127 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
4128 dev->tx_timeout = sky2_tx_timeout;
4129 dev->watchdog_timeo = TX_WATCHDOG;
4130 #ifdef CONFIG_NET_POLL_CONTROLLER
4132 dev->poll_controller = sky2_netpoll;
4135 sky2 = netdev_priv(dev);
4138 sky2->msg_enable = netif_msg_init(debug, default_msg);
4140 /* Auto speed and flow control */
4141 sky2->autoneg = AUTONEG_ENABLE;
4142 sky2->flow_mode = FC_BOTH;
4146 sky2->advertising = sky2_supported_modes(hw);
4147 sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);
4150 spin_lock_init(&sky2->phy_lock);
4151 sky2->tx_pending = TX_DEF_PENDING;
4152 sky2->rx_pending = RX_DEF_PENDING;
4154 hw->dev[port] = dev;
4158 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
4160 dev->features |= NETIF_F_HIGHDMA;
4162 #ifdef SKY2_VLAN_TAG_USED
4163 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4164 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4165 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4166 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4167 dev->vlan_rx_register = sky2_vlan_rx_register;
4171 /* read the mac address */
4172 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
4173 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
4178 static void __devinit sky2_show_addr(struct net_device *dev)
4180 const struct sky2_port *sky2 = netdev_priv(dev);
4181 DECLARE_MAC_BUF(mac);
4183 if (netif_msg_probe(sky2))
4184 printk(KERN_INFO PFX "%s: addr %s\n",
4185 dev->name, print_mac(mac, dev->dev_addr));
4188 /* Handle software interrupt used during MSI test */
4189 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
4191 struct sky2_hw *hw = dev_id;
4192 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4197 if (status & Y2_IS_IRQ_SW) {
4198 hw->flags |= SKY2_HW_USE_MSI;
4199 wake_up(&hw->msi_wait);
4200 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4202 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4207 /* Test interrupt path by forcing a a software IRQ */
4208 static int __devinit sky2_test_msi(struct sky2_hw *hw)
4210 struct pci_dev *pdev = hw->pdev;
4213 init_waitqueue_head (&hw->msi_wait);
4215 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4217 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
4219 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4223 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
4224 sky2_read8(hw, B0_CTST);
4226 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
4228 if (!(hw->flags & SKY2_HW_USE_MSI)) {
4229 /* MSI test failed, go back to INTx mode */
4230 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4231 "switching to INTx mode.\n");
4234 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4237 sky2_write32(hw, B0_IMSK, 0);
4238 sky2_read32(hw, B0_IMSK);
4240 free_irq(pdev->irq, hw);
4245 static int __devinit pci_wake_enabled(struct pci_dev *dev)
4247 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
4252 if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value))
4254 return value & PCI_PM_CTRL_PME_ENABLE;
4257 /* This driver supports yukon2 chipset only */
4258 static const char *sky2_name(u8 chipid, char *buf, int sz)
4260 const char *name[] = {
4262 "EC Ultra", /* 0xb4 */
4263 "Extreme", /* 0xb5 */
4267 "Supreme", /* 0xb9 */
4270 if (chipid >= CHIP_ID_YUKON_XL && chipid < CHIP_ID_YUKON_SUPR)
4271 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
4273 snprintf(buf, sz, "(chip %#x)", chipid);
4277 static int __devinit sky2_probe(struct pci_dev *pdev,
4278 const struct pci_device_id *ent)
4280 struct net_device *dev;
4282 int err, using_dac = 0, wol_default;
4285 err = pci_enable_device(pdev);
4287 dev_err(&pdev->dev, "cannot enable PCI device\n");
4291 err = pci_request_regions(pdev, DRV_NAME);
4293 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
4294 goto err_out_disable;
4297 pci_set_master(pdev);
4299 if (sizeof(dma_addr_t) > sizeof(u32) &&
4300 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
4302 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
4304 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4305 "for consistent allocations\n");
4306 goto err_out_free_regions;
4309 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
4311 dev_err(&pdev->dev, "no usable DMA configuration\n");
4312 goto err_out_free_regions;
4316 wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0;
4319 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
4321 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
4322 goto err_out_free_regions;
4327 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4329 dev_err(&pdev->dev, "cannot map device registers\n");
4330 goto err_out_free_hw;
4334 /* The sk98lin vendor driver uses hardware byte swapping but
4335 * this driver uses software swapping.
4339 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
4340 reg &= ~PCI_REV_DESC;
4341 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
4345 /* ring for status responses */
4346 hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
4348 goto err_out_iounmap;
4350 err = sky2_init(hw);
4352 goto err_out_iounmap;
4354 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-2 %s rev %d\n",
4355 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
4356 pdev->irq, sky2_name(hw->chip_id, buf1, sizeof(buf1)),
4361 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
4364 goto err_out_free_pci;
4367 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4368 err = sky2_test_msi(hw);
4369 if (err == -EOPNOTSUPP)
4370 pci_disable_msi(pdev);
4372 goto err_out_free_netdev;
4375 err = register_netdev(dev);
4377 dev_err(&pdev->dev, "cannot register net device\n");
4378 goto err_out_free_netdev;
4381 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4383 err = request_irq(pdev->irq, sky2_intr,
4384 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
4387 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4388 goto err_out_unregister;
4390 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4391 napi_enable(&hw->napi);
4393 sky2_show_addr(dev);
4395 if (hw->ports > 1) {
4396 struct net_device *dev1;
4398 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
4400 dev_warn(&pdev->dev, "allocation for second device failed\n");
4401 else if ((err = register_netdev(dev1))) {
4402 dev_warn(&pdev->dev,
4403 "register of second port failed (%d)\n", err);
4407 sky2_show_addr(dev1);
4410 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
4411 INIT_WORK(&hw->restart_work, sky2_restart);
4413 pci_set_drvdata(pdev, hw);
4418 if (hw->flags & SKY2_HW_USE_MSI)
4419 pci_disable_msi(pdev);
4420 unregister_netdev(dev);
4421 err_out_free_netdev:
4424 sky2_write8(hw, B0_CTST, CS_RST_SET);
4425 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4430 err_out_free_regions:
4431 pci_release_regions(pdev);
4433 pci_disable_device(pdev);
4435 pci_set_drvdata(pdev, NULL);
4439 static void __devexit sky2_remove(struct pci_dev *pdev)
4441 struct sky2_hw *hw = pci_get_drvdata(pdev);
4447 del_timer_sync(&hw->watchdog_timer);
4448 cancel_work_sync(&hw->restart_work);
4450 for (i = hw->ports-1; i >= 0; --i)
4451 unregister_netdev(hw->dev[i]);
4453 sky2_write32(hw, B0_IMSK, 0);
4457 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
4458 sky2_write8(hw, B0_CTST, CS_RST_SET);
4459 sky2_read8(hw, B0_CTST);
4461 free_irq(pdev->irq, hw);
4462 if (hw->flags & SKY2_HW_USE_MSI)
4463 pci_disable_msi(pdev);
4464 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4465 pci_release_regions(pdev);
4466 pci_disable_device(pdev);
4468 for (i = hw->ports-1; i >= 0; --i)
4469 free_netdev(hw->dev[i]);
4474 pci_set_drvdata(pdev, NULL);
4478 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4480 struct sky2_hw *hw = pci_get_drvdata(pdev);
4486 del_timer_sync(&hw->watchdog_timer);
4487 cancel_work_sync(&hw->restart_work);
4489 for (i = 0; i < hw->ports; i++) {
4490 struct net_device *dev = hw->dev[i];
4491 struct sky2_port *sky2 = netdev_priv(dev);
4493 netif_device_detach(dev);
4494 if (netif_running(dev))
4498 sky2_wol_init(sky2);
4503 sky2_write32(hw, B0_IMSK, 0);
4504 napi_disable(&hw->napi);
4507 pci_save_state(pdev);
4508 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
4509 sky2_power_state(hw, pci_choose_state(pdev, state));
4514 static int sky2_resume(struct pci_dev *pdev)
4516 struct sky2_hw *hw = pci_get_drvdata(pdev);
4522 sky2_power_state(hw, PCI_D0);
4524 err = pci_restore_state(pdev);
4528 pci_enable_wake(pdev, PCI_D0, 0);
4530 /* Re-enable all clocks */
4531 if (hw->chip_id == CHIP_ID_YUKON_EX ||
4532 hw->chip_id == CHIP_ID_YUKON_EC_U ||
4533 hw->chip_id == CHIP_ID_YUKON_FE_P)
4534 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
4537 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4538 napi_enable(&hw->napi);
4540 for (i = 0; i < hw->ports; i++) {
4541 struct net_device *dev = hw->dev[i];
4543 netif_device_attach(dev);
4544 if (netif_running(dev)) {
4547 printk(KERN_ERR PFX "%s: could not up: %d\n",
4559 dev_err(&pdev->dev, "resume failed (%d)\n", err);
4560 pci_disable_device(pdev);
4565 static void sky2_shutdown(struct pci_dev *pdev)
4567 struct sky2_hw *hw = pci_get_drvdata(pdev);
4573 del_timer_sync(&hw->watchdog_timer);
4575 for (i = 0; i < hw->ports; i++) {
4576 struct net_device *dev = hw->dev[i];
4577 struct sky2_port *sky2 = netdev_priv(dev);
4581 sky2_wol_init(sky2);
4588 pci_enable_wake(pdev, PCI_D3hot, wol);
4589 pci_enable_wake(pdev, PCI_D3cold, wol);
4591 pci_disable_device(pdev);
4592 sky2_power_state(hw, PCI_D3hot);
4595 static struct pci_driver sky2_driver = {
4597 .id_table = sky2_id_table,
4598 .probe = sky2_probe,
4599 .remove = __devexit_p(sky2_remove),
4601 .suspend = sky2_suspend,
4602 .resume = sky2_resume,
4604 .shutdown = sky2_shutdown,
4607 static int __init sky2_init_module(void)
4610 return pci_register_driver(&sky2_driver);
4613 static void __exit sky2_cleanup_module(void)
4615 pci_unregister_driver(&sky2_driver);
4616 sky2_debug_cleanup();
4619 module_init(sky2_init_module);
4620 module_exit(sky2_cleanup_module);
4622 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
4623 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
4624 MODULE_LICENSE("GPL");
4625 MODULE_VERSION(DRV_VERSION);