2 * tg3.c: Broadcom Tigon3 ethernet driver.
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2011 Broadcom Corporation.
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/stringify.h>
22 #include <linux/kernel.h>
23 #include <linux/types.h>
24 #include <linux/compiler.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
28 #include <linux/init.h>
29 #include <linux/ioport.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/ethtool.h>
35 #include <linux/mdio.h>
36 #include <linux/mii.h>
37 #include <linux/phy.h>
38 #include <linux/brcmphy.h>
39 #include <linux/if_vlan.h>
41 #include <linux/tcp.h>
42 #include <linux/workqueue.h>
43 #include <linux/prefetch.h>
44 #include <linux/dma-mapping.h>
45 #include <linux/firmware.h>
47 #include <net/checksum.h>
50 #include <asm/system.h>
52 #include <asm/byteorder.h>
53 #include <linux/uaccess.h>
56 #include <asm/idprom.h>
65 /* Functions & macros to verify TG3_FLAGS types */
67 static inline int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits)
69 return test_bit(flag, bits);
72 static inline void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits)
77 static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits)
79 clear_bit(flag, bits);
82 #define tg3_flag(tp, flag) \
83 _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
84 #define tg3_flag_set(tp, flag) \
85 _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
86 #define tg3_flag_clear(tp, flag) \
87 _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
89 #define DRV_MODULE_NAME "tg3"
91 #define TG3_MIN_NUM 119
92 #define DRV_MODULE_VERSION \
93 __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
94 #define DRV_MODULE_RELDATE "May 18, 2011"
96 #define TG3_DEF_MAC_MODE 0
97 #define TG3_DEF_RX_MODE 0
98 #define TG3_DEF_TX_MODE 0
99 #define TG3_DEF_MSG_ENABLE \
109 /* length of time before we decide the hardware is borked,
110 * and dev->tx_timeout() should be called to fix the problem
113 #define TG3_TX_TIMEOUT (5 * HZ)
115 /* hardware minimum and maximum for a single frame's data payload */
116 #define TG3_MIN_MTU 60
117 #define TG3_MAX_MTU(tp) \
118 (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500)
120 /* These numbers seem to be hard coded in the NIC firmware somehow.
121 * You can't change the ring sizes, but you can change where you place
122 * them in the NIC onboard memory.
124 #define TG3_RX_STD_RING_SIZE(tp) \
125 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
126 TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
127 #define TG3_DEF_RX_RING_PENDING 200
128 #define TG3_RX_JMB_RING_SIZE(tp) \
129 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
130 TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
131 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
132 #define TG3_RSS_INDIR_TBL_SIZE 128
134 /* Do not place this n-ring entries value into the tp struct itself,
135 * we really want to expose these constants to GCC so that modulo et
136 * al. operations are done with shifts and masks instead of with
137 * hw multiply/modulo instructions. Another solution would be to
138 * replace things like '% foo' with '& (foo - 1)'.
141 #define TG3_TX_RING_SIZE 512
142 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
144 #define TG3_RX_STD_RING_BYTES(tp) \
145 (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
146 #define TG3_RX_JMB_RING_BYTES(tp) \
147 (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
148 #define TG3_RX_RCB_RING_BYTES(tp) \
149 (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
150 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
152 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
154 #define TG3_DMA_BYTE_ENAB 64
156 #define TG3_RX_STD_DMA_SZ 1536
157 #define TG3_RX_JMB_DMA_SZ 9046
159 #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
161 #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
162 #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
164 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
165 (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
167 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
168 (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
170 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
171 * that are at least dword aligned when used in PCIX mode. The driver
172 * works around this bug by double copying the packet. This workaround
173 * is built into the normal double copy length check for efficiency.
175 * However, the double copy is only necessary on those architectures
176 * where unaligned memory accesses are inefficient. For those architectures
177 * where unaligned memory accesses incur little penalty, we can reintegrate
178 * the 5701 in the normal rx path. Doing so saves a device structure
179 * dereference by hardcoding the double copy threshold in place.
181 #define TG3_RX_COPY_THRESHOLD 256
182 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
183 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
185 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
188 /* minimum number of free TX descriptors required to wake up TX process */
189 #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
191 #define TG3_RAW_IP_ALIGN 2
193 #define TG3_FW_UPDATE_TIMEOUT_SEC 5
195 #define FIRMWARE_TG3 "tigon/tg3.bin"
196 #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
197 #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
199 static char version[] __devinitdata =
200 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
202 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
203 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
204 MODULE_LICENSE("GPL");
205 MODULE_VERSION(DRV_MODULE_VERSION);
206 MODULE_FIRMWARE(FIRMWARE_TG3);
207 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
208 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
210 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
211 module_param(tg3_debug, int, 0);
212 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
214 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
227 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
235 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
236 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
237 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
238 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
239 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
240 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
252 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
253 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
254 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
255 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
256 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
257 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
258 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
259 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
260 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
261 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
262 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
263 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
264 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
265 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
266 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
267 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
268 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
269 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
270 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
271 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
272 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
273 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
274 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
275 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
276 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
277 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
278 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
279 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
280 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
281 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
282 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
283 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
284 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
285 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
286 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
287 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)},
288 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
289 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
290 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
291 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
292 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
293 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
294 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
295 {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */
299 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
301 static const struct {
302 const char string[ETH_GSTRING_LEN];
303 } ethtool_stats_keys[] = {
306 { "rx_ucast_packets" },
307 { "rx_mcast_packets" },
308 { "rx_bcast_packets" },
310 { "rx_align_errors" },
311 { "rx_xon_pause_rcvd" },
312 { "rx_xoff_pause_rcvd" },
313 { "rx_mac_ctrl_rcvd" },
314 { "rx_xoff_entered" },
315 { "rx_frame_too_long_errors" },
317 { "rx_undersize_packets" },
318 { "rx_in_length_errors" },
319 { "rx_out_length_errors" },
320 { "rx_64_or_less_octet_packets" },
321 { "rx_65_to_127_octet_packets" },
322 { "rx_128_to_255_octet_packets" },
323 { "rx_256_to_511_octet_packets" },
324 { "rx_512_to_1023_octet_packets" },
325 { "rx_1024_to_1522_octet_packets" },
326 { "rx_1523_to_2047_octet_packets" },
327 { "rx_2048_to_4095_octet_packets" },
328 { "rx_4096_to_8191_octet_packets" },
329 { "rx_8192_to_9022_octet_packets" },
336 { "tx_flow_control" },
338 { "tx_single_collisions" },
339 { "tx_mult_collisions" },
341 { "tx_excessive_collisions" },
342 { "tx_late_collisions" },
343 { "tx_collide_2times" },
344 { "tx_collide_3times" },
345 { "tx_collide_4times" },
346 { "tx_collide_5times" },
347 { "tx_collide_6times" },
348 { "tx_collide_7times" },
349 { "tx_collide_8times" },
350 { "tx_collide_9times" },
351 { "tx_collide_10times" },
352 { "tx_collide_11times" },
353 { "tx_collide_12times" },
354 { "tx_collide_13times" },
355 { "tx_collide_14times" },
356 { "tx_collide_15times" },
357 { "tx_ucast_packets" },
358 { "tx_mcast_packets" },
359 { "tx_bcast_packets" },
360 { "tx_carrier_sense_errors" },
364 { "dma_writeq_full" },
365 { "dma_write_prioq_full" },
369 { "rx_threshold_hit" },
371 { "dma_readq_full" },
372 { "dma_read_prioq_full" },
373 { "tx_comp_queue_full" },
375 { "ring_set_send_prod_index" },
376 { "ring_status_update" },
378 { "nic_avoided_irqs" },
379 { "nic_tx_threshold_hit" },
381 { "mbuf_lwm_thresh_hit" },
384 #define TG3_NUM_STATS ARRAY_SIZE(ethtool_stats_keys)
387 static const struct {
388 const char string[ETH_GSTRING_LEN];
389 } ethtool_test_keys[] = {
390 { "nvram test (online) " },
391 { "link test (online) " },
392 { "register test (offline)" },
393 { "memory test (offline)" },
394 { "loopback test (offline)" },
395 { "interrupt test (offline)" },
398 #define TG3_NUM_TEST ARRAY_SIZE(ethtool_test_keys)
401 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
403 writel(val, tp->regs + off);
406 static u32 tg3_read32(struct tg3 *tp, u32 off)
408 return readl(tp->regs + off);
411 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
413 writel(val, tp->aperegs + off);
416 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
418 return readl(tp->aperegs + off);
421 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
425 spin_lock_irqsave(&tp->indirect_lock, flags);
426 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
427 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
428 spin_unlock_irqrestore(&tp->indirect_lock, flags);
431 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
433 writel(val, tp->regs + off);
434 readl(tp->regs + off);
437 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
442 spin_lock_irqsave(&tp->indirect_lock, flags);
443 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
444 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
445 spin_unlock_irqrestore(&tp->indirect_lock, flags);
449 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
453 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
454 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
455 TG3_64BIT_REG_LOW, val);
458 if (off == TG3_RX_STD_PROD_IDX_REG) {
459 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
460 TG3_64BIT_REG_LOW, val);
464 spin_lock_irqsave(&tp->indirect_lock, flags);
465 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
466 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
467 spin_unlock_irqrestore(&tp->indirect_lock, flags);
469 /* In indirect mode when disabling interrupts, we also need
470 * to clear the interrupt bit in the GRC local ctrl register.
472 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
474 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
475 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
479 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
484 spin_lock_irqsave(&tp->indirect_lock, flags);
485 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
486 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
487 spin_unlock_irqrestore(&tp->indirect_lock, flags);
491 /* usec_wait specifies the wait time in usec when writing to certain registers
492 * where it is unsafe to read back the register without some delay.
493 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
494 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
496 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
498 if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND))
499 /* Non-posted methods */
500 tp->write32(tp, off, val);
503 tg3_write32(tp, off, val);
508 /* Wait again after the read for the posted method to guarantee that
509 * the wait time is met.
515 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
517 tp->write32_mbox(tp, off, val);
518 if (!tg3_flag(tp, MBOX_WRITE_REORDER) && !tg3_flag(tp, ICH_WORKAROUND))
519 tp->read32_mbox(tp, off);
522 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
524 void __iomem *mbox = tp->regs + off;
526 if (tg3_flag(tp, TXD_MBOX_HWBUG))
528 if (tg3_flag(tp, MBOX_WRITE_REORDER))
532 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
534 return readl(tp->regs + off + GRCMBOX_BASE);
537 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
539 writel(val, tp->regs + off + GRCMBOX_BASE);
542 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
543 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
544 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
545 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
546 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
548 #define tw32(reg, val) tp->write32(tp, reg, val)
549 #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
550 #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
551 #define tr32(reg) tp->read32(tp, reg)
553 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
557 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
558 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
561 spin_lock_irqsave(&tp->indirect_lock, flags);
562 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
563 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
564 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
566 /* Always leave this as zero. */
567 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
569 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
570 tw32_f(TG3PCI_MEM_WIN_DATA, val);
572 /* Always leave this as zero. */
573 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
575 spin_unlock_irqrestore(&tp->indirect_lock, flags);
578 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
582 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
583 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
588 spin_lock_irqsave(&tp->indirect_lock, flags);
589 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
590 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
591 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
593 /* Always leave this as zero. */
594 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
596 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
597 *val = tr32(TG3PCI_MEM_WIN_DATA);
599 /* Always leave this as zero. */
600 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
602 spin_unlock_irqrestore(&tp->indirect_lock, flags);
605 static void tg3_ape_lock_init(struct tg3 *tp)
610 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
611 regbase = TG3_APE_LOCK_GRANT;
613 regbase = TG3_APE_PER_LOCK_GRANT;
615 /* Make sure the driver hasn't any stale locks. */
616 for (i = 0; i < 8; i++)
617 tg3_ape_write32(tp, regbase + 4 * i, APE_LOCK_GRANT_DRIVER);
620 static int tg3_ape_lock(struct tg3 *tp, int locknum)
624 u32 status, req, gnt;
626 if (!tg3_flag(tp, ENABLE_APE))
630 case TG3_APE_LOCK_GRC:
631 case TG3_APE_LOCK_MEM:
637 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
638 req = TG3_APE_LOCK_REQ;
639 gnt = TG3_APE_LOCK_GRANT;
641 req = TG3_APE_PER_LOCK_REQ;
642 gnt = TG3_APE_PER_LOCK_GRANT;
647 tg3_ape_write32(tp, req + off, APE_LOCK_REQ_DRIVER);
649 /* Wait for up to 1 millisecond to acquire lock. */
650 for (i = 0; i < 100; i++) {
651 status = tg3_ape_read32(tp, gnt + off);
652 if (status == APE_LOCK_GRANT_DRIVER)
657 if (status != APE_LOCK_GRANT_DRIVER) {
658 /* Revoke the lock request. */
659 tg3_ape_write32(tp, gnt + off,
660 APE_LOCK_GRANT_DRIVER);
668 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
672 if (!tg3_flag(tp, ENABLE_APE))
676 case TG3_APE_LOCK_GRC:
677 case TG3_APE_LOCK_MEM:
683 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
684 gnt = TG3_APE_LOCK_GRANT;
686 gnt = TG3_APE_PER_LOCK_GRANT;
688 tg3_ape_write32(tp, gnt + 4 * locknum, APE_LOCK_GRANT_DRIVER);
691 static void tg3_disable_ints(struct tg3 *tp)
695 tw32(TG3PCI_MISC_HOST_CTRL,
696 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
697 for (i = 0; i < tp->irq_max; i++)
698 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
701 static void tg3_enable_ints(struct tg3 *tp)
708 tw32(TG3PCI_MISC_HOST_CTRL,
709 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
711 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
712 for (i = 0; i < tp->irq_cnt; i++) {
713 struct tg3_napi *tnapi = &tp->napi[i];
715 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
716 if (tg3_flag(tp, 1SHOT_MSI))
717 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
719 tp->coal_now |= tnapi->coal_now;
722 /* Force an initial interrupt */
723 if (!tg3_flag(tp, TAGGED_STATUS) &&
724 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
725 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
727 tw32(HOSTCC_MODE, tp->coal_now);
729 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
732 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
734 struct tg3 *tp = tnapi->tp;
735 struct tg3_hw_status *sblk = tnapi->hw_status;
736 unsigned int work_exists = 0;
738 /* check for phy events */
739 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
740 if (sblk->status & SD_STATUS_LINK_CHG)
743 /* check for RX/TX work to do */
744 if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
745 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
752 * similar to tg3_enable_ints, but it accurately determines whether there
753 * is new work pending and can return without flushing the PIO write
754 * which reenables interrupts
756 static void tg3_int_reenable(struct tg3_napi *tnapi)
758 struct tg3 *tp = tnapi->tp;
760 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
763 /* When doing tagged status, this work check is unnecessary.
764 * The last_tag we write above tells the chip which piece of
765 * work we've completed.
767 if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi))
768 tw32(HOSTCC_MODE, tp->coalesce_mode |
769 HOSTCC_MODE_ENABLE | tnapi->coal_now);
772 static void tg3_switch_clocks(struct tg3 *tp)
777 if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS))
780 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
782 orig_clock_ctrl = clock_ctrl;
783 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
784 CLOCK_CTRL_CLKRUN_OENABLE |
786 tp->pci_clock_ctrl = clock_ctrl;
788 if (tg3_flag(tp, 5705_PLUS)) {
789 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
790 tw32_wait_f(TG3PCI_CLOCK_CTRL,
791 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
793 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
794 tw32_wait_f(TG3PCI_CLOCK_CTRL,
796 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
798 tw32_wait_f(TG3PCI_CLOCK_CTRL,
799 clock_ctrl | (CLOCK_CTRL_ALTCLK),
802 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
805 #define PHY_BUSY_LOOPS 5000
807 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
813 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
815 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
821 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
822 MI_COM_PHY_ADDR_MASK);
823 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
824 MI_COM_REG_ADDR_MASK);
825 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
827 tw32_f(MAC_MI_COM, frame_val);
829 loops = PHY_BUSY_LOOPS;
832 frame_val = tr32(MAC_MI_COM);
834 if ((frame_val & MI_COM_BUSY) == 0) {
836 frame_val = tr32(MAC_MI_COM);
844 *val = frame_val & MI_COM_DATA_MASK;
848 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
849 tw32_f(MAC_MI_MODE, tp->mi_mode);
856 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
862 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
863 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
866 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
868 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
872 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
873 MI_COM_PHY_ADDR_MASK);
874 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
875 MI_COM_REG_ADDR_MASK);
876 frame_val |= (val & MI_COM_DATA_MASK);
877 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
879 tw32_f(MAC_MI_COM, frame_val);
881 loops = PHY_BUSY_LOOPS;
884 frame_val = tr32(MAC_MI_COM);
885 if ((frame_val & MI_COM_BUSY) == 0) {
887 frame_val = tr32(MAC_MI_COM);
897 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
898 tw32_f(MAC_MI_MODE, tp->mi_mode);
905 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
909 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
913 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
917 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
918 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
922 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
928 static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
932 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
936 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
940 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
941 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
945 err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
951 static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
955 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
957 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
962 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
966 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
968 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
973 static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val)
977 err = tg3_writephy(tp, MII_TG3_AUX_CTRL,
978 (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) |
979 MII_TG3_AUXCTL_SHDWSEL_MISC);
981 err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val);
986 static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)
988 if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC)
989 set |= MII_TG3_AUXCTL_MISC_WREN;
991 return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
994 #define TG3_PHY_AUXCTL_SMDSP_ENABLE(tp) \
995 tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \
996 MII_TG3_AUXCTL_ACTL_SMDSP_ENA | \
997 MII_TG3_AUXCTL_ACTL_TX_6DB)
999 #define TG3_PHY_AUXCTL_SMDSP_DISABLE(tp) \
1000 tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \
1001 MII_TG3_AUXCTL_ACTL_TX_6DB);
1003 static int tg3_bmcr_reset(struct tg3 *tp)
1008 /* OK, reset it, and poll the BMCR_RESET bit until it
1009 * clears or we time out.
1011 phy_control = BMCR_RESET;
1012 err = tg3_writephy(tp, MII_BMCR, phy_control);
1018 err = tg3_readphy(tp, MII_BMCR, &phy_control);
1022 if ((phy_control & BMCR_RESET) == 0) {
1034 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
1036 struct tg3 *tp = bp->priv;
1039 spin_lock_bh(&tp->lock);
1041 if (tg3_readphy(tp, reg, &val))
1044 spin_unlock_bh(&tp->lock);
1049 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
1051 struct tg3 *tp = bp->priv;
1054 spin_lock_bh(&tp->lock);
1056 if (tg3_writephy(tp, reg, val))
1059 spin_unlock_bh(&tp->lock);
1064 static int tg3_mdio_reset(struct mii_bus *bp)
1069 static void tg3_mdio_config_5785(struct tg3 *tp)
1072 struct phy_device *phydev;
1074 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1075 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1076 case PHY_ID_BCM50610:
1077 case PHY_ID_BCM50610M:
1078 val = MAC_PHYCFG2_50610_LED_MODES;
1080 case PHY_ID_BCMAC131:
1081 val = MAC_PHYCFG2_AC131_LED_MODES;
1083 case PHY_ID_RTL8211C:
1084 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
1086 case PHY_ID_RTL8201E:
1087 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
1093 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
1094 tw32(MAC_PHYCFG2, val);
1096 val = tr32(MAC_PHYCFG1);
1097 val &= ~(MAC_PHYCFG1_RGMII_INT |
1098 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
1099 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
1100 tw32(MAC_PHYCFG1, val);
1105 if (!tg3_flag(tp, RGMII_INBAND_DISABLE))
1106 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1107 MAC_PHYCFG2_FMODE_MASK_MASK |
1108 MAC_PHYCFG2_GMODE_MASK_MASK |
1109 MAC_PHYCFG2_ACT_MASK_MASK |
1110 MAC_PHYCFG2_QUAL_MASK_MASK |
1111 MAC_PHYCFG2_INBAND_ENABLE;
1113 tw32(MAC_PHYCFG2, val);
1115 val = tr32(MAC_PHYCFG1);
1116 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1117 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1118 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1119 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1120 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1121 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1122 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1124 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1125 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1126 tw32(MAC_PHYCFG1, val);
1128 val = tr32(MAC_EXT_RGMII_MODE);
1129 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1130 MAC_RGMII_MODE_RX_QUALITY |
1131 MAC_RGMII_MODE_RX_ACTIVITY |
1132 MAC_RGMII_MODE_RX_ENG_DET |
1133 MAC_RGMII_MODE_TX_ENABLE |
1134 MAC_RGMII_MODE_TX_LOWPWR |
1135 MAC_RGMII_MODE_TX_RESET);
1136 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1137 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1138 val |= MAC_RGMII_MODE_RX_INT_B |
1139 MAC_RGMII_MODE_RX_QUALITY |
1140 MAC_RGMII_MODE_RX_ACTIVITY |
1141 MAC_RGMII_MODE_RX_ENG_DET;
1142 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1143 val |= MAC_RGMII_MODE_TX_ENABLE |
1144 MAC_RGMII_MODE_TX_LOWPWR |
1145 MAC_RGMII_MODE_TX_RESET;
1147 tw32(MAC_EXT_RGMII_MODE, val);
1150 static void tg3_mdio_start(struct tg3 *tp)
1152 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1153 tw32_f(MAC_MI_MODE, tp->mi_mode);
1156 if (tg3_flag(tp, MDIOBUS_INITED) &&
1157 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1158 tg3_mdio_config_5785(tp);
1161 static int tg3_mdio_init(struct tg3 *tp)
1165 struct phy_device *phydev;
1167 if (tg3_flag(tp, 5717_PLUS)) {
1170 tp->phy_addr = PCI_FUNC(tp->pdev->devfn) + 1;
1172 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1173 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1175 is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1176 TG3_CPMU_PHY_STRAP_IS_SERDES;
1180 tp->phy_addr = TG3_PHY_MII_ADDR;
1184 if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED))
1187 tp->mdio_bus = mdiobus_alloc();
1188 if (tp->mdio_bus == NULL)
1191 tp->mdio_bus->name = "tg3 mdio bus";
1192 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1193 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1194 tp->mdio_bus->priv = tp;
1195 tp->mdio_bus->parent = &tp->pdev->dev;
1196 tp->mdio_bus->read = &tg3_mdio_read;
1197 tp->mdio_bus->write = &tg3_mdio_write;
1198 tp->mdio_bus->reset = &tg3_mdio_reset;
1199 tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1200 tp->mdio_bus->irq = &tp->mdio_irq[0];
1202 for (i = 0; i < PHY_MAX_ADDR; i++)
1203 tp->mdio_bus->irq[i] = PHY_POLL;
1205 /* The bus registration will look for all the PHYs on the mdio bus.
1206 * Unfortunately, it does not ensure the PHY is powered up before
1207 * accessing the PHY ID registers. A chip reset is the
1208 * quickest way to bring the device back to an operational state..
1210 if (tg3_readphy(tp, MII_BMCR, ®) || (reg & BMCR_PDOWN))
1213 i = mdiobus_register(tp->mdio_bus);
1215 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1216 mdiobus_free(tp->mdio_bus);
1220 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1222 if (!phydev || !phydev->drv) {
1223 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1224 mdiobus_unregister(tp->mdio_bus);
1225 mdiobus_free(tp->mdio_bus);
1229 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1230 case PHY_ID_BCM57780:
1231 phydev->interface = PHY_INTERFACE_MODE_GMII;
1232 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1234 case PHY_ID_BCM50610:
1235 case PHY_ID_BCM50610M:
1236 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1237 PHY_BRCM_RX_REFCLK_UNUSED |
1238 PHY_BRCM_DIS_TXCRXC_NOENRGY |
1239 PHY_BRCM_AUTO_PWRDWN_ENABLE;
1240 if (tg3_flag(tp, RGMII_INBAND_DISABLE))
1241 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1242 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1243 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1244 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1245 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1247 case PHY_ID_RTL8211C:
1248 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1250 case PHY_ID_RTL8201E:
1251 case PHY_ID_BCMAC131:
1252 phydev->interface = PHY_INTERFACE_MODE_MII;
1253 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1254 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1258 tg3_flag_set(tp, MDIOBUS_INITED);
1260 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1261 tg3_mdio_config_5785(tp);
1266 static void tg3_mdio_fini(struct tg3 *tp)
1268 if (tg3_flag(tp, MDIOBUS_INITED)) {
1269 tg3_flag_clear(tp, MDIOBUS_INITED);
1270 mdiobus_unregister(tp->mdio_bus);
1271 mdiobus_free(tp->mdio_bus);
1275 /* tp->lock is held. */
1276 static inline void tg3_generate_fw_event(struct tg3 *tp)
1280 val = tr32(GRC_RX_CPU_EVENT);
1281 val |= GRC_RX_CPU_DRIVER_EVENT;
1282 tw32_f(GRC_RX_CPU_EVENT, val);
1284 tp->last_event_jiffies = jiffies;
1287 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1289 /* tp->lock is held. */
1290 static void tg3_wait_for_event_ack(struct tg3 *tp)
1293 unsigned int delay_cnt;
1296 /* If enough time has passed, no wait is necessary. */
1297 time_remain = (long)(tp->last_event_jiffies + 1 +
1298 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1300 if (time_remain < 0)
1303 /* Check if we can shorten the wait time. */
1304 delay_cnt = jiffies_to_usecs(time_remain);
1305 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1306 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1307 delay_cnt = (delay_cnt >> 3) + 1;
1309 for (i = 0; i < delay_cnt; i++) {
1310 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1316 /* tp->lock is held. */
1317 static void tg3_ump_link_report(struct tg3 *tp)
1322 if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF))
1325 tg3_wait_for_event_ack(tp);
1327 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1329 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1332 if (!tg3_readphy(tp, MII_BMCR, ®))
1334 if (!tg3_readphy(tp, MII_BMSR, ®))
1335 val |= (reg & 0xffff);
1336 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1339 if (!tg3_readphy(tp, MII_ADVERTISE, ®))
1341 if (!tg3_readphy(tp, MII_LPA, ®))
1342 val |= (reg & 0xffff);
1343 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1346 if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1347 if (!tg3_readphy(tp, MII_CTRL1000, ®))
1349 if (!tg3_readphy(tp, MII_STAT1000, ®))
1350 val |= (reg & 0xffff);
1352 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1354 if (!tg3_readphy(tp, MII_PHYADDR, ®))
1358 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1360 tg3_generate_fw_event(tp);
1363 static void tg3_link_report(struct tg3 *tp)
1365 if (!netif_carrier_ok(tp->dev)) {
1366 netif_info(tp, link, tp->dev, "Link is down\n");
1367 tg3_ump_link_report(tp);
1368 } else if (netif_msg_link(tp)) {
1369 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1370 (tp->link_config.active_speed == SPEED_1000 ?
1372 (tp->link_config.active_speed == SPEED_100 ?
1374 (tp->link_config.active_duplex == DUPLEX_FULL ?
1377 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1378 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1380 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1383 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
1384 netdev_info(tp->dev, "EEE is %s\n",
1385 tp->setlpicnt ? "enabled" : "disabled");
1387 tg3_ump_link_report(tp);
1391 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1395 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1396 miireg = ADVERTISE_PAUSE_CAP;
1397 else if (flow_ctrl & FLOW_CTRL_TX)
1398 miireg = ADVERTISE_PAUSE_ASYM;
1399 else if (flow_ctrl & FLOW_CTRL_RX)
1400 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1407 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1411 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1412 miireg = ADVERTISE_1000XPAUSE;
1413 else if (flow_ctrl & FLOW_CTRL_TX)
1414 miireg = ADVERTISE_1000XPSE_ASYM;
1415 else if (flow_ctrl & FLOW_CTRL_RX)
1416 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1423 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1427 if (lcladv & ADVERTISE_1000XPAUSE) {
1428 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1429 if (rmtadv & LPA_1000XPAUSE)
1430 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1431 else if (rmtadv & LPA_1000XPAUSE_ASYM)
1434 if (rmtadv & LPA_1000XPAUSE)
1435 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1437 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1438 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1445 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1449 u32 old_rx_mode = tp->rx_mode;
1450 u32 old_tx_mode = tp->tx_mode;
1452 if (tg3_flag(tp, USE_PHYLIB))
1453 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1455 autoneg = tp->link_config.autoneg;
1457 if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) {
1458 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1459 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1461 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1463 flowctrl = tp->link_config.flowctrl;
1465 tp->link_config.active_flowctrl = flowctrl;
1467 if (flowctrl & FLOW_CTRL_RX)
1468 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1470 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1472 if (old_rx_mode != tp->rx_mode)
1473 tw32_f(MAC_RX_MODE, tp->rx_mode);
1475 if (flowctrl & FLOW_CTRL_TX)
1476 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1478 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1480 if (old_tx_mode != tp->tx_mode)
1481 tw32_f(MAC_TX_MODE, tp->tx_mode);
1484 static void tg3_adjust_link(struct net_device *dev)
1486 u8 oldflowctrl, linkmesg = 0;
1487 u32 mac_mode, lcl_adv, rmt_adv;
1488 struct tg3 *tp = netdev_priv(dev);
1489 struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1491 spin_lock_bh(&tp->lock);
1493 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1494 MAC_MODE_HALF_DUPLEX);
1496 oldflowctrl = tp->link_config.active_flowctrl;
1502 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1503 mac_mode |= MAC_MODE_PORT_MODE_MII;
1504 else if (phydev->speed == SPEED_1000 ||
1505 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1506 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1508 mac_mode |= MAC_MODE_PORT_MODE_MII;
1510 if (phydev->duplex == DUPLEX_HALF)
1511 mac_mode |= MAC_MODE_HALF_DUPLEX;
1513 lcl_adv = tg3_advert_flowctrl_1000T(
1514 tp->link_config.flowctrl);
1517 rmt_adv = LPA_PAUSE_CAP;
1518 if (phydev->asym_pause)
1519 rmt_adv |= LPA_PAUSE_ASYM;
1522 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1524 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1526 if (mac_mode != tp->mac_mode) {
1527 tp->mac_mode = mac_mode;
1528 tw32_f(MAC_MODE, tp->mac_mode);
1532 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1533 if (phydev->speed == SPEED_10)
1535 MAC_MI_STAT_10MBPS_MODE |
1536 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1538 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1541 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1542 tw32(MAC_TX_LENGTHS,
1543 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1544 (6 << TX_LENGTHS_IPG_SHIFT) |
1545 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1547 tw32(MAC_TX_LENGTHS,
1548 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1549 (6 << TX_LENGTHS_IPG_SHIFT) |
1550 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1552 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1553 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1554 phydev->speed != tp->link_config.active_speed ||
1555 phydev->duplex != tp->link_config.active_duplex ||
1556 oldflowctrl != tp->link_config.active_flowctrl)
1559 tp->link_config.active_speed = phydev->speed;
1560 tp->link_config.active_duplex = phydev->duplex;
1562 spin_unlock_bh(&tp->lock);
1565 tg3_link_report(tp);
1568 static int tg3_phy_init(struct tg3 *tp)
1570 struct phy_device *phydev;
1572 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
1575 /* Bring the PHY back to a known state. */
1578 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1580 /* Attach the MAC to the PHY. */
1581 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1582 phydev->dev_flags, phydev->interface);
1583 if (IS_ERR(phydev)) {
1584 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
1585 return PTR_ERR(phydev);
1588 /* Mask with MAC supported features. */
1589 switch (phydev->interface) {
1590 case PHY_INTERFACE_MODE_GMII:
1591 case PHY_INTERFACE_MODE_RGMII:
1592 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
1593 phydev->supported &= (PHY_GBIT_FEATURES |
1595 SUPPORTED_Asym_Pause);
1599 case PHY_INTERFACE_MODE_MII:
1600 phydev->supported &= (PHY_BASIC_FEATURES |
1602 SUPPORTED_Asym_Pause);
1605 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1609 tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
1611 phydev->advertising = phydev->supported;
1616 static void tg3_phy_start(struct tg3 *tp)
1618 struct phy_device *phydev;
1620 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1623 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1625 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
1626 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
1627 phydev->speed = tp->link_config.orig_speed;
1628 phydev->duplex = tp->link_config.orig_duplex;
1629 phydev->autoneg = tp->link_config.orig_autoneg;
1630 phydev->advertising = tp->link_config.orig_advertising;
1635 phy_start_aneg(phydev);
1638 static void tg3_phy_stop(struct tg3 *tp)
1640 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1643 phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1646 static void tg3_phy_fini(struct tg3 *tp)
1648 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
1649 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1650 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
1654 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1658 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1661 tg3_writephy(tp, MII_TG3_FET_TEST,
1662 phytest | MII_TG3_FET_SHADOW_EN);
1663 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1665 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1667 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1668 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1670 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1674 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1678 if (!tg3_flag(tp, 5705_PLUS) ||
1679 (tg3_flag(tp, 5717_PLUS) &&
1680 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
1683 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1684 tg3_phy_fet_toggle_apd(tp, enable);
1688 reg = MII_TG3_MISC_SHDW_WREN |
1689 MII_TG3_MISC_SHDW_SCR5_SEL |
1690 MII_TG3_MISC_SHDW_SCR5_LPED |
1691 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1692 MII_TG3_MISC_SHDW_SCR5_SDTL |
1693 MII_TG3_MISC_SHDW_SCR5_C125OE;
1694 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1695 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1697 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1700 reg = MII_TG3_MISC_SHDW_WREN |
1701 MII_TG3_MISC_SHDW_APD_SEL |
1702 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1704 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1706 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1709 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1713 if (!tg3_flag(tp, 5705_PLUS) ||
1714 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
1717 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1720 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1721 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1723 tg3_writephy(tp, MII_TG3_FET_TEST,
1724 ephy | MII_TG3_FET_SHADOW_EN);
1725 if (!tg3_readphy(tp, reg, &phy)) {
1727 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1729 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1730 tg3_writephy(tp, reg, phy);
1732 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1737 ret = tg3_phy_auxctl_read(tp,
1738 MII_TG3_AUXCTL_SHDWSEL_MISC, &phy);
1741 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1743 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1744 tg3_phy_auxctl_write(tp,
1745 MII_TG3_AUXCTL_SHDWSEL_MISC, phy);
1750 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1755 if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
1758 ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val);
1760 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC,
1761 val | MII_TG3_AUXCTL_MISC_WIRESPD_EN);
1764 static void tg3_phy_apply_otp(struct tg3 *tp)
1773 if (TG3_PHY_AUXCTL_SMDSP_ENABLE(tp))
1776 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1777 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1778 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1780 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1781 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1782 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1784 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1785 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1786 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1788 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1789 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1791 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1792 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1794 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1795 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1796 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1798 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
1801 static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up)
1805 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
1810 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
1811 current_link_up == 1 &&
1812 tp->link_config.active_duplex == DUPLEX_FULL &&
1813 (tp->link_config.active_speed == SPEED_100 ||
1814 tp->link_config.active_speed == SPEED_1000)) {
1817 if (tp->link_config.active_speed == SPEED_1000)
1818 eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
1820 eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
1822 tw32(TG3_CPMU_EEE_CTRL, eeectl);
1824 tg3_phy_cl45_read(tp, MDIO_MMD_AN,
1825 TG3_CL45_D7_EEERES_STAT, &val);
1827 if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
1828 val == TG3_CL45_D7_EEERES_STAT_LP_100TX)
1832 if (!tp->setlpicnt) {
1833 val = tr32(TG3_CPMU_EEE_MODE);
1834 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
1838 static void tg3_phy_eee_enable(struct tg3 *tp)
1842 if (tp->link_config.active_speed == SPEED_1000 &&
1843 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1844 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
1845 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
1846 !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
1847 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0003);
1848 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
1851 val = tr32(TG3_CPMU_EEE_MODE);
1852 tw32(TG3_CPMU_EEE_MODE, val | TG3_CPMU_EEEMD_LPI_ENABLE);
1855 static int tg3_wait_macro_done(struct tg3 *tp)
1862 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
1863 if ((tmp32 & 0x1000) == 0)
1873 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1875 static const u32 test_pat[4][6] = {
1876 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1877 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1878 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1879 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1883 for (chan = 0; chan < 4; chan++) {
1886 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1887 (chan * 0x2000) | 0x0200);
1888 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1890 for (i = 0; i < 6; i++)
1891 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1894 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1895 if (tg3_wait_macro_done(tp)) {
1900 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1901 (chan * 0x2000) | 0x0200);
1902 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
1903 if (tg3_wait_macro_done(tp)) {
1908 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
1909 if (tg3_wait_macro_done(tp)) {
1914 for (i = 0; i < 6; i += 2) {
1917 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1918 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1919 tg3_wait_macro_done(tp)) {
1925 if (low != test_pat[chan][i] ||
1926 high != test_pat[chan][i+1]) {
1927 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1928 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1929 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1939 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1943 for (chan = 0; chan < 4; chan++) {
1946 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1947 (chan * 0x2000) | 0x0200);
1948 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1949 for (i = 0; i < 6; i++)
1950 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1951 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1952 if (tg3_wait_macro_done(tp))
1959 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1961 u32 reg32, phy9_orig;
1962 int retries, do_phy_reset, err;
1968 err = tg3_bmcr_reset(tp);
1974 /* Disable transmitter and interrupt. */
1975 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32))
1979 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1981 /* Set full-duplex, 1000 mbps. */
1982 tg3_writephy(tp, MII_BMCR,
1983 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1985 /* Set to master mode. */
1986 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1989 tg3_writephy(tp, MII_TG3_CTRL,
1990 (MII_TG3_CTRL_AS_MASTER |
1991 MII_TG3_CTRL_ENABLE_AS_MASTER));
1993 err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp);
1997 /* Block the PHY control access. */
1998 tg3_phydsp_write(tp, 0x8005, 0x0800);
2000 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
2003 } while (--retries);
2005 err = tg3_phy_reset_chanpat(tp);
2009 tg3_phydsp_write(tp, 0x8005, 0x0000);
2011 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
2012 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
2014 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2016 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
2018 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) {
2020 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2027 /* This will reset the tigon3 PHY if there is no valid
2028 * link unless the FORCE argument is non-zero.
2030 static int tg3_phy_reset(struct tg3 *tp)
2035 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2036 val = tr32(GRC_MISC_CFG);
2037 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
2040 err = tg3_readphy(tp, MII_BMSR, &val);
2041 err |= tg3_readphy(tp, MII_BMSR, &val);
2045 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
2046 netif_carrier_off(tp->dev);
2047 tg3_link_report(tp);
2050 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2051 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2052 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
2053 err = tg3_phy_reset_5703_4_5(tp);
2060 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
2061 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
2062 cpmuctrl = tr32(TG3_CPMU_CTRL);
2063 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2065 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2068 err = tg3_bmcr_reset(tp);
2072 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
2073 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2074 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
2076 tw32(TG3_CPMU_CTRL, cpmuctrl);
2079 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2080 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2081 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2082 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2083 CPMU_LSPD_1000MB_MACCLK_12_5) {
2084 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2086 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2090 if (tg3_flag(tp, 5717_PLUS) &&
2091 (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
2094 tg3_phy_apply_otp(tp);
2096 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
2097 tg3_phy_toggle_apd(tp, true);
2099 tg3_phy_toggle_apd(tp, false);
2102 if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) &&
2103 !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2104 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2105 tg3_phydsp_write(tp, 0x000a, 0x0323);
2106 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2109 if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
2110 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2111 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2114 if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
2115 if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2116 tg3_phydsp_write(tp, 0x000a, 0x310b);
2117 tg3_phydsp_write(tp, 0x201f, 0x9506);
2118 tg3_phydsp_write(tp, 0x401f, 0x14e2);
2119 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2121 } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
2122 if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2123 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2124 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2125 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2126 tg3_writephy(tp, MII_TG3_TEST1,
2127 MII_TG3_TEST1_TRIM_EN | 0x4);
2129 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2131 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2135 /* Set Extended packet length bit (bit 14) on all chips that */
2136 /* support jumbo frames */
2137 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2138 /* Cannot do read-modify-write on 5401 */
2139 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
2140 } else if (tg3_flag(tp, JUMBO_CAPABLE)) {
2141 /* Set bit 14 with read-modify-write to preserve other bits */
2142 err = tg3_phy_auxctl_read(tp,
2143 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2145 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2146 val | MII_TG3_AUXCTL_ACTL_EXTPKTLEN);
2149 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2150 * jumbo frames transmission.
2152 if (tg3_flag(tp, JUMBO_CAPABLE)) {
2153 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
2154 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2155 val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2158 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2159 /* adjust output voltage */
2160 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2163 tg3_phy_toggle_automdix(tp, 1);
2164 tg3_phy_set_wirespeed(tp);
2168 static void tg3_frob_aux_power(struct tg3 *tp)
2170 bool need_vaux = false;
2172 /* The GPIOs do something completely different on 57765. */
2173 if (!tg3_flag(tp, IS_NIC) ||
2174 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2175 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2178 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2179 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2180 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2181 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) &&
2182 tp->pdev_peer != tp->pdev) {
2183 struct net_device *dev_peer;
2185 dev_peer = pci_get_drvdata(tp->pdev_peer);
2187 /* remove_one() may have been run on the peer. */
2189 struct tg3 *tp_peer = netdev_priv(dev_peer);
2191 if (tg3_flag(tp_peer, INIT_COMPLETE))
2194 if (tg3_flag(tp_peer, WOL_ENABLE) ||
2195 tg3_flag(tp_peer, ENABLE_ASF))
2200 if (tg3_flag(tp, WOL_ENABLE) || tg3_flag(tp, ENABLE_ASF))
2204 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2205 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2206 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2207 (GRC_LCLCTRL_GPIO_OE0 |
2208 GRC_LCLCTRL_GPIO_OE1 |
2209 GRC_LCLCTRL_GPIO_OE2 |
2210 GRC_LCLCTRL_GPIO_OUTPUT0 |
2211 GRC_LCLCTRL_GPIO_OUTPUT1),
2213 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2214 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2215 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2216 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2217 GRC_LCLCTRL_GPIO_OE1 |
2218 GRC_LCLCTRL_GPIO_OE2 |
2219 GRC_LCLCTRL_GPIO_OUTPUT0 |
2220 GRC_LCLCTRL_GPIO_OUTPUT1 |
2222 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2224 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2225 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2227 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2228 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2231 u32 grc_local_ctrl = 0;
2233 /* Workaround to prevent overdrawing Amps. */
2234 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2236 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2237 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2238 grc_local_ctrl, 100);
2241 /* On 5753 and variants, GPIO2 cannot be used. */
2242 no_gpio2 = tp->nic_sram_data_cfg &
2243 NIC_SRAM_DATA_CFG_NO_GPIO2;
2245 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2246 GRC_LCLCTRL_GPIO_OE1 |
2247 GRC_LCLCTRL_GPIO_OE2 |
2248 GRC_LCLCTRL_GPIO_OUTPUT1 |
2249 GRC_LCLCTRL_GPIO_OUTPUT2;
2251 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2252 GRC_LCLCTRL_GPIO_OUTPUT2);
2254 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2255 grc_local_ctrl, 100);
2257 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2259 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2260 grc_local_ctrl, 100);
2263 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2264 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2265 grc_local_ctrl, 100);
2269 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2270 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2271 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2272 (GRC_LCLCTRL_GPIO_OE1 |
2273 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2275 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2276 GRC_LCLCTRL_GPIO_OE1, 100);
2278 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2279 (GRC_LCLCTRL_GPIO_OE1 |
2280 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2285 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2287 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2289 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2290 if (speed != SPEED_10)
2292 } else if (speed == SPEED_10)
2298 static int tg3_setup_phy(struct tg3 *, int);
2300 #define RESET_KIND_SHUTDOWN 0
2301 #define RESET_KIND_INIT 1
2302 #define RESET_KIND_SUSPEND 2
2304 static void tg3_write_sig_post_reset(struct tg3 *, int);
2305 static int tg3_halt_cpu(struct tg3 *, u32);
2307 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2311 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
2312 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2313 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2314 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2317 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2318 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2319 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2324 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2326 val = tr32(GRC_MISC_CFG);
2327 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2330 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2332 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2335 tg3_writephy(tp, MII_ADVERTISE, 0);
2336 tg3_writephy(tp, MII_BMCR,
2337 BMCR_ANENABLE | BMCR_ANRESTART);
2339 tg3_writephy(tp, MII_TG3_FET_TEST,
2340 phytest | MII_TG3_FET_SHADOW_EN);
2341 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2342 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2344 MII_TG3_FET_SHDW_AUXMODE4,
2347 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2350 } else if (do_low_power) {
2351 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2352 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2354 val = MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2355 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2356 MII_TG3_AUXCTL_PCTL_VREG_11V;
2357 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val);
2360 /* The PHY should not be powered down on some chips because
2363 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2364 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2365 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2366 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2369 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2370 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2371 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2372 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2373 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2374 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2377 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2380 /* tp->lock is held. */
2381 static int tg3_nvram_lock(struct tg3 *tp)
2383 if (tg3_flag(tp, NVRAM)) {
2386 if (tp->nvram_lock_cnt == 0) {
2387 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2388 for (i = 0; i < 8000; i++) {
2389 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2394 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2398 tp->nvram_lock_cnt++;
2403 /* tp->lock is held. */
2404 static void tg3_nvram_unlock(struct tg3 *tp)
2406 if (tg3_flag(tp, NVRAM)) {
2407 if (tp->nvram_lock_cnt > 0)
2408 tp->nvram_lock_cnt--;
2409 if (tp->nvram_lock_cnt == 0)
2410 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2414 /* tp->lock is held. */
2415 static void tg3_enable_nvram_access(struct tg3 *tp)
2417 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
2418 u32 nvaccess = tr32(NVRAM_ACCESS);
2420 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2424 /* tp->lock is held. */
2425 static void tg3_disable_nvram_access(struct tg3 *tp)
2427 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
2428 u32 nvaccess = tr32(NVRAM_ACCESS);
2430 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2434 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2435 u32 offset, u32 *val)
2440 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2443 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2444 EEPROM_ADDR_DEVID_MASK |
2446 tw32(GRC_EEPROM_ADDR,
2448 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2449 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2450 EEPROM_ADDR_ADDR_MASK) |
2451 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2453 for (i = 0; i < 1000; i++) {
2454 tmp = tr32(GRC_EEPROM_ADDR);
2456 if (tmp & EEPROM_ADDR_COMPLETE)
2460 if (!(tmp & EEPROM_ADDR_COMPLETE))
2463 tmp = tr32(GRC_EEPROM_DATA);
2466 * The data will always be opposite the native endian
2467 * format. Perform a blind byteswap to compensate.
2474 #define NVRAM_CMD_TIMEOUT 10000
2476 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2480 tw32(NVRAM_CMD, nvram_cmd);
2481 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2483 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2489 if (i == NVRAM_CMD_TIMEOUT)
2495 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2497 if (tg3_flag(tp, NVRAM) &&
2498 tg3_flag(tp, NVRAM_BUFFERED) &&
2499 tg3_flag(tp, FLASH) &&
2500 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
2501 (tp->nvram_jedecnum == JEDEC_ATMEL))
2503 addr = ((addr / tp->nvram_pagesize) <<
2504 ATMEL_AT45DB0X1B_PAGE_POS) +
2505 (addr % tp->nvram_pagesize);
2510 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2512 if (tg3_flag(tp, NVRAM) &&
2513 tg3_flag(tp, NVRAM_BUFFERED) &&
2514 tg3_flag(tp, FLASH) &&
2515 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
2516 (tp->nvram_jedecnum == JEDEC_ATMEL))
2518 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2519 tp->nvram_pagesize) +
2520 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2525 /* NOTE: Data read in from NVRAM is byteswapped according to
2526 * the byteswapping settings for all other register accesses.
2527 * tg3 devices are BE devices, so on a BE machine, the data
2528 * returned will be exactly as it is seen in NVRAM. On a LE
2529 * machine, the 32-bit value will be byteswapped.
2531 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2535 if (!tg3_flag(tp, NVRAM))
2536 return tg3_nvram_read_using_eeprom(tp, offset, val);
2538 offset = tg3_nvram_phys_addr(tp, offset);
2540 if (offset > NVRAM_ADDR_MSK)
2543 ret = tg3_nvram_lock(tp);
2547 tg3_enable_nvram_access(tp);
2549 tw32(NVRAM_ADDR, offset);
2550 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2551 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2554 *val = tr32(NVRAM_RDDATA);
2556 tg3_disable_nvram_access(tp);
2558 tg3_nvram_unlock(tp);
2563 /* Ensures NVRAM data is in bytestream format. */
2564 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2567 int res = tg3_nvram_read(tp, offset, &v);
2569 *val = cpu_to_be32(v);
2573 /* tp->lock is held. */
2574 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2576 u32 addr_high, addr_low;
2579 addr_high = ((tp->dev->dev_addr[0] << 8) |
2580 tp->dev->dev_addr[1]);
2581 addr_low = ((tp->dev->dev_addr[2] << 24) |
2582 (tp->dev->dev_addr[3] << 16) |
2583 (tp->dev->dev_addr[4] << 8) |
2584 (tp->dev->dev_addr[5] << 0));
2585 for (i = 0; i < 4; i++) {
2586 if (i == 1 && skip_mac_1)
2588 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2589 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2592 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2593 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2594 for (i = 0; i < 12; i++) {
2595 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2596 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2600 addr_high = (tp->dev->dev_addr[0] +
2601 tp->dev->dev_addr[1] +
2602 tp->dev->dev_addr[2] +
2603 tp->dev->dev_addr[3] +
2604 tp->dev->dev_addr[4] +
2605 tp->dev->dev_addr[5]) &
2606 TX_BACKOFF_SEED_MASK;
2607 tw32(MAC_TX_BACKOFF_SEED, addr_high);
2610 static void tg3_enable_register_access(struct tg3 *tp)
2613 * Make sure register accesses (indirect or otherwise) will function
2616 pci_write_config_dword(tp->pdev,
2617 TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
2620 static int tg3_power_up(struct tg3 *tp)
2622 tg3_enable_register_access(tp);
2624 pci_set_power_state(tp->pdev, PCI_D0);
2626 /* Switch out of Vaux if it is a NIC */
2627 if (tg3_flag(tp, IS_NIC))
2628 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2633 static int tg3_power_down_prepare(struct tg3 *tp)
2636 bool device_should_wake, do_low_power;
2638 tg3_enable_register_access(tp);
2640 /* Restore the CLKREQ setting. */
2641 if (tg3_flag(tp, CLKREQ_BUG)) {
2644 pci_read_config_word(tp->pdev,
2645 tp->pcie_cap + PCI_EXP_LNKCTL,
2647 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2648 pci_write_config_word(tp->pdev,
2649 tp->pcie_cap + PCI_EXP_LNKCTL,
2653 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2654 tw32(TG3PCI_MISC_HOST_CTRL,
2655 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2657 device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
2658 tg3_flag(tp, WOL_ENABLE);
2660 if (tg3_flag(tp, USE_PHYLIB)) {
2661 do_low_power = false;
2662 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
2663 !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2664 struct phy_device *phydev;
2665 u32 phyid, advertising;
2667 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2669 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2671 tp->link_config.orig_speed = phydev->speed;
2672 tp->link_config.orig_duplex = phydev->duplex;
2673 tp->link_config.orig_autoneg = phydev->autoneg;
2674 tp->link_config.orig_advertising = phydev->advertising;
2676 advertising = ADVERTISED_TP |
2678 ADVERTISED_Autoneg |
2679 ADVERTISED_10baseT_Half;
2681 if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) {
2682 if (tg3_flag(tp, WOL_SPEED_100MB))
2684 ADVERTISED_100baseT_Half |
2685 ADVERTISED_100baseT_Full |
2686 ADVERTISED_10baseT_Full;
2688 advertising |= ADVERTISED_10baseT_Full;
2691 phydev->advertising = advertising;
2693 phy_start_aneg(phydev);
2695 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2696 if (phyid != PHY_ID_BCMAC131) {
2697 phyid &= PHY_BCM_OUI_MASK;
2698 if (phyid == PHY_BCM_OUI_1 ||
2699 phyid == PHY_BCM_OUI_2 ||
2700 phyid == PHY_BCM_OUI_3)
2701 do_low_power = true;
2705 do_low_power = true;
2707 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2708 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2709 tp->link_config.orig_speed = tp->link_config.speed;
2710 tp->link_config.orig_duplex = tp->link_config.duplex;
2711 tp->link_config.orig_autoneg = tp->link_config.autoneg;
2714 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
2715 tp->link_config.speed = SPEED_10;
2716 tp->link_config.duplex = DUPLEX_HALF;
2717 tp->link_config.autoneg = AUTONEG_ENABLE;
2718 tg3_setup_phy(tp, 0);
2722 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2725 val = tr32(GRC_VCPU_EXT_CTRL);
2726 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2727 } else if (!tg3_flag(tp, ENABLE_ASF)) {
2731 for (i = 0; i < 200; i++) {
2732 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2733 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2738 if (tg3_flag(tp, WOL_CAP))
2739 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2740 WOL_DRV_STATE_SHUTDOWN |
2744 if (device_should_wake) {
2747 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
2749 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
2750 tg3_phy_auxctl_write(tp,
2751 MII_TG3_AUXCTL_SHDWSEL_PWRCTL,
2752 MII_TG3_AUXCTL_PCTL_WOL_EN |
2753 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2754 MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC);
2758 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
2759 mac_mode = MAC_MODE_PORT_MODE_GMII;
2761 mac_mode = MAC_MODE_PORT_MODE_MII;
2763 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2764 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2766 u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ?
2767 SPEED_100 : SPEED_10;
2768 if (tg3_5700_link_polarity(tp, speed))
2769 mac_mode |= MAC_MODE_LINK_POLARITY;
2771 mac_mode &= ~MAC_MODE_LINK_POLARITY;
2774 mac_mode = MAC_MODE_PORT_MODE_TBI;
2777 if (!tg3_flag(tp, 5750_PLUS))
2778 tw32(MAC_LED_CTRL, tp->led_ctrl);
2780 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2781 if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) &&
2782 (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)))
2783 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2785 if (tg3_flag(tp, ENABLE_APE))
2786 mac_mode |= MAC_MODE_APE_TX_EN |
2787 MAC_MODE_APE_RX_EN |
2788 MAC_MODE_TDE_ENABLE;
2790 tw32_f(MAC_MODE, mac_mode);
2793 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2797 if (!tg3_flag(tp, WOL_SPEED_100MB) &&
2798 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2799 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2802 base_val = tp->pci_clock_ctrl;
2803 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2804 CLOCK_CTRL_TXCLK_DISABLE);
2806 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2807 CLOCK_CTRL_PWRDOWN_PLL133, 40);
2808 } else if (tg3_flag(tp, 5780_CLASS) ||
2809 tg3_flag(tp, CPMU_PRESENT) ||
2810 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2812 } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) {
2813 u32 newbits1, newbits2;
2815 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2816 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2817 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2818 CLOCK_CTRL_TXCLK_DISABLE |
2820 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2821 } else if (tg3_flag(tp, 5705_PLUS)) {
2822 newbits1 = CLOCK_CTRL_625_CORE;
2823 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2825 newbits1 = CLOCK_CTRL_ALTCLK;
2826 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2829 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2832 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2835 if (!tg3_flag(tp, 5705_PLUS)) {
2838 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2839 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2840 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2841 CLOCK_CTRL_TXCLK_DISABLE |
2842 CLOCK_CTRL_44MHZ_CORE);
2844 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2847 tw32_wait_f(TG3PCI_CLOCK_CTRL,
2848 tp->pci_clock_ctrl | newbits3, 40);
2852 if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF))
2853 tg3_power_down_phy(tp, do_low_power);
2855 tg3_frob_aux_power(tp);
2857 /* Workaround for unstable PLL clock */
2858 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2859 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2860 u32 val = tr32(0x7d00);
2862 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2864 if (!tg3_flag(tp, ENABLE_ASF)) {
2867 err = tg3_nvram_lock(tp);
2868 tg3_halt_cpu(tp, RX_CPU_BASE);
2870 tg3_nvram_unlock(tp);
2874 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2879 static void tg3_power_down(struct tg3 *tp)
2881 tg3_power_down_prepare(tp);
2883 pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE));
2884 pci_set_power_state(tp->pdev, PCI_D3hot);
2887 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2889 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2890 case MII_TG3_AUX_STAT_10HALF:
2892 *duplex = DUPLEX_HALF;
2895 case MII_TG3_AUX_STAT_10FULL:
2897 *duplex = DUPLEX_FULL;
2900 case MII_TG3_AUX_STAT_100HALF:
2902 *duplex = DUPLEX_HALF;
2905 case MII_TG3_AUX_STAT_100FULL:
2907 *duplex = DUPLEX_FULL;
2910 case MII_TG3_AUX_STAT_1000HALF:
2911 *speed = SPEED_1000;
2912 *duplex = DUPLEX_HALF;
2915 case MII_TG3_AUX_STAT_1000FULL:
2916 *speed = SPEED_1000;
2917 *duplex = DUPLEX_FULL;
2921 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2922 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2924 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2928 *speed = SPEED_INVALID;
2929 *duplex = DUPLEX_INVALID;
2934 static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl)
2939 new_adv = ADVERTISE_CSMA;
2940 if (advertise & ADVERTISED_10baseT_Half)
2941 new_adv |= ADVERTISE_10HALF;
2942 if (advertise & ADVERTISED_10baseT_Full)
2943 new_adv |= ADVERTISE_10FULL;
2944 if (advertise & ADVERTISED_100baseT_Half)
2945 new_adv |= ADVERTISE_100HALF;
2946 if (advertise & ADVERTISED_100baseT_Full)
2947 new_adv |= ADVERTISE_100FULL;
2949 new_adv |= tg3_advert_flowctrl_1000T(flowctrl);
2951 err = tg3_writephy(tp, MII_ADVERTISE, new_adv);
2955 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
2959 if (advertise & ADVERTISED_1000baseT_Half)
2960 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2961 if (advertise & ADVERTISED_1000baseT_Full)
2962 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2964 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2965 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2966 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2967 MII_TG3_CTRL_ENABLE_AS_MASTER);
2969 err = tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2973 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2976 tw32(TG3_CPMU_EEE_MODE,
2977 tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2979 err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp);
2983 switch (GET_ASIC_REV(tp->pci_chip_rev_id)) {
2985 case ASIC_REV_57765:
2986 if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
2987 tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
2988 MII_TG3_DSP_CH34TP2_HIBW01);
2991 val = MII_TG3_DSP_TAP26_ALNOKO |
2992 MII_TG3_DSP_TAP26_RMRXSTO |
2993 MII_TG3_DSP_TAP26_OPCSINPT;
2994 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
2998 /* Advertise 100-BaseTX EEE ability */
2999 if (advertise & ADVERTISED_100baseT_Full)
3000 val |= MDIO_AN_EEE_ADV_100TX;
3001 /* Advertise 1000-BaseT EEE ability */
3002 if (advertise & ADVERTISED_1000baseT_Full)
3003 val |= MDIO_AN_EEE_ADV_1000T;
3004 err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
3006 err2 = TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
3015 static void tg3_phy_copper_begin(struct tg3 *tp)
3020 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
3021 new_adv = ADVERTISED_10baseT_Half |
3022 ADVERTISED_10baseT_Full;
3023 if (tg3_flag(tp, WOL_SPEED_100MB))
3024 new_adv |= ADVERTISED_100baseT_Half |
3025 ADVERTISED_100baseT_Full;
3027 tg3_phy_autoneg_cfg(tp, new_adv,
3028 FLOW_CTRL_TX | FLOW_CTRL_RX);
3029 } else if (tp->link_config.speed == SPEED_INVALID) {
3030 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
3031 tp->link_config.advertising &=
3032 ~(ADVERTISED_1000baseT_Half |
3033 ADVERTISED_1000baseT_Full);
3035 tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
3036 tp->link_config.flowctrl);
3038 /* Asking for a specific link mode. */
3039 if (tp->link_config.speed == SPEED_1000) {
3040 if (tp->link_config.duplex == DUPLEX_FULL)
3041 new_adv = ADVERTISED_1000baseT_Full;
3043 new_adv = ADVERTISED_1000baseT_Half;
3044 } else if (tp->link_config.speed == SPEED_100) {
3045 if (tp->link_config.duplex == DUPLEX_FULL)
3046 new_adv = ADVERTISED_100baseT_Full;
3048 new_adv = ADVERTISED_100baseT_Half;
3050 if (tp->link_config.duplex == DUPLEX_FULL)
3051 new_adv = ADVERTISED_10baseT_Full;
3053 new_adv = ADVERTISED_10baseT_Half;
3056 tg3_phy_autoneg_cfg(tp, new_adv,
3057 tp->link_config.flowctrl);
3060 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
3061 tp->link_config.speed != SPEED_INVALID) {
3062 u32 bmcr, orig_bmcr;
3064 tp->link_config.active_speed = tp->link_config.speed;
3065 tp->link_config.active_duplex = tp->link_config.duplex;
3068 switch (tp->link_config.speed) {
3074 bmcr |= BMCR_SPEED100;
3078 bmcr |= TG3_BMCR_SPEED1000;
3082 if (tp->link_config.duplex == DUPLEX_FULL)
3083 bmcr |= BMCR_FULLDPLX;
3085 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
3086 (bmcr != orig_bmcr)) {
3087 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
3088 for (i = 0; i < 1500; i++) {
3092 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
3093 tg3_readphy(tp, MII_BMSR, &tmp))
3095 if (!(tmp & BMSR_LSTATUS)) {
3100 tg3_writephy(tp, MII_BMCR, bmcr);
3104 tg3_writephy(tp, MII_BMCR,
3105 BMCR_ANENABLE | BMCR_ANRESTART);
3109 static int tg3_init_5401phy_dsp(struct tg3 *tp)
3113 /* Turn off tap power management. */
3114 /* Set Extended packet length bit */
3115 err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
3117 err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
3118 err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
3119 err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
3120 err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
3121 err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
3128 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
3130 u32 adv_reg, all_mask = 0;
3132 if (mask & ADVERTISED_10baseT_Half)
3133 all_mask |= ADVERTISE_10HALF;
3134 if (mask & ADVERTISED_10baseT_Full)
3135 all_mask |= ADVERTISE_10FULL;
3136 if (mask & ADVERTISED_100baseT_Half)
3137 all_mask |= ADVERTISE_100HALF;
3138 if (mask & ADVERTISED_100baseT_Full)
3139 all_mask |= ADVERTISE_100FULL;
3141 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
3144 if ((adv_reg & all_mask) != all_mask)
3146 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
3150 if (mask & ADVERTISED_1000baseT_Half)
3151 all_mask |= ADVERTISE_1000HALF;
3152 if (mask & ADVERTISED_1000baseT_Full)
3153 all_mask |= ADVERTISE_1000FULL;
3155 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
3158 if ((tg3_ctrl & all_mask) != all_mask)
3164 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
3168 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3171 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3172 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3174 if (tp->link_config.active_duplex == DUPLEX_FULL) {
3175 if (curadv != reqadv)
3178 if (tg3_flag(tp, PAUSE_AUTONEG))
3179 tg3_readphy(tp, MII_LPA, rmtadv);
3181 /* Reprogram the advertisement register, even if it
3182 * does not affect the current link. If the link
3183 * gets renegotiated in the future, we can save an
3184 * additional renegotiation cycle by advertising
3185 * it correctly in the first place.
3187 if (curadv != reqadv) {
3188 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3189 ADVERTISE_PAUSE_ASYM);
3190 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3197 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3199 int current_link_up;
3201 u32 lcl_adv, rmt_adv;
3209 (MAC_STATUS_SYNC_CHANGED |
3210 MAC_STATUS_CFG_CHANGED |
3211 MAC_STATUS_MI_COMPLETION |
3212 MAC_STATUS_LNKSTATE_CHANGED));
3215 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3217 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3221 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0);
3223 /* Some third-party PHYs need to be reset on link going
3226 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3227 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3228 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3229 netif_carrier_ok(tp->dev)) {
3230 tg3_readphy(tp, MII_BMSR, &bmsr);
3231 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3232 !(bmsr & BMSR_LSTATUS))
3238 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
3239 tg3_readphy(tp, MII_BMSR, &bmsr);
3240 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3241 !tg3_flag(tp, INIT_COMPLETE))
3244 if (!(bmsr & BMSR_LSTATUS)) {
3245 err = tg3_init_5401phy_dsp(tp);
3249 tg3_readphy(tp, MII_BMSR, &bmsr);
3250 for (i = 0; i < 1000; i++) {
3252 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3253 (bmsr & BMSR_LSTATUS)) {
3259 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
3260 TG3_PHY_REV_BCM5401_B0 &&
3261 !(bmsr & BMSR_LSTATUS) &&
3262 tp->link_config.active_speed == SPEED_1000) {
3263 err = tg3_phy_reset(tp);
3265 err = tg3_init_5401phy_dsp(tp);
3270 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3271 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3272 /* 5701 {A0,B0} CRC bug workaround */
3273 tg3_writephy(tp, 0x15, 0x0a75);
3274 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3275 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
3276 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3279 /* Clear pending interrupts... */
3280 tg3_readphy(tp, MII_TG3_ISTAT, &val);
3281 tg3_readphy(tp, MII_TG3_ISTAT, &val);
3283 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
3284 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3285 else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
3286 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3288 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3289 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3290 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3291 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3292 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3294 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3297 current_link_up = 0;
3298 current_speed = SPEED_INVALID;
3299 current_duplex = DUPLEX_INVALID;
3301 if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
3302 err = tg3_phy_auxctl_read(tp,
3303 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
3305 if (!err && !(val & (1 << 10))) {
3306 tg3_phy_auxctl_write(tp,
3307 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
3314 for (i = 0; i < 100; i++) {
3315 tg3_readphy(tp, MII_BMSR, &bmsr);
3316 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3317 (bmsr & BMSR_LSTATUS))
3322 if (bmsr & BMSR_LSTATUS) {
3325 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3326 for (i = 0; i < 2000; i++) {
3328 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3333 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3338 for (i = 0; i < 200; i++) {
3339 tg3_readphy(tp, MII_BMCR, &bmcr);
3340 if (tg3_readphy(tp, MII_BMCR, &bmcr))
3342 if (bmcr && bmcr != 0x7fff)
3350 tp->link_config.active_speed = current_speed;
3351 tp->link_config.active_duplex = current_duplex;
3353 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3354 if ((bmcr & BMCR_ANENABLE) &&
3355 tg3_copper_is_advertising_all(tp,
3356 tp->link_config.advertising)) {
3357 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3359 current_link_up = 1;
3362 if (!(bmcr & BMCR_ANENABLE) &&
3363 tp->link_config.speed == current_speed &&
3364 tp->link_config.duplex == current_duplex &&
3365 tp->link_config.flowctrl ==
3366 tp->link_config.active_flowctrl) {
3367 current_link_up = 1;
3371 if (current_link_up == 1 &&
3372 tp->link_config.active_duplex == DUPLEX_FULL)
3373 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3377 if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
3378 tg3_phy_copper_begin(tp);
3380 tg3_readphy(tp, MII_BMSR, &bmsr);
3381 if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||
3382 (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
3383 current_link_up = 1;
3386 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3387 if (current_link_up == 1) {
3388 if (tp->link_config.active_speed == SPEED_100 ||
3389 tp->link_config.active_speed == SPEED_10)
3390 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3392 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3393 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
3394 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3396 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3398 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3399 if (tp->link_config.active_duplex == DUPLEX_HALF)
3400 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3402 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3403 if (current_link_up == 1 &&
3404 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3405 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3407 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3410 /* ??? Without this setting Netgear GA302T PHY does not
3411 * ??? send/receive packets...
3413 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
3414 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3415 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3416 tw32_f(MAC_MI_MODE, tp->mi_mode);
3420 tw32_f(MAC_MODE, tp->mac_mode);
3423 tg3_phy_eee_adjust(tp, current_link_up);
3425 if (tg3_flag(tp, USE_LINKCHG_REG)) {
3426 /* Polled via timer. */
3427 tw32_f(MAC_EVENT, 0);
3429 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3433 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3434 current_link_up == 1 &&
3435 tp->link_config.active_speed == SPEED_1000 &&
3436 (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) {
3439 (MAC_STATUS_SYNC_CHANGED |
3440 MAC_STATUS_CFG_CHANGED));
3443 NIC_SRAM_FIRMWARE_MBOX,
3444 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3447 /* Prevent send BD corruption. */
3448 if (tg3_flag(tp, CLKREQ_BUG)) {
3449 u16 oldlnkctl, newlnkctl;
3451 pci_read_config_word(tp->pdev,
3452 tp->pcie_cap + PCI_EXP_LNKCTL,
3454 if (tp->link_config.active_speed == SPEED_100 ||
3455 tp->link_config.active_speed == SPEED_10)
3456 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3458 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3459 if (newlnkctl != oldlnkctl)
3460 pci_write_config_word(tp->pdev,
3461 tp->pcie_cap + PCI_EXP_LNKCTL,
3465 if (current_link_up != netif_carrier_ok(tp->dev)) {
3466 if (current_link_up)
3467 netif_carrier_on(tp->dev);
3469 netif_carrier_off(tp->dev);
3470 tg3_link_report(tp);
3476 struct tg3_fiber_aneginfo {
3478 #define ANEG_STATE_UNKNOWN 0
3479 #define ANEG_STATE_AN_ENABLE 1
3480 #define ANEG_STATE_RESTART_INIT 2
3481 #define ANEG_STATE_RESTART 3
3482 #define ANEG_STATE_DISABLE_LINK_OK 4
3483 #define ANEG_STATE_ABILITY_DETECT_INIT 5
3484 #define ANEG_STATE_ABILITY_DETECT 6
3485 #define ANEG_STATE_ACK_DETECT_INIT 7
3486 #define ANEG_STATE_ACK_DETECT 8
3487 #define ANEG_STATE_COMPLETE_ACK_INIT 9
3488 #define ANEG_STATE_COMPLETE_ACK 10
3489 #define ANEG_STATE_IDLE_DETECT_INIT 11
3490 #define ANEG_STATE_IDLE_DETECT 12
3491 #define ANEG_STATE_LINK_OK 13
3492 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3493 #define ANEG_STATE_NEXT_PAGE_WAIT 15
3496 #define MR_AN_ENABLE 0x00000001
3497 #define MR_RESTART_AN 0x00000002
3498 #define MR_AN_COMPLETE 0x00000004
3499 #define MR_PAGE_RX 0x00000008
3500 #define MR_NP_LOADED 0x00000010
3501 #define MR_TOGGLE_TX 0x00000020
3502 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
3503 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
3504 #define MR_LP_ADV_SYM_PAUSE 0x00000100
3505 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
3506 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3507 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3508 #define MR_LP_ADV_NEXT_PAGE 0x00001000
3509 #define MR_TOGGLE_RX 0x00002000
3510 #define MR_NP_RX 0x00004000
3512 #define MR_LINK_OK 0x80000000
3514 unsigned long link_time, cur_time;
3516 u32 ability_match_cfg;
3517 int ability_match_count;
3519 char ability_match, idle_match, ack_match;
3521 u32 txconfig, rxconfig;
3522 #define ANEG_CFG_NP 0x00000080
3523 #define ANEG_CFG_ACK 0x00000040
3524 #define ANEG_CFG_RF2 0x00000020
3525 #define ANEG_CFG_RF1 0x00000010
3526 #define ANEG_CFG_PS2 0x00000001
3527 #define ANEG_CFG_PS1 0x00008000
3528 #define ANEG_CFG_HD 0x00004000
3529 #define ANEG_CFG_FD 0x00002000
3530 #define ANEG_CFG_INVAL 0x00001f06
3535 #define ANEG_TIMER_ENAB 2
3536 #define ANEG_FAILED -1
3538 #define ANEG_STATE_SETTLE_TIME 10000
3540 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3541 struct tg3_fiber_aneginfo *ap)
3544 unsigned long delta;
3548 if (ap->state == ANEG_STATE_UNKNOWN) {
3552 ap->ability_match_cfg = 0;
3553 ap->ability_match_count = 0;
3554 ap->ability_match = 0;
3560 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3561 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3563 if (rx_cfg_reg != ap->ability_match_cfg) {
3564 ap->ability_match_cfg = rx_cfg_reg;
3565 ap->ability_match = 0;
3566 ap->ability_match_count = 0;
3568 if (++ap->ability_match_count > 1) {
3569 ap->ability_match = 1;
3570 ap->ability_match_cfg = rx_cfg_reg;
3573 if (rx_cfg_reg & ANEG_CFG_ACK)
3581 ap->ability_match_cfg = 0;
3582 ap->ability_match_count = 0;
3583 ap->ability_match = 0;
3589 ap->rxconfig = rx_cfg_reg;
3592 switch (ap->state) {
3593 case ANEG_STATE_UNKNOWN:
3594 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3595 ap->state = ANEG_STATE_AN_ENABLE;
3598 case ANEG_STATE_AN_ENABLE:
3599 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3600 if (ap->flags & MR_AN_ENABLE) {
3603 ap->ability_match_cfg = 0;
3604 ap->ability_match_count = 0;
3605 ap->ability_match = 0;
3609 ap->state = ANEG_STATE_RESTART_INIT;
3611 ap->state = ANEG_STATE_DISABLE_LINK_OK;
3615 case ANEG_STATE_RESTART_INIT:
3616 ap->link_time = ap->cur_time;
3617 ap->flags &= ~(MR_NP_LOADED);
3619 tw32(MAC_TX_AUTO_NEG, 0);
3620 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3621 tw32_f(MAC_MODE, tp->mac_mode);
3624 ret = ANEG_TIMER_ENAB;
3625 ap->state = ANEG_STATE_RESTART;
3628 case ANEG_STATE_RESTART:
3629 delta = ap->cur_time - ap->link_time;
3630 if (delta > ANEG_STATE_SETTLE_TIME)
3631 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3633 ret = ANEG_TIMER_ENAB;
3636 case ANEG_STATE_DISABLE_LINK_OK:
3640 case ANEG_STATE_ABILITY_DETECT_INIT:
3641 ap->flags &= ~(MR_TOGGLE_TX);
3642 ap->txconfig = ANEG_CFG_FD;
3643 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3644 if (flowctrl & ADVERTISE_1000XPAUSE)
3645 ap->txconfig |= ANEG_CFG_PS1;
3646 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3647 ap->txconfig |= ANEG_CFG_PS2;
3648 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3649 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3650 tw32_f(MAC_MODE, tp->mac_mode);
3653 ap->state = ANEG_STATE_ABILITY_DETECT;
3656 case ANEG_STATE_ABILITY_DETECT:
3657 if (ap->ability_match != 0 && ap->rxconfig != 0)
3658 ap->state = ANEG_STATE_ACK_DETECT_INIT;
3661 case ANEG_STATE_ACK_DETECT_INIT:
3662 ap->txconfig |= ANEG_CFG_ACK;
3663 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3664 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3665 tw32_f(MAC_MODE, tp->mac_mode);
3668 ap->state = ANEG_STATE_ACK_DETECT;
3671 case ANEG_STATE_ACK_DETECT:
3672 if (ap->ack_match != 0) {
3673 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3674 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3675 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3677 ap->state = ANEG_STATE_AN_ENABLE;
3679 } else if (ap->ability_match != 0 &&
3680 ap->rxconfig == 0) {
3681 ap->state = ANEG_STATE_AN_ENABLE;
3685 case ANEG_STATE_COMPLETE_ACK_INIT:
3686 if (ap->rxconfig & ANEG_CFG_INVAL) {
3690 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3691 MR_LP_ADV_HALF_DUPLEX |
3692 MR_LP_ADV_SYM_PAUSE |
3693 MR_LP_ADV_ASYM_PAUSE |
3694 MR_LP_ADV_REMOTE_FAULT1 |
3695 MR_LP_ADV_REMOTE_FAULT2 |
3696 MR_LP_ADV_NEXT_PAGE |
3699 if (ap->rxconfig & ANEG_CFG_FD)
3700 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3701 if (ap->rxconfig & ANEG_CFG_HD)
3702 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3703 if (ap->rxconfig & ANEG_CFG_PS1)
3704 ap->flags |= MR_LP_ADV_SYM_PAUSE;
3705 if (ap->rxconfig & ANEG_CFG_PS2)
3706 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3707 if (ap->rxconfig & ANEG_CFG_RF1)
3708 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3709 if (ap->rxconfig & ANEG_CFG_RF2)
3710 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3711 if (ap->rxconfig & ANEG_CFG_NP)
3712 ap->flags |= MR_LP_ADV_NEXT_PAGE;
3714 ap->link_time = ap->cur_time;
3716 ap->flags ^= (MR_TOGGLE_TX);
3717 if (ap->rxconfig & 0x0008)
3718 ap->flags |= MR_TOGGLE_RX;
3719 if (ap->rxconfig & ANEG_CFG_NP)
3720 ap->flags |= MR_NP_RX;
3721 ap->flags |= MR_PAGE_RX;
3723 ap->state = ANEG_STATE_COMPLETE_ACK;
3724 ret = ANEG_TIMER_ENAB;
3727 case ANEG_STATE_COMPLETE_ACK:
3728 if (ap->ability_match != 0 &&
3729 ap->rxconfig == 0) {
3730 ap->state = ANEG_STATE_AN_ENABLE;
3733 delta = ap->cur_time - ap->link_time;
3734 if (delta > ANEG_STATE_SETTLE_TIME) {
3735 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3736 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3738 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3739 !(ap->flags & MR_NP_RX)) {
3740 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3748 case ANEG_STATE_IDLE_DETECT_INIT:
3749 ap->link_time = ap->cur_time;
3750 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3751 tw32_f(MAC_MODE, tp->mac_mode);
3754 ap->state = ANEG_STATE_IDLE_DETECT;
3755 ret = ANEG_TIMER_ENAB;
3758 case ANEG_STATE_IDLE_DETECT:
3759 if (ap->ability_match != 0 &&
3760 ap->rxconfig == 0) {
3761 ap->state = ANEG_STATE_AN_ENABLE;
3764 delta = ap->cur_time - ap->link_time;
3765 if (delta > ANEG_STATE_SETTLE_TIME) {
3766 /* XXX another gem from the Broadcom driver :( */
3767 ap->state = ANEG_STATE_LINK_OK;
3771 case ANEG_STATE_LINK_OK:
3772 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3776 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3777 /* ??? unimplemented */
3780 case ANEG_STATE_NEXT_PAGE_WAIT:
3781 /* ??? unimplemented */
3792 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3795 struct tg3_fiber_aneginfo aninfo;
3796 int status = ANEG_FAILED;
3800 tw32_f(MAC_TX_AUTO_NEG, 0);
3802 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3803 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3806 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3809 memset(&aninfo, 0, sizeof(aninfo));
3810 aninfo.flags |= MR_AN_ENABLE;
3811 aninfo.state = ANEG_STATE_UNKNOWN;
3812 aninfo.cur_time = 0;
3814 while (++tick < 195000) {
3815 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3816 if (status == ANEG_DONE || status == ANEG_FAILED)
3822 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3823 tw32_f(MAC_MODE, tp->mac_mode);
3826 *txflags = aninfo.txconfig;
3827 *rxflags = aninfo.flags;
3829 if (status == ANEG_DONE &&
3830 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3831 MR_LP_ADV_FULL_DUPLEX)))
3837 static void tg3_init_bcm8002(struct tg3 *tp)
3839 u32 mac_status = tr32(MAC_STATUS);
3842 /* Reset when initting first time or we have a link. */
3843 if (tg3_flag(tp, INIT_COMPLETE) &&
3844 !(mac_status & MAC_STATUS_PCS_SYNCED))
3847 /* Set PLL lock range. */
3848 tg3_writephy(tp, 0x16, 0x8007);
3851 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3853 /* Wait for reset to complete. */
3854 /* XXX schedule_timeout() ... */
3855 for (i = 0; i < 500; i++)
3858 /* Config mode; select PMA/Ch 1 regs. */
3859 tg3_writephy(tp, 0x10, 0x8411);
3861 /* Enable auto-lock and comdet, select txclk for tx. */
3862 tg3_writephy(tp, 0x11, 0x0a10);
3864 tg3_writephy(tp, 0x18, 0x00a0);
3865 tg3_writephy(tp, 0x16, 0x41ff);
3867 /* Assert and deassert POR. */
3868 tg3_writephy(tp, 0x13, 0x0400);
3870 tg3_writephy(tp, 0x13, 0x0000);
3872 tg3_writephy(tp, 0x11, 0x0a50);
3874 tg3_writephy(tp, 0x11, 0x0a10);
3876 /* Wait for signal to stabilize */
3877 /* XXX schedule_timeout() ... */
3878 for (i = 0; i < 15000; i++)
3881 /* Deselect the channel register so we can read the PHYID
3884 tg3_writephy(tp, 0x10, 0x8011);
3887 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3890 u32 sg_dig_ctrl, sg_dig_status;
3891 u32 serdes_cfg, expected_sg_dig_ctrl;
3892 int workaround, port_a;
3893 int current_link_up;
3896 expected_sg_dig_ctrl = 0;
3899 current_link_up = 0;
3901 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3902 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3904 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3907 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3908 /* preserve bits 20-23 for voltage regulator */
3909 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3912 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3914 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3915 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3917 u32 val = serdes_cfg;
3923 tw32_f(MAC_SERDES_CFG, val);
3926 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3928 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3929 tg3_setup_flow_control(tp, 0, 0);
3930 current_link_up = 1;
3935 /* Want auto-negotiation. */
3936 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3938 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3939 if (flowctrl & ADVERTISE_1000XPAUSE)
3940 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3941 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3942 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3944 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3945 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
3946 tp->serdes_counter &&
3947 ((mac_status & (MAC_STATUS_PCS_SYNCED |
3948 MAC_STATUS_RCVD_CFG)) ==
3949 MAC_STATUS_PCS_SYNCED)) {
3950 tp->serdes_counter--;
3951 current_link_up = 1;
3956 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3957 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3959 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3961 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3962 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3963 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3964 MAC_STATUS_SIGNAL_DET)) {
3965 sg_dig_status = tr32(SG_DIG_STATUS);
3966 mac_status = tr32(MAC_STATUS);
3968 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3969 (mac_status & MAC_STATUS_PCS_SYNCED)) {
3970 u32 local_adv = 0, remote_adv = 0;
3972 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3973 local_adv |= ADVERTISE_1000XPAUSE;
3974 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3975 local_adv |= ADVERTISE_1000XPSE_ASYM;
3977 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3978 remote_adv |= LPA_1000XPAUSE;
3979 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3980 remote_adv |= LPA_1000XPAUSE_ASYM;
3982 tg3_setup_flow_control(tp, local_adv, remote_adv);
3983 current_link_up = 1;
3984 tp->serdes_counter = 0;
3985 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3986 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3987 if (tp->serdes_counter)
3988 tp->serdes_counter--;
3991 u32 val = serdes_cfg;
3998 tw32_f(MAC_SERDES_CFG, val);
4001 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
4004 /* Link parallel detection - link is up */
4005 /* only if we have PCS_SYNC and not */
4006 /* receiving config code words */
4007 mac_status = tr32(MAC_STATUS);
4008 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
4009 !(mac_status & MAC_STATUS_RCVD_CFG)) {
4010 tg3_setup_flow_control(tp, 0, 0);
4011 current_link_up = 1;
4013 TG3_PHYFLG_PARALLEL_DETECT;
4014 tp->serdes_counter =
4015 SERDES_PARALLEL_DET_TIMEOUT;
4017 goto restart_autoneg;
4021 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
4022 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4026 return current_link_up;
4029 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
4031 int current_link_up = 0;
4033 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
4036 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4037 u32 txflags, rxflags;
4040 if (fiber_autoneg(tp, &txflags, &rxflags)) {
4041 u32 local_adv = 0, remote_adv = 0;
4043 if (txflags & ANEG_CFG_PS1)
4044 local_adv |= ADVERTISE_1000XPAUSE;
4045 if (txflags & ANEG_CFG_PS2)
4046 local_adv |= ADVERTISE_1000XPSE_ASYM;
4048 if (rxflags & MR_LP_ADV_SYM_PAUSE)
4049 remote_adv |= LPA_1000XPAUSE;
4050 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
4051 remote_adv |= LPA_1000XPAUSE_ASYM;
4053 tg3_setup_flow_control(tp, local_adv, remote_adv);
4055 current_link_up = 1;
4057 for (i = 0; i < 30; i++) {
4060 (MAC_STATUS_SYNC_CHANGED |
4061 MAC_STATUS_CFG_CHANGED));
4063 if ((tr32(MAC_STATUS) &
4064 (MAC_STATUS_SYNC_CHANGED |
4065 MAC_STATUS_CFG_CHANGED)) == 0)
4069 mac_status = tr32(MAC_STATUS);
4070 if (current_link_up == 0 &&
4071 (mac_status & MAC_STATUS_PCS_SYNCED) &&
4072 !(mac_status & MAC_STATUS_RCVD_CFG))
4073 current_link_up = 1;
4075 tg3_setup_flow_control(tp, 0, 0);
4077 /* Forcing 1000FD link up. */
4078 current_link_up = 1;
4080 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
4083 tw32_f(MAC_MODE, tp->mac_mode);
4088 return current_link_up;
4091 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
4094 u16 orig_active_speed;
4095 u8 orig_active_duplex;
4097 int current_link_up;
4100 orig_pause_cfg = tp->link_config.active_flowctrl;
4101 orig_active_speed = tp->link_config.active_speed;
4102 orig_active_duplex = tp->link_config.active_duplex;
4104 if (!tg3_flag(tp, HW_AUTONEG) &&
4105 netif_carrier_ok(tp->dev) &&
4106 tg3_flag(tp, INIT_COMPLETE)) {
4107 mac_status = tr32(MAC_STATUS);
4108 mac_status &= (MAC_STATUS_PCS_SYNCED |
4109 MAC_STATUS_SIGNAL_DET |
4110 MAC_STATUS_CFG_CHANGED |
4111 MAC_STATUS_RCVD_CFG);
4112 if (mac_status == (MAC_STATUS_PCS_SYNCED |
4113 MAC_STATUS_SIGNAL_DET)) {
4114 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4115 MAC_STATUS_CFG_CHANGED));
4120 tw32_f(MAC_TX_AUTO_NEG, 0);
4122 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
4123 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
4124 tw32_f(MAC_MODE, tp->mac_mode);
4127 if (tp->phy_id == TG3_PHY_ID_BCM8002)
4128 tg3_init_bcm8002(tp);
4130 /* Enable link change event even when serdes polling. */
4131 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4134 current_link_up = 0;
4135 mac_status = tr32(MAC_STATUS);
4137 if (tg3_flag(tp, HW_AUTONEG))
4138 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
4140 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
4142 tp->napi[0].hw_status->status =
4143 (SD_STATUS_UPDATED |
4144 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
4146 for (i = 0; i < 100; i++) {
4147 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4148 MAC_STATUS_CFG_CHANGED));
4150 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
4151 MAC_STATUS_CFG_CHANGED |
4152 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
4156 mac_status = tr32(MAC_STATUS);
4157 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
4158 current_link_up = 0;
4159 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
4160 tp->serdes_counter == 0) {
4161 tw32_f(MAC_MODE, (tp->mac_mode |
4162 MAC_MODE_SEND_CONFIGS));
4164 tw32_f(MAC_MODE, tp->mac_mode);
4168 if (current_link_up == 1) {
4169 tp->link_config.active_speed = SPEED_1000;
4170 tp->link_config.active_duplex = DUPLEX_FULL;
4171 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4172 LED_CTRL_LNKLED_OVERRIDE |
4173 LED_CTRL_1000MBPS_ON));
4175 tp->link_config.active_speed = SPEED_INVALID;
4176 tp->link_config.active_duplex = DUPLEX_INVALID;
4177 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4178 LED_CTRL_LNKLED_OVERRIDE |
4179 LED_CTRL_TRAFFIC_OVERRIDE));
4182 if (current_link_up != netif_carrier_ok(tp->dev)) {
4183 if (current_link_up)
4184 netif_carrier_on(tp->dev);
4186 netif_carrier_off(tp->dev);
4187 tg3_link_report(tp);
4189 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4190 if (orig_pause_cfg != now_pause_cfg ||
4191 orig_active_speed != tp->link_config.active_speed ||
4192 orig_active_duplex != tp->link_config.active_duplex)
4193 tg3_link_report(tp);
4199 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4201 int current_link_up, err = 0;
4205 u32 local_adv, remote_adv;
4207 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4208 tw32_f(MAC_MODE, tp->mac_mode);
4214 (MAC_STATUS_SYNC_CHANGED |
4215 MAC_STATUS_CFG_CHANGED |
4216 MAC_STATUS_MI_COMPLETION |
4217 MAC_STATUS_LNKSTATE_CHANGED));
4223 current_link_up = 0;
4224 current_speed = SPEED_INVALID;
4225 current_duplex = DUPLEX_INVALID;
4227 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4228 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4229 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4230 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4231 bmsr |= BMSR_LSTATUS;
4233 bmsr &= ~BMSR_LSTATUS;
4236 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4238 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4239 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4240 /* do nothing, just check for link up at the end */
4241 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4244 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4245 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4246 ADVERTISE_1000XPAUSE |
4247 ADVERTISE_1000XPSE_ASYM |
4250 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4252 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4253 new_adv |= ADVERTISE_1000XHALF;
4254 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4255 new_adv |= ADVERTISE_1000XFULL;
4257 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4258 tg3_writephy(tp, MII_ADVERTISE, new_adv);
4259 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4260 tg3_writephy(tp, MII_BMCR, bmcr);
4262 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4263 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4264 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4271 bmcr &= ~BMCR_SPEED1000;
4272 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4274 if (tp->link_config.duplex == DUPLEX_FULL)
4275 new_bmcr |= BMCR_FULLDPLX;
4277 if (new_bmcr != bmcr) {
4278 /* BMCR_SPEED1000 is a reserved bit that needs
4279 * to be set on write.
4281 new_bmcr |= BMCR_SPEED1000;
4283 /* Force a linkdown */
4284 if (netif_carrier_ok(tp->dev)) {
4287 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4288 adv &= ~(ADVERTISE_1000XFULL |
4289 ADVERTISE_1000XHALF |
4291 tg3_writephy(tp, MII_ADVERTISE, adv);
4292 tg3_writephy(tp, MII_BMCR, bmcr |
4296 netif_carrier_off(tp->dev);
4298 tg3_writephy(tp, MII_BMCR, new_bmcr);
4300 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4301 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4302 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4304 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4305 bmsr |= BMSR_LSTATUS;
4307 bmsr &= ~BMSR_LSTATUS;
4309 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4313 if (bmsr & BMSR_LSTATUS) {
4314 current_speed = SPEED_1000;
4315 current_link_up = 1;
4316 if (bmcr & BMCR_FULLDPLX)
4317 current_duplex = DUPLEX_FULL;
4319 current_duplex = DUPLEX_HALF;
4324 if (bmcr & BMCR_ANENABLE) {
4327 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4328 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4329 common = local_adv & remote_adv;
4330 if (common & (ADVERTISE_1000XHALF |
4331 ADVERTISE_1000XFULL)) {
4332 if (common & ADVERTISE_1000XFULL)
4333 current_duplex = DUPLEX_FULL;
4335 current_duplex = DUPLEX_HALF;
4336 } else if (!tg3_flag(tp, 5780_CLASS)) {
4337 /* Link is up via parallel detect */
4339 current_link_up = 0;
4344 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4345 tg3_setup_flow_control(tp, local_adv, remote_adv);
4347 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4348 if (tp->link_config.active_duplex == DUPLEX_HALF)
4349 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4351 tw32_f(MAC_MODE, tp->mac_mode);
4354 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4356 tp->link_config.active_speed = current_speed;
4357 tp->link_config.active_duplex = current_duplex;
4359 if (current_link_up != netif_carrier_ok(tp->dev)) {
4360 if (current_link_up)
4361 netif_carrier_on(tp->dev);
4363 netif_carrier_off(tp->dev);
4364 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4366 tg3_link_report(tp);
4371 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4373 if (tp->serdes_counter) {
4374 /* Give autoneg time to complete. */
4375 tp->serdes_counter--;
4379 if (!netif_carrier_ok(tp->dev) &&
4380 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4383 tg3_readphy(tp, MII_BMCR, &bmcr);
4384 if (bmcr & BMCR_ANENABLE) {
4387 /* Select shadow register 0x1f */
4388 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
4389 tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
4391 /* Select expansion interrupt status register */
4392 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4393 MII_TG3_DSP_EXP1_INT_STAT);
4394 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4395 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4397 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4398 /* We have signal detect and not receiving
4399 * config code words, link is up by parallel
4403 bmcr &= ~BMCR_ANENABLE;
4404 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4405 tg3_writephy(tp, MII_BMCR, bmcr);
4406 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
4409 } else if (netif_carrier_ok(tp->dev) &&
4410 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4411 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4414 /* Select expansion interrupt status register */
4415 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4416 MII_TG3_DSP_EXP1_INT_STAT);
4417 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4421 /* Config code words received, turn on autoneg. */
4422 tg3_readphy(tp, MII_BMCR, &bmcr);
4423 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4425 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4431 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4436 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
4437 err = tg3_setup_fiber_phy(tp, force_reset);
4438 else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4439 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4441 err = tg3_setup_copper_phy(tp, force_reset);
4443 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4446 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4447 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4449 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4454 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4455 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4456 tw32(GRC_MISC_CFG, val);
4459 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4460 (6 << TX_LENGTHS_IPG_SHIFT);
4461 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
4462 val |= tr32(MAC_TX_LENGTHS) &
4463 (TX_LENGTHS_JMB_FRM_LEN_MSK |
4464 TX_LENGTHS_CNT_DWN_VAL_MSK);
4466 if (tp->link_config.active_speed == SPEED_1000 &&
4467 tp->link_config.active_duplex == DUPLEX_HALF)
4468 tw32(MAC_TX_LENGTHS, val |
4469 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT));
4471 tw32(MAC_TX_LENGTHS, val |
4472 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
4474 if (!tg3_flag(tp, 5705_PLUS)) {
4475 if (netif_carrier_ok(tp->dev)) {
4476 tw32(HOSTCC_STAT_COAL_TICKS,
4477 tp->coal.stats_block_coalesce_usecs);
4479 tw32(HOSTCC_STAT_COAL_TICKS, 0);
4483 if (tg3_flag(tp, ASPM_WORKAROUND)) {
4484 val = tr32(PCIE_PWR_MGMT_THRESH);
4485 if (!netif_carrier_ok(tp->dev))
4486 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4489 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4490 tw32(PCIE_PWR_MGMT_THRESH, val);
4496 static inline int tg3_irq_sync(struct tg3 *tp)
4498 return tp->irq_sync;
4501 static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len)
4505 dst = (u32 *)((u8 *)dst + off);
4506 for (i = 0; i < len; i += sizeof(u32))
4507 *dst++ = tr32(off + i);
4510 static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs)
4512 tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0);
4513 tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200);
4514 tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0);
4515 tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0);
4516 tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04);
4517 tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80);
4518 tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48);
4519 tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04);
4520 tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20);
4521 tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c);
4522 tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c);
4523 tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c);
4524 tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44);
4525 tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04);
4526 tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20);
4527 tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14);
4528 tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08);
4529 tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08);
4530 tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100);
4532 if (tg3_flag(tp, SUPPORT_MSIX))
4533 tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180);
4535 tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10);
4536 tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58);
4537 tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08);
4538 tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08);
4539 tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04);
4540 tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04);
4541 tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04);
4542 tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04);
4544 if (!tg3_flag(tp, 5705_PLUS)) {
4545 tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04);
4546 tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04);
4547 tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04);
4550 tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110);
4551 tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120);
4552 tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c);
4553 tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04);
4554 tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c);
4556 if (tg3_flag(tp, NVRAM))
4557 tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24);
4560 static void tg3_dump_state(struct tg3 *tp)
4565 regs = kzalloc(TG3_REG_BLK_SIZE, GFP_ATOMIC);
4567 netdev_err(tp->dev, "Failed allocating register dump buffer\n");
4571 if (tg3_flag(tp, PCI_EXPRESS)) {
4572 /* Read up to but not including private PCI registers */
4573 for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32))
4574 regs[i / sizeof(u32)] = tr32(i);
4576 tg3_dump_legacy_regs(tp, regs);
4578 for (i = 0; i < TG3_REG_BLK_SIZE / sizeof(u32); i += 4) {
4579 if (!regs[i + 0] && !regs[i + 1] &&
4580 !regs[i + 2] && !regs[i + 3])
4583 netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
4585 regs[i + 0], regs[i + 1], regs[i + 2], regs[i + 3]);
4590 for (i = 0; i < tp->irq_cnt; i++) {
4591 struct tg3_napi *tnapi = &tp->napi[i];
4593 /* SW status block */
4595 "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
4597 tnapi->hw_status->status,
4598 tnapi->hw_status->status_tag,
4599 tnapi->hw_status->rx_jumbo_consumer,
4600 tnapi->hw_status->rx_consumer,
4601 tnapi->hw_status->rx_mini_consumer,
4602 tnapi->hw_status->idx[0].rx_producer,
4603 tnapi->hw_status->idx[0].tx_consumer);
4606 "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n",
4608 tnapi->last_tag, tnapi->last_irq_tag,
4609 tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending,
4611 tnapi->prodring.rx_std_prod_idx,
4612 tnapi->prodring.rx_std_cons_idx,
4613 tnapi->prodring.rx_jmb_prod_idx,
4614 tnapi->prodring.rx_jmb_cons_idx);
4618 /* This is called whenever we suspect that the system chipset is re-
4619 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4620 * is bogus tx completions. We try to recover by setting the
4621 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4624 static void tg3_tx_recover(struct tg3 *tp)
4626 BUG_ON(tg3_flag(tp, MBOX_WRITE_REORDER) ||
4627 tp->write32_tx_mbox == tg3_write_indirect_mbox);
4629 netdev_warn(tp->dev,
4630 "The system may be re-ordering memory-mapped I/O "
4631 "cycles to the network device, attempting to recover. "
4632 "Please report the problem to the driver maintainer "
4633 "and include system chipset information.\n");
4635 spin_lock(&tp->lock);
4636 tg3_flag_set(tp, TX_RECOVERY_PENDING);
4637 spin_unlock(&tp->lock);
4640 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4642 /* Tell compiler to fetch tx indices from memory. */
4644 return tnapi->tx_pending -
4645 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4648 /* Tigon3 never reports partial packet sends. So we do not
4649 * need special logic to handle SKBs that have not had all
4650 * of their frags sent yet, like SunGEM does.
4652 static void tg3_tx(struct tg3_napi *tnapi)
4654 struct tg3 *tp = tnapi->tp;
4655 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4656 u32 sw_idx = tnapi->tx_cons;
4657 struct netdev_queue *txq;
4658 int index = tnapi - tp->napi;
4660 if (tg3_flag(tp, ENABLE_TSS))
4663 txq = netdev_get_tx_queue(tp->dev, index);
4665 while (sw_idx != hw_idx) {
4666 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
4667 struct sk_buff *skb = ri->skb;
4670 if (unlikely(skb == NULL)) {
4675 pci_unmap_single(tp->pdev,
4676 dma_unmap_addr(ri, mapping),
4682 sw_idx = NEXT_TX(sw_idx);
4684 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4685 ri = &tnapi->tx_buffers[sw_idx];
4686 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4689 pci_unmap_page(tp->pdev,
4690 dma_unmap_addr(ri, mapping),
4691 skb_shinfo(skb)->frags[i].size,
4693 sw_idx = NEXT_TX(sw_idx);
4698 if (unlikely(tx_bug)) {
4704 tnapi->tx_cons = sw_idx;
4706 /* Need to make the tx_cons update visible to tg3_start_xmit()
4707 * before checking for netif_queue_stopped(). Without the
4708 * memory barrier, there is a small possibility that tg3_start_xmit()
4709 * will miss it and cause the queue to be stopped forever.
4713 if (unlikely(netif_tx_queue_stopped(txq) &&
4714 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4715 __netif_tx_lock(txq, smp_processor_id());
4716 if (netif_tx_queue_stopped(txq) &&
4717 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4718 netif_tx_wake_queue(txq);
4719 __netif_tx_unlock(txq);
4723 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4728 pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
4729 map_sz, PCI_DMA_FROMDEVICE);
4730 dev_kfree_skb_any(ri->skb);
4734 /* Returns size of skb allocated or < 0 on error.
4736 * We only need to fill in the address because the other members
4737 * of the RX descriptor are invariant, see tg3_init_rings.
4739 * Note the purposeful assymetry of cpu vs. chip accesses. For
4740 * posting buffers we only dirty the first cache line of the RX
4741 * descriptor (containing the address). Whereas for the RX status
4742 * buffers the cpu only reads the last cacheline of the RX descriptor
4743 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4745 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4746 u32 opaque_key, u32 dest_idx_unmasked)
4748 struct tg3_rx_buffer_desc *desc;
4749 struct ring_info *map;
4750 struct sk_buff *skb;
4752 int skb_size, dest_idx;
4754 switch (opaque_key) {
4755 case RXD_OPAQUE_RING_STD:
4756 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
4757 desc = &tpr->rx_std[dest_idx];
4758 map = &tpr->rx_std_buffers[dest_idx];
4759 skb_size = tp->rx_pkt_map_sz;
4762 case RXD_OPAQUE_RING_JUMBO:
4763 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
4764 desc = &tpr->rx_jmb[dest_idx].std;
4765 map = &tpr->rx_jmb_buffers[dest_idx];
4766 skb_size = TG3_RX_JMB_MAP_SZ;
4773 /* Do not overwrite any of the map or rp information
4774 * until we are sure we can commit to a new buffer.
4776 * Callers depend upon this behavior and assume that
4777 * we leave everything unchanged if we fail.
4779 skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4783 skb_reserve(skb, tp->rx_offset);
4785 mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4786 PCI_DMA_FROMDEVICE);
4787 if (pci_dma_mapping_error(tp->pdev, mapping)) {
4793 dma_unmap_addr_set(map, mapping, mapping);
4795 desc->addr_hi = ((u64)mapping >> 32);
4796 desc->addr_lo = ((u64)mapping & 0xffffffff);
4801 /* We only need to move over in the address because the other
4802 * members of the RX descriptor are invariant. See notes above
4803 * tg3_alloc_rx_skb for full details.
4805 static void tg3_recycle_rx(struct tg3_napi *tnapi,
4806 struct tg3_rx_prodring_set *dpr,
4807 u32 opaque_key, int src_idx,
4808 u32 dest_idx_unmasked)
4810 struct tg3 *tp = tnapi->tp;
4811 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4812 struct ring_info *src_map, *dest_map;
4813 struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
4816 switch (opaque_key) {
4817 case RXD_OPAQUE_RING_STD:
4818 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
4819 dest_desc = &dpr->rx_std[dest_idx];
4820 dest_map = &dpr->rx_std_buffers[dest_idx];
4821 src_desc = &spr->rx_std[src_idx];
4822 src_map = &spr->rx_std_buffers[src_idx];
4825 case RXD_OPAQUE_RING_JUMBO:
4826 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
4827 dest_desc = &dpr->rx_jmb[dest_idx].std;
4828 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4829 src_desc = &spr->rx_jmb[src_idx].std;
4830 src_map = &spr->rx_jmb_buffers[src_idx];
4837 dest_map->skb = src_map->skb;
4838 dma_unmap_addr_set(dest_map, mapping,
4839 dma_unmap_addr(src_map, mapping));
4840 dest_desc->addr_hi = src_desc->addr_hi;
4841 dest_desc->addr_lo = src_desc->addr_lo;
4843 /* Ensure that the update to the skb happens after the physical
4844 * addresses have been transferred to the new BD location.
4848 src_map->skb = NULL;
4851 /* The RX ring scheme is composed of multiple rings which post fresh
4852 * buffers to the chip, and one special ring the chip uses to report
4853 * status back to the host.
4855 * The special ring reports the status of received packets to the
4856 * host. The chip does not write into the original descriptor the
4857 * RX buffer was obtained from. The chip simply takes the original
4858 * descriptor as provided by the host, updates the status and length
4859 * field, then writes this into the next status ring entry.
4861 * Each ring the host uses to post buffers to the chip is described
4862 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4863 * it is first placed into the on-chip ram. When the packet's length
4864 * is known, it walks down the TG3_BDINFO entries to select the ring.
4865 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4866 * which is within the range of the new packet's length is chosen.
4868 * The "separate ring for rx status" scheme may sound queer, but it makes
4869 * sense from a cache coherency perspective. If only the host writes
4870 * to the buffer post rings, and only the chip writes to the rx status
4871 * rings, then cache lines never move beyond shared-modified state.
4872 * If both the host and chip were to write into the same ring, cache line
4873 * eviction could occur since both entities want it in an exclusive state.
4875 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4877 struct tg3 *tp = tnapi->tp;
4878 u32 work_mask, rx_std_posted = 0;
4879 u32 std_prod_idx, jmb_prod_idx;
4880 u32 sw_idx = tnapi->rx_rcb_ptr;
4883 struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
4885 hw_idx = *(tnapi->rx_rcb_prod_idx);
4887 * We need to order the read of hw_idx and the read of
4888 * the opaque cookie.
4893 std_prod_idx = tpr->rx_std_prod_idx;
4894 jmb_prod_idx = tpr->rx_jmb_prod_idx;
4895 while (sw_idx != hw_idx && budget > 0) {
4896 struct ring_info *ri;
4897 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4899 struct sk_buff *skb;
4900 dma_addr_t dma_addr;
4901 u32 opaque_key, desc_idx, *post_ptr;
4903 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4904 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4905 if (opaque_key == RXD_OPAQUE_RING_STD) {
4906 ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
4907 dma_addr = dma_unmap_addr(ri, mapping);
4909 post_ptr = &std_prod_idx;
4911 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4912 ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
4913 dma_addr = dma_unmap_addr(ri, mapping);
4915 post_ptr = &jmb_prod_idx;
4917 goto next_pkt_nopost;
4919 work_mask |= opaque_key;
4921 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4922 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4924 tg3_recycle_rx(tnapi, tpr, opaque_key,
4925 desc_idx, *post_ptr);
4927 /* Other statistics kept track of by card. */
4932 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4935 if (len > TG3_RX_COPY_THRESH(tp)) {
4938 skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
4943 pci_unmap_single(tp->pdev, dma_addr, skb_size,
4944 PCI_DMA_FROMDEVICE);
4946 /* Ensure that the update to the skb happens
4947 * after the usage of the old DMA mapping.
4955 struct sk_buff *copy_skb;
4957 tg3_recycle_rx(tnapi, tpr, opaque_key,
4958 desc_idx, *post_ptr);
4960 copy_skb = netdev_alloc_skb(tp->dev, len +
4962 if (copy_skb == NULL)
4963 goto drop_it_no_recycle;
4965 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
4966 skb_put(copy_skb, len);
4967 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4968 skb_copy_from_linear_data(skb, copy_skb->data, len);
4969 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4971 /* We'll reuse the original ring buffer. */
4975 if ((tp->dev->features & NETIF_F_RXCSUM) &&
4976 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4977 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4978 >> RXD_TCPCSUM_SHIFT) == 0xffff))
4979 skb->ip_summed = CHECKSUM_UNNECESSARY;
4981 skb_checksum_none_assert(skb);
4983 skb->protocol = eth_type_trans(skb, tp->dev);
4985 if (len > (tp->dev->mtu + ETH_HLEN) &&
4986 skb->protocol != htons(ETH_P_8021Q)) {
4988 goto drop_it_no_recycle;
4991 if (desc->type_flags & RXD_FLAG_VLAN &&
4992 !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG))
4993 __vlan_hwaccel_put_tag(skb,
4994 desc->err_vlan & RXD_VLAN_MASK);
4996 napi_gro_receive(&tnapi->napi, skb);
5004 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
5005 tpr->rx_std_prod_idx = std_prod_idx &
5006 tp->rx_std_ring_mask;
5007 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5008 tpr->rx_std_prod_idx);
5009 work_mask &= ~RXD_OPAQUE_RING_STD;
5014 sw_idx &= tp->rx_ret_ring_mask;
5016 /* Refresh hw_idx to see if there is new work */
5017 if (sw_idx == hw_idx) {
5018 hw_idx = *(tnapi->rx_rcb_prod_idx);
5023 /* ACK the status ring. */
5024 tnapi->rx_rcb_ptr = sw_idx;
5025 tw32_rx_mbox(tnapi->consmbox, sw_idx);
5027 /* Refill RX ring(s). */
5028 if (!tg3_flag(tp, ENABLE_RSS)) {
5029 if (work_mask & RXD_OPAQUE_RING_STD) {
5030 tpr->rx_std_prod_idx = std_prod_idx &
5031 tp->rx_std_ring_mask;
5032 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5033 tpr->rx_std_prod_idx);
5035 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
5036 tpr->rx_jmb_prod_idx = jmb_prod_idx &
5037 tp->rx_jmb_ring_mask;
5038 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
5039 tpr->rx_jmb_prod_idx);
5042 } else if (work_mask) {
5043 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
5044 * updated before the producer indices can be updated.
5048 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
5049 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
5051 if (tnapi != &tp->napi[1])
5052 napi_schedule(&tp->napi[1].napi);
5058 static void tg3_poll_link(struct tg3 *tp)
5060 /* handle link change and other phy events */
5061 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
5062 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
5064 if (sblk->status & SD_STATUS_LINK_CHG) {
5065 sblk->status = SD_STATUS_UPDATED |
5066 (sblk->status & ~SD_STATUS_LINK_CHG);
5067 spin_lock(&tp->lock);
5068 if (tg3_flag(tp, USE_PHYLIB)) {
5070 (MAC_STATUS_SYNC_CHANGED |
5071 MAC_STATUS_CFG_CHANGED |
5072 MAC_STATUS_MI_COMPLETION |
5073 MAC_STATUS_LNKSTATE_CHANGED));
5076 tg3_setup_phy(tp, 0);
5077 spin_unlock(&tp->lock);
5082 static int tg3_rx_prodring_xfer(struct tg3 *tp,
5083 struct tg3_rx_prodring_set *dpr,
5084 struct tg3_rx_prodring_set *spr)
5086 u32 si, di, cpycnt, src_prod_idx;
5090 src_prod_idx = spr->rx_std_prod_idx;
5092 /* Make sure updates to the rx_std_buffers[] entries and the
5093 * standard producer index are seen in the correct order.
5097 if (spr->rx_std_cons_idx == src_prod_idx)
5100 if (spr->rx_std_cons_idx < src_prod_idx)
5101 cpycnt = src_prod_idx - spr->rx_std_cons_idx;
5103 cpycnt = tp->rx_std_ring_mask + 1 -
5104 spr->rx_std_cons_idx;
5106 cpycnt = min(cpycnt,
5107 tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
5109 si = spr->rx_std_cons_idx;
5110 di = dpr->rx_std_prod_idx;
5112 for (i = di; i < di + cpycnt; i++) {
5113 if (dpr->rx_std_buffers[i].skb) {
5123 /* Ensure that updates to the rx_std_buffers ring and the
5124 * shadowed hardware producer ring from tg3_recycle_skb() are
5125 * ordered correctly WRT the skb check above.
5129 memcpy(&dpr->rx_std_buffers[di],
5130 &spr->rx_std_buffers[si],
5131 cpycnt * sizeof(struct ring_info));
5133 for (i = 0; i < cpycnt; i++, di++, si++) {
5134 struct tg3_rx_buffer_desc *sbd, *dbd;
5135 sbd = &spr->rx_std[si];
5136 dbd = &dpr->rx_std[di];
5137 dbd->addr_hi = sbd->addr_hi;
5138 dbd->addr_lo = sbd->addr_lo;
5141 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
5142 tp->rx_std_ring_mask;
5143 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
5144 tp->rx_std_ring_mask;
5148 src_prod_idx = spr->rx_jmb_prod_idx;
5150 /* Make sure updates to the rx_jmb_buffers[] entries and
5151 * the jumbo producer index are seen in the correct order.
5155 if (spr->rx_jmb_cons_idx == src_prod_idx)
5158 if (spr->rx_jmb_cons_idx < src_prod_idx)
5159 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
5161 cpycnt = tp->rx_jmb_ring_mask + 1 -
5162 spr->rx_jmb_cons_idx;
5164 cpycnt = min(cpycnt,
5165 tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
5167 si = spr->rx_jmb_cons_idx;
5168 di = dpr->rx_jmb_prod_idx;
5170 for (i = di; i < di + cpycnt; i++) {
5171 if (dpr->rx_jmb_buffers[i].skb) {
5181 /* Ensure that updates to the rx_jmb_buffers ring and the
5182 * shadowed hardware producer ring from tg3_recycle_skb() are
5183 * ordered correctly WRT the skb check above.
5187 memcpy(&dpr->rx_jmb_buffers[di],
5188 &spr->rx_jmb_buffers[si],
5189 cpycnt * sizeof(struct ring_info));
5191 for (i = 0; i < cpycnt; i++, di++, si++) {
5192 struct tg3_rx_buffer_desc *sbd, *dbd;
5193 sbd = &spr->rx_jmb[si].std;
5194 dbd = &dpr->rx_jmb[di].std;
5195 dbd->addr_hi = sbd->addr_hi;
5196 dbd->addr_lo = sbd->addr_lo;
5199 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
5200 tp->rx_jmb_ring_mask;
5201 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
5202 tp->rx_jmb_ring_mask;
5208 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
5210 struct tg3 *tp = tnapi->tp;
5212 /* run TX completion thread */
5213 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
5215 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
5219 /* run RX thread, within the bounds set by NAPI.
5220 * All RX "locking" is done by ensuring outside
5221 * code synchronizes with tg3->napi.poll()
5223 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
5224 work_done += tg3_rx(tnapi, budget - work_done);
5226 if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) {
5227 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
5229 u32 std_prod_idx = dpr->rx_std_prod_idx;
5230 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
5232 for (i = 1; i < tp->irq_cnt; i++)
5233 err |= tg3_rx_prodring_xfer(tp, dpr,
5234 &tp->napi[i].prodring);
5238 if (std_prod_idx != dpr->rx_std_prod_idx)
5239 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5240 dpr->rx_std_prod_idx);
5242 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
5243 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
5244 dpr->rx_jmb_prod_idx);
5249 tw32_f(HOSTCC_MODE, tp->coal_now);
5255 static int tg3_poll_msix(struct napi_struct *napi, int budget)
5257 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5258 struct tg3 *tp = tnapi->tp;
5260 struct tg3_hw_status *sblk = tnapi->hw_status;
5263 work_done = tg3_poll_work(tnapi, work_done, budget);
5265 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
5268 if (unlikely(work_done >= budget))
5271 /* tp->last_tag is used in tg3_int_reenable() below
5272 * to tell the hw how much work has been processed,
5273 * so we must read it before checking for more work.
5275 tnapi->last_tag = sblk->status_tag;
5276 tnapi->last_irq_tag = tnapi->last_tag;
5279 /* check for RX/TX work to do */
5280 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
5281 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
5282 napi_complete(napi);
5283 /* Reenable interrupts. */
5284 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
5293 /* work_done is guaranteed to be less than budget. */
5294 napi_complete(napi);
5295 schedule_work(&tp->reset_task);
5299 static void tg3_process_error(struct tg3 *tp)
5302 bool real_error = false;
5304 if (tg3_flag(tp, ERROR_PROCESSED))
5307 /* Check Flow Attention register */
5308 val = tr32(HOSTCC_FLOW_ATTN);
5309 if (val & ~HOSTCC_FLOW_ATTN_MBUF_LWM) {
5310 netdev_err(tp->dev, "FLOW Attention error. Resetting chip.\n");
5314 if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) {
5315 netdev_err(tp->dev, "MSI Status error. Resetting chip.\n");
5319 if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) {
5320 netdev_err(tp->dev, "DMA Status error. Resetting chip.\n");
5329 tg3_flag_set(tp, ERROR_PROCESSED);
5330 schedule_work(&tp->reset_task);
5333 static int tg3_poll(struct napi_struct *napi, int budget)
5335 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5336 struct tg3 *tp = tnapi->tp;
5338 struct tg3_hw_status *sblk = tnapi->hw_status;
5341 if (sblk->status & SD_STATUS_ERROR)
5342 tg3_process_error(tp);
5346 work_done = tg3_poll_work(tnapi, work_done, budget);
5348 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
5351 if (unlikely(work_done >= budget))
5354 if (tg3_flag(tp, TAGGED_STATUS)) {
5355 /* tp->last_tag is used in tg3_int_reenable() below
5356 * to tell the hw how much work has been processed,
5357 * so we must read it before checking for more work.
5359 tnapi->last_tag = sblk->status_tag;
5360 tnapi->last_irq_tag = tnapi->last_tag;
5363 sblk->status &= ~SD_STATUS_UPDATED;
5365 if (likely(!tg3_has_work(tnapi))) {
5366 napi_complete(napi);
5367 tg3_int_reenable(tnapi);
5375 /* work_done is guaranteed to be less than budget. */
5376 napi_complete(napi);
5377 schedule_work(&tp->reset_task);
5381 static void tg3_napi_disable(struct tg3 *tp)
5385 for (i = tp->irq_cnt - 1; i >= 0; i--)
5386 napi_disable(&tp->napi[i].napi);
5389 static void tg3_napi_enable(struct tg3 *tp)
5393 for (i = 0; i < tp->irq_cnt; i++)
5394 napi_enable(&tp->napi[i].napi);
5397 static void tg3_napi_init(struct tg3 *tp)
5401 netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
5402 for (i = 1; i < tp->irq_cnt; i++)
5403 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
5406 static void tg3_napi_fini(struct tg3 *tp)
5410 for (i = 0; i < tp->irq_cnt; i++)
5411 netif_napi_del(&tp->napi[i].napi);
5414 static inline void tg3_netif_stop(struct tg3 *tp)
5416 tp->dev->trans_start = jiffies; /* prevent tx timeout */
5417 tg3_napi_disable(tp);
5418 netif_tx_disable(tp->dev);
5421 static inline void tg3_netif_start(struct tg3 *tp)
5423 /* NOTE: unconditional netif_tx_wake_all_queues is only
5424 * appropriate so long as all callers are assured to
5425 * have free tx slots (such as after tg3_init_hw)
5427 netif_tx_wake_all_queues(tp->dev);
5429 tg3_napi_enable(tp);
5430 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
5431 tg3_enable_ints(tp);
5434 static void tg3_irq_quiesce(struct tg3 *tp)
5438 BUG_ON(tp->irq_sync);
5443 for (i = 0; i < tp->irq_cnt; i++)
5444 synchronize_irq(tp->napi[i].irq_vec);
5447 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5448 * If irq_sync is non-zero, then the IRQ handler must be synchronized
5449 * with as well. Most of the time, this is not necessary except when
5450 * shutting down the device.
5452 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5454 spin_lock_bh(&tp->lock);
5456 tg3_irq_quiesce(tp);
5459 static inline void tg3_full_unlock(struct tg3 *tp)
5461 spin_unlock_bh(&tp->lock);
5464 /* One-shot MSI handler - Chip automatically disables interrupt
5465 * after sending MSI so driver doesn't have to do it.
5467 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
5469 struct tg3_napi *tnapi = dev_id;
5470 struct tg3 *tp = tnapi->tp;
5472 prefetch(tnapi->hw_status);
5474 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5476 if (likely(!tg3_irq_sync(tp)))
5477 napi_schedule(&tnapi->napi);
5482 /* MSI ISR - No need to check for interrupt sharing and no need to
5483 * flush status block and interrupt mailbox. PCI ordering rules
5484 * guarantee that MSI will arrive after the status block.
5486 static irqreturn_t tg3_msi(int irq, void *dev_id)
5488 struct tg3_napi *tnapi = dev_id;
5489 struct tg3 *tp = tnapi->tp;
5491 prefetch(tnapi->hw_status);
5493 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5495 * Writing any value to intr-mbox-0 clears PCI INTA# and
5496 * chip-internal interrupt pending events.
5497 * Writing non-zero to intr-mbox-0 additional tells the
5498 * NIC to stop sending us irqs, engaging "in-intr-handler"
5501 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5502 if (likely(!tg3_irq_sync(tp)))
5503 napi_schedule(&tnapi->napi);
5505 return IRQ_RETVAL(1);
5508 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
5510 struct tg3_napi *tnapi = dev_id;
5511 struct tg3 *tp = tnapi->tp;
5512 struct tg3_hw_status *sblk = tnapi->hw_status;
5513 unsigned int handled = 1;
5515 /* In INTx mode, it is possible for the interrupt to arrive at
5516 * the CPU before the status block posted prior to the interrupt.
5517 * Reading the PCI State register will confirm whether the
5518 * interrupt is ours and will flush the status block.
5520 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5521 if (tg3_flag(tp, CHIP_RESETTING) ||
5522 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5529 * Writing any value to intr-mbox-0 clears PCI INTA# and
5530 * chip-internal interrupt pending events.
5531 * Writing non-zero to intr-mbox-0 additional tells the
5532 * NIC to stop sending us irqs, engaging "in-intr-handler"
5535 * Flush the mailbox to de-assert the IRQ immediately to prevent
5536 * spurious interrupts. The flush impacts performance but
5537 * excessive spurious interrupts can be worse in some cases.
5539 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5540 if (tg3_irq_sync(tp))
5542 sblk->status &= ~SD_STATUS_UPDATED;
5543 if (likely(tg3_has_work(tnapi))) {
5544 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5545 napi_schedule(&tnapi->napi);
5547 /* No work, shared interrupt perhaps? re-enable
5548 * interrupts, and flush that PCI write
5550 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5554 return IRQ_RETVAL(handled);
5557 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
5559 struct tg3_napi *tnapi = dev_id;
5560 struct tg3 *tp = tnapi->tp;
5561 struct tg3_hw_status *sblk = tnapi->hw_status;
5562 unsigned int handled = 1;
5564 /* In INTx mode, it is possible for the interrupt to arrive at
5565 * the CPU before the status block posted prior to the interrupt.
5566 * Reading the PCI State register will confirm whether the
5567 * interrupt is ours and will flush the status block.
5569 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
5570 if (tg3_flag(tp, CHIP_RESETTING) ||
5571 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5578 * writing any value to intr-mbox-0 clears PCI INTA# and
5579 * chip-internal interrupt pending events.
5580 * writing non-zero to intr-mbox-0 additional tells the
5581 * NIC to stop sending us irqs, engaging "in-intr-handler"
5584 * Flush the mailbox to de-assert the IRQ immediately to prevent
5585 * spurious interrupts. The flush impacts performance but
5586 * excessive spurious interrupts can be worse in some cases.
5588 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5591 * In a shared interrupt configuration, sometimes other devices'
5592 * interrupts will scream. We record the current status tag here
5593 * so that the above check can report that the screaming interrupts
5594 * are unhandled. Eventually they will be silenced.
5596 tnapi->last_irq_tag = sblk->status_tag;
5598 if (tg3_irq_sync(tp))
5601 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5603 napi_schedule(&tnapi->napi);
5606 return IRQ_RETVAL(handled);
5609 /* ISR for interrupt test */
5610 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5612 struct tg3_napi *tnapi = dev_id;
5613 struct tg3 *tp = tnapi->tp;
5614 struct tg3_hw_status *sblk = tnapi->hw_status;
5616 if ((sblk->status & SD_STATUS_UPDATED) ||
5617 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5618 tg3_disable_ints(tp);
5619 return IRQ_RETVAL(1);
5621 return IRQ_RETVAL(0);
5624 static int tg3_init_hw(struct tg3 *, int);
5625 static int tg3_halt(struct tg3 *, int, int);
5627 /* Restart hardware after configuration changes, self-test, etc.
5628 * Invoked with tp->lock held.
5630 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5631 __releases(tp->lock)
5632 __acquires(tp->lock)
5636 err = tg3_init_hw(tp, reset_phy);
5639 "Failed to re-initialize device, aborting\n");
5640 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5641 tg3_full_unlock(tp);
5642 del_timer_sync(&tp->timer);
5644 tg3_napi_enable(tp);
5646 tg3_full_lock(tp, 0);
5651 #ifdef CONFIG_NET_POLL_CONTROLLER
5652 static void tg3_poll_controller(struct net_device *dev)
5655 struct tg3 *tp = netdev_priv(dev);
5657 for (i = 0; i < tp->irq_cnt; i++)
5658 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
5662 static void tg3_reset_task(struct work_struct *work)
5664 struct tg3 *tp = container_of(work, struct tg3, reset_task);
5666 unsigned int restart_timer;
5668 tg3_full_lock(tp, 0);
5670 if (!netif_running(tp->dev)) {
5671 tg3_full_unlock(tp);
5675 tg3_full_unlock(tp);
5681 tg3_full_lock(tp, 1);
5683 restart_timer = tg3_flag(tp, RESTART_TIMER);
5684 tg3_flag_clear(tp, RESTART_TIMER);
5686 if (tg3_flag(tp, TX_RECOVERY_PENDING)) {
5687 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5688 tp->write32_rx_mbox = tg3_write_flush_reg32;
5689 tg3_flag_set(tp, MBOX_WRITE_REORDER);
5690 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
5693 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5694 err = tg3_init_hw(tp, 1);
5698 tg3_netif_start(tp);
5701 mod_timer(&tp->timer, jiffies + 1);
5704 tg3_full_unlock(tp);
5710 static void tg3_tx_timeout(struct net_device *dev)
5712 struct tg3 *tp = netdev_priv(dev);
5714 if (netif_msg_tx_err(tp)) {
5715 netdev_err(dev, "transmit timed out, resetting\n");
5719 schedule_work(&tp->reset_task);
5722 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5723 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5725 u32 base = (u32) mapping & 0xffffffff;
5727 return (base > 0xffffdcc0) && (base + len + 8 < base);
5730 /* Test for DMA addresses > 40-bit */
5731 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5734 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5735 if (tg3_flag(tp, 40BIT_DMA_BUG))
5736 return ((u64) mapping + len) > DMA_BIT_MASK(40);
5743 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5744 dma_addr_t mapping, int len, u32 flags,
5747 struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5748 int is_end = (mss_and_is_end & 0x1);
5749 u32 mss = (mss_and_is_end >> 1);
5753 flags |= TXD_FLAG_END;
5754 if (flags & TXD_FLAG_VLAN) {
5755 vlan_tag = flags >> 16;
5758 vlan_tag |= (mss << TXD_MSS_SHIFT);
5760 txd->addr_hi = ((u64) mapping >> 32);
5761 txd->addr_lo = ((u64) mapping & 0xffffffff);
5762 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5763 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5766 static void tg3_skb_error_unmap(struct tg3_napi *tnapi,
5767 struct sk_buff *skb, int last)
5770 u32 entry = tnapi->tx_prod;
5771 struct ring_info *txb = &tnapi->tx_buffers[entry];
5773 pci_unmap_single(tnapi->tp->pdev,
5774 dma_unmap_addr(txb, mapping),
5777 for (i = 0; i < last; i++) {
5778 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5780 entry = NEXT_TX(entry);
5781 txb = &tnapi->tx_buffers[entry];
5783 pci_unmap_page(tnapi->tp->pdev,
5784 dma_unmap_addr(txb, mapping),
5785 frag->size, PCI_DMA_TODEVICE);
5789 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5790 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5791 struct sk_buff *skb,
5792 u32 base_flags, u32 mss)
5794 struct tg3 *tp = tnapi->tp;
5795 struct sk_buff *new_skb;
5796 dma_addr_t new_addr = 0;
5797 u32 entry = tnapi->tx_prod;
5800 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5801 new_skb = skb_copy(skb, GFP_ATOMIC);
5803 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5805 new_skb = skb_copy_expand(skb,
5806 skb_headroom(skb) + more_headroom,
5807 skb_tailroom(skb), GFP_ATOMIC);
5813 /* New SKB is guaranteed to be linear. */
5814 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5816 /* Make sure the mapping succeeded */
5817 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5819 dev_kfree_skb(new_skb);
5821 /* Make sure new skb does not cross any 4G boundaries.
5822 * Drop the packet if it does.
5824 } else if (tg3_flag(tp, 4G_DMA_BNDRY_BUG) &&
5825 tg3_4g_overflow_test(new_addr, new_skb->len)) {
5826 pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5829 dev_kfree_skb(new_skb);
5831 tnapi->tx_buffers[entry].skb = new_skb;
5832 dma_unmap_addr_set(&tnapi->tx_buffers[entry],
5835 tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5836 base_flags, 1 | (mss << 1));
5845 static netdev_tx_t tg3_start_xmit(struct sk_buff *, struct net_device *);
5847 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5848 * TSO header is greater than 80 bytes.
5850 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5852 struct sk_buff *segs, *nskb;
5853 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5855 /* Estimate the number of fragments in the worst case */
5856 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5857 netif_stop_queue(tp->dev);
5859 /* netif_tx_stop_queue() must be done before checking
5860 * checking tx index in tg3_tx_avail() below, because in
5861 * tg3_tx(), we update tx index before checking for
5862 * netif_tx_queue_stopped().
5865 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5866 return NETDEV_TX_BUSY;
5868 netif_wake_queue(tp->dev);
5871 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5873 goto tg3_tso_bug_end;
5879 tg3_start_xmit(nskb, tp->dev);
5885 return NETDEV_TX_OK;
5888 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5889 * support TG3_FLAG_HW_TSO_1 or firmware TSO only.
5891 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
5893 struct tg3 *tp = netdev_priv(dev);
5894 u32 len, entry, base_flags, mss;
5895 int i = -1, would_hit_hwbug;
5897 struct tg3_napi *tnapi;
5898 struct netdev_queue *txq;
5901 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5902 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5903 if (tg3_flag(tp, ENABLE_TSS))
5906 /* We are running in BH disabled context with netif_tx_lock
5907 * and TX reclaim runs via tp->napi.poll inside of a software
5908 * interrupt. Furthermore, IRQ processing runs lockless so we have
5909 * no IRQ context deadlocks to worry about either. Rejoice!
5911 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5912 if (!netif_tx_queue_stopped(txq)) {
5913 netif_tx_stop_queue(txq);
5915 /* This is a hard error, log it. */
5917 "BUG! Tx Ring full when queue awake!\n");
5919 return NETDEV_TX_BUSY;
5922 entry = tnapi->tx_prod;
5924 if (skb->ip_summed == CHECKSUM_PARTIAL)
5925 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5927 mss = skb_shinfo(skb)->gso_size;
5930 u32 tcp_opt_len, hdr_len;
5932 if (skb_header_cloned(skb) &&
5933 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5939 tcp_opt_len = tcp_optlen(skb);
5941 if (skb_is_gso_v6(skb)) {
5942 hdr_len = skb_headlen(skb) - ETH_HLEN;
5946 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5947 hdr_len = ip_tcp_len + tcp_opt_len;
5950 iph->tot_len = htons(mss + hdr_len);
5953 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5954 tg3_flag(tp, TSO_BUG))
5955 return tg3_tso_bug(tp, skb);
5957 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5958 TXD_FLAG_CPU_POST_DMA);
5960 if (tg3_flag(tp, HW_TSO_1) ||
5961 tg3_flag(tp, HW_TSO_2) ||
5962 tg3_flag(tp, HW_TSO_3)) {
5963 tcp_hdr(skb)->check = 0;
5964 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5966 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5971 if (tg3_flag(tp, HW_TSO_3)) {
5972 mss |= (hdr_len & 0xc) << 12;
5974 base_flags |= 0x00000010;
5975 base_flags |= (hdr_len & 0x3e0) << 5;
5976 } else if (tg3_flag(tp, HW_TSO_2))
5977 mss |= hdr_len << 9;
5978 else if (tg3_flag(tp, HW_TSO_1) ||
5979 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5980 if (tcp_opt_len || iph->ihl > 5) {
5983 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5984 mss |= (tsflags << 11);
5987 if (tcp_opt_len || iph->ihl > 5) {
5990 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5991 base_flags |= tsflags << 12;
5996 if (vlan_tx_tag_present(skb))
5997 base_flags |= (TXD_FLAG_VLAN |
5998 (vlan_tx_tag_get(skb) << 16));
6000 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
6001 !mss && skb->len > VLAN_ETH_FRAME_LEN)
6002 base_flags |= TXD_FLAG_JMB_PKT;
6004 len = skb_headlen(skb);
6006 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
6007 if (pci_dma_mapping_error(tp->pdev, mapping)) {
6012 tnapi->tx_buffers[entry].skb = skb;
6013 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
6015 would_hit_hwbug = 0;
6017 if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8)
6018 would_hit_hwbug = 1;
6020 if (tg3_flag(tp, 4G_DMA_BNDRY_BUG) &&
6021 tg3_4g_overflow_test(mapping, len))
6022 would_hit_hwbug = 1;
6024 if (tg3_flag(tp, 40BIT_DMA_LIMIT_BUG) &&
6025 tg3_40bit_overflow_test(tp, mapping, len))
6026 would_hit_hwbug = 1;
6028 if (tg3_flag(tp, 5701_DMA_BUG))
6029 would_hit_hwbug = 1;
6031 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
6032 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
6034 entry = NEXT_TX(entry);
6036 /* Now loop through additional data fragments, and queue them. */
6037 if (skb_shinfo(skb)->nr_frags > 0) {
6038 last = skb_shinfo(skb)->nr_frags - 1;
6039 for (i = 0; i <= last; i++) {
6040 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6043 mapping = pci_map_page(tp->pdev,
6046 len, PCI_DMA_TODEVICE);
6048 tnapi->tx_buffers[entry].skb = NULL;
6049 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
6051 if (pci_dma_mapping_error(tp->pdev, mapping))
6054 if (tg3_flag(tp, SHORT_DMA_BUG) &&
6056 would_hit_hwbug = 1;
6058 if (tg3_flag(tp, 4G_DMA_BNDRY_BUG) &&
6059 tg3_4g_overflow_test(mapping, len))
6060 would_hit_hwbug = 1;
6062 if (tg3_flag(tp, 40BIT_DMA_LIMIT_BUG) &&
6063 tg3_40bit_overflow_test(tp, mapping, len))
6064 would_hit_hwbug = 1;
6066 if (tg3_flag(tp, HW_TSO_1) ||
6067 tg3_flag(tp, HW_TSO_2) ||
6068 tg3_flag(tp, HW_TSO_3))
6069 tg3_set_txd(tnapi, entry, mapping, len,
6070 base_flags, (i == last)|(mss << 1));
6072 tg3_set_txd(tnapi, entry, mapping, len,
6073 base_flags, (i == last));
6075 entry = NEXT_TX(entry);
6079 if (would_hit_hwbug) {
6080 tg3_skb_error_unmap(tnapi, skb, i);
6082 /* If the workaround fails due to memory/mapping
6083 * failure, silently drop this packet.
6085 if (tigon3_dma_hwbug_workaround(tnapi, skb, base_flags, mss))
6088 entry = NEXT_TX(tnapi->tx_prod);
6091 /* Packets are ready, update Tx producer idx local and on card. */
6092 tw32_tx_mbox(tnapi->prodmbox, entry);
6094 tnapi->tx_prod = entry;
6095 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
6096 netif_tx_stop_queue(txq);
6098 /* netif_tx_stop_queue() must be done before checking
6099 * checking tx index in tg3_tx_avail() below, because in
6100 * tg3_tx(), we update tx index before checking for
6101 * netif_tx_queue_stopped().
6104 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
6105 netif_tx_wake_queue(txq);
6111 return NETDEV_TX_OK;
6114 tg3_skb_error_unmap(tnapi, skb, i);
6116 tnapi->tx_buffers[tnapi->tx_prod].skb = NULL;
6117 return NETDEV_TX_OK;
6120 static void tg3_set_loopback(struct net_device *dev, u32 features)
6122 struct tg3 *tp = netdev_priv(dev);
6124 if (features & NETIF_F_LOOPBACK) {
6125 if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)
6129 * Clear MAC_MODE_HALF_DUPLEX or you won't get packets back in
6130 * loopback mode if Half-Duplex mode was negotiated earlier.
6132 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
6134 /* Enable internal MAC loopback mode */
6135 tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK;
6136 spin_lock_bh(&tp->lock);
6137 tw32(MAC_MODE, tp->mac_mode);
6138 netif_carrier_on(tp->dev);
6139 spin_unlock_bh(&tp->lock);
6140 netdev_info(dev, "Internal MAC loopback mode enabled.\n");
6142 if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
6145 /* Disable internal MAC loopback mode */
6146 tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK;
6147 spin_lock_bh(&tp->lock);
6148 tw32(MAC_MODE, tp->mac_mode);
6149 /* Force link status check */
6150 tg3_setup_phy(tp, 1);
6151 spin_unlock_bh(&tp->lock);
6152 netdev_info(dev, "Internal MAC loopback mode disabled.\n");
6156 static u32 tg3_fix_features(struct net_device *dev, u32 features)
6158 struct tg3 *tp = netdev_priv(dev);
6160 if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS))
6161 features &= ~NETIF_F_ALL_TSO;
6166 static int tg3_set_features(struct net_device *dev, u32 features)
6168 u32 changed = dev->features ^ features;
6170 if ((changed & NETIF_F_LOOPBACK) && netif_running(dev))
6171 tg3_set_loopback(dev, features);
6176 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
6181 if (new_mtu > ETH_DATA_LEN) {
6182 if (tg3_flag(tp, 5780_CLASS)) {
6183 netdev_update_features(dev);
6184 tg3_flag_clear(tp, TSO_CAPABLE);
6186 tg3_flag_set(tp, JUMBO_RING_ENABLE);
6189 if (tg3_flag(tp, 5780_CLASS)) {
6190 tg3_flag_set(tp, TSO_CAPABLE);
6191 netdev_update_features(dev);
6193 tg3_flag_clear(tp, JUMBO_RING_ENABLE);
6197 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
6199 struct tg3 *tp = netdev_priv(dev);
6202 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
6205 if (!netif_running(dev)) {
6206 /* We'll just catch it later when the
6209 tg3_set_mtu(dev, tp, new_mtu);
6217 tg3_full_lock(tp, 1);
6219 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6221 tg3_set_mtu(dev, tp, new_mtu);
6223 err = tg3_restart_hw(tp, 0);
6226 tg3_netif_start(tp);
6228 tg3_full_unlock(tp);
6236 static void tg3_rx_prodring_free(struct tg3 *tp,
6237 struct tg3_rx_prodring_set *tpr)
6241 if (tpr != &tp->napi[0].prodring) {
6242 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
6243 i = (i + 1) & tp->rx_std_ring_mask)
6244 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6247 if (tg3_flag(tp, JUMBO_CAPABLE)) {
6248 for (i = tpr->rx_jmb_cons_idx;
6249 i != tpr->rx_jmb_prod_idx;
6250 i = (i + 1) & tp->rx_jmb_ring_mask) {
6251 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6259 for (i = 0; i <= tp->rx_std_ring_mask; i++)
6260 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6263 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
6264 for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
6265 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6270 /* Initialize rx rings for packet processing.
6272 * The chip has been shut down and the driver detached from
6273 * the networking, so no interrupts or new tx packets will
6274 * end up in the driver. tp->{tx,}lock are held and thus
6277 static int tg3_rx_prodring_alloc(struct tg3 *tp,
6278 struct tg3_rx_prodring_set *tpr)
6280 u32 i, rx_pkt_dma_sz;
6282 tpr->rx_std_cons_idx = 0;
6283 tpr->rx_std_prod_idx = 0;
6284 tpr->rx_jmb_cons_idx = 0;
6285 tpr->rx_jmb_prod_idx = 0;
6287 if (tpr != &tp->napi[0].prodring) {
6288 memset(&tpr->rx_std_buffers[0], 0,
6289 TG3_RX_STD_BUFF_RING_SIZE(tp));
6290 if (tpr->rx_jmb_buffers)
6291 memset(&tpr->rx_jmb_buffers[0], 0,
6292 TG3_RX_JMB_BUFF_RING_SIZE(tp));
6296 /* Zero out all descriptors. */
6297 memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
6299 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
6300 if (tg3_flag(tp, 5780_CLASS) &&
6301 tp->dev->mtu > ETH_DATA_LEN)
6302 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
6303 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
6305 /* Initialize invariants of the rings, we only set this
6306 * stuff once. This works because the card does not
6307 * write into the rx buffer posting rings.
6309 for (i = 0; i <= tp->rx_std_ring_mask; i++) {
6310 struct tg3_rx_buffer_desc *rxd;
6312 rxd = &tpr->rx_std[i];
6313 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
6314 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
6315 rxd->opaque = (RXD_OPAQUE_RING_STD |
6316 (i << RXD_OPAQUE_INDEX_SHIFT));
6319 /* Now allocate fresh SKBs for each rx ring. */
6320 for (i = 0; i < tp->rx_pending; i++) {
6321 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
6322 netdev_warn(tp->dev,
6323 "Using a smaller RX standard ring. Only "
6324 "%d out of %d buffers were allocated "
6325 "successfully\n", i, tp->rx_pending);
6333 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
6336 memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));
6338 if (!tg3_flag(tp, JUMBO_RING_ENABLE))
6341 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {
6342 struct tg3_rx_buffer_desc *rxd;
6344 rxd = &tpr->rx_jmb[i].std;
6345 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
6346 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
6348 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
6349 (i << RXD_OPAQUE_INDEX_SHIFT));
6352 for (i = 0; i < tp->rx_jumbo_pending; i++) {
6353 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) {
6354 netdev_warn(tp->dev,
6355 "Using a smaller RX jumbo ring. Only %d "
6356 "out of %d buffers were allocated "
6357 "successfully\n", i, tp->rx_jumbo_pending);
6360 tp->rx_jumbo_pending = i;
6369 tg3_rx_prodring_free(tp, tpr);
6373 static void tg3_rx_prodring_fini(struct tg3 *tp,
6374 struct tg3_rx_prodring_set *tpr)
6376 kfree(tpr->rx_std_buffers);
6377 tpr->rx_std_buffers = NULL;
6378 kfree(tpr->rx_jmb_buffers);
6379 tpr->rx_jmb_buffers = NULL;
6381 dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp),
6382 tpr->rx_std, tpr->rx_std_mapping);
6386 dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp),
6387 tpr->rx_jmb, tpr->rx_jmb_mapping);
6392 static int tg3_rx_prodring_init(struct tg3 *tp,
6393 struct tg3_rx_prodring_set *tpr)
6395 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp),
6397 if (!tpr->rx_std_buffers)
6400 tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev,
6401 TG3_RX_STD_RING_BYTES(tp),
6402 &tpr->rx_std_mapping,
6407 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
6408 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp),
6410 if (!tpr->rx_jmb_buffers)
6413 tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev,
6414 TG3_RX_JMB_RING_BYTES(tp),
6415 &tpr->rx_jmb_mapping,
6424 tg3_rx_prodring_fini(tp, tpr);
6428 /* Free up pending packets in all rx/tx rings.
6430 * The chip has been shut down and the driver detached from
6431 * the networking, so no interrupts or new tx packets will
6432 * end up in the driver. tp->{tx,}lock is not held and we are not
6433 * in an interrupt context and thus may sleep.
6435 static void tg3_free_rings(struct tg3 *tp)
6439 for (j = 0; j < tp->irq_cnt; j++) {
6440 struct tg3_napi *tnapi = &tp->napi[j];
6442 tg3_rx_prodring_free(tp, &tnapi->prodring);
6444 if (!tnapi->tx_buffers)
6447 for (i = 0; i < TG3_TX_RING_SIZE; ) {
6448 struct ring_info *txp;
6449 struct sk_buff *skb;
6452 txp = &tnapi->tx_buffers[i];
6460 pci_unmap_single(tp->pdev,
6461 dma_unmap_addr(txp, mapping),
6468 for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
6469 txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
6470 pci_unmap_page(tp->pdev,
6471 dma_unmap_addr(txp, mapping),
6472 skb_shinfo(skb)->frags[k].size,
6477 dev_kfree_skb_any(skb);
6482 /* Initialize tx/rx rings for packet processing.
6484 * The chip has been shut down and the driver detached from
6485 * the networking, so no interrupts or new tx packets will
6486 * end up in the driver. tp->{tx,}lock are held and thus
6489 static int tg3_init_rings(struct tg3 *tp)
6493 /* Free up all the SKBs. */
6496 for (i = 0; i < tp->irq_cnt; i++) {
6497 struct tg3_napi *tnapi = &tp->napi[i];
6499 tnapi->last_tag = 0;
6500 tnapi->last_irq_tag = 0;
6501 tnapi->hw_status->status = 0;
6502 tnapi->hw_status->status_tag = 0;
6503 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6508 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
6510 tnapi->rx_rcb_ptr = 0;
6512 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6514 if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
6524 * Must not be invoked with interrupt sources disabled and
6525 * the hardware shutdown down.
6527 static void tg3_free_consistent(struct tg3 *tp)
6531 for (i = 0; i < tp->irq_cnt; i++) {
6532 struct tg3_napi *tnapi = &tp->napi[i];
6534 if (tnapi->tx_ring) {
6535 dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES,
6536 tnapi->tx_ring, tnapi->tx_desc_mapping);
6537 tnapi->tx_ring = NULL;
6540 kfree(tnapi->tx_buffers);
6541 tnapi->tx_buffers = NULL;
6543 if (tnapi->rx_rcb) {
6544 dma_free_coherent(&tp->pdev->dev,
6545 TG3_RX_RCB_RING_BYTES(tp),
6547 tnapi->rx_rcb_mapping);
6548 tnapi->rx_rcb = NULL;
6551 tg3_rx_prodring_fini(tp, &tnapi->prodring);
6553 if (tnapi->hw_status) {
6554 dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE,
6556 tnapi->status_mapping);
6557 tnapi->hw_status = NULL;
6562 dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats),
6563 tp->hw_stats, tp->stats_mapping);
6564 tp->hw_stats = NULL;
6569 * Must not be invoked with interrupt sources disabled and
6570 * the hardware shutdown down. Can sleep.
6572 static int tg3_alloc_consistent(struct tg3 *tp)
6576 tp->hw_stats = dma_alloc_coherent(&tp->pdev->dev,
6577 sizeof(struct tg3_hw_stats),
6583 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6585 for (i = 0; i < tp->irq_cnt; i++) {
6586 struct tg3_napi *tnapi = &tp->napi[i];
6587 struct tg3_hw_status *sblk;
6589 tnapi->hw_status = dma_alloc_coherent(&tp->pdev->dev,
6591 &tnapi->status_mapping,
6593 if (!tnapi->hw_status)
6596 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6597 sblk = tnapi->hw_status;
6599 if (tg3_rx_prodring_init(tp, &tnapi->prodring))
6602 /* If multivector TSS is enabled, vector 0 does not handle
6603 * tx interrupts. Don't allocate any resources for it.
6605 if ((!i && !tg3_flag(tp, ENABLE_TSS)) ||
6606 (i && tg3_flag(tp, ENABLE_TSS))) {
6607 tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
6610 if (!tnapi->tx_buffers)
6613 tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev,
6615 &tnapi->tx_desc_mapping,
6617 if (!tnapi->tx_ring)
6622 * When RSS is enabled, the status block format changes
6623 * slightly. The "rx_jumbo_consumer", "reserved",
6624 * and "rx_mini_consumer" members get mapped to the
6625 * other three rx return ring producer indexes.
6629 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6632 tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6635 tnapi->rx_rcb_prod_idx = &sblk->reserved;
6638 tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6643 * If multivector RSS is enabled, vector 0 does not handle
6644 * rx or tx interrupts. Don't allocate any resources for it.
6646 if (!i && tg3_flag(tp, ENABLE_RSS))
6649 tnapi->rx_rcb = dma_alloc_coherent(&tp->pdev->dev,
6650 TG3_RX_RCB_RING_BYTES(tp),
6651 &tnapi->rx_rcb_mapping,
6656 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6662 tg3_free_consistent(tp);
6666 #define MAX_WAIT_CNT 1000
6668 /* To stop a block, clear the enable bit and poll till it
6669 * clears. tp->lock is held.
6671 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
6676 if (tg3_flag(tp, 5705_PLUS)) {
6683 /* We can't enable/disable these bits of the
6684 * 5705/5750, just say success.
6697 for (i = 0; i < MAX_WAIT_CNT; i++) {
6700 if ((val & enable_bit) == 0)
6704 if (i == MAX_WAIT_CNT && !silent) {
6705 dev_err(&tp->pdev->dev,
6706 "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
6714 /* tp->lock is held. */
6715 static int tg3_abort_hw(struct tg3 *tp, int silent)
6719 tg3_disable_ints(tp);
6721 tp->rx_mode &= ~RX_MODE_ENABLE;
6722 tw32_f(MAC_RX_MODE, tp->rx_mode);
6725 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6726 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6727 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6728 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6729 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6730 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6732 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6733 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6734 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6735 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6736 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6737 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6738 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
6740 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6741 tw32_f(MAC_MODE, tp->mac_mode);
6744 tp->tx_mode &= ~TX_MODE_ENABLE;
6745 tw32_f(MAC_TX_MODE, tp->tx_mode);
6747 for (i = 0; i < MAX_WAIT_CNT; i++) {
6749 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6752 if (i >= MAX_WAIT_CNT) {
6753 dev_err(&tp->pdev->dev,
6754 "%s timed out, TX_MODE_ENABLE will not clear "
6755 "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
6759 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
6760 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6761 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
6763 tw32(FTQ_RESET, 0xffffffff);
6764 tw32(FTQ_RESET, 0x00000000);
6766 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6767 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
6769 for (i = 0; i < tp->irq_cnt; i++) {
6770 struct tg3_napi *tnapi = &tp->napi[i];
6771 if (tnapi->hw_status)
6772 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6775 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6780 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6785 /* NCSI does not support APE events */
6786 if (tg3_flag(tp, APE_HAS_NCSI))
6789 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6790 if (apedata != APE_SEG_SIG_MAGIC)
6793 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
6794 if (!(apedata & APE_FW_STATUS_READY))
6797 /* Wait for up to 1 millisecond for APE to service previous event. */
6798 for (i = 0; i < 10; i++) {
6799 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6802 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6804 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6805 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6806 event | APE_EVENT_STATUS_EVENT_PENDING);
6808 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6810 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6816 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6817 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6820 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6825 if (!tg3_flag(tp, ENABLE_APE))
6829 case RESET_KIND_INIT:
6830 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6831 APE_HOST_SEG_SIG_MAGIC);
6832 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6833 APE_HOST_SEG_LEN_MAGIC);
6834 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6835 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6836 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6837 APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
6838 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6839 APE_HOST_BEHAV_NO_PHYLOCK);
6840 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
6841 TG3_APE_HOST_DRVR_STATE_START);
6843 event = APE_EVENT_STATUS_STATE_START;
6845 case RESET_KIND_SHUTDOWN:
6846 /* With the interface we are currently using,
6847 * APE does not track driver state. Wiping
6848 * out the HOST SEGMENT SIGNATURE forces
6849 * the APE to assume OS absent status.
6851 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6853 if (device_may_wakeup(&tp->pdev->dev) &&
6854 tg3_flag(tp, WOL_ENABLE)) {
6855 tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
6856 TG3_APE_HOST_WOL_SPEED_AUTO);
6857 apedata = TG3_APE_HOST_DRVR_STATE_WOL;
6859 apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
6861 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
6863 event = APE_EVENT_STATUS_STATE_UNLOAD;
6865 case RESET_KIND_SUSPEND:
6866 event = APE_EVENT_STATUS_STATE_SUSPEND;
6872 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6874 tg3_ape_send_event(tp, event);
6877 /* tp->lock is held. */
6878 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6880 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6881 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6883 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
6885 case RESET_KIND_INIT:
6886 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6890 case RESET_KIND_SHUTDOWN:
6891 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6895 case RESET_KIND_SUSPEND:
6896 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6905 if (kind == RESET_KIND_INIT ||
6906 kind == RESET_KIND_SUSPEND)
6907 tg3_ape_driver_state_change(tp, kind);
6910 /* tp->lock is held. */
6911 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6913 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
6915 case RESET_KIND_INIT:
6916 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6917 DRV_STATE_START_DONE);
6920 case RESET_KIND_SHUTDOWN:
6921 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6922 DRV_STATE_UNLOAD_DONE);
6930 if (kind == RESET_KIND_SHUTDOWN)
6931 tg3_ape_driver_state_change(tp, kind);
6934 /* tp->lock is held. */
6935 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6937 if (tg3_flag(tp, ENABLE_ASF)) {
6939 case RESET_KIND_INIT:
6940 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6944 case RESET_KIND_SHUTDOWN:
6945 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6949 case RESET_KIND_SUSPEND:
6950 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6960 static int tg3_poll_fw(struct tg3 *tp)
6965 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6966 /* Wait up to 20ms for init done. */
6967 for (i = 0; i < 200; i++) {
6968 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6975 /* Wait for firmware initialization to complete. */
6976 for (i = 0; i < 100000; i++) {
6977 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6978 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6983 /* Chip might not be fitted with firmware. Some Sun onboard
6984 * parts are configured like that. So don't signal the timeout
6985 * of the above loop as an error, but do report the lack of
6986 * running firmware once.
6988 if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) {
6989 tg3_flag_set(tp, NO_FWARE_REPORTED);
6991 netdev_info(tp->dev, "No firmware running\n");
6994 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
6995 /* The 57765 A0 needs a little more
6996 * time to do some important work.
7004 /* Save PCI command register before chip reset */
7005 static void tg3_save_pci_state(struct tg3 *tp)
7007 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
7010 /* Restore PCI state after chip reset */
7011 static void tg3_restore_pci_state(struct tg3 *tp)
7015 /* Re-enable indirect register accesses. */
7016 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
7017 tp->misc_host_ctrl);
7019 /* Set MAX PCI retry to zero. */
7020 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
7021 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7022 tg3_flag(tp, PCIX_MODE))
7023 val |= PCISTATE_RETRY_SAME_DMA;
7024 /* Allow reads and writes to the APE register and memory space. */
7025 if (tg3_flag(tp, ENABLE_APE))
7026 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7027 PCISTATE_ALLOW_APE_SHMEM_WR |
7028 PCISTATE_ALLOW_APE_PSPACE_WR;
7029 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
7031 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
7033 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
7034 if (tg3_flag(tp, PCI_EXPRESS))
7035 pcie_set_readrq(tp->pdev, tp->pcie_readrq);
7037 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
7038 tp->pci_cacheline_sz);
7039 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
7044 /* Make sure PCI-X relaxed ordering bit is clear. */
7045 if (tg3_flag(tp, PCIX_MODE)) {
7048 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7050 pcix_cmd &= ~PCI_X_CMD_ERO;
7051 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7055 if (tg3_flag(tp, 5780_CLASS)) {
7057 /* Chip reset on 5780 will reset MSI enable bit,
7058 * so need to restore it.
7060 if (tg3_flag(tp, USING_MSI)) {
7063 pci_read_config_word(tp->pdev,
7064 tp->msi_cap + PCI_MSI_FLAGS,
7066 pci_write_config_word(tp->pdev,
7067 tp->msi_cap + PCI_MSI_FLAGS,
7068 ctrl | PCI_MSI_FLAGS_ENABLE);
7069 val = tr32(MSGINT_MODE);
7070 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
7075 static void tg3_stop_fw(struct tg3 *);
7077 /* tp->lock is held. */
7078 static int tg3_chip_reset(struct tg3 *tp)
7081 void (*write_op)(struct tg3 *, u32, u32);
7086 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
7088 /* No matching tg3_nvram_unlock() after this because
7089 * chip reset below will undo the nvram lock.
7091 tp->nvram_lock_cnt = 0;
7093 /* GRC_MISC_CFG core clock reset will clear the memory
7094 * enable bit in PCI register 4 and the MSI enable bit
7095 * on some chips, so we save relevant registers here.
7097 tg3_save_pci_state(tp);
7099 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
7100 tg3_flag(tp, 5755_PLUS))
7101 tw32(GRC_FASTBOOT_PC, 0);
7104 * We must avoid the readl() that normally takes place.
7105 * It locks machines, causes machine checks, and other
7106 * fun things. So, temporarily disable the 5701
7107 * hardware workaround, while we do the reset.
7109 write_op = tp->write32;
7110 if (write_op == tg3_write_flush_reg32)
7111 tp->write32 = tg3_write32;
7113 /* Prevent the irq handler from reading or writing PCI registers
7114 * during chip reset when the memory enable bit in the PCI command
7115 * register may be cleared. The chip does not generate interrupt
7116 * at this time, but the irq handler may still be called due to irq
7117 * sharing or irqpoll.
7119 tg3_flag_set(tp, CHIP_RESETTING);
7120 for (i = 0; i < tp->irq_cnt; i++) {
7121 struct tg3_napi *tnapi = &tp->napi[i];
7122 if (tnapi->hw_status) {
7123 tnapi->hw_status->status = 0;
7124 tnapi->hw_status->status_tag = 0;
7126 tnapi->last_tag = 0;
7127 tnapi->last_irq_tag = 0;
7131 for (i = 0; i < tp->irq_cnt; i++)
7132 synchronize_irq(tp->napi[i].irq_vec);
7134 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7135 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7136 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7140 val = GRC_MISC_CFG_CORECLK_RESET;
7142 if (tg3_flag(tp, PCI_EXPRESS)) {
7143 /* Force PCIe 1.0a mode */
7144 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7145 !tg3_flag(tp, 57765_PLUS) &&
7146 tr32(TG3_PCIE_PHY_TSTCTL) ==
7147 (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
7148 tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
7150 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
7151 tw32(GRC_MISC_CFG, (1 << 29));
7156 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7157 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
7158 tw32(GRC_VCPU_EXT_CTRL,
7159 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
7162 /* Manage gphy power for all CPMU absent PCIe devices. */
7163 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, CPMU_PRESENT))
7164 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
7166 tw32(GRC_MISC_CFG, val);
7168 /* restore 5701 hardware bug workaround write method */
7169 tp->write32 = write_op;
7171 /* Unfortunately, we have to delay before the PCI read back.
7172 * Some 575X chips even will not respond to a PCI cfg access
7173 * when the reset command is given to the chip.
7175 * How do these hardware designers expect things to work
7176 * properly if the PCI write is posted for a long period
7177 * of time? It is always necessary to have some method by
7178 * which a register read back can occur to push the write
7179 * out which does the reset.
7181 * For most tg3 variants the trick below was working.
7186 /* Flush PCI posted writes. The normal MMIO registers
7187 * are inaccessible at this time so this is the only
7188 * way to make this reliably (actually, this is no longer
7189 * the case, see above). I tried to use indirect
7190 * register read/write but this upset some 5701 variants.
7192 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
7196 if (tg3_flag(tp, PCI_EXPRESS) && tp->pcie_cap) {
7199 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
7203 /* Wait for link training to complete. */
7204 for (i = 0; i < 5000; i++)
7207 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
7208 pci_write_config_dword(tp->pdev, 0xc4,
7209 cfg_val | (1 << 15));
7212 /* Clear the "no snoop" and "relaxed ordering" bits. */
7213 pci_read_config_word(tp->pdev,
7214 tp->pcie_cap + PCI_EXP_DEVCTL,
7216 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
7217 PCI_EXP_DEVCTL_NOSNOOP_EN);
7219 * Older PCIe devices only support the 128 byte
7220 * MPS setting. Enforce the restriction.
7222 if (!tg3_flag(tp, CPMU_PRESENT))
7223 val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
7224 pci_write_config_word(tp->pdev,
7225 tp->pcie_cap + PCI_EXP_DEVCTL,
7228 pcie_set_readrq(tp->pdev, tp->pcie_readrq);
7230 /* Clear error status */
7231 pci_write_config_word(tp->pdev,
7232 tp->pcie_cap + PCI_EXP_DEVSTA,
7233 PCI_EXP_DEVSTA_CED |
7234 PCI_EXP_DEVSTA_NFED |
7235 PCI_EXP_DEVSTA_FED |
7236 PCI_EXP_DEVSTA_URD);
7239 tg3_restore_pci_state(tp);
7241 tg3_flag_clear(tp, CHIP_RESETTING);
7242 tg3_flag_clear(tp, ERROR_PROCESSED);
7245 if (tg3_flag(tp, 5780_CLASS))
7246 val = tr32(MEMARB_MODE);
7247 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
7249 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
7251 tw32(0x5000, 0x400);
7254 tw32(GRC_MODE, tp->grc_mode);
7256 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
7259 tw32(0xc4, val | (1 << 15));
7262 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
7263 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7264 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
7265 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
7266 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
7267 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7270 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
7271 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
7273 } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
7274 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
7279 tw32_f(MAC_MODE, val);
7282 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
7284 err = tg3_poll_fw(tp);
7290 if (tg3_flag(tp, PCI_EXPRESS) &&
7291 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
7292 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7293 !tg3_flag(tp, 57765_PLUS)) {
7296 tw32(0x7c00, val | (1 << 25));
7299 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
7300 val = tr32(TG3_CPMU_CLCK_ORIDE);
7301 tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
7304 /* Reprobe ASF enable state. */
7305 tg3_flag_clear(tp, ENABLE_ASF);
7306 tg3_flag_clear(tp, ASF_NEW_HANDSHAKE);
7307 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
7308 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
7311 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
7312 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
7313 tg3_flag_set(tp, ENABLE_ASF);
7314 tp->last_event_jiffies = jiffies;
7315 if (tg3_flag(tp, 5750_PLUS))
7316 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
7323 /* tp->lock is held. */
7324 static void tg3_stop_fw(struct tg3 *tp)
7326 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
7327 /* Wait for RX cpu to ACK the previous event. */
7328 tg3_wait_for_event_ack(tp);
7330 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
7332 tg3_generate_fw_event(tp);
7334 /* Wait for RX cpu to ACK this event. */
7335 tg3_wait_for_event_ack(tp);
7339 /* tp->lock is held. */
7340 static int tg3_halt(struct tg3 *tp, int kind, int silent)
7346 tg3_write_sig_pre_reset(tp, kind);
7348 tg3_abort_hw(tp, silent);
7349 err = tg3_chip_reset(tp);
7351 __tg3_set_mac_addr(tp, 0);
7353 tg3_write_sig_legacy(tp, kind);
7354 tg3_write_sig_post_reset(tp, kind);
7362 #define RX_CPU_SCRATCH_BASE 0x30000
7363 #define RX_CPU_SCRATCH_SIZE 0x04000
7364 #define TX_CPU_SCRATCH_BASE 0x34000
7365 #define TX_CPU_SCRATCH_SIZE 0x04000
7367 /* tp->lock is held. */
7368 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
7372 BUG_ON(offset == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS));
7374 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7375 u32 val = tr32(GRC_VCPU_EXT_CTRL);
7377 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
7380 if (offset == RX_CPU_BASE) {
7381 for (i = 0; i < 10000; i++) {
7382 tw32(offset + CPU_STATE, 0xffffffff);
7383 tw32(offset + CPU_MODE, CPU_MODE_HALT);
7384 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7388 tw32(offset + CPU_STATE, 0xffffffff);
7389 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
7392 for (i = 0; i < 10000; i++) {
7393 tw32(offset + CPU_STATE, 0xffffffff);
7394 tw32(offset + CPU_MODE, CPU_MODE_HALT);
7395 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7401 netdev_err(tp->dev, "%s timed out, %s CPU\n",
7402 __func__, offset == RX_CPU_BASE ? "RX" : "TX");
7406 /* Clear firmware's nvram arbitration. */
7407 if (tg3_flag(tp, NVRAM))
7408 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
7413 unsigned int fw_base;
7414 unsigned int fw_len;
7415 const __be32 *fw_data;
7418 /* tp->lock is held. */
7419 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
7420 int cpu_scratch_size, struct fw_info *info)
7422 int err, lock_err, i;
7423 void (*write_op)(struct tg3 *, u32, u32);
7425 if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) {
7427 "%s: Trying to load TX cpu firmware which is 5705\n",
7432 if (tg3_flag(tp, 5705_PLUS))
7433 write_op = tg3_write_mem;
7435 write_op = tg3_write_indirect_reg32;
7437 /* It is possible that bootcode is still loading at this point.
7438 * Get the nvram lock first before halting the cpu.
7440 lock_err = tg3_nvram_lock(tp);
7441 err = tg3_halt_cpu(tp, cpu_base);
7443 tg3_nvram_unlock(tp);
7447 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
7448 write_op(tp, cpu_scratch_base + i, 0);
7449 tw32(cpu_base + CPU_STATE, 0xffffffff);
7450 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
7451 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
7452 write_op(tp, (cpu_scratch_base +
7453 (info->fw_base & 0xffff) +
7455 be32_to_cpu(info->fw_data[i]));
7463 /* tp->lock is held. */
7464 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
7466 struct fw_info info;
7467 const __be32 *fw_data;
7470 fw_data = (void *)tp->fw->data;
7472 /* Firmware blob starts with version numbers, followed by
7473 start address and length. We are setting complete length.
7474 length = end_address_of_bss - start_address_of_text.
7475 Remainder is the blob to be loaded contiguously
7476 from start address. */
7478 info.fw_base = be32_to_cpu(fw_data[1]);
7479 info.fw_len = tp->fw->size - 12;
7480 info.fw_data = &fw_data[3];
7482 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
7483 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
7488 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
7489 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
7494 /* Now startup only the RX cpu. */
7495 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7496 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7498 for (i = 0; i < 5; i++) {
7499 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
7501 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7502 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
7503 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7507 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
7508 "should be %08x\n", __func__,
7509 tr32(RX_CPU_BASE + CPU_PC), info.fw_base);
7512 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7513 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
7518 /* tp->lock is held. */
7519 static int tg3_load_tso_firmware(struct tg3 *tp)
7521 struct fw_info info;
7522 const __be32 *fw_data;
7523 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
7526 if (tg3_flag(tp, HW_TSO_1) ||
7527 tg3_flag(tp, HW_TSO_2) ||
7528 tg3_flag(tp, HW_TSO_3))
7531 fw_data = (void *)tp->fw->data;
7533 /* Firmware blob starts with version numbers, followed by
7534 start address and length. We are setting complete length.
7535 length = end_address_of_bss - start_address_of_text.
7536 Remainder is the blob to be loaded contiguously
7537 from start address. */
7539 info.fw_base = be32_to_cpu(fw_data[1]);
7540 cpu_scratch_size = tp->fw_len;
7541 info.fw_len = tp->fw->size - 12;
7542 info.fw_data = &fw_data[3];
7544 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7545 cpu_base = RX_CPU_BASE;
7546 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
7548 cpu_base = TX_CPU_BASE;
7549 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
7550 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
7553 err = tg3_load_firmware_cpu(tp, cpu_base,
7554 cpu_scratch_base, cpu_scratch_size,
7559 /* Now startup the cpu. */
7560 tw32(cpu_base + CPU_STATE, 0xffffffff);
7561 tw32_f(cpu_base + CPU_PC, info.fw_base);
7563 for (i = 0; i < 5; i++) {
7564 if (tr32(cpu_base + CPU_PC) == info.fw_base)
7566 tw32(cpu_base + CPU_STATE, 0xffffffff);
7567 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
7568 tw32_f(cpu_base + CPU_PC, info.fw_base);
7573 "%s fails to set CPU PC, is %08x should be %08x\n",
7574 __func__, tr32(cpu_base + CPU_PC), info.fw_base);
7577 tw32(cpu_base + CPU_STATE, 0xffffffff);
7578 tw32_f(cpu_base + CPU_MODE, 0x00000000);
7583 static int tg3_set_mac_addr(struct net_device *dev, void *p)
7585 struct tg3 *tp = netdev_priv(dev);
7586 struct sockaddr *addr = p;
7587 int err = 0, skip_mac_1 = 0;
7589 if (!is_valid_ether_addr(addr->sa_data))
7592 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7594 if (!netif_running(dev))
7597 if (tg3_flag(tp, ENABLE_ASF)) {
7598 u32 addr0_high, addr0_low, addr1_high, addr1_low;
7600 addr0_high = tr32(MAC_ADDR_0_HIGH);
7601 addr0_low = tr32(MAC_ADDR_0_LOW);
7602 addr1_high = tr32(MAC_ADDR_1_HIGH);
7603 addr1_low = tr32(MAC_ADDR_1_LOW);
7605 /* Skip MAC addr 1 if ASF is using it. */
7606 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7607 !(addr1_high == 0 && addr1_low == 0))
7610 spin_lock_bh(&tp->lock);
7611 __tg3_set_mac_addr(tp, skip_mac_1);
7612 spin_unlock_bh(&tp->lock);
7617 /* tp->lock is held. */
7618 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7619 dma_addr_t mapping, u32 maxlen_flags,
7623 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7624 ((u64) mapping >> 32));
7626 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7627 ((u64) mapping & 0xffffffff));
7629 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7632 if (!tg3_flag(tp, 5705_PLUS))
7634 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7638 static void __tg3_set_rx_mode(struct net_device *);
7639 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7643 if (!tg3_flag(tp, ENABLE_TSS)) {
7644 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7645 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7646 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7648 tw32(HOSTCC_TXCOL_TICKS, 0);
7649 tw32(HOSTCC_TXMAX_FRAMES, 0);
7650 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7653 if (!tg3_flag(tp, ENABLE_RSS)) {
7654 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7655 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7656 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7658 tw32(HOSTCC_RXCOL_TICKS, 0);
7659 tw32(HOSTCC_RXMAX_FRAMES, 0);
7660 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
7663 if (!tg3_flag(tp, 5705_PLUS)) {
7664 u32 val = ec->stats_block_coalesce_usecs;
7666 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7667 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7669 if (!netif_carrier_ok(tp->dev))
7672 tw32(HOSTCC_STAT_COAL_TICKS, val);
7675 for (i = 0; i < tp->irq_cnt - 1; i++) {
7678 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7679 tw32(reg, ec->rx_coalesce_usecs);
7680 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7681 tw32(reg, ec->rx_max_coalesced_frames);
7682 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7683 tw32(reg, ec->rx_max_coalesced_frames_irq);
7685 if (tg3_flag(tp, ENABLE_TSS)) {
7686 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7687 tw32(reg, ec->tx_coalesce_usecs);
7688 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7689 tw32(reg, ec->tx_max_coalesced_frames);
7690 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7691 tw32(reg, ec->tx_max_coalesced_frames_irq);
7695 for (; i < tp->irq_max - 1; i++) {
7696 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7697 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7698 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7700 if (tg3_flag(tp, ENABLE_TSS)) {
7701 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7702 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7703 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7708 /* tp->lock is held. */
7709 static void tg3_rings_reset(struct tg3 *tp)
7712 u32 stblk, txrcb, rxrcb, limit;
7713 struct tg3_napi *tnapi = &tp->napi[0];
7715 /* Disable all transmit rings but the first. */
7716 if (!tg3_flag(tp, 5705_PLUS))
7717 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7718 else if (tg3_flag(tp, 5717_PLUS))
7719 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
7720 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7721 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
7723 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7725 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7726 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7727 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7728 BDINFO_FLAGS_DISABLED);
7731 /* Disable all receive return rings but the first. */
7732 if (tg3_flag(tp, 5717_PLUS))
7733 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7734 else if (!tg3_flag(tp, 5705_PLUS))
7735 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7736 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7737 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7738 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7740 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7742 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7743 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7744 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7745 BDINFO_FLAGS_DISABLED);
7747 /* Disable interrupts */
7748 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7750 /* Zero mailbox registers. */
7751 if (tg3_flag(tp, SUPPORT_MSIX)) {
7752 for (i = 1; i < tp->irq_max; i++) {
7753 tp->napi[i].tx_prod = 0;
7754 tp->napi[i].tx_cons = 0;
7755 if (tg3_flag(tp, ENABLE_TSS))
7756 tw32_mailbox(tp->napi[i].prodmbox, 0);
7757 tw32_rx_mbox(tp->napi[i].consmbox, 0);
7758 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7760 if (!tg3_flag(tp, ENABLE_TSS))
7761 tw32_mailbox(tp->napi[0].prodmbox, 0);
7763 tp->napi[0].tx_prod = 0;
7764 tp->napi[0].tx_cons = 0;
7765 tw32_mailbox(tp->napi[0].prodmbox, 0);
7766 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7769 /* Make sure the NIC-based send BD rings are disabled. */
7770 if (!tg3_flag(tp, 5705_PLUS)) {
7771 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7772 for (i = 0; i < 16; i++)
7773 tw32_tx_mbox(mbox + i * 8, 0);
7776 txrcb = NIC_SRAM_SEND_RCB;
7777 rxrcb = NIC_SRAM_RCV_RET_RCB;
7779 /* Clear status block in ram. */
7780 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7782 /* Set status block DMA address */
7783 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7784 ((u64) tnapi->status_mapping >> 32));
7785 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7786 ((u64) tnapi->status_mapping & 0xffffffff));
7788 if (tnapi->tx_ring) {
7789 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7790 (TG3_TX_RING_SIZE <<
7791 BDINFO_FLAGS_MAXLEN_SHIFT),
7792 NIC_SRAM_TX_BUFFER_DESC);
7793 txrcb += TG3_BDINFO_SIZE;
7796 if (tnapi->rx_rcb) {
7797 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7798 (tp->rx_ret_ring_mask + 1) <<
7799 BDINFO_FLAGS_MAXLEN_SHIFT, 0);
7800 rxrcb += TG3_BDINFO_SIZE;
7803 stblk = HOSTCC_STATBLCK_RING1;
7805 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7806 u64 mapping = (u64)tnapi->status_mapping;
7807 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7808 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7810 /* Clear status block in ram. */
7811 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7813 if (tnapi->tx_ring) {
7814 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7815 (TG3_TX_RING_SIZE <<
7816 BDINFO_FLAGS_MAXLEN_SHIFT),
7817 NIC_SRAM_TX_BUFFER_DESC);
7818 txrcb += TG3_BDINFO_SIZE;
7821 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7822 ((tp->rx_ret_ring_mask + 1) <<
7823 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7826 rxrcb += TG3_BDINFO_SIZE;
7830 static void tg3_setup_rxbd_thresholds(struct tg3 *tp)
7832 u32 val, bdcache_maxcnt, host_rep_thresh, nic_rep_thresh;
7834 if (!tg3_flag(tp, 5750_PLUS) ||
7835 tg3_flag(tp, 5780_CLASS) ||
7836 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
7837 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7838 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5700;
7839 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7840 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
7841 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5755;
7843 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5906;
7845 nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post);
7846 host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1);
7848 val = min(nic_rep_thresh, host_rep_thresh);
7849 tw32(RCVBDI_STD_THRESH, val);
7851 if (tg3_flag(tp, 57765_PLUS))
7852 tw32(STD_REPLENISH_LWM, bdcache_maxcnt);
7854 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
7857 if (!tg3_flag(tp, 5705_PLUS))
7858 bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700;
7860 bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5717;
7862 host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1);
7864 val = min(bdcache_maxcnt / 2, host_rep_thresh);
7865 tw32(RCVBDI_JUMBO_THRESH, val);
7867 if (tg3_flag(tp, 57765_PLUS))
7868 tw32(JMB_REPLENISH_LWM, bdcache_maxcnt);
7871 /* tp->lock is held. */
7872 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7874 u32 val, rdmac_mode;
7876 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
7878 tg3_disable_ints(tp);
7882 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7884 if (tg3_flag(tp, INIT_COMPLETE))
7885 tg3_abort_hw(tp, 1);
7887 /* Enable MAC control of LPI */
7888 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
7889 tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL,
7890 TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
7891 TG3_CPMU_EEE_LNKIDL_UART_IDL);
7893 tw32_f(TG3_CPMU_EEE_CTRL,
7894 TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
7896 val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
7897 TG3_CPMU_EEEMD_LPI_IN_TX |
7898 TG3_CPMU_EEEMD_LPI_IN_RX |
7899 TG3_CPMU_EEEMD_EEE_ENABLE;
7901 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
7902 val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN;
7904 if (tg3_flag(tp, ENABLE_APE))
7905 val |= TG3_CPMU_EEEMD_APE_TX_DET_EN;
7907 tw32_f(TG3_CPMU_EEE_MODE, val);
7909 tw32_f(TG3_CPMU_EEE_DBTMR1,
7910 TG3_CPMU_DBTMR1_PCIEXIT_2047US |
7911 TG3_CPMU_DBTMR1_LNKIDLE_2047US);
7913 tw32_f(TG3_CPMU_EEE_DBTMR2,
7914 TG3_CPMU_DBTMR2_APE_TX_2047US |
7915 TG3_CPMU_DBTMR2_TXIDXEQ_2047US);
7921 err = tg3_chip_reset(tp);
7925 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7927 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
7928 val = tr32(TG3_CPMU_CTRL);
7929 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7930 tw32(TG3_CPMU_CTRL, val);
7932 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7933 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7934 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7935 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7937 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7938 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7939 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7940 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7942 val = tr32(TG3_CPMU_HST_ACC);
7943 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7944 val |= CPMU_HST_ACC_MACCLK_6_25;
7945 tw32(TG3_CPMU_HST_ACC, val);
7948 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7949 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7950 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7951 PCIE_PWR_MGMT_L1_THRESH_4MS;
7952 tw32(PCIE_PWR_MGMT_THRESH, val);
7954 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7955 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7957 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
7959 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7960 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7963 if (tg3_flag(tp, L1PLLPD_EN)) {
7964 u32 grc_mode = tr32(GRC_MODE);
7966 /* Access the lower 1K of PL PCIE block registers. */
7967 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7968 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7970 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
7971 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
7972 val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
7974 tw32(GRC_MODE, grc_mode);
7977 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
7978 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
7979 u32 grc_mode = tr32(GRC_MODE);
7981 /* Access the lower 1K of PL PCIE block registers. */
7982 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7983 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7985 val = tr32(TG3_PCIE_TLDLPL_PORT +
7986 TG3_PCIE_PL_LO_PHYCTL5);
7987 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
7988 val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
7990 tw32(GRC_MODE, grc_mode);
7993 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_57765_AX) {
7994 u32 grc_mode = tr32(GRC_MODE);
7996 /* Access the lower 1K of DL PCIE block registers. */
7997 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7998 tw32(GRC_MODE, val | GRC_MODE_PCIE_DL_SEL);
8000 val = tr32(TG3_PCIE_TLDLPL_PORT +
8001 TG3_PCIE_DL_LO_FTSMAX);
8002 val &= ~TG3_PCIE_DL_LO_FTSMAX_MSK;
8003 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX,
8004 val | TG3_PCIE_DL_LO_FTSMAX_VAL);
8006 tw32(GRC_MODE, grc_mode);
8009 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
8010 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
8011 val |= CPMU_LSPD_10MB_MACCLK_6_25;
8012 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
8015 /* This works around an issue with Athlon chipsets on
8016 * B3 tigon3 silicon. This bit has no effect on any
8017 * other revision. But do not set this on PCI Express
8018 * chips and don't even touch the clocks if the CPMU is present.
8020 if (!tg3_flag(tp, CPMU_PRESENT)) {
8021 if (!tg3_flag(tp, PCI_EXPRESS))
8022 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
8023 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
8026 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
8027 tg3_flag(tp, PCIX_MODE)) {
8028 val = tr32(TG3PCI_PCISTATE);
8029 val |= PCISTATE_RETRY_SAME_DMA;
8030 tw32(TG3PCI_PCISTATE, val);
8033 if (tg3_flag(tp, ENABLE_APE)) {
8034 /* Allow reads and writes to the
8035 * APE register and memory space.
8037 val = tr32(TG3PCI_PCISTATE);
8038 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
8039 PCISTATE_ALLOW_APE_SHMEM_WR |
8040 PCISTATE_ALLOW_APE_PSPACE_WR;
8041 tw32(TG3PCI_PCISTATE, val);
8044 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
8045 /* Enable some hw fixes. */
8046 val = tr32(TG3PCI_MSI_DATA);
8047 val |= (1 << 26) | (1 << 28) | (1 << 29);
8048 tw32(TG3PCI_MSI_DATA, val);
8051 /* Descriptor ring init may make accesses to the
8052 * NIC SRAM area to setup the TX descriptors, so we
8053 * can only do this after the hardware has been
8054 * successfully reset.
8056 err = tg3_init_rings(tp);
8060 if (tg3_flag(tp, 57765_PLUS)) {
8061 val = tr32(TG3PCI_DMA_RW_CTRL) &
8062 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
8063 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0)
8064 val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
8065 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765 &&
8066 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
8067 val |= DMA_RWCTRL_TAGGED_STAT_WA;
8068 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
8069 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
8070 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
8071 /* This value is determined during the probe time DMA
8072 * engine test, tg3_test_dma.
8074 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
8077 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
8078 GRC_MODE_4X_NIC_SEND_RINGS |
8079 GRC_MODE_NO_TX_PHDR_CSUM |
8080 GRC_MODE_NO_RX_PHDR_CSUM);
8081 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
8083 /* Pseudo-header checksum is done by hardware logic and not
8084 * the offload processers, so make the chip do the pseudo-
8085 * header checksums on receive. For transmit it is more
8086 * convenient to do the pseudo-header checksum in software
8087 * as Linux does that on transmit for us in all cases.
8089 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
8093 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
8095 /* Setup the timer prescalar register. Clock is always 66Mhz. */
8096 val = tr32(GRC_MISC_CFG);
8098 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
8099 tw32(GRC_MISC_CFG, val);
8101 /* Initialize MBUF/DESC pool. */
8102 if (tg3_flag(tp, 5750_PLUS)) {
8104 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
8105 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
8106 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
8107 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
8109 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
8110 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
8111 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
8112 } else if (tg3_flag(tp, TSO_CAPABLE)) {
8115 fw_len = tp->fw_len;
8116 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
8117 tw32(BUFMGR_MB_POOL_ADDR,
8118 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
8119 tw32(BUFMGR_MB_POOL_SIZE,
8120 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
8123 if (tp->dev->mtu <= ETH_DATA_LEN) {
8124 tw32(BUFMGR_MB_RDMA_LOW_WATER,
8125 tp->bufmgr_config.mbuf_read_dma_low_water);
8126 tw32(BUFMGR_MB_MACRX_LOW_WATER,
8127 tp->bufmgr_config.mbuf_mac_rx_low_water);
8128 tw32(BUFMGR_MB_HIGH_WATER,
8129 tp->bufmgr_config.mbuf_high_water);
8131 tw32(BUFMGR_MB_RDMA_LOW_WATER,
8132 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
8133 tw32(BUFMGR_MB_MACRX_LOW_WATER,
8134 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
8135 tw32(BUFMGR_MB_HIGH_WATER,
8136 tp->bufmgr_config.mbuf_high_water_jumbo);
8138 tw32(BUFMGR_DMA_LOW_WATER,
8139 tp->bufmgr_config.dma_low_water);
8140 tw32(BUFMGR_DMA_HIGH_WATER,
8141 tp->bufmgr_config.dma_high_water);
8143 val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;
8144 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
8145 val |= BUFMGR_MODE_NO_TX_UNDERRUN;
8146 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8147 tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 ||
8148 tp->pci_chip_rev_id == CHIPREV_ID_5720_A0)
8149 val |= BUFMGR_MODE_MBLOW_ATTN_ENAB;
8150 tw32(BUFMGR_MODE, val);
8151 for (i = 0; i < 2000; i++) {
8152 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
8157 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
8161 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
8162 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
8164 tg3_setup_rxbd_thresholds(tp);
8166 /* Initialize TG3_BDINFO's at:
8167 * RCVDBDI_STD_BD: standard eth size rx ring
8168 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
8169 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
8172 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
8173 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
8174 * ring attribute flags
8175 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
8177 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
8178 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
8180 * The size of each ring is fixed in the firmware, but the location is
8183 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
8184 ((u64) tpr->rx_std_mapping >> 32));
8185 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
8186 ((u64) tpr->rx_std_mapping & 0xffffffff));
8187 if (!tg3_flag(tp, 5717_PLUS))
8188 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
8189 NIC_SRAM_RX_BUFFER_DESC);
8191 /* Disable the mini ring */
8192 if (!tg3_flag(tp, 5705_PLUS))
8193 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
8194 BDINFO_FLAGS_DISABLED);
8196 /* Program the jumbo buffer descriptor ring control
8197 * blocks on those devices that have them.
8199 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
8200 (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) {
8202 if (tg3_flag(tp, JUMBO_RING_ENABLE)) {
8203 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
8204 ((u64) tpr->rx_jmb_mapping >> 32));
8205 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
8206 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
8207 val = TG3_RX_JMB_RING_SIZE(tp) <<
8208 BDINFO_FLAGS_MAXLEN_SHIFT;
8209 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
8210 val | BDINFO_FLAGS_USE_EXT_RECV);
8211 if (!tg3_flag(tp, USE_JUMBO_BDFLAG) ||
8212 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8213 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
8214 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
8216 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
8217 BDINFO_FLAGS_DISABLED);
8220 if (tg3_flag(tp, 57765_PLUS)) {
8221 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8222 val = TG3_RX_STD_MAX_SIZE_5700;
8224 val = TG3_RX_STD_MAX_SIZE_5717;
8225 val <<= BDINFO_FLAGS_MAXLEN_SHIFT;
8226 val |= (TG3_RX_STD_DMA_SZ << 2);
8228 val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
8230 val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT;
8232 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
8234 tpr->rx_std_prod_idx = tp->rx_pending;
8235 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
8237 tpr->rx_jmb_prod_idx =
8238 tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0;
8239 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
8241 tg3_rings_reset(tp);
8243 /* Initialize MAC address and backoff seed. */
8244 __tg3_set_mac_addr(tp, 0);
8246 /* MTU + ethernet header + FCS + optional VLAN tag */
8247 tw32(MAC_RX_MTU_SIZE,
8248 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
8250 /* The slot time is changed by tg3_setup_phy if we
8251 * run at gigabit with half duplex.
8253 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
8254 (6 << TX_LENGTHS_IPG_SHIFT) |
8255 (32 << TX_LENGTHS_SLOT_TIME_SHIFT);
8257 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
8258 val |= tr32(MAC_TX_LENGTHS) &
8259 (TX_LENGTHS_JMB_FRM_LEN_MSK |
8260 TX_LENGTHS_CNT_DWN_VAL_MSK);
8262 tw32(MAC_TX_LENGTHS, val);
8264 /* Receive rules. */
8265 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
8266 tw32(RCVLPC_CONFIG, 0x0181);
8268 /* Calculate RDMAC_MODE setting early, we need it to determine
8269 * the RCVLPC_STATE_ENABLE mask.
8271 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
8272 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
8273 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
8274 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
8275 RDMAC_MODE_LNGREAD_ENAB);
8277 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
8278 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
8280 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8281 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8282 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8283 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
8284 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
8285 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
8287 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8288 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
8289 if (tg3_flag(tp, TSO_CAPABLE) &&
8290 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
8291 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
8292 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8293 !tg3_flag(tp, IS_5788)) {
8294 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8298 if (tg3_flag(tp, PCI_EXPRESS))
8299 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8301 if (tg3_flag(tp, HW_TSO_1) ||
8302 tg3_flag(tp, HW_TSO_2) ||
8303 tg3_flag(tp, HW_TSO_3))
8304 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
8306 if (tg3_flag(tp, 57765_PLUS) ||
8307 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8308 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8309 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
8311 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
8312 rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET;
8314 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
8315 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8316 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8317 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
8318 tg3_flag(tp, 57765_PLUS)) {
8319 val = tr32(TG3_RDMA_RSRVCTRL_REG);
8320 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
8321 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
8322 val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK |
8323 TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK |
8324 TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK);
8325 val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B |
8326 TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
8327 TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K;
8329 tw32(TG3_RDMA_RSRVCTRL_REG,
8330 val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
8333 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
8334 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
8335 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
8336 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val |
8337 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
8338 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K);
8341 /* Receive/send statistics. */
8342 if (tg3_flag(tp, 5750_PLUS)) {
8343 val = tr32(RCVLPC_STATS_ENABLE);
8344 val &= ~RCVLPC_STATSENAB_DACK_FIX;
8345 tw32(RCVLPC_STATS_ENABLE, val);
8346 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
8347 tg3_flag(tp, TSO_CAPABLE)) {
8348 val = tr32(RCVLPC_STATS_ENABLE);
8349 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
8350 tw32(RCVLPC_STATS_ENABLE, val);
8352 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
8354 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
8355 tw32(SNDDATAI_STATSENAB, 0xffffff);
8356 tw32(SNDDATAI_STATSCTRL,
8357 (SNDDATAI_SCTRL_ENABLE |
8358 SNDDATAI_SCTRL_FASTUPD));
8360 /* Setup host coalescing engine. */
8361 tw32(HOSTCC_MODE, 0);
8362 for (i = 0; i < 2000; i++) {
8363 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
8368 __tg3_set_coalesce(tp, &tp->coal);
8370 if (!tg3_flag(tp, 5705_PLUS)) {
8371 /* Status/statistics block address. See tg3_timer,
8372 * the tg3_periodic_fetch_stats call there, and
8373 * tg3_get_stats to see how this works for 5705/5750 chips.
8375 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
8376 ((u64) tp->stats_mapping >> 32));
8377 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
8378 ((u64) tp->stats_mapping & 0xffffffff));
8379 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
8381 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
8383 /* Clear statistics and status block memory areas */
8384 for (i = NIC_SRAM_STATS_BLK;
8385 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
8387 tg3_write_mem(tp, i, 0);
8392 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
8394 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
8395 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
8396 if (!tg3_flag(tp, 5705_PLUS))
8397 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
8399 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
8400 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
8401 /* reset to prevent losing 1st rx packet intermittently */
8402 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8406 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
8407 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE |
8408 MAC_MODE_FHDE_ENABLE;
8409 if (tg3_flag(tp, ENABLE_APE))
8410 tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
8411 if (!tg3_flag(tp, 5705_PLUS) &&
8412 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
8413 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
8414 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8415 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
8418 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
8419 * If TG3_FLAG_IS_NIC is zero, we should read the
8420 * register to preserve the GPIO settings for LOMs. The GPIOs,
8421 * whether used as inputs or outputs, are set by boot code after
8424 if (!tg3_flag(tp, IS_NIC)) {
8427 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
8428 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
8429 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
8431 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8432 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
8433 GRC_LCLCTRL_GPIO_OUTPUT3;
8435 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
8436 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
8438 tp->grc_local_ctrl &= ~gpio_mask;
8439 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
8441 /* GPIO1 must be driven high for eeprom write protect */
8442 if (tg3_flag(tp, EEPROM_WRITE_PROT))
8443 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
8444 GRC_LCLCTRL_GPIO_OUTPUT1);
8446 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8449 if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1) {
8450 val = tr32(MSGINT_MODE);
8451 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
8452 tw32(MSGINT_MODE, val);
8455 if (!tg3_flag(tp, 5705_PLUS)) {
8456 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
8460 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
8461 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
8462 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
8463 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
8464 WDMAC_MODE_LNGREAD_ENAB);
8466 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8467 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
8468 if (tg3_flag(tp, TSO_CAPABLE) &&
8469 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
8470 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
8472 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8473 !tg3_flag(tp, IS_5788)) {
8474 val |= WDMAC_MODE_RX_ACCEL;
8478 /* Enable host coalescing bug fix */
8479 if (tg3_flag(tp, 5755_PLUS))
8480 val |= WDMAC_MODE_STATUS_TAG_FIX;
8482 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8483 val |= WDMAC_MODE_BURST_ALL_DATA;
8485 tw32_f(WDMAC_MODE, val);
8488 if (tg3_flag(tp, PCIX_MODE)) {
8491 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8493 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
8494 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
8495 pcix_cmd |= PCI_X_CMD_READ_2K;
8496 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
8497 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8498 pcix_cmd |= PCI_X_CMD_READ_2K;
8500 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8504 tw32_f(RDMAC_MODE, rdmac_mode);
8507 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8508 if (!tg3_flag(tp, 5705_PLUS))
8509 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
8511 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8513 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8515 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8517 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8518 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8519 val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ;
8520 if (tg3_flag(tp, LRG_PROD_RING_CAP))
8521 val |= RCVDBDI_MODE_LRG_RING_SZ;
8522 tw32(RCVDBDI_MODE, val);
8523 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
8524 if (tg3_flag(tp, HW_TSO_1) ||
8525 tg3_flag(tp, HW_TSO_2) ||
8526 tg3_flag(tp, HW_TSO_3))
8527 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
8528 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
8529 if (tg3_flag(tp, ENABLE_TSS))
8530 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8531 tw32(SNDBDI_MODE, val);
8532 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8534 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8535 err = tg3_load_5701_a0_firmware_fix(tp);
8540 if (tg3_flag(tp, TSO_CAPABLE)) {
8541 err = tg3_load_tso_firmware(tp);
8546 tp->tx_mode = TX_MODE_ENABLE;
8548 if (tg3_flag(tp, 5755_PLUS) ||
8549 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8550 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
8552 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
8553 val = TX_MODE_JMB_FRM_LEN | TX_MODE_CNT_DN_MODE;
8554 tp->tx_mode &= ~val;
8555 tp->tx_mode |= tr32(MAC_TX_MODE) & val;
8558 tw32_f(MAC_TX_MODE, tp->tx_mode);
8561 if (tg3_flag(tp, ENABLE_RSS)) {
8562 u32 reg = MAC_RSS_INDIR_TBL_0;
8563 u8 *ent = (u8 *)&val;
8565 /* Setup the indirection table */
8566 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8567 int idx = i % sizeof(val);
8569 ent[idx] = i % (tp->irq_cnt - 1);
8570 if (idx == sizeof(val) - 1) {
8576 /* Setup the "secret" hash key. */
8577 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8578 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8579 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8580 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8581 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8582 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8583 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8584 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8585 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8586 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8589 tp->rx_mode = RX_MODE_ENABLE;
8590 if (tg3_flag(tp, 5755_PLUS))
8591 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8593 if (tg3_flag(tp, ENABLE_RSS))
8594 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8595 RX_MODE_RSS_ITBL_HASH_BITS_7 |
8596 RX_MODE_RSS_IPV6_HASH_EN |
8597 RX_MODE_RSS_TCP_IPV6_HASH_EN |
8598 RX_MODE_RSS_IPV4_HASH_EN |
8599 RX_MODE_RSS_TCP_IPV4_HASH_EN;
8601 tw32_f(MAC_RX_MODE, tp->rx_mode);
8604 tw32(MAC_LED_CTRL, tp->led_ctrl);
8606 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
8607 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
8608 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8611 tw32_f(MAC_RX_MODE, tp->rx_mode);
8614 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
8615 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
8616 !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
8617 /* Set drive transmission level to 1.2V */
8618 /* only if the signal pre-emphasis bit is not set */
8619 val = tr32(MAC_SERDES_CFG);
8622 tw32(MAC_SERDES_CFG, val);
8624 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
8625 tw32(MAC_SERDES_CFG, 0x616000);
8628 /* Prevent chip from dropping frames when flow control
8631 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8635 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
8637 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8638 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
8639 /* Use hardware link auto-negotiation */
8640 tg3_flag_set(tp, HW_AUTONEG);
8643 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8644 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
8647 tmp = tr32(SERDES_RX_CTRL);
8648 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
8649 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
8650 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
8651 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8654 if (!tg3_flag(tp, USE_PHYLIB)) {
8655 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
8656 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
8657 tp->link_config.speed = tp->link_config.orig_speed;
8658 tp->link_config.duplex = tp->link_config.orig_duplex;
8659 tp->link_config.autoneg = tp->link_config.orig_autoneg;
8662 err = tg3_setup_phy(tp, 0);
8666 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
8667 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
8670 /* Clear CRC stats. */
8671 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
8672 tg3_writephy(tp, MII_TG3_TEST1,
8673 tmp | MII_TG3_TEST1_CRC_EN);
8674 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
8679 __tg3_set_rx_mode(tp->dev);
8681 /* Initialize receive rules. */
8682 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
8683 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
8684 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
8685 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
8687 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS))
8691 if (tg3_flag(tp, ENABLE_ASF))
8695 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
8697 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
8699 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
8701 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
8703 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
8705 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
8707 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
8709 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
8711 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
8713 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
8715 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
8717 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
8719 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
8721 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
8729 if (tg3_flag(tp, ENABLE_APE))
8730 /* Write our heartbeat update interval to APE. */
8731 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
8732 APE_HOST_HEARTBEAT_INT_DISABLE);
8734 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
8739 /* Called at device open time to get the chip ready for
8740 * packet processing. Invoked with tp->lock held.
8742 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
8744 tg3_switch_clocks(tp);
8746 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8748 return tg3_reset_hw(tp, reset_phy);
8751 #define TG3_STAT_ADD32(PSTAT, REG) \
8752 do { u32 __val = tr32(REG); \
8753 (PSTAT)->low += __val; \
8754 if ((PSTAT)->low < __val) \
8755 (PSTAT)->high += 1; \
8758 static void tg3_periodic_fetch_stats(struct tg3 *tp)
8760 struct tg3_hw_stats *sp = tp->hw_stats;
8762 if (!netif_carrier_ok(tp->dev))
8765 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
8766 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8767 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8768 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8769 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8770 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8771 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8772 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8773 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8774 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8775 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8776 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8777 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8779 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8780 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8781 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8782 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8783 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8784 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8785 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8786 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8787 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8788 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8789 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8790 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8791 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8792 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
8794 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8795 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
8796 tp->pci_chip_rev_id != CHIPREV_ID_5719_A0 &&
8797 tp->pci_chip_rev_id != CHIPREV_ID_5720_A0) {
8798 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8800 u32 val = tr32(HOSTCC_FLOW_ATTN);
8801 val = (val & HOSTCC_FLOW_ATTN_MBUF_LWM) ? 1 : 0;
8803 tw32(HOSTCC_FLOW_ATTN, HOSTCC_FLOW_ATTN_MBUF_LWM);
8804 sp->rx_discards.low += val;
8805 if (sp->rx_discards.low < val)
8806 sp->rx_discards.high += 1;
8808 sp->mbuf_lwm_thresh_hit = sp->rx_discards;
8810 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
8813 static void tg3_timer(unsigned long __opaque)
8815 struct tg3 *tp = (struct tg3 *) __opaque;
8820 spin_lock(&tp->lock);
8822 if (!tg3_flag(tp, TAGGED_STATUS)) {
8823 /* All of this garbage is because when using non-tagged
8824 * IRQ status the mailbox/status_block protocol the chip
8825 * uses with the cpu is race prone.
8827 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
8828 tw32(GRC_LOCAL_CTRL,
8829 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8831 tw32(HOSTCC_MODE, tp->coalesce_mode |
8832 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
8835 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8836 tg3_flag_set(tp, RESTART_TIMER);
8837 spin_unlock(&tp->lock);
8838 schedule_work(&tp->reset_task);
8843 /* This part only runs once per second. */
8844 if (!--tp->timer_counter) {
8845 if (tg3_flag(tp, 5705_PLUS))
8846 tg3_periodic_fetch_stats(tp);
8848 if (tp->setlpicnt && !--tp->setlpicnt)
8849 tg3_phy_eee_enable(tp);
8851 if (tg3_flag(tp, USE_LINKCHG_REG)) {
8855 mac_stat = tr32(MAC_STATUS);
8858 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
8859 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8861 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8865 tg3_setup_phy(tp, 0);
8866 } else if (tg3_flag(tp, POLL_SERDES)) {
8867 u32 mac_stat = tr32(MAC_STATUS);
8870 if (netif_carrier_ok(tp->dev) &&
8871 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8874 if (!netif_carrier_ok(tp->dev) &&
8875 (mac_stat & (MAC_STATUS_PCS_SYNCED |
8876 MAC_STATUS_SIGNAL_DET))) {
8880 if (!tp->serdes_counter) {
8883 ~MAC_MODE_PORT_MODE_MASK));
8885 tw32_f(MAC_MODE, tp->mac_mode);
8888 tg3_setup_phy(tp, 0);
8890 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8891 tg3_flag(tp, 5780_CLASS)) {
8892 tg3_serdes_parallel_detect(tp);
8895 tp->timer_counter = tp->timer_multiplier;
8898 /* Heartbeat is only sent once every 2 seconds.
8900 * The heartbeat is to tell the ASF firmware that the host
8901 * driver is still alive. In the event that the OS crashes,
8902 * ASF needs to reset the hardware to free up the FIFO space
8903 * that may be filled with rx packets destined for the host.
8904 * If the FIFO is full, ASF will no longer function properly.
8906 * Unintended resets have been reported on real time kernels
8907 * where the timer doesn't run on time. Netpoll will also have
8910 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8911 * to check the ring condition when the heartbeat is expiring
8912 * before doing the reset. This will prevent most unintended
8915 if (!--tp->asf_counter) {
8916 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
8917 tg3_wait_for_event_ack(tp);
8919 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
8920 FWCMD_NICDRV_ALIVE3);
8921 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
8922 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
8923 TG3_FW_UPDATE_TIMEOUT_SEC);
8925 tg3_generate_fw_event(tp);
8927 tp->asf_counter = tp->asf_multiplier;
8930 spin_unlock(&tp->lock);
8933 tp->timer.expires = jiffies + tp->timer_offset;
8934 add_timer(&tp->timer);
8937 static int tg3_request_irq(struct tg3 *tp, int irq_num)
8940 unsigned long flags;
8942 struct tg3_napi *tnapi = &tp->napi[irq_num];
8944 if (tp->irq_cnt == 1)
8945 name = tp->dev->name;
8947 name = &tnapi->irq_lbl[0];
8948 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8949 name[IFNAMSIZ-1] = 0;
8952 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
8954 if (tg3_flag(tp, 1SHOT_MSI))
8959 if (tg3_flag(tp, TAGGED_STATUS))
8960 fn = tg3_interrupt_tagged;
8961 flags = IRQF_SHARED;
8964 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
8967 static int tg3_test_interrupt(struct tg3 *tp)
8969 struct tg3_napi *tnapi = &tp->napi[0];
8970 struct net_device *dev = tp->dev;
8971 int err, i, intr_ok = 0;
8974 if (!netif_running(dev))
8977 tg3_disable_ints(tp);
8979 free_irq(tnapi->irq_vec, tnapi);
8982 * Turn off MSI one shot mode. Otherwise this test has no
8983 * observable way to know whether the interrupt was delivered.
8985 if (tg3_flag(tp, 57765_PLUS)) {
8986 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8987 tw32(MSGINT_MODE, val);
8990 err = request_irq(tnapi->irq_vec, tg3_test_isr,
8991 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
8995 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
8996 tg3_enable_ints(tp);
8998 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9001 for (i = 0; i < 5; i++) {
9002 u32 int_mbox, misc_host_ctrl;
9004 int_mbox = tr32_mailbox(tnapi->int_mbox);
9005 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
9007 if ((int_mbox != 0) ||
9008 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
9013 if (tg3_flag(tp, 57765_PLUS) &&
9014 tnapi->hw_status->status_tag != tnapi->last_tag)
9015 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
9020 tg3_disable_ints(tp);
9022 free_irq(tnapi->irq_vec, tnapi);
9024 err = tg3_request_irq(tp, 0);
9030 /* Reenable MSI one shot mode. */
9031 if (tg3_flag(tp, 57765_PLUS)) {
9032 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
9033 tw32(MSGINT_MODE, val);
9041 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
9042 * successfully restored
9044 static int tg3_test_msi(struct tg3 *tp)
9049 if (!tg3_flag(tp, USING_MSI))
9052 /* Turn off SERR reporting in case MSI terminates with Master
9055 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
9056 pci_write_config_word(tp->pdev, PCI_COMMAND,
9057 pci_cmd & ~PCI_COMMAND_SERR);
9059 err = tg3_test_interrupt(tp);
9061 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
9066 /* other failures */
9070 /* MSI test failed, go back to INTx mode */
9071 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
9072 "to INTx mode. Please report this failure to the PCI "
9073 "maintainer and include system chipset information\n");
9075 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
9077 pci_disable_msi(tp->pdev);
9079 tg3_flag_clear(tp, USING_MSI);
9080 tp->napi[0].irq_vec = tp->pdev->irq;
9082 err = tg3_request_irq(tp, 0);
9086 /* Need to reset the chip because the MSI cycle may have terminated
9087 * with Master Abort.
9089 tg3_full_lock(tp, 1);
9091 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9092 err = tg3_init_hw(tp, 1);
9094 tg3_full_unlock(tp);
9097 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
9102 static int tg3_request_firmware(struct tg3 *tp)
9104 const __be32 *fw_data;
9106 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
9107 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
9112 fw_data = (void *)tp->fw->data;
9114 /* Firmware blob starts with version numbers, followed by
9115 * start address and _full_ length including BSS sections
9116 * (which must be longer than the actual data, of course
9119 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
9120 if (tp->fw_len < (tp->fw->size - 12)) {
9121 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
9122 tp->fw_len, tp->fw_needed);
9123 release_firmware(tp->fw);
9128 /* We no longer need firmware; we have it. */
9129 tp->fw_needed = NULL;
9133 static bool tg3_enable_msix(struct tg3 *tp)
9135 int i, rc, cpus = num_online_cpus();
9136 struct msix_entry msix_ent[tp->irq_max];
9139 /* Just fallback to the simpler MSI mode. */
9143 * We want as many rx rings enabled as there are cpus.
9144 * The first MSIX vector only deals with link interrupts, etc,
9145 * so we add one to the number of vectors we are requesting.
9147 tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
9149 for (i = 0; i < tp->irq_max; i++) {
9150 msix_ent[i].entry = i;
9151 msix_ent[i].vector = 0;
9154 rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
9157 } else if (rc != 0) {
9158 if (pci_enable_msix(tp->pdev, msix_ent, rc))
9160 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
9165 for (i = 0; i < tp->irq_max; i++)
9166 tp->napi[i].irq_vec = msix_ent[i].vector;
9168 netif_set_real_num_tx_queues(tp->dev, 1);
9169 rc = tp->irq_cnt > 1 ? tp->irq_cnt - 1 : 1;
9170 if (netif_set_real_num_rx_queues(tp->dev, rc)) {
9171 pci_disable_msix(tp->pdev);
9175 if (tp->irq_cnt > 1) {
9176 tg3_flag_set(tp, ENABLE_RSS);
9178 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
9179 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
9180 tg3_flag_set(tp, ENABLE_TSS);
9181 netif_set_real_num_tx_queues(tp->dev, tp->irq_cnt - 1);
9188 static void tg3_ints_init(struct tg3 *tp)
9190 if ((tg3_flag(tp, SUPPORT_MSI) || tg3_flag(tp, SUPPORT_MSIX)) &&
9191 !tg3_flag(tp, TAGGED_STATUS)) {
9192 /* All MSI supporting chips should support tagged
9193 * status. Assert that this is the case.
9195 netdev_warn(tp->dev,
9196 "MSI without TAGGED_STATUS? Not using MSI\n");
9200 if (tg3_flag(tp, SUPPORT_MSIX) && tg3_enable_msix(tp))
9201 tg3_flag_set(tp, USING_MSIX);
9202 else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0)
9203 tg3_flag_set(tp, USING_MSI);
9205 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
9206 u32 msi_mode = tr32(MSGINT_MODE);
9207 if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1)
9208 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
9209 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
9212 if (!tg3_flag(tp, USING_MSIX)) {
9214 tp->napi[0].irq_vec = tp->pdev->irq;
9215 netif_set_real_num_tx_queues(tp->dev, 1);
9216 netif_set_real_num_rx_queues(tp->dev, 1);
9220 static void tg3_ints_fini(struct tg3 *tp)
9222 if (tg3_flag(tp, USING_MSIX))
9223 pci_disable_msix(tp->pdev);
9224 else if (tg3_flag(tp, USING_MSI))
9225 pci_disable_msi(tp->pdev);
9226 tg3_flag_clear(tp, USING_MSI);
9227 tg3_flag_clear(tp, USING_MSIX);
9228 tg3_flag_clear(tp, ENABLE_RSS);
9229 tg3_flag_clear(tp, ENABLE_TSS);
9232 static int tg3_open(struct net_device *dev)
9234 struct tg3 *tp = netdev_priv(dev);
9237 if (tp->fw_needed) {
9238 err = tg3_request_firmware(tp);
9239 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
9243 netdev_warn(tp->dev, "TSO capability disabled\n");
9244 tg3_flag_clear(tp, TSO_CAPABLE);
9245 } else if (!tg3_flag(tp, TSO_CAPABLE)) {
9246 netdev_notice(tp->dev, "TSO capability restored\n");
9247 tg3_flag_set(tp, TSO_CAPABLE);
9251 netif_carrier_off(tp->dev);
9253 err = tg3_power_up(tp);
9257 tg3_full_lock(tp, 0);
9259 tg3_disable_ints(tp);
9260 tg3_flag_clear(tp, INIT_COMPLETE);
9262 tg3_full_unlock(tp);
9265 * Setup interrupts first so we know how
9266 * many NAPI resources to allocate
9270 /* The placement of this call is tied
9271 * to the setup and use of Host TX descriptors.
9273 err = tg3_alloc_consistent(tp);
9279 tg3_napi_enable(tp);
9281 for (i = 0; i < tp->irq_cnt; i++) {
9282 struct tg3_napi *tnapi = &tp->napi[i];
9283 err = tg3_request_irq(tp, i);
9285 for (i--; i >= 0; i--)
9286 free_irq(tnapi->irq_vec, tnapi);
9294 tg3_full_lock(tp, 0);
9296 err = tg3_init_hw(tp, 1);
9298 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9301 if (tg3_flag(tp, TAGGED_STATUS))
9302 tp->timer_offset = HZ;
9304 tp->timer_offset = HZ / 10;
9306 BUG_ON(tp->timer_offset > HZ);
9307 tp->timer_counter = tp->timer_multiplier =
9308 (HZ / tp->timer_offset);
9309 tp->asf_counter = tp->asf_multiplier =
9310 ((HZ / tp->timer_offset) * 2);
9312 init_timer(&tp->timer);
9313 tp->timer.expires = jiffies + tp->timer_offset;
9314 tp->timer.data = (unsigned long) tp;
9315 tp->timer.function = tg3_timer;
9318 tg3_full_unlock(tp);
9323 if (tg3_flag(tp, USING_MSI)) {
9324 err = tg3_test_msi(tp);
9327 tg3_full_lock(tp, 0);
9328 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9330 tg3_full_unlock(tp);
9335 if (!tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) {
9336 u32 val = tr32(PCIE_TRANSACTION_CFG);
9338 tw32(PCIE_TRANSACTION_CFG,
9339 val | PCIE_TRANS_CFG_1SHOT_MSI);
9345 tg3_full_lock(tp, 0);
9347 add_timer(&tp->timer);
9348 tg3_flag_set(tp, INIT_COMPLETE);
9349 tg3_enable_ints(tp);
9351 tg3_full_unlock(tp);
9353 netif_tx_start_all_queues(dev);
9356 * Reset loopback feature if it was turned on while the device was down
9357 * make sure that it's installed properly now.
9359 if (dev->features & NETIF_F_LOOPBACK)
9360 tg3_set_loopback(dev, dev->features);
9365 for (i = tp->irq_cnt - 1; i >= 0; i--) {
9366 struct tg3_napi *tnapi = &tp->napi[i];
9367 free_irq(tnapi->irq_vec, tnapi);
9371 tg3_napi_disable(tp);
9373 tg3_free_consistent(tp);
9380 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *,
9381 struct rtnl_link_stats64 *);
9382 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
9384 static int tg3_close(struct net_device *dev)
9387 struct tg3 *tp = netdev_priv(dev);
9389 tg3_napi_disable(tp);
9390 cancel_work_sync(&tp->reset_task);
9392 netif_tx_stop_all_queues(dev);
9394 del_timer_sync(&tp->timer);
9398 tg3_full_lock(tp, 1);
9400 tg3_disable_ints(tp);
9402 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9404 tg3_flag_clear(tp, INIT_COMPLETE);
9406 tg3_full_unlock(tp);
9408 for (i = tp->irq_cnt - 1; i >= 0; i--) {
9409 struct tg3_napi *tnapi = &tp->napi[i];
9410 free_irq(tnapi->irq_vec, tnapi);
9415 tg3_get_stats64(tp->dev, &tp->net_stats_prev);
9417 memcpy(&tp->estats_prev, tg3_get_estats(tp),
9418 sizeof(tp->estats_prev));
9422 tg3_free_consistent(tp);
9426 netif_carrier_off(tp->dev);
9431 static inline u64 get_stat64(tg3_stat64_t *val)
9433 return ((u64)val->high << 32) | ((u64)val->low);
9436 static u64 calc_crc_errors(struct tg3 *tp)
9438 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9440 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
9441 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9442 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
9445 spin_lock_bh(&tp->lock);
9446 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9447 tg3_writephy(tp, MII_TG3_TEST1,
9448 val | MII_TG3_TEST1_CRC_EN);
9449 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
9452 spin_unlock_bh(&tp->lock);
9454 tp->phy_crc_errors += val;
9456 return tp->phy_crc_errors;
9459 return get_stat64(&hw_stats->rx_fcs_errors);
9462 #define ESTAT_ADD(member) \
9463 estats->member = old_estats->member + \
9464 get_stat64(&hw_stats->member)
9466 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
9468 struct tg3_ethtool_stats *estats = &tp->estats;
9469 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9470 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9475 ESTAT_ADD(rx_octets);
9476 ESTAT_ADD(rx_fragments);
9477 ESTAT_ADD(rx_ucast_packets);
9478 ESTAT_ADD(rx_mcast_packets);
9479 ESTAT_ADD(rx_bcast_packets);
9480 ESTAT_ADD(rx_fcs_errors);
9481 ESTAT_ADD(rx_align_errors);
9482 ESTAT_ADD(rx_xon_pause_rcvd);
9483 ESTAT_ADD(rx_xoff_pause_rcvd);
9484 ESTAT_ADD(rx_mac_ctrl_rcvd);
9485 ESTAT_ADD(rx_xoff_entered);
9486 ESTAT_ADD(rx_frame_too_long_errors);
9487 ESTAT_ADD(rx_jabbers);
9488 ESTAT_ADD(rx_undersize_packets);
9489 ESTAT_ADD(rx_in_length_errors);
9490 ESTAT_ADD(rx_out_length_errors);
9491 ESTAT_ADD(rx_64_or_less_octet_packets);
9492 ESTAT_ADD(rx_65_to_127_octet_packets);
9493 ESTAT_ADD(rx_128_to_255_octet_packets);
9494 ESTAT_ADD(rx_256_to_511_octet_packets);
9495 ESTAT_ADD(rx_512_to_1023_octet_packets);
9496 ESTAT_ADD(rx_1024_to_1522_octet_packets);
9497 ESTAT_ADD(rx_1523_to_2047_octet_packets);
9498 ESTAT_ADD(rx_2048_to_4095_octet_packets);
9499 ESTAT_ADD(rx_4096_to_8191_octet_packets);
9500 ESTAT_ADD(rx_8192_to_9022_octet_packets);
9502 ESTAT_ADD(tx_octets);
9503 ESTAT_ADD(tx_collisions);
9504 ESTAT_ADD(tx_xon_sent);
9505 ESTAT_ADD(tx_xoff_sent);
9506 ESTAT_ADD(tx_flow_control);
9507 ESTAT_ADD(tx_mac_errors);
9508 ESTAT_ADD(tx_single_collisions);
9509 ESTAT_ADD(tx_mult_collisions);
9510 ESTAT_ADD(tx_deferred);
9511 ESTAT_ADD(tx_excessive_collisions);
9512 ESTAT_ADD(tx_late_collisions);
9513 ESTAT_ADD(tx_collide_2times);
9514 ESTAT_ADD(tx_collide_3times);
9515 ESTAT_ADD(tx_collide_4times);
9516 ESTAT_ADD(tx_collide_5times);
9517 ESTAT_ADD(tx_collide_6times);
9518 ESTAT_ADD(tx_collide_7times);
9519 ESTAT_ADD(tx_collide_8times);
9520 ESTAT_ADD(tx_collide_9times);
9521 ESTAT_ADD(tx_collide_10times);
9522 ESTAT_ADD(tx_collide_11times);
9523 ESTAT_ADD(tx_collide_12times);
9524 ESTAT_ADD(tx_collide_13times);
9525 ESTAT_ADD(tx_collide_14times);
9526 ESTAT_ADD(tx_collide_15times);
9527 ESTAT_ADD(tx_ucast_packets);
9528 ESTAT_ADD(tx_mcast_packets);
9529 ESTAT_ADD(tx_bcast_packets);
9530 ESTAT_ADD(tx_carrier_sense_errors);
9531 ESTAT_ADD(tx_discards);
9532 ESTAT_ADD(tx_errors);
9534 ESTAT_ADD(dma_writeq_full);
9535 ESTAT_ADD(dma_write_prioq_full);
9536 ESTAT_ADD(rxbds_empty);
9537 ESTAT_ADD(rx_discards);
9538 ESTAT_ADD(rx_errors);
9539 ESTAT_ADD(rx_threshold_hit);
9541 ESTAT_ADD(dma_readq_full);
9542 ESTAT_ADD(dma_read_prioq_full);
9543 ESTAT_ADD(tx_comp_queue_full);
9545 ESTAT_ADD(ring_set_send_prod_index);
9546 ESTAT_ADD(ring_status_update);
9547 ESTAT_ADD(nic_irqs);
9548 ESTAT_ADD(nic_avoided_irqs);
9549 ESTAT_ADD(nic_tx_threshold_hit);
9551 ESTAT_ADD(mbuf_lwm_thresh_hit);
9556 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
9557 struct rtnl_link_stats64 *stats)
9559 struct tg3 *tp = netdev_priv(dev);
9560 struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
9561 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9566 stats->rx_packets = old_stats->rx_packets +
9567 get_stat64(&hw_stats->rx_ucast_packets) +
9568 get_stat64(&hw_stats->rx_mcast_packets) +
9569 get_stat64(&hw_stats->rx_bcast_packets);
9571 stats->tx_packets = old_stats->tx_packets +
9572 get_stat64(&hw_stats->tx_ucast_packets) +
9573 get_stat64(&hw_stats->tx_mcast_packets) +
9574 get_stat64(&hw_stats->tx_bcast_packets);
9576 stats->rx_bytes = old_stats->rx_bytes +
9577 get_stat64(&hw_stats->rx_octets);
9578 stats->tx_bytes = old_stats->tx_bytes +
9579 get_stat64(&hw_stats->tx_octets);
9581 stats->rx_errors = old_stats->rx_errors +
9582 get_stat64(&hw_stats->rx_errors);
9583 stats->tx_errors = old_stats->tx_errors +
9584 get_stat64(&hw_stats->tx_errors) +
9585 get_stat64(&hw_stats->tx_mac_errors) +
9586 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9587 get_stat64(&hw_stats->tx_discards);
9589 stats->multicast = old_stats->multicast +
9590 get_stat64(&hw_stats->rx_mcast_packets);
9591 stats->collisions = old_stats->collisions +
9592 get_stat64(&hw_stats->tx_collisions);
9594 stats->rx_length_errors = old_stats->rx_length_errors +
9595 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9596 get_stat64(&hw_stats->rx_undersize_packets);
9598 stats->rx_over_errors = old_stats->rx_over_errors +
9599 get_stat64(&hw_stats->rxbds_empty);
9600 stats->rx_frame_errors = old_stats->rx_frame_errors +
9601 get_stat64(&hw_stats->rx_align_errors);
9602 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9603 get_stat64(&hw_stats->tx_discards);
9604 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9605 get_stat64(&hw_stats->tx_carrier_sense_errors);
9607 stats->rx_crc_errors = old_stats->rx_crc_errors +
9608 calc_crc_errors(tp);
9610 stats->rx_missed_errors = old_stats->rx_missed_errors +
9611 get_stat64(&hw_stats->rx_discards);
9613 stats->rx_dropped = tp->rx_dropped;
9618 static inline u32 calc_crc(unsigned char *buf, int len)
9626 for (j = 0; j < len; j++) {
9629 for (k = 0; k < 8; k++) {
9642 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9644 /* accept or reject all multicast frames */
9645 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9646 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9647 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9648 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9651 static void __tg3_set_rx_mode(struct net_device *dev)
9653 struct tg3 *tp = netdev_priv(dev);
9656 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9657 RX_MODE_KEEP_VLAN_TAG);
9659 #if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE)
9660 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9663 if (!tg3_flag(tp, ENABLE_ASF))
9664 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9667 if (dev->flags & IFF_PROMISC) {
9668 /* Promiscuous mode. */
9669 rx_mode |= RX_MODE_PROMISC;
9670 } else if (dev->flags & IFF_ALLMULTI) {
9671 /* Accept all multicast. */
9672 tg3_set_multi(tp, 1);
9673 } else if (netdev_mc_empty(dev)) {
9674 /* Reject all multicast. */
9675 tg3_set_multi(tp, 0);
9677 /* Accept one or more multicast(s). */
9678 struct netdev_hw_addr *ha;
9679 u32 mc_filter[4] = { 0, };
9684 netdev_for_each_mc_addr(ha, dev) {
9685 crc = calc_crc(ha->addr, ETH_ALEN);
9687 regidx = (bit & 0x60) >> 5;
9689 mc_filter[regidx] |= (1 << bit);
9692 tw32(MAC_HASH_REG_0, mc_filter[0]);
9693 tw32(MAC_HASH_REG_1, mc_filter[1]);
9694 tw32(MAC_HASH_REG_2, mc_filter[2]);
9695 tw32(MAC_HASH_REG_3, mc_filter[3]);
9698 if (rx_mode != tp->rx_mode) {
9699 tp->rx_mode = rx_mode;
9700 tw32_f(MAC_RX_MODE, rx_mode);
9705 static void tg3_set_rx_mode(struct net_device *dev)
9707 struct tg3 *tp = netdev_priv(dev);
9709 if (!netif_running(dev))
9712 tg3_full_lock(tp, 0);
9713 __tg3_set_rx_mode(dev);
9714 tg3_full_unlock(tp);
9717 static int tg3_get_regs_len(struct net_device *dev)
9719 return TG3_REG_BLK_SIZE;
9722 static void tg3_get_regs(struct net_device *dev,
9723 struct ethtool_regs *regs, void *_p)
9725 struct tg3 *tp = netdev_priv(dev);
9729 memset(_p, 0, TG3_REG_BLK_SIZE);
9731 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9734 tg3_full_lock(tp, 0);
9736 tg3_dump_legacy_regs(tp, (u32 *)_p);
9738 tg3_full_unlock(tp);
9741 static int tg3_get_eeprom_len(struct net_device *dev)
9743 struct tg3 *tp = netdev_priv(dev);
9745 return tp->nvram_size;
9748 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9750 struct tg3 *tp = netdev_priv(dev);
9753 u32 i, offset, len, b_offset, b_count;
9756 if (tg3_flag(tp, NO_NVRAM))
9759 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9762 offset = eeprom->offset;
9766 eeprom->magic = TG3_EEPROM_MAGIC;
9769 /* adjustments to start on required 4 byte boundary */
9770 b_offset = offset & 3;
9771 b_count = 4 - b_offset;
9772 if (b_count > len) {
9773 /* i.e. offset=1 len=2 */
9776 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
9779 memcpy(data, ((char *)&val) + b_offset, b_count);
9782 eeprom->len += b_count;
9785 /* read bytes up to the last 4 byte boundary */
9786 pd = &data[eeprom->len];
9787 for (i = 0; i < (len - (len & 3)); i += 4) {
9788 ret = tg3_nvram_read_be32(tp, offset + i, &val);
9793 memcpy(pd + i, &val, 4);
9798 /* read last bytes not ending on 4 byte boundary */
9799 pd = &data[eeprom->len];
9801 b_offset = offset + len - b_count;
9802 ret = tg3_nvram_read_be32(tp, b_offset, &val);
9805 memcpy(pd, &val, b_count);
9806 eeprom->len += b_count;
9811 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
9813 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9815 struct tg3 *tp = netdev_priv(dev);
9817 u32 offset, len, b_offset, odd_len;
9821 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9824 if (tg3_flag(tp, NO_NVRAM) ||
9825 eeprom->magic != TG3_EEPROM_MAGIC)
9828 offset = eeprom->offset;
9831 if ((b_offset = (offset & 3))) {
9832 /* adjustments to start on required 4 byte boundary */
9833 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
9844 /* adjustments to end on required 4 byte boundary */
9846 len = (len + 3) & ~3;
9847 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
9853 if (b_offset || odd_len) {
9854 buf = kmalloc(len, GFP_KERNEL);
9858 memcpy(buf, &start, 4);
9860 memcpy(buf+len-4, &end, 4);
9861 memcpy(buf + b_offset, data, eeprom->len);
9864 ret = tg3_nvram_write_block(tp, offset, len, buf);
9872 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9874 struct tg3 *tp = netdev_priv(dev);
9876 if (tg3_flag(tp, USE_PHYLIB)) {
9877 struct phy_device *phydev;
9878 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
9880 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9881 return phy_ethtool_gset(phydev, cmd);
9884 cmd->supported = (SUPPORTED_Autoneg);
9886 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
9887 cmd->supported |= (SUPPORTED_1000baseT_Half |
9888 SUPPORTED_1000baseT_Full);
9890 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
9891 cmd->supported |= (SUPPORTED_100baseT_Half |
9892 SUPPORTED_100baseT_Full |
9893 SUPPORTED_10baseT_Half |
9894 SUPPORTED_10baseT_Full |
9896 cmd->port = PORT_TP;
9898 cmd->supported |= SUPPORTED_FIBRE;
9899 cmd->port = PORT_FIBRE;
9902 cmd->advertising = tp->link_config.advertising;
9903 if (netif_running(dev)) {
9904 ethtool_cmd_speed_set(cmd, tp->link_config.active_speed);
9905 cmd->duplex = tp->link_config.active_duplex;
9907 ethtool_cmd_speed_set(cmd, SPEED_INVALID);
9908 cmd->duplex = DUPLEX_INVALID;
9910 cmd->phy_address = tp->phy_addr;
9911 cmd->transceiver = XCVR_INTERNAL;
9912 cmd->autoneg = tp->link_config.autoneg;
9918 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9920 struct tg3 *tp = netdev_priv(dev);
9921 u32 speed = ethtool_cmd_speed(cmd);
9923 if (tg3_flag(tp, USE_PHYLIB)) {
9924 struct phy_device *phydev;
9925 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
9927 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9928 return phy_ethtool_sset(phydev, cmd);
9931 if (cmd->autoneg != AUTONEG_ENABLE &&
9932 cmd->autoneg != AUTONEG_DISABLE)
9935 if (cmd->autoneg == AUTONEG_DISABLE &&
9936 cmd->duplex != DUPLEX_FULL &&
9937 cmd->duplex != DUPLEX_HALF)
9940 if (cmd->autoneg == AUTONEG_ENABLE) {
9941 u32 mask = ADVERTISED_Autoneg |
9943 ADVERTISED_Asym_Pause;
9945 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
9946 mask |= ADVERTISED_1000baseT_Half |
9947 ADVERTISED_1000baseT_Full;
9949 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
9950 mask |= ADVERTISED_100baseT_Half |
9951 ADVERTISED_100baseT_Full |
9952 ADVERTISED_10baseT_Half |
9953 ADVERTISED_10baseT_Full |
9956 mask |= ADVERTISED_FIBRE;
9958 if (cmd->advertising & ~mask)
9961 mask &= (ADVERTISED_1000baseT_Half |
9962 ADVERTISED_1000baseT_Full |
9963 ADVERTISED_100baseT_Half |
9964 ADVERTISED_100baseT_Full |
9965 ADVERTISED_10baseT_Half |
9966 ADVERTISED_10baseT_Full);
9968 cmd->advertising &= mask;
9970 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
9971 if (speed != SPEED_1000)
9974 if (cmd->duplex != DUPLEX_FULL)
9977 if (speed != SPEED_100 &&
9983 tg3_full_lock(tp, 0);
9985 tp->link_config.autoneg = cmd->autoneg;
9986 if (cmd->autoneg == AUTONEG_ENABLE) {
9987 tp->link_config.advertising = (cmd->advertising |
9988 ADVERTISED_Autoneg);
9989 tp->link_config.speed = SPEED_INVALID;
9990 tp->link_config.duplex = DUPLEX_INVALID;
9992 tp->link_config.advertising = 0;
9993 tp->link_config.speed = speed;
9994 tp->link_config.duplex = cmd->duplex;
9997 tp->link_config.orig_speed = tp->link_config.speed;
9998 tp->link_config.orig_duplex = tp->link_config.duplex;
9999 tp->link_config.orig_autoneg = tp->link_config.autoneg;
10001 if (netif_running(dev))
10002 tg3_setup_phy(tp, 1);
10004 tg3_full_unlock(tp);
10009 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
10011 struct tg3 *tp = netdev_priv(dev);
10013 strcpy(info->driver, DRV_MODULE_NAME);
10014 strcpy(info->version, DRV_MODULE_VERSION);
10015 strcpy(info->fw_version, tp->fw_ver);
10016 strcpy(info->bus_info, pci_name(tp->pdev));
10019 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
10021 struct tg3 *tp = netdev_priv(dev);
10023 if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev))
10024 wol->supported = WAKE_MAGIC;
10026 wol->supported = 0;
10028 if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev))
10029 wol->wolopts = WAKE_MAGIC;
10030 memset(&wol->sopass, 0, sizeof(wol->sopass));
10033 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
10035 struct tg3 *tp = netdev_priv(dev);
10036 struct device *dp = &tp->pdev->dev;
10038 if (wol->wolopts & ~WAKE_MAGIC)
10040 if ((wol->wolopts & WAKE_MAGIC) &&
10041 !(tg3_flag(tp, WOL_CAP) && device_can_wakeup(dp)))
10044 device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC);
10046 spin_lock_bh(&tp->lock);
10047 if (device_may_wakeup(dp))
10048 tg3_flag_set(tp, WOL_ENABLE);
10050 tg3_flag_clear(tp, WOL_ENABLE);
10051 spin_unlock_bh(&tp->lock);
10056 static u32 tg3_get_msglevel(struct net_device *dev)
10058 struct tg3 *tp = netdev_priv(dev);
10059 return tp->msg_enable;
10062 static void tg3_set_msglevel(struct net_device *dev, u32 value)
10064 struct tg3 *tp = netdev_priv(dev);
10065 tp->msg_enable = value;
10068 static int tg3_nway_reset(struct net_device *dev)
10070 struct tg3 *tp = netdev_priv(dev);
10073 if (!netif_running(dev))
10076 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
10079 if (tg3_flag(tp, USE_PHYLIB)) {
10080 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
10082 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
10086 spin_lock_bh(&tp->lock);
10088 tg3_readphy(tp, MII_BMCR, &bmcr);
10089 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
10090 ((bmcr & BMCR_ANENABLE) ||
10091 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
10092 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
10096 spin_unlock_bh(&tp->lock);
10102 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
10104 struct tg3 *tp = netdev_priv(dev);
10106 ering->rx_max_pending = tp->rx_std_ring_mask;
10107 ering->rx_mini_max_pending = 0;
10108 if (tg3_flag(tp, JUMBO_RING_ENABLE))
10109 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask;
10111 ering->rx_jumbo_max_pending = 0;
10113 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
10115 ering->rx_pending = tp->rx_pending;
10116 ering->rx_mini_pending = 0;
10117 if (tg3_flag(tp, JUMBO_RING_ENABLE))
10118 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
10120 ering->rx_jumbo_pending = 0;
10122 ering->tx_pending = tp->napi[0].tx_pending;
10125 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
10127 struct tg3 *tp = netdev_priv(dev);
10128 int i, irq_sync = 0, err = 0;
10130 if ((ering->rx_pending > tp->rx_std_ring_mask) ||
10131 (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) ||
10132 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
10133 (ering->tx_pending <= MAX_SKB_FRAGS) ||
10134 (tg3_flag(tp, TSO_BUG) &&
10135 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
10138 if (netif_running(dev)) {
10140 tg3_netif_stop(tp);
10144 tg3_full_lock(tp, irq_sync);
10146 tp->rx_pending = ering->rx_pending;
10148 if (tg3_flag(tp, MAX_RXPEND_64) &&
10149 tp->rx_pending > 63)
10150 tp->rx_pending = 63;
10151 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
10153 for (i = 0; i < tp->irq_max; i++)
10154 tp->napi[i].tx_pending = ering->tx_pending;
10156 if (netif_running(dev)) {
10157 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10158 err = tg3_restart_hw(tp, 1);
10160 tg3_netif_start(tp);
10163 tg3_full_unlock(tp);
10165 if (irq_sync && !err)
10171 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10173 struct tg3 *tp = netdev_priv(dev);
10175 epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG);
10177 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
10178 epause->rx_pause = 1;
10180 epause->rx_pause = 0;
10182 if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
10183 epause->tx_pause = 1;
10185 epause->tx_pause = 0;
10188 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10190 struct tg3 *tp = netdev_priv(dev);
10193 if (tg3_flag(tp, USE_PHYLIB)) {
10195 struct phy_device *phydev;
10197 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10199 if (!(phydev->supported & SUPPORTED_Pause) ||
10200 (!(phydev->supported & SUPPORTED_Asym_Pause) &&
10201 (epause->rx_pause != epause->tx_pause)))
10204 tp->link_config.flowctrl = 0;
10205 if (epause->rx_pause) {
10206 tp->link_config.flowctrl |= FLOW_CTRL_RX;
10208 if (epause->tx_pause) {
10209 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10210 newadv = ADVERTISED_Pause;
10212 newadv = ADVERTISED_Pause |
10213 ADVERTISED_Asym_Pause;
10214 } else if (epause->tx_pause) {
10215 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10216 newadv = ADVERTISED_Asym_Pause;
10220 if (epause->autoneg)
10221 tg3_flag_set(tp, PAUSE_AUTONEG);
10223 tg3_flag_clear(tp, PAUSE_AUTONEG);
10225 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
10226 u32 oldadv = phydev->advertising &
10227 (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
10228 if (oldadv != newadv) {
10229 phydev->advertising &=
10230 ~(ADVERTISED_Pause |
10231 ADVERTISED_Asym_Pause);
10232 phydev->advertising |= newadv;
10233 if (phydev->autoneg) {
10235 * Always renegotiate the link to
10236 * inform our link partner of our
10237 * flow control settings, even if the
10238 * flow control is forced. Let
10239 * tg3_adjust_link() do the final
10240 * flow control setup.
10242 return phy_start_aneg(phydev);
10246 if (!epause->autoneg)
10247 tg3_setup_flow_control(tp, 0, 0);
10249 tp->link_config.orig_advertising &=
10250 ~(ADVERTISED_Pause |
10251 ADVERTISED_Asym_Pause);
10252 tp->link_config.orig_advertising |= newadv;
10257 if (netif_running(dev)) {
10258 tg3_netif_stop(tp);
10262 tg3_full_lock(tp, irq_sync);
10264 if (epause->autoneg)
10265 tg3_flag_set(tp, PAUSE_AUTONEG);
10267 tg3_flag_clear(tp, PAUSE_AUTONEG);
10268 if (epause->rx_pause)
10269 tp->link_config.flowctrl |= FLOW_CTRL_RX;
10271 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
10272 if (epause->tx_pause)
10273 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10275 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
10277 if (netif_running(dev)) {
10278 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10279 err = tg3_restart_hw(tp, 1);
10281 tg3_netif_start(tp);
10284 tg3_full_unlock(tp);
10290 static int tg3_get_sset_count(struct net_device *dev, int sset)
10294 return TG3_NUM_TEST;
10296 return TG3_NUM_STATS;
10298 return -EOPNOTSUPP;
10302 static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
10304 switch (stringset) {
10306 memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys));
10309 memcpy(buf, ðtool_test_keys, sizeof(ethtool_test_keys));
10312 WARN_ON(1); /* we need a WARN() */
10317 static int tg3_set_phys_id(struct net_device *dev,
10318 enum ethtool_phys_id_state state)
10320 struct tg3 *tp = netdev_priv(dev);
10322 if (!netif_running(tp->dev))
10326 case ETHTOOL_ID_ACTIVE:
10327 return 1; /* cycle on/off once per second */
10329 case ETHTOOL_ID_ON:
10330 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10331 LED_CTRL_1000MBPS_ON |
10332 LED_CTRL_100MBPS_ON |
10333 LED_CTRL_10MBPS_ON |
10334 LED_CTRL_TRAFFIC_OVERRIDE |
10335 LED_CTRL_TRAFFIC_BLINK |
10336 LED_CTRL_TRAFFIC_LED);
10339 case ETHTOOL_ID_OFF:
10340 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10341 LED_CTRL_TRAFFIC_OVERRIDE);
10344 case ETHTOOL_ID_INACTIVE:
10345 tw32(MAC_LED_CTRL, tp->led_ctrl);
10352 static void tg3_get_ethtool_stats(struct net_device *dev,
10353 struct ethtool_stats *estats, u64 *tmp_stats)
10355 struct tg3 *tp = netdev_priv(dev);
10356 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
10359 static __be32 * tg3_vpd_readblock(struct tg3 *tp)
10363 u32 offset = 0, len = 0;
10366 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &magic))
10369 if (magic == TG3_EEPROM_MAGIC) {
10370 for (offset = TG3_NVM_DIR_START;
10371 offset < TG3_NVM_DIR_END;
10372 offset += TG3_NVM_DIRENT_SIZE) {
10373 if (tg3_nvram_read(tp, offset, &val))
10376 if ((val >> TG3_NVM_DIRTYPE_SHIFT) ==
10377 TG3_NVM_DIRTYPE_EXTVPD)
10381 if (offset != TG3_NVM_DIR_END) {
10382 len = (val & TG3_NVM_DIRTYPE_LENMSK) * 4;
10383 if (tg3_nvram_read(tp, offset + 4, &offset))
10386 offset = tg3_nvram_logical_addr(tp, offset);
10390 if (!offset || !len) {
10391 offset = TG3_NVM_VPD_OFF;
10392 len = TG3_NVM_VPD_LEN;
10395 buf = kmalloc(len, GFP_KERNEL);
10399 if (magic == TG3_EEPROM_MAGIC) {
10400 for (i = 0; i < len; i += 4) {
10401 /* The data is in little-endian format in NVRAM.
10402 * Use the big-endian read routines to preserve
10403 * the byte order as it exists in NVRAM.
10405 if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4]))
10411 unsigned int pos = 0;
10413 ptr = (u8 *)&buf[0];
10414 for (i = 0; pos < len && i < 3; i++, pos += cnt, ptr += cnt) {
10415 cnt = pci_read_vpd(tp->pdev, pos,
10417 if (cnt == -ETIMEDOUT || cnt == -EINTR)
10433 #define NVRAM_TEST_SIZE 0x100
10434 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
10435 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
10436 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
10437 #define NVRAM_SELFBOOT_HW_SIZE 0x20
10438 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
10440 static int tg3_test_nvram(struct tg3 *tp)
10444 int i, j, k, err = 0, size;
10446 if (tg3_flag(tp, NO_NVRAM))
10449 if (tg3_nvram_read(tp, 0, &magic) != 0)
10452 if (magic == TG3_EEPROM_MAGIC)
10453 size = NVRAM_TEST_SIZE;
10454 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
10455 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10456 TG3_EEPROM_SB_FORMAT_1) {
10457 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10458 case TG3_EEPROM_SB_REVISION_0:
10459 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10461 case TG3_EEPROM_SB_REVISION_2:
10462 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10464 case TG3_EEPROM_SB_REVISION_3:
10465 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10472 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10473 size = NVRAM_SELFBOOT_HW_SIZE;
10477 buf = kmalloc(size, GFP_KERNEL);
10482 for (i = 0, j = 0; i < size; i += 4, j++) {
10483 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10490 /* Selfboot format */
10491 magic = be32_to_cpu(buf[0]);
10492 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
10493 TG3_EEPROM_MAGIC_FW) {
10494 u8 *buf8 = (u8 *) buf, csum8 = 0;
10496 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
10497 TG3_EEPROM_SB_REVISION_2) {
10498 /* For rev 2, the csum doesn't include the MBA. */
10499 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10501 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10504 for (i = 0; i < size; i++)
10517 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
10518 TG3_EEPROM_MAGIC_HW) {
10519 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
10520 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
10521 u8 *buf8 = (u8 *) buf;
10523 /* Separate the parity bits and the data bytes. */
10524 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10525 if ((i == 0) || (i == 8)) {
10529 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10530 parity[k++] = buf8[i] & msk;
10532 } else if (i == 16) {
10536 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10537 parity[k++] = buf8[i] & msk;
10540 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10541 parity[k++] = buf8[i] & msk;
10544 data[j++] = buf8[i];
10548 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10549 u8 hw8 = hweight8(data[i]);
10551 if ((hw8 & 0x1) && parity[i])
10553 else if (!(hw8 & 0x1) && !parity[i])
10562 /* Bootstrap checksum at offset 0x10 */
10563 csum = calc_crc((unsigned char *) buf, 0x10);
10564 if (csum != le32_to_cpu(buf[0x10/4]))
10567 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10568 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
10569 if (csum != le32_to_cpu(buf[0xfc/4]))
10574 buf = tg3_vpd_readblock(tp);
10578 i = pci_vpd_find_tag((u8 *)buf, 0, TG3_NVM_VPD_LEN,
10579 PCI_VPD_LRDT_RO_DATA);
10581 j = pci_vpd_lrdt_size(&((u8 *)buf)[i]);
10585 if (i + PCI_VPD_LRDT_TAG_SIZE + j > TG3_NVM_VPD_LEN)
10588 i += PCI_VPD_LRDT_TAG_SIZE;
10589 j = pci_vpd_find_info_keyword((u8 *)buf, i, j,
10590 PCI_VPD_RO_KEYWORD_CHKSUM);
10594 j += PCI_VPD_INFO_FLD_HDR_SIZE;
10596 for (i = 0; i <= j; i++)
10597 csum8 += ((u8 *)buf)[i];
10611 #define TG3_SERDES_TIMEOUT_SEC 2
10612 #define TG3_COPPER_TIMEOUT_SEC 6
10614 static int tg3_test_link(struct tg3 *tp)
10618 if (!netif_running(tp->dev))
10621 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
10622 max = TG3_SERDES_TIMEOUT_SEC;
10624 max = TG3_COPPER_TIMEOUT_SEC;
10626 for (i = 0; i < max; i++) {
10627 if (netif_carrier_ok(tp->dev))
10630 if (msleep_interruptible(1000))
10637 /* Only test the commonly used registers */
10638 static int tg3_test_registers(struct tg3 *tp)
10640 int i, is_5705, is_5750;
10641 u32 offset, read_mask, write_mask, val, save_val, read_val;
10645 #define TG3_FL_5705 0x1
10646 #define TG3_FL_NOT_5705 0x2
10647 #define TG3_FL_NOT_5788 0x4
10648 #define TG3_FL_NOT_5750 0x8
10652 /* MAC Control Registers */
10653 { MAC_MODE, TG3_FL_NOT_5705,
10654 0x00000000, 0x00ef6f8c },
10655 { MAC_MODE, TG3_FL_5705,
10656 0x00000000, 0x01ef6b8c },
10657 { MAC_STATUS, TG3_FL_NOT_5705,
10658 0x03800107, 0x00000000 },
10659 { MAC_STATUS, TG3_FL_5705,
10660 0x03800100, 0x00000000 },
10661 { MAC_ADDR_0_HIGH, 0x0000,
10662 0x00000000, 0x0000ffff },
10663 { MAC_ADDR_0_LOW, 0x0000,
10664 0x00000000, 0xffffffff },
10665 { MAC_RX_MTU_SIZE, 0x0000,
10666 0x00000000, 0x0000ffff },
10667 { MAC_TX_MODE, 0x0000,
10668 0x00000000, 0x00000070 },
10669 { MAC_TX_LENGTHS, 0x0000,
10670 0x00000000, 0x00003fff },
10671 { MAC_RX_MODE, TG3_FL_NOT_5705,
10672 0x00000000, 0x000007fc },
10673 { MAC_RX_MODE, TG3_FL_5705,
10674 0x00000000, 0x000007dc },
10675 { MAC_HASH_REG_0, 0x0000,
10676 0x00000000, 0xffffffff },
10677 { MAC_HASH_REG_1, 0x0000,
10678 0x00000000, 0xffffffff },
10679 { MAC_HASH_REG_2, 0x0000,
10680 0x00000000, 0xffffffff },
10681 { MAC_HASH_REG_3, 0x0000,
10682 0x00000000, 0xffffffff },
10684 /* Receive Data and Receive BD Initiator Control Registers. */
10685 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10686 0x00000000, 0xffffffff },
10687 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10688 0x00000000, 0xffffffff },
10689 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10690 0x00000000, 0x00000003 },
10691 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10692 0x00000000, 0xffffffff },
10693 { RCVDBDI_STD_BD+0, 0x0000,
10694 0x00000000, 0xffffffff },
10695 { RCVDBDI_STD_BD+4, 0x0000,
10696 0x00000000, 0xffffffff },
10697 { RCVDBDI_STD_BD+8, 0x0000,
10698 0x00000000, 0xffff0002 },
10699 { RCVDBDI_STD_BD+0xc, 0x0000,
10700 0x00000000, 0xffffffff },
10702 /* Receive BD Initiator Control Registers. */
10703 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10704 0x00000000, 0xffffffff },
10705 { RCVBDI_STD_THRESH, TG3_FL_5705,
10706 0x00000000, 0x000003ff },
10707 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10708 0x00000000, 0xffffffff },
10710 /* Host Coalescing Control Registers. */
10711 { HOSTCC_MODE, TG3_FL_NOT_5705,
10712 0x00000000, 0x00000004 },
10713 { HOSTCC_MODE, TG3_FL_5705,
10714 0x00000000, 0x000000f6 },
10715 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10716 0x00000000, 0xffffffff },
10717 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10718 0x00000000, 0x000003ff },
10719 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10720 0x00000000, 0xffffffff },
10721 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10722 0x00000000, 0x000003ff },
10723 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10724 0x00000000, 0xffffffff },
10725 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10726 0x00000000, 0x000000ff },
10727 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10728 0x00000000, 0xffffffff },
10729 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10730 0x00000000, 0x000000ff },
10731 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10732 0x00000000, 0xffffffff },
10733 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10734 0x00000000, 0xffffffff },
10735 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10736 0x00000000, 0xffffffff },
10737 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10738 0x00000000, 0x000000ff },
10739 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10740 0x00000000, 0xffffffff },
10741 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10742 0x00000000, 0x000000ff },
10743 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10744 0x00000000, 0xffffffff },
10745 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10746 0x00000000, 0xffffffff },
10747 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10748 0x00000000, 0xffffffff },
10749 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10750 0x00000000, 0xffffffff },
10751 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10752 0x00000000, 0xffffffff },
10753 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10754 0xffffffff, 0x00000000 },
10755 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10756 0xffffffff, 0x00000000 },
10758 /* Buffer Manager Control Registers. */
10759 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
10760 0x00000000, 0x007fff80 },
10761 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
10762 0x00000000, 0x007fffff },
10763 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10764 0x00000000, 0x0000003f },
10765 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10766 0x00000000, 0x000001ff },
10767 { BUFMGR_MB_HIGH_WATER, 0x0000,
10768 0x00000000, 0x000001ff },
10769 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10770 0xffffffff, 0x00000000 },
10771 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10772 0xffffffff, 0x00000000 },
10774 /* Mailbox Registers */
10775 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10776 0x00000000, 0x000001ff },
10777 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10778 0x00000000, 0x000001ff },
10779 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10780 0x00000000, 0x000007ff },
10781 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10782 0x00000000, 0x000001ff },
10784 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10787 is_5705 = is_5750 = 0;
10788 if (tg3_flag(tp, 5705_PLUS)) {
10790 if (tg3_flag(tp, 5750_PLUS))
10794 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10795 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10798 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10801 if (tg3_flag(tp, IS_5788) &&
10802 (reg_tbl[i].flags & TG3_FL_NOT_5788))
10805 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10808 offset = (u32) reg_tbl[i].offset;
10809 read_mask = reg_tbl[i].read_mask;
10810 write_mask = reg_tbl[i].write_mask;
10812 /* Save the original register content */
10813 save_val = tr32(offset);
10815 /* Determine the read-only value. */
10816 read_val = save_val & read_mask;
10818 /* Write zero to the register, then make sure the read-only bits
10819 * are not changed and the read/write bits are all zeros.
10823 val = tr32(offset);
10825 /* Test the read-only and read/write bits. */
10826 if (((val & read_mask) != read_val) || (val & write_mask))
10829 /* Write ones to all the bits defined by RdMask and WrMask, then
10830 * make sure the read-only bits are not changed and the
10831 * read/write bits are all ones.
10833 tw32(offset, read_mask | write_mask);
10835 val = tr32(offset);
10837 /* Test the read-only bits. */
10838 if ((val & read_mask) != read_val)
10841 /* Test the read/write bits. */
10842 if ((val & write_mask) != write_mask)
10845 tw32(offset, save_val);
10851 if (netif_msg_hw(tp))
10852 netdev_err(tp->dev,
10853 "Register test failed at offset %x\n", offset);
10854 tw32(offset, save_val);
10858 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10860 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10864 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
10865 for (j = 0; j < len; j += 4) {
10868 tg3_write_mem(tp, offset + j, test_pattern[i]);
10869 tg3_read_mem(tp, offset + j, &val);
10870 if (val != test_pattern[i])
10877 static int tg3_test_memory(struct tg3 *tp)
10879 static struct mem_entry {
10882 } mem_tbl_570x[] = {
10883 { 0x00000000, 0x00b50},
10884 { 0x00002000, 0x1c000},
10885 { 0xffffffff, 0x00000}
10886 }, mem_tbl_5705[] = {
10887 { 0x00000100, 0x0000c},
10888 { 0x00000200, 0x00008},
10889 { 0x00004000, 0x00800},
10890 { 0x00006000, 0x01000},
10891 { 0x00008000, 0x02000},
10892 { 0x00010000, 0x0e000},
10893 { 0xffffffff, 0x00000}
10894 }, mem_tbl_5755[] = {
10895 { 0x00000200, 0x00008},
10896 { 0x00004000, 0x00800},
10897 { 0x00006000, 0x00800},
10898 { 0x00008000, 0x02000},
10899 { 0x00010000, 0x0c000},
10900 { 0xffffffff, 0x00000}
10901 }, mem_tbl_5906[] = {
10902 { 0x00000200, 0x00008},
10903 { 0x00004000, 0x00400},
10904 { 0x00006000, 0x00400},
10905 { 0x00008000, 0x01000},
10906 { 0x00010000, 0x01000},
10907 { 0xffffffff, 0x00000}
10908 }, mem_tbl_5717[] = {
10909 { 0x00000200, 0x00008},
10910 { 0x00010000, 0x0a000},
10911 { 0x00020000, 0x13c00},
10912 { 0xffffffff, 0x00000}
10913 }, mem_tbl_57765[] = {
10914 { 0x00000200, 0x00008},
10915 { 0x00004000, 0x00800},
10916 { 0x00006000, 0x09800},
10917 { 0x00010000, 0x0a000},
10918 { 0xffffffff, 0x00000}
10920 struct mem_entry *mem_tbl;
10924 if (tg3_flag(tp, 5717_PLUS))
10925 mem_tbl = mem_tbl_5717;
10926 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
10927 mem_tbl = mem_tbl_57765;
10928 else if (tg3_flag(tp, 5755_PLUS))
10929 mem_tbl = mem_tbl_5755;
10930 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10931 mem_tbl = mem_tbl_5906;
10932 else if (tg3_flag(tp, 5705_PLUS))
10933 mem_tbl = mem_tbl_5705;
10935 mem_tbl = mem_tbl_570x;
10937 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10938 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
10946 #define TG3_MAC_LOOPBACK 0
10947 #define TG3_PHY_LOOPBACK 1
10948 #define TG3_TSO_LOOPBACK 2
10950 #define TG3_TSO_MSS 500
10952 #define TG3_TSO_IP_HDR_LEN 20
10953 #define TG3_TSO_TCP_HDR_LEN 20
10954 #define TG3_TSO_TCP_OPT_LEN 12
10956 static const u8 tg3_tso_header[] = {
10958 0x45, 0x00, 0x00, 0x00,
10959 0x00, 0x00, 0x40, 0x00,
10960 0x40, 0x06, 0x00, 0x00,
10961 0x0a, 0x00, 0x00, 0x01,
10962 0x0a, 0x00, 0x00, 0x02,
10963 0x0d, 0x00, 0xe0, 0x00,
10964 0x00, 0x00, 0x01, 0x00,
10965 0x00, 0x00, 0x02, 0x00,
10966 0x80, 0x10, 0x10, 0x00,
10967 0x14, 0x09, 0x00, 0x00,
10968 0x01, 0x01, 0x08, 0x0a,
10969 0x11, 0x11, 0x11, 0x11,
10970 0x11, 0x11, 0x11, 0x11,
10973 static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, int loopback_mode)
10975 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
10976 u32 base_flags = 0, mss = 0, desc_idx, coal_now, data_off, val;
10977 struct sk_buff *skb, *rx_skb;
10980 int num_pkts, tx_len, rx_len, i, err;
10981 struct tg3_rx_buffer_desc *desc;
10982 struct tg3_napi *tnapi, *rnapi;
10983 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
10985 tnapi = &tp->napi[0];
10986 rnapi = &tp->napi[0];
10987 if (tp->irq_cnt > 1) {
10988 if (tg3_flag(tp, ENABLE_RSS))
10989 rnapi = &tp->napi[1];
10990 if (tg3_flag(tp, ENABLE_TSS))
10991 tnapi = &tp->napi[1];
10993 coal_now = tnapi->coal_now | rnapi->coal_now;
10995 if (loopback_mode == TG3_MAC_LOOPBACK) {
10996 /* HW errata - mac loopback fails in some cases on 5780.
10997 * Normal traffic and PHY loopback are not affected by
10998 * errata. Also, the MAC loopback test is deprecated for
10999 * all newer ASIC revisions.
11001 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
11002 tg3_flag(tp, CPMU_PRESENT))
11005 mac_mode = tp->mac_mode &
11006 ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
11007 mac_mode |= MAC_MODE_PORT_INT_LPBACK;
11008 if (!tg3_flag(tp, 5705_PLUS))
11009 mac_mode |= MAC_MODE_LINK_POLARITY;
11010 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
11011 mac_mode |= MAC_MODE_PORT_MODE_MII;
11013 mac_mode |= MAC_MODE_PORT_MODE_GMII;
11014 tw32(MAC_MODE, mac_mode);
11016 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
11017 tg3_phy_fet_toggle_apd(tp, false);
11018 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
11020 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
11022 tg3_phy_toggle_automdix(tp, 0);
11024 tg3_writephy(tp, MII_BMCR, val);
11027 mac_mode = tp->mac_mode &
11028 ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
11029 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
11030 tg3_writephy(tp, MII_TG3_FET_PTEST,
11031 MII_TG3_FET_PTEST_FRC_TX_LINK |
11032 MII_TG3_FET_PTEST_FRC_TX_LOCK);
11033 /* The write needs to be flushed for the AC131 */
11034 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11035 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
11036 mac_mode |= MAC_MODE_PORT_MODE_MII;
11038 mac_mode |= MAC_MODE_PORT_MODE_GMII;
11040 /* reset to prevent losing 1st rx packet intermittently */
11041 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
11042 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
11044 tw32_f(MAC_RX_MODE, tp->rx_mode);
11046 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
11047 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
11048 if (masked_phy_id == TG3_PHY_ID_BCM5401)
11049 mac_mode &= ~MAC_MODE_LINK_POLARITY;
11050 else if (masked_phy_id == TG3_PHY_ID_BCM5411)
11051 mac_mode |= MAC_MODE_LINK_POLARITY;
11052 tg3_writephy(tp, MII_TG3_EXT_CTRL,
11053 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
11055 tw32(MAC_MODE, mac_mode);
11057 /* Wait for link */
11058 for (i = 0; i < 100; i++) {
11059 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
11068 skb = netdev_alloc_skb(tp->dev, tx_len);
11072 tx_data = skb_put(skb, tx_len);
11073 memcpy(tx_data, tp->dev->dev_addr, 6);
11074 memset(tx_data + 6, 0x0, 8);
11076 tw32(MAC_RX_MTU_SIZE, tx_len + ETH_FCS_LEN);
11078 if (loopback_mode == TG3_TSO_LOOPBACK) {
11079 struct iphdr *iph = (struct iphdr *)&tx_data[ETH_HLEN];
11081 u32 hdr_len = TG3_TSO_IP_HDR_LEN + TG3_TSO_TCP_HDR_LEN +
11082 TG3_TSO_TCP_OPT_LEN;
11084 memcpy(tx_data + ETH_ALEN * 2, tg3_tso_header,
11085 sizeof(tg3_tso_header));
11088 val = tx_len - ETH_ALEN * 2 - sizeof(tg3_tso_header);
11089 num_pkts = DIV_ROUND_UP(val, TG3_TSO_MSS);
11091 /* Set the total length field in the IP header */
11092 iph->tot_len = htons((u16)(mss + hdr_len));
11094 base_flags = (TXD_FLAG_CPU_PRE_DMA |
11095 TXD_FLAG_CPU_POST_DMA);
11097 if (tg3_flag(tp, HW_TSO_1) ||
11098 tg3_flag(tp, HW_TSO_2) ||
11099 tg3_flag(tp, HW_TSO_3)) {
11101 val = ETH_HLEN + TG3_TSO_IP_HDR_LEN;
11102 th = (struct tcphdr *)&tx_data[val];
11105 base_flags |= TXD_FLAG_TCPUDP_CSUM;
11107 if (tg3_flag(tp, HW_TSO_3)) {
11108 mss |= (hdr_len & 0xc) << 12;
11109 if (hdr_len & 0x10)
11110 base_flags |= 0x00000010;
11111 base_flags |= (hdr_len & 0x3e0) << 5;
11112 } else if (tg3_flag(tp, HW_TSO_2))
11113 mss |= hdr_len << 9;
11114 else if (tg3_flag(tp, HW_TSO_1) ||
11115 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
11116 mss |= (TG3_TSO_TCP_OPT_LEN << 9);
11118 base_flags |= (TG3_TSO_TCP_OPT_LEN << 10);
11121 data_off = ETH_ALEN * 2 + sizeof(tg3_tso_header);
11124 data_off = ETH_HLEN;
11127 for (i = data_off; i < tx_len; i++)
11128 tx_data[i] = (u8) (i & 0xff);
11130 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
11131 if (pci_dma_mapping_error(tp->pdev, map)) {
11132 dev_kfree_skb(skb);
11136 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
11141 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
11143 tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len,
11144 base_flags, (mss << 1) | 1);
11148 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
11149 tr32_mailbox(tnapi->prodmbox);
11153 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
11154 for (i = 0; i < 35; i++) {
11155 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
11160 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
11161 rx_idx = rnapi->hw_status->idx[0].rx_producer;
11162 if ((tx_idx == tnapi->tx_prod) &&
11163 (rx_idx == (rx_start_idx + num_pkts)))
11167 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
11168 dev_kfree_skb(skb);
11170 if (tx_idx != tnapi->tx_prod)
11173 if (rx_idx != rx_start_idx + num_pkts)
11177 while (rx_idx != rx_start_idx) {
11178 desc = &rnapi->rx_rcb[rx_start_idx++];
11179 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
11180 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
11182 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
11183 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
11186 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT)
11189 if (loopback_mode != TG3_TSO_LOOPBACK) {
11190 if (rx_len != tx_len)
11193 if (pktsz <= TG3_RX_STD_DMA_SZ - ETH_FCS_LEN) {
11194 if (opaque_key != RXD_OPAQUE_RING_STD)
11197 if (opaque_key != RXD_OPAQUE_RING_JUMBO)
11200 } else if ((desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
11201 (desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
11202 >> RXD_TCPCSUM_SHIFT != 0xffff) {
11206 if (opaque_key == RXD_OPAQUE_RING_STD) {
11207 rx_skb = tpr->rx_std_buffers[desc_idx].skb;
11208 map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx],
11210 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
11211 rx_skb = tpr->rx_jmb_buffers[desc_idx].skb;
11212 map = dma_unmap_addr(&tpr->rx_jmb_buffers[desc_idx],
11217 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len,
11218 PCI_DMA_FROMDEVICE);
11220 for (i = data_off; i < rx_len; i++, val++) {
11221 if (*(rx_skb->data + i) != (u8) (val & 0xff))
11228 /* tg3_free_rings will unmap and free the rx_skb */
11233 #define TG3_STD_LOOPBACK_FAILED 1
11234 #define TG3_JMB_LOOPBACK_FAILED 2
11235 #define TG3_TSO_LOOPBACK_FAILED 4
11237 #define TG3_MAC_LOOPBACK_SHIFT 0
11238 #define TG3_PHY_LOOPBACK_SHIFT 4
11239 #define TG3_LOOPBACK_FAILED 0x00000077
11241 static int tg3_test_loopback(struct tg3 *tp)
11244 u32 eee_cap, cpmuctrl = 0;
11246 if (!netif_running(tp->dev))
11247 return TG3_LOOPBACK_FAILED;
11249 eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP;
11250 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
11252 err = tg3_reset_hw(tp, 1);
11254 err = TG3_LOOPBACK_FAILED;
11258 if (tg3_flag(tp, ENABLE_RSS)) {
11261 /* Reroute all rx packets to the 1st queue */
11262 for (i = MAC_RSS_INDIR_TBL_0;
11263 i < MAC_RSS_INDIR_TBL_0 + TG3_RSS_INDIR_TBL_SIZE; i += 4)
11267 /* Turn off gphy autopowerdown. */
11268 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
11269 tg3_phy_toggle_apd(tp, false);
11271 if (tg3_flag(tp, CPMU_PRESENT)) {
11275 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
11277 /* Wait for up to 40 microseconds to acquire lock. */
11278 for (i = 0; i < 4; i++) {
11279 status = tr32(TG3_CPMU_MUTEX_GNT);
11280 if (status == CPMU_MUTEX_GNT_DRIVER)
11285 if (status != CPMU_MUTEX_GNT_DRIVER) {
11286 err = TG3_LOOPBACK_FAILED;
11290 /* Turn off link-based power management. */
11291 cpmuctrl = tr32(TG3_CPMU_CTRL);
11292 tw32(TG3_CPMU_CTRL,
11293 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
11294 CPMU_CTRL_LINK_AWARE_MODE));
11297 if (tg3_run_loopback(tp, ETH_FRAME_LEN, TG3_MAC_LOOPBACK))
11298 err |= TG3_STD_LOOPBACK_FAILED << TG3_MAC_LOOPBACK_SHIFT;
11300 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
11301 tg3_run_loopback(tp, 9000 + ETH_HLEN, TG3_MAC_LOOPBACK))
11302 err |= TG3_JMB_LOOPBACK_FAILED << TG3_MAC_LOOPBACK_SHIFT;
11304 if (tg3_flag(tp, CPMU_PRESENT)) {
11305 tw32(TG3_CPMU_CTRL, cpmuctrl);
11307 /* Release the mutex */
11308 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
11311 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
11312 !tg3_flag(tp, USE_PHYLIB)) {
11313 if (tg3_run_loopback(tp, ETH_FRAME_LEN, TG3_PHY_LOOPBACK))
11314 err |= TG3_STD_LOOPBACK_FAILED <<
11315 TG3_PHY_LOOPBACK_SHIFT;
11316 if (tg3_flag(tp, TSO_CAPABLE) &&
11317 tg3_run_loopback(tp, ETH_FRAME_LEN, TG3_TSO_LOOPBACK))
11318 err |= TG3_TSO_LOOPBACK_FAILED <<
11319 TG3_PHY_LOOPBACK_SHIFT;
11320 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
11321 tg3_run_loopback(tp, 9000 + ETH_HLEN, TG3_PHY_LOOPBACK))
11322 err |= TG3_JMB_LOOPBACK_FAILED <<
11323 TG3_PHY_LOOPBACK_SHIFT;
11326 /* Re-enable gphy autopowerdown. */
11327 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
11328 tg3_phy_toggle_apd(tp, true);
11331 tp->phy_flags |= eee_cap;
11336 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
11339 struct tg3 *tp = netdev_priv(dev);
11341 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11344 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
11346 if (tg3_test_nvram(tp) != 0) {
11347 etest->flags |= ETH_TEST_FL_FAILED;
11350 if (tg3_test_link(tp) != 0) {
11351 etest->flags |= ETH_TEST_FL_FAILED;
11354 if (etest->flags & ETH_TEST_FL_OFFLINE) {
11355 int err, err2 = 0, irq_sync = 0;
11357 if (netif_running(dev)) {
11359 tg3_netif_stop(tp);
11363 tg3_full_lock(tp, irq_sync);
11365 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
11366 err = tg3_nvram_lock(tp);
11367 tg3_halt_cpu(tp, RX_CPU_BASE);
11368 if (!tg3_flag(tp, 5705_PLUS))
11369 tg3_halt_cpu(tp, TX_CPU_BASE);
11371 tg3_nvram_unlock(tp);
11373 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
11376 if (tg3_test_registers(tp) != 0) {
11377 etest->flags |= ETH_TEST_FL_FAILED;
11380 if (tg3_test_memory(tp) != 0) {
11381 etest->flags |= ETH_TEST_FL_FAILED;
11384 if ((data[4] = tg3_test_loopback(tp)) != 0)
11385 etest->flags |= ETH_TEST_FL_FAILED;
11387 tg3_full_unlock(tp);
11389 if (tg3_test_interrupt(tp) != 0) {
11390 etest->flags |= ETH_TEST_FL_FAILED;
11394 tg3_full_lock(tp, 0);
11396 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11397 if (netif_running(dev)) {
11398 tg3_flag_set(tp, INIT_COMPLETE);
11399 err2 = tg3_restart_hw(tp, 1);
11401 tg3_netif_start(tp);
11404 tg3_full_unlock(tp);
11406 if (irq_sync && !err2)
11409 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11410 tg3_power_down(tp);
11414 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
11416 struct mii_ioctl_data *data = if_mii(ifr);
11417 struct tg3 *tp = netdev_priv(dev);
11420 if (tg3_flag(tp, USE_PHYLIB)) {
11421 struct phy_device *phydev;
11422 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
11424 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
11425 return phy_mii_ioctl(phydev, ifr, cmd);
11430 data->phy_id = tp->phy_addr;
11433 case SIOCGMIIREG: {
11436 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
11437 break; /* We have no PHY */
11439 if (!netif_running(dev))
11442 spin_lock_bh(&tp->lock);
11443 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
11444 spin_unlock_bh(&tp->lock);
11446 data->val_out = mii_regval;
11452 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
11453 break; /* We have no PHY */
11455 if (!netif_running(dev))
11458 spin_lock_bh(&tp->lock);
11459 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
11460 spin_unlock_bh(&tp->lock);
11468 return -EOPNOTSUPP;
11471 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11473 struct tg3 *tp = netdev_priv(dev);
11475 memcpy(ec, &tp->coal, sizeof(*ec));
11479 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11481 struct tg3 *tp = netdev_priv(dev);
11482 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
11483 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
11485 if (!tg3_flag(tp, 5705_PLUS)) {
11486 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
11487 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
11488 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
11489 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
11492 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
11493 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
11494 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
11495 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
11496 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
11497 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
11498 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
11499 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
11500 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
11501 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
11504 /* No rx interrupts will be generated if both are zero */
11505 if ((ec->rx_coalesce_usecs == 0) &&
11506 (ec->rx_max_coalesced_frames == 0))
11509 /* No tx interrupts will be generated if both are zero */
11510 if ((ec->tx_coalesce_usecs == 0) &&
11511 (ec->tx_max_coalesced_frames == 0))
11514 /* Only copy relevant parameters, ignore all others. */
11515 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
11516 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
11517 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
11518 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
11519 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
11520 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
11521 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
11522 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
11523 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
11525 if (netif_running(dev)) {
11526 tg3_full_lock(tp, 0);
11527 __tg3_set_coalesce(tp, &tp->coal);
11528 tg3_full_unlock(tp);
11533 static const struct ethtool_ops tg3_ethtool_ops = {
11534 .get_settings = tg3_get_settings,
11535 .set_settings = tg3_set_settings,
11536 .get_drvinfo = tg3_get_drvinfo,
11537 .get_regs_len = tg3_get_regs_len,
11538 .get_regs = tg3_get_regs,
11539 .get_wol = tg3_get_wol,
11540 .set_wol = tg3_set_wol,
11541 .get_msglevel = tg3_get_msglevel,
11542 .set_msglevel = tg3_set_msglevel,
11543 .nway_reset = tg3_nway_reset,
11544 .get_link = ethtool_op_get_link,
11545 .get_eeprom_len = tg3_get_eeprom_len,
11546 .get_eeprom = tg3_get_eeprom,
11547 .set_eeprom = tg3_set_eeprom,
11548 .get_ringparam = tg3_get_ringparam,
11549 .set_ringparam = tg3_set_ringparam,
11550 .get_pauseparam = tg3_get_pauseparam,
11551 .set_pauseparam = tg3_set_pauseparam,
11552 .self_test = tg3_self_test,
11553 .get_strings = tg3_get_strings,
11554 .set_phys_id = tg3_set_phys_id,
11555 .get_ethtool_stats = tg3_get_ethtool_stats,
11556 .get_coalesce = tg3_get_coalesce,
11557 .set_coalesce = tg3_set_coalesce,
11558 .get_sset_count = tg3_get_sset_count,
11561 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
11563 u32 cursize, val, magic;
11565 tp->nvram_size = EEPROM_CHIP_SIZE;
11567 if (tg3_nvram_read(tp, 0, &magic) != 0)
11570 if ((magic != TG3_EEPROM_MAGIC) &&
11571 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
11572 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
11576 * Size the chip by reading offsets at increasing powers of two.
11577 * When we encounter our validation signature, we know the addressing
11578 * has wrapped around, and thus have our chip size.
11582 while (cursize < tp->nvram_size) {
11583 if (tg3_nvram_read(tp, cursize, &val) != 0)
11592 tp->nvram_size = cursize;
11595 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
11599 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &val) != 0)
11602 /* Selfboot format */
11603 if (val != TG3_EEPROM_MAGIC) {
11604 tg3_get_eeprom_size(tp);
11608 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
11610 /* This is confusing. We want to operate on the
11611 * 16-bit value at offset 0xf2. The tg3_nvram_read()
11612 * call will read from NVRAM and byteswap the data
11613 * according to the byteswapping settings for all
11614 * other register accesses. This ensures the data we
11615 * want will always reside in the lower 16-bits.
11616 * However, the data in NVRAM is in LE format, which
11617 * means the data from the NVRAM read will always be
11618 * opposite the endianness of the CPU. The 16-bit
11619 * byteswap then brings the data to CPU endianness.
11621 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
11625 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11628 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
11632 nvcfg1 = tr32(NVRAM_CFG1);
11633 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
11634 tg3_flag_set(tp, FLASH);
11636 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11637 tw32(NVRAM_CFG1, nvcfg1);
11640 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
11641 tg3_flag(tp, 5780_CLASS)) {
11642 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
11643 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
11644 tp->nvram_jedecnum = JEDEC_ATMEL;
11645 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11646 tg3_flag_set(tp, NVRAM_BUFFERED);
11648 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
11649 tp->nvram_jedecnum = JEDEC_ATMEL;
11650 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
11652 case FLASH_VENDOR_ATMEL_EEPROM:
11653 tp->nvram_jedecnum = JEDEC_ATMEL;
11654 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11655 tg3_flag_set(tp, NVRAM_BUFFERED);
11657 case FLASH_VENDOR_ST:
11658 tp->nvram_jedecnum = JEDEC_ST;
11659 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
11660 tg3_flag_set(tp, NVRAM_BUFFERED);
11662 case FLASH_VENDOR_SAIFUN:
11663 tp->nvram_jedecnum = JEDEC_SAIFUN;
11664 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
11666 case FLASH_VENDOR_SST_SMALL:
11667 case FLASH_VENDOR_SST_LARGE:
11668 tp->nvram_jedecnum = JEDEC_SST;
11669 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
11673 tp->nvram_jedecnum = JEDEC_ATMEL;
11674 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11675 tg3_flag_set(tp, NVRAM_BUFFERED);
11679 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
11681 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11682 case FLASH_5752PAGE_SIZE_256:
11683 tp->nvram_pagesize = 256;
11685 case FLASH_5752PAGE_SIZE_512:
11686 tp->nvram_pagesize = 512;
11688 case FLASH_5752PAGE_SIZE_1K:
11689 tp->nvram_pagesize = 1024;
11691 case FLASH_5752PAGE_SIZE_2K:
11692 tp->nvram_pagesize = 2048;
11694 case FLASH_5752PAGE_SIZE_4K:
11695 tp->nvram_pagesize = 4096;
11697 case FLASH_5752PAGE_SIZE_264:
11698 tp->nvram_pagesize = 264;
11700 case FLASH_5752PAGE_SIZE_528:
11701 tp->nvram_pagesize = 528;
11706 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11710 nvcfg1 = tr32(NVRAM_CFG1);
11712 /* NVRAM protection for TPM */
11713 if (nvcfg1 & (1 << 27))
11714 tg3_flag_set(tp, PROTECTED_NVRAM);
11716 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11717 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11718 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11719 tp->nvram_jedecnum = JEDEC_ATMEL;
11720 tg3_flag_set(tp, NVRAM_BUFFERED);
11722 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11723 tp->nvram_jedecnum = JEDEC_ATMEL;
11724 tg3_flag_set(tp, NVRAM_BUFFERED);
11725 tg3_flag_set(tp, FLASH);
11727 case FLASH_5752VENDOR_ST_M45PE10:
11728 case FLASH_5752VENDOR_ST_M45PE20:
11729 case FLASH_5752VENDOR_ST_M45PE40:
11730 tp->nvram_jedecnum = JEDEC_ST;
11731 tg3_flag_set(tp, NVRAM_BUFFERED);
11732 tg3_flag_set(tp, FLASH);
11736 if (tg3_flag(tp, FLASH)) {
11737 tg3_nvram_get_pagesize(tp, nvcfg1);
11739 /* For eeprom, set pagesize to maximum eeprom size */
11740 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11742 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11743 tw32(NVRAM_CFG1, nvcfg1);
11747 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11749 u32 nvcfg1, protect = 0;
11751 nvcfg1 = tr32(NVRAM_CFG1);
11753 /* NVRAM protection for TPM */
11754 if (nvcfg1 & (1 << 27)) {
11755 tg3_flag_set(tp, PROTECTED_NVRAM);
11759 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11761 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11762 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11763 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11764 case FLASH_5755VENDOR_ATMEL_FLASH_5:
11765 tp->nvram_jedecnum = JEDEC_ATMEL;
11766 tg3_flag_set(tp, NVRAM_BUFFERED);
11767 tg3_flag_set(tp, FLASH);
11768 tp->nvram_pagesize = 264;
11769 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11770 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11771 tp->nvram_size = (protect ? 0x3e200 :
11772 TG3_NVRAM_SIZE_512KB);
11773 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11774 tp->nvram_size = (protect ? 0x1f200 :
11775 TG3_NVRAM_SIZE_256KB);
11777 tp->nvram_size = (protect ? 0x1f200 :
11778 TG3_NVRAM_SIZE_128KB);
11780 case FLASH_5752VENDOR_ST_M45PE10:
11781 case FLASH_5752VENDOR_ST_M45PE20:
11782 case FLASH_5752VENDOR_ST_M45PE40:
11783 tp->nvram_jedecnum = JEDEC_ST;
11784 tg3_flag_set(tp, NVRAM_BUFFERED);
11785 tg3_flag_set(tp, FLASH);
11786 tp->nvram_pagesize = 256;
11787 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11788 tp->nvram_size = (protect ?
11789 TG3_NVRAM_SIZE_64KB :
11790 TG3_NVRAM_SIZE_128KB);
11791 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11792 tp->nvram_size = (protect ?
11793 TG3_NVRAM_SIZE_64KB :
11794 TG3_NVRAM_SIZE_256KB);
11796 tp->nvram_size = (protect ?
11797 TG3_NVRAM_SIZE_128KB :
11798 TG3_NVRAM_SIZE_512KB);
11803 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11807 nvcfg1 = tr32(NVRAM_CFG1);
11809 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11810 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11811 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11812 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11813 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11814 tp->nvram_jedecnum = JEDEC_ATMEL;
11815 tg3_flag_set(tp, NVRAM_BUFFERED);
11816 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11818 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11819 tw32(NVRAM_CFG1, nvcfg1);
11821 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11822 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11823 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11824 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11825 tp->nvram_jedecnum = JEDEC_ATMEL;
11826 tg3_flag_set(tp, NVRAM_BUFFERED);
11827 tg3_flag_set(tp, FLASH);
11828 tp->nvram_pagesize = 264;
11830 case FLASH_5752VENDOR_ST_M45PE10:
11831 case FLASH_5752VENDOR_ST_M45PE20:
11832 case FLASH_5752VENDOR_ST_M45PE40:
11833 tp->nvram_jedecnum = JEDEC_ST;
11834 tg3_flag_set(tp, NVRAM_BUFFERED);
11835 tg3_flag_set(tp, FLASH);
11836 tp->nvram_pagesize = 256;
11841 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11843 u32 nvcfg1, protect = 0;
11845 nvcfg1 = tr32(NVRAM_CFG1);
11847 /* NVRAM protection for TPM */
11848 if (nvcfg1 & (1 << 27)) {
11849 tg3_flag_set(tp, PROTECTED_NVRAM);
11853 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11855 case FLASH_5761VENDOR_ATMEL_ADB021D:
11856 case FLASH_5761VENDOR_ATMEL_ADB041D:
11857 case FLASH_5761VENDOR_ATMEL_ADB081D:
11858 case FLASH_5761VENDOR_ATMEL_ADB161D:
11859 case FLASH_5761VENDOR_ATMEL_MDB021D:
11860 case FLASH_5761VENDOR_ATMEL_MDB041D:
11861 case FLASH_5761VENDOR_ATMEL_MDB081D:
11862 case FLASH_5761VENDOR_ATMEL_MDB161D:
11863 tp->nvram_jedecnum = JEDEC_ATMEL;
11864 tg3_flag_set(tp, NVRAM_BUFFERED);
11865 tg3_flag_set(tp, FLASH);
11866 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
11867 tp->nvram_pagesize = 256;
11869 case FLASH_5761VENDOR_ST_A_M45PE20:
11870 case FLASH_5761VENDOR_ST_A_M45PE40:
11871 case FLASH_5761VENDOR_ST_A_M45PE80:
11872 case FLASH_5761VENDOR_ST_A_M45PE16:
11873 case FLASH_5761VENDOR_ST_M_M45PE20:
11874 case FLASH_5761VENDOR_ST_M_M45PE40:
11875 case FLASH_5761VENDOR_ST_M_M45PE80:
11876 case FLASH_5761VENDOR_ST_M_M45PE16:
11877 tp->nvram_jedecnum = JEDEC_ST;
11878 tg3_flag_set(tp, NVRAM_BUFFERED);
11879 tg3_flag_set(tp, FLASH);
11880 tp->nvram_pagesize = 256;
11885 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11888 case FLASH_5761VENDOR_ATMEL_ADB161D:
11889 case FLASH_5761VENDOR_ATMEL_MDB161D:
11890 case FLASH_5761VENDOR_ST_A_M45PE16:
11891 case FLASH_5761VENDOR_ST_M_M45PE16:
11892 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11894 case FLASH_5761VENDOR_ATMEL_ADB081D:
11895 case FLASH_5761VENDOR_ATMEL_MDB081D:
11896 case FLASH_5761VENDOR_ST_A_M45PE80:
11897 case FLASH_5761VENDOR_ST_M_M45PE80:
11898 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11900 case FLASH_5761VENDOR_ATMEL_ADB041D:
11901 case FLASH_5761VENDOR_ATMEL_MDB041D:
11902 case FLASH_5761VENDOR_ST_A_M45PE40:
11903 case FLASH_5761VENDOR_ST_M_M45PE40:
11904 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11906 case FLASH_5761VENDOR_ATMEL_ADB021D:
11907 case FLASH_5761VENDOR_ATMEL_MDB021D:
11908 case FLASH_5761VENDOR_ST_A_M45PE20:
11909 case FLASH_5761VENDOR_ST_M_M45PE20:
11910 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11916 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11918 tp->nvram_jedecnum = JEDEC_ATMEL;
11919 tg3_flag_set(tp, NVRAM_BUFFERED);
11920 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11923 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11927 nvcfg1 = tr32(NVRAM_CFG1);
11929 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11930 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11931 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11932 tp->nvram_jedecnum = JEDEC_ATMEL;
11933 tg3_flag_set(tp, NVRAM_BUFFERED);
11934 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11936 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11937 tw32(NVRAM_CFG1, nvcfg1);
11939 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11940 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11941 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11942 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11943 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11944 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11945 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11946 tp->nvram_jedecnum = JEDEC_ATMEL;
11947 tg3_flag_set(tp, NVRAM_BUFFERED);
11948 tg3_flag_set(tp, FLASH);
11950 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11951 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11952 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11953 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11954 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11956 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11957 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11958 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11960 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11961 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11962 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11966 case FLASH_5752VENDOR_ST_M45PE10:
11967 case FLASH_5752VENDOR_ST_M45PE20:
11968 case FLASH_5752VENDOR_ST_M45PE40:
11969 tp->nvram_jedecnum = JEDEC_ST;
11970 tg3_flag_set(tp, NVRAM_BUFFERED);
11971 tg3_flag_set(tp, FLASH);
11973 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11974 case FLASH_5752VENDOR_ST_M45PE10:
11975 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11977 case FLASH_5752VENDOR_ST_M45PE20:
11978 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11980 case FLASH_5752VENDOR_ST_M45PE40:
11981 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11986 tg3_flag_set(tp, NO_NVRAM);
11990 tg3_nvram_get_pagesize(tp, nvcfg1);
11991 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11992 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
11996 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
12000 nvcfg1 = tr32(NVRAM_CFG1);
12002 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12003 case FLASH_5717VENDOR_ATMEL_EEPROM:
12004 case FLASH_5717VENDOR_MICRO_EEPROM:
12005 tp->nvram_jedecnum = JEDEC_ATMEL;
12006 tg3_flag_set(tp, NVRAM_BUFFERED);
12007 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12009 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12010 tw32(NVRAM_CFG1, nvcfg1);
12012 case FLASH_5717VENDOR_ATMEL_MDB011D:
12013 case FLASH_5717VENDOR_ATMEL_ADB011B:
12014 case FLASH_5717VENDOR_ATMEL_ADB011D:
12015 case FLASH_5717VENDOR_ATMEL_MDB021D:
12016 case FLASH_5717VENDOR_ATMEL_ADB021B:
12017 case FLASH_5717VENDOR_ATMEL_ADB021D:
12018 case FLASH_5717VENDOR_ATMEL_45USPT:
12019 tp->nvram_jedecnum = JEDEC_ATMEL;
12020 tg3_flag_set(tp, NVRAM_BUFFERED);
12021 tg3_flag_set(tp, FLASH);
12023 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12024 case FLASH_5717VENDOR_ATMEL_MDB021D:
12025 /* Detect size with tg3_nvram_get_size() */
12027 case FLASH_5717VENDOR_ATMEL_ADB021B:
12028 case FLASH_5717VENDOR_ATMEL_ADB021D:
12029 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12032 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12036 case FLASH_5717VENDOR_ST_M_M25PE10:
12037 case FLASH_5717VENDOR_ST_A_M25PE10:
12038 case FLASH_5717VENDOR_ST_M_M45PE10:
12039 case FLASH_5717VENDOR_ST_A_M45PE10:
12040 case FLASH_5717VENDOR_ST_M_M25PE20:
12041 case FLASH_5717VENDOR_ST_A_M25PE20:
12042 case FLASH_5717VENDOR_ST_M_M45PE20:
12043 case FLASH_5717VENDOR_ST_A_M45PE20:
12044 case FLASH_5717VENDOR_ST_25USPT:
12045 case FLASH_5717VENDOR_ST_45USPT:
12046 tp->nvram_jedecnum = JEDEC_ST;
12047 tg3_flag_set(tp, NVRAM_BUFFERED);
12048 tg3_flag_set(tp, FLASH);
12050 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12051 case FLASH_5717VENDOR_ST_M_M25PE20:
12052 case FLASH_5717VENDOR_ST_M_M45PE20:
12053 /* Detect size with tg3_nvram_get_size() */
12055 case FLASH_5717VENDOR_ST_A_M25PE20:
12056 case FLASH_5717VENDOR_ST_A_M45PE20:
12057 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12060 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12065 tg3_flag_set(tp, NO_NVRAM);
12069 tg3_nvram_get_pagesize(tp, nvcfg1);
12070 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
12071 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
12074 static void __devinit tg3_get_5720_nvram_info(struct tg3 *tp)
12076 u32 nvcfg1, nvmpinstrp;
12078 nvcfg1 = tr32(NVRAM_CFG1);
12079 nvmpinstrp = nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK;
12081 switch (nvmpinstrp) {
12082 case FLASH_5720_EEPROM_HD:
12083 case FLASH_5720_EEPROM_LD:
12084 tp->nvram_jedecnum = JEDEC_ATMEL;
12085 tg3_flag_set(tp, NVRAM_BUFFERED);
12087 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12088 tw32(NVRAM_CFG1, nvcfg1);
12089 if (nvmpinstrp == FLASH_5720_EEPROM_HD)
12090 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12092 tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE;
12094 case FLASH_5720VENDOR_M_ATMEL_DB011D:
12095 case FLASH_5720VENDOR_A_ATMEL_DB011B:
12096 case FLASH_5720VENDOR_A_ATMEL_DB011D:
12097 case FLASH_5720VENDOR_M_ATMEL_DB021D:
12098 case FLASH_5720VENDOR_A_ATMEL_DB021B:
12099 case FLASH_5720VENDOR_A_ATMEL_DB021D:
12100 case FLASH_5720VENDOR_M_ATMEL_DB041D:
12101 case FLASH_5720VENDOR_A_ATMEL_DB041B:
12102 case FLASH_5720VENDOR_A_ATMEL_DB041D:
12103 case FLASH_5720VENDOR_M_ATMEL_DB081D:
12104 case FLASH_5720VENDOR_A_ATMEL_DB081D:
12105 case FLASH_5720VENDOR_ATMEL_45USPT:
12106 tp->nvram_jedecnum = JEDEC_ATMEL;
12107 tg3_flag_set(tp, NVRAM_BUFFERED);
12108 tg3_flag_set(tp, FLASH);
12110 switch (nvmpinstrp) {
12111 case FLASH_5720VENDOR_M_ATMEL_DB021D:
12112 case FLASH_5720VENDOR_A_ATMEL_DB021B:
12113 case FLASH_5720VENDOR_A_ATMEL_DB021D:
12114 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12116 case FLASH_5720VENDOR_M_ATMEL_DB041D:
12117 case FLASH_5720VENDOR_A_ATMEL_DB041B:
12118 case FLASH_5720VENDOR_A_ATMEL_DB041D:
12119 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
12121 case FLASH_5720VENDOR_M_ATMEL_DB081D:
12122 case FLASH_5720VENDOR_A_ATMEL_DB081D:
12123 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
12126 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12130 case FLASH_5720VENDOR_M_ST_M25PE10:
12131 case FLASH_5720VENDOR_M_ST_M45PE10:
12132 case FLASH_5720VENDOR_A_ST_M25PE10:
12133 case FLASH_5720VENDOR_A_ST_M45PE10:
12134 case FLASH_5720VENDOR_M_ST_M25PE20:
12135 case FLASH_5720VENDOR_M_ST_M45PE20:
12136 case FLASH_5720VENDOR_A_ST_M25PE20:
12137 case FLASH_5720VENDOR_A_ST_M45PE20:
12138 case FLASH_5720VENDOR_M_ST_M25PE40:
12139 case FLASH_5720VENDOR_M_ST_M45PE40:
12140 case FLASH_5720VENDOR_A_ST_M25PE40:
12141 case FLASH_5720VENDOR_A_ST_M45PE40:
12142 case FLASH_5720VENDOR_M_ST_M25PE80:
12143 case FLASH_5720VENDOR_M_ST_M45PE80:
12144 case FLASH_5720VENDOR_A_ST_M25PE80:
12145 case FLASH_5720VENDOR_A_ST_M45PE80:
12146 case FLASH_5720VENDOR_ST_25USPT:
12147 case FLASH_5720VENDOR_ST_45USPT:
12148 tp->nvram_jedecnum = JEDEC_ST;
12149 tg3_flag_set(tp, NVRAM_BUFFERED);
12150 tg3_flag_set(tp, FLASH);
12152 switch (nvmpinstrp) {
12153 case FLASH_5720VENDOR_M_ST_M25PE20:
12154 case FLASH_5720VENDOR_M_ST_M45PE20:
12155 case FLASH_5720VENDOR_A_ST_M25PE20:
12156 case FLASH_5720VENDOR_A_ST_M45PE20:
12157 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12159 case FLASH_5720VENDOR_M_ST_M25PE40:
12160 case FLASH_5720VENDOR_M_ST_M45PE40:
12161 case FLASH_5720VENDOR_A_ST_M25PE40:
12162 case FLASH_5720VENDOR_A_ST_M45PE40:
12163 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
12165 case FLASH_5720VENDOR_M_ST_M25PE80:
12166 case FLASH_5720VENDOR_M_ST_M45PE80:
12167 case FLASH_5720VENDOR_A_ST_M25PE80:
12168 case FLASH_5720VENDOR_A_ST_M45PE80:
12169 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
12172 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12177 tg3_flag_set(tp, NO_NVRAM);
12181 tg3_nvram_get_pagesize(tp, nvcfg1);
12182 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
12183 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
12186 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
12187 static void __devinit tg3_nvram_init(struct tg3 *tp)
12189 tw32_f(GRC_EEPROM_ADDR,
12190 (EEPROM_ADDR_FSM_RESET |
12191 (EEPROM_DEFAULT_CLOCK_PERIOD <<
12192 EEPROM_ADDR_CLKPERD_SHIFT)));
12196 /* Enable seeprom accesses. */
12197 tw32_f(GRC_LOCAL_CTRL,
12198 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
12201 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12202 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
12203 tg3_flag_set(tp, NVRAM);
12205 if (tg3_nvram_lock(tp)) {
12206 netdev_warn(tp->dev,
12207 "Cannot get nvram lock, %s failed\n",
12211 tg3_enable_nvram_access(tp);
12213 tp->nvram_size = 0;
12215 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12216 tg3_get_5752_nvram_info(tp);
12217 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
12218 tg3_get_5755_nvram_info(tp);
12219 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12220 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12221 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12222 tg3_get_5787_nvram_info(tp);
12223 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
12224 tg3_get_5761_nvram_info(tp);
12225 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12226 tg3_get_5906_nvram_info(tp);
12227 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
12228 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
12229 tg3_get_57780_nvram_info(tp);
12230 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
12231 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
12232 tg3_get_5717_nvram_info(tp);
12233 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
12234 tg3_get_5720_nvram_info(tp);
12236 tg3_get_nvram_info(tp);
12238 if (tp->nvram_size == 0)
12239 tg3_get_nvram_size(tp);
12241 tg3_disable_nvram_access(tp);
12242 tg3_nvram_unlock(tp);
12245 tg3_flag_clear(tp, NVRAM);
12246 tg3_flag_clear(tp, NVRAM_BUFFERED);
12248 tg3_get_eeprom_size(tp);
12252 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
12253 u32 offset, u32 len, u8 *buf)
12258 for (i = 0; i < len; i += 4) {
12264 memcpy(&data, buf + i, 4);
12267 * The SEEPROM interface expects the data to always be opposite
12268 * the native endian format. We accomplish this by reversing
12269 * all the operations that would have been performed on the
12270 * data from a call to tg3_nvram_read_be32().
12272 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
12274 val = tr32(GRC_EEPROM_ADDR);
12275 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
12277 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
12279 tw32(GRC_EEPROM_ADDR, val |
12280 (0 << EEPROM_ADDR_DEVID_SHIFT) |
12281 (addr & EEPROM_ADDR_ADDR_MASK) |
12282 EEPROM_ADDR_START |
12283 EEPROM_ADDR_WRITE);
12285 for (j = 0; j < 1000; j++) {
12286 val = tr32(GRC_EEPROM_ADDR);
12288 if (val & EEPROM_ADDR_COMPLETE)
12292 if (!(val & EEPROM_ADDR_COMPLETE)) {
12301 /* offset and length are dword aligned */
12302 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
12306 u32 pagesize = tp->nvram_pagesize;
12307 u32 pagemask = pagesize - 1;
12311 tmp = kmalloc(pagesize, GFP_KERNEL);
12317 u32 phy_addr, page_off, size;
12319 phy_addr = offset & ~pagemask;
12321 for (j = 0; j < pagesize; j += 4) {
12322 ret = tg3_nvram_read_be32(tp, phy_addr + j,
12323 (__be32 *) (tmp + j));
12330 page_off = offset & pagemask;
12337 memcpy(tmp + page_off, buf, size);
12339 offset = offset + (pagesize - page_off);
12341 tg3_enable_nvram_access(tp);
12344 * Before we can erase the flash page, we need
12345 * to issue a special "write enable" command.
12347 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
12349 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
12352 /* Erase the target page */
12353 tw32(NVRAM_ADDR, phy_addr);
12355 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
12356 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
12358 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
12361 /* Issue another write enable to start the write. */
12362 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
12364 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
12367 for (j = 0; j < pagesize; j += 4) {
12370 data = *((__be32 *) (tmp + j));
12372 tw32(NVRAM_WRDATA, be32_to_cpu(data));
12374 tw32(NVRAM_ADDR, phy_addr + j);
12376 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
12380 nvram_cmd |= NVRAM_CMD_FIRST;
12381 else if (j == (pagesize - 4))
12382 nvram_cmd |= NVRAM_CMD_LAST;
12384 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
12391 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
12392 tg3_nvram_exec_cmd(tp, nvram_cmd);
12399 /* offset and length are dword aligned */
12400 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
12405 for (i = 0; i < len; i += 4, offset += 4) {
12406 u32 page_off, phy_addr, nvram_cmd;
12409 memcpy(&data, buf + i, 4);
12410 tw32(NVRAM_WRDATA, be32_to_cpu(data));
12412 page_off = offset % tp->nvram_pagesize;
12414 phy_addr = tg3_nvram_phys_addr(tp, offset);
12416 tw32(NVRAM_ADDR, phy_addr);
12418 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
12420 if (page_off == 0 || i == 0)
12421 nvram_cmd |= NVRAM_CMD_FIRST;
12422 if (page_off == (tp->nvram_pagesize - 4))
12423 nvram_cmd |= NVRAM_CMD_LAST;
12425 if (i == (len - 4))
12426 nvram_cmd |= NVRAM_CMD_LAST;
12428 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
12429 !tg3_flag(tp, 5755_PLUS) &&
12430 (tp->nvram_jedecnum == JEDEC_ST) &&
12431 (nvram_cmd & NVRAM_CMD_FIRST)) {
12433 if ((ret = tg3_nvram_exec_cmd(tp,
12434 NVRAM_CMD_WREN | NVRAM_CMD_GO |
12439 if (!tg3_flag(tp, FLASH)) {
12440 /* We always do complete word writes to eeprom. */
12441 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
12444 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
12450 /* offset and length are dword aligned */
12451 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
12455 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
12456 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
12457 ~GRC_LCLCTRL_GPIO_OUTPUT1);
12461 if (!tg3_flag(tp, NVRAM)) {
12462 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
12466 ret = tg3_nvram_lock(tp);
12470 tg3_enable_nvram_access(tp);
12471 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM))
12472 tw32(NVRAM_WRITE1, 0x406);
12474 grc_mode = tr32(GRC_MODE);
12475 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
12477 if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) {
12478 ret = tg3_nvram_write_block_buffered(tp, offset, len,
12481 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
12485 grc_mode = tr32(GRC_MODE);
12486 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
12488 tg3_disable_nvram_access(tp);
12489 tg3_nvram_unlock(tp);
12492 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
12493 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
12500 struct subsys_tbl_ent {
12501 u16 subsys_vendor, subsys_devid;
12505 static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = {
12506 /* Broadcom boards. */
12507 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12508 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
12509 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12510 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
12511 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12512 TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
12513 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12514 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
12515 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12516 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
12517 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12518 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
12519 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12520 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
12521 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12522 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
12523 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12524 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
12525 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12526 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
12527 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12528 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
12531 { TG3PCI_SUBVENDOR_ID_3COM,
12532 TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
12533 { TG3PCI_SUBVENDOR_ID_3COM,
12534 TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
12535 { TG3PCI_SUBVENDOR_ID_3COM,
12536 TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
12537 { TG3PCI_SUBVENDOR_ID_3COM,
12538 TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
12539 { TG3PCI_SUBVENDOR_ID_3COM,
12540 TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
12543 { TG3PCI_SUBVENDOR_ID_DELL,
12544 TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
12545 { TG3PCI_SUBVENDOR_ID_DELL,
12546 TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
12547 { TG3PCI_SUBVENDOR_ID_DELL,
12548 TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
12549 { TG3PCI_SUBVENDOR_ID_DELL,
12550 TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
12552 /* Compaq boards. */
12553 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12554 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
12555 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12556 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
12557 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12558 TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
12559 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12560 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
12561 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12562 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
12565 { TG3PCI_SUBVENDOR_ID_IBM,
12566 TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
12569 static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp)
12573 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
12574 if ((subsys_id_to_phy_id[i].subsys_vendor ==
12575 tp->pdev->subsystem_vendor) &&
12576 (subsys_id_to_phy_id[i].subsys_devid ==
12577 tp->pdev->subsystem_device))
12578 return &subsys_id_to_phy_id[i];
12583 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
12588 /* On some early chips the SRAM cannot be accessed in D3hot state,
12589 * so need make sure we're in D0.
12591 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
12592 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
12593 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
12596 /* Make sure register accesses (indirect or otherwise)
12597 * will function correctly.
12599 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12600 tp->misc_host_ctrl);
12602 /* The memory arbiter has to be enabled in order for SRAM accesses
12603 * to succeed. Normally on powerup the tg3 chip firmware will make
12604 * sure it is enabled, but other entities such as system netboot
12605 * code might disable it.
12607 val = tr32(MEMARB_MODE);
12608 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
12610 tp->phy_id = TG3_PHY_ID_INVALID;
12611 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12613 /* Assume an onboard device and WOL capable by default. */
12614 tg3_flag_set(tp, EEPROM_WRITE_PROT);
12615 tg3_flag_set(tp, WOL_CAP);
12617 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12618 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
12619 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
12620 tg3_flag_set(tp, IS_NIC);
12622 val = tr32(VCPU_CFGSHDW);
12623 if (val & VCPU_CFGSHDW_ASPM_DBNC)
12624 tg3_flag_set(tp, ASPM_WORKAROUND);
12625 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
12626 (val & VCPU_CFGSHDW_WOL_MAGPKT)) {
12627 tg3_flag_set(tp, WOL_ENABLE);
12628 device_set_wakeup_enable(&tp->pdev->dev, true);
12633 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
12634 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
12635 u32 nic_cfg, led_cfg;
12636 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
12637 int eeprom_phy_serdes = 0;
12639 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
12640 tp->nic_sram_data_cfg = nic_cfg;
12642 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
12643 ver >>= NIC_SRAM_DATA_VER_SHIFT;
12644 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12645 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
12646 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703 &&
12647 (ver > 0) && (ver < 0x100))
12648 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
12650 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12651 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
12653 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
12654 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
12655 eeprom_phy_serdes = 1;
12657 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
12658 if (nic_phy_id != 0) {
12659 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
12660 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
12662 eeprom_phy_id = (id1 >> 16) << 10;
12663 eeprom_phy_id |= (id2 & 0xfc00) << 16;
12664 eeprom_phy_id |= (id2 & 0x03ff) << 0;
12668 tp->phy_id = eeprom_phy_id;
12669 if (eeprom_phy_serdes) {
12670 if (!tg3_flag(tp, 5705_PLUS))
12671 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12673 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
12676 if (tg3_flag(tp, 5750_PLUS))
12677 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
12678 SHASTA_EXT_LED_MODE_MASK);
12680 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
12684 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
12685 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12688 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
12689 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12692 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
12693 tp->led_ctrl = LED_CTRL_MODE_MAC;
12695 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12696 * read on some older 5700/5701 bootcode.
12698 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12700 GET_ASIC_REV(tp->pci_chip_rev_id) ==
12702 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12706 case SHASTA_EXT_LED_SHARED:
12707 tp->led_ctrl = LED_CTRL_MODE_SHARED;
12708 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
12709 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
12710 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12711 LED_CTRL_MODE_PHY_2);
12714 case SHASTA_EXT_LED_MAC:
12715 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
12718 case SHASTA_EXT_LED_COMBO:
12719 tp->led_ctrl = LED_CTRL_MODE_COMBO;
12720 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
12721 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12722 LED_CTRL_MODE_PHY_2);
12727 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12728 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
12729 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
12730 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12732 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
12733 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12735 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
12736 tg3_flag_set(tp, EEPROM_WRITE_PROT);
12737 if ((tp->pdev->subsystem_vendor ==
12738 PCI_VENDOR_ID_ARIMA) &&
12739 (tp->pdev->subsystem_device == 0x205a ||
12740 tp->pdev->subsystem_device == 0x2063))
12741 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
12743 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
12744 tg3_flag_set(tp, IS_NIC);
12747 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
12748 tg3_flag_set(tp, ENABLE_ASF);
12749 if (tg3_flag(tp, 5750_PLUS))
12750 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
12753 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
12754 tg3_flag(tp, 5750_PLUS))
12755 tg3_flag_set(tp, ENABLE_APE);
12757 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
12758 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
12759 tg3_flag_clear(tp, WOL_CAP);
12761 if (tg3_flag(tp, WOL_CAP) &&
12762 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)) {
12763 tg3_flag_set(tp, WOL_ENABLE);
12764 device_set_wakeup_enable(&tp->pdev->dev, true);
12767 if (cfg2 & (1 << 17))
12768 tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
12770 /* serdes signal pre-emphasis in register 0x590 set by */
12771 /* bootcode if bit 18 is set */
12772 if (cfg2 & (1 << 18))
12773 tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
12775 if ((tg3_flag(tp, 57765_PLUS) ||
12776 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12777 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
12778 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
12779 tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
12781 if (tg3_flag(tp, PCI_EXPRESS) &&
12782 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12783 !tg3_flag(tp, 57765_PLUS)) {
12786 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
12787 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
12788 tg3_flag_set(tp, ASPM_WORKAROUND);
12791 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
12792 tg3_flag_set(tp, RGMII_INBAND_DISABLE);
12793 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
12794 tg3_flag_set(tp, RGMII_EXT_IBND_RX_EN);
12795 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
12796 tg3_flag_set(tp, RGMII_EXT_IBND_TX_EN);
12799 if (tg3_flag(tp, WOL_CAP))
12800 device_set_wakeup_enable(&tp->pdev->dev,
12801 tg3_flag(tp, WOL_ENABLE));
12803 device_set_wakeup_capable(&tp->pdev->dev, false);
12806 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
12811 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
12812 tw32(OTP_CTRL, cmd);
12814 /* Wait for up to 1 ms for command to execute. */
12815 for (i = 0; i < 100; i++) {
12816 val = tr32(OTP_STATUS);
12817 if (val & OTP_STATUS_CMD_DONE)
12822 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
12825 /* Read the gphy configuration from the OTP region of the chip. The gphy
12826 * configuration is a 32-bit value that straddles the alignment boundary.
12827 * We do two 32-bit reads and then shift and merge the results.
12829 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
12831 u32 bhalf_otp, thalf_otp;
12833 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12835 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12838 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12840 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12843 thalf_otp = tr32(OTP_READ_DATA);
12845 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12847 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12850 bhalf_otp = tr32(OTP_READ_DATA);
12852 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12855 static void __devinit tg3_phy_init_link_config(struct tg3 *tp)
12857 u32 adv = ADVERTISED_Autoneg |
12860 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12861 adv |= ADVERTISED_1000baseT_Half |
12862 ADVERTISED_1000baseT_Full;
12864 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
12865 adv |= ADVERTISED_100baseT_Half |
12866 ADVERTISED_100baseT_Full |
12867 ADVERTISED_10baseT_Half |
12868 ADVERTISED_10baseT_Full |
12871 adv |= ADVERTISED_FIBRE;
12873 tp->link_config.advertising = adv;
12874 tp->link_config.speed = SPEED_INVALID;
12875 tp->link_config.duplex = DUPLEX_INVALID;
12876 tp->link_config.autoneg = AUTONEG_ENABLE;
12877 tp->link_config.active_speed = SPEED_INVALID;
12878 tp->link_config.active_duplex = DUPLEX_INVALID;
12879 tp->link_config.orig_speed = SPEED_INVALID;
12880 tp->link_config.orig_duplex = DUPLEX_INVALID;
12881 tp->link_config.orig_autoneg = AUTONEG_INVALID;
12884 static int __devinit tg3_phy_probe(struct tg3 *tp)
12886 u32 hw_phy_id_1, hw_phy_id_2;
12887 u32 hw_phy_id, hw_phy_id_masked;
12890 /* flow control autonegotiation is default behavior */
12891 tg3_flag_set(tp, PAUSE_AUTONEG);
12892 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
12894 if (tg3_flag(tp, USE_PHYLIB))
12895 return tg3_phy_init(tp);
12897 /* Reading the PHY ID register can conflict with ASF
12898 * firmware access to the PHY hardware.
12901 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) {
12902 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
12904 /* Now read the physical PHY_ID from the chip and verify
12905 * that it is sane. If it doesn't look good, we fall back
12906 * to either the hard-coded table based PHY_ID and failing
12907 * that the value found in the eeprom area.
12909 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12910 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12912 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
12913 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12914 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
12916 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
12919 if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
12920 tp->phy_id = hw_phy_id;
12921 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
12922 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12924 tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
12926 if (tp->phy_id != TG3_PHY_ID_INVALID) {
12927 /* Do nothing, phy ID already set up in
12928 * tg3_get_eeprom_hw_cfg().
12931 struct subsys_tbl_ent *p;
12933 /* No eeprom signature? Try the hardcoded
12934 * subsys device table.
12936 p = tg3_lookup_by_subsys(tp);
12940 tp->phy_id = p->phy_id;
12942 tp->phy_id == TG3_PHY_ID_BCM8002)
12943 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12947 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
12948 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
12949 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720 ||
12950 (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 &&
12951 tp->pci_chip_rev_id != CHIPREV_ID_5717_A0) ||
12952 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12953 tp->pci_chip_rev_id != CHIPREV_ID_57765_A0)))
12954 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
12956 tg3_phy_init_link_config(tp);
12958 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
12959 !tg3_flag(tp, ENABLE_APE) &&
12960 !tg3_flag(tp, ENABLE_ASF)) {
12963 tg3_readphy(tp, MII_BMSR, &bmsr);
12964 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12965 (bmsr & BMSR_LSTATUS))
12966 goto skip_phy_reset;
12968 err = tg3_phy_reset(tp);
12972 tg3_phy_set_wirespeed(tp);
12974 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12975 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12976 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12977 if (!tg3_copper_is_advertising_all(tp, mask)) {
12978 tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
12979 tp->link_config.flowctrl);
12981 tg3_writephy(tp, MII_BMCR,
12982 BMCR_ANENABLE | BMCR_ANRESTART);
12987 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
12988 err = tg3_init_5401phy_dsp(tp);
12992 err = tg3_init_5401phy_dsp(tp);
12998 static void __devinit tg3_read_vpd(struct tg3 *tp)
13001 unsigned int block_end, rosize, len;
13004 vpd_data = (u8 *)tg3_vpd_readblock(tp);
13008 i = pci_vpd_find_tag(vpd_data, 0, TG3_NVM_VPD_LEN,
13009 PCI_VPD_LRDT_RO_DATA);
13011 goto out_not_found;
13013 rosize = pci_vpd_lrdt_size(&vpd_data[i]);
13014 block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
13015 i += PCI_VPD_LRDT_TAG_SIZE;
13017 if (block_end > TG3_NVM_VPD_LEN)
13018 goto out_not_found;
13020 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
13021 PCI_VPD_RO_KEYWORD_MFR_ID);
13023 len = pci_vpd_info_field_size(&vpd_data[j]);
13025 j += PCI_VPD_INFO_FLD_HDR_SIZE;
13026 if (j + len > block_end || len != 4 ||
13027 memcmp(&vpd_data[j], "1028", 4))
13030 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
13031 PCI_VPD_RO_KEYWORD_VENDOR0);
13035 len = pci_vpd_info_field_size(&vpd_data[j]);
13037 j += PCI_VPD_INFO_FLD_HDR_SIZE;
13038 if (j + len > block_end)
13041 memcpy(tp->fw_ver, &vpd_data[j], len);
13042 strncat(tp->fw_ver, " bc ", TG3_NVM_VPD_LEN - len - 1);
13046 i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
13047 PCI_VPD_RO_KEYWORD_PARTNO);
13049 goto out_not_found;
13051 len = pci_vpd_info_field_size(&vpd_data[i]);
13053 i += PCI_VPD_INFO_FLD_HDR_SIZE;
13054 if (len > TG3_BPN_SIZE ||
13055 (len + i) > TG3_NVM_VPD_LEN)
13056 goto out_not_found;
13058 memcpy(tp->board_part_number, &vpd_data[i], len);
13062 if (tp->board_part_number[0])
13066 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13067 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717)
13068 strcpy(tp->board_part_number, "BCM5717");
13069 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718)
13070 strcpy(tp->board_part_number, "BCM5718");
13073 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
13074 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
13075 strcpy(tp->board_part_number, "BCM57780");
13076 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
13077 strcpy(tp->board_part_number, "BCM57760");
13078 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
13079 strcpy(tp->board_part_number, "BCM57790");
13080 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
13081 strcpy(tp->board_part_number, "BCM57788");
13084 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
13085 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
13086 strcpy(tp->board_part_number, "BCM57761");
13087 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
13088 strcpy(tp->board_part_number, "BCM57765");
13089 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
13090 strcpy(tp->board_part_number, "BCM57781");
13091 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
13092 strcpy(tp->board_part_number, "BCM57785");
13093 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
13094 strcpy(tp->board_part_number, "BCM57791");
13095 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
13096 strcpy(tp->board_part_number, "BCM57795");
13099 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13100 strcpy(tp->board_part_number, "BCM95906");
13103 strcpy(tp->board_part_number, "none");
13107 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
13111 if (tg3_nvram_read(tp, offset, &val) ||
13112 (val & 0xfc000000) != 0x0c000000 ||
13113 tg3_nvram_read(tp, offset + 4, &val) ||
13120 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
13122 u32 val, offset, start, ver_offset;
13124 bool newver = false;
13126 if (tg3_nvram_read(tp, 0xc, &offset) ||
13127 tg3_nvram_read(tp, 0x4, &start))
13130 offset = tg3_nvram_logical_addr(tp, offset);
13132 if (tg3_nvram_read(tp, offset, &val))
13135 if ((val & 0xfc000000) == 0x0c000000) {
13136 if (tg3_nvram_read(tp, offset + 4, &val))
13143 dst_off = strlen(tp->fw_ver);
13146 if (TG3_VER_SIZE - dst_off < 16 ||
13147 tg3_nvram_read(tp, offset + 8, &ver_offset))
13150 offset = offset + ver_offset - start;
13151 for (i = 0; i < 16; i += 4) {
13153 if (tg3_nvram_read_be32(tp, offset + i, &v))
13156 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
13161 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
13164 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
13165 TG3_NVM_BCVER_MAJSFT;
13166 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
13167 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
13168 "v%d.%02d", major, minor);
13172 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
13174 u32 val, major, minor;
13176 /* Use native endian representation */
13177 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
13180 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
13181 TG3_NVM_HWSB_CFG1_MAJSFT;
13182 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
13183 TG3_NVM_HWSB_CFG1_MINSFT;
13185 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
13188 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
13190 u32 offset, major, minor, build;
13192 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
13194 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
13197 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
13198 case TG3_EEPROM_SB_REVISION_0:
13199 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
13201 case TG3_EEPROM_SB_REVISION_2:
13202 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
13204 case TG3_EEPROM_SB_REVISION_3:
13205 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
13207 case TG3_EEPROM_SB_REVISION_4:
13208 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
13210 case TG3_EEPROM_SB_REVISION_5:
13211 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
13213 case TG3_EEPROM_SB_REVISION_6:
13214 offset = TG3_EEPROM_SB_F1R6_EDH_OFF;
13220 if (tg3_nvram_read(tp, offset, &val))
13223 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
13224 TG3_EEPROM_SB_EDH_BLD_SHFT;
13225 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
13226 TG3_EEPROM_SB_EDH_MAJ_SHFT;
13227 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
13229 if (minor > 99 || build > 26)
13232 offset = strlen(tp->fw_ver);
13233 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
13234 " v%d.%02d", major, minor);
13237 offset = strlen(tp->fw_ver);
13238 if (offset < TG3_VER_SIZE - 1)
13239 tp->fw_ver[offset] = 'a' + build - 1;
13243 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
13245 u32 val, offset, start;
13248 for (offset = TG3_NVM_DIR_START;
13249 offset < TG3_NVM_DIR_END;
13250 offset += TG3_NVM_DIRENT_SIZE) {
13251 if (tg3_nvram_read(tp, offset, &val))
13254 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
13258 if (offset == TG3_NVM_DIR_END)
13261 if (!tg3_flag(tp, 5705_PLUS))
13262 start = 0x08000000;
13263 else if (tg3_nvram_read(tp, offset - 4, &start))
13266 if (tg3_nvram_read(tp, offset + 4, &offset) ||
13267 !tg3_fw_img_is_valid(tp, offset) ||
13268 tg3_nvram_read(tp, offset + 8, &val))
13271 offset += val - start;
13273 vlen = strlen(tp->fw_ver);
13275 tp->fw_ver[vlen++] = ',';
13276 tp->fw_ver[vlen++] = ' ';
13278 for (i = 0; i < 4; i++) {
13280 if (tg3_nvram_read_be32(tp, offset, &v))
13283 offset += sizeof(v);
13285 if (vlen > TG3_VER_SIZE - sizeof(v)) {
13286 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
13290 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
13295 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
13301 if (!tg3_flag(tp, ENABLE_APE) || !tg3_flag(tp, ENABLE_ASF))
13304 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
13305 if (apedata != APE_SEG_SIG_MAGIC)
13308 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
13309 if (!(apedata & APE_FW_STATUS_READY))
13312 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
13314 if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI) {
13315 tg3_flag_set(tp, APE_HAS_NCSI);
13321 vlen = strlen(tp->fw_ver);
13323 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
13325 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
13326 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
13327 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
13328 (apedata & APE_FW_VERSION_BLDMSK));
13331 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
13334 bool vpd_vers = false;
13336 if (tp->fw_ver[0] != 0)
13339 if (tg3_flag(tp, NO_NVRAM)) {
13340 strcat(tp->fw_ver, "sb");
13344 if (tg3_nvram_read(tp, 0, &val))
13347 if (val == TG3_EEPROM_MAGIC)
13348 tg3_read_bc_ver(tp);
13349 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
13350 tg3_read_sb_ver(tp, val);
13351 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
13352 tg3_read_hwsb_ver(tp);
13356 if (!tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || vpd_vers)
13359 tg3_read_mgmtfw_ver(tp);
13362 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
13365 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
13367 static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
13369 if (tg3_flag(tp, LRG_PROD_RING_CAP))
13370 return TG3_RX_RET_MAX_SIZE_5717;
13371 else if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))
13372 return TG3_RX_RET_MAX_SIZE_5700;
13374 return TG3_RX_RET_MAX_SIZE_5705;
13377 static DEFINE_PCI_DEVICE_TABLE(tg3_write_reorder_chipsets) = {
13378 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) },
13379 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) },
13380 { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) },
13384 static int __devinit tg3_get_invariants(struct tg3 *tp)
13387 u32 pci_state_reg, grc_misc_cfg;
13392 /* Force memory write invalidate off. If we leave it on,
13393 * then on 5700_BX chips we have to enable a workaround.
13394 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
13395 * to match the cacheline size. The Broadcom driver have this
13396 * workaround but turns MWI off all the times so never uses
13397 * it. This seems to suggest that the workaround is insufficient.
13399 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13400 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
13401 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13403 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
13404 * has the register indirect write enable bit set before
13405 * we try to access any of the MMIO registers. It is also
13406 * critical that the PCI-X hw workaround situation is decided
13407 * before that as well.
13409 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13412 tp->pci_chip_rev_id = (misc_ctrl_reg >>
13413 MISC_HOST_CTRL_CHIPREV_SHIFT);
13414 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
13415 u32 prod_id_asic_rev;
13417 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
13418 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
13419 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
13420 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720)
13421 pci_read_config_dword(tp->pdev,
13422 TG3PCI_GEN2_PRODID_ASICREV,
13423 &prod_id_asic_rev);
13424 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
13425 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
13426 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
13427 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
13428 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13429 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
13430 pci_read_config_dword(tp->pdev,
13431 TG3PCI_GEN15_PRODID_ASICREV,
13432 &prod_id_asic_rev);
13434 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
13435 &prod_id_asic_rev);
13437 tp->pci_chip_rev_id = prod_id_asic_rev;
13440 /* Wrong chip ID in 5752 A0. This code can be removed later
13441 * as A0 is not in production.
13443 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
13444 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
13446 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
13447 * we need to disable memory and use config. cycles
13448 * only to access all registers. The 5702/03 chips
13449 * can mistakenly decode the special cycles from the
13450 * ICH chipsets as memory write cycles, causing corruption
13451 * of register and memory space. Only certain ICH bridges
13452 * will drive special cycles with non-zero data during the
13453 * address phase which can fall within the 5703's address
13454 * range. This is not an ICH bug as the PCI spec allows
13455 * non-zero address during special cycles. However, only
13456 * these ICH bridges are known to drive non-zero addresses
13457 * during special cycles.
13459 * Since special cycles do not cross PCI bridges, we only
13460 * enable this workaround if the 5703 is on the secondary
13461 * bus of these ICH bridges.
13463 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
13464 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
13465 static struct tg3_dev_id {
13469 } ich_chipsets[] = {
13470 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
13472 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
13474 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
13476 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
13480 struct tg3_dev_id *pci_id = &ich_chipsets[0];
13481 struct pci_dev *bridge = NULL;
13483 while (pci_id->vendor != 0) {
13484 bridge = pci_get_device(pci_id->vendor, pci_id->device,
13490 if (pci_id->rev != PCI_ANY_ID) {
13491 if (bridge->revision > pci_id->rev)
13494 if (bridge->subordinate &&
13495 (bridge->subordinate->number ==
13496 tp->pdev->bus->number)) {
13497 tg3_flag_set(tp, ICH_WORKAROUND);
13498 pci_dev_put(bridge);
13504 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
13505 static struct tg3_dev_id {
13508 } bridge_chipsets[] = {
13509 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
13510 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
13513 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
13514 struct pci_dev *bridge = NULL;
13516 while (pci_id->vendor != 0) {
13517 bridge = pci_get_device(pci_id->vendor,
13524 if (bridge->subordinate &&
13525 (bridge->subordinate->number <=
13526 tp->pdev->bus->number) &&
13527 (bridge->subordinate->subordinate >=
13528 tp->pdev->bus->number)) {
13529 tg3_flag_set(tp, 5701_DMA_BUG);
13530 pci_dev_put(bridge);
13536 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
13537 * DMA addresses > 40-bit. This bridge may have other additional
13538 * 57xx devices behind it in some 4-port NIC designs for example.
13539 * Any tg3 device found behind the bridge will also need the 40-bit
13542 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
13543 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13544 tg3_flag_set(tp, 5780_CLASS);
13545 tg3_flag_set(tp, 40BIT_DMA_BUG);
13546 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
13548 struct pci_dev *bridge = NULL;
13551 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
13552 PCI_DEVICE_ID_SERVERWORKS_EPB,
13554 if (bridge && bridge->subordinate &&
13555 (bridge->subordinate->number <=
13556 tp->pdev->bus->number) &&
13557 (bridge->subordinate->subordinate >=
13558 tp->pdev->bus->number)) {
13559 tg3_flag_set(tp, 40BIT_DMA_BUG);
13560 pci_dev_put(bridge);
13566 /* Initialize misc host control in PCI block. */
13567 tp->misc_host_ctrl |= (misc_ctrl_reg &
13568 MISC_HOST_CTRL_CHIPREV);
13569 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13570 tp->misc_host_ctrl);
13572 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
13573 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
13574 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13575 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
13576 tp->pdev_peer = tg3_find_peer(tp);
13578 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13579 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13580 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
13581 tg3_flag_set(tp, 5717_PLUS);
13583 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 ||
13584 tg3_flag(tp, 5717_PLUS))
13585 tg3_flag_set(tp, 57765_PLUS);
13587 /* Intentionally exclude ASIC_REV_5906 */
13588 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13589 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13590 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13591 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13592 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13593 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13594 tg3_flag(tp, 57765_PLUS))
13595 tg3_flag_set(tp, 5755_PLUS);
13597 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13598 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13599 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13600 tg3_flag(tp, 5755_PLUS) ||
13601 tg3_flag(tp, 5780_CLASS))
13602 tg3_flag_set(tp, 5750_PLUS);
13604 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
13605 tg3_flag(tp, 5750_PLUS))
13606 tg3_flag_set(tp, 5705_PLUS);
13608 /* Determine TSO capabilities */
13609 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
13610 ; /* Do nothing. HW bug. */
13611 else if (tg3_flag(tp, 57765_PLUS))
13612 tg3_flag_set(tp, HW_TSO_3);
13613 else if (tg3_flag(tp, 5755_PLUS) ||
13614 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13615 tg3_flag_set(tp, HW_TSO_2);
13616 else if (tg3_flag(tp, 5750_PLUS)) {
13617 tg3_flag_set(tp, HW_TSO_1);
13618 tg3_flag_set(tp, TSO_BUG);
13619 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
13620 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
13621 tg3_flag_clear(tp, TSO_BUG);
13622 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13623 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13624 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
13625 tg3_flag_set(tp, TSO_BUG);
13626 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13627 tp->fw_needed = FIRMWARE_TG3TSO5;
13629 tp->fw_needed = FIRMWARE_TG3TSO;
13632 /* Selectively allow TSO based on operating conditions */
13633 if (tg3_flag(tp, HW_TSO_1) ||
13634 tg3_flag(tp, HW_TSO_2) ||
13635 tg3_flag(tp, HW_TSO_3) ||
13636 (tp->fw_needed && !tg3_flag(tp, ENABLE_ASF)))
13637 tg3_flag_set(tp, TSO_CAPABLE);
13639 tg3_flag_clear(tp, TSO_CAPABLE);
13640 tg3_flag_clear(tp, TSO_BUG);
13641 tp->fw_needed = NULL;
13644 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
13645 tp->fw_needed = FIRMWARE_TG3;
13649 if (tg3_flag(tp, 5750_PLUS)) {
13650 tg3_flag_set(tp, SUPPORT_MSI);
13651 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
13652 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
13653 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
13654 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
13655 tp->pdev_peer == tp->pdev))
13656 tg3_flag_clear(tp, SUPPORT_MSI);
13658 if (tg3_flag(tp, 5755_PLUS) ||
13659 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13660 tg3_flag_set(tp, 1SHOT_MSI);
13663 if (tg3_flag(tp, 57765_PLUS)) {
13664 tg3_flag_set(tp, SUPPORT_MSIX);
13665 tp->irq_max = TG3_IRQ_MAX_VECS;
13669 /* All chips can get confused if TX buffers
13670 * straddle the 4GB address boundary.
13672 tg3_flag_set(tp, 4G_DMA_BNDRY_BUG);
13674 if (tg3_flag(tp, 5755_PLUS))
13675 tg3_flag_set(tp, SHORT_DMA_BUG);
13677 tg3_flag_set(tp, 40BIT_DMA_LIMIT_BUG);
13679 if (tg3_flag(tp, 5717_PLUS))
13680 tg3_flag_set(tp, LRG_PROD_RING_CAP);
13682 if (tg3_flag(tp, 57765_PLUS) &&
13683 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
13684 tg3_flag_set(tp, USE_JUMBO_BDFLAG);
13686 if (!tg3_flag(tp, 5705_PLUS) ||
13687 tg3_flag(tp, 5780_CLASS) ||
13688 tg3_flag(tp, USE_JUMBO_BDFLAG))
13689 tg3_flag_set(tp, JUMBO_CAPABLE);
13691 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13694 tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
13695 if (tp->pcie_cap != 0) {
13698 tg3_flag_set(tp, PCI_EXPRESS);
13700 tp->pcie_readrq = 4096;
13701 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13702 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
13703 tp->pcie_readrq = 2048;
13705 pcie_set_readrq(tp->pdev, tp->pcie_readrq);
13707 pci_read_config_word(tp->pdev,
13708 tp->pcie_cap + PCI_EXP_LNKCTL,
13710 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
13711 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
13713 tg3_flag_clear(tp, HW_TSO_2);
13714 tg3_flag_clear(tp, TSO_CAPABLE);
13716 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13717 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13718 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
13719 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
13720 tg3_flag_set(tp, CLKREQ_BUG);
13721 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
13722 tg3_flag_set(tp, L1PLLPD_EN);
13724 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
13725 tg3_flag_set(tp, PCI_EXPRESS);
13726 } else if (!tg3_flag(tp, 5705_PLUS) ||
13727 tg3_flag(tp, 5780_CLASS)) {
13728 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
13729 if (!tp->pcix_cap) {
13730 dev_err(&tp->pdev->dev,
13731 "Cannot find PCI-X capability, aborting\n");
13735 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
13736 tg3_flag_set(tp, PCIX_MODE);
13739 /* If we have an AMD 762 or VIA K8T800 chipset, write
13740 * reordering to the mailbox registers done by the host
13741 * controller can cause major troubles. We read back from
13742 * every mailbox register write to force the writes to be
13743 * posted to the chip in order.
13745 if (pci_dev_present(tg3_write_reorder_chipsets) &&
13746 !tg3_flag(tp, PCI_EXPRESS))
13747 tg3_flag_set(tp, MBOX_WRITE_REORDER);
13749 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
13750 &tp->pci_cacheline_sz);
13751 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13752 &tp->pci_lat_timer);
13753 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13754 tp->pci_lat_timer < 64) {
13755 tp->pci_lat_timer = 64;
13756 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13757 tp->pci_lat_timer);
13760 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
13761 /* 5700 BX chips need to have their TX producer index
13762 * mailboxes written twice to workaround a bug.
13764 tg3_flag_set(tp, TXD_MBOX_HWBUG);
13766 /* If we are in PCI-X mode, enable register write workaround.
13768 * The workaround is to use indirect register accesses
13769 * for all chip writes not to mailbox registers.
13771 if (tg3_flag(tp, PCIX_MODE)) {
13774 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
13776 /* The chip can have it's power management PCI config
13777 * space registers clobbered due to this bug.
13778 * So explicitly force the chip into D0 here.
13780 pci_read_config_dword(tp->pdev,
13781 tp->pm_cap + PCI_PM_CTRL,
13783 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
13784 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
13785 pci_write_config_dword(tp->pdev,
13786 tp->pm_cap + PCI_PM_CTRL,
13789 /* Also, force SERR#/PERR# in PCI command. */
13790 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13791 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
13792 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13796 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
13797 tg3_flag_set(tp, PCI_HIGH_SPEED);
13798 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
13799 tg3_flag_set(tp, PCI_32BIT);
13801 /* Chip-specific fixup from Broadcom driver */
13802 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
13803 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
13804 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
13805 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
13808 /* Default fast path register access methods */
13809 tp->read32 = tg3_read32;
13810 tp->write32 = tg3_write32;
13811 tp->read32_mbox = tg3_read32;
13812 tp->write32_mbox = tg3_write32;
13813 tp->write32_tx_mbox = tg3_write32;
13814 tp->write32_rx_mbox = tg3_write32;
13816 /* Various workaround register access methods */
13817 if (tg3_flag(tp, PCIX_TARGET_HWBUG))
13818 tp->write32 = tg3_write_indirect_reg32;
13819 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13820 (tg3_flag(tp, PCI_EXPRESS) &&
13821 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
13823 * Back to back register writes can cause problems on these
13824 * chips, the workaround is to read back all reg writes
13825 * except those to mailbox regs.
13827 * See tg3_write_indirect_reg32().
13829 tp->write32 = tg3_write_flush_reg32;
13832 if (tg3_flag(tp, TXD_MBOX_HWBUG) || tg3_flag(tp, MBOX_WRITE_REORDER)) {
13833 tp->write32_tx_mbox = tg3_write32_tx_mbox;
13834 if (tg3_flag(tp, MBOX_WRITE_REORDER))
13835 tp->write32_rx_mbox = tg3_write_flush_reg32;
13838 if (tg3_flag(tp, ICH_WORKAROUND)) {
13839 tp->read32 = tg3_read_indirect_reg32;
13840 tp->write32 = tg3_write_indirect_reg32;
13841 tp->read32_mbox = tg3_read_indirect_mbox;
13842 tp->write32_mbox = tg3_write_indirect_mbox;
13843 tp->write32_tx_mbox = tg3_write_indirect_mbox;
13844 tp->write32_rx_mbox = tg3_write_indirect_mbox;
13849 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13850 pci_cmd &= ~PCI_COMMAND_MEMORY;
13851 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13853 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13854 tp->read32_mbox = tg3_read32_mbox_5906;
13855 tp->write32_mbox = tg3_write32_mbox_5906;
13856 tp->write32_tx_mbox = tg3_write32_mbox_5906;
13857 tp->write32_rx_mbox = tg3_write32_mbox_5906;
13860 if (tp->write32 == tg3_write_indirect_reg32 ||
13861 (tg3_flag(tp, PCIX_MODE) &&
13862 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13863 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
13864 tg3_flag_set(tp, SRAM_USE_CONFIG);
13866 /* Get eeprom hw config before calling tg3_set_power_state().
13867 * In particular, the TG3_FLAG_IS_NIC flag must be
13868 * determined before calling tg3_set_power_state() so that
13869 * we know whether or not to switch out of Vaux power.
13870 * When the flag is set, it means that GPIO1 is used for eeprom
13871 * write protect and also implies that it is a LOM where GPIOs
13872 * are not used to switch power.
13874 tg3_get_eeprom_hw_cfg(tp);
13876 if (tg3_flag(tp, ENABLE_APE)) {
13877 /* Allow reads and writes to the
13878 * APE register and memory space.
13880 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
13881 PCISTATE_ALLOW_APE_SHMEM_WR |
13882 PCISTATE_ALLOW_APE_PSPACE_WR;
13883 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
13887 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13888 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13889 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13890 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13891 tg3_flag(tp, 57765_PLUS))
13892 tg3_flag_set(tp, CPMU_PRESENT);
13894 /* Set up tp->grc_local_ctrl before calling tg3_power_up().
13895 * GPIO1 driven high will bring 5700's external PHY out of reset.
13896 * It is also used as eeprom write protect on LOMs.
13898 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
13899 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13900 tg3_flag(tp, EEPROM_WRITE_PROT))
13901 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
13902 GRC_LCLCTRL_GPIO_OUTPUT1);
13903 /* Unused GPIO3 must be driven as output on 5752 because there
13904 * are no pull-up resistors on unused GPIO pins.
13906 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13907 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
13909 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13910 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13911 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13912 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13914 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
13915 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
13916 /* Turn off the debug UART. */
13917 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13918 if (tg3_flag(tp, IS_NIC))
13919 /* Keep VMain power. */
13920 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13921 GRC_LCLCTRL_GPIO_OUTPUT0;
13924 /* Force the chip into D0. */
13925 err = tg3_power_up(tp);
13927 dev_err(&tp->pdev->dev, "Transition to D0 failed\n");
13931 /* Derive initial jumbo mode from MTU assigned in
13932 * ether_setup() via the alloc_etherdev() call
13934 if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS))
13935 tg3_flag_set(tp, JUMBO_RING_ENABLE);
13937 /* Determine WakeOnLan speed to use. */
13938 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13939 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13940 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13941 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13942 tg3_flag_clear(tp, WOL_SPEED_100MB);
13944 tg3_flag_set(tp, WOL_SPEED_100MB);
13947 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13948 tp->phy_flags |= TG3_PHYFLG_IS_FET;
13950 /* A few boards don't want Ethernet@WireSpeed phy feature */
13951 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13952 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13953 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
13954 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
13955 (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
13956 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
13957 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
13959 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
13960 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
13961 tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
13962 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
13963 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
13965 if (tg3_flag(tp, 5705_PLUS) &&
13966 !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
13967 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
13968 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
13969 !tg3_flag(tp, 57765_PLUS)) {
13970 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13971 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13972 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13973 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
13974 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13975 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13976 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
13977 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13978 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
13980 tp->phy_flags |= TG3_PHYFLG_BER_BUG;
13983 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13984 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13985 tp->phy_otp = tg3_read_otp_phycfg(tp);
13986 if (tp->phy_otp == 0)
13987 tp->phy_otp = TG3_OTP_DEFAULT;
13990 if (tg3_flag(tp, CPMU_PRESENT))
13991 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13993 tp->mi_mode = MAC_MI_MODE_BASE;
13995 tp->coalesce_mode = 0;
13996 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13997 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13998 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
14000 /* Set these bits to enable statistics workaround. */
14001 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
14002 tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 ||
14003 tp->pci_chip_rev_id == CHIPREV_ID_5720_A0) {
14004 tp->coalesce_mode |= HOSTCC_MODE_ATTN;
14005 tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN;
14008 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14009 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
14010 tg3_flag_set(tp, USE_PHYLIB);
14012 err = tg3_mdio_init(tp);
14016 /* Initialize data/descriptor byte/word swapping. */
14017 val = tr32(GRC_MODE);
14018 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
14019 val &= (GRC_MODE_BYTE_SWAP_B2HRX_DATA |
14020 GRC_MODE_WORD_SWAP_B2HRX_DATA |
14021 GRC_MODE_B2HRX_ENABLE |
14022 GRC_MODE_HTX2B_ENABLE |
14023 GRC_MODE_HOST_STACKUP);
14025 val &= GRC_MODE_HOST_STACKUP;
14027 tw32(GRC_MODE, val | tp->grc_mode);
14029 tg3_switch_clocks(tp);
14031 /* Clear this out for sanity. */
14032 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
14034 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
14036 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
14037 !tg3_flag(tp, PCIX_TARGET_HWBUG)) {
14038 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
14040 if (chiprevid == CHIPREV_ID_5701_A0 ||
14041 chiprevid == CHIPREV_ID_5701_B0 ||
14042 chiprevid == CHIPREV_ID_5701_B2 ||
14043 chiprevid == CHIPREV_ID_5701_B5) {
14044 void __iomem *sram_base;
14046 /* Write some dummy words into the SRAM status block
14047 * area, see if it reads back correctly. If the return
14048 * value is bad, force enable the PCIX workaround.
14050 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
14052 writel(0x00000000, sram_base);
14053 writel(0x00000000, sram_base + 4);
14054 writel(0xffffffff, sram_base + 4);
14055 if (readl(sram_base) != 0x00000000)
14056 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
14061 tg3_nvram_init(tp);
14063 grc_misc_cfg = tr32(GRC_MISC_CFG);
14064 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
14066 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
14067 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
14068 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
14069 tg3_flag_set(tp, IS_5788);
14071 if (!tg3_flag(tp, IS_5788) &&
14072 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
14073 tg3_flag_set(tp, TAGGED_STATUS);
14074 if (tg3_flag(tp, TAGGED_STATUS)) {
14075 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
14076 HOSTCC_MODE_CLRTICK_TXBD);
14078 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
14079 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
14080 tp->misc_host_ctrl);
14083 /* Preserve the APE MAC_MODE bits */
14084 if (tg3_flag(tp, ENABLE_APE))
14085 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
14087 tp->mac_mode = TG3_DEF_MAC_MODE;
14089 /* these are limited to 10/100 only */
14090 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
14091 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
14092 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
14093 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
14094 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
14095 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
14096 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
14097 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
14098 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
14099 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
14100 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
14101 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
14102 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
14103 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
14104 (tp->phy_flags & TG3_PHYFLG_IS_FET))
14105 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
14107 err = tg3_phy_probe(tp);
14109 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
14110 /* ... but do not return immediately ... */
14115 tg3_read_fw_ver(tp);
14117 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
14118 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
14120 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
14121 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
14123 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
14126 /* 5700 {AX,BX} chips have a broken status block link
14127 * change bit implementation, so we must use the
14128 * status register in those cases.
14130 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
14131 tg3_flag_set(tp, USE_LINKCHG_REG);
14133 tg3_flag_clear(tp, USE_LINKCHG_REG);
14135 /* The led_ctrl is set during tg3_phy_probe, here we might
14136 * have to force the link status polling mechanism based
14137 * upon subsystem IDs.
14139 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
14140 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
14141 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
14142 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
14143 tg3_flag_set(tp, USE_LINKCHG_REG);
14146 /* For all SERDES we poll the MAC status register. */
14147 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
14148 tg3_flag_set(tp, POLL_SERDES);
14150 tg3_flag_clear(tp, POLL_SERDES);
14152 tp->rx_offset = NET_IP_ALIGN;
14153 tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
14154 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
14155 tg3_flag(tp, PCIX_MODE)) {
14157 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
14158 tp->rx_copy_thresh = ~(u16)0;
14162 tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1;
14163 tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1;
14164 tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1;
14166 tp->rx_std_max_post = tp->rx_std_ring_mask + 1;
14168 /* Increment the rx prod index on the rx std ring by at most
14169 * 8 for these chips to workaround hw errata.
14171 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
14172 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
14173 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
14174 tp->rx_std_max_post = 8;
14176 if (tg3_flag(tp, ASPM_WORKAROUND))
14177 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
14178 PCIE_PWR_MGMT_L1_THRESH_MSK;
14183 #ifdef CONFIG_SPARC
14184 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
14186 struct net_device *dev = tp->dev;
14187 struct pci_dev *pdev = tp->pdev;
14188 struct device_node *dp = pci_device_to_OF_node(pdev);
14189 const unsigned char *addr;
14192 addr = of_get_property(dp, "local-mac-address", &len);
14193 if (addr && len == 6) {
14194 memcpy(dev->dev_addr, addr, 6);
14195 memcpy(dev->perm_addr, dev->dev_addr, 6);
14201 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
14203 struct net_device *dev = tp->dev;
14205 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
14206 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
14211 static int __devinit tg3_get_device_address(struct tg3 *tp)
14213 struct net_device *dev = tp->dev;
14214 u32 hi, lo, mac_offset;
14217 #ifdef CONFIG_SPARC
14218 if (!tg3_get_macaddr_sparc(tp))
14223 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
14224 tg3_flag(tp, 5780_CLASS)) {
14225 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
14227 if (tg3_nvram_lock(tp))
14228 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
14230 tg3_nvram_unlock(tp);
14231 } else if (tg3_flag(tp, 5717_PLUS)) {
14232 if (PCI_FUNC(tp->pdev->devfn) & 1)
14234 if (PCI_FUNC(tp->pdev->devfn) > 1)
14235 mac_offset += 0x18c;
14236 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
14239 /* First try to get it from MAC address mailbox. */
14240 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
14241 if ((hi >> 16) == 0x484b) {
14242 dev->dev_addr[0] = (hi >> 8) & 0xff;
14243 dev->dev_addr[1] = (hi >> 0) & 0xff;
14245 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
14246 dev->dev_addr[2] = (lo >> 24) & 0xff;
14247 dev->dev_addr[3] = (lo >> 16) & 0xff;
14248 dev->dev_addr[4] = (lo >> 8) & 0xff;
14249 dev->dev_addr[5] = (lo >> 0) & 0xff;
14251 /* Some old bootcode may report a 0 MAC address in SRAM */
14252 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
14255 /* Next, try NVRAM. */
14256 if (!tg3_flag(tp, NO_NVRAM) &&
14257 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
14258 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
14259 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
14260 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
14262 /* Finally just fetch it out of the MAC control regs. */
14264 hi = tr32(MAC_ADDR_0_HIGH);
14265 lo = tr32(MAC_ADDR_0_LOW);
14267 dev->dev_addr[5] = lo & 0xff;
14268 dev->dev_addr[4] = (lo >> 8) & 0xff;
14269 dev->dev_addr[3] = (lo >> 16) & 0xff;
14270 dev->dev_addr[2] = (lo >> 24) & 0xff;
14271 dev->dev_addr[1] = hi & 0xff;
14272 dev->dev_addr[0] = (hi >> 8) & 0xff;
14276 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
14277 #ifdef CONFIG_SPARC
14278 if (!tg3_get_default_macaddr_sparc(tp))
14283 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
14287 #define BOUNDARY_SINGLE_CACHELINE 1
14288 #define BOUNDARY_MULTI_CACHELINE 2
14290 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
14292 int cacheline_size;
14296 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
14298 cacheline_size = 1024;
14300 cacheline_size = (int) byte * 4;
14302 /* On 5703 and later chips, the boundary bits have no
14305 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14306 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
14307 !tg3_flag(tp, PCI_EXPRESS))
14310 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
14311 goal = BOUNDARY_MULTI_CACHELINE;
14313 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
14314 goal = BOUNDARY_SINGLE_CACHELINE;
14320 if (tg3_flag(tp, 57765_PLUS)) {
14321 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
14328 /* PCI controllers on most RISC systems tend to disconnect
14329 * when a device tries to burst across a cache-line boundary.
14330 * Therefore, letting tg3 do so just wastes PCI bandwidth.
14332 * Unfortunately, for PCI-E there are only limited
14333 * write-side controls for this, and thus for reads
14334 * we will still get the disconnects. We'll also waste
14335 * these PCI cycles for both read and write for chips
14336 * other than 5700 and 5701 which do not implement the
14339 if (tg3_flag(tp, PCIX_MODE) && !tg3_flag(tp, PCI_EXPRESS)) {
14340 switch (cacheline_size) {
14345 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14346 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
14347 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
14349 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
14350 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
14355 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
14356 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
14360 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
14361 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
14364 } else if (tg3_flag(tp, PCI_EXPRESS)) {
14365 switch (cacheline_size) {
14369 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14370 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
14371 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
14377 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
14378 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
14382 switch (cacheline_size) {
14384 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14385 val |= (DMA_RWCTRL_READ_BNDRY_16 |
14386 DMA_RWCTRL_WRITE_BNDRY_16);
14391 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14392 val |= (DMA_RWCTRL_READ_BNDRY_32 |
14393 DMA_RWCTRL_WRITE_BNDRY_32);
14398 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14399 val |= (DMA_RWCTRL_READ_BNDRY_64 |
14400 DMA_RWCTRL_WRITE_BNDRY_64);
14405 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14406 val |= (DMA_RWCTRL_READ_BNDRY_128 |
14407 DMA_RWCTRL_WRITE_BNDRY_128);
14412 val |= (DMA_RWCTRL_READ_BNDRY_256 |
14413 DMA_RWCTRL_WRITE_BNDRY_256);
14416 val |= (DMA_RWCTRL_READ_BNDRY_512 |
14417 DMA_RWCTRL_WRITE_BNDRY_512);
14421 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
14422 DMA_RWCTRL_WRITE_BNDRY_1024);
14431 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
14433 struct tg3_internal_buffer_desc test_desc;
14434 u32 sram_dma_descs;
14437 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
14439 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
14440 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
14441 tw32(RDMAC_STATUS, 0);
14442 tw32(WDMAC_STATUS, 0);
14444 tw32(BUFMGR_MODE, 0);
14445 tw32(FTQ_RESET, 0);
14447 test_desc.addr_hi = ((u64) buf_dma) >> 32;
14448 test_desc.addr_lo = buf_dma & 0xffffffff;
14449 test_desc.nic_mbuf = 0x00002100;
14450 test_desc.len = size;
14453 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
14454 * the *second* time the tg3 driver was getting loaded after an
14457 * Broadcom tells me:
14458 * ...the DMA engine is connected to the GRC block and a DMA
14459 * reset may affect the GRC block in some unpredictable way...
14460 * The behavior of resets to individual blocks has not been tested.
14462 * Broadcom noted the GRC reset will also reset all sub-components.
14465 test_desc.cqid_sqid = (13 << 8) | 2;
14467 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
14470 test_desc.cqid_sqid = (16 << 8) | 7;
14472 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
14475 test_desc.flags = 0x00000005;
14477 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
14480 val = *(((u32 *)&test_desc) + i);
14481 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
14482 sram_dma_descs + (i * sizeof(u32)));
14483 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
14485 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
14488 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
14490 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
14493 for (i = 0; i < 40; i++) {
14497 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
14499 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
14500 if ((val & 0xffff) == sram_dma_descs) {
14511 #define TEST_BUFFER_SIZE 0x2000
14513 static DEFINE_PCI_DEVICE_TABLE(tg3_dma_wait_state_chipsets) = {
14514 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
14518 static int __devinit tg3_test_dma(struct tg3 *tp)
14520 dma_addr_t buf_dma;
14521 u32 *buf, saved_dma_rwctrl;
14524 buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE,
14525 &buf_dma, GFP_KERNEL);
14531 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
14532 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
14534 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
14536 if (tg3_flag(tp, 57765_PLUS))
14539 if (tg3_flag(tp, PCI_EXPRESS)) {
14540 /* DMA read watermark not used on PCIE */
14541 tp->dma_rwctrl |= 0x00180000;
14542 } else if (!tg3_flag(tp, PCIX_MODE)) {
14543 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
14544 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
14545 tp->dma_rwctrl |= 0x003f0000;
14547 tp->dma_rwctrl |= 0x003f000f;
14549 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
14550 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
14551 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
14552 u32 read_water = 0x7;
14554 /* If the 5704 is behind the EPB bridge, we can
14555 * do the less restrictive ONE_DMA workaround for
14556 * better performance.
14558 if (tg3_flag(tp, 40BIT_DMA_BUG) &&
14559 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14560 tp->dma_rwctrl |= 0x8000;
14561 else if (ccval == 0x6 || ccval == 0x7)
14562 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
14564 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
14566 /* Set bit 23 to enable PCIX hw bug fix */
14568 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
14569 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
14571 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
14572 /* 5780 always in PCIX mode */
14573 tp->dma_rwctrl |= 0x00144000;
14574 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
14575 /* 5714 always in PCIX mode */
14576 tp->dma_rwctrl |= 0x00148000;
14578 tp->dma_rwctrl |= 0x001b000f;
14582 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
14583 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14584 tp->dma_rwctrl &= 0xfffffff0;
14586 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14587 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
14588 /* Remove this if it causes problems for some boards. */
14589 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
14591 /* On 5700/5701 chips, we need to set this bit.
14592 * Otherwise the chip will issue cacheline transactions
14593 * to streamable DMA memory with not all the byte
14594 * enables turned on. This is an error on several
14595 * RISC PCI controllers, in particular sparc64.
14597 * On 5703/5704 chips, this bit has been reassigned
14598 * a different meaning. In particular, it is used
14599 * on those chips to enable a PCI-X workaround.
14601 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
14604 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14607 /* Unneeded, already done by tg3_get_invariants. */
14608 tg3_switch_clocks(tp);
14611 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14612 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
14615 /* It is best to perform DMA test with maximum write burst size
14616 * to expose the 5700/5701 write DMA bug.
14618 saved_dma_rwctrl = tp->dma_rwctrl;
14619 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14620 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14625 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
14628 /* Send the buffer to the chip. */
14629 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
14631 dev_err(&tp->pdev->dev,
14632 "%s: Buffer write failed. err = %d\n",
14638 /* validate data reached card RAM correctly. */
14639 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14641 tg3_read_mem(tp, 0x2100 + (i*4), &val);
14642 if (le32_to_cpu(val) != p[i]) {
14643 dev_err(&tp->pdev->dev,
14644 "%s: Buffer corrupted on device! "
14645 "(%d != %d)\n", __func__, val, i);
14646 /* ret = -ENODEV here? */
14651 /* Now read it back. */
14652 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
14654 dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
14655 "err = %d\n", __func__, ret);
14660 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14664 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14665 DMA_RWCTRL_WRITE_BNDRY_16) {
14666 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14667 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14668 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14671 dev_err(&tp->pdev->dev,
14672 "%s: Buffer corrupted on read back! "
14673 "(%d != %d)\n", __func__, p[i], i);
14679 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
14685 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14686 DMA_RWCTRL_WRITE_BNDRY_16) {
14687 /* DMA test passed without adjusting DMA boundary,
14688 * now look for chipsets that are known to expose the
14689 * DMA bug without failing the test.
14691 if (pci_dev_present(tg3_dma_wait_state_chipsets)) {
14692 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14693 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14695 /* Safe to use the calculated DMA boundary. */
14696 tp->dma_rwctrl = saved_dma_rwctrl;
14699 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14703 dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma);
14708 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
14710 if (tg3_flag(tp, 57765_PLUS)) {
14711 tp->bufmgr_config.mbuf_read_dma_low_water =
14712 DEFAULT_MB_RDMA_LOW_WATER_5705;
14713 tp->bufmgr_config.mbuf_mac_rx_low_water =
14714 DEFAULT_MB_MACRX_LOW_WATER_57765;
14715 tp->bufmgr_config.mbuf_high_water =
14716 DEFAULT_MB_HIGH_WATER_57765;
14718 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14719 DEFAULT_MB_RDMA_LOW_WATER_5705;
14720 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14721 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
14722 tp->bufmgr_config.mbuf_high_water_jumbo =
14723 DEFAULT_MB_HIGH_WATER_JUMBO_57765;
14724 } else if (tg3_flag(tp, 5705_PLUS)) {
14725 tp->bufmgr_config.mbuf_read_dma_low_water =
14726 DEFAULT_MB_RDMA_LOW_WATER_5705;
14727 tp->bufmgr_config.mbuf_mac_rx_low_water =
14728 DEFAULT_MB_MACRX_LOW_WATER_5705;
14729 tp->bufmgr_config.mbuf_high_water =
14730 DEFAULT_MB_HIGH_WATER_5705;
14731 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14732 tp->bufmgr_config.mbuf_mac_rx_low_water =
14733 DEFAULT_MB_MACRX_LOW_WATER_5906;
14734 tp->bufmgr_config.mbuf_high_water =
14735 DEFAULT_MB_HIGH_WATER_5906;
14738 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14739 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
14740 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14741 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
14742 tp->bufmgr_config.mbuf_high_water_jumbo =
14743 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
14745 tp->bufmgr_config.mbuf_read_dma_low_water =
14746 DEFAULT_MB_RDMA_LOW_WATER;
14747 tp->bufmgr_config.mbuf_mac_rx_low_water =
14748 DEFAULT_MB_MACRX_LOW_WATER;
14749 tp->bufmgr_config.mbuf_high_water =
14750 DEFAULT_MB_HIGH_WATER;
14752 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14753 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
14754 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14755 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
14756 tp->bufmgr_config.mbuf_high_water_jumbo =
14757 DEFAULT_MB_HIGH_WATER_JUMBO;
14760 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
14761 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
14764 static char * __devinit tg3_phy_string(struct tg3 *tp)
14766 switch (tp->phy_id & TG3_PHY_ID_MASK) {
14767 case TG3_PHY_ID_BCM5400: return "5400";
14768 case TG3_PHY_ID_BCM5401: return "5401";
14769 case TG3_PHY_ID_BCM5411: return "5411";
14770 case TG3_PHY_ID_BCM5701: return "5701";
14771 case TG3_PHY_ID_BCM5703: return "5703";
14772 case TG3_PHY_ID_BCM5704: return "5704";
14773 case TG3_PHY_ID_BCM5705: return "5705";
14774 case TG3_PHY_ID_BCM5750: return "5750";
14775 case TG3_PHY_ID_BCM5752: return "5752";
14776 case TG3_PHY_ID_BCM5714: return "5714";
14777 case TG3_PHY_ID_BCM5780: return "5780";
14778 case TG3_PHY_ID_BCM5755: return "5755";
14779 case TG3_PHY_ID_BCM5787: return "5787";
14780 case TG3_PHY_ID_BCM5784: return "5784";
14781 case TG3_PHY_ID_BCM5756: return "5722/5756";
14782 case TG3_PHY_ID_BCM5906: return "5906";
14783 case TG3_PHY_ID_BCM5761: return "5761";
14784 case TG3_PHY_ID_BCM5718C: return "5718C";
14785 case TG3_PHY_ID_BCM5718S: return "5718S";
14786 case TG3_PHY_ID_BCM57765: return "57765";
14787 case TG3_PHY_ID_BCM5719C: return "5719C";
14788 case TG3_PHY_ID_BCM5720C: return "5720C";
14789 case TG3_PHY_ID_BCM8002: return "8002/serdes";
14790 case 0: return "serdes";
14791 default: return "unknown";
14795 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
14797 if (tg3_flag(tp, PCI_EXPRESS)) {
14798 strcpy(str, "PCI Express");
14800 } else if (tg3_flag(tp, PCIX_MODE)) {
14801 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
14803 strcpy(str, "PCIX:");
14805 if ((clock_ctrl == 7) ||
14806 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
14807 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
14808 strcat(str, "133MHz");
14809 else if (clock_ctrl == 0)
14810 strcat(str, "33MHz");
14811 else if (clock_ctrl == 2)
14812 strcat(str, "50MHz");
14813 else if (clock_ctrl == 4)
14814 strcat(str, "66MHz");
14815 else if (clock_ctrl == 6)
14816 strcat(str, "100MHz");
14818 strcpy(str, "PCI:");
14819 if (tg3_flag(tp, PCI_HIGH_SPEED))
14820 strcat(str, "66MHz");
14822 strcat(str, "33MHz");
14824 if (tg3_flag(tp, PCI_32BIT))
14825 strcat(str, ":32-bit");
14827 strcat(str, ":64-bit");
14831 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
14833 struct pci_dev *peer;
14834 unsigned int func, devnr = tp->pdev->devfn & ~7;
14836 for (func = 0; func < 8; func++) {
14837 peer = pci_get_slot(tp->pdev->bus, devnr | func);
14838 if (peer && peer != tp->pdev)
14842 /* 5704 can be configured in single-port mode, set peer to
14843 * tp->pdev in that case.
14851 * We don't need to keep the refcount elevated; there's no way
14852 * to remove one half of this device without removing the other
14859 static void __devinit tg3_init_coal(struct tg3 *tp)
14861 struct ethtool_coalesce *ec = &tp->coal;
14863 memset(ec, 0, sizeof(*ec));
14864 ec->cmd = ETHTOOL_GCOALESCE;
14865 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
14866 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
14867 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
14868 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
14869 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
14870 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
14871 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
14872 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
14873 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
14875 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
14876 HOSTCC_MODE_CLRTICK_TXBD)) {
14877 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
14878 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
14879 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
14880 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
14883 if (tg3_flag(tp, 5705_PLUS)) {
14884 ec->rx_coalesce_usecs_irq = 0;
14885 ec->tx_coalesce_usecs_irq = 0;
14886 ec->stats_block_coalesce_usecs = 0;
14890 static const struct net_device_ops tg3_netdev_ops = {
14891 .ndo_open = tg3_open,
14892 .ndo_stop = tg3_close,
14893 .ndo_start_xmit = tg3_start_xmit,
14894 .ndo_get_stats64 = tg3_get_stats64,
14895 .ndo_validate_addr = eth_validate_addr,
14896 .ndo_set_multicast_list = tg3_set_rx_mode,
14897 .ndo_set_mac_address = tg3_set_mac_addr,
14898 .ndo_do_ioctl = tg3_ioctl,
14899 .ndo_tx_timeout = tg3_tx_timeout,
14900 .ndo_change_mtu = tg3_change_mtu,
14901 .ndo_fix_features = tg3_fix_features,
14902 .ndo_set_features = tg3_set_features,
14903 #ifdef CONFIG_NET_POLL_CONTROLLER
14904 .ndo_poll_controller = tg3_poll_controller,
14908 static int __devinit tg3_init_one(struct pci_dev *pdev,
14909 const struct pci_device_id *ent)
14911 struct net_device *dev;
14913 int i, err, pm_cap;
14914 u32 sndmbx, rcvmbx, intmbx;
14916 u64 dma_mask, persist_dma_mask;
14919 printk_once(KERN_INFO "%s\n", version);
14921 err = pci_enable_device(pdev);
14923 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
14927 err = pci_request_regions(pdev, DRV_MODULE_NAME);
14929 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
14930 goto err_out_disable_pdev;
14933 pci_set_master(pdev);
14935 /* Find power-management capability. */
14936 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14938 dev_err(&pdev->dev,
14939 "Cannot find Power Management capability, aborting\n");
14941 goto err_out_free_res;
14944 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
14946 dev_err(&pdev->dev, "Etherdev alloc failed, aborting\n");
14948 goto err_out_free_res;
14951 SET_NETDEV_DEV(dev, &pdev->dev);
14953 tp = netdev_priv(dev);
14956 tp->pm_cap = pm_cap;
14957 tp->rx_mode = TG3_DEF_RX_MODE;
14958 tp->tx_mode = TG3_DEF_TX_MODE;
14961 tp->msg_enable = tg3_debug;
14963 tp->msg_enable = TG3_DEF_MSG_ENABLE;
14965 /* The word/byte swap controls here control register access byte
14966 * swapping. DMA data byte swapping is controlled in the GRC_MODE
14969 tp->misc_host_ctrl =
14970 MISC_HOST_CTRL_MASK_PCI_INT |
14971 MISC_HOST_CTRL_WORD_SWAP |
14972 MISC_HOST_CTRL_INDIR_ACCESS |
14973 MISC_HOST_CTRL_PCISTATE_RW;
14975 /* The NONFRM (non-frame) byte/word swap controls take effect
14976 * on descriptor entries, anything which isn't packet data.
14978 * The StrongARM chips on the board (one for tx, one for rx)
14979 * are running in big-endian mode.
14981 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14982 GRC_MODE_WSWAP_NONFRM_DATA);
14983 #ifdef __BIG_ENDIAN
14984 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14986 spin_lock_init(&tp->lock);
14987 spin_lock_init(&tp->indirect_lock);
14988 INIT_WORK(&tp->reset_task, tg3_reset_task);
14990 tp->regs = pci_ioremap_bar(pdev, BAR_0);
14992 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
14994 goto err_out_free_dev;
14997 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14998 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
15000 dev->ethtool_ops = &tg3_ethtool_ops;
15001 dev->watchdog_timeo = TG3_TX_TIMEOUT;
15002 dev->netdev_ops = &tg3_netdev_ops;
15003 dev->irq = pdev->irq;
15005 err = tg3_get_invariants(tp);
15007 dev_err(&pdev->dev,
15008 "Problem fetching invariants of chip, aborting\n");
15009 goto err_out_iounmap;
15012 /* The EPB bridge inside 5714, 5715, and 5780 and any
15013 * device behind the EPB cannot support DMA addresses > 40-bit.
15014 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
15015 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
15016 * do DMA address check in tg3_start_xmit().
15018 if (tg3_flag(tp, IS_5788))
15019 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
15020 else if (tg3_flag(tp, 40BIT_DMA_BUG)) {
15021 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
15022 #ifdef CONFIG_HIGHMEM
15023 dma_mask = DMA_BIT_MASK(64);
15026 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
15028 /* Configure DMA attributes. */
15029 if (dma_mask > DMA_BIT_MASK(32)) {
15030 err = pci_set_dma_mask(pdev, dma_mask);
15032 features |= NETIF_F_HIGHDMA;
15033 err = pci_set_consistent_dma_mask(pdev,
15036 dev_err(&pdev->dev, "Unable to obtain 64 bit "
15037 "DMA for consistent allocations\n");
15038 goto err_out_iounmap;
15042 if (err || dma_mask == DMA_BIT_MASK(32)) {
15043 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
15045 dev_err(&pdev->dev,
15046 "No usable DMA configuration, aborting\n");
15047 goto err_out_iounmap;
15051 tg3_init_bufmgr_config(tp);
15053 features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
15055 /* 5700 B0 chips do not support checksumming correctly due
15056 * to hardware bugs.
15058 if (tp->pci_chip_rev_id != CHIPREV_ID_5700_B0) {
15059 features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
15061 if (tg3_flag(tp, 5755_PLUS))
15062 features |= NETIF_F_IPV6_CSUM;
15065 /* TSO is on by default on chips that support hardware TSO.
15066 * Firmware TSO on older chips gives lower performance, so it
15067 * is off by default, but can be enabled using ethtool.
15069 if ((tg3_flag(tp, HW_TSO_1) ||
15070 tg3_flag(tp, HW_TSO_2) ||
15071 tg3_flag(tp, HW_TSO_3)) &&
15072 (features & NETIF_F_IP_CSUM))
15073 features |= NETIF_F_TSO;
15074 if (tg3_flag(tp, HW_TSO_2) || tg3_flag(tp, HW_TSO_3)) {
15075 if (features & NETIF_F_IPV6_CSUM)
15076 features |= NETIF_F_TSO6;
15077 if (tg3_flag(tp, HW_TSO_3) ||
15078 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
15079 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
15080 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
15081 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
15082 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
15083 features |= NETIF_F_TSO_ECN;
15086 dev->features |= features;
15087 dev->vlan_features |= features;
15090 * Add loopback capability only for a subset of devices that support
15091 * MAC-LOOPBACK. Eventually this need to be enhanced to allow INT-PHY
15092 * loopback for the remaining devices.
15094 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5780 &&
15095 !tg3_flag(tp, CPMU_PRESENT))
15096 /* Add the loopback capability */
15097 features |= NETIF_F_LOOPBACK;
15099 dev->hw_features |= features;
15101 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
15102 !tg3_flag(tp, TSO_CAPABLE) &&
15103 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
15104 tg3_flag_set(tp, MAX_RXPEND_64);
15105 tp->rx_pending = 63;
15108 err = tg3_get_device_address(tp);
15110 dev_err(&pdev->dev,
15111 "Could not obtain valid ethernet address, aborting\n");
15112 goto err_out_iounmap;
15115 if (tg3_flag(tp, ENABLE_APE)) {
15116 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
15117 if (!tp->aperegs) {
15118 dev_err(&pdev->dev,
15119 "Cannot map APE registers, aborting\n");
15121 goto err_out_iounmap;
15124 tg3_ape_lock_init(tp);
15126 if (tg3_flag(tp, ENABLE_ASF))
15127 tg3_read_dash_ver(tp);
15131 * Reset chip in case UNDI or EFI driver did not shutdown
15132 * DMA self test will enable WDMAC and we'll see (spurious)
15133 * pending DMA on the PCI bus at that point.
15135 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
15136 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
15137 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
15138 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
15141 err = tg3_test_dma(tp);
15143 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
15144 goto err_out_apeunmap;
15147 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
15148 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
15149 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
15150 for (i = 0; i < tp->irq_max; i++) {
15151 struct tg3_napi *tnapi = &tp->napi[i];
15154 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
15156 tnapi->int_mbox = intmbx;
15162 tnapi->consmbox = rcvmbx;
15163 tnapi->prodmbox = sndmbx;
15166 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
15168 tnapi->coal_now = HOSTCC_MODE_NOW;
15170 if (!tg3_flag(tp, SUPPORT_MSIX))
15174 * If we support MSIX, we'll be using RSS. If we're using
15175 * RSS, the first vector only handles link interrupts and the
15176 * remaining vectors handle rx and tx interrupts. Reuse the
15177 * mailbox values for the next iteration. The values we setup
15178 * above are still useful for the single vectored mode.
15193 pci_set_drvdata(pdev, dev);
15195 err = register_netdev(dev);
15197 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
15198 goto err_out_apeunmap;
15201 netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
15202 tp->board_part_number,
15203 tp->pci_chip_rev_id,
15204 tg3_bus_string(tp, str),
15207 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
15208 struct phy_device *phydev;
15209 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
15211 "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
15212 phydev->drv->name, dev_name(&phydev->dev));
15216 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
15217 ethtype = "10/100Base-TX";
15218 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
15219 ethtype = "1000Base-SX";
15221 ethtype = "10/100/1000Base-T";
15223 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
15224 "(WireSpeed[%d], EEE[%d])\n",
15225 tg3_phy_string(tp), ethtype,
15226 (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0,
15227 (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0);
15230 netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
15231 (dev->features & NETIF_F_RXCSUM) != 0,
15232 tg3_flag(tp, USE_LINKCHG_REG) != 0,
15233 (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
15234 tg3_flag(tp, ENABLE_ASF) != 0,
15235 tg3_flag(tp, TSO_CAPABLE) != 0);
15236 netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
15238 pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
15239 ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
15241 pci_save_state(pdev);
15247 iounmap(tp->aperegs);
15248 tp->aperegs = NULL;
15261 pci_release_regions(pdev);
15263 err_out_disable_pdev:
15264 pci_disable_device(pdev);
15265 pci_set_drvdata(pdev, NULL);
15269 static void __devexit tg3_remove_one(struct pci_dev *pdev)
15271 struct net_device *dev = pci_get_drvdata(pdev);
15274 struct tg3 *tp = netdev_priv(dev);
15277 release_firmware(tp->fw);
15279 cancel_work_sync(&tp->reset_task);
15281 if (!tg3_flag(tp, USE_PHYLIB)) {
15286 unregister_netdev(dev);
15288 iounmap(tp->aperegs);
15289 tp->aperegs = NULL;
15296 pci_release_regions(pdev);
15297 pci_disable_device(pdev);
15298 pci_set_drvdata(pdev, NULL);
15302 #ifdef CONFIG_PM_SLEEP
15303 static int tg3_suspend(struct device *device)
15305 struct pci_dev *pdev = to_pci_dev(device);
15306 struct net_device *dev = pci_get_drvdata(pdev);
15307 struct tg3 *tp = netdev_priv(dev);
15310 if (!netif_running(dev))
15313 flush_work_sync(&tp->reset_task);
15315 tg3_netif_stop(tp);
15317 del_timer_sync(&tp->timer);
15319 tg3_full_lock(tp, 1);
15320 tg3_disable_ints(tp);
15321 tg3_full_unlock(tp);
15323 netif_device_detach(dev);
15325 tg3_full_lock(tp, 0);
15326 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
15327 tg3_flag_clear(tp, INIT_COMPLETE);
15328 tg3_full_unlock(tp);
15330 err = tg3_power_down_prepare(tp);
15334 tg3_full_lock(tp, 0);
15336 tg3_flag_set(tp, INIT_COMPLETE);
15337 err2 = tg3_restart_hw(tp, 1);
15341 tp->timer.expires = jiffies + tp->timer_offset;
15342 add_timer(&tp->timer);
15344 netif_device_attach(dev);
15345 tg3_netif_start(tp);
15348 tg3_full_unlock(tp);
15357 static int tg3_resume(struct device *device)
15359 struct pci_dev *pdev = to_pci_dev(device);
15360 struct net_device *dev = pci_get_drvdata(pdev);
15361 struct tg3 *tp = netdev_priv(dev);
15364 if (!netif_running(dev))
15367 netif_device_attach(dev);
15369 tg3_full_lock(tp, 0);
15371 tg3_flag_set(tp, INIT_COMPLETE);
15372 err = tg3_restart_hw(tp, 1);
15376 tp->timer.expires = jiffies + tp->timer_offset;
15377 add_timer(&tp->timer);
15379 tg3_netif_start(tp);
15382 tg3_full_unlock(tp);
15390 static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume);
15391 #define TG3_PM_OPS (&tg3_pm_ops)
15395 #define TG3_PM_OPS NULL
15397 #endif /* CONFIG_PM_SLEEP */
15400 * tg3_io_error_detected - called when PCI error is detected
15401 * @pdev: Pointer to PCI device
15402 * @state: The current pci connection state
15404 * This function is called after a PCI bus error affecting
15405 * this device has been detected.
15407 static pci_ers_result_t tg3_io_error_detected(struct pci_dev *pdev,
15408 pci_channel_state_t state)
15410 struct net_device *netdev = pci_get_drvdata(pdev);
15411 struct tg3 *tp = netdev_priv(netdev);
15412 pci_ers_result_t err = PCI_ERS_RESULT_NEED_RESET;
15414 netdev_info(netdev, "PCI I/O error detected\n");
15418 if (!netif_running(netdev))
15423 tg3_netif_stop(tp);
15425 del_timer_sync(&tp->timer);
15426 tg3_flag_clear(tp, RESTART_TIMER);
15428 /* Want to make sure that the reset task doesn't run */
15429 cancel_work_sync(&tp->reset_task);
15430 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
15431 tg3_flag_clear(tp, RESTART_TIMER);
15433 netif_device_detach(netdev);
15435 /* Clean up software state, even if MMIO is blocked */
15436 tg3_full_lock(tp, 0);
15437 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
15438 tg3_full_unlock(tp);
15441 if (state == pci_channel_io_perm_failure)
15442 err = PCI_ERS_RESULT_DISCONNECT;
15444 pci_disable_device(pdev);
15452 * tg3_io_slot_reset - called after the pci bus has been reset.
15453 * @pdev: Pointer to PCI device
15455 * Restart the card from scratch, as if from a cold-boot.
15456 * At this point, the card has exprienced a hard reset,
15457 * followed by fixups by BIOS, and has its config space
15458 * set up identically to what it was at cold boot.
15460 static pci_ers_result_t tg3_io_slot_reset(struct pci_dev *pdev)
15462 struct net_device *netdev = pci_get_drvdata(pdev);
15463 struct tg3 *tp = netdev_priv(netdev);
15464 pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
15469 if (pci_enable_device(pdev)) {
15470 netdev_err(netdev, "Cannot re-enable PCI device after reset.\n");
15474 pci_set_master(pdev);
15475 pci_restore_state(pdev);
15476 pci_save_state(pdev);
15478 if (!netif_running(netdev)) {
15479 rc = PCI_ERS_RESULT_RECOVERED;
15483 err = tg3_power_up(tp);
15485 netdev_err(netdev, "Failed to restore register access.\n");
15489 rc = PCI_ERS_RESULT_RECOVERED;
15498 * tg3_io_resume - called when traffic can start flowing again.
15499 * @pdev: Pointer to PCI device
15501 * This callback is called when the error recovery driver tells
15502 * us that its OK to resume normal operation.
15504 static void tg3_io_resume(struct pci_dev *pdev)
15506 struct net_device *netdev = pci_get_drvdata(pdev);
15507 struct tg3 *tp = netdev_priv(netdev);
15512 if (!netif_running(netdev))
15515 tg3_full_lock(tp, 0);
15516 tg3_flag_set(tp, INIT_COMPLETE);
15517 err = tg3_restart_hw(tp, 1);
15518 tg3_full_unlock(tp);
15520 netdev_err(netdev, "Cannot restart hardware after reset.\n");
15524 netif_device_attach(netdev);
15526 tp->timer.expires = jiffies + tp->timer_offset;
15527 add_timer(&tp->timer);
15529 tg3_netif_start(tp);
15537 static struct pci_error_handlers tg3_err_handler = {
15538 .error_detected = tg3_io_error_detected,
15539 .slot_reset = tg3_io_slot_reset,
15540 .resume = tg3_io_resume
15543 static struct pci_driver tg3_driver = {
15544 .name = DRV_MODULE_NAME,
15545 .id_table = tg3_pci_tbl,
15546 .probe = tg3_init_one,
15547 .remove = __devexit_p(tg3_remove_one),
15548 .err_handler = &tg3_err_handler,
15549 .driver.pm = TG3_PM_OPS,
15552 static int __init tg3_init(void)
15554 return pci_register_driver(&tg3_driver);
15557 static void __exit tg3_cleanup(void)
15559 pci_unregister_driver(&tg3_driver);
15562 module_init(tg3_init);
15563 module_exit(tg3_cleanup);