2 * Copyright (c) 2009 jokeliu@163.com
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * version 2 as published by the Free Software Foundation.
8 * Author : jokeliujl <jokeliu@163.com>
12 /* sr9700 spec. register table on android platform */
27 #define EPDR 0x0D // 0x0D ~ 0x0E
48 /* Bit definition for registers */
49 // Network Control Reg
50 #define NCR_RST (1 << 0)
51 #define NCR_LBK (3 << 1)
52 #define NCR_FDX (1 << 3)
53 #define NCR_WAKEEN (1 << 6)
55 #define NSR_RXRDY (1 << 0)
56 #define NSR_RXOV (1 << 1)
57 #define NSR_TX1END (1 << 2)
58 #define NSR_TX2END (1 << 3)
59 #define NSR_TXFULL (1 << 4)
60 #define NSR_WAKEST (1 << 5)
61 #define NSR_LINKST (1 << 6)
62 #define NSR_SPEED (1 << 7)
64 #define TCR_CRC_DIS (1 << 1)
65 #define TCR_PAD_DIS (1 << 2)
66 #define TCR_LC_CARE (1 << 3)
67 #define TCR_CRS_CARE (1 << 4)
68 #define TCR_EXCECM (1 << 5)
69 #define TCR_LF_EN (1 << 6)
70 // Tx Status Reg for Packet 1
71 #define TSR1_EC (1 << 2)
72 #define TSR1_COL (1 << 3)
73 #define TSR1_LC (1 << 4)
74 #define TSR1_NC (1 << 5)
75 #define TSR1_LOC (1 << 6)
76 #define TSR1_TLF (1 << 7)
77 // Tx Status Reg for Packet 2
78 #define TSR2_EC (1 << 2)
79 #define TSR2_COL (1 << 3)
80 #define TSR2_LC (1 << 4)
81 #define TSR2_NC (1 << 5)
82 #define TSR2_LOC (1 << 6)
83 #define TSR2_TLF (1 << 7)
85 #define RCR_RXEN (1 << 0)
86 #define RCR_PRMSC (1 << 1)
87 #define RCR_RUNT (1 << 2)
88 #define RCR_ALL (1 << 3)
89 #define RCR_DIS_CRC (1 << 4)
90 #define RCR_DIS_LONG (1 << 5)
92 #define RSR_AE (1 << 2)
93 #define RSR_MF (1 << 6)
94 #define RSR_RF (1 << 7)
95 // Recv Overflow Counter Reg
96 #define ROCR_ROC (0x7F << 0)
97 #define ROCR_RXFU (1 << 7)
98 // Back Pressure Threshold Reg
99 #define BPTR_JPT (0x0F << 0)
100 #define BPTR_BPHW (0x0F << 4)
101 // Flow Control Threshold Reg
102 #define FCTR_LWOT (0x0F << 0)
103 #define FCTR_HWOT (0x0F << 4)
104 // rx/tx Flow Control Reg
105 #define FCR_FLCE (1 << 0)
106 #define FCR_BKPA (1 << 4)
107 #define FCR_TXPEN (1 << 5)
108 #define FCR_TXPF (1 << 6)
109 #define FCR_TXP0 (1 << 7)
110 // EEPROM & PHY Control Reg
111 #define EPCR_ERRE (1 << 0)
112 #define EPCR_ERPRW (1 << 1)
113 #define EPCR_ERPRR (1 << 2)
114 #define EPCR_EPOS (1 << 3)
115 #define EPCR_WEP (1 << 4)
116 // EEPROM & PHY Address Reg
117 #define EPAR_EROA (0x3F << 0)
118 #define EPAR_PHY_ADR (0x03 << 6)
119 // Wakeup Control Reg
120 #define WCR_MAGICST (1 << 0)
121 #define WCR_LINKST (1 << 2)
122 #define WCR_MAGICEN (1 << 3)
123 #define WCR_LINKEN (1 << 5)
125 #define PRR_PHY_RST (1 << 0)
126 // USB Device Address Reg
127 #define USBDA_USBFA (0x7F << 0)
128 // TX packet Counter & USB Status Reg
129 #define TXC_USBS_TXC0 (1 << 0)
130 #define TXC_USBS_TXC1 (1 << 1)
131 #define TXC_USBS_TXC2 (1 << 2)
132 #define TXC_USBS_EP1RDY (1 << 5)
133 #define TXC_USBS_SUSFLAG (1 << 6)
134 #define TXC_USBS_RXFAULT (1 << 7)
136 #define USBC_EP3NAK (1 << 4)
137 #define USBC_EP3ACK (1 << 5)
140 #define QF_RD_REGS 0x00
141 #define QF_WR_REGS 0x01
142 #define QF_WR_REG 0x03
143 #define QF_REQ_RD_REG (USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE)
144 #define QF_REQ_WR_REG (USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE)
146 #define QF_SHARE_TIMEOUT 1000
147 #define QF_EEPROM_LEN 256
148 #define QF_MCAST_SIZE 8
149 #define QF_MCAST_MAX 64
150 #define QF_TX_OVERHEAD 2 // 2bytes header
151 #define QF_RX_OVERHEAD 7 // 3bytes header + 4crc tail
153 /*----------------------------------------------------------------------------------------------*/