2 * FarSync WAN driver for Linux (2.6.x kernel version)
4 * Actually sync driver for X.21, V.35 and V.24 on FarSync T-series cards
6 * Copyright (C) 2001-2004 FarSite Communications Ltd.
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
14 * Author: R.J.Dunlop <bob.dunlop@farsite.co.uk>
15 * Maintainer: Kevin Curtis <kevin.curtis@farsite.co.uk>
18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/version.h>
23 #include <linux/pci.h>
24 #include <linux/sched.h>
25 #include <linux/slab.h>
26 #include <linux/ioport.h>
27 #include <linux/init.h>
29 #include <linux/hdlc.h>
31 #include <asm/uaccess.h>
38 MODULE_AUTHOR("R.J.Dunlop <bob.dunlop@farsite.co.uk>");
39 MODULE_DESCRIPTION("FarSync T-Series WAN driver. FarSite Communications Ltd.");
40 MODULE_LICENSE("GPL");
42 /* Driver configuration and global parameters
43 * ==========================================
46 /* Number of ports (per card) and cards supported
48 #define FST_MAX_PORTS 4
49 #define FST_MAX_CARDS 32
51 /* Default parameters for the link
53 #define FST_TX_QUEUE_LEN 100 /* At 8Mbps a longer queue length is
55 #define FST_TXQ_DEPTH 16 /* This one is for the buffering
56 * of frames on the way down to the card
57 * so that we can keep the card busy
58 * and maximise throughput
60 #define FST_HIGH_WATER_MARK 12 /* Point at which we flow control
62 #define FST_LOW_WATER_MARK 8 /* Point at which we remove flow
63 * control from network layer */
64 #define FST_MAX_MTU 8000 /* Huge but possible */
65 #define FST_DEF_MTU 1500 /* Common sane value */
67 #define FST_TX_TIMEOUT (2*HZ)
70 #define ARPHRD_MYTYPE ARPHRD_RAWHDLC /* Raw frames */
72 #define ARPHRD_MYTYPE ARPHRD_HDLC /* Cisco-HDLC (keepalives etc) */
76 * Modules parameters and associated variables
78 static int fst_txq_low = FST_LOW_WATER_MARK;
79 static int fst_txq_high = FST_HIGH_WATER_MARK;
80 static int fst_max_reads = 7;
81 static int fst_excluded_cards = 0;
82 static int fst_excluded_list[FST_MAX_CARDS];
84 module_param(fst_txq_low, int, 0);
85 module_param(fst_txq_high, int, 0);
86 module_param(fst_max_reads, int, 0);
87 module_param(fst_excluded_cards, int, 0);
88 module_param_array(fst_excluded_list, int, NULL, 0);
90 /* Card shared memory layout
91 * =========================
95 /* This information is derived in part from the FarSite FarSync Smc.h
96 * file. Unfortunately various name clashes and the non-portability of the
97 * bit field declarations in that file have meant that I have chosen to
98 * recreate the information here.
100 * The SMC (Shared Memory Configuration) has a version number that is
101 * incremented every time there is a significant change. This number can
102 * be used to check that we have not got out of step with the firmware
103 * contained in the .CDE files.
105 #define SMC_VERSION 24
107 #define FST_MEMSIZE 0x100000 /* Size of card memory (1Mb) */
109 #define SMC_BASE 0x00002000L /* Base offset of the shared memory window main
110 * configuration structure */
111 #define BFM_BASE 0x00010000L /* Base offset of the shared memory window DMA
114 #define LEN_TX_BUFFER 8192 /* Size of packet buffers */
115 #define LEN_RX_BUFFER 8192
117 #define LEN_SMALL_TX_BUFFER 256 /* Size of obsolete buffs used for DOS diags */
118 #define LEN_SMALL_RX_BUFFER 256
120 #define NUM_TX_BUFFER 2 /* Must be power of 2. Fixed by firmware */
121 #define NUM_RX_BUFFER 8
123 /* Interrupt retry time in milliseconds */
124 #define INT_RETRY_TIME 2
126 /* The Am186CH/CC processors support a SmartDMA mode using circular pools
127 * of buffer descriptors. The structure is almost identical to that used
128 * in the LANCE Ethernet controllers. Details available as PDF from the
129 * AMD web site: http://www.amd.com/products/epd/processors/\
130 * 2.16bitcont/3.am186cxfa/a21914/21914.pdf
132 struct txdesc { /* Transmit descriptor */
133 volatile u16 ladr; /* Low order address of packet. This is a
134 * linear address in the Am186 memory space
136 volatile u8 hadr; /* High order address. Low 4 bits only, high 4
139 volatile u8 bits; /* Status and config */
140 volatile u16 bcnt; /* 2s complement of packet size in low 15 bits.
141 * Transmit terminal count interrupt enable in
144 u16 unused; /* Not used in Tx */
147 struct rxdesc { /* Receive descriptor */
148 volatile u16 ladr; /* Low order address of packet */
149 volatile u8 hadr; /* High order address */
150 volatile u8 bits; /* Status and config */
151 volatile u16 bcnt; /* 2s complement of buffer size in low 15 bits.
152 * Receive terminal count interrupt enable in
155 volatile u16 mcnt; /* Message byte count (15 bits) */
158 /* Convert a length into the 15 bit 2's complement */
159 /* #define cnv_bcnt(len) (( ~(len) + 1 ) & 0x7FFF ) */
160 /* Since we need to set the high bit to enable the completion interrupt this
161 * can be made a lot simpler
163 #define cnv_bcnt(len) (-(len))
165 /* Status and config bits for the above */
166 #define DMA_OWN 0x80 /* SmartDMA owns the descriptor */
167 #define TX_STP 0x02 /* Tx: start of packet */
168 #define TX_ENP 0x01 /* Tx: end of packet */
169 #define RX_ERR 0x40 /* Rx: error (OR of next 4 bits) */
170 #define RX_FRAM 0x20 /* Rx: framing error */
171 #define RX_OFLO 0x10 /* Rx: overflow error */
172 #define RX_CRC 0x08 /* Rx: CRC error */
173 #define RX_HBUF 0x04 /* Rx: buffer error */
174 #define RX_STP 0x02 /* Rx: start of packet */
175 #define RX_ENP 0x01 /* Rx: end of packet */
177 /* Interrupts from the card are caused by various events which are presented
178 * in a circular buffer as several events may be processed on one physical int
180 #define MAX_CIRBUFF 32
183 u8 rdindex; /* read, then increment and wrap */
184 u8 wrindex; /* write, then increment and wrap */
185 u8 evntbuff[MAX_CIRBUFF];
188 /* Interrupt event codes.
189 * Where appropriate the two low order bits indicate the port number
191 #define CTLA_CHG 0x18 /* Control signal changed */
192 #define CTLB_CHG 0x19
193 #define CTLC_CHG 0x1A
194 #define CTLD_CHG 0x1B
196 #define INIT_CPLT 0x20 /* Initialisation complete */
197 #define INIT_FAIL 0x21 /* Initialisation failed */
199 #define ABTA_SENT 0x24 /* Abort sent */
200 #define ABTB_SENT 0x25
201 #define ABTC_SENT 0x26
202 #define ABTD_SENT 0x27
204 #define TXA_UNDF 0x28 /* Transmission underflow */
205 #define TXB_UNDF 0x29
206 #define TXC_UNDF 0x2A
207 #define TXD_UNDF 0x2B
212 #define TE1_ALMA 0x30
214 /* Port physical configuration. See farsync.h for field values */
216 u16 lineInterface; /* Physical interface type */
217 u8 x25op; /* Unused at present */
218 u8 internalClock; /* 1 => internal clock, 0 => external */
219 u8 transparentMode; /* 1 => on, 0 => off */
220 u8 invertClock; /* 0 => normal, 1 => inverted */
221 u8 padBytes[6]; /* Padding */
222 u32 lineSpeed; /* Speed in bps */
225 /* TE1 port physical configuration */
249 u32 receiveBufferDelay;
250 u32 framingErrorCount;
251 u32 codeViolationCount;
256 u8 receiveRemoteAlarm;
257 u8 alarmIndicationSignal;
261 /* Finally sling all the above together into the shared memory structure.
262 * Sorry it's a hodge podge of arrays, structures and unused bits, it's been
263 * evolving under NT for some time so I guess we're stuck with it.
264 * The structure starts at offset SMC_BASE.
265 * See farsync.h for some field values.
268 /* DMA descriptor rings */
269 struct rxdesc rxDescrRing[FST_MAX_PORTS][NUM_RX_BUFFER];
270 struct txdesc txDescrRing[FST_MAX_PORTS][NUM_TX_BUFFER];
272 /* Obsolete small buffers */
273 u8 smallRxBuffer[FST_MAX_PORTS][NUM_RX_BUFFER][LEN_SMALL_RX_BUFFER];
274 u8 smallTxBuffer[FST_MAX_PORTS][NUM_TX_BUFFER][LEN_SMALL_TX_BUFFER];
276 u8 taskStatus; /* 0x00 => initialising, 0x01 => running,
280 u8 interruptHandshake; /* Set to 0x01 by adapter to signal interrupt,
281 * set to 0xEE by host to acknowledge interrupt
284 u16 smcVersion; /* Must match SMC_VERSION */
286 u32 smcFirmwareVersion; /* 0xIIVVRRBB where II = product ID, VV = major
287 * version, RR = revision and BB = build
290 u16 txa_done; /* Obsolete completion flags */
299 u16 mailbox[4]; /* Diagnostics mailbox. Not used */
301 struct cirbuff interruptEvent; /* interrupt causes */
303 u32 v24IpSts[FST_MAX_PORTS]; /* V.24 control input status */
304 u32 v24OpSts[FST_MAX_PORTS]; /* V.24 control output status */
306 struct port_cfg portConfig[FST_MAX_PORTS];
308 u16 clockStatus[FST_MAX_PORTS]; /* lsb: 0=> present, 1=> absent */
310 u16 cableStatus; /* lsb: 0=> present, 1=> absent */
312 u16 txDescrIndex[FST_MAX_PORTS]; /* transmit descriptor ring index */
313 u16 rxDescrIndex[FST_MAX_PORTS]; /* receive descriptor ring index */
315 u16 portMailbox[FST_MAX_PORTS][2]; /* command, modifier */
316 u16 cardMailbox[4]; /* Not used */
318 /* Number of times the card thinks the host has
319 * missed an interrupt by not acknowledging
320 * within 2mS (I guess NT has problems)
322 u32 interruptRetryCount;
324 /* Driver private data used as an ID. We'll not
325 * use this as I'd rather keep such things
326 * in main memory rather than on the PCI bus
328 u32 portHandle[FST_MAX_PORTS];
330 /* Count of Tx underflows for stats */
331 u32 transmitBufferUnderflow[FST_MAX_PORTS];
333 /* Debounced V.24 control input status */
334 u32 v24DebouncedSts[FST_MAX_PORTS];
336 /* Adapter debounce timers. Don't touch */
337 u32 ctsTimer[FST_MAX_PORTS];
338 u32 ctsTimerRun[FST_MAX_PORTS];
339 u32 dcdTimer[FST_MAX_PORTS];
340 u32 dcdTimerRun[FST_MAX_PORTS];
342 u32 numberOfPorts; /* Number of ports detected at startup */
346 u16 cardMode; /* Bit-mask to enable features:
347 * Bit 0: 1 enables LED identify mode
350 u16 portScheduleOffset;
352 struct su_config suConfig; /* TE1 Bits */
353 struct su_status suStatus;
355 u32 endOfSmcSignature; /* endOfSmcSignature MUST be the last member of
356 * the structure and marks the end of shared
357 * memory. Adapter code initializes it as
362 /* endOfSmcSignature value */
363 #define END_SIG 0x12345678
365 /* Mailbox values. (portMailbox) */
366 #define NOP 0 /* No operation */
367 #define ACK 1 /* Positive acknowledgement to PC driver */
368 #define NAK 2 /* Negative acknowledgement to PC driver */
369 #define STARTPORT 3 /* Start an HDLC port */
370 #define STOPPORT 4 /* Stop an HDLC port */
371 #define ABORTTX 5 /* Abort the transmitter for a port */
372 #define SETV24O 6 /* Set V24 outputs */
374 /* PLX Chip Register Offsets */
375 #define CNTRL_9052 0x50 /* Control Register */
376 #define CNTRL_9054 0x6c /* Control Register */
378 #define INTCSR_9052 0x4c /* Interrupt control/status register */
379 #define INTCSR_9054 0x68 /* Interrupt control/status register */
381 /* 9054 DMA Registers */
383 * Note that we will be using DMA Channel 0 for copying rx data
384 * and Channel 1 for copying tx data
386 #define DMAMODE0 0x80
387 #define DMAPADR0 0x84
388 #define DMALADR0 0x88
391 #define DMAMODE1 0x94
392 #define DMAPADR1 0x98
393 #define DMALADR1 0x9c
402 #define DMAMARBR 0xac
404 #define FST_MIN_DMA_LEN 64
405 #define FST_RX_DMA_INT 0x01
406 #define FST_TX_DMA_INT 0x02
407 #define FST_CARD_INT 0x04
409 /* Larger buffers are positioned in memory at offset BFM_BASE */
411 u8 txBuffer[FST_MAX_PORTS][NUM_TX_BUFFER][LEN_TX_BUFFER];
412 u8 rxBuffer[FST_MAX_PORTS][NUM_RX_BUFFER][LEN_RX_BUFFER];
415 /* Calculate offset of a buffer object within the shared memory window */
416 #define BUF_OFFSET(X) (BFM_BASE + offsetof(struct buf_window, X))
420 /* Device driver private information
421 * =================================
423 /* Per port (line or channel) information
425 struct fst_port_info {
426 struct net_device *dev; /* Device struct - must be first */
427 struct fst_card_info *card; /* Card we're associated with */
428 int index; /* Port index on the card */
429 int hwif; /* Line hardware (lineInterface copy) */
430 int run; /* Port is running */
431 int mode; /* Normal or FarSync raw */
432 int rxpos; /* Next Rx buffer to use */
433 int txpos; /* Next Tx buffer to use */
434 int txipos; /* Next Tx buffer to check for free */
435 int start; /* Indication of start/stop to network */
437 * A sixteen entry transmit queue
439 int txqs; /* index to get next buffer to tx */
440 int txqe; /* index to queue next packet */
441 struct sk_buff *txq[FST_TXQ_DEPTH]; /* The queue */
445 /* Per card information
447 struct fst_card_info {
448 char __iomem *mem; /* Card memory mapped to kernel space */
449 char __iomem *ctlmem; /* Control memory for PCI cards */
450 unsigned int phys_mem; /* Physical memory window address */
451 unsigned int phys_ctlmem; /* Physical control memory address */
452 unsigned int irq; /* Interrupt request line number */
453 unsigned int nports; /* Number of serial ports */
454 unsigned int type; /* Type index of card */
455 unsigned int state; /* State of card */
456 spinlock_t card_lock; /* Lock for SMP access */
457 unsigned short pci_conf; /* PCI card config in I/O space */
459 struct fst_port_info ports[FST_MAX_PORTS];
460 struct pci_dev *device; /* Information about the pci device */
461 int card_no; /* Inst of the card on the system */
462 int family; /* TxP or TxU */
463 int dmarx_in_progress;
464 int dmatx_in_progress;
465 unsigned long int_count;
466 unsigned long int_time_ave;
467 void *rx_dma_handle_host;
468 dma_addr_t rx_dma_handle_card;
469 void *tx_dma_handle_host;
470 dma_addr_t tx_dma_handle_card;
471 struct sk_buff *dma_skb_rx;
472 struct fst_port_info *dma_port_rx;
473 struct fst_port_info *dma_port_tx;
480 /* Convert an HDLC device pointer into a port info pointer and similar */
481 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
482 #define port_to_dev(P) ((P)->dev)
486 * Shared memory window access macros
488 * We have a nice memory based structure above, which could be directly
489 * mapped on i386 but might not work on other architectures unless we use
490 * the readb,w,l and writeb,w,l macros. Unfortunately these macros take
491 * physical offsets so we have to convert. The only saving grace is that
492 * this should all collapse back to a simple indirection eventually.
494 #define WIN_OFFSET(X) ((long)&(((struct fst_shared *)SMC_BASE)->X))
496 #define FST_RDB(C,E) readb ((C)->mem + WIN_OFFSET(E))
497 #define FST_RDW(C,E) readw ((C)->mem + WIN_OFFSET(E))
498 #define FST_RDL(C,E) readl ((C)->mem + WIN_OFFSET(E))
500 #define FST_WRB(C,E,B) writeb ((B), (C)->mem + WIN_OFFSET(E))
501 #define FST_WRW(C,E,W) writew ((W), (C)->mem + WIN_OFFSET(E))
502 #define FST_WRL(C,E,L) writel ((L), (C)->mem + WIN_OFFSET(E))
509 static int fst_debug_mask = { FST_DEBUG };
511 /* Most common debug activity is to print something if the corresponding bit
512 * is set in the debug mask. Note: this uses a non-ANSI extension in GCC to
513 * support variable numbers of macro parameters. The inverted if prevents us
514 * eating someone else's else clause.
516 #define dbg(F, fmt, args...) \
518 if (fst_debug_mask & (F)) \
519 printk(KERN_DEBUG pr_fmt(fmt), ##args); \
522 #define dbg(F, fmt, args...) \
525 printk(KERN_DEBUG pr_fmt(fmt), ##args); \
530 * PCI ID lookup table
532 static DEFINE_PCI_DEVICE_TABLE(fst_pci_dev_id) = {
533 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T2P, PCI_ANY_ID,
534 PCI_ANY_ID, 0, 0, FST_TYPE_T2P},
536 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T4P, PCI_ANY_ID,
537 PCI_ANY_ID, 0, 0, FST_TYPE_T4P},
539 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T1U, PCI_ANY_ID,
540 PCI_ANY_ID, 0, 0, FST_TYPE_T1U},
542 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T2U, PCI_ANY_ID,
543 PCI_ANY_ID, 0, 0, FST_TYPE_T2U},
545 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T4U, PCI_ANY_ID,
546 PCI_ANY_ID, 0, 0, FST_TYPE_T4U},
548 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_TE1, PCI_ANY_ID,
549 PCI_ANY_ID, 0, 0, FST_TYPE_TE1},
551 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_TE1C, PCI_ANY_ID,
552 PCI_ANY_ID, 0, 0, FST_TYPE_TE1},
556 MODULE_DEVICE_TABLE(pci, fst_pci_dev_id);
559 * Device Driver Work Queues
561 * So that we don't spend too much time processing events in the
562 * Interrupt Service routine, we will declare a work queue per Card
563 * and make the ISR schedule a task in the queue for later execution.
564 * In the 2.4 Kernel we used to use the immediate queue for BH's
565 * Now that they are gone, tasklets seem to be much better than work
569 static void do_bottom_half_tx(struct fst_card_info *card);
570 static void do_bottom_half_rx(struct fst_card_info *card);
571 static void fst_process_tx_work_q(unsigned long work_q);
572 static void fst_process_int_work_q(unsigned long work_q);
574 static DECLARE_TASKLET(fst_tx_task, fst_process_tx_work_q, 0);
575 static DECLARE_TASKLET(fst_int_task, fst_process_int_work_q, 0);
577 static struct fst_card_info *fst_card_array[FST_MAX_CARDS];
578 static spinlock_t fst_work_q_lock;
579 static u64 fst_work_txq;
580 static u64 fst_work_intq;
583 fst_q_work_item(u64 * queue, int card_index)
589 * Grab the queue exclusively
591 spin_lock_irqsave(&fst_work_q_lock, flags);
594 * Making an entry in the queue is simply a matter of setting
595 * a bit for the card indicating that there is work to do in the
596 * bottom half for the card. Note the limitation of 64 cards.
597 * That ought to be enough
599 mask = 1 << card_index;
601 spin_unlock_irqrestore(&fst_work_q_lock, flags);
605 fst_process_tx_work_q(unsigned long /*void **/work_q)
612 * Grab the queue exclusively
614 dbg(DBG_TX, "fst_process_tx_work_q\n");
615 spin_lock_irqsave(&fst_work_q_lock, flags);
616 work_txq = fst_work_txq;
618 spin_unlock_irqrestore(&fst_work_q_lock, flags);
621 * Call the bottom half for each card with work waiting
623 for (i = 0; i < FST_MAX_CARDS; i++) {
624 if (work_txq & 0x01) {
625 if (fst_card_array[i] != NULL) {
626 dbg(DBG_TX, "Calling tx bh for card %d\n", i);
627 do_bottom_half_tx(fst_card_array[i]);
630 work_txq = work_txq >> 1;
635 fst_process_int_work_q(unsigned long /*void **/work_q)
642 * Grab the queue exclusively
644 dbg(DBG_INTR, "fst_process_int_work_q\n");
645 spin_lock_irqsave(&fst_work_q_lock, flags);
646 work_intq = fst_work_intq;
648 spin_unlock_irqrestore(&fst_work_q_lock, flags);
651 * Call the bottom half for each card with work waiting
653 for (i = 0; i < FST_MAX_CARDS; i++) {
654 if (work_intq & 0x01) {
655 if (fst_card_array[i] != NULL) {
657 "Calling rx & tx bh for card %d\n", i);
658 do_bottom_half_rx(fst_card_array[i]);
659 do_bottom_half_tx(fst_card_array[i]);
662 work_intq = work_intq >> 1;
666 /* Card control functions
667 * ======================
669 /* Place the processor in reset state
671 * Used to be a simple write to card control space but a glitch in the latest
672 * AMD Am186CH processor means that we now have to do it by asserting and de-
673 * asserting the PLX chip PCI Adapter Software Reset. Bit 30 in CNTRL register
674 * at offset 9052_CNTRL. Note the updates for the TXU.
677 fst_cpureset(struct fst_card_info *card)
679 unsigned char interrupt_line_register;
680 unsigned long j = jiffies + 1;
683 if (card->family == FST_FAMILY_TXU) {
684 if (pci_read_config_byte
685 (card->device, PCI_INTERRUPT_LINE, &interrupt_line_register)) {
687 "Error in reading interrupt line register\n");
690 * Assert PLX software reset and Am186 hardware reset
691 * and then deassert the PLX software reset but 186 still in reset
693 outw(0x440f, card->pci_conf + CNTRL_9054 + 2);
694 outw(0x040f, card->pci_conf + CNTRL_9054 + 2);
696 * We are delaying here to allow the 9054 to reset itself
701 outw(0x240f, card->pci_conf + CNTRL_9054 + 2);
703 * We are delaying here to allow the 9054 to reload its eeprom
708 outw(0x040f, card->pci_conf + CNTRL_9054 + 2);
710 if (pci_write_config_byte
711 (card->device, PCI_INTERRUPT_LINE, interrupt_line_register)) {
713 "Error in writing interrupt line register\n");
717 regval = inl(card->pci_conf + CNTRL_9052);
719 outl(regval | 0x40000000, card->pci_conf + CNTRL_9052);
720 outl(regval & ~0x40000000, card->pci_conf + CNTRL_9052);
724 /* Release the processor from reset
727 fst_cpurelease(struct fst_card_info *card)
729 if (card->family == FST_FAMILY_TXU) {
731 * Force posted writes to complete
733 (void) readb(card->mem);
736 * Release LRESET DO = 1
737 * Then release Local Hold, DO = 1
739 outw(0x040e, card->pci_conf + CNTRL_9054 + 2);
740 outw(0x040f, card->pci_conf + CNTRL_9054 + 2);
742 (void) readb(card->ctlmem);
746 /* Clear the cards interrupt flag
749 fst_clear_intr(struct fst_card_info *card)
751 if (card->family == FST_FAMILY_TXU) {
752 (void) readb(card->ctlmem);
754 /* Poke the appropriate PLX chip register (same as enabling interrupts)
756 outw(0x0543, card->pci_conf + INTCSR_9052);
760 /* Enable card interrupts
763 fst_enable_intr(struct fst_card_info *card)
765 if (card->family == FST_FAMILY_TXU) {
766 outl(0x0f0c0900, card->pci_conf + INTCSR_9054);
768 outw(0x0543, card->pci_conf + INTCSR_9052);
772 /* Disable card interrupts
775 fst_disable_intr(struct fst_card_info *card)
777 if (card->family == FST_FAMILY_TXU) {
778 outl(0x00000000, card->pci_conf + INTCSR_9054);
780 outw(0x0000, card->pci_conf + INTCSR_9052);
784 /* Process the result of trying to pass a received frame up the stack
787 fst_process_rx_status(int rx_status, char *name)
799 dbg(DBG_ASS, "%s: Received packet dropped\n", name);
805 /* Initilaise DMA for PLX 9054
808 fst_init_dma(struct fst_card_info *card)
811 * This is only required for the PLX 9054
813 if (card->family == FST_FAMILY_TXU) {
814 pci_set_master(card->device);
815 outl(0x00020441, card->pci_conf + DMAMODE0);
816 outl(0x00020441, card->pci_conf + DMAMODE1);
817 outl(0x0, card->pci_conf + DMATHR);
821 /* Tx dma complete interrupt
824 fst_tx_dma_complete(struct fst_card_info *card, struct fst_port_info *port,
827 struct net_device *dev = port_to_dev(port);
830 * Everything is now set, just tell the card to go
832 dbg(DBG_TX, "fst_tx_dma_complete\n");
833 FST_WRB(card, txDescrRing[port->index][txpos].bits,
834 DMA_OWN | TX_STP | TX_ENP);
835 dev->stats.tx_packets++;
836 dev->stats.tx_bytes += len;
837 dev->trans_start = jiffies;
841 * Mark it for our own raw sockets interface
843 static __be16 farsync_type_trans(struct sk_buff *skb, struct net_device *dev)
846 skb_reset_mac_header(skb);
847 skb->pkt_type = PACKET_HOST;
848 return htons(ETH_P_CUST);
851 /* Rx dma complete interrupt
854 fst_rx_dma_complete(struct fst_card_info *card, struct fst_port_info *port,
855 int len, struct sk_buff *skb, int rxp)
857 struct net_device *dev = port_to_dev(port);
861 dbg(DBG_TX, "fst_rx_dma_complete\n");
863 memcpy(skb_put(skb, len), card->rx_dma_handle_host, len);
865 /* Reset buffer descriptor */
866 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
869 dev->stats.rx_packets++;
870 dev->stats.rx_bytes += len;
873 dbg(DBG_RX, "Pushing the frame up the stack\n");
874 if (port->mode == FST_RAW)
875 skb->protocol = farsync_type_trans(skb, dev);
877 skb->protocol = hdlc_type_trans(skb, dev);
878 rx_status = netif_rx(skb);
879 fst_process_rx_status(rx_status, port_to_dev(port)->name);
880 if (rx_status == NET_RX_DROP)
881 dev->stats.rx_dropped++;
885 * Receive a frame through the DMA
888 fst_rx_dma(struct fst_card_info *card, unsigned char *skb,
889 unsigned char *mem, int len)
892 * This routine will setup the DMA and start it
895 dbg(DBG_RX, "In fst_rx_dma %p %p %d\n", skb, mem, len);
896 if (card->dmarx_in_progress) {
897 dbg(DBG_ASS, "In fst_rx_dma while dma in progress\n");
900 outl((unsigned long) skb, card->pci_conf + DMAPADR0); /* Copy to here */
901 outl((unsigned long) mem, card->pci_conf + DMALADR0); /* from here */
902 outl(len, card->pci_conf + DMASIZ0); /* for this length */
903 outl(0x00000000c, card->pci_conf + DMADPR0); /* In this direction */
906 * We use the dmarx_in_progress flag to flag the channel as busy
908 card->dmarx_in_progress = 1;
909 outb(0x03, card->pci_conf + DMACSR0); /* Start the transfer */
913 * Send a frame through the DMA
916 fst_tx_dma(struct fst_card_info *card, unsigned char *skb,
917 unsigned char *mem, int len)
920 * This routine will setup the DMA and start it.
923 dbg(DBG_TX, "In fst_tx_dma %p %p %d\n", skb, mem, len);
924 if (card->dmatx_in_progress) {
925 dbg(DBG_ASS, "In fst_tx_dma while dma in progress\n");
928 outl((unsigned long) skb, card->pci_conf + DMAPADR1); /* Copy from here */
929 outl((unsigned long) mem, card->pci_conf + DMALADR1); /* to here */
930 outl(len, card->pci_conf + DMASIZ1); /* for this length */
931 outl(0x000000004, card->pci_conf + DMADPR1); /* In this direction */
934 * We use the dmatx_in_progress to flag the channel as busy
936 card->dmatx_in_progress = 1;
937 outb(0x03, card->pci_conf + DMACSR1); /* Start the transfer */
940 /* Issue a Mailbox command for a port.
941 * Note we issue them on a fire and forget basis, not expecting to see an
942 * error and not waiting for completion.
945 fst_issue_cmd(struct fst_port_info *port, unsigned short cmd)
947 struct fst_card_info *card;
948 unsigned short mbval;
953 spin_lock_irqsave(&card->card_lock, flags);
954 mbval = FST_RDW(card, portMailbox[port->index][0]);
957 /* Wait for any previous command to complete */
958 while (mbval > NAK) {
959 spin_unlock_irqrestore(&card->card_lock, flags);
960 schedule_timeout_uninterruptible(1);
961 spin_lock_irqsave(&card->card_lock, flags);
963 if (++safety > 2000) {
964 pr_err("Mailbox safety timeout\n");
968 mbval = FST_RDW(card, portMailbox[port->index][0]);
971 dbg(DBG_CMD, "Mailbox clear after %d jiffies\n", safety);
974 dbg(DBG_CMD, "issue_cmd: previous command was NAK'd\n");
977 FST_WRW(card, portMailbox[port->index][0], cmd);
979 if (cmd == ABORTTX || cmd == STARTPORT) {
985 spin_unlock_irqrestore(&card->card_lock, flags);
988 /* Port output signals control
991 fst_op_raise(struct fst_port_info *port, unsigned int outputs)
993 outputs |= FST_RDL(port->card, v24OpSts[port->index]);
994 FST_WRL(port->card, v24OpSts[port->index], outputs);
997 fst_issue_cmd(port, SETV24O);
1001 fst_op_lower(struct fst_port_info *port, unsigned int outputs)
1003 outputs = ~outputs & FST_RDL(port->card, v24OpSts[port->index]);
1004 FST_WRL(port->card, v24OpSts[port->index], outputs);
1007 fst_issue_cmd(port, SETV24O);
1011 * Setup port Rx buffers
1014 fst_rx_config(struct fst_port_info *port)
1018 unsigned int offset;
1019 unsigned long flags;
1020 struct fst_card_info *card;
1024 spin_lock_irqsave(&card->card_lock, flags);
1025 for (i = 0; i < NUM_RX_BUFFER; i++) {
1026 offset = BUF_OFFSET(rxBuffer[pi][i][0]);
1028 FST_WRW(card, rxDescrRing[pi][i].ladr, (u16) offset);
1029 FST_WRB(card, rxDescrRing[pi][i].hadr, (u8) (offset >> 16));
1030 FST_WRW(card, rxDescrRing[pi][i].bcnt, cnv_bcnt(LEN_RX_BUFFER));
1031 FST_WRW(card, rxDescrRing[pi][i].mcnt, LEN_RX_BUFFER);
1032 FST_WRB(card, rxDescrRing[pi][i].bits, DMA_OWN);
1035 spin_unlock_irqrestore(&card->card_lock, flags);
1039 * Setup port Tx buffers
1042 fst_tx_config(struct fst_port_info *port)
1046 unsigned int offset;
1047 unsigned long flags;
1048 struct fst_card_info *card;
1052 spin_lock_irqsave(&card->card_lock, flags);
1053 for (i = 0; i < NUM_TX_BUFFER; i++) {
1054 offset = BUF_OFFSET(txBuffer[pi][i][0]);
1056 FST_WRW(card, txDescrRing[pi][i].ladr, (u16) offset);
1057 FST_WRB(card, txDescrRing[pi][i].hadr, (u8) (offset >> 16));
1058 FST_WRW(card, txDescrRing[pi][i].bcnt, 0);
1059 FST_WRB(card, txDescrRing[pi][i].bits, 0);
1064 spin_unlock_irqrestore(&card->card_lock, flags);
1067 /* TE1 Alarm change interrupt event
1070 fst_intr_te1_alarm(struct fst_card_info *card, struct fst_port_info *port)
1076 los = FST_RDB(card, suStatus.lossOfSignal);
1077 rra = FST_RDB(card, suStatus.receiveRemoteAlarm);
1078 ais = FST_RDB(card, suStatus.alarmIndicationSignal);
1084 if (netif_carrier_ok(port_to_dev(port))) {
1085 dbg(DBG_INTR, "Net carrier off\n");
1086 netif_carrier_off(port_to_dev(port));
1092 if (!netif_carrier_ok(port_to_dev(port))) {
1093 dbg(DBG_INTR, "Net carrier on\n");
1094 netif_carrier_on(port_to_dev(port));
1099 dbg(DBG_INTR, "Assert LOS Alarm\n");
1101 dbg(DBG_INTR, "De-assert LOS Alarm\n");
1103 dbg(DBG_INTR, "Assert RRA Alarm\n");
1105 dbg(DBG_INTR, "De-assert RRA Alarm\n");
1108 dbg(DBG_INTR, "Assert AIS Alarm\n");
1110 dbg(DBG_INTR, "De-assert AIS Alarm\n");
1113 /* Control signal change interrupt event
1116 fst_intr_ctlchg(struct fst_card_info *card, struct fst_port_info *port)
1120 signals = FST_RDL(card, v24DebouncedSts[port->index]);
1122 if (signals & (((port->hwif == X21) || (port->hwif == X21D))
1123 ? IPSTS_INDICATE : IPSTS_DCD)) {
1124 if (!netif_carrier_ok(port_to_dev(port))) {
1125 dbg(DBG_INTR, "DCD active\n");
1126 netif_carrier_on(port_to_dev(port));
1129 if (netif_carrier_ok(port_to_dev(port))) {
1130 dbg(DBG_INTR, "DCD lost\n");
1131 netif_carrier_off(port_to_dev(port));
1139 fst_log_rx_error(struct fst_card_info *card, struct fst_port_info *port,
1140 unsigned char dmabits, int rxp, unsigned short len)
1142 struct net_device *dev = port_to_dev(port);
1145 * Increment the appropriate error counter
1147 dev->stats.rx_errors++;
1148 if (dmabits & RX_OFLO) {
1149 dev->stats.rx_fifo_errors++;
1150 dbg(DBG_ASS, "Rx fifo error on card %d port %d buffer %d\n",
1151 card->card_no, port->index, rxp);
1153 if (dmabits & RX_CRC) {
1154 dev->stats.rx_crc_errors++;
1155 dbg(DBG_ASS, "Rx crc error on card %d port %d\n",
1156 card->card_no, port->index);
1158 if (dmabits & RX_FRAM) {
1159 dev->stats.rx_frame_errors++;
1160 dbg(DBG_ASS, "Rx frame error on card %d port %d\n",
1161 card->card_no, port->index);
1163 if (dmabits == (RX_STP | RX_ENP)) {
1164 dev->stats.rx_length_errors++;
1165 dbg(DBG_ASS, "Rx length error (%d) on card %d port %d\n",
1166 len, card->card_no, port->index);
1170 /* Rx Error Recovery
1173 fst_recover_rx_error(struct fst_card_info *card, struct fst_port_info *port,
1174 unsigned char dmabits, int rxp, unsigned short len)
1181 * Discard buffer descriptors until we see the start of the
1182 * next frame. Note that for long frames this could be in
1183 * a subsequent interrupt.
1186 while ((dmabits & (DMA_OWN | RX_STP)) == 0) {
1187 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
1188 rxp = (rxp+1) % NUM_RX_BUFFER;
1189 if (++i > NUM_RX_BUFFER) {
1190 dbg(DBG_ASS, "intr_rx: Discarding more bufs"
1194 dmabits = FST_RDB(card, rxDescrRing[pi][rxp].bits);
1195 dbg(DBG_ASS, "DMA Bits of next buffer was %x\n", dmabits);
1197 dbg(DBG_ASS, "There were %d subsequent buffers in error\n", i);
1199 /* Discard the terminal buffer */
1200 if (!(dmabits & DMA_OWN)) {
1201 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
1202 rxp = (rxp+1) % NUM_RX_BUFFER;
1209 /* Rx complete interrupt
1212 fst_intr_rx(struct fst_card_info *card, struct fst_port_info *port)
1214 unsigned char dmabits;
1219 struct sk_buff *skb;
1220 struct net_device *dev = port_to_dev(port);
1222 /* Check we have a buffer to process */
1225 dmabits = FST_RDB(card, rxDescrRing[pi][rxp].bits);
1226 if (dmabits & DMA_OWN) {
1227 dbg(DBG_RX | DBG_INTR, "intr_rx: No buffer port %d pos %d\n",
1231 if (card->dmarx_in_progress) {
1235 /* Get buffer length */
1236 len = FST_RDW(card, rxDescrRing[pi][rxp].mcnt);
1237 /* Discard the CRC */
1241 * This seems to happen on the TE1 interface sometimes
1242 * so throw the frame away and log the event.
1244 pr_err("Frame received with 0 length. Card %d Port %d\n",
1245 card->card_no, port->index);
1246 /* Return descriptor to card */
1247 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
1249 rxp = (rxp+1) % NUM_RX_BUFFER;
1254 /* Check buffer length and for other errors. We insist on one packet
1255 * in one buffer. This simplifies things greatly and since we've
1256 * allocated 8K it shouldn't be a real world limitation
1258 dbg(DBG_RX, "intr_rx: %d,%d: flags %x len %d\n", pi, rxp, dmabits, len);
1259 if (dmabits != (RX_STP | RX_ENP) || len > LEN_RX_BUFFER - 2) {
1260 fst_log_rx_error(card, port, dmabits, rxp, len);
1261 fst_recover_rx_error(card, port, dmabits, rxp, len);
1266 if ((skb = dev_alloc_skb(len)) == NULL) {
1267 dbg(DBG_RX, "intr_rx: can't allocate buffer\n");
1269 dev->stats.rx_dropped++;
1271 /* Return descriptor to card */
1272 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
1274 rxp = (rxp+1) % NUM_RX_BUFFER;
1280 * We know the length we need to receive, len.
1281 * It's not worth using the DMA for reads of less than
1285 if ((len < FST_MIN_DMA_LEN) || (card->family == FST_FAMILY_TXP)) {
1286 memcpy_fromio(skb_put(skb, len),
1287 card->mem + BUF_OFFSET(rxBuffer[pi][rxp][0]),
1290 /* Reset buffer descriptor */
1291 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
1294 dev->stats.rx_packets++;
1295 dev->stats.rx_bytes += len;
1298 dbg(DBG_RX, "Pushing frame up the stack\n");
1299 if (port->mode == FST_RAW)
1300 skb->protocol = farsync_type_trans(skb, dev);
1302 skb->protocol = hdlc_type_trans(skb, dev);
1303 rx_status = netif_rx(skb);
1304 fst_process_rx_status(rx_status, port_to_dev(port)->name);
1305 if (rx_status == NET_RX_DROP)
1306 dev->stats.rx_dropped++;
1308 card->dma_skb_rx = skb;
1309 card->dma_port_rx = port;
1310 card->dma_len_rx = len;
1311 card->dma_rxpos = rxp;
1312 fst_rx_dma(card, (char *) card->rx_dma_handle_card,
1313 (char *) BUF_OFFSET(rxBuffer[pi][rxp][0]), len);
1315 if (rxp != port->rxpos) {
1316 dbg(DBG_ASS, "About to increment rxpos by more than 1\n");
1317 dbg(DBG_ASS, "rxp = %d rxpos = %d\n", rxp, port->rxpos);
1319 rxp = (rxp+1) % NUM_RX_BUFFER;
1324 * The bottom halfs to the ISR
1329 do_bottom_half_tx(struct fst_card_info *card)
1331 struct fst_port_info *port;
1334 struct sk_buff *skb;
1335 unsigned long flags;
1336 struct net_device *dev;
1339 * Find a free buffer for the transmit
1340 * Step through each port on this card
1343 dbg(DBG_TX, "do_bottom_half_tx\n");
1344 for (pi = 0, port = card->ports; pi < card->nports; pi++, port++) {
1348 dev = port_to_dev(port);
1349 while (!(FST_RDB(card, txDescrRing[pi][port->txpos].bits) &
1351 !(card->dmatx_in_progress)) {
1353 * There doesn't seem to be a txdone event per-se
1354 * We seem to have to deduce it, by checking the DMA_OWN
1355 * bit on the next buffer we think we can use
1357 spin_lock_irqsave(&card->card_lock, flags);
1358 if ((txq_length = port->txqe - port->txqs) < 0) {
1360 * This is the case where one has wrapped and the
1361 * maths gives us a negative number
1363 txq_length = txq_length + FST_TXQ_DEPTH;
1365 spin_unlock_irqrestore(&card->card_lock, flags);
1366 if (txq_length > 0) {
1368 * There is something to send
1370 spin_lock_irqsave(&card->card_lock, flags);
1371 skb = port->txq[port->txqs];
1373 if (port->txqs == FST_TXQ_DEPTH) {
1376 spin_unlock_irqrestore(&card->card_lock, flags);
1378 * copy the data and set the required indicators on the
1381 FST_WRW(card, txDescrRing[pi][port->txpos].bcnt,
1382 cnv_bcnt(skb->len));
1383 if ((skb->len < FST_MIN_DMA_LEN) ||
1384 (card->family == FST_FAMILY_TXP)) {
1385 /* Enqueue the packet with normal io */
1386 memcpy_toio(card->mem +
1387 BUF_OFFSET(txBuffer[pi]
1390 skb->data, skb->len);
1392 txDescrRing[pi][port->txpos].
1394 DMA_OWN | TX_STP | TX_ENP);
1395 dev->stats.tx_packets++;
1396 dev->stats.tx_bytes += skb->len;
1397 dev->trans_start = jiffies;
1399 /* Or do it through dma */
1400 memcpy(card->tx_dma_handle_host,
1401 skb->data, skb->len);
1402 card->dma_port_tx = port;
1403 card->dma_len_tx = skb->len;
1404 card->dma_txpos = port->txpos;
1409 BUF_OFFSET(txBuffer[pi]
1413 if (++port->txpos >= NUM_TX_BUFFER)
1416 * If we have flow control on, can we now release it?
1419 if (txq_length < fst_txq_low) {
1420 netif_wake_queue(port_to_dev
1428 * Nothing to send so break out of the while loop
1437 do_bottom_half_rx(struct fst_card_info *card)
1439 struct fst_port_info *port;
1443 /* Check for rx completions on all ports on this card */
1444 dbg(DBG_RX, "do_bottom_half_rx\n");
1445 for (pi = 0, port = card->ports; pi < card->nports; pi++, port++) {
1449 while (!(FST_RDB(card, rxDescrRing[pi][port->rxpos].bits)
1450 & DMA_OWN) && !(card->dmarx_in_progress)) {
1451 if (rx_count > fst_max_reads) {
1453 * Don't spend forever in receive processing
1454 * Schedule another event
1456 fst_q_work_item(&fst_work_intq, card->card_no);
1457 tasklet_schedule(&fst_int_task);
1458 break; /* Leave the loop */
1460 fst_intr_rx(card, port);
1467 * The interrupt service routine
1468 * Dev_id is our fst_card_info pointer
1471 fst_intr(int dummy, void *dev_id)
1473 struct fst_card_info *card = dev_id;
1474 struct fst_port_info *port;
1475 int rdidx; /* Event buffer indices */
1477 int event; /* Actual event for processing */
1478 unsigned int dma_intcsr = 0;
1479 unsigned int do_card_interrupt;
1480 unsigned int int_retry_count;
1483 * Check to see if the interrupt was for this card
1485 * Note that the call to clear the interrupt is important
1487 dbg(DBG_INTR, "intr: %d %p\n", card->irq, card);
1488 if (card->state != FST_RUNNING) {
1489 pr_err("Interrupt received for card %d in a non running state (%d)\n",
1490 card->card_no, card->state);
1493 * It is possible to really be running, i.e. we have re-loaded
1495 * Clear and reprime the interrupt source
1497 fst_clear_intr(card);
1501 /* Clear and reprime the interrupt source */
1502 fst_clear_intr(card);
1505 * Is the interrupt for this card (handshake == 1)
1507 do_card_interrupt = 0;
1508 if (FST_RDB(card, interruptHandshake) == 1) {
1509 do_card_interrupt += FST_CARD_INT;
1510 /* Set the software acknowledge */
1511 FST_WRB(card, interruptHandshake, 0xEE);
1513 if (card->family == FST_FAMILY_TXU) {
1515 * Is it a DMA Interrupt
1517 dma_intcsr = inl(card->pci_conf + INTCSR_9054);
1518 if (dma_intcsr & 0x00200000) {
1520 * DMA Channel 0 (Rx transfer complete)
1522 dbg(DBG_RX, "DMA Rx xfer complete\n");
1523 outb(0x8, card->pci_conf + DMACSR0);
1524 fst_rx_dma_complete(card, card->dma_port_rx,
1525 card->dma_len_rx, card->dma_skb_rx,
1527 card->dmarx_in_progress = 0;
1528 do_card_interrupt += FST_RX_DMA_INT;
1530 if (dma_intcsr & 0x00400000) {
1532 * DMA Channel 1 (Tx transfer complete)
1534 dbg(DBG_TX, "DMA Tx xfer complete\n");
1535 outb(0x8, card->pci_conf + DMACSR1);
1536 fst_tx_dma_complete(card, card->dma_port_tx,
1537 card->dma_len_tx, card->dma_txpos);
1538 card->dmatx_in_progress = 0;
1539 do_card_interrupt += FST_TX_DMA_INT;
1544 * Have we been missing Interrupts
1546 int_retry_count = FST_RDL(card, interruptRetryCount);
1547 if (int_retry_count) {
1548 dbg(DBG_ASS, "Card %d int_retry_count is %d\n",
1549 card->card_no, int_retry_count);
1550 FST_WRL(card, interruptRetryCount, 0);
1553 if (!do_card_interrupt) {
1557 /* Scehdule the bottom half of the ISR */
1558 fst_q_work_item(&fst_work_intq, card->card_no);
1559 tasklet_schedule(&fst_int_task);
1561 /* Drain the event queue */
1562 rdidx = FST_RDB(card, interruptEvent.rdindex) & 0x1f;
1563 wridx = FST_RDB(card, interruptEvent.wrindex) & 0x1f;
1564 while (rdidx != wridx) {
1565 event = FST_RDB(card, interruptEvent.evntbuff[rdidx]);
1566 port = &card->ports[event & 0x03];
1568 dbg(DBG_INTR, "Processing Interrupt event: %x\n", event);
1572 dbg(DBG_INTR, "TE1 Alarm intr\n");
1574 fst_intr_te1_alarm(card, port);
1582 fst_intr_ctlchg(card, port);
1589 dbg(DBG_TX, "Abort complete port %d\n", port->index);
1596 /* Difficult to see how we'd get this given that we
1597 * always load up the entire packet for DMA.
1599 dbg(DBG_TX, "Tx underflow port %d\n", port->index);
1600 port_to_dev(port)->stats.tx_errors++;
1601 port_to_dev(port)->stats.tx_fifo_errors++;
1602 dbg(DBG_ASS, "Tx underflow on card %d port %d\n",
1603 card->card_no, port->index);
1607 dbg(DBG_INIT, "Card init OK intr\n");
1611 dbg(DBG_INIT, "Card init FAILED intr\n");
1612 card->state = FST_IFAILED;
1616 pr_err("intr: unknown card event %d. ignored\n", event);
1620 /* Bump and wrap the index */
1621 if (++rdidx >= MAX_CIRBUFF)
1624 FST_WRB(card, interruptEvent.rdindex, rdidx);
1628 /* Check that the shared memory configuration is one that we can handle
1629 * and that some basic parameters are correct
1632 check_started_ok(struct fst_card_info *card)
1636 /* Check structure version and end marker */
1637 if (FST_RDW(card, smcVersion) != SMC_VERSION) {
1638 pr_err("Bad shared memory version %d expected %d\n",
1639 FST_RDW(card, smcVersion), SMC_VERSION);
1640 card->state = FST_BADVERSION;
1643 if (FST_RDL(card, endOfSmcSignature) != END_SIG) {
1644 pr_err("Missing shared memory signature\n");
1645 card->state = FST_BADVERSION;
1648 /* Firmware status flag, 0x00 = initialising, 0x01 = OK, 0xFF = fail */
1649 if ((i = FST_RDB(card, taskStatus)) == 0x01) {
1650 card->state = FST_RUNNING;
1651 } else if (i == 0xFF) {
1652 pr_err("Firmware initialisation failed. Card halted\n");
1653 card->state = FST_HALTED;
1655 } else if (i != 0x00) {
1656 pr_err("Unknown firmware status 0x%x\n", i);
1657 card->state = FST_HALTED;
1661 /* Finally check the number of ports reported by firmware against the
1662 * number we assumed at card detection. Should never happen with
1663 * existing firmware etc so we just report it for the moment.
1665 if (FST_RDL(card, numberOfPorts) != card->nports) {
1666 pr_warning("Port count mismatch on card %d. "
1667 "Firmware thinks %d we say %d\n",
1669 FST_RDL(card, numberOfPorts), card->nports);
1674 set_conf_from_info(struct fst_card_info *card, struct fst_port_info *port,
1675 struct fstioc_info *info)
1678 unsigned char my_framing;
1680 /* Set things according to the user set valid flags
1681 * Several of the old options have been invalidated/replaced by the
1682 * generic hdlc package.
1685 if (info->valid & FSTVAL_PROTO) {
1686 if (info->proto == FST_RAW)
1687 port->mode = FST_RAW;
1689 port->mode = FST_GEN_HDLC;
1692 if (info->valid & FSTVAL_CABLE)
1695 if (info->valid & FSTVAL_SPEED)
1698 if (info->valid & FSTVAL_PHASE)
1699 FST_WRB(card, portConfig[port->index].invertClock,
1701 if (info->valid & FSTVAL_MODE)
1702 FST_WRW(card, cardMode, info->cardMode);
1703 if (info->valid & FSTVAL_TE1) {
1704 FST_WRL(card, suConfig.dataRate, info->lineSpeed);
1705 FST_WRB(card, suConfig.clocking, info->clockSource);
1706 my_framing = FRAMING_E1;
1707 if (info->framing == E1)
1708 my_framing = FRAMING_E1;
1709 if (info->framing == T1)
1710 my_framing = FRAMING_T1;
1711 if (info->framing == J1)
1712 my_framing = FRAMING_J1;
1713 FST_WRB(card, suConfig.framing, my_framing);
1714 FST_WRB(card, suConfig.structure, info->structure);
1715 FST_WRB(card, suConfig.interface, info->interface);
1716 FST_WRB(card, suConfig.coding, info->coding);
1717 FST_WRB(card, suConfig.lineBuildOut, info->lineBuildOut);
1718 FST_WRB(card, suConfig.equalizer, info->equalizer);
1719 FST_WRB(card, suConfig.transparentMode, info->transparentMode);
1720 FST_WRB(card, suConfig.loopMode, info->loopMode);
1721 FST_WRB(card, suConfig.range, info->range);
1722 FST_WRB(card, suConfig.txBufferMode, info->txBufferMode);
1723 FST_WRB(card, suConfig.rxBufferMode, info->rxBufferMode);
1724 FST_WRB(card, suConfig.startingSlot, info->startingSlot);
1725 FST_WRB(card, suConfig.losThreshold, info->losThreshold);
1727 FST_WRB(card, suConfig.enableIdleCode, 1);
1729 FST_WRB(card, suConfig.enableIdleCode, 0);
1730 FST_WRB(card, suConfig.idleCode, info->idleCode);
1732 if (info->valid & FSTVAL_TE1) {
1733 printk("Setting TE1 data\n");
1734 printk("Line Speed = %d\n", info->lineSpeed);
1735 printk("Start slot = %d\n", info->startingSlot);
1736 printk("Clock source = %d\n", info->clockSource);
1737 printk("Framing = %d\n", my_framing);
1738 printk("Structure = %d\n", info->structure);
1739 printk("interface = %d\n", info->interface);
1740 printk("Coding = %d\n", info->coding);
1741 printk("Line build out = %d\n", info->lineBuildOut);
1742 printk("Equaliser = %d\n", info->equalizer);
1743 printk("Transparent mode = %d\n",
1744 info->transparentMode);
1745 printk("Loop mode = %d\n", info->loopMode);
1746 printk("Range = %d\n", info->range);
1747 printk("Tx Buffer mode = %d\n", info->txBufferMode);
1748 printk("Rx Buffer mode = %d\n", info->rxBufferMode);
1749 printk("LOS Threshold = %d\n", info->losThreshold);
1750 printk("Idle Code = %d\n", info->idleCode);
1755 if (info->valid & FSTVAL_DEBUG) {
1756 fst_debug_mask = info->debug;
1764 gather_conf_info(struct fst_card_info *card, struct fst_port_info *port,
1765 struct fstioc_info *info)
1769 memset(info, 0, sizeof (struct fstioc_info));
1772 info->kernelVersion = LINUX_VERSION_CODE;
1773 info->nports = card->nports;
1774 info->type = card->type;
1775 info->state = card->state;
1776 info->proto = FST_GEN_HDLC;
1779 info->debug = fst_debug_mask;
1782 /* Only mark information as valid if card is running.
1783 * Copy the data anyway in case it is useful for diagnostics
1785 info->valid = ((card->state == FST_RUNNING) ? FSTVAL_ALL : FSTVAL_CARD)
1791 info->lineInterface = FST_RDW(card, portConfig[i].lineInterface);
1792 info->internalClock = FST_RDB(card, portConfig[i].internalClock);
1793 info->lineSpeed = FST_RDL(card, portConfig[i].lineSpeed);
1794 info->invertClock = FST_RDB(card, portConfig[i].invertClock);
1795 info->v24IpSts = FST_RDL(card, v24IpSts[i]);
1796 info->v24OpSts = FST_RDL(card, v24OpSts[i]);
1797 info->clockStatus = FST_RDW(card, clockStatus[i]);
1798 info->cableStatus = FST_RDW(card, cableStatus);
1799 info->cardMode = FST_RDW(card, cardMode);
1800 info->smcFirmwareVersion = FST_RDL(card, smcFirmwareVersion);
1803 * The T2U can report cable presence for both A or B
1804 * in bits 0 and 1 of cableStatus. See which port we are and
1807 if (card->family == FST_FAMILY_TXU) {
1808 if (port->index == 0) {
1812 info->cableStatus = info->cableStatus & 1;
1817 info->cableStatus = info->cableStatus >> 1;
1818 info->cableStatus = info->cableStatus & 1;
1822 * Some additional bits if we are TE1
1824 if (card->type == FST_TYPE_TE1) {
1825 info->lineSpeed = FST_RDL(card, suConfig.dataRate);
1826 info->clockSource = FST_RDB(card, suConfig.clocking);
1827 info->framing = FST_RDB(card, suConfig.framing);
1828 info->structure = FST_RDB(card, suConfig.structure);
1829 info->interface = FST_RDB(card, suConfig.interface);
1830 info->coding = FST_RDB(card, suConfig.coding);
1831 info->lineBuildOut = FST_RDB(card, suConfig.lineBuildOut);
1832 info->equalizer = FST_RDB(card, suConfig.equalizer);
1833 info->loopMode = FST_RDB(card, suConfig.loopMode);
1834 info->range = FST_RDB(card, suConfig.range);
1835 info->txBufferMode = FST_RDB(card, suConfig.txBufferMode);
1836 info->rxBufferMode = FST_RDB(card, suConfig.rxBufferMode);
1837 info->startingSlot = FST_RDB(card, suConfig.startingSlot);
1838 info->losThreshold = FST_RDB(card, suConfig.losThreshold);
1839 if (FST_RDB(card, suConfig.enableIdleCode))
1840 info->idleCode = FST_RDB(card, suConfig.idleCode);
1843 info->receiveBufferDelay =
1844 FST_RDL(card, suStatus.receiveBufferDelay);
1845 info->framingErrorCount =
1846 FST_RDL(card, suStatus.framingErrorCount);
1847 info->codeViolationCount =
1848 FST_RDL(card, suStatus.codeViolationCount);
1849 info->crcErrorCount = FST_RDL(card, suStatus.crcErrorCount);
1850 info->lineAttenuation = FST_RDL(card, suStatus.lineAttenuation);
1851 info->lossOfSignal = FST_RDB(card, suStatus.lossOfSignal);
1852 info->receiveRemoteAlarm =
1853 FST_RDB(card, suStatus.receiveRemoteAlarm);
1854 info->alarmIndicationSignal =
1855 FST_RDB(card, suStatus.alarmIndicationSignal);
1860 fst_set_iface(struct fst_card_info *card, struct fst_port_info *port,
1863 sync_serial_settings sync;
1866 if (ifr->ifr_settings.size != sizeof (sync)) {
1871 (&sync, ifr->ifr_settings.ifs_ifsu.sync, sizeof (sync))) {
1880 switch (ifr->ifr_settings.type) {
1882 FST_WRW(card, portConfig[i].lineInterface, V35);
1887 FST_WRW(card, portConfig[i].lineInterface, V24);
1892 FST_WRW(card, portConfig[i].lineInterface, X21);
1897 FST_WRW(card, portConfig[i].lineInterface, X21D);
1902 FST_WRW(card, portConfig[i].lineInterface, T1);
1907 FST_WRW(card, portConfig[i].lineInterface, E1);
1911 case IF_IFACE_SYNC_SERIAL:
1918 switch (sync.clock_type) {
1920 FST_WRB(card, portConfig[i].internalClock, EXTCLK);
1924 FST_WRB(card, portConfig[i].internalClock, INTCLK);
1930 FST_WRL(card, portConfig[i].lineSpeed, sync.clock_rate);
1935 fst_get_iface(struct fst_card_info *card, struct fst_port_info *port,
1938 sync_serial_settings sync;
1941 /* First check what line type is set, we'll default to reporting X.21
1942 * if nothing is set as IF_IFACE_SYNC_SERIAL implies it can't be
1945 switch (port->hwif) {
1947 ifr->ifr_settings.type = IF_IFACE_E1;
1950 ifr->ifr_settings.type = IF_IFACE_T1;
1953 ifr->ifr_settings.type = IF_IFACE_V35;
1956 ifr->ifr_settings.type = IF_IFACE_V24;
1959 ifr->ifr_settings.type = IF_IFACE_X21D;
1963 ifr->ifr_settings.type = IF_IFACE_X21;
1966 if (ifr->ifr_settings.size == 0) {
1967 return 0; /* only type requested */
1969 if (ifr->ifr_settings.size < sizeof (sync)) {
1974 sync.clock_rate = FST_RDL(card, portConfig[i].lineSpeed);
1975 /* Lucky card and linux use same encoding here */
1976 sync.clock_type = FST_RDB(card, portConfig[i].internalClock) ==
1977 INTCLK ? CLOCK_INT : CLOCK_EXT;
1980 if (copy_to_user(ifr->ifr_settings.ifs_ifsu.sync, &sync, sizeof (sync))) {
1984 ifr->ifr_settings.size = sizeof (sync);
1989 fst_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1991 struct fst_card_info *card;
1992 struct fst_port_info *port;
1993 struct fstioc_write wrthdr;
1994 struct fstioc_info info;
1995 unsigned long flags;
1998 dbg(DBG_IOCTL, "ioctl: %x, %p\n", cmd, ifr->ifr_data);
2000 port = dev_to_port(dev);
2003 if (!capable(CAP_NET_ADMIN))
2009 card->state = FST_RESET;
2013 fst_cpurelease(card);
2014 card->state = FST_STARTING;
2017 case FSTWRITE: /* Code write (download) */
2019 /* First copy in the header with the length and offset of data
2022 if (ifr->ifr_data == NULL) {
2025 if (copy_from_user(&wrthdr, ifr->ifr_data,
2026 sizeof (struct fstioc_write))) {
2030 /* Sanity check the parameters. We don't support partial writes
2031 * when going over the top
2033 if (wrthdr.size > FST_MEMSIZE || wrthdr.offset > FST_MEMSIZE ||
2034 wrthdr.size + wrthdr.offset > FST_MEMSIZE) {
2038 /* Now copy the data to the card. */
2040 buf = memdup_user(ifr->ifr_data + sizeof(struct fstioc_write),
2043 return PTR_ERR(buf);
2045 memcpy_toio(card->mem + wrthdr.offset, buf, wrthdr.size);
2048 /* Writes to the memory of a card in the reset state constitute
2051 if (card->state == FST_RESET) {
2052 card->state = FST_DOWNLOAD;
2058 /* If card has just been started check the shared memory config
2059 * version and marker
2061 if (card->state == FST_STARTING) {
2062 check_started_ok(card);
2064 /* If everything checked out enable card interrupts */
2065 if (card->state == FST_RUNNING) {
2066 spin_lock_irqsave(&card->card_lock, flags);
2067 fst_enable_intr(card);
2068 FST_WRB(card, interruptHandshake, 0xEE);
2069 spin_unlock_irqrestore(&card->card_lock, flags);
2073 if (ifr->ifr_data == NULL) {
2077 gather_conf_info(card, port, &info);
2079 if (copy_to_user(ifr->ifr_data, &info, sizeof (info))) {
2087 * Most of the settings have been moved to the generic ioctls
2088 * this just covers debug and board ident now
2091 if (card->state != FST_RUNNING) {
2092 pr_err("Attempt to configure card %d in non-running state (%d)\n",
2093 card->card_no, card->state);
2096 if (copy_from_user(&info, ifr->ifr_data, sizeof (info))) {
2100 return set_conf_from_info(card, port, &info);
2103 switch (ifr->ifr_settings.type) {
2105 return fst_get_iface(card, port, ifr);
2107 case IF_IFACE_SYNC_SERIAL:
2114 return fst_set_iface(card, port, ifr);
2117 port->mode = FST_RAW;
2121 if (port->mode == FST_RAW) {
2122 ifr->ifr_settings.type = IF_PROTO_RAW;
2125 return hdlc_ioctl(dev, ifr, cmd);
2128 port->mode = FST_GEN_HDLC;
2129 dbg(DBG_IOCTL, "Passing this type to hdlc %x\n",
2130 ifr->ifr_settings.type);
2131 return hdlc_ioctl(dev, ifr, cmd);
2135 /* Not one of ours. Pass through to HDLC package */
2136 return hdlc_ioctl(dev, ifr, cmd);
2141 fst_openport(struct fst_port_info *port)
2146 /* Only init things if card is actually running. This allows open to
2147 * succeed for downloads etc.
2149 if (port->card->state == FST_RUNNING) {
2151 dbg(DBG_OPEN, "open: found port already running\n");
2153 fst_issue_cmd(port, STOPPORT);
2157 fst_rx_config(port);
2158 fst_tx_config(port);
2159 fst_op_raise(port, OPSTS_RTS | OPSTS_DTR);
2161 fst_issue_cmd(port, STARTPORT);
2164 signals = FST_RDL(port->card, v24DebouncedSts[port->index]);
2165 if (signals & (((port->hwif == X21) || (port->hwif == X21D))
2166 ? IPSTS_INDICATE : IPSTS_DCD))
2167 netif_carrier_on(port_to_dev(port));
2169 netif_carrier_off(port_to_dev(port));
2171 txq_length = port->txqe - port->txqs;
2179 fst_closeport(struct fst_port_info *port)
2181 if (port->card->state == FST_RUNNING) {
2184 fst_op_lower(port, OPSTS_RTS | OPSTS_DTR);
2186 fst_issue_cmd(port, STOPPORT);
2188 dbg(DBG_OPEN, "close: port not running\n");
2194 fst_open(struct net_device *dev)
2197 struct fst_port_info *port;
2199 port = dev_to_port(dev);
2200 if (!try_module_get(THIS_MODULE))
2203 if (port->mode != FST_RAW) {
2204 err = hdlc_open(dev);
2210 netif_wake_queue(dev);
2215 fst_close(struct net_device *dev)
2217 struct fst_port_info *port;
2218 struct fst_card_info *card;
2219 unsigned char tx_dma_done;
2220 unsigned char rx_dma_done;
2222 port = dev_to_port(dev);
2225 tx_dma_done = inb(card->pci_conf + DMACSR1);
2226 rx_dma_done = inb(card->pci_conf + DMACSR0);
2228 "Port Close: tx_dma_in_progress = %d (%x) rx_dma_in_progress = %d (%x)\n",
2229 card->dmatx_in_progress, tx_dma_done, card->dmarx_in_progress,
2232 netif_stop_queue(dev);
2233 fst_closeport(dev_to_port(dev));
2234 if (port->mode != FST_RAW) {
2237 module_put(THIS_MODULE);
2242 fst_attach(struct net_device *dev, unsigned short encoding, unsigned short parity)
2245 * Setting currently fixed in FarSync card so we check and forget
2247 if (encoding != ENCODING_NRZ || parity != PARITY_CRC16_PR1_CCITT)
2253 fst_tx_timeout(struct net_device *dev)
2255 struct fst_port_info *port;
2256 struct fst_card_info *card;
2258 port = dev_to_port(dev);
2260 dev->stats.tx_errors++;
2261 dev->stats.tx_aborted_errors++;
2262 dbg(DBG_ASS, "Tx timeout card %d port %d\n",
2263 card->card_no, port->index);
2264 fst_issue_cmd(port, ABORTTX);
2266 dev->trans_start = jiffies;
2267 netif_wake_queue(dev);
2272 fst_start_xmit(struct sk_buff *skb, struct net_device *dev)
2274 struct fst_card_info *card;
2275 struct fst_port_info *port;
2276 unsigned long flags;
2279 port = dev_to_port(dev);
2281 dbg(DBG_TX, "fst_start_xmit: length = %d\n", skb->len);
2283 /* Drop packet with error if we don't have carrier */
2284 if (!netif_carrier_ok(dev)) {
2286 dev->stats.tx_errors++;
2287 dev->stats.tx_carrier_errors++;
2289 "Tried to transmit but no carrier on card %d port %d\n",
2290 card->card_no, port->index);
2291 return NETDEV_TX_OK;
2294 /* Drop it if it's too big! MTU failure ? */
2295 if (skb->len > LEN_TX_BUFFER) {
2296 dbg(DBG_ASS, "Packet too large %d vs %d\n", skb->len,
2299 dev->stats.tx_errors++;
2300 return NETDEV_TX_OK;
2304 * We are always going to queue the packet
2305 * so that the bottom half is the only place we tx from
2306 * Check there is room in the port txq
2308 spin_lock_irqsave(&card->card_lock, flags);
2309 if ((txq_length = port->txqe - port->txqs) < 0) {
2311 * This is the case where the next free has wrapped but the
2314 txq_length = txq_length + FST_TXQ_DEPTH;
2316 spin_unlock_irqrestore(&card->card_lock, flags);
2317 if (txq_length > fst_txq_high) {
2319 * We have got enough buffers in the pipeline. Ask the network
2320 * layer to stop sending frames down
2322 netif_stop_queue(dev);
2323 port->start = 1; /* I'm using this to signal stop sent up */
2326 if (txq_length == FST_TXQ_DEPTH - 1) {
2328 * This shouldn't have happened but such is life
2331 dev->stats.tx_errors++;
2332 dbg(DBG_ASS, "Tx queue overflow card %d port %d\n",
2333 card->card_no, port->index);
2334 return NETDEV_TX_OK;
2340 spin_lock_irqsave(&card->card_lock, flags);
2341 port->txq[port->txqe] = skb;
2343 if (port->txqe == FST_TXQ_DEPTH)
2345 spin_unlock_irqrestore(&card->card_lock, flags);
2347 /* Scehdule the bottom half which now does transmit processing */
2348 fst_q_work_item(&fst_work_txq, card->card_no);
2349 tasklet_schedule(&fst_tx_task);
2351 return NETDEV_TX_OK;
2355 * Card setup having checked hardware resources.
2356 * Should be pretty bizarre if we get an error here (kernel memory
2357 * exhaustion is one possibility). If we do see a problem we report it
2358 * via a printk and leave the corresponding interface and all that follow
2361 static char *type_strings[] __devinitdata = {
2362 "no hardware", /* Should never be seen */
2371 static void __devinit
2372 fst_init_card(struct fst_card_info *card)
2377 /* We're working on a number of ports based on the card ID. If the
2378 * firmware detects something different later (should never happen)
2379 * we'll have to revise it in some way then.
2381 for (i = 0; i < card->nports; i++) {
2382 err = register_hdlc_device(card->ports[i].dev);
2385 pr_err("Cannot register HDLC device for port %d (errno %d)\n",
2387 for (j = i; j < card->nports; j++) {
2388 free_netdev(card->ports[j].dev);
2389 card->ports[j].dev = NULL;
2396 pr_info("%s-%s: %s IRQ%d, %d ports\n",
2397 port_to_dev(&card->ports[0])->name,
2398 port_to_dev(&card->ports[card->nports - 1])->name,
2399 type_strings[card->type], card->irq, card->nports);
2402 static const struct net_device_ops fst_ops = {
2403 .ndo_open = fst_open,
2404 .ndo_stop = fst_close,
2405 .ndo_change_mtu = hdlc_change_mtu,
2406 .ndo_start_xmit = hdlc_start_xmit,
2407 .ndo_do_ioctl = fst_ioctl,
2408 .ndo_tx_timeout = fst_tx_timeout,
2412 * Initialise card when detected.
2413 * Returns 0 to indicate success, or errno otherwise.
2415 static int __devinit
2416 fst_add_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2418 static int no_of_cards_added = 0;
2419 struct fst_card_info *card;
2423 printk_once(KERN_INFO
2424 pr_fmt("FarSync WAN driver " FST_USER_VERSION
2425 " (c) 2001-2004 FarSite Communications Ltd.\n"));
2427 dbg(DBG_ASS, "The value of debug mask is %x\n", fst_debug_mask);
2430 * We are going to be clever and allow certain cards not to be
2431 * configured. An exclude list can be provided in /etc/modules.conf
2433 if (fst_excluded_cards != 0) {
2435 * There are cards to exclude
2438 for (i = 0; i < fst_excluded_cards; i++) {
2439 if ((pdev->devfn) >> 3 == fst_excluded_list[i]) {
2440 pr_info("FarSync PCI device %d not assigned\n",
2441 (pdev->devfn) >> 3);
2447 /* Allocate driver private data */
2448 card = kzalloc(sizeof (struct fst_card_info), GFP_KERNEL);
2450 pr_err("FarSync card found but insufficient memory for driver storage\n");
2454 /* Try to enable the device */
2455 if ((err = pci_enable_device(pdev)) != 0) {
2456 pr_err("Failed to enable card. Err %d\n", -err);
2461 if ((err = pci_request_regions(pdev, "FarSync")) !=0) {
2462 pr_err("Failed to allocate regions. Err %d\n", -err);
2463 pci_disable_device(pdev);
2468 /* Get virtual addresses of memory regions */
2469 card->pci_conf = pci_resource_start(pdev, 1);
2470 card->phys_mem = pci_resource_start(pdev, 2);
2471 card->phys_ctlmem = pci_resource_start(pdev, 3);
2472 if ((card->mem = ioremap(card->phys_mem, FST_MEMSIZE)) == NULL) {
2473 pr_err("Physical memory remap failed\n");
2474 pci_release_regions(pdev);
2475 pci_disable_device(pdev);
2479 if ((card->ctlmem = ioremap(card->phys_ctlmem, 0x10)) == NULL) {
2480 pr_err("Control memory remap failed\n");
2481 pci_release_regions(pdev);
2482 pci_disable_device(pdev);
2486 dbg(DBG_PCI, "kernel mem %p, ctlmem %p\n", card->mem, card->ctlmem);
2488 /* Register the interrupt handler */
2489 if (request_irq(pdev->irq, fst_intr, IRQF_SHARED, FST_DEV_NAME, card)) {
2490 pr_err("Unable to register interrupt %d\n", card->irq);
2491 pci_release_regions(pdev);
2492 pci_disable_device(pdev);
2493 iounmap(card->ctlmem);
2499 /* Record info we need */
2500 card->irq = pdev->irq;
2501 card->type = ent->driver_data;
2502 card->family = ((ent->driver_data == FST_TYPE_T2P) ||
2503 (ent->driver_data == FST_TYPE_T4P))
2504 ? FST_FAMILY_TXP : FST_FAMILY_TXU;
2505 if ((ent->driver_data == FST_TYPE_T1U) ||
2506 (ent->driver_data == FST_TYPE_TE1))
2509 card->nports = ((ent->driver_data == FST_TYPE_T2P) ||
2510 (ent->driver_data == FST_TYPE_T2U)) ? 2 : 4;
2512 card->state = FST_UNINIT;
2513 spin_lock_init ( &card->card_lock );
2515 for ( i = 0 ; i < card->nports ; i++ ) {
2516 struct net_device *dev = alloc_hdlcdev(&card->ports[i]);
2520 free_netdev(card->ports[i].dev);
2521 pr_err("FarSync: out of memory\n");
2522 free_irq(card->irq, card);
2523 pci_release_regions(pdev);
2524 pci_disable_device(pdev);
2525 iounmap(card->ctlmem);
2530 card->ports[i].dev = dev;
2531 card->ports[i].card = card;
2532 card->ports[i].index = i;
2533 card->ports[i].run = 0;
2535 hdlc = dev_to_hdlc(dev);
2537 /* Fill in the net device info */
2538 /* Since this is a PCI setup this is purely
2539 * informational. Give them the buffer addresses
2540 * and basic card I/O.
2542 dev->mem_start = card->phys_mem
2543 + BUF_OFFSET ( txBuffer[i][0][0]);
2544 dev->mem_end = card->phys_mem
2545 + BUF_OFFSET ( txBuffer[i][NUM_TX_BUFFER][0]);
2546 dev->base_addr = card->pci_conf;
2547 dev->irq = card->irq;
2549 dev->netdev_ops = &fst_ops;
2550 dev->tx_queue_len = FST_TX_QUEUE_LEN;
2551 dev->watchdog_timeo = FST_TX_TIMEOUT;
2552 hdlc->attach = fst_attach;
2553 hdlc->xmit = fst_start_xmit;
2556 card->device = pdev;
2558 dbg(DBG_PCI, "type %d nports %d irq %d\n", card->type,
2559 card->nports, card->irq);
2560 dbg(DBG_PCI, "conf %04x mem %08x ctlmem %08x\n",
2561 card->pci_conf, card->phys_mem, card->phys_ctlmem);
2563 /* Reset the card's processor */
2565 card->state = FST_RESET;
2567 /* Initialise DMA (if required) */
2570 /* Record driver data for later use */
2571 pci_set_drvdata(pdev, card);
2573 /* Remainder of card setup */
2574 fst_card_array[no_of_cards_added] = card;
2575 card->card_no = no_of_cards_added++; /* Record instance and bump it */
2576 fst_init_card(card);
2577 if (card->family == FST_FAMILY_TXU) {
2579 * Allocate a dma buffer for transmit and receives
2581 card->rx_dma_handle_host =
2582 pci_alloc_consistent(card->device, FST_MAX_MTU,
2583 &card->rx_dma_handle_card);
2584 if (card->rx_dma_handle_host == NULL) {
2585 pr_err("Could not allocate rx dma buffer\n");
2586 fst_disable_intr(card);
2587 pci_release_regions(pdev);
2588 pci_disable_device(pdev);
2589 iounmap(card->ctlmem);
2594 card->tx_dma_handle_host =
2595 pci_alloc_consistent(card->device, FST_MAX_MTU,
2596 &card->tx_dma_handle_card);
2597 if (card->tx_dma_handle_host == NULL) {
2598 pr_err("Could not allocate tx dma buffer\n");
2599 fst_disable_intr(card);
2600 pci_release_regions(pdev);
2601 pci_disable_device(pdev);
2602 iounmap(card->ctlmem);
2608 return 0; /* Success */
2612 * Cleanup and close down a card
2614 static void __devexit
2615 fst_remove_one(struct pci_dev *pdev)
2617 struct fst_card_info *card;
2620 card = pci_get_drvdata(pdev);
2622 for (i = 0; i < card->nports; i++) {
2623 struct net_device *dev = port_to_dev(&card->ports[i]);
2624 unregister_hdlc_device(dev);
2627 fst_disable_intr(card);
2628 free_irq(card->irq, card);
2630 iounmap(card->ctlmem);
2632 pci_release_regions(pdev);
2633 if (card->family == FST_FAMILY_TXU) {
2637 pci_free_consistent(card->device, FST_MAX_MTU,
2638 card->rx_dma_handle_host,
2639 card->rx_dma_handle_card);
2640 pci_free_consistent(card->device, FST_MAX_MTU,
2641 card->tx_dma_handle_host,
2642 card->tx_dma_handle_card);
2644 fst_card_array[card->card_no] = NULL;
2647 static struct pci_driver fst_driver = {
2649 .id_table = fst_pci_dev_id,
2650 .probe = fst_add_one,
2651 .remove = __devexit_p(fst_remove_one),
2661 for (i = 0; i < FST_MAX_CARDS; i++)
2662 fst_card_array[i] = NULL;
2663 spin_lock_init(&fst_work_q_lock);
2664 return pci_register_driver(&fst_driver);
2668 fst_cleanup_module(void)
2670 pr_info("FarSync WAN driver unloading\n");
2671 pci_unregister_driver(&fst_driver);
2674 module_init(fst_init);
2675 module_exit(fst_cleanup_module);