drivers/net/wireless/ath/ath10k/hw.c

   1 /*
   2  * Copyright (c) 2014-2015 Qualcomm Atheros, Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/types.h>
  18 #include "core.h"
  19 #include "hw.h"
  20
  21 const struct ath10k_hw_regs qca988x_regs = {
  22         .rtc_state_cold_reset_mask      = 0x00000400,
  23         .rtc_soc_base_address           = 0x00004000,
  24         .rtc_wmac_base_address          = 0x00005000,
  25         .soc_core_base_address          = 0x00009000,
  26         .ce_wrapper_base_address        = 0x00057000,
  27         .ce0_base_address               = 0x00057400,
  28         .ce1_base_address               = 0x00057800,
  29         .ce2_base_address               = 0x00057c00,
  30         .ce3_base_address               = 0x00058000,
  31         .ce4_base_address               = 0x00058400,
  32         .ce5_base_address               = 0x00058800,
  33         .ce6_base_address               = 0x00058c00,
  34         .ce7_base_address               = 0x00059000,
  35         .soc_reset_control_si0_rst_mask = 0x00000001,
  36         .soc_reset_control_ce_rst_mask  = 0x00040000,
  37         .soc_chip_id_address            = 0x000000ec,
  38         .scratch_3_address              = 0x00000030,
  39         .fw_indicator_address           = 0x00009030,
  40         .pcie_local_base_address        = 0x00080000,
  41         .ce_wrap_intr_sum_host_msi_lsb  = 0x00000008,
  42         .ce_wrap_intr_sum_host_msi_mask = 0x0000ff00,
  43         .pcie_intr_fw_mask              = 0x00000400,
  44         .pcie_intr_ce_mask_all          = 0x0007f800,
  45         .pcie_intr_clr_address          = 0x00000014,
  46 };
  47
  48 const struct ath10k_hw_regs qca6174_regs = {
  49         .rtc_state_cold_reset_mask              = 0x00002000,
  50         .rtc_soc_base_address                   = 0x00000800,
  51         .rtc_wmac_base_address                  = 0x00001000,
  52         .soc_core_base_address                  = 0x0003a000,
  53         .ce_wrapper_base_address                = 0x00034000,
  54         .ce0_base_address                       = 0x00034400,
  55         .ce1_base_address                       = 0x00034800,
  56         .ce2_base_address                       = 0x00034c00,
  57         .ce3_base_address                       = 0x00035000,
  58         .ce4_base_address                       = 0x00035400,
  59         .ce5_base_address                       = 0x00035800,
  60         .ce6_base_address                       = 0x00035c00,
  61         .ce7_base_address                       = 0x00036000,
  62         .soc_reset_control_si0_rst_mask         = 0x00000000,
  63         .soc_reset_control_ce_rst_mask          = 0x00000001,
  64         .soc_chip_id_address                    = 0x000000f0,
  65         .scratch_3_address                      = 0x00000028,
  66         .fw_indicator_address                   = 0x00009028,
  67         .pcie_local_base_address                = 0x00080000,
  68         .ce_wrap_intr_sum_host_msi_lsb          = 0x00000008,
  69         .ce_wrap_intr_sum_host_msi_mask         = 0x0000ff00,
  70         .pcie_intr_fw_mask                      = 0x00000400,
  71         .pcie_intr_ce_mask_all                  = 0x0007f800,
  72         .pcie_intr_clr_address                  = 0x00000014,
  73 };
  74
  75 const struct ath10k_hw_values qca988x_values = {
  76         .rtc_state_val_on               = 3,
  77         .ce_count                       = 8,
  78         .msi_assign_ce_max              = 7,
  79         .num_target_ce_config_wlan      = 7,
  80 };
  81
  82 const struct ath10k_hw_values qca6174_values = {
  83         .rtc_state_val_on               = 3,
  84         .ce_count                       = 8,
  85         .msi_assign_ce_max              = 7,
  86         .num_target_ce_config_wlan      = 7,
  87 };
  88
  89 void ath10k_hw_fill_survey_time(struct ath10k *ar, struct survey_info *survey,
  90                                 u32 cc, u32 rcc, u32 cc_prev, u32 rcc_prev)
  91 {
  92         u32 cc_fix = 0;
  93
  94         survey->filled |= SURVEY_INFO_TIME |
  95                           SURVEY_INFO_TIME_BUSY;
  96
  97         if (ar->hw_params.has_shifted_cc_wraparound && cc < cc_prev) {
  98                 cc_fix = 0x7fffffff;
  99                 survey->filled &= ~SURVEY_INFO_TIME_BUSY;
 100         }
 101
 102         cc -= cc_prev - cc_fix;
 103         rcc -= rcc_prev;
 104
 105         survey->time = CCNT_TO_MSEC(cc);
 106         survey->time_busy = CCNT_TO_MSEC(rcc);
 107 }