2 * Copyright (c) 2005-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21 #include "targaddrs.h"
23 #define ATH10K_FW_DIR "ath10k"
25 /* QCA988X 1.0 definitions (unsupported) */
26 #define QCA988X_HW_1_0_CHIP_ID_REV 0x0
28 /* QCA988X 2.0 definitions */
29 #define QCA988X_HW_2_0_VERSION 0x4100016c
30 #define QCA988X_HW_2_0_CHIP_ID_REV 0x2
31 #define QCA988X_HW_2_0_FW_DIR ATH10K_FW_DIR "/QCA988X/hw2.0"
32 #define QCA988X_HW_2_0_FW_FILE "firmware.bin"
33 #define QCA988X_HW_2_0_OTP_FILE "otp.bin"
34 #define QCA988X_HW_2_0_BOARD_DATA_FILE "board.bin"
35 #define QCA988X_HW_2_0_PATCH_LOAD_ADDR 0x1234
37 /* QCA6174 target BMI version signatures */
38 #define QCA6174_HW_1_0_VERSION 0x05000000
39 #define QCA6174_HW_1_1_VERSION 0x05000001
40 #define QCA6174_HW_1_3_VERSION 0x05000003
41 #define QCA6174_HW_2_1_VERSION 0x05010000
42 #define QCA6174_HW_3_0_VERSION 0x05020000
43 #define QCA6174_HW_3_2_VERSION 0x05030000
45 enum qca6174_pci_rev {
46 QCA6174_PCI_REV_1_1 = 0x11,
47 QCA6174_PCI_REV_1_3 = 0x13,
48 QCA6174_PCI_REV_2_0 = 0x20,
49 QCA6174_PCI_REV_3_0 = 0x30,
52 enum qca6174_chip_id_rev {
53 QCA6174_HW_1_0_CHIP_ID_REV = 0,
54 QCA6174_HW_1_1_CHIP_ID_REV = 1,
55 QCA6174_HW_1_3_CHIP_ID_REV = 2,
56 QCA6174_HW_2_1_CHIP_ID_REV = 4,
57 QCA6174_HW_2_2_CHIP_ID_REV = 5,
58 QCA6174_HW_3_0_CHIP_ID_REV = 8,
59 QCA6174_HW_3_1_CHIP_ID_REV = 9,
60 QCA6174_HW_3_2_CHIP_ID_REV = 10,
63 #define QCA6174_HW_2_1_FW_DIR "ath10k/QCA6174/hw2.1"
64 #define QCA6174_HW_2_1_FW_FILE "firmware.bin"
65 #define QCA6174_HW_2_1_OTP_FILE "otp.bin"
66 #define QCA6174_HW_2_1_BOARD_DATA_FILE "board.bin"
67 #define QCA6174_HW_2_1_PATCH_LOAD_ADDR 0x1234
69 #define QCA6174_HW_3_0_FW_DIR "ath10k/QCA6174/hw3.0"
70 #define QCA6174_HW_3_0_FW_FILE "firmware.bin"
71 #define QCA6174_HW_3_0_OTP_FILE "otp.bin"
72 #define QCA6174_HW_3_0_BOARD_DATA_FILE "board.bin"
73 #define QCA6174_HW_3_0_PATCH_LOAD_ADDR 0x1234
75 #define ATH10K_FW_API2_FILE "firmware-2.bin"
76 #define ATH10K_FW_API3_FILE "firmware-3.bin"
78 /* added support for ATH10K_FW_IE_WMI_OP_VERSION */
79 #define ATH10K_FW_API4_FILE "firmware-4.bin"
81 /* HTT id conflict fix for management frames over HTT */
82 #define ATH10K_FW_API5_FILE "firmware-5.bin"
84 #define ATH10K_FW_UTF_FILE "utf.bin"
86 /* includes also the null byte */
87 #define ATH10K_FIRMWARE_MAGIC "QCA-ATH10K"
89 #define REG_DUMP_COUNT_QCA988X 60
91 #define QCA988X_CAL_DATA_LEN 2116
99 enum ath10k_fw_ie_type {
100 ATH10K_FW_IE_FW_VERSION = 0,
101 ATH10K_FW_IE_TIMESTAMP = 1,
102 ATH10K_FW_IE_FEATURES = 2,
103 ATH10K_FW_IE_FW_IMAGE = 3,
104 ATH10K_FW_IE_OTP_IMAGE = 4,
106 /* WMI "operations" interface version, 32 bit value. Supported from
107 * FW API 4 and above.
109 ATH10K_FW_IE_WMI_OP_VERSION = 5,
111 /* HTT "operations" interface version, 32 bit value. Supported from
112 * FW API 5 and above.
114 ATH10K_FW_IE_HTT_OP_VERSION = 6,
117 enum ath10k_fw_wmi_op_version {
118 ATH10K_FW_WMI_OP_VERSION_UNSET = 0,
120 ATH10K_FW_WMI_OP_VERSION_MAIN = 1,
121 ATH10K_FW_WMI_OP_VERSION_10_1 = 2,
122 ATH10K_FW_WMI_OP_VERSION_10_2 = 3,
123 ATH10K_FW_WMI_OP_VERSION_TLV = 4,
124 ATH10K_FW_WMI_OP_VERSION_10_2_4 = 5,
127 ATH10K_FW_WMI_OP_VERSION_MAX,
130 enum ath10k_fw_htt_op_version {
131 ATH10K_FW_HTT_OP_VERSION_UNSET = 0,
133 ATH10K_FW_HTT_OP_VERSION_MAIN = 1,
135 /* also used in 10.2 and 10.2.4 branches */
136 ATH10K_FW_HTT_OP_VERSION_10_1 = 2,
138 ATH10K_FW_HTT_OP_VERSION_TLV = 3,
141 ATH10K_FW_HTT_OP_VERSION_MAX,
149 struct ath10k_hw_regs {
150 u32 rtc_state_cold_reset_mask;
151 u32 rtc_soc_base_address;
152 u32 rtc_wmac_base_address;
153 u32 soc_core_base_address;
154 u32 ce_wrapper_base_address;
155 u32 ce0_base_address;
156 u32 ce1_base_address;
157 u32 ce2_base_address;
158 u32 ce3_base_address;
159 u32 ce4_base_address;
160 u32 ce5_base_address;
161 u32 ce6_base_address;
162 u32 ce7_base_address;
163 u32 soc_reset_control_si0_rst_mask;
164 u32 soc_reset_control_ce_rst_mask;
165 u32 soc_chip_id_address;
166 u32 scratch_3_address;
169 extern const struct ath10k_hw_regs qca988x_regs;
170 extern const struct ath10k_hw_regs qca6174_regs;
172 void ath10k_hw_fill_survey_time(struct ath10k *ar, struct survey_info *survey,
173 u32 cc, u32 rcc, u32 cc_prev, u32 rcc_prev);
175 #define QCA_REV_988X(ar) ((ar)->hw_rev == ATH10K_HW_QCA988X)
176 #define QCA_REV_6174(ar) ((ar)->hw_rev == ATH10K_HW_QCA6174)
178 /* Known pecularities:
179 * - current FW doesn't support raw rx mode (last tested v599)
180 * - current FW dumps upon raw tx mode (last tested v599)
181 * - raw appears in nwifi decap, raw and nwifi appear in ethernet decap
182 * - raw have FCS, nwifi doesn't
183 * - ethernet frames have 802.11 header decapped and parts (base hdr, cipher
184 * param, llc/snap) are aligned to 4byte boundaries each */
185 enum ath10k_hw_txrx_mode {
186 ATH10K_HW_TXRX_RAW = 0,
187 ATH10K_HW_TXRX_NATIVE_WIFI = 1,
188 ATH10K_HW_TXRX_ETHERNET = 2,
190 /* Valid for HTT >= 3.0. Used for management frames in TX_FRM. */
191 ATH10K_HW_TXRX_MGMT = 3,
194 enum ath10k_mcast2ucast_mode {
195 ATH10K_MCAST2UCAST_DISABLED = 0,
196 ATH10K_MCAST2UCAST_ENABLED = 1,
199 struct ath10k_pktlog_hdr {
208 enum ath10k_hw_rate_ofdm {
209 ATH10K_HW_RATE_OFDM_48M = 0,
210 ATH10K_HW_RATE_OFDM_24M,
211 ATH10K_HW_RATE_OFDM_12M,
212 ATH10K_HW_RATE_OFDM_6M,
213 ATH10K_HW_RATE_OFDM_54M,
214 ATH10K_HW_RATE_OFDM_36M,
215 ATH10K_HW_RATE_OFDM_18M,
216 ATH10K_HW_RATE_OFDM_9M,
219 enum ath10k_hw_rate_cck {
220 ATH10K_HW_RATE_CCK_LP_11M = 0,
221 ATH10K_HW_RATE_CCK_LP_5_5M,
222 ATH10K_HW_RATE_CCK_LP_2M,
223 ATH10K_HW_RATE_CCK_LP_1M,
224 ATH10K_HW_RATE_CCK_SP_11M,
225 ATH10K_HW_RATE_CCK_SP_5_5M,
226 ATH10K_HW_RATE_CCK_SP_2M,
229 /* Target specific defines for MAIN firmware */
230 #define TARGET_NUM_VDEVS 8
231 #define TARGET_NUM_PEER_AST 2
232 #define TARGET_NUM_WDS_ENTRIES 32
233 #define TARGET_DMA_BURST_SIZE 0
234 #define TARGET_MAC_AGGR_DELIM 0
235 #define TARGET_AST_SKID_LIMIT 16
236 #define TARGET_NUM_STATIONS 16
237 #define TARGET_NUM_PEERS ((TARGET_NUM_STATIONS) + \
239 #define TARGET_NUM_OFFLOAD_PEERS 0
240 #define TARGET_NUM_OFFLOAD_REORDER_BUFS 0
241 #define TARGET_NUM_PEER_KEYS 2
242 #define TARGET_NUM_TIDS ((TARGET_NUM_PEERS) * 2)
243 #define TARGET_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2))
244 #define TARGET_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2))
245 #define TARGET_RX_TIMEOUT_LO_PRI 100
246 #define TARGET_RX_TIMEOUT_HI_PRI 40
248 /* Native Wifi decap mode is used to align IP frames to 4-byte boundaries and
249 * avoid a very expensive re-alignment in mac80211. */
250 #define TARGET_RX_DECAP_MODE ATH10K_HW_TXRX_NATIVE_WIFI
252 #define TARGET_SCAN_MAX_PENDING_REQS 4
253 #define TARGET_BMISS_OFFLOAD_MAX_VDEV 3
254 #define TARGET_ROAM_OFFLOAD_MAX_VDEV 3
255 #define TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES 8
256 #define TARGET_GTK_OFFLOAD_MAX_VDEV 3
257 #define TARGET_NUM_MCAST_GROUPS 0
258 #define TARGET_NUM_MCAST_TABLE_ELEMS 0
259 #define TARGET_MCAST2UCAST_MODE ATH10K_MCAST2UCAST_DISABLED
260 #define TARGET_TX_DBG_LOG_SIZE 1024
261 #define TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 0
262 #define TARGET_VOW_CONFIG 0
263 #define TARGET_NUM_MSDU_DESC (1024 + 400)
264 #define TARGET_MAX_FRAG_ENTRIES 0
266 /* Target specific defines for 10.X firmware */
267 #define TARGET_10X_NUM_VDEVS 16
268 #define TARGET_10X_NUM_PEER_AST 2
269 #define TARGET_10X_NUM_WDS_ENTRIES 32
270 #define TARGET_10X_DMA_BURST_SIZE 0
271 #define TARGET_10X_MAC_AGGR_DELIM 0
272 #define TARGET_10X_AST_SKID_LIMIT 128
273 #define TARGET_10X_NUM_STATIONS 128
274 #define TARGET_10X_NUM_PEERS ((TARGET_10X_NUM_STATIONS) + \
275 (TARGET_10X_NUM_VDEVS))
276 #define TARGET_10X_NUM_OFFLOAD_PEERS 0
277 #define TARGET_10X_NUM_OFFLOAD_REORDER_BUFS 0
278 #define TARGET_10X_NUM_PEER_KEYS 2
279 #define TARGET_10X_NUM_TIDS_MAX 256
280 #define TARGET_10X_NUM_TIDS min((TARGET_10X_NUM_TIDS_MAX), \
281 (TARGET_10X_NUM_PEERS) * 2)
282 #define TARGET_10X_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2))
283 #define TARGET_10X_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2))
284 #define TARGET_10X_RX_TIMEOUT_LO_PRI 100
285 #define TARGET_10X_RX_TIMEOUT_HI_PRI 40
286 #define TARGET_10X_RX_DECAP_MODE ATH10K_HW_TXRX_NATIVE_WIFI
287 #define TARGET_10X_SCAN_MAX_PENDING_REQS 4
288 #define TARGET_10X_BMISS_OFFLOAD_MAX_VDEV 2
289 #define TARGET_10X_ROAM_OFFLOAD_MAX_VDEV 2
290 #define TARGET_10X_ROAM_OFFLOAD_MAX_AP_PROFILES 8
291 #define TARGET_10X_GTK_OFFLOAD_MAX_VDEV 3
292 #define TARGET_10X_NUM_MCAST_GROUPS 0
293 #define TARGET_10X_NUM_MCAST_TABLE_ELEMS 0
294 #define TARGET_10X_MCAST2UCAST_MODE ATH10K_MCAST2UCAST_DISABLED
295 #define TARGET_10X_TX_DBG_LOG_SIZE 1024
296 #define TARGET_10X_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1
297 #define TARGET_10X_VOW_CONFIG 0
298 #define TARGET_10X_NUM_MSDU_DESC (1024 + 400)
299 #define TARGET_10X_MAX_FRAG_ENTRIES 0
301 /* 10.2 parameters */
302 #define TARGET_10_2_DMA_BURST_SIZE 1
304 /* Target specific defines for WMI-TLV firmware */
305 #define TARGET_TLV_NUM_VDEVS 4
306 #define TARGET_TLV_NUM_STATIONS 32
307 #define TARGET_TLV_NUM_PEERS 35
308 #define TARGET_TLV_NUM_TDLS_VDEVS 1
309 #define TARGET_TLV_NUM_TIDS ((TARGET_TLV_NUM_PEERS) * 2)
310 #define TARGET_TLV_NUM_MSDU_DESC (1024 + 32)
311 #define TARGET_TLV_NUM_WOW_PATTERNS 22
313 /* Number of Copy Engines supported */
317 * Total number of PCIe MSI interrupts requested for all interrupt sources.
318 * PCIe standard forces this to be a power of 2.
319 * Some Host OS's limit MSI requests that can be granted to 8
320 * so for now we abide by this limit and avoid requesting more
323 #define MSI_NUM_REQUEST_LOG2 3
324 #define MSI_NUM_REQUEST (1<<MSI_NUM_REQUEST_LOG2)
327 * Granted MSIs are assigned as follows:
328 * Firmware uses the first
329 * Remaining MSIs, if any, are used by Copy Engines
330 * This mapping is known to both Target firmware and Host software.
331 * It may be changed as long as Host and Target are kept in sync.
333 /* MSI for firmware (errors, etc.) */
334 #define MSI_ASSIGN_FW 0
336 /* MSIs for Copy Engines */
337 #define MSI_ASSIGN_CE_INITIAL 1
338 #define MSI_ASSIGN_CE_MAX 7
341 #define RTC_STATE_V_ON 3
343 #define RTC_STATE_COLD_RESET_MASK ar->regs->rtc_state_cold_reset_mask
344 #define RTC_STATE_V_LSB 0
345 #define RTC_STATE_V_MASK 0x00000007
346 #define RTC_STATE_ADDRESS 0x0000
347 #define PCIE_SOC_WAKE_V_MASK 0x00000001
348 #define PCIE_SOC_WAKE_ADDRESS 0x0004
349 #define PCIE_SOC_WAKE_RESET 0x00000000
350 #define SOC_GLOBAL_RESET_ADDRESS 0x0008
352 #define RTC_SOC_BASE_ADDRESS ar->regs->rtc_soc_base_address
353 #define RTC_WMAC_BASE_ADDRESS ar->regs->rtc_wmac_base_address
354 #define MAC_COEX_BASE_ADDRESS 0x00006000
355 #define BT_COEX_BASE_ADDRESS 0x00007000
356 #define SOC_PCIE_BASE_ADDRESS 0x00008000
357 #define SOC_CORE_BASE_ADDRESS ar->regs->soc_core_base_address
358 #define WLAN_UART_BASE_ADDRESS 0x0000c000
359 #define WLAN_SI_BASE_ADDRESS 0x00010000
360 #define WLAN_GPIO_BASE_ADDRESS 0x00014000
361 #define WLAN_ANALOG_INTF_BASE_ADDRESS 0x0001c000
362 #define WLAN_MAC_BASE_ADDRESS 0x00020000
363 #define EFUSE_BASE_ADDRESS 0x00030000
364 #define FPGA_REG_BASE_ADDRESS 0x00039000
365 #define WLAN_UART2_BASE_ADDRESS 0x00054c00
366 #define CE_WRAPPER_BASE_ADDRESS ar->regs->ce_wrapper_base_address
367 #define CE0_BASE_ADDRESS ar->regs->ce0_base_address
368 #define CE1_BASE_ADDRESS ar->regs->ce1_base_address
369 #define CE2_BASE_ADDRESS ar->regs->ce2_base_address
370 #define CE3_BASE_ADDRESS ar->regs->ce3_base_address
371 #define CE4_BASE_ADDRESS ar->regs->ce4_base_address
372 #define CE5_BASE_ADDRESS ar->regs->ce5_base_address
373 #define CE6_BASE_ADDRESS ar->regs->ce6_base_address
374 #define CE7_BASE_ADDRESS ar->regs->ce7_base_address
375 #define DBI_BASE_ADDRESS 0x00060000
376 #define WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS 0x0006c000
377 #define PCIE_LOCAL_BASE_ADDRESS 0x00080000
379 #define SOC_RESET_CONTROL_ADDRESS 0x00000000
380 #define SOC_RESET_CONTROL_OFFSET 0x00000000
381 #define SOC_RESET_CONTROL_SI0_RST_MASK ar->regs->soc_reset_control_si0_rst_mask
382 #define SOC_RESET_CONTROL_CE_RST_MASK ar->regs->soc_reset_control_ce_rst_mask
383 #define SOC_RESET_CONTROL_CPU_WARM_RST_MASK 0x00000040
384 #define SOC_CPU_CLOCK_OFFSET 0x00000020
385 #define SOC_CPU_CLOCK_STANDARD_LSB 0
386 #define SOC_CPU_CLOCK_STANDARD_MASK 0x00000003
387 #define SOC_CLOCK_CONTROL_OFFSET 0x00000028
388 #define SOC_CLOCK_CONTROL_SI0_CLK_MASK 0x00000001
389 #define SOC_SYSTEM_SLEEP_OFFSET 0x000000c4
390 #define SOC_LPO_CAL_OFFSET 0x000000e0
391 #define SOC_LPO_CAL_ENABLE_LSB 20
392 #define SOC_LPO_CAL_ENABLE_MASK 0x00100000
393 #define SOC_LF_TIMER_CONTROL0_ADDRESS 0x00000050
394 #define SOC_LF_TIMER_CONTROL0_ENABLE_MASK 0x00000004
396 #define SOC_CHIP_ID_ADDRESS ar->regs->soc_chip_id_address
397 #define SOC_CHIP_ID_REV_LSB 8
398 #define SOC_CHIP_ID_REV_MASK 0x00000f00
400 #define WLAN_RESET_CONTROL_COLD_RST_MASK 0x00000008
401 #define WLAN_RESET_CONTROL_WARM_RST_MASK 0x00000004
402 #define WLAN_SYSTEM_SLEEP_DISABLE_LSB 0
403 #define WLAN_SYSTEM_SLEEP_DISABLE_MASK 0x00000001
405 #define WLAN_GPIO_PIN0_ADDRESS 0x00000028
406 #define WLAN_GPIO_PIN0_CONFIG_MASK 0x00007800
407 #define WLAN_GPIO_PIN1_ADDRESS 0x0000002c
408 #define WLAN_GPIO_PIN1_CONFIG_MASK 0x00007800
409 #define WLAN_GPIO_PIN10_ADDRESS 0x00000050
410 #define WLAN_GPIO_PIN11_ADDRESS 0x00000054
411 #define WLAN_GPIO_PIN12_ADDRESS 0x00000058
412 #define WLAN_GPIO_PIN13_ADDRESS 0x0000005c
414 #define CLOCK_GPIO_OFFSET 0xffffffff
415 #define CLOCK_GPIO_BT_CLK_OUT_EN_LSB 0
416 #define CLOCK_GPIO_BT_CLK_OUT_EN_MASK 0
418 #define SI_CONFIG_OFFSET 0x00000000
419 #define SI_CONFIG_BIDIR_OD_DATA_LSB 18
420 #define SI_CONFIG_BIDIR_OD_DATA_MASK 0x00040000
421 #define SI_CONFIG_I2C_LSB 16
422 #define SI_CONFIG_I2C_MASK 0x00010000
423 #define SI_CONFIG_POS_SAMPLE_LSB 7
424 #define SI_CONFIG_POS_SAMPLE_MASK 0x00000080
425 #define SI_CONFIG_INACTIVE_DATA_LSB 5
426 #define SI_CONFIG_INACTIVE_DATA_MASK 0x00000020
427 #define SI_CONFIG_INACTIVE_CLK_LSB 4
428 #define SI_CONFIG_INACTIVE_CLK_MASK 0x00000010
429 #define SI_CONFIG_DIVIDER_LSB 0
430 #define SI_CONFIG_DIVIDER_MASK 0x0000000f
431 #define SI_CS_OFFSET 0x00000004
432 #define SI_CS_DONE_ERR_MASK 0x00000400
433 #define SI_CS_DONE_INT_MASK 0x00000200
434 #define SI_CS_START_LSB 8
435 #define SI_CS_START_MASK 0x00000100
436 #define SI_CS_RX_CNT_LSB 4
437 #define SI_CS_RX_CNT_MASK 0x000000f0
438 #define SI_CS_TX_CNT_LSB 0
439 #define SI_CS_TX_CNT_MASK 0x0000000f
441 #define SI_TX_DATA0_OFFSET 0x00000008
442 #define SI_TX_DATA1_OFFSET 0x0000000c
443 #define SI_RX_DATA0_OFFSET 0x00000010
444 #define SI_RX_DATA1_OFFSET 0x00000014
446 #define CORE_CTRL_CPU_INTR_MASK 0x00002000
447 #define CORE_CTRL_PCIE_REG_31_MASK 0x00000800
448 #define CORE_CTRL_ADDRESS 0x0000
449 #define PCIE_INTR_ENABLE_ADDRESS 0x0008
450 #define PCIE_INTR_CAUSE_ADDRESS 0x000c
451 #define PCIE_INTR_CLR_ADDRESS 0x0014
452 #define SCRATCH_3_ADDRESS ar->regs->scratch_3_address
453 #define CPU_INTR_ADDRESS 0x0010
455 /* Cycle counters are running at 88MHz */
456 #define CCNT_TO_MSEC(x) ((x) / 88000)
458 /* Firmware indications to the Host via SCRATCH_3 register. */
459 #define FW_INDICATOR_ADDRESS (SOC_CORE_BASE_ADDRESS + SCRATCH_3_ADDRESS)
460 #define FW_IND_EVENT_PENDING 1
461 #define FW_IND_INITIALIZED 2
463 /* HOST_REG interrupt from firmware */
464 #define PCIE_INTR_FIRMWARE_MASK 0x00000400
465 #define PCIE_INTR_CE_MASK_ALL 0x0007f800
467 #define DRAM_BASE_ADDRESS 0x00400000
471 #define SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET
472 #define WLAN_SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET
473 #define WLAN_RESET_CONTROL_OFFSET SOC_RESET_CONTROL_OFFSET
474 #define CLOCK_CONTROL_OFFSET SOC_CLOCK_CONTROL_OFFSET
475 #define CLOCK_CONTROL_SI0_CLK_MASK SOC_CLOCK_CONTROL_SI0_CLK_MASK
476 #define RESET_CONTROL_MBOX_RST_MASK MISSING
477 #define RESET_CONTROL_SI0_RST_MASK SOC_RESET_CONTROL_SI0_RST_MASK
478 #define GPIO_BASE_ADDRESS WLAN_GPIO_BASE_ADDRESS
479 #define GPIO_PIN0_OFFSET WLAN_GPIO_PIN0_ADDRESS
480 #define GPIO_PIN1_OFFSET WLAN_GPIO_PIN1_ADDRESS
481 #define GPIO_PIN0_CONFIG_MASK WLAN_GPIO_PIN0_CONFIG_MASK
482 #define GPIO_PIN1_CONFIG_MASK WLAN_GPIO_PIN1_CONFIG_MASK
483 #define SI_BASE_ADDRESS WLAN_SI_BASE_ADDRESS
484 #define SCRATCH_BASE_ADDRESS SOC_CORE_BASE_ADDRESS
485 #define LOCAL_SCRATCH_OFFSET 0x18
486 #define CPU_CLOCK_OFFSET SOC_CPU_CLOCK_OFFSET
487 #define LPO_CAL_OFFSET SOC_LPO_CAL_OFFSET
488 #define GPIO_PIN10_OFFSET WLAN_GPIO_PIN10_ADDRESS
489 #define GPIO_PIN11_OFFSET WLAN_GPIO_PIN11_ADDRESS
490 #define GPIO_PIN12_OFFSET WLAN_GPIO_PIN12_ADDRESS
491 #define GPIO_PIN13_OFFSET WLAN_GPIO_PIN13_ADDRESS
492 #define CPU_CLOCK_STANDARD_LSB SOC_CPU_CLOCK_STANDARD_LSB
493 #define CPU_CLOCK_STANDARD_MASK SOC_CPU_CLOCK_STANDARD_MASK
494 #define LPO_CAL_ENABLE_LSB SOC_LPO_CAL_ENABLE_LSB
495 #define LPO_CAL_ENABLE_MASK SOC_LPO_CAL_ENABLE_MASK
496 #define ANALOG_INTF_BASE_ADDRESS WLAN_ANALOG_INTF_BASE_ADDRESS
497 #define MBOX_BASE_ADDRESS MISSING
498 #define INT_STATUS_ENABLE_ERROR_LSB MISSING
499 #define INT_STATUS_ENABLE_ERROR_MASK MISSING
500 #define INT_STATUS_ENABLE_CPU_LSB MISSING
501 #define INT_STATUS_ENABLE_CPU_MASK MISSING
502 #define INT_STATUS_ENABLE_COUNTER_LSB MISSING
503 #define INT_STATUS_ENABLE_COUNTER_MASK MISSING
504 #define INT_STATUS_ENABLE_MBOX_DATA_LSB MISSING
505 #define INT_STATUS_ENABLE_MBOX_DATA_MASK MISSING
506 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB MISSING
507 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK MISSING
508 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB MISSING
509 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK MISSING
510 #define COUNTER_INT_STATUS_ENABLE_BIT_LSB MISSING
511 #define COUNTER_INT_STATUS_ENABLE_BIT_MASK MISSING
512 #define INT_STATUS_ENABLE_ADDRESS MISSING
513 #define CPU_INT_STATUS_ENABLE_BIT_LSB MISSING
514 #define CPU_INT_STATUS_ENABLE_BIT_MASK MISSING
515 #define HOST_INT_STATUS_ADDRESS MISSING
516 #define CPU_INT_STATUS_ADDRESS MISSING
517 #define ERROR_INT_STATUS_ADDRESS MISSING
518 #define ERROR_INT_STATUS_WAKEUP_MASK MISSING
519 #define ERROR_INT_STATUS_WAKEUP_LSB MISSING
520 #define ERROR_INT_STATUS_RX_UNDERFLOW_MASK MISSING
521 #define ERROR_INT_STATUS_RX_UNDERFLOW_LSB MISSING
522 #define ERROR_INT_STATUS_TX_OVERFLOW_MASK MISSING
523 #define ERROR_INT_STATUS_TX_OVERFLOW_LSB MISSING
524 #define COUNT_DEC_ADDRESS MISSING
525 #define HOST_INT_STATUS_CPU_MASK MISSING
526 #define HOST_INT_STATUS_CPU_LSB MISSING
527 #define HOST_INT_STATUS_ERROR_MASK MISSING
528 #define HOST_INT_STATUS_ERROR_LSB MISSING
529 #define HOST_INT_STATUS_COUNTER_MASK MISSING
530 #define HOST_INT_STATUS_COUNTER_LSB MISSING
531 #define RX_LOOKAHEAD_VALID_ADDRESS MISSING
532 #define WINDOW_DATA_ADDRESS MISSING
533 #define WINDOW_READ_ADDR_ADDRESS MISSING
534 #define WINDOW_WRITE_ADDR_ADDRESS MISSING
536 #define RTC_STATE_V_GET(x) (((x) & RTC_STATE_V_MASK) >> RTC_STATE_V_LSB)