2 * Copyright (c) 2005-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include <linux/pci.h>
19 #include <linux/module.h>
20 #include <linux/interrupt.h>
21 #include <linux/spinlock.h>
22 #include <linux/bitops.h>
27 #include "targaddrs.h"
36 enum ath10k_pci_irq_mode {
37 ATH10K_PCI_IRQ_AUTO = 0,
38 ATH10K_PCI_IRQ_LEGACY = 1,
39 ATH10K_PCI_IRQ_MSI = 2,
42 enum ath10k_pci_reset_mode {
43 ATH10K_PCI_RESET_AUTO = 0,
44 ATH10K_PCI_RESET_WARM_ONLY = 1,
47 static unsigned int ath10k_pci_irq_mode = ATH10K_PCI_IRQ_AUTO;
48 static unsigned int ath10k_pci_reset_mode = ATH10K_PCI_RESET_AUTO;
50 module_param_named(irq_mode, ath10k_pci_irq_mode, uint, 0644);
51 MODULE_PARM_DESC(irq_mode, "0: auto, 1: legacy, 2: msi (default: 0)");
53 module_param_named(reset_mode, ath10k_pci_reset_mode, uint, 0644);
54 MODULE_PARM_DESC(reset_mode, "0: auto, 1: warm only (default: 0)");
56 /* how long wait to wait for target to initialise, in ms */
57 #define ATH10K_PCI_TARGET_WAIT 3000
58 #define ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS 3
60 #define QCA988X_2_0_DEVICE_ID (0x003c)
61 #define QCA6164_2_1_DEVICE_ID (0x0041)
62 #define QCA6174_2_1_DEVICE_ID (0x003e)
63 #define QCA99X0_2_0_DEVICE_ID (0x0040)
65 static const struct pci_device_id ath10k_pci_id_table[] = {
66 { PCI_VDEVICE(ATHEROS, QCA988X_2_0_DEVICE_ID) }, /* PCI-E QCA988X V2 */
67 { PCI_VDEVICE(ATHEROS, QCA6164_2_1_DEVICE_ID) }, /* PCI-E QCA6164 V2.1 */
68 { PCI_VDEVICE(ATHEROS, QCA6174_2_1_DEVICE_ID) }, /* PCI-E QCA6174 V2.1 */
69 { PCI_VDEVICE(ATHEROS, QCA99X0_2_0_DEVICE_ID) }, /* PCI-E QCA99X0 V2 */
73 static const struct ath10k_pci_supp_chip ath10k_pci_supp_chips[] = {
74 /* QCA988X pre 2.0 chips are not supported because they need some nasty
75 * hacks. ath10k doesn't have them and these devices crash horribly
78 { QCA988X_2_0_DEVICE_ID, QCA988X_HW_2_0_CHIP_ID_REV },
80 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_2_1_CHIP_ID_REV },
81 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_2_2_CHIP_ID_REV },
82 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_3_0_CHIP_ID_REV },
83 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_3_1_CHIP_ID_REV },
84 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_3_2_CHIP_ID_REV },
86 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_2_1_CHIP_ID_REV },
87 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_2_2_CHIP_ID_REV },
88 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_0_CHIP_ID_REV },
89 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_1_CHIP_ID_REV },
90 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_2_CHIP_ID_REV },
92 { QCA99X0_2_0_DEVICE_ID, QCA99X0_HW_2_0_CHIP_ID_REV },
95 static void ath10k_pci_buffer_cleanup(struct ath10k *ar);
96 static int ath10k_pci_cold_reset(struct ath10k *ar);
97 static int ath10k_pci_safe_chip_reset(struct ath10k *ar);
98 static int ath10k_pci_wait_for_target_init(struct ath10k *ar);
99 static int ath10k_pci_init_irq(struct ath10k *ar);
100 static int ath10k_pci_deinit_irq(struct ath10k *ar);
101 static int ath10k_pci_request_irq(struct ath10k *ar);
102 static void ath10k_pci_free_irq(struct ath10k *ar);
103 static int ath10k_pci_bmi_wait(struct ath10k_ce_pipe *tx_pipe,
104 struct ath10k_ce_pipe *rx_pipe,
105 struct bmi_xfer *xfer);
106 static int ath10k_pci_qca99x0_chip_reset(struct ath10k *ar);
108 static const struct ce_attr host_ce_config_wlan[] = {
109 /* CE0: host->target HTC control and raw streams */
111 .flags = CE_ATTR_FLAGS,
117 /* CE1: target->host HTT + HTC control */
119 .flags = CE_ATTR_FLAGS,
122 .dest_nentries = 512,
125 /* CE2: target->host WMI */
127 .flags = CE_ATTR_FLAGS,
130 .dest_nentries = 128,
133 /* CE3: host->target WMI */
135 .flags = CE_ATTR_FLAGS,
141 /* CE4: host->target HTT */
143 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
144 .src_nentries = CE_HTT_H2T_MSG_SRC_NENTRIES,
151 .flags = CE_ATTR_FLAGS,
157 /* CE6: target autonomous hif_memcpy */
159 .flags = CE_ATTR_FLAGS,
165 /* CE7: ce_diag, the Diagnostic Window */
167 .flags = CE_ATTR_FLAGS,
169 .src_sz_max = DIAG_TRANSFER_LIMIT,
173 /* CE8: target->host pktlog */
175 .flags = CE_ATTR_FLAGS,
178 .dest_nentries = 128,
181 /* CE9 target autonomous qcache memcpy */
183 .flags = CE_ATTR_FLAGS,
189 /* CE10: target autonomous hif memcpy */
191 .flags = CE_ATTR_FLAGS,
197 /* CE11: target autonomous hif memcpy */
199 .flags = CE_ATTR_FLAGS,
206 /* Target firmware's Copy Engine configuration. */
207 static const struct ce_pipe_config target_ce_config_wlan[] = {
208 /* CE0: host->target HTC control and raw streams */
210 .pipenum = __cpu_to_le32(0),
211 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
212 .nentries = __cpu_to_le32(32),
213 .nbytes_max = __cpu_to_le32(256),
214 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
215 .reserved = __cpu_to_le32(0),
218 /* CE1: target->host HTT + HTC control */
220 .pipenum = __cpu_to_le32(1),
221 .pipedir = __cpu_to_le32(PIPEDIR_IN),
222 .nentries = __cpu_to_le32(32),
223 .nbytes_max = __cpu_to_le32(2048),
224 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
225 .reserved = __cpu_to_le32(0),
228 /* CE2: target->host WMI */
230 .pipenum = __cpu_to_le32(2),
231 .pipedir = __cpu_to_le32(PIPEDIR_IN),
232 .nentries = __cpu_to_le32(64),
233 .nbytes_max = __cpu_to_le32(2048),
234 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
235 .reserved = __cpu_to_le32(0),
238 /* CE3: host->target WMI */
240 .pipenum = __cpu_to_le32(3),
241 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
242 .nentries = __cpu_to_le32(32),
243 .nbytes_max = __cpu_to_le32(2048),
244 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
245 .reserved = __cpu_to_le32(0),
248 /* CE4: host->target HTT */
250 .pipenum = __cpu_to_le32(4),
251 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
252 .nentries = __cpu_to_le32(256),
253 .nbytes_max = __cpu_to_le32(256),
254 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
255 .reserved = __cpu_to_le32(0),
258 /* NB: 50% of src nentries, since tx has 2 frags */
262 .pipenum = __cpu_to_le32(5),
263 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
264 .nentries = __cpu_to_le32(32),
265 .nbytes_max = __cpu_to_le32(2048),
266 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
267 .reserved = __cpu_to_le32(0),
270 /* CE6: Reserved for target autonomous hif_memcpy */
272 .pipenum = __cpu_to_le32(6),
273 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
274 .nentries = __cpu_to_le32(32),
275 .nbytes_max = __cpu_to_le32(4096),
276 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
277 .reserved = __cpu_to_le32(0),
280 /* CE7 used only by Host */
282 .pipenum = __cpu_to_le32(7),
283 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
284 .nentries = __cpu_to_le32(0),
285 .nbytes_max = __cpu_to_le32(0),
286 .flags = __cpu_to_le32(0),
287 .reserved = __cpu_to_le32(0),
290 /* CE8 target->host packtlog */
292 .pipenum = __cpu_to_le32(8),
293 .pipedir = __cpu_to_le32(PIPEDIR_IN),
294 .nentries = __cpu_to_le32(64),
295 .nbytes_max = __cpu_to_le32(2048),
296 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
297 .reserved = __cpu_to_le32(0),
300 /* CE9 target autonomous qcache memcpy */
302 .pipenum = __cpu_to_le32(9),
303 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
304 .nentries = __cpu_to_le32(32),
305 .nbytes_max = __cpu_to_le32(2048),
306 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
307 .reserved = __cpu_to_le32(0),
310 /* It not necessary to send target wlan configuration for CE10 & CE11
311 * as these CEs are not actively used in target.
316 * Map from service/endpoint to Copy Engine.
317 * This table is derived from the CE_PCI TABLE, above.
318 * It is passed to the Target at startup for use by firmware.
320 static const struct service_to_pipe target_service_to_ce_map_wlan[] = {
322 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO),
323 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
327 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO),
328 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
332 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK),
333 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
337 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK),
338 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
342 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE),
343 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
347 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE),
348 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
352 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI),
353 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
357 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI),
358 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
362 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL),
363 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
367 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL),
368 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
372 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL),
373 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
377 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL),
378 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
382 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS),
383 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
387 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS),
388 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
392 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG),
393 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
397 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG),
398 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
402 /* (Additions here) */
411 static bool ath10k_pci_is_awake(struct ath10k *ar)
413 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
414 u32 val = ioread32(ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
417 return RTC_STATE_V_GET(val) == RTC_STATE_V_ON;
420 static void __ath10k_pci_wake(struct ath10k *ar)
422 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
424 lockdep_assert_held(&ar_pci->ps_lock);
426 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps wake reg refcount %lu awake %d\n",
427 ar_pci->ps_wake_refcount, ar_pci->ps_awake);
429 iowrite32(PCIE_SOC_WAKE_V_MASK,
430 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
431 PCIE_SOC_WAKE_ADDRESS);
434 static void __ath10k_pci_sleep(struct ath10k *ar)
436 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
438 lockdep_assert_held(&ar_pci->ps_lock);
440 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps sleep reg refcount %lu awake %d\n",
441 ar_pci->ps_wake_refcount, ar_pci->ps_awake);
443 iowrite32(PCIE_SOC_WAKE_RESET,
444 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
445 PCIE_SOC_WAKE_ADDRESS);
446 ar_pci->ps_awake = false;
449 static int ath10k_pci_wake_wait(struct ath10k *ar)
454 while (tot_delay < PCIE_WAKE_TIMEOUT) {
455 if (ath10k_pci_is_awake(ar))
459 tot_delay += curr_delay;
468 static int ath10k_pci_wake(struct ath10k *ar)
470 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
474 spin_lock_irqsave(&ar_pci->ps_lock, flags);
476 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps wake refcount %lu awake %d\n",
477 ar_pci->ps_wake_refcount, ar_pci->ps_awake);
479 /* This function can be called very frequently. To avoid excessive
480 * CPU stalls for MMIO reads use a cache var to hold the device state.
482 if (!ar_pci->ps_awake) {
483 __ath10k_pci_wake(ar);
485 ret = ath10k_pci_wake_wait(ar);
487 ar_pci->ps_awake = true;
491 ar_pci->ps_wake_refcount++;
492 WARN_ON(ar_pci->ps_wake_refcount == 0);
495 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
500 static void ath10k_pci_sleep(struct ath10k *ar)
502 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
505 spin_lock_irqsave(&ar_pci->ps_lock, flags);
507 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps sleep refcount %lu awake %d\n",
508 ar_pci->ps_wake_refcount, ar_pci->ps_awake);
510 if (WARN_ON(ar_pci->ps_wake_refcount == 0))
513 ar_pci->ps_wake_refcount--;
515 mod_timer(&ar_pci->ps_timer, jiffies +
516 msecs_to_jiffies(ATH10K_PCI_SLEEP_GRACE_PERIOD_MSEC));
519 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
522 static void ath10k_pci_ps_timer(unsigned long ptr)
524 struct ath10k *ar = (void *)ptr;
525 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
528 spin_lock_irqsave(&ar_pci->ps_lock, flags);
530 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps timer refcount %lu awake %d\n",
531 ar_pci->ps_wake_refcount, ar_pci->ps_awake);
533 if (ar_pci->ps_wake_refcount > 0)
536 __ath10k_pci_sleep(ar);
539 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
542 static void ath10k_pci_sleep_sync(struct ath10k *ar)
544 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
547 del_timer_sync(&ar_pci->ps_timer);
549 spin_lock_irqsave(&ar_pci->ps_lock, flags);
550 WARN_ON(ar_pci->ps_wake_refcount > 0);
551 __ath10k_pci_sleep(ar);
552 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
555 void ath10k_pci_write32(struct ath10k *ar, u32 offset, u32 value)
557 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
560 if (unlikely(offset + sizeof(value) > ar_pci->mem_len)) {
561 ath10k_warn(ar, "refusing to write mmio out of bounds at 0x%08x - 0x%08zx (max 0x%08zx)\n",
562 offset, offset + sizeof(value), ar_pci->mem_len);
566 ret = ath10k_pci_wake(ar);
568 ath10k_warn(ar, "failed to wake target for write32 of 0x%08x at 0x%08x: %d\n",
573 iowrite32(value, ar_pci->mem + offset);
574 ath10k_pci_sleep(ar);
577 u32 ath10k_pci_read32(struct ath10k *ar, u32 offset)
579 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
583 if (unlikely(offset + sizeof(val) > ar_pci->mem_len)) {
584 ath10k_warn(ar, "refusing to read mmio out of bounds at 0x%08x - 0x%08zx (max 0x%08zx)\n",
585 offset, offset + sizeof(val), ar_pci->mem_len);
589 ret = ath10k_pci_wake(ar);
591 ath10k_warn(ar, "failed to wake target for read32 at 0x%08x: %d\n",
596 val = ioread32(ar_pci->mem + offset);
597 ath10k_pci_sleep(ar);
602 u32 ath10k_pci_soc_read32(struct ath10k *ar, u32 addr)
604 return ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS + addr);
607 void ath10k_pci_soc_write32(struct ath10k *ar, u32 addr, u32 val)
609 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + addr, val);
612 u32 ath10k_pci_reg_read32(struct ath10k *ar, u32 addr)
614 return ath10k_pci_read32(ar, PCIE_LOCAL_BASE_ADDRESS + addr);
617 void ath10k_pci_reg_write32(struct ath10k *ar, u32 addr, u32 val)
619 ath10k_pci_write32(ar, PCIE_LOCAL_BASE_ADDRESS + addr, val);
622 static bool ath10k_pci_irq_pending(struct ath10k *ar)
626 /* Check if the shared legacy irq is for us */
627 cause = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
628 PCIE_INTR_CAUSE_ADDRESS);
629 if (cause & (PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL))
635 static void ath10k_pci_disable_and_clear_legacy_irq(struct ath10k *ar)
637 /* IMPORTANT: INTR_CLR register has to be set after
638 * INTR_ENABLE is set to 0, otherwise interrupt can not be
640 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,
642 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_CLR_ADDRESS,
643 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL);
645 /* IMPORTANT: this extra read transaction is required to
646 * flush the posted write buffer. */
647 (void)ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
648 PCIE_INTR_ENABLE_ADDRESS);
651 static void ath10k_pci_enable_legacy_irq(struct ath10k *ar)
653 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
654 PCIE_INTR_ENABLE_ADDRESS,
655 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL);
657 /* IMPORTANT: this extra read transaction is required to
658 * flush the posted write buffer. */
659 (void)ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
660 PCIE_INTR_ENABLE_ADDRESS);
663 static inline const char *ath10k_pci_get_irq_method(struct ath10k *ar)
665 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
667 if (ar_pci->num_msi_intrs > 1)
670 if (ar_pci->num_msi_intrs == 1)
676 static int __ath10k_pci_rx_post_buf(struct ath10k_pci_pipe *pipe)
678 struct ath10k *ar = pipe->hif_ce_state;
679 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
680 struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl;
685 lockdep_assert_held(&ar_pci->ce_lock);
687 skb = dev_alloc_skb(pipe->buf_sz);
691 WARN_ONCE((unsigned long)skb->data & 3, "unaligned skb");
693 paddr = dma_map_single(ar->dev, skb->data,
694 skb->len + skb_tailroom(skb),
696 if (unlikely(dma_mapping_error(ar->dev, paddr))) {
697 ath10k_warn(ar, "failed to dma map pci rx buf\n");
698 dev_kfree_skb_any(skb);
702 ATH10K_SKB_RXCB(skb)->paddr = paddr;
704 ret = __ath10k_ce_rx_post_buf(ce_pipe, skb, paddr);
706 ath10k_warn(ar, "failed to post pci rx buf: %d\n", ret);
707 dma_unmap_single(ar->dev, paddr, skb->len + skb_tailroom(skb),
709 dev_kfree_skb_any(skb);
716 static void __ath10k_pci_rx_post_pipe(struct ath10k_pci_pipe *pipe)
718 struct ath10k *ar = pipe->hif_ce_state;
719 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
720 struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl;
723 lockdep_assert_held(&ar_pci->ce_lock);
725 if (pipe->buf_sz == 0)
728 if (!ce_pipe->dest_ring)
731 num = __ath10k_ce_rx_num_free_bufs(ce_pipe);
733 ret = __ath10k_pci_rx_post_buf(pipe);
735 ath10k_warn(ar, "failed to post pci rx buf: %d\n", ret);
736 mod_timer(&ar_pci->rx_post_retry, jiffies +
737 ATH10K_PCI_RX_POST_RETRY_MS);
743 static void ath10k_pci_rx_post_pipe(struct ath10k_pci_pipe *pipe)
745 struct ath10k *ar = pipe->hif_ce_state;
746 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
748 spin_lock_bh(&ar_pci->ce_lock);
749 __ath10k_pci_rx_post_pipe(pipe);
750 spin_unlock_bh(&ar_pci->ce_lock);
753 static void ath10k_pci_rx_post(struct ath10k *ar)
755 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
758 spin_lock_bh(&ar_pci->ce_lock);
759 for (i = 0; i < CE_COUNT; i++)
760 __ath10k_pci_rx_post_pipe(&ar_pci->pipe_info[i]);
761 spin_unlock_bh(&ar_pci->ce_lock);
764 static void ath10k_pci_rx_replenish_retry(unsigned long ptr)
766 struct ath10k *ar = (void *)ptr;
768 ath10k_pci_rx_post(ar);
771 static u32 ath10k_pci_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr)
775 switch (ar->hw_rev) {
776 case ATH10K_HW_QCA988X:
777 case ATH10K_HW_QCA6174:
778 val = (ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
782 case ATH10K_HW_QCA99X0:
783 val = ath10k_pci_read32(ar, PCIE_BAR_REG_ADDRESS);
787 val |= 0x100000 | (addr & 0xfffff);
792 * Diagnostic read/write access is provided for startup/config/debug usage.
793 * Caller must guarantee proper alignment, when applicable, and single user
796 static int ath10k_pci_diag_read_mem(struct ath10k *ar, u32 address, void *data,
799 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
802 unsigned int completed_nbytes, orig_nbytes, remaining_bytes;
805 struct ath10k_ce_pipe *ce_diag;
806 /* Host buffer address in CE space */
808 dma_addr_t ce_data_base = 0;
809 void *data_buf = NULL;
812 spin_lock_bh(&ar_pci->ce_lock);
814 ce_diag = ar_pci->ce_diag;
817 * Allocate a temporary bounce buffer to hold caller's data
818 * to be DMA'ed from Target. This guarantees
819 * 1) 4-byte alignment
820 * 2) Buffer in DMA-able space
822 orig_nbytes = nbytes;
823 data_buf = (unsigned char *)dma_alloc_coherent(ar->dev,
832 memset(data_buf, 0, orig_nbytes);
834 remaining_bytes = orig_nbytes;
835 ce_data = ce_data_base;
836 while (remaining_bytes) {
837 nbytes = min_t(unsigned int, remaining_bytes,
838 DIAG_TRANSFER_LIMIT);
840 ret = __ath10k_ce_rx_post_buf(ce_diag, NULL, ce_data);
844 /* Request CE to send from Target(!) address to Host buffer */
846 * The address supplied by the caller is in the
847 * Target CPU virtual address space.
849 * In order to use this address with the diagnostic CE,
850 * convert it from Target CPU virtual address space
851 * to CE address space
853 address = ath10k_pci_targ_cpu_to_ce_addr(ar, address);
855 ret = ath10k_ce_send_nolock(ce_diag, NULL, (u32)address, nbytes, 0,
861 while (ath10k_ce_completed_send_next_nolock(ce_diag, NULL, &buf,
865 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
871 if (nbytes != completed_nbytes) {
876 if (buf != (u32)address) {
882 while (ath10k_ce_completed_recv_next_nolock(ce_diag, NULL, &buf,
887 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
893 if (nbytes != completed_nbytes) {
898 if (buf != ce_data) {
903 remaining_bytes -= nbytes;
910 memcpy(data, data_buf, orig_nbytes);
912 ath10k_warn(ar, "failed to read diag value at 0x%x: %d\n",
916 dma_free_coherent(ar->dev, orig_nbytes, data_buf,
919 spin_unlock_bh(&ar_pci->ce_lock);
924 static int ath10k_pci_diag_read32(struct ath10k *ar, u32 address, u32 *value)
929 ret = ath10k_pci_diag_read_mem(ar, address, &val, sizeof(val));
930 *value = __le32_to_cpu(val);
935 static int __ath10k_pci_diag_read_hi(struct ath10k *ar, void *dest,
941 host_addr = host_interest_item_address(src);
943 ret = ath10k_pci_diag_read32(ar, host_addr, &addr);
945 ath10k_warn(ar, "failed to get memcpy hi address for firmware address %d: %d\n",
950 ret = ath10k_pci_diag_read_mem(ar, addr, dest, len);
952 ath10k_warn(ar, "failed to memcpy firmware memory from %d (%d B): %d\n",
960 #define ath10k_pci_diag_read_hi(ar, dest, src, len) \
961 __ath10k_pci_diag_read_hi(ar, dest, HI_ITEM(src), len)
963 static int ath10k_pci_diag_write_mem(struct ath10k *ar, u32 address,
964 const void *data, int nbytes)
966 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
969 unsigned int completed_nbytes, orig_nbytes, remaining_bytes;
972 struct ath10k_ce_pipe *ce_diag;
973 void *data_buf = NULL;
974 u32 ce_data; /* Host buffer address in CE space */
975 dma_addr_t ce_data_base = 0;
978 spin_lock_bh(&ar_pci->ce_lock);
980 ce_diag = ar_pci->ce_diag;
983 * Allocate a temporary bounce buffer to hold caller's data
984 * to be DMA'ed to Target. This guarantees
985 * 1) 4-byte alignment
986 * 2) Buffer in DMA-able space
988 orig_nbytes = nbytes;
989 data_buf = (unsigned char *)dma_alloc_coherent(ar->dev,
998 /* Copy caller's data to allocated DMA buf */
999 memcpy(data_buf, data, orig_nbytes);
1002 * The address supplied by the caller is in the
1003 * Target CPU virtual address space.
1005 * In order to use this address with the diagnostic CE,
1007 * Target CPU virtual address space
1011 address = ath10k_pci_targ_cpu_to_ce_addr(ar, address);
1013 remaining_bytes = orig_nbytes;
1014 ce_data = ce_data_base;
1015 while (remaining_bytes) {
1016 /* FIXME: check cast */
1017 nbytes = min_t(int, remaining_bytes, DIAG_TRANSFER_LIMIT);
1019 /* Set up to receive directly into Target(!) address */
1020 ret = __ath10k_ce_rx_post_buf(ce_diag, NULL, address);
1025 * Request CE to send caller-supplied data that
1026 * was copied to bounce buffer to Target(!) address.
1028 ret = ath10k_ce_send_nolock(ce_diag, NULL, (u32)ce_data,
1034 while (ath10k_ce_completed_send_next_nolock(ce_diag, NULL, &buf,
1039 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
1045 if (nbytes != completed_nbytes) {
1050 if (buf != ce_data) {
1056 while (ath10k_ce_completed_recv_next_nolock(ce_diag, NULL, &buf,
1058 &id, &flags) != 0) {
1061 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
1067 if (nbytes != completed_nbytes) {
1072 if (buf != address) {
1077 remaining_bytes -= nbytes;
1084 dma_free_coherent(ar->dev, orig_nbytes, data_buf,
1089 ath10k_warn(ar, "failed to write diag value at 0x%x: %d\n",
1092 spin_unlock_bh(&ar_pci->ce_lock);
1097 static int ath10k_pci_diag_write32(struct ath10k *ar, u32 address, u32 value)
1099 __le32 val = __cpu_to_le32(value);
1101 return ath10k_pci_diag_write_mem(ar, address, &val, sizeof(val));
1104 /* Called by lower (CE) layer when a send to Target completes. */
1105 static void ath10k_pci_ce_send_done(struct ath10k_ce_pipe *ce_state)
1107 struct ath10k *ar = ce_state->ar;
1108 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1109 struct ath10k_hif_cb *cb = &ar_pci->msg_callbacks_current;
1110 struct sk_buff_head list;
1111 struct sk_buff *skb;
1113 unsigned int nbytes;
1114 unsigned int transfer_id;
1116 __skb_queue_head_init(&list);
1117 while (ath10k_ce_completed_send_next(ce_state, (void **)&skb, &ce_data,
1118 &nbytes, &transfer_id) == 0) {
1119 /* no need to call tx completion for NULL pointers */
1123 __skb_queue_tail(&list, skb);
1126 while ((skb = __skb_dequeue(&list)))
1127 cb->tx_completion(ar, skb);
1130 /* Called by lower (CE) layer when data is received from the Target. */
1131 static void ath10k_pci_ce_recv_data(struct ath10k_ce_pipe *ce_state)
1133 struct ath10k *ar = ce_state->ar;
1134 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1135 struct ath10k_pci_pipe *pipe_info = &ar_pci->pipe_info[ce_state->id];
1136 struct ath10k_hif_cb *cb = &ar_pci->msg_callbacks_current;
1137 struct sk_buff *skb;
1138 struct sk_buff_head list;
1139 void *transfer_context;
1141 unsigned int nbytes, max_nbytes;
1142 unsigned int transfer_id;
1145 __skb_queue_head_init(&list);
1146 while (ath10k_ce_completed_recv_next(ce_state, &transfer_context,
1147 &ce_data, &nbytes, &transfer_id,
1149 skb = transfer_context;
1150 max_nbytes = skb->len + skb_tailroom(skb);
1151 dma_unmap_single(ar->dev, ATH10K_SKB_RXCB(skb)->paddr,
1152 max_nbytes, DMA_FROM_DEVICE);
1154 if (unlikely(max_nbytes < nbytes)) {
1155 ath10k_warn(ar, "rxed more than expected (nbytes %d, max %d)",
1156 nbytes, max_nbytes);
1157 dev_kfree_skb_any(skb);
1161 skb_put(skb, nbytes);
1162 __skb_queue_tail(&list, skb);
1165 while ((skb = __skb_dequeue(&list))) {
1166 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci rx ce pipe %d len %d\n",
1167 ce_state->id, skb->len);
1168 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci rx: ",
1169 skb->data, skb->len);
1171 cb->rx_completion(ar, skb);
1174 ath10k_pci_rx_post_pipe(pipe_info);
1177 static int ath10k_pci_hif_tx_sg(struct ath10k *ar, u8 pipe_id,
1178 struct ath10k_hif_sg_item *items, int n_items)
1180 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1181 struct ath10k_pci_pipe *pci_pipe = &ar_pci->pipe_info[pipe_id];
1182 struct ath10k_ce_pipe *ce_pipe = pci_pipe->ce_hdl;
1183 struct ath10k_ce_ring *src_ring = ce_pipe->src_ring;
1184 unsigned int nentries_mask;
1185 unsigned int sw_index;
1186 unsigned int write_index;
1189 spin_lock_bh(&ar_pci->ce_lock);
1191 nentries_mask = src_ring->nentries_mask;
1192 sw_index = src_ring->sw_index;
1193 write_index = src_ring->write_index;
1195 if (unlikely(CE_RING_DELTA(nentries_mask,
1196 write_index, sw_index - 1) < n_items)) {
1201 for (i = 0; i < n_items - 1; i++) {
1202 ath10k_dbg(ar, ATH10K_DBG_PCI,
1203 "pci tx item %d paddr 0x%08x len %d n_items %d\n",
1204 i, items[i].paddr, items[i].len, n_items);
1205 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci tx data: ",
1206 items[i].vaddr, items[i].len);
1208 err = ath10k_ce_send_nolock(ce_pipe,
1209 items[i].transfer_context,
1212 items[i].transfer_id,
1213 CE_SEND_FLAG_GATHER);
1218 /* `i` is equal to `n_items -1` after for() */
1220 ath10k_dbg(ar, ATH10K_DBG_PCI,
1221 "pci tx item %d paddr 0x%08x len %d n_items %d\n",
1222 i, items[i].paddr, items[i].len, n_items);
1223 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci tx data: ",
1224 items[i].vaddr, items[i].len);
1226 err = ath10k_ce_send_nolock(ce_pipe,
1227 items[i].transfer_context,
1230 items[i].transfer_id,
1235 spin_unlock_bh(&ar_pci->ce_lock);
1240 __ath10k_ce_send_revert(ce_pipe);
1242 spin_unlock_bh(&ar_pci->ce_lock);
1246 static int ath10k_pci_hif_diag_read(struct ath10k *ar, u32 address, void *buf,
1249 return ath10k_pci_diag_read_mem(ar, address, buf, buf_len);
1252 static u16 ath10k_pci_hif_get_free_queue_number(struct ath10k *ar, u8 pipe)
1254 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1256 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif get free queue number\n");
1258 return ath10k_ce_num_free_src_entries(ar_pci->pipe_info[pipe].ce_hdl);
1261 static void ath10k_pci_dump_registers(struct ath10k *ar,
1262 struct ath10k_fw_crash_data *crash_data)
1264 __le32 reg_dump_values[REG_DUMP_COUNT_QCA988X] = {};
1267 lockdep_assert_held(&ar->data_lock);
1269 ret = ath10k_pci_diag_read_hi(ar, ®_dump_values[0],
1271 REG_DUMP_COUNT_QCA988X * sizeof(__le32));
1273 ath10k_err(ar, "failed to read firmware dump area: %d\n", ret);
1277 BUILD_BUG_ON(REG_DUMP_COUNT_QCA988X % 4);
1279 ath10k_err(ar, "firmware register dump:\n");
1280 for (i = 0; i < REG_DUMP_COUNT_QCA988X; i += 4)
1281 ath10k_err(ar, "[%02d]: 0x%08X 0x%08X 0x%08X 0x%08X\n",
1283 __le32_to_cpu(reg_dump_values[i]),
1284 __le32_to_cpu(reg_dump_values[i + 1]),
1285 __le32_to_cpu(reg_dump_values[i + 2]),
1286 __le32_to_cpu(reg_dump_values[i + 3]));
1291 for (i = 0; i < REG_DUMP_COUNT_QCA988X; i++)
1292 crash_data->registers[i] = reg_dump_values[i];
1295 static void ath10k_pci_fw_crashed_dump(struct ath10k *ar)
1297 struct ath10k_fw_crash_data *crash_data;
1300 spin_lock_bh(&ar->data_lock);
1302 ar->stats.fw_crash_counter++;
1304 crash_data = ath10k_debug_get_new_fw_crash_data(ar);
1307 scnprintf(uuid, sizeof(uuid), "%pUl", &crash_data->uuid);
1309 scnprintf(uuid, sizeof(uuid), "n/a");
1311 ath10k_err(ar, "firmware crashed! (uuid %s)\n", uuid);
1312 ath10k_print_driver_info(ar);
1313 ath10k_pci_dump_registers(ar, crash_data);
1315 spin_unlock_bh(&ar->data_lock);
1317 queue_work(ar->workqueue, &ar->restart_work);
1320 static void ath10k_pci_hif_send_complete_check(struct ath10k *ar, u8 pipe,
1323 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif send complete check\n");
1328 * Decide whether to actually poll for completions, or just
1329 * wait for a later chance.
1330 * If there seem to be plenty of resources left, then just wait
1331 * since checking involves reading a CE register, which is a
1332 * relatively expensive operation.
1334 resources = ath10k_pci_hif_get_free_queue_number(ar, pipe);
1337 * If at least 50% of the total resources are still available,
1338 * don't bother checking again yet.
1340 if (resources > (host_ce_config_wlan[pipe].src_nentries >> 1))
1343 ath10k_ce_per_engine_service(ar, pipe);
1346 static void ath10k_pci_hif_set_callbacks(struct ath10k *ar,
1347 struct ath10k_hif_cb *callbacks)
1349 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1351 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif set callbacks\n");
1353 memcpy(&ar_pci->msg_callbacks_current, callbacks,
1354 sizeof(ar_pci->msg_callbacks_current));
1357 static void ath10k_pci_kill_tasklet(struct ath10k *ar)
1359 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1362 tasklet_kill(&ar_pci->intr_tq);
1363 tasklet_kill(&ar_pci->msi_fw_err);
1365 for (i = 0; i < CE_COUNT; i++)
1366 tasklet_kill(&ar_pci->pipe_info[i].intr);
1368 del_timer_sync(&ar_pci->rx_post_retry);
1371 static int ath10k_pci_hif_map_service_to_pipe(struct ath10k *ar,
1372 u16 service_id, u8 *ul_pipe,
1373 u8 *dl_pipe, int *ul_is_polled,
1376 const struct service_to_pipe *entry;
1377 bool ul_set = false, dl_set = false;
1380 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif map service\n");
1382 /* polling for received messages not supported */
1385 for (i = 0; i < ARRAY_SIZE(target_service_to_ce_map_wlan); i++) {
1386 entry = &target_service_to_ce_map_wlan[i];
1388 if (__le32_to_cpu(entry->service_id) != service_id)
1391 switch (__le32_to_cpu(entry->pipedir)) {
1396 *dl_pipe = __le32_to_cpu(entry->pipenum);
1401 *ul_pipe = __le32_to_cpu(entry->pipenum);
1407 *dl_pipe = __le32_to_cpu(entry->pipenum);
1408 *ul_pipe = __le32_to_cpu(entry->pipenum);
1415 if (WARN_ON(!ul_set || !dl_set))
1419 (host_ce_config_wlan[*ul_pipe].flags & CE_ATTR_DIS_INTR) != 0;
1424 static void ath10k_pci_hif_get_default_pipe(struct ath10k *ar,
1425 u8 *ul_pipe, u8 *dl_pipe)
1427 int ul_is_polled, dl_is_polled;
1429 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif get default pipe\n");
1431 (void)ath10k_pci_hif_map_service_to_pipe(ar,
1432 ATH10K_HTC_SVC_ID_RSVD_CTRL,
1439 static void ath10k_pci_irq_msi_fw_mask(struct ath10k *ar)
1443 switch (ar->hw_rev) {
1444 case ATH10K_HW_QCA988X:
1445 case ATH10K_HW_QCA6174:
1446 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
1448 val &= ~CORE_CTRL_PCIE_REG_31_MASK;
1449 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
1450 CORE_CTRL_ADDRESS, val);
1452 case ATH10K_HW_QCA99X0:
1453 /* TODO: Find appropriate register configuration for QCA99X0
1460 static void ath10k_pci_irq_msi_fw_unmask(struct ath10k *ar)
1464 switch (ar->hw_rev) {
1465 case ATH10K_HW_QCA988X:
1466 case ATH10K_HW_QCA6174:
1467 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
1469 val |= CORE_CTRL_PCIE_REG_31_MASK;
1470 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
1471 CORE_CTRL_ADDRESS, val);
1473 case ATH10K_HW_QCA99X0:
1474 /* TODO: Find appropriate register configuration for QCA99X0
1475 * to unmask irq/MSI.
1481 static void ath10k_pci_irq_disable(struct ath10k *ar)
1483 ath10k_ce_disable_interrupts(ar);
1484 ath10k_pci_disable_and_clear_legacy_irq(ar);
1485 ath10k_pci_irq_msi_fw_mask(ar);
1488 static void ath10k_pci_irq_sync(struct ath10k *ar)
1490 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1493 for (i = 0; i < max(1, ar_pci->num_msi_intrs); i++)
1494 synchronize_irq(ar_pci->pdev->irq + i);
1497 static void ath10k_pci_irq_enable(struct ath10k *ar)
1499 ath10k_ce_enable_interrupts(ar);
1500 ath10k_pci_enable_legacy_irq(ar);
1501 ath10k_pci_irq_msi_fw_unmask(ar);
1504 static int ath10k_pci_hif_start(struct ath10k *ar)
1506 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1507 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif start\n");
1509 ath10k_pci_irq_enable(ar);
1510 ath10k_pci_rx_post(ar);
1512 pcie_capability_write_word(ar_pci->pdev, PCI_EXP_LNKCTL,
1518 static void ath10k_pci_rx_pipe_cleanup(struct ath10k_pci_pipe *pci_pipe)
1521 struct ath10k_ce_pipe *ce_pipe;
1522 struct ath10k_ce_ring *ce_ring;
1523 struct sk_buff *skb;
1526 ar = pci_pipe->hif_ce_state;
1527 ce_pipe = pci_pipe->ce_hdl;
1528 ce_ring = ce_pipe->dest_ring;
1533 if (!pci_pipe->buf_sz)
1536 for (i = 0; i < ce_ring->nentries; i++) {
1537 skb = ce_ring->per_transfer_context[i];
1541 ce_ring->per_transfer_context[i] = NULL;
1543 dma_unmap_single(ar->dev, ATH10K_SKB_RXCB(skb)->paddr,
1544 skb->len + skb_tailroom(skb),
1546 dev_kfree_skb_any(skb);
1550 static void ath10k_pci_tx_pipe_cleanup(struct ath10k_pci_pipe *pci_pipe)
1553 struct ath10k_pci *ar_pci;
1554 struct ath10k_ce_pipe *ce_pipe;
1555 struct ath10k_ce_ring *ce_ring;
1556 struct ce_desc *ce_desc;
1557 struct sk_buff *skb;
1560 ar = pci_pipe->hif_ce_state;
1561 ar_pci = ath10k_pci_priv(ar);
1562 ce_pipe = pci_pipe->ce_hdl;
1563 ce_ring = ce_pipe->src_ring;
1568 if (!pci_pipe->buf_sz)
1571 ce_desc = ce_ring->shadow_base;
1572 if (WARN_ON(!ce_desc))
1575 for (i = 0; i < ce_ring->nentries; i++) {
1576 skb = ce_ring->per_transfer_context[i];
1580 ce_ring->per_transfer_context[i] = NULL;
1582 ar_pci->msg_callbacks_current.tx_completion(ar, skb);
1587 * Cleanup residual buffers for device shutdown:
1588 * buffers that were enqueued for receive
1589 * buffers that were to be sent
1590 * Note: Buffers that had completed but which were
1591 * not yet processed are on a completion queue. They
1592 * are handled when the completion thread shuts down.
1594 static void ath10k_pci_buffer_cleanup(struct ath10k *ar)
1596 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1599 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) {
1600 struct ath10k_pci_pipe *pipe_info;
1602 pipe_info = &ar_pci->pipe_info[pipe_num];
1603 ath10k_pci_rx_pipe_cleanup(pipe_info);
1604 ath10k_pci_tx_pipe_cleanup(pipe_info);
1608 static void ath10k_pci_ce_deinit(struct ath10k *ar)
1612 for (i = 0; i < CE_COUNT; i++)
1613 ath10k_ce_deinit_pipe(ar, i);
1616 static void ath10k_pci_flush(struct ath10k *ar)
1618 ath10k_pci_kill_tasklet(ar);
1619 ath10k_pci_buffer_cleanup(ar);
1622 static void ath10k_pci_hif_stop(struct ath10k *ar)
1624 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1625 unsigned long flags;
1627 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif stop\n");
1629 /* Most likely the device has HTT Rx ring configured. The only way to
1630 * prevent the device from accessing (and possible corrupting) host
1631 * memory is to reset the chip now.
1633 * There's also no known way of masking MSI interrupts on the device.
1634 * For ranged MSI the CE-related interrupts can be masked. However
1635 * regardless how many MSI interrupts are assigned the first one
1636 * is always used for firmware indications (crashes) and cannot be
1637 * masked. To prevent the device from asserting the interrupt reset it
1638 * before proceeding with cleanup.
1640 ath10k_pci_safe_chip_reset(ar);
1642 ath10k_pci_irq_disable(ar);
1643 ath10k_pci_irq_sync(ar);
1644 ath10k_pci_flush(ar);
1646 spin_lock_irqsave(&ar_pci->ps_lock, flags);
1647 WARN_ON(ar_pci->ps_wake_refcount > 0);
1648 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
1651 static int ath10k_pci_hif_exchange_bmi_msg(struct ath10k *ar,
1652 void *req, u32 req_len,
1653 void *resp, u32 *resp_len)
1655 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1656 struct ath10k_pci_pipe *pci_tx = &ar_pci->pipe_info[BMI_CE_NUM_TO_TARG];
1657 struct ath10k_pci_pipe *pci_rx = &ar_pci->pipe_info[BMI_CE_NUM_TO_HOST];
1658 struct ath10k_ce_pipe *ce_tx = pci_tx->ce_hdl;
1659 struct ath10k_ce_pipe *ce_rx = pci_rx->ce_hdl;
1660 dma_addr_t req_paddr = 0;
1661 dma_addr_t resp_paddr = 0;
1662 struct bmi_xfer xfer = {};
1663 void *treq, *tresp = NULL;
1668 if (resp && !resp_len)
1671 if (resp && resp_len && *resp_len == 0)
1674 treq = kmemdup(req, req_len, GFP_KERNEL);
1678 req_paddr = dma_map_single(ar->dev, treq, req_len, DMA_TO_DEVICE);
1679 ret = dma_mapping_error(ar->dev, req_paddr);
1685 if (resp && resp_len) {
1686 tresp = kzalloc(*resp_len, GFP_KERNEL);
1692 resp_paddr = dma_map_single(ar->dev, tresp, *resp_len,
1694 ret = dma_mapping_error(ar->dev, resp_paddr);
1700 xfer.wait_for_resp = true;
1703 ath10k_ce_rx_post_buf(ce_rx, &xfer, resp_paddr);
1706 ret = ath10k_ce_send(ce_tx, &xfer, req_paddr, req_len, -1, 0);
1710 ret = ath10k_pci_bmi_wait(ce_tx, ce_rx, &xfer);
1713 unsigned int unused_nbytes;
1714 unsigned int unused_id;
1716 ath10k_ce_cancel_send_next(ce_tx, NULL, &unused_buffer,
1717 &unused_nbytes, &unused_id);
1719 /* non-zero means we did not time out */
1727 ath10k_ce_revoke_recv_next(ce_rx, NULL, &unused_buffer);
1728 dma_unmap_single(ar->dev, resp_paddr,
1729 *resp_len, DMA_FROM_DEVICE);
1732 dma_unmap_single(ar->dev, req_paddr, req_len, DMA_TO_DEVICE);
1734 if (ret == 0 && resp_len) {
1735 *resp_len = min(*resp_len, xfer.resp_len);
1736 memcpy(resp, tresp, xfer.resp_len);
1745 static void ath10k_pci_bmi_send_done(struct ath10k_ce_pipe *ce_state)
1747 struct bmi_xfer *xfer;
1749 unsigned int nbytes;
1750 unsigned int transfer_id;
1752 if (ath10k_ce_completed_send_next(ce_state, (void **)&xfer, &ce_data,
1753 &nbytes, &transfer_id))
1756 xfer->tx_done = true;
1759 static void ath10k_pci_bmi_recv_data(struct ath10k_ce_pipe *ce_state)
1761 struct ath10k *ar = ce_state->ar;
1762 struct bmi_xfer *xfer;
1764 unsigned int nbytes;
1765 unsigned int transfer_id;
1768 if (ath10k_ce_completed_recv_next(ce_state, (void **)&xfer, &ce_data,
1769 &nbytes, &transfer_id, &flags))
1772 if (WARN_ON_ONCE(!xfer))
1775 if (!xfer->wait_for_resp) {
1776 ath10k_warn(ar, "unexpected: BMI data received; ignoring\n");
1780 xfer->resp_len = nbytes;
1781 xfer->rx_done = true;
1784 static int ath10k_pci_bmi_wait(struct ath10k_ce_pipe *tx_pipe,
1785 struct ath10k_ce_pipe *rx_pipe,
1786 struct bmi_xfer *xfer)
1788 unsigned long timeout = jiffies + BMI_COMMUNICATION_TIMEOUT_HZ;
1790 while (time_before_eq(jiffies, timeout)) {
1791 ath10k_pci_bmi_send_done(tx_pipe);
1792 ath10k_pci_bmi_recv_data(rx_pipe);
1794 if (xfer->tx_done && (xfer->rx_done == xfer->wait_for_resp))
1804 * Send an interrupt to the device to wake up the Target CPU
1805 * so it has an opportunity to notice any changed state.
1807 static int ath10k_pci_wake_target_cpu(struct ath10k *ar)
1811 addr = SOC_CORE_BASE_ADDRESS | CORE_CTRL_ADDRESS;
1812 val = ath10k_pci_read32(ar, addr);
1813 val |= CORE_CTRL_CPU_INTR_MASK;
1814 ath10k_pci_write32(ar, addr, val);
1819 static int ath10k_pci_get_num_banks(struct ath10k *ar)
1821 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1823 switch (ar_pci->pdev->device) {
1824 case QCA988X_2_0_DEVICE_ID:
1825 case QCA99X0_2_0_DEVICE_ID:
1827 case QCA6164_2_1_DEVICE_ID:
1828 case QCA6174_2_1_DEVICE_ID:
1829 switch (MS(ar->chip_id, SOC_CHIP_ID_REV)) {
1830 case QCA6174_HW_1_0_CHIP_ID_REV:
1831 case QCA6174_HW_1_1_CHIP_ID_REV:
1832 case QCA6174_HW_2_1_CHIP_ID_REV:
1833 case QCA6174_HW_2_2_CHIP_ID_REV:
1835 case QCA6174_HW_1_3_CHIP_ID_REV:
1837 case QCA6174_HW_3_0_CHIP_ID_REV:
1838 case QCA6174_HW_3_1_CHIP_ID_REV:
1839 case QCA6174_HW_3_2_CHIP_ID_REV:
1845 ath10k_warn(ar, "unknown number of banks, assuming 1\n");
1849 static int ath10k_pci_init_config(struct ath10k *ar)
1851 u32 interconnect_targ_addr;
1852 u32 pcie_state_targ_addr = 0;
1853 u32 pipe_cfg_targ_addr = 0;
1854 u32 svc_to_pipe_map = 0;
1855 u32 pcie_config_flags = 0;
1857 u32 ealloc_targ_addr;
1859 u32 flag2_targ_addr;
1862 /* Download to Target the CE Config and the service-to-CE map */
1863 interconnect_targ_addr =
1864 host_interest_item_address(HI_ITEM(hi_interconnect_state));
1866 /* Supply Target-side CE configuration */
1867 ret = ath10k_pci_diag_read32(ar, interconnect_targ_addr,
1868 &pcie_state_targ_addr);
1870 ath10k_err(ar, "Failed to get pcie state addr: %d\n", ret);
1874 if (pcie_state_targ_addr == 0) {
1876 ath10k_err(ar, "Invalid pcie state addr\n");
1880 ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr +
1881 offsetof(struct pcie_state,
1883 &pipe_cfg_targ_addr);
1885 ath10k_err(ar, "Failed to get pipe cfg addr: %d\n", ret);
1889 if (pipe_cfg_targ_addr == 0) {
1891 ath10k_err(ar, "Invalid pipe cfg addr\n");
1895 ret = ath10k_pci_diag_write_mem(ar, pipe_cfg_targ_addr,
1896 target_ce_config_wlan,
1897 sizeof(struct ce_pipe_config) *
1898 NUM_TARGET_CE_CONFIG_WLAN);
1901 ath10k_err(ar, "Failed to write pipe cfg: %d\n", ret);
1905 ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr +
1906 offsetof(struct pcie_state,
1910 ath10k_err(ar, "Failed to get svc/pipe map: %d\n", ret);
1914 if (svc_to_pipe_map == 0) {
1916 ath10k_err(ar, "Invalid svc_to_pipe map\n");
1920 ret = ath10k_pci_diag_write_mem(ar, svc_to_pipe_map,
1921 target_service_to_ce_map_wlan,
1922 sizeof(target_service_to_ce_map_wlan));
1924 ath10k_err(ar, "Failed to write svc/pipe map: %d\n", ret);
1928 ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr +
1929 offsetof(struct pcie_state,
1931 &pcie_config_flags);
1933 ath10k_err(ar, "Failed to get pcie config_flags: %d\n", ret);
1937 pcie_config_flags &= ~PCIE_CONFIG_FLAG_ENABLE_L1;
1939 ret = ath10k_pci_diag_write32(ar, (pcie_state_targ_addr +
1940 offsetof(struct pcie_state,
1944 ath10k_err(ar, "Failed to write pcie config_flags: %d\n", ret);
1948 /* configure early allocation */
1949 ealloc_targ_addr = host_interest_item_address(HI_ITEM(hi_early_alloc));
1951 ret = ath10k_pci_diag_read32(ar, ealloc_targ_addr, &ealloc_value);
1953 ath10k_err(ar, "Faile to get early alloc val: %d\n", ret);
1957 /* first bank is switched to IRAM */
1958 ealloc_value |= ((HI_EARLY_ALLOC_MAGIC << HI_EARLY_ALLOC_MAGIC_SHIFT) &
1959 HI_EARLY_ALLOC_MAGIC_MASK);
1960 ealloc_value |= ((ath10k_pci_get_num_banks(ar) <<
1961 HI_EARLY_ALLOC_IRAM_BANKS_SHIFT) &
1962 HI_EARLY_ALLOC_IRAM_BANKS_MASK);
1964 ret = ath10k_pci_diag_write32(ar, ealloc_targ_addr, ealloc_value);
1966 ath10k_err(ar, "Failed to set early alloc val: %d\n", ret);
1970 /* Tell Target to proceed with initialization */
1971 flag2_targ_addr = host_interest_item_address(HI_ITEM(hi_option_flag2));
1973 ret = ath10k_pci_diag_read32(ar, flag2_targ_addr, &flag2_value);
1975 ath10k_err(ar, "Failed to get option val: %d\n", ret);
1979 flag2_value |= HI_OPTION_EARLY_CFG_DONE;
1981 ret = ath10k_pci_diag_write32(ar, flag2_targ_addr, flag2_value);
1983 ath10k_err(ar, "Failed to set option val: %d\n", ret);
1990 static int ath10k_pci_alloc_pipes(struct ath10k *ar)
1992 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1993 struct ath10k_pci_pipe *pipe;
1996 for (i = 0; i < CE_COUNT; i++) {
1997 pipe = &ar_pci->pipe_info[i];
1998 pipe->ce_hdl = &ar_pci->ce_states[i];
2000 pipe->hif_ce_state = ar;
2002 ret = ath10k_ce_alloc_pipe(ar, i, &host_ce_config_wlan[i],
2003 ath10k_pci_ce_send_done,
2004 ath10k_pci_ce_recv_data);
2006 ath10k_err(ar, "failed to allocate copy engine pipe %d: %d\n",
2011 /* Last CE is Diagnostic Window */
2012 if (i == CE_DIAG_PIPE) {
2013 ar_pci->ce_diag = pipe->ce_hdl;
2017 pipe->buf_sz = (size_t)(host_ce_config_wlan[i].src_sz_max);
2023 static void ath10k_pci_free_pipes(struct ath10k *ar)
2027 for (i = 0; i < CE_COUNT; i++)
2028 ath10k_ce_free_pipe(ar, i);
2031 static int ath10k_pci_init_pipes(struct ath10k *ar)
2035 for (i = 0; i < CE_COUNT; i++) {
2036 ret = ath10k_ce_init_pipe(ar, i, &host_ce_config_wlan[i]);
2038 ath10k_err(ar, "failed to initialize copy engine pipe %d: %d\n",
2047 static bool ath10k_pci_has_fw_crashed(struct ath10k *ar)
2049 return ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS) &
2050 FW_IND_EVENT_PENDING;
2053 static void ath10k_pci_fw_crashed_clear(struct ath10k *ar)
2057 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS);
2058 val &= ~FW_IND_EVENT_PENDING;
2059 ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, val);
2062 /* this function effectively clears target memory controller assert line */
2063 static void ath10k_pci_warm_reset_si0(struct ath10k *ar)
2067 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
2068 ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS,
2069 val | SOC_RESET_CONTROL_SI0_RST_MASK);
2070 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
2074 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
2075 ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS,
2076 val & ~SOC_RESET_CONTROL_SI0_RST_MASK);
2077 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
2082 static void ath10k_pci_warm_reset_cpu(struct ath10k *ar)
2086 ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, 0);
2088 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
2089 SOC_RESET_CONTROL_ADDRESS);
2090 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,
2091 val | SOC_RESET_CONTROL_CPU_WARM_RST_MASK);
2094 static void ath10k_pci_warm_reset_ce(struct ath10k *ar)
2098 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
2099 SOC_RESET_CONTROL_ADDRESS);
2101 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,
2102 val | SOC_RESET_CONTROL_CE_RST_MASK);
2104 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,
2105 val & ~SOC_RESET_CONTROL_CE_RST_MASK);
2108 static void ath10k_pci_warm_reset_clear_lf(struct ath10k *ar)
2112 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
2113 SOC_LF_TIMER_CONTROL0_ADDRESS);
2114 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS +
2115 SOC_LF_TIMER_CONTROL0_ADDRESS,
2116 val & ~SOC_LF_TIMER_CONTROL0_ENABLE_MASK);
2119 static int ath10k_pci_warm_reset(struct ath10k *ar)
2123 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot warm reset\n");
2125 spin_lock_bh(&ar->data_lock);
2126 ar->stats.fw_warm_reset_counter++;
2127 spin_unlock_bh(&ar->data_lock);
2129 ath10k_pci_irq_disable(ar);
2131 /* Make sure the target CPU is not doing anything dangerous, e.g. if it
2132 * were to access copy engine while host performs copy engine reset
2133 * then it is possible for the device to confuse pci-e controller to
2134 * the point of bringing host system to a complete stop (i.e. hang).
2136 ath10k_pci_warm_reset_si0(ar);
2137 ath10k_pci_warm_reset_cpu(ar);
2138 ath10k_pci_init_pipes(ar);
2139 ath10k_pci_wait_for_target_init(ar);
2141 ath10k_pci_warm_reset_clear_lf(ar);
2142 ath10k_pci_warm_reset_ce(ar);
2143 ath10k_pci_warm_reset_cpu(ar);
2144 ath10k_pci_init_pipes(ar);
2146 ret = ath10k_pci_wait_for_target_init(ar);
2148 ath10k_warn(ar, "failed to wait for target init: %d\n", ret);
2152 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot warm reset complete\n");
2157 static int ath10k_pci_safe_chip_reset(struct ath10k *ar)
2159 if (QCA_REV_988X(ar) || QCA_REV_6174(ar)) {
2160 return ath10k_pci_warm_reset(ar);
2161 } else if (QCA_REV_99X0(ar)) {
2162 ath10k_pci_irq_disable(ar);
2163 return ath10k_pci_qca99x0_chip_reset(ar);
2169 static int ath10k_pci_qca988x_chip_reset(struct ath10k *ar)
2174 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot 988x chip reset\n");
2176 /* Some hardware revisions (e.g. CUS223v2) has issues with cold reset.
2177 * It is thus preferred to use warm reset which is safer but may not be
2178 * able to recover the device from all possible fail scenarios.
2180 * Warm reset doesn't always work on first try so attempt it a few
2181 * times before giving up.
2183 for (i = 0; i < ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS; i++) {
2184 ret = ath10k_pci_warm_reset(ar);
2186 ath10k_warn(ar, "failed to warm reset attempt %d of %d: %d\n",
2187 i + 1, ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS,
2192 /* FIXME: Sometimes copy engine doesn't recover after warm
2193 * reset. In most cases this needs cold reset. In some of these
2194 * cases the device is in such a state that a cold reset may
2197 * Reading any host interest register via copy engine is
2198 * sufficient to verify if device is capable of booting
2201 ret = ath10k_pci_init_pipes(ar);
2203 ath10k_warn(ar, "failed to init copy engine: %d\n",
2208 ret = ath10k_pci_diag_read32(ar, QCA988X_HOST_INTEREST_ADDRESS,
2211 ath10k_warn(ar, "failed to poke copy engine: %d\n",
2216 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot chip reset complete (warm)\n");
2220 if (ath10k_pci_reset_mode == ATH10K_PCI_RESET_WARM_ONLY) {
2221 ath10k_warn(ar, "refusing cold reset as requested\n");
2225 ret = ath10k_pci_cold_reset(ar);
2227 ath10k_warn(ar, "failed to cold reset: %d\n", ret);
2231 ret = ath10k_pci_wait_for_target_init(ar);
2233 ath10k_warn(ar, "failed to wait for target after cold reset: %d\n",
2238 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca988x chip reset complete (cold)\n");
2243 static int ath10k_pci_qca6174_chip_reset(struct ath10k *ar)
2247 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca6174 chip reset\n");
2249 /* FIXME: QCA6174 requires cold + warm reset to work. */
2251 ret = ath10k_pci_cold_reset(ar);
2253 ath10k_warn(ar, "failed to cold reset: %d\n", ret);
2257 ret = ath10k_pci_wait_for_target_init(ar);
2259 ath10k_warn(ar, "failed to wait for target after cold reset: %d\n",
2264 ret = ath10k_pci_warm_reset(ar);
2266 ath10k_warn(ar, "failed to warm reset: %d\n", ret);
2270 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca6174 chip reset complete (cold)\n");
2275 static int ath10k_pci_qca99x0_chip_reset(struct ath10k *ar)
2279 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca99x0 chip reset\n");
2281 ret = ath10k_pci_cold_reset(ar);
2283 ath10k_warn(ar, "failed to cold reset: %d\n", ret);
2287 ret = ath10k_pci_wait_for_target_init(ar);
2289 ath10k_warn(ar, "failed to wait for target after cold reset: %d\n",
2294 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca99x0 chip reset complete (cold)\n");
2299 static int ath10k_pci_chip_reset(struct ath10k *ar)
2301 if (QCA_REV_988X(ar))
2302 return ath10k_pci_qca988x_chip_reset(ar);
2303 else if (QCA_REV_6174(ar))
2304 return ath10k_pci_qca6174_chip_reset(ar);
2305 else if (QCA_REV_99X0(ar))
2306 return ath10k_pci_qca99x0_chip_reset(ar);
2311 static int ath10k_pci_hif_power_up(struct ath10k *ar)
2313 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2316 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif power up\n");
2318 pcie_capability_read_word(ar_pci->pdev, PCI_EXP_LNKCTL,
2320 pcie_capability_write_word(ar_pci->pdev, PCI_EXP_LNKCTL,
2321 ar_pci->link_ctl & ~PCI_EXP_LNKCTL_ASPMC);
2324 * Bring the target up cleanly.
2326 * The target may be in an undefined state with an AUX-powered Target
2327 * and a Host in WoW mode. If the Host crashes, loses power, or is
2328 * restarted (without unloading the driver) then the Target is left
2329 * (aux) powered and running. On a subsequent driver load, the Target
2330 * is in an unexpected state. We try to catch that here in order to
2331 * reset the Target and retry the probe.
2333 ret = ath10k_pci_chip_reset(ar);
2335 if (ath10k_pci_has_fw_crashed(ar)) {
2336 ath10k_warn(ar, "firmware crashed during chip reset\n");
2337 ath10k_pci_fw_crashed_clear(ar);
2338 ath10k_pci_fw_crashed_dump(ar);
2341 ath10k_err(ar, "failed to reset chip: %d\n", ret);
2345 ret = ath10k_pci_init_pipes(ar);
2347 ath10k_err(ar, "failed to initialize CE: %d\n", ret);
2351 ret = ath10k_pci_init_config(ar);
2353 ath10k_err(ar, "failed to setup init config: %d\n", ret);
2357 ret = ath10k_pci_wake_target_cpu(ar);
2359 ath10k_err(ar, "could not wake up target CPU: %d\n", ret);
2366 ath10k_pci_ce_deinit(ar);
2372 static void ath10k_pci_hif_power_down(struct ath10k *ar)
2374 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif power down\n");
2376 /* Currently hif_power_up performs effectively a reset and hif_stop
2377 * resets the chip as well so there's no point in resetting here.
2383 static int ath10k_pci_hif_suspend(struct ath10k *ar)
2385 /* The grace timer can still be counting down and ar->ps_awake be true.
2386 * It is known that the device may be asleep after resuming regardless
2387 * of the SoC powersave state before suspending. Hence make sure the
2388 * device is asleep before proceeding.
2390 ath10k_pci_sleep_sync(ar);
2395 static int ath10k_pci_hif_resume(struct ath10k *ar)
2397 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2398 struct pci_dev *pdev = ar_pci->pdev;
2401 /* Suspend/Resume resets the PCI configuration space, so we have to
2402 * re-disable the RETRY_TIMEOUT register (0x41) to keep PCI Tx retries
2403 * from interfering with C3 CPU state. pci_restore_state won't help
2404 * here since it only restores the first 64 bytes pci config header.
2406 pci_read_config_dword(pdev, 0x40, &val);
2407 if ((val & 0x0000ff00) != 0)
2408 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
2414 static const struct ath10k_hif_ops ath10k_pci_hif_ops = {
2415 .tx_sg = ath10k_pci_hif_tx_sg,
2416 .diag_read = ath10k_pci_hif_diag_read,
2417 .diag_write = ath10k_pci_diag_write_mem,
2418 .exchange_bmi_msg = ath10k_pci_hif_exchange_bmi_msg,
2419 .start = ath10k_pci_hif_start,
2420 .stop = ath10k_pci_hif_stop,
2421 .map_service_to_pipe = ath10k_pci_hif_map_service_to_pipe,
2422 .get_default_pipe = ath10k_pci_hif_get_default_pipe,
2423 .send_complete_check = ath10k_pci_hif_send_complete_check,
2424 .set_callbacks = ath10k_pci_hif_set_callbacks,
2425 .get_free_queue_number = ath10k_pci_hif_get_free_queue_number,
2426 .power_up = ath10k_pci_hif_power_up,
2427 .power_down = ath10k_pci_hif_power_down,
2428 .read32 = ath10k_pci_read32,
2429 .write32 = ath10k_pci_write32,
2431 .suspend = ath10k_pci_hif_suspend,
2432 .resume = ath10k_pci_hif_resume,
2436 static void ath10k_pci_ce_tasklet(unsigned long ptr)
2438 struct ath10k_pci_pipe *pipe = (struct ath10k_pci_pipe *)ptr;
2439 struct ath10k_pci *ar_pci = pipe->ar_pci;
2441 ath10k_ce_per_engine_service(ar_pci->ar, pipe->pipe_num);
2444 static void ath10k_msi_err_tasklet(unsigned long data)
2446 struct ath10k *ar = (struct ath10k *)data;
2448 if (!ath10k_pci_has_fw_crashed(ar)) {
2449 ath10k_warn(ar, "received unsolicited fw crash interrupt\n");
2453 ath10k_pci_irq_disable(ar);
2454 ath10k_pci_fw_crashed_clear(ar);
2455 ath10k_pci_fw_crashed_dump(ar);
2459 * Handler for a per-engine interrupt on a PARTICULAR CE.
2460 * This is used in cases where each CE has a private MSI interrupt.
2462 static irqreturn_t ath10k_pci_per_engine_handler(int irq, void *arg)
2464 struct ath10k *ar = arg;
2465 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2466 int ce_id = irq - ar_pci->pdev->irq - MSI_ASSIGN_CE_INITIAL;
2468 if (ce_id < 0 || ce_id >= ARRAY_SIZE(ar_pci->pipe_info)) {
2469 ath10k_warn(ar, "unexpected/invalid irq %d ce_id %d\n", irq,
2475 * NOTE: We are able to derive ce_id from irq because we
2476 * use a one-to-one mapping for CE's 0..5.
2477 * CE's 6 & 7 do not use interrupts at all.
2479 * This mapping must be kept in sync with the mapping
2482 tasklet_schedule(&ar_pci->pipe_info[ce_id].intr);
2486 static irqreturn_t ath10k_pci_msi_fw_handler(int irq, void *arg)
2488 struct ath10k *ar = arg;
2489 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2491 tasklet_schedule(&ar_pci->msi_fw_err);
2496 * Top-level interrupt handler for all PCI interrupts from a Target.
2497 * When a block of MSI interrupts is allocated, this top-level handler
2498 * is not used; instead, we directly call the correct sub-handler.
2500 static irqreturn_t ath10k_pci_interrupt_handler(int irq, void *arg)
2502 struct ath10k *ar = arg;
2503 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2505 if (ar_pci->num_msi_intrs == 0) {
2506 if (!ath10k_pci_irq_pending(ar))
2509 ath10k_pci_disable_and_clear_legacy_irq(ar);
2512 tasklet_schedule(&ar_pci->intr_tq);
2517 static void ath10k_pci_tasklet(unsigned long data)
2519 struct ath10k *ar = (struct ath10k *)data;
2520 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2522 if (ath10k_pci_has_fw_crashed(ar)) {
2523 ath10k_pci_irq_disable(ar);
2524 ath10k_pci_fw_crashed_clear(ar);
2525 ath10k_pci_fw_crashed_dump(ar);
2529 ath10k_ce_per_engine_service_any(ar);
2531 /* Re-enable legacy irq that was disabled in the irq handler */
2532 if (ar_pci->num_msi_intrs == 0)
2533 ath10k_pci_enable_legacy_irq(ar);
2536 static int ath10k_pci_request_irq_msix(struct ath10k *ar)
2538 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2541 ret = request_irq(ar_pci->pdev->irq + MSI_ASSIGN_FW,
2542 ath10k_pci_msi_fw_handler,
2543 IRQF_SHARED, "ath10k_pci", ar);
2545 ath10k_warn(ar, "failed to request MSI-X fw irq %d: %d\n",
2546 ar_pci->pdev->irq + MSI_ASSIGN_FW, ret);
2550 for (i = MSI_ASSIGN_CE_INITIAL; i <= MSI_ASSIGN_CE_MAX; i++) {
2551 ret = request_irq(ar_pci->pdev->irq + i,
2552 ath10k_pci_per_engine_handler,
2553 IRQF_SHARED, "ath10k_pci", ar);
2555 ath10k_warn(ar, "failed to request MSI-X ce irq %d: %d\n",
2556 ar_pci->pdev->irq + i, ret);
2558 for (i--; i >= MSI_ASSIGN_CE_INITIAL; i--)
2559 free_irq(ar_pci->pdev->irq + i, ar);
2561 free_irq(ar_pci->pdev->irq + MSI_ASSIGN_FW, ar);
2569 static int ath10k_pci_request_irq_msi(struct ath10k *ar)
2571 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2574 ret = request_irq(ar_pci->pdev->irq,
2575 ath10k_pci_interrupt_handler,
2576 IRQF_SHARED, "ath10k_pci", ar);
2578 ath10k_warn(ar, "failed to request MSI irq %d: %d\n",
2579 ar_pci->pdev->irq, ret);
2586 static int ath10k_pci_request_irq_legacy(struct ath10k *ar)
2588 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2591 ret = request_irq(ar_pci->pdev->irq,
2592 ath10k_pci_interrupt_handler,
2593 IRQF_SHARED, "ath10k_pci", ar);
2595 ath10k_warn(ar, "failed to request legacy irq %d: %d\n",
2596 ar_pci->pdev->irq, ret);
2603 static int ath10k_pci_request_irq(struct ath10k *ar)
2605 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2607 switch (ar_pci->num_msi_intrs) {
2609 return ath10k_pci_request_irq_legacy(ar);
2611 return ath10k_pci_request_irq_msi(ar);
2613 return ath10k_pci_request_irq_msix(ar);
2617 static void ath10k_pci_free_irq(struct ath10k *ar)
2619 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2622 /* There's at least one interrupt irregardless whether its legacy INTR
2623 * or MSI or MSI-X */
2624 for (i = 0; i < max(1, ar_pci->num_msi_intrs); i++)
2625 free_irq(ar_pci->pdev->irq + i, ar);
2628 static void ath10k_pci_init_irq_tasklets(struct ath10k *ar)
2630 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2633 tasklet_init(&ar_pci->intr_tq, ath10k_pci_tasklet, (unsigned long)ar);
2634 tasklet_init(&ar_pci->msi_fw_err, ath10k_msi_err_tasklet,
2637 for (i = 0; i < CE_COUNT; i++) {
2638 ar_pci->pipe_info[i].ar_pci = ar_pci;
2639 tasklet_init(&ar_pci->pipe_info[i].intr, ath10k_pci_ce_tasklet,
2640 (unsigned long)&ar_pci->pipe_info[i]);
2644 static int ath10k_pci_init_irq(struct ath10k *ar)
2646 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2649 ath10k_pci_init_irq_tasklets(ar);
2651 if (ath10k_pci_irq_mode != ATH10K_PCI_IRQ_AUTO)
2652 ath10k_info(ar, "limiting irq mode to: %d\n",
2653 ath10k_pci_irq_mode);
2656 if (ath10k_pci_irq_mode == ATH10K_PCI_IRQ_AUTO) {
2657 ar_pci->num_msi_intrs = MSI_ASSIGN_CE_MAX + 1;
2658 ret = pci_enable_msi_range(ar_pci->pdev, ar_pci->num_msi_intrs,
2659 ar_pci->num_msi_intrs);
2667 if (ath10k_pci_irq_mode != ATH10K_PCI_IRQ_LEGACY) {
2668 ar_pci->num_msi_intrs = 1;
2669 ret = pci_enable_msi(ar_pci->pdev);
2678 * A potential race occurs here: The CORE_BASE write
2679 * depends on target correctly decoding AXI address but
2680 * host won't know when target writes BAR to CORE_CTRL.
2681 * This write might get lost if target has NOT written BAR.
2682 * For now, fix the race by repeating the write in below
2683 * synchronization checking. */
2684 ar_pci->num_msi_intrs = 0;
2686 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,
2687 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL);
2692 static void ath10k_pci_deinit_irq_legacy(struct ath10k *ar)
2694 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,
2698 static int ath10k_pci_deinit_irq(struct ath10k *ar)
2700 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2702 switch (ar_pci->num_msi_intrs) {
2704 ath10k_pci_deinit_irq_legacy(ar);
2707 pci_disable_msi(ar_pci->pdev);
2714 static int ath10k_pci_wait_for_target_init(struct ath10k *ar)
2716 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2717 unsigned long timeout;
2720 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot waiting target to initialise\n");
2722 timeout = jiffies + msecs_to_jiffies(ATH10K_PCI_TARGET_WAIT);
2725 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS);
2727 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot target indicator %x\n",
2730 /* target should never return this */
2731 if (val == 0xffffffff)
2734 /* the device has crashed so don't bother trying anymore */
2735 if (val & FW_IND_EVENT_PENDING)
2738 if (val & FW_IND_INITIALIZED)
2741 if (ar_pci->num_msi_intrs == 0)
2742 /* Fix potential race by repeating CORE_BASE writes */
2743 ath10k_pci_enable_legacy_irq(ar);
2746 } while (time_before(jiffies, timeout));
2748 ath10k_pci_disable_and_clear_legacy_irq(ar);
2749 ath10k_pci_irq_msi_fw_mask(ar);
2751 if (val == 0xffffffff) {
2752 ath10k_err(ar, "failed to read device register, device is gone\n");
2756 if (val & FW_IND_EVENT_PENDING) {
2757 ath10k_warn(ar, "device has crashed during init\n");
2761 if (!(val & FW_IND_INITIALIZED)) {
2762 ath10k_err(ar, "failed to receive initialized event from target: %08x\n",
2767 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot target initialised\n");
2771 static int ath10k_pci_cold_reset(struct ath10k *ar)
2775 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cold reset\n");
2777 spin_lock_bh(&ar->data_lock);
2779 ar->stats.fw_cold_reset_counter++;
2781 spin_unlock_bh(&ar->data_lock);
2783 /* Put Target, including PCIe, into RESET. */
2784 val = ath10k_pci_reg_read32(ar, SOC_GLOBAL_RESET_ADDRESS);
2786 ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val);
2788 /* After writing into SOC_GLOBAL_RESET to put device into
2789 * reset and pulling out of reset pcie may not be stable
2790 * for any immediate pcie register access and cause bus error,
2791 * add delay before any pcie access request to fix this issue.
2795 /* Pull Target, including PCIe, out of RESET. */
2797 ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val);
2801 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cold reset complete\n");
2806 static int ath10k_pci_claim(struct ath10k *ar)
2808 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2809 struct pci_dev *pdev = ar_pci->pdev;
2812 pci_set_drvdata(pdev, ar);
2814 ret = pci_enable_device(pdev);
2816 ath10k_err(ar, "failed to enable pci device: %d\n", ret);
2820 ret = pci_request_region(pdev, BAR_NUM, "ath");
2822 ath10k_err(ar, "failed to request region BAR%d: %d\n", BAR_NUM,
2827 /* Target expects 32 bit DMA. Enforce it. */
2828 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2830 ath10k_err(ar, "failed to set dma mask to 32-bit: %d\n", ret);
2834 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
2836 ath10k_err(ar, "failed to set consistent dma mask to 32-bit: %d\n",
2841 pci_set_master(pdev);
2843 /* Arrange for access to Target SoC registers. */
2844 ar_pci->mem_len = pci_resource_len(pdev, BAR_NUM);
2845 ar_pci->mem = pci_iomap(pdev, BAR_NUM, 0);
2847 ath10k_err(ar, "failed to iomap BAR%d\n", BAR_NUM);
2852 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot pci_mem 0x%p\n", ar_pci->mem);
2856 pci_clear_master(pdev);
2859 pci_release_region(pdev, BAR_NUM);
2862 pci_disable_device(pdev);
2867 static void ath10k_pci_release(struct ath10k *ar)
2869 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2870 struct pci_dev *pdev = ar_pci->pdev;
2872 pci_iounmap(pdev, ar_pci->mem);
2873 pci_release_region(pdev, BAR_NUM);
2874 pci_clear_master(pdev);
2875 pci_disable_device(pdev);
2878 static bool ath10k_pci_chip_is_supported(u32 dev_id, u32 chip_id)
2880 const struct ath10k_pci_supp_chip *supp_chip;
2882 u32 rev_id = MS(chip_id, SOC_CHIP_ID_REV);
2884 for (i = 0; i < ARRAY_SIZE(ath10k_pci_supp_chips); i++) {
2885 supp_chip = &ath10k_pci_supp_chips[i];
2887 if (supp_chip->dev_id == dev_id &&
2888 supp_chip->rev_id == rev_id)
2895 static int ath10k_pci_probe(struct pci_dev *pdev,
2896 const struct pci_device_id *pci_dev)
2900 struct ath10k_pci *ar_pci;
2901 enum ath10k_hw_rev hw_rev;
2904 switch (pci_dev->device) {
2905 case QCA988X_2_0_DEVICE_ID:
2906 hw_rev = ATH10K_HW_QCA988X;
2908 case QCA6164_2_1_DEVICE_ID:
2909 case QCA6174_2_1_DEVICE_ID:
2910 hw_rev = ATH10K_HW_QCA6174;
2912 case QCA99X0_2_0_DEVICE_ID:
2913 hw_rev = ATH10K_HW_QCA99X0;
2920 ar = ath10k_core_create(sizeof(*ar_pci), &pdev->dev, ATH10K_BUS_PCI,
2921 hw_rev, &ath10k_pci_hif_ops);
2923 dev_err(&pdev->dev, "failed to allocate core\n");
2927 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci probe\n");
2929 ar_pci = ath10k_pci_priv(ar);
2930 ar_pci->pdev = pdev;
2931 ar_pci->dev = &pdev->dev;
2933 ar->dev_id = pci_dev->device;
2935 if (pdev->subsystem_vendor || pdev->subsystem_device)
2936 scnprintf(ar->spec_board_id, sizeof(ar->spec_board_id),
2937 "%04x:%04x:%04x:%04x",
2938 pdev->vendor, pdev->device,
2939 pdev->subsystem_vendor, pdev->subsystem_device);
2941 spin_lock_init(&ar_pci->ce_lock);
2942 spin_lock_init(&ar_pci->ps_lock);
2944 setup_timer(&ar_pci->rx_post_retry, ath10k_pci_rx_replenish_retry,
2946 setup_timer(&ar_pci->ps_timer, ath10k_pci_ps_timer,
2949 ret = ath10k_pci_claim(ar);
2951 ath10k_err(ar, "failed to claim device: %d\n", ret);
2952 goto err_core_destroy;
2955 ret = ath10k_pci_alloc_pipes(ar);
2957 ath10k_err(ar, "failed to allocate copy engine pipes: %d\n",
2962 ath10k_pci_ce_deinit(ar);
2963 ath10k_pci_irq_disable(ar);
2965 ret = ath10k_pci_init_irq(ar);
2967 ath10k_err(ar, "failed to init irqs: %d\n", ret);
2968 goto err_free_pipes;
2971 ath10k_info(ar, "pci irq %s interrupts %d irq_mode %d reset_mode %d\n",
2972 ath10k_pci_get_irq_method(ar), ar_pci->num_msi_intrs,
2973 ath10k_pci_irq_mode, ath10k_pci_reset_mode);
2975 ret = ath10k_pci_request_irq(ar);
2977 ath10k_warn(ar, "failed to request irqs: %d\n", ret);
2978 goto err_deinit_irq;
2981 ret = ath10k_pci_chip_reset(ar);
2983 ath10k_err(ar, "failed to reset chip: %d\n", ret);
2987 chip_id = ath10k_pci_soc_read32(ar, SOC_CHIP_ID_ADDRESS);
2988 if (chip_id == 0xffffffff) {
2989 ath10k_err(ar, "failed to get chip id\n");
2993 if (!ath10k_pci_chip_is_supported(pdev->device, chip_id)) {
2994 ath10k_err(ar, "device %04x with chip_id %08x isn't supported\n",
2995 pdev->device, chip_id);
2999 ret = ath10k_core_register(ar, chip_id);
3001 ath10k_err(ar, "failed to register driver core: %d\n", ret);
3008 ath10k_pci_free_irq(ar);
3009 ath10k_pci_kill_tasklet(ar);
3012 ath10k_pci_deinit_irq(ar);
3015 ath10k_pci_free_pipes(ar);
3018 ath10k_pci_sleep_sync(ar);
3019 ath10k_pci_release(ar);
3022 ath10k_core_destroy(ar);
3027 static void ath10k_pci_remove(struct pci_dev *pdev)
3029 struct ath10k *ar = pci_get_drvdata(pdev);
3030 struct ath10k_pci *ar_pci;
3032 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci remove\n");
3037 ar_pci = ath10k_pci_priv(ar);
3042 ath10k_core_unregister(ar);
3043 ath10k_pci_free_irq(ar);
3044 ath10k_pci_kill_tasklet(ar);
3045 ath10k_pci_deinit_irq(ar);
3046 ath10k_pci_ce_deinit(ar);
3047 ath10k_pci_free_pipes(ar);
3048 ath10k_pci_sleep_sync(ar);
3049 ath10k_pci_release(ar);
3050 ath10k_core_destroy(ar);
3053 MODULE_DEVICE_TABLE(pci, ath10k_pci_id_table);
3055 static struct pci_driver ath10k_pci_driver = {
3056 .name = "ath10k_pci",
3057 .id_table = ath10k_pci_id_table,
3058 .probe = ath10k_pci_probe,
3059 .remove = ath10k_pci_remove,
3062 static int __init ath10k_pci_init(void)
3066 ret = pci_register_driver(&ath10k_pci_driver);
3068 printk(KERN_ERR "failed to register ath10k pci driver: %d\n",
3073 module_init(ath10k_pci_init);
3075 static void __exit ath10k_pci_exit(void)
3077 pci_unregister_driver(&ath10k_pci_driver);
3080 module_exit(ath10k_pci_exit);
3082 MODULE_AUTHOR("Qualcomm Atheros");
3083 MODULE_DESCRIPTION("Driver support for Atheros QCA988X PCIe devices");
3084 MODULE_LICENSE("Dual BSD/GPL");
3086 /* QCA988x 2.0 firmware files */
3087 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" QCA988X_HW_2_0_FW_FILE);
3088 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API2_FILE);
3089 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API3_FILE);
3090 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API4_FILE);
3091 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API5_FILE);
3092 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" QCA988X_HW_2_0_BOARD_DATA_FILE);
3094 /* QCA6174 2.1 firmware files */
3095 MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" ATH10K_FW_API4_FILE);
3096 MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" ATH10K_FW_API5_FILE);
3097 MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" QCA6174_HW_2_1_BOARD_DATA_FILE);
3099 /* QCA6174 3.1 firmware files */
3100 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_FW_API4_FILE);
3101 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_FW_API5_FILE);
3102 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" QCA6174_HW_3_0_BOARD_DATA_FILE);