2 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com>
5 * Permission to use, copy, modify, and distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21 /* TODO: Clean up channel debuging -doesn't work anyway- and start
22 * working on reg. control code using all available eeprom information
23 * -rev. engineering needed- */
27 #include <linux/types.h>
28 #include <linux/average.h>
29 #include <net/mac80211.h>
31 /* RX/TX descriptor hw structs
32 * TODO: Driver part should only see sw structs */
35 /* EEPROM structs/offsets
36 * TODO: Make a more generic struct (eg. add more stuff to ath5k_capabilities)
37 * and clean up common bits, then introduce set/get functions in eeprom.c */
42 #define PCI_DEVICE_ID_ATHEROS_AR5210 0x0007 /* AR5210 */
43 #define PCI_DEVICE_ID_ATHEROS_AR5311 0x0011 /* AR5311 */
44 #define PCI_DEVICE_ID_ATHEROS_AR5211 0x0012 /* AR5211 */
45 #define PCI_DEVICE_ID_ATHEROS_AR5212 0x0013 /* AR5212 */
46 #define PCI_DEVICE_ID_3COM_3CRDAG675 0x0013 /* 3CRDAG675 (Atheros AR5212) */
47 #define PCI_DEVICE_ID_3COM_2_3CRPAG175 0x0013 /* 3CRPAG175 (Atheros AR5212) */
48 #define PCI_DEVICE_ID_ATHEROS_AR5210_AP 0x0207 /* AR5210 (Early) */
49 #define PCI_DEVICE_ID_ATHEROS_AR5212_IBM 0x1014 /* AR5212 (IBM MiniPCI) */
50 #define PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT 0x1107 /* AR5210 (no eeprom) */
51 #define PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT 0x1113 /* AR5212 (no eeprom) */
52 #define PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT 0x1112 /* AR5211 (no eeprom) */
53 #define PCI_DEVICE_ID_ATHEROS_AR5212_FPGA 0xf013 /* AR5212 (emulation board) */
54 #define PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY 0xff12 /* AR5211 (emulation board) */
55 #define PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B 0xf11b /* AR5211 (emulation board) */
56 #define PCI_DEVICE_ID_ATHEROS_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */
57 #define PCI_DEVICE_ID_ATHEROS_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
58 #define PCI_DEVICE_ID_ATHEROS_AR5312_REV8 0x0058 /* AR5312 WMAC (AP43-030) */
59 #define PCI_DEVICE_ID_ATHEROS_AR5212_0014 0x0014 /* AR5212 compatible */
60 #define PCI_DEVICE_ID_ATHEROS_AR5212_0015 0x0015 /* AR5212 compatible */
61 #define PCI_DEVICE_ID_ATHEROS_AR5212_0016 0x0016 /* AR5212 compatible */
62 #define PCI_DEVICE_ID_ATHEROS_AR5212_0017 0x0017 /* AR5212 compatible */
63 #define PCI_DEVICE_ID_ATHEROS_AR5212_0018 0x0018 /* AR5212 compatible */
64 #define PCI_DEVICE_ID_ATHEROS_AR5212_0019 0x0019 /* AR5212 compatible */
65 #define PCI_DEVICE_ID_ATHEROS_AR2413 0x001a /* AR2413 (Griffin-lite) */
66 #define PCI_DEVICE_ID_ATHEROS_AR5413 0x001b /* AR5413 (Eagle) */
67 #define PCI_DEVICE_ID_ATHEROS_AR5424 0x001c /* AR5424 (Condor PCI-E) */
68 #define PCI_DEVICE_ID_ATHEROS_AR5416 0x0023 /* AR5416 */
69 #define PCI_DEVICE_ID_ATHEROS_AR5418 0x0024 /* AR5418 */
71 /****************************\
72 GENERIC DRIVER DEFINITIONS
73 \****************************/
75 #define ATH5K_PRINTF(fmt, ...) printk("%s: " fmt, __func__, ##__VA_ARGS__)
77 #define ATH5K_PRINTK(_sc, _level, _fmt, ...) \
78 printk(_level "ath5k %s: " _fmt, \
79 ((_sc) && (_sc)->hw) ? wiphy_name((_sc)->hw->wiphy) : "", \
82 #define ATH5K_PRINTK_LIMIT(_sc, _level, _fmt, ...) do { \
83 if (net_ratelimit()) \
84 ATH5K_PRINTK(_sc, _level, _fmt, ##__VA_ARGS__); \
87 #define ATH5K_INFO(_sc, _fmt, ...) \
88 ATH5K_PRINTK(_sc, KERN_INFO, _fmt, ##__VA_ARGS__)
90 #define ATH5K_WARN(_sc, _fmt, ...) \
91 ATH5K_PRINTK_LIMIT(_sc, KERN_WARNING, _fmt, ##__VA_ARGS__)
93 #define ATH5K_ERR(_sc, _fmt, ...) \
94 ATH5K_PRINTK_LIMIT(_sc, KERN_ERR, _fmt, ##__VA_ARGS__)
97 * AR5K REGISTER ACCESS
100 /* Some macros to read/write fields */
102 /* First shift, then mask */
103 #define AR5K_REG_SM(_val, _flags) \
104 (((_val) << _flags##_S) & (_flags))
106 /* First mask, then shift */
107 #define AR5K_REG_MS(_val, _flags) \
108 (((_val) & (_flags)) >> _flags##_S)
110 /* Some registers can hold multiple values of interest. For this
111 * reason when we want to write to these registers we must first
112 * retrieve the values which we do not want to clear (lets call this
113 * old_data) and then set the register with this and our new_value:
114 * ( old_data | new_value) */
115 #define AR5K_REG_WRITE_BITS(ah, _reg, _flags, _val) \
116 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & ~(_flags)) | \
117 (((_val) << _flags##_S) & (_flags)), _reg)
119 #define AR5K_REG_MASKED_BITS(ah, _reg, _flags, _mask) \
120 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & \
121 (_mask)) | (_flags), _reg)
123 #define AR5K_REG_ENABLE_BITS(ah, _reg, _flags) \
124 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) | (_flags), _reg)
126 #define AR5K_REG_DISABLE_BITS(ah, _reg, _flags) \
127 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) & ~(_flags), _reg)
129 /* Access to PHY registers */
130 #define AR5K_PHY_READ(ah, _reg) \
131 ath5k_hw_reg_read(ah, (ah)->ah_phy + ((_reg) << 2))
133 #define AR5K_PHY_WRITE(ah, _reg, _val) \
134 ath5k_hw_reg_write(ah, _val, (ah)->ah_phy + ((_reg) << 2))
136 /* Access QCU registers per queue */
137 #define AR5K_REG_READ_Q(ah, _reg, _queue) \
138 (ath5k_hw_reg_read(ah, _reg) & (1 << _queue)) \
140 #define AR5K_REG_WRITE_Q(ah, _reg, _queue) \
141 ath5k_hw_reg_write(ah, (1 << _queue), _reg)
143 #define AR5K_Q_ENABLE_BITS(_reg, _queue) do { \
144 _reg |= 1 << _queue; \
147 #define AR5K_Q_DISABLE_BITS(_reg, _queue) do { \
148 _reg &= ~(1 << _queue); \
151 /* Used while writing initvals */
152 #define AR5K_REG_WAIT(_i) do { \
157 /* Register dumps are done per operation mode */
158 #define AR5K_INI_RFGAIN_5GHZ 0
159 #define AR5K_INI_RFGAIN_2GHZ 1
162 * Some tuneable values (these should be changeable by the user)
163 * TODO: Make use of them and add more options OR use debug/configfs
165 #define AR5K_TUNE_DMA_BEACON_RESP 2
166 #define AR5K_TUNE_SW_BEACON_RESP 10
167 #define AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF 0
168 #define AR5K_TUNE_RADAR_ALERT false
169 #define AR5K_TUNE_MIN_TX_FIFO_THRES 1
170 #define AR5K_TUNE_MAX_TX_FIFO_THRES ((IEEE80211_MAX_FRAME_LEN / 64) + 1)
171 #define AR5K_TUNE_REGISTER_TIMEOUT 20000
172 /* Register for RSSI threshold has a mask of 0xff, so 255 seems to
173 * be the max value. */
174 #define AR5K_TUNE_RSSI_THRES 129
175 /* This must be set when setting the RSSI threshold otherwise it can
176 * prevent a reset. If AR5K_RSSI_THR is read after writing to it
177 * the BMISS_THRES will be seen as 0, seems harware doesn't keep
178 * track of it. Max value depends on harware. For AR5210 this is just 7.
179 * For AR5211+ this seems to be up to 255. */
180 #define AR5K_TUNE_BMISS_THRES 7
181 #define AR5K_TUNE_REGISTER_DWELL_TIME 20000
182 #define AR5K_TUNE_BEACON_INTERVAL 100
183 #define AR5K_TUNE_AIFS 2
184 #define AR5K_TUNE_AIFS_11B 2
185 #define AR5K_TUNE_AIFS_XR 0
186 #define AR5K_TUNE_CWMIN 15
187 #define AR5K_TUNE_CWMIN_11B 31
188 #define AR5K_TUNE_CWMIN_XR 3
189 #define AR5K_TUNE_CWMAX 1023
190 #define AR5K_TUNE_CWMAX_11B 1023
191 #define AR5K_TUNE_CWMAX_XR 7
192 #define AR5K_TUNE_NOISE_FLOOR -72
193 #define AR5K_TUNE_CCA_MAX_GOOD_VALUE -95
194 #define AR5K_TUNE_MAX_TXPOWER 63
195 #define AR5K_TUNE_DEFAULT_TXPOWER 25
196 #define AR5K_TUNE_TPC_TXPOWER false
197 #define ATH5K_TUNE_CALIBRATION_INTERVAL_FULL 10000 /* 10 sec */
198 #define ATH5K_TUNE_CALIBRATION_INTERVAL_ANI 1000 /* 1 sec */
199 #define ATH5K_TUNE_CALIBRATION_INTERVAL_NF 60000 /* 60 sec */
201 #define ATH5K_TX_COMPLETE_POLL_INT 3000 /* 3 sec */
203 #define AR5K_INIT_CARR_SENSE_EN 1
205 /*Swap RX/TX Descriptor for big endian archs*/
206 #if defined(__BIG_ENDIAN)
207 #define AR5K_INIT_CFG ( \
208 AR5K_CFG_SWTD | AR5K_CFG_SWRD \
211 #define AR5K_INIT_CFG 0x00000000
215 #define AR5K_INIT_CYCRSSI_THR1 2
217 /* Tx retry limits */
218 #define AR5K_INIT_SH_RETRY 10
219 #define AR5K_INIT_LG_RETRY AR5K_INIT_SH_RETRY
220 /* For station mode */
221 #define AR5K_INIT_SSH_RETRY 32
222 #define AR5K_INIT_SLG_RETRY AR5K_INIT_SSH_RETRY
223 #define AR5K_INIT_TX_RETRY 10
227 #define AR5K_INIT_SLOT_TIME_TURBO 6
228 #define AR5K_INIT_SLOT_TIME_DEFAULT 9
229 #define AR5K_INIT_SLOT_TIME_HALF_RATE 13
230 #define AR5K_INIT_SLOT_TIME_QUARTER_RATE 21
231 #define AR5K_INIT_SLOT_TIME_B 20
232 #define AR5K_SLOT_TIME_MAX 0xffff
235 #define AR5K_INIT_SIFS_TURBO 6
236 /* XXX: 8 from initvals 10 from standard */
237 #define AR5K_INIT_SIFS_DEFAULT_BG 8
238 #define AR5K_INIT_SIFS_DEFAULT_A 16
239 #define AR5K_INIT_SIFS_HALF_RATE 32
240 #define AR5K_INIT_SIFS_QUARTER_RATE 64
242 /* Used to calculate tx time for non 5/10/40MHz
244 /* It's preamble time + signal time (16 + 4) */
245 #define AR5K_INIT_OFDM_PREAMPLE_TIME 20
246 /* Preamble time for 40MHz (turbo) operation (min ?) */
247 #define AR5K_INIT_OFDM_PREAMBLE_TIME_MIN 14
248 #define AR5K_INIT_OFDM_SYMBOL_TIME 4
249 #define AR5K_INIT_OFDM_PLCP_BITS 22
251 /* Rx latency for 5 and 10MHz operation (max ?) */
252 #define AR5K_INIT_RX_LAT_MAX 63
253 /* Tx latencies from initvals (5212 only but no problem
254 * because we only tweak them on 5212) */
255 #define AR5K_INIT_TX_LAT_A 54
256 #define AR5K_INIT_TX_LAT_BG 384
257 /* Tx latency for 40MHz (turbo) operation (min ?) */
258 #define AR5K_INIT_TX_LAT_MIN 32
259 /* Default Tx/Rx latencies (same for 5211)*/
260 #define AR5K_INIT_TX_LATENCY_5210 54
261 #define AR5K_INIT_RX_LATENCY_5210 29
263 /* Tx frame to Tx data start delay */
264 #define AR5K_INIT_TXF2TXD_START_DEFAULT 14
265 #define AR5K_INIT_TXF2TXD_START_DELAY_10MHZ 12
266 #define AR5K_INIT_TXF2TXD_START_DELAY_5MHZ 13
268 /* We need to increase PHY switch and agc settling time
270 #define AR5K_SWITCH_SETTLING 5760
271 #define AR5K_SWITCH_SETTLING_TURBO 7168
273 #define AR5K_AGC_SETTLING 28
274 /* 38 on 5210 but shouldn't matter */
275 #define AR5K_AGC_SETTLING_TURBO 37
278 /* GENERIC CHIPSET DEFINITIONS */
300 * Common silicon revision/version values
303 enum ath5k_srev_type {
308 struct ath5k_srev_name {
310 enum ath5k_srev_type sr_type;
314 #define AR5K_SREV_UNKNOWN 0xffff
316 #define AR5K_SREV_AR5210 0x00 /* Crete */
317 #define AR5K_SREV_AR5311 0x10 /* Maui 1 */
318 #define AR5K_SREV_AR5311A 0x20 /* Maui 2 */
319 #define AR5K_SREV_AR5311B 0x30 /* Spirit */
320 #define AR5K_SREV_AR5211 0x40 /* Oahu */
321 #define AR5K_SREV_AR5212 0x50 /* Venice */
322 #define AR5K_SREV_AR5212_V4 0x54 /* ??? */
323 #define AR5K_SREV_AR5213 0x55 /* ??? */
324 #define AR5K_SREV_AR5213A 0x59 /* Hainan */
325 #define AR5K_SREV_AR2413 0x78 /* Griffin lite */
326 #define AR5K_SREV_AR2414 0x70 /* Griffin */
327 #define AR5K_SREV_AR5424 0x90 /* Condor */
328 #define AR5K_SREV_AR5413 0xa4 /* Eagle lite */
329 #define AR5K_SREV_AR5414 0xa0 /* Eagle */
330 #define AR5K_SREV_AR2415 0xb0 /* Talon */
331 #define AR5K_SREV_AR5416 0xc0 /* PCI-E */
332 #define AR5K_SREV_AR5418 0xca /* PCI-E */
333 #define AR5K_SREV_AR2425 0xe0 /* Swan */
334 #define AR5K_SREV_AR2417 0xf0 /* Nala */
336 #define AR5K_SREV_RAD_5110 0x00
337 #define AR5K_SREV_RAD_5111 0x10
338 #define AR5K_SREV_RAD_5111A 0x15
339 #define AR5K_SREV_RAD_2111 0x20
340 #define AR5K_SREV_RAD_5112 0x30
341 #define AR5K_SREV_RAD_5112A 0x35
342 #define AR5K_SREV_RAD_5112B 0x36
343 #define AR5K_SREV_RAD_2112 0x40
344 #define AR5K_SREV_RAD_2112A 0x45
345 #define AR5K_SREV_RAD_2112B 0x46
346 #define AR5K_SREV_RAD_2413 0x50
347 #define AR5K_SREV_RAD_5413 0x60
348 #define AR5K_SREV_RAD_2316 0x70 /* Cobra SoC */
349 #define AR5K_SREV_RAD_2317 0x80
350 #define AR5K_SREV_RAD_5424 0xa0 /* Mostly same as 5413 */
351 #define AR5K_SREV_RAD_2425 0xa2
352 #define AR5K_SREV_RAD_5133 0xc0
354 #define AR5K_SREV_PHY_5211 0x30
355 #define AR5K_SREV_PHY_5212 0x41
356 #define AR5K_SREV_PHY_5212A 0x42
357 #define AR5K_SREV_PHY_5212B 0x43
358 #define AR5K_SREV_PHY_2413 0x45
359 #define AR5K_SREV_PHY_5413 0x61
360 #define AR5K_SREV_PHY_2425 0x70
362 /* TODO add support to mac80211 for vendor-specific rates and modes */
365 * Some of this information is based on Documentation from:
367 * http://madwifi-project.org/wiki/ChipsetFeatures/SuperAG
369 * Modulation for Atheros' eXtended Range - range enhancing extension that is
370 * supposed to double the distance an Atheros client device can keep a
371 * connection with an Atheros access point. This is achieved by increasing
372 * the receiver sensitivity up to, -105dBm, which is about 20dB above what
373 * the 802.11 specifications demand. In addition, new (proprietary) data rates
374 * are introduced: 3, 2, 1, 0.5 and 0.25 MBit/s.
376 * Please note that can you either use XR or TURBO but you cannot use both,
377 * they are exclusive.
380 #define MODULATION_XR 0x00000200
382 * Modulation for Atheros' Turbo G and Turbo A, its supposed to provide a
383 * throughput transmission speed up to 40Mbit/s-60Mbit/s at a 108Mbit/s
384 * signaling rate achieved through the bonding of two 54Mbit/s 802.11g
385 * channels. To use this feature your Access Point must also suport it.
386 * There is also a distinction between "static" and "dynamic" turbo modes:
388 * - Static: is the dumb version: devices set to this mode stick to it until
389 * the mode is turned off.
390 * - Dynamic: is the intelligent version, the network decides itself if it
391 * is ok to use turbo. As soon as traffic is detected on adjacent channels
392 * (which would get used in turbo mode), or when a non-turbo station joins
393 * the network, turbo mode won't be used until the situation changes again.
394 * Dynamic mode is achieved by Atheros' Adaptive Radio (AR) feature which
395 * monitors the used radio band in order to decide whether turbo mode may
398 * This article claims Super G sticks to bonding of channels 5 and 6 for
401 * http://www.pcworld.com/article/id,113428-page,1/article.html
403 * The channel bonding seems to be driver specific though. In addition to
404 * deciding what channels will be used, these "Turbo" modes are accomplished
405 * by also enabling the following features:
407 * - Bursting: allows multiple frames to be sent at once, rather than pausing
408 * after each frame. Bursting is a standards-compliant feature that can be
409 * used with any Access Point.
410 * - Fast frames: increases the amount of information that can be sent per
411 * frame, also resulting in a reduction of transmission overhead. It is a
412 * proprietary feature that needs to be supported by the Access Point.
413 * - Compression: data frames are compressed in real time using a Lempel Ziv
414 * algorithm. This is done transparently. Once this feature is enabled,
415 * compression and decompression takes place inside the chipset, without
416 * putting additional load on the host CPU.
419 #define MODULATION_TURBO 0x00000080
421 enum ath5k_driver_mode {
429 enum ath5k_ant_mode {
430 AR5K_ANTMODE_DEFAULT = 0, /* default antenna setup */
431 AR5K_ANTMODE_FIXED_A = 1, /* only antenna A is present */
432 AR5K_ANTMODE_FIXED_B = 2, /* only antenna B is present */
433 AR5K_ANTMODE_SINGLE_AP = 3, /* sta locked on a single ap */
434 AR5K_ANTMODE_SECTOR_AP = 4, /* AP with tx antenna set on tx desc */
435 AR5K_ANTMODE_SECTOR_STA = 5, /* STA with tx antenna set on tx desc */
436 AR5K_ANTMODE_DEBUG = 6, /* Debug mode -A -> Rx, B-> Tx- */
441 AR5K_BWMODE_DEFAULT = 0, /* 20MHz, default operation */
442 AR5K_BWMODE_5MHZ = 1, /* Quarter rate */
443 AR5K_BWMODE_10MHZ = 2, /* Half rate */
444 AR5K_BWMODE_40MHZ = 3 /* Turbo */
452 * TX Status descriptor
454 struct ath5k_tx_status {
468 #define AR5K_TXSTAT_ALTRATE 0x80
469 #define AR5K_TXERR_XRETRY 0x01
470 #define AR5K_TXERR_FILT 0x02
471 #define AR5K_TXERR_FIFO 0x04
474 * enum ath5k_tx_queue - Queue types used to classify tx queues.
475 * @AR5K_TX_QUEUE_INACTIVE: q is unused -- see ath5k_hw_release_tx_queue
476 * @AR5K_TX_QUEUE_DATA: A normal data queue
477 * @AR5K_TX_QUEUE_XR_DATA: An XR-data queue
478 * @AR5K_TX_QUEUE_BEACON: The beacon queue
479 * @AR5K_TX_QUEUE_CAB: The after-beacon queue
480 * @AR5K_TX_QUEUE_UAPSD: Unscheduled Automatic Power Save Delivery queue
482 enum ath5k_tx_queue {
483 AR5K_TX_QUEUE_INACTIVE = 0,
485 AR5K_TX_QUEUE_XR_DATA,
486 AR5K_TX_QUEUE_BEACON,
491 #define AR5K_NUM_TX_QUEUES 10
492 #define AR5K_NUM_TX_QUEUES_NOQCU 2
495 * Queue syb-types to classify normal data queues.
496 * These are the 4 Access Categories as defined in
497 * WME spec. 0 is the lowest priority and 4 is the
498 * highest. Normal data that hasn't been classified
499 * goes to the Best Effort AC.
501 enum ath5k_tx_queue_subtype {
502 AR5K_WME_AC_BK = 0, /*Background traffic*/
503 AR5K_WME_AC_BE, /*Best-effort (normal) traffic)*/
504 AR5K_WME_AC_VI, /*Video traffic*/
505 AR5K_WME_AC_VO, /*Voice traffic*/
509 * Queue ID numbers as returned by the hw functions, each number
510 * represents a hw queue. If hw does not support hw queues
511 * (eg 5210) all data goes in one queue. These match
512 * d80211 definitions (net80211/MadWiFi don't use them).
514 enum ath5k_tx_queue_id {
515 AR5K_TX_QUEUE_ID_NOQCU_DATA = 0,
516 AR5K_TX_QUEUE_ID_NOQCU_BEACON = 1,
517 AR5K_TX_QUEUE_ID_DATA_MIN = 0, /*IEEE80211_TX_QUEUE_DATA0*/
518 AR5K_TX_QUEUE_ID_DATA_MAX = 4, /*IEEE80211_TX_QUEUE_DATA4*/
519 AR5K_TX_QUEUE_ID_DATA_SVP = 5, /*IEEE80211_TX_QUEUE_SVP - Spectralink Voice Protocol*/
520 AR5K_TX_QUEUE_ID_CAB = 6, /*IEEE80211_TX_QUEUE_AFTER_BEACON*/
521 AR5K_TX_QUEUE_ID_BEACON = 7, /*IEEE80211_TX_QUEUE_BEACON*/
522 AR5K_TX_QUEUE_ID_UAPSD = 8,
523 AR5K_TX_QUEUE_ID_XR_DATA = 9,
527 * Flags to set hw queue's parameters...
529 #define AR5K_TXQ_FLAG_TXOKINT_ENABLE 0x0001 /* Enable TXOK interrupt */
530 #define AR5K_TXQ_FLAG_TXERRINT_ENABLE 0x0002 /* Enable TXERR interrupt */
531 #define AR5K_TXQ_FLAG_TXEOLINT_ENABLE 0x0004 /* Enable TXEOL interrupt -not used- */
532 #define AR5K_TXQ_FLAG_TXDESCINT_ENABLE 0x0008 /* Enable TXDESC interrupt -not used- */
533 #define AR5K_TXQ_FLAG_TXURNINT_ENABLE 0x0010 /* Enable TXURN interrupt */
534 #define AR5K_TXQ_FLAG_CBRORNINT_ENABLE 0x0020 /* Enable CBRORN interrupt */
535 #define AR5K_TXQ_FLAG_CBRURNINT_ENABLE 0x0040 /* Enable CBRURN interrupt */
536 #define AR5K_TXQ_FLAG_QTRIGINT_ENABLE 0x0080 /* Enable QTRIG interrupt */
537 #define AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE 0x0100 /* Enable TXNOFRM interrupt */
538 #define AR5K_TXQ_FLAG_BACKOFF_DISABLE 0x0200 /* Disable random post-backoff */
539 #define AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE 0x0300 /* Enable ready time expiry policy (?)*/
540 #define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE 0x0800 /* Enable backoff while bursting */
541 #define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS 0x1000 /* Disable backoff while bursting */
542 #define AR5K_TXQ_FLAG_COMPRESSION_ENABLE 0x2000 /* Enable hw compression -not implemented-*/
545 * A struct to hold tx queue's parameters
547 struct ath5k_txq_info {
548 enum ath5k_tx_queue tqi_type;
549 enum ath5k_tx_queue_subtype tqi_subtype;
550 u16 tqi_flags; /* Tx queue flags (see above) */
551 u8 tqi_aifs; /* Arbitrated Interframe Space */
552 u16 tqi_cw_min; /* Minimum Contention Window */
553 u16 tqi_cw_max; /* Maximum Contention Window */
554 u32 tqi_cbr_period; /* Constant bit rate period */
555 u32 tqi_cbr_overflow_limit;
557 u32 tqi_ready_time; /* Time queue waits after an event */
561 * Transmit packet types.
562 * used on tx control descriptor
564 enum ath5k_pkt_type {
565 AR5K_PKT_TYPE_NORMAL = 0,
566 AR5K_PKT_TYPE_ATIM = 1,
567 AR5K_PKT_TYPE_PSPOLL = 2,
568 AR5K_PKT_TYPE_BEACON = 3,
569 AR5K_PKT_TYPE_PROBE_RESP = 4,
570 AR5K_PKT_TYPE_PIFS = 5,
574 * TX power and TPC settings
576 #define AR5K_TXPOWER_OFDM(_r, _v) ( \
577 ((0 & 1) << ((_v) + 6)) | \
578 (((ah->ah_txpower.txp_rates_power_table[(_r)]) & 0x3f) << (_v)) \
581 #define AR5K_TXPOWER_CCK(_r, _v) ( \
582 (ah->ah_txpower.txp_rates_power_table[(_r)] & 0x3f) << (_v) \
586 * DMA size definitions (2^(n+2))
605 * RX Status descriptor
607 struct ath5k_rx_status {
619 #define AR5K_RXERR_CRC 0x01
620 #define AR5K_RXERR_PHY 0x02
621 #define AR5K_RXERR_FIFO 0x04
622 #define AR5K_RXERR_DECRYPT 0x08
623 #define AR5K_RXERR_MIC 0x10
624 #define AR5K_RXKEYIX_INVALID ((u8) - 1)
625 #define AR5K_TXKEYIX_INVALID ((u32) - 1)
628 /**************************\
629 BEACON TIMERS DEFINITIONS
630 \**************************/
632 #define AR5K_BEACON_PERIOD 0x0000ffff
633 #define AR5K_BEACON_ENA 0x00800000 /*enable beacon xmit*/
634 #define AR5K_BEACON_RESET_TSF 0x01000000 /*force a TSF reset*/
638 * TSF to TU conversion:
640 * TSF is a 64bit value in usec (microseconds).
641 * TU is a 32bit value and defined by IEEE802.11 (page 6) as "A measurement of
642 * time equal to 1024 usec", so it's roughly milliseconds (usec / 1024).
644 #define TSF_TO_TU(_tsf) (u32)((_tsf) >> 10)
647 /*******************************\
648 GAIN OPTIMIZATION DEFINITIONS
649 \*******************************/
652 AR5K_RFGAIN_INACTIVE = 0,
654 AR5K_RFGAIN_READ_REQUESTED,
655 AR5K_RFGAIN_NEED_CHANGE,
668 /********************\
670 \********************/
672 #define AR5K_SLOT_TIME_9 396
673 #define AR5K_SLOT_TIME_20 880
674 #define AR5K_SLOT_TIME_MAX 0xffff
677 #define CHANNEL_CW_INT 0x0008 /* Contention Window interference detected */
678 #define CHANNEL_CCK 0x0020 /* CCK channel */
679 #define CHANNEL_OFDM 0x0040 /* OFDM channel */
680 #define CHANNEL_2GHZ 0x0080 /* 2GHz channel. */
681 #define CHANNEL_5GHZ 0x0100 /* 5GHz channel */
682 #define CHANNEL_PASSIVE 0x0200 /* Only passive scan allowed */
683 #define CHANNEL_DYN 0x0400 /* Dynamic CCK-OFDM channel (for g operation) */
684 #define CHANNEL_XR 0x0800 /* XR channel */
686 #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
687 #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
688 #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
689 #define CHANNEL_X (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR)
691 #define CHANNEL_ALL (CHANNEL_OFDM|CHANNEL_CCK|CHANNEL_2GHZ|CHANNEL_5GHZ)
693 #define CHANNEL_MODES CHANNEL_ALL
696 * Used internaly for reset_tx_queue).
697 * Also see struct struct ieee80211_channel.
699 #define IS_CHAN_XR(_c) ((_c->hw_value & CHANNEL_XR) != 0)
700 #define IS_CHAN_B(_c) ((_c->hw_value & CHANNEL_B) != 0)
703 * The following structure is used to map 2GHz channels to
704 * 5GHz Atheros channels.
707 struct ath5k_athchan_2ghz {
718 * Seems the ar5xxx harware supports up to 32 rates, indexed by 1-32.
720 * The rate code is used to get the RX rate or set the TX rate on the
721 * hardware descriptors. It is also used for internal modulation control
724 * This is the hardware rate map we are aware of:
726 * rate_code 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08
727 * rate_kbps 3000 1000 ? ? ? 2000 500 48000
729 * rate_code 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10
730 * rate_kbps 24000 12000 6000 54000 36000 18000 9000 ?
732 * rate_code 17 18 19 20 21 22 23 24
733 * rate_kbps ? ? ? ? ? ? ? 11000
735 * rate_code 25 26 27 28 29 30 31 32
736 * rate_kbps 5500 2000 1000 11000S 5500S 2000S ? ?
738 * "S" indicates CCK rates with short preamble.
740 * AR5211 has different rate codes for CCK (802.11B) rates. It only uses the
741 * lowest 4 bits, so they are the same as below with a 0xF mask.
742 * (0xB, 0xA, 0x9 and 0x8 for 1M, 2M, 5.5M and 11M).
743 * We handle this in ath5k_setup_bands().
745 #define AR5K_MAX_RATES 32
748 #define ATH5K_RATE_CODE_1M 0x1B
749 #define ATH5K_RATE_CODE_2M 0x1A
750 #define ATH5K_RATE_CODE_5_5M 0x19
751 #define ATH5K_RATE_CODE_11M 0x18
753 #define ATH5K_RATE_CODE_6M 0x0B
754 #define ATH5K_RATE_CODE_9M 0x0F
755 #define ATH5K_RATE_CODE_12M 0x0A
756 #define ATH5K_RATE_CODE_18M 0x0E
757 #define ATH5K_RATE_CODE_24M 0x09
758 #define ATH5K_RATE_CODE_36M 0x0D
759 #define ATH5K_RATE_CODE_48M 0x08
760 #define ATH5K_RATE_CODE_54M 0x0C
762 #define ATH5K_RATE_CODE_XR_500K 0x07
763 #define ATH5K_RATE_CODE_XR_1M 0x02
764 #define ATH5K_RATE_CODE_XR_2M 0x06
765 #define ATH5K_RATE_CODE_XR_3M 0x01
767 /* adding this flag to rate_code enables short preamble */
768 #define AR5K_SET_SHORT_PREAMBLE 0x04
774 #define AR5K_KEYCACHE_SIZE 8
776 /***********************\
777 HW RELATED DEFINITIONS
778 \***********************/
783 #define AR5K_RSSI_EP_MULTIPLIER (1<<7)
785 #define AR5K_ASSERT_ENTRY(_e, _s) do { \
791 * Hardware interrupt abstraction
795 * enum ath5k_int - Hardware interrupt masks helpers
797 * @AR5K_INT_RX: mask to identify received frame interrupts, of type
798 * AR5K_ISR_RXOK or AR5K_ISR_RXERR
799 * @AR5K_INT_RXDESC: Request RX descriptor/Read RX descriptor (?)
800 * @AR5K_INT_RXNOFRM: No frame received (?)
801 * @AR5K_INT_RXEOL: received End Of List for VEOL (Virtual End Of List). The
802 * Queue Control Unit (QCU) signals an EOL interrupt only if a descriptor's
803 * LinkPtr is NULL. For more details, refer to:
804 * http://www.freepatentsonline.com/20030225739.html
805 * @AR5K_INT_RXORN: Indicates we got RX overrun (eg. no more descriptors).
806 * Note that Rx overrun is not always fatal, on some chips we can continue
807 * operation without reseting the card, that's why int_fatal is not
808 * common for all chips.
809 * @AR5K_INT_TX: mask to identify received frame interrupts, of type
810 * AR5K_ISR_TXOK or AR5K_ISR_TXERR
811 * @AR5K_INT_TXDESC: Request TX descriptor/Read TX status descriptor (?)
812 * @AR5K_INT_TXURN: received when we should increase the TX trigger threshold
813 * We currently do increments on interrupt by
814 * (AR5K_TUNE_MAX_TX_FIFO_THRES - current_trigger_level) / 2
815 * @AR5K_INT_MIB: Indicates the either Management Information Base counters or
816 * one of the PHY error counters reached the maximum value and should be
818 * @AR5K_INT_RXPHY: RX PHY Error
819 * @AR5K_INT_RXKCM: RX Key cache miss
820 * @AR5K_INT_SWBA: SoftWare Beacon Alert - indicates its time to send a
821 * beacon that must be handled in software. The alternative is if you
822 * have VEOL support, in that case you let the hardware deal with things.
823 * @AR5K_INT_BMISS: If in STA mode this indicates we have stopped seeing
824 * beacons from the AP have associated with, we should probably try to
825 * reassociate. When in IBSS mode this might mean we have not received
826 * any beacons from any local stations. Note that every station in an
827 * IBSS schedules to send beacons at the Target Beacon Transmission Time
828 * (TBTT) with a random backoff.
829 * @AR5K_INT_BNR: Beacon Not Ready interrupt - ??
830 * @AR5K_INT_GPIO: GPIO interrupt is used for RF Kill, disabled for now
831 * until properly handled
832 * @AR5K_INT_FATAL: Fatal errors were encountered, typically caused by DMA
833 * errors. These types of errors we can enable seem to be of type
834 * AR5K_SIMR2_MCABT, AR5K_SIMR2_SSERR and AR5K_SIMR2_DPERR.
835 * @AR5K_INT_GLOBAL: Used to clear and set the IER
836 * @AR5K_INT_NOCARD: signals the card has been removed
837 * @AR5K_INT_COMMON: common interrupts shared amogst MACs with the same
840 * These are mapped to take advantage of some common bits
841 * between the MACs, to be able to set intr properties
842 * easier. Some of them are not used yet inside hw.c. Most map
843 * to the respective hw interrupt value as they are common amogst different
847 AR5K_INT_RXOK = 0x00000001,
848 AR5K_INT_RXDESC = 0x00000002,
849 AR5K_INT_RXERR = 0x00000004,
850 AR5K_INT_RXNOFRM = 0x00000008,
851 AR5K_INT_RXEOL = 0x00000010,
852 AR5K_INT_RXORN = 0x00000020,
853 AR5K_INT_TXOK = 0x00000040,
854 AR5K_INT_TXDESC = 0x00000080,
855 AR5K_INT_TXERR = 0x00000100,
856 AR5K_INT_TXNOFRM = 0x00000200,
857 AR5K_INT_TXEOL = 0x00000400,
858 AR5K_INT_TXURN = 0x00000800,
859 AR5K_INT_MIB = 0x00001000,
860 AR5K_INT_SWI = 0x00002000,
861 AR5K_INT_RXPHY = 0x00004000,
862 AR5K_INT_RXKCM = 0x00008000,
863 AR5K_INT_SWBA = 0x00010000,
864 AR5K_INT_BRSSI = 0x00020000,
865 AR5K_INT_BMISS = 0x00040000,
866 AR5K_INT_FATAL = 0x00080000, /* Non common */
867 AR5K_INT_BNR = 0x00100000, /* Non common */
868 AR5K_INT_TIM = 0x00200000, /* Non common */
869 AR5K_INT_DTIM = 0x00400000, /* Non common */
870 AR5K_INT_DTIM_SYNC = 0x00800000, /* Non common */
871 AR5K_INT_GPIO = 0x01000000,
872 AR5K_INT_BCN_TIMEOUT = 0x02000000, /* Non common */
873 AR5K_INT_CAB_TIMEOUT = 0x04000000, /* Non common */
874 AR5K_INT_RX_DOPPLER = 0x08000000, /* Non common */
875 AR5K_INT_QCBRORN = 0x10000000, /* Non common */
876 AR5K_INT_QCBRURN = 0x20000000, /* Non common */
877 AR5K_INT_QTRIG = 0x40000000, /* Non common */
878 AR5K_INT_GLOBAL = 0x80000000,
880 AR5K_INT_COMMON = AR5K_INT_RXOK
902 AR5K_INT_NOCARD = 0xffffffff
905 /* mask which calibration is active at the moment */
906 enum ath5k_calibration_mask {
907 AR5K_CALIBRATION_FULL = 0x01,
908 AR5K_CALIBRATION_SHORT = 0x02,
909 AR5K_CALIBRATION_ANI = 0x04,
915 enum ath5k_power_mode {
916 AR5K_PM_UNDEFINED = 0,
920 AR5K_PM_NETWORK_SLEEP,
924 * These match net80211 definitions (not used in
926 * TODO: Clean this up
928 #define AR5K_LED_INIT 0 /*IEEE80211_S_INIT*/
929 #define AR5K_LED_SCAN 1 /*IEEE80211_S_SCAN*/
930 #define AR5K_LED_AUTH 2 /*IEEE80211_S_AUTH*/
931 #define AR5K_LED_ASSOC 3 /*IEEE80211_S_ASSOC*/
932 #define AR5K_LED_RUN 4 /*IEEE80211_S_RUN*/
934 /* GPIO-controlled software LED */
935 #define AR5K_SOFTLED_PIN 0
936 #define AR5K_SOFTLED_ON 0
937 #define AR5K_SOFTLED_OFF 1
940 * Chipset capabilities -see ath5k_hw_get_capability-
941 * get_capability function is not yet fully implemented
942 * in ath5k so most of these don't work yet...
943 * TODO: Implement these & merge with _TUNE_ stuff above
945 enum ath5k_capability_type {
946 AR5K_CAP_REG_DMN = 0, /* Used to get current reg. domain id */
947 AR5K_CAP_TKIP_MIC = 2, /* Can handle TKIP MIC in hardware */
948 AR5K_CAP_TKIP_SPLIT = 3, /* TKIP uses split keys */
949 AR5K_CAP_PHYCOUNTERS = 4, /* PHY error counters */
950 AR5K_CAP_DIVERSITY = 5, /* Supports fast diversity */
951 AR5K_CAP_NUM_TXQUEUES = 6, /* Used to get max number of hw txqueues */
952 AR5K_CAP_VEOL = 7, /* Supports virtual EOL */
953 AR5K_CAP_COMPRESSION = 8, /* Supports compression */
954 AR5K_CAP_BURST = 9, /* Supports packet bursting */
955 AR5K_CAP_FASTFRAME = 10, /* Supports fast frames */
956 AR5K_CAP_TXPOW = 11, /* Used to get global tx power limit */
957 AR5K_CAP_TPC = 12, /* Can do per-packet tx power control (needed for 802.11a) */
958 AR5K_CAP_BSSIDMASK = 13, /* Supports bssid mask */
959 AR5K_CAP_MCAST_KEYSRCH = 14, /* Supports multicast key search */
960 AR5K_CAP_TSF_ADJUST = 15, /* Supports beacon tsf adjust */
961 AR5K_CAP_XR = 16, /* Supports XR mode */
962 AR5K_CAP_WME_TKIPMIC = 17, /* Supports TKIP MIC when using WMM */
963 AR5K_CAP_CHAN_HALFRATE = 18, /* Supports half rate channels */
964 AR5K_CAP_CHAN_QUARTERRATE = 19, /* Supports quarter rate channels */
965 AR5K_CAP_RFSILENT = 20, /* Supports RFsilent */
969 /* XXX: we *may* move cap_range stuff to struct wiphy */
970 struct ath5k_capabilities {
972 * Supported PHY modes
973 * (ie. CHANNEL_A, CHANNEL_B, ...)
975 DECLARE_BITMAP(cap_mode, AR5K_MODE_MAX);
978 * Frequency range (without regulation restrictions)
988 * Values stored in the EEPROM (some of them...)
990 struct ath5k_eeprom_info cap_eeprom;
999 bool cap_has_phyerr_counters;
1002 /* size of noise floor history (keep it a power of two) */
1003 #define ATH5K_NF_CAL_HIST_MAX 8
1004 struct ath5k_nfcal_hist
1006 s16 index; /* current index into nfval */
1007 s16 nfval[ATH5K_NF_CAL_HIST_MAX]; /* last few noise floors */
1011 * struct avg_val - Helper structure for average calculation
1012 * @avg: contains the actual average value
1013 * @avg_weight: is used internally during calculation to prevent rounding errors
1015 struct ath5k_avg_val {
1020 /***************************************\
1021 HARDWARE ABSTRACTION LAYER STRUCTURE
1022 \***************************************/
1028 #define AR5K_MAX_GPIO 10
1029 #define AR5K_MAX_RF_BANKS 8
1031 /* TODO: Clean up and merge with ath5k_softc */
1033 struct ath_common common;
1035 struct ath5k_softc *ah_sc;
1036 void __iomem *ah_iobase;
1038 enum ath5k_int ah_imr;
1040 struct ieee80211_channel *ah_current_channel;
1041 bool ah_calibration;
1042 bool ah_single_chip;
1044 enum ath5k_version ah_version;
1045 enum ath5k_radio ah_radio;
1049 u16 ah_phy_revision;
1050 u16 ah_radio_5ghz_revision;
1051 u16 ah_radio_2ghz_revision;
1053 #define ah_modes ah_capabilities.cap_mode
1054 #define ah_ee_version ah_capabilities.cap_eeprom.ee_version
1056 u32 ah_limit_tx_retries;
1057 u8 ah_coverage_class;
1058 bool ah_ack_bitrate_high;
1061 /* Antenna Control */
1062 u32 ah_ant_ctl[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX];
1066 bool ah_software_retry;
1068 struct ath5k_capabilities ah_capabilities;
1070 struct ath5k_txq_info ah_txq[AR5K_NUM_TX_QUEUES];
1072 u32 ah_txq_imr_txok;
1073 u32 ah_txq_imr_txerr;
1074 u32 ah_txq_imr_txurn;
1075 u32 ah_txq_imr_txdesc;
1076 u32 ah_txq_imr_txeol;
1077 u32 ah_txq_imr_cbrorn;
1078 u32 ah_txq_imr_cbrurn;
1079 u32 ah_txq_imr_qtrig;
1080 u32 ah_txq_imr_nofrm;
1083 size_t ah_rf_banks_size;
1084 size_t ah_rf_regs_count;
1085 struct ath5k_gain ah_gain;
1086 u8 ah_offset[AR5K_MAX_RF_BANKS];
1090 /* Temporary tables used for interpolation */
1091 u8 tmpL[AR5K_EEPROM_N_PD_GAINS]
1092 [AR5K_EEPROM_POWER_TABLE_SIZE];
1093 u8 tmpR[AR5K_EEPROM_N_PD_GAINS]
1094 [AR5K_EEPROM_POWER_TABLE_SIZE];
1095 u8 txp_pd_table[AR5K_EEPROM_POWER_TABLE_SIZE * 2];
1096 u16 txp_rates_power_table[AR5K_MAX_RATES];
1099 /* Values in 0.25dB units */
1102 /* Values in 0.5dB units */
1105 s16 txp_cck_ofdm_gainf_delta;
1106 /* Value in dB units */
1107 s16 txp_cck_ofdm_pwr_delta;
1113 struct ieee80211_channel r_last_channel;
1116 struct ath5k_nfcal_hist ah_nfcal_hist;
1118 /* average beacon RSSI in our BSS (used by ANI) */
1119 struct ewma ah_beacon_rssi_avg;
1121 /* noise floor from last periodic calibration */
1124 /* Calibration timestamp */
1125 unsigned long ah_cal_next_full;
1126 unsigned long ah_cal_next_ani;
1127 unsigned long ah_cal_next_nf;
1129 /* Calibration mask */
1135 int (*ah_setup_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1136 unsigned int, unsigned int, int, enum ath5k_pkt_type,
1137 unsigned int, unsigned int, unsigned int, unsigned int,
1138 unsigned int, unsigned int, unsigned int, unsigned int);
1139 int (*ah_proc_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1140 struct ath5k_tx_status *);
1141 int (*ah_proc_rx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1142 struct ath5k_rx_status *);
1148 extern const struct ieee80211_ops ath5k_hw_ops;
1150 /* Initialization and detach functions */
1151 int ath5k_init_softc(struct ath5k_softc *sc, const struct ath_bus_ops *bus_ops);
1152 void ath5k_deinit_softc(struct ath5k_softc *sc);
1153 int ath5k_hw_init(struct ath5k_softc *sc);
1154 void ath5k_hw_deinit(struct ath5k_hw *ah);
1156 int ath5k_sysfs_register(struct ath5k_softc *sc);
1157 void ath5k_sysfs_unregister(struct ath5k_softc *sc);
1159 /*Chip id helper function */
1160 const char *ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val);
1163 int ath5k_init_leds(struct ath5k_softc *sc);
1164 void ath5k_led_enable(struct ath5k_softc *sc);
1165 void ath5k_led_off(struct ath5k_softc *sc);
1166 void ath5k_unregister_leds(struct ath5k_softc *sc);
1169 /* Reset Functions */
1170 int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial);
1171 int ath5k_hw_on_hold(struct ath5k_hw *ah);
1172 int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
1173 struct ieee80211_channel *channel, bool fast, bool skip_pcu);
1174 int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val,
1176 /* Power management functions */
1179 /* Clock rate related functions */
1180 unsigned int ath5k_hw_htoclock(struct ath5k_hw *ah, unsigned int usec);
1181 unsigned int ath5k_hw_clocktoh(struct ath5k_hw *ah, unsigned int clock);
1182 void ath5k_hw_set_clockrate(struct ath5k_hw *ah);
1185 /* DMA Related Functions */
1186 void ath5k_hw_start_rx_dma(struct ath5k_hw *ah);
1187 u32 ath5k_hw_get_rxdp(struct ath5k_hw *ah);
1188 int ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr);
1189 int ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue);
1190 int ath5k_hw_stop_beacon_queue(struct ath5k_hw *ah, unsigned int queue);
1191 u32 ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue);
1192 int ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue,
1194 int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase);
1195 /* Interrupt handling */
1196 bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah);
1197 int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask);
1198 enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum ath5k_int new_mask);
1199 void ath5k_hw_update_mib_counters(struct ath5k_hw *ah);
1200 /* Init/Stop functions */
1201 void ath5k_hw_dma_init(struct ath5k_hw *ah);
1202 int ath5k_hw_dma_stop(struct ath5k_hw *ah);
1204 /* EEPROM access functions */
1205 int ath5k_eeprom_init(struct ath5k_hw *ah);
1206 void ath5k_eeprom_detach(struct ath5k_hw *ah);
1207 int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac);
1210 /* Protocol Control Unit Functions */
1212 int ath5k_hw_get_frame_duration(struct ath5k_hw *ah,
1213 int len, struct ieee80211_rate *rate);
1214 unsigned int ath5k_hw_get_default_slottime(struct ath5k_hw *ah);
1215 unsigned int ath5k_hw_get_default_sifs(struct ath5k_hw *ah);
1216 extern int ath5k_hw_set_opmode(struct ath5k_hw *ah, enum nl80211_iftype opmode);
1217 void ath5k_hw_set_coverage_class(struct ath5k_hw *ah, u8 coverage_class);
1218 /* RX filter control*/
1219 int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac);
1220 void ath5k_hw_set_bssid(struct ath5k_hw *ah);
1221 void ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask);
1222 void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1);
1223 u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah);
1224 void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter);
1225 /* Receive (DRU) start/stop functions */
1226 void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah);
1227 void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah);
1228 /* Beacon control functions */
1229 u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah);
1230 void ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64);
1231 void ath5k_hw_reset_tsf(struct ath5k_hw *ah);
1232 void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval);
1233 bool ath5k_hw_check_beacon_timers(struct ath5k_hw *ah, int intval);
1235 void ath5k_hw_pcu_init(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
1238 /* Queue Control Unit, DFS Control Unit Functions */
1239 int ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue,
1240 struct ath5k_txq_info *queue_info);
1241 int ath5k_hw_set_tx_queueprops(struct ath5k_hw *ah, int queue,
1242 const struct ath5k_txq_info *queue_info);
1243 int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah,
1244 enum ath5k_tx_queue queue_type,
1245 struct ath5k_txq_info *queue_info);
1246 u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue);
1247 void ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue);
1248 int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue);
1249 int ath5k_hw_set_ifs_intervals(struct ath5k_hw *ah, unsigned int slot_time);
1251 int ath5k_hw_init_queues(struct ath5k_hw *ah);
1253 /* Hardware Descriptor Functions */
1254 int ath5k_hw_init_desc_functions(struct ath5k_hw *ah);
1255 int ath5k_hw_setup_rx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
1256 u32 size, unsigned int flags);
1257 int ath5k_hw_setup_mrr_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
1258 unsigned int tx_rate1, u_int tx_tries1, u_int tx_rate2,
1259 u_int tx_tries2, unsigned int tx_rate3, u_int tx_tries3);
1262 /* GPIO Functions */
1263 void ath5k_hw_set_ledstate(struct ath5k_hw *ah, unsigned int state);
1264 int ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio);
1265 int ath5k_hw_set_gpio_output(struct ath5k_hw *ah, u32 gpio);
1266 u32 ath5k_hw_get_gpio(struct ath5k_hw *ah, u32 gpio);
1267 int ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val);
1268 void ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio,
1269 u32 interrupt_level);
1272 /* RFkill Functions */
1273 void ath5k_rfkill_hw_start(struct ath5k_hw *ah);
1274 void ath5k_rfkill_hw_stop(struct ath5k_hw *ah);
1277 /* Misc functions TODO: Cleanup */
1278 int ath5k_hw_set_capabilities(struct ath5k_hw *ah);
1279 int ath5k_hw_get_capability(struct ath5k_hw *ah,
1280 enum ath5k_capability_type cap_type, u32 capability,
1282 int ath5k_hw_enable_pspoll(struct ath5k_hw *ah, u8 *bssid, u16 assoc_id);
1283 int ath5k_hw_disable_pspoll(struct ath5k_hw *ah);
1286 /* Initial register settings functions */
1287 int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel);
1291 /* Misc PHY functions */
1292 u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan);
1293 int ath5k_hw_phy_disable(struct ath5k_hw *ah);
1294 /* Gain_F optimization */
1295 enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah);
1296 int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah);
1297 /* PHY/RF channel functions */
1298 bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags);
1299 /* PHY calibration */
1300 void ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah);
1301 int ath5k_hw_phy_calibrate(struct ath5k_hw *ah,
1302 struct ieee80211_channel *channel);
1303 void ath5k_hw_update_noise_floor(struct ath5k_hw *ah);
1304 /* Spur mitigation */
1305 bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah,
1306 struct ieee80211_channel *channel);
1307 /* Antenna control */
1308 void ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode);
1309 void ath5k_hw_set_antenna_switch(struct ath5k_hw *ah, u8 ee_mode);
1310 /* TX power setup */
1311 int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower);
1313 int ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
1314 u8 mode, u8 ee_mode, u8 freq, bool fast);
1317 * Functions used internaly
1320 static inline struct ath_common *ath5k_hw_common(struct ath5k_hw *ah)
1325 static inline struct ath_regulatory *ath5k_hw_regulatory(struct ath5k_hw *ah)
1327 return &(ath5k_hw_common(ah)->regulatory);
1330 static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
1332 return ioread32(ah->ah_iobase + reg);
1335 static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
1337 iowrite32(val, ah->ah_iobase + reg);
1340 static inline void ath5k_read_cachesize(struct ath_common *common, int *csz)
1342 common->bus_ops->read_cachesize(common, csz);
1345 static inline u32 ath5k_hw_bitswap(u32 val, unsigned int bits)
1347 u32 retval = 0, bit, i;
1349 for (i = 0; i < bits; i++) {
1350 bit = (val >> i) & 1;
1351 retval = (retval << 1) | bit;