2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
43 #include <linux/module.h>
44 #include <linux/delay.h>
45 #include <linux/hardirq.h>
48 #include <linux/netdevice.h>
49 #include <linux/cache.h>
50 #include <linux/ethtool.h>
51 #include <linux/uaccess.h>
52 #include <linux/slab.h>
53 #include <linux/etherdevice.h>
55 #include <net/ieee80211_radiotap.h>
57 #include <asm/unaligned.h>
65 static int modparam_nohwcrypt;
66 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
67 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
69 static int modparam_all_channels;
70 module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO);
71 MODULE_PARM_DESC(all_channels, "Expose all channels the device can use.");
74 MODULE_AUTHOR("Jiri Slaby");
75 MODULE_AUTHOR("Nick Kossifidis");
76 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
77 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
78 MODULE_LICENSE("Dual BSD/GPL");
79 MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
81 static int ath5k_init(struct ieee80211_hw *hw);
82 static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan,
84 static int ath5k_beacon_update(struct ieee80211_hw *hw,
85 struct ieee80211_vif *vif);
86 static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
89 static const struct ath5k_srev_name srev_names[] = {
90 #ifdef CONFIG_ATHEROS_AR231X
91 { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R2 },
92 { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R7 },
93 { "2313", AR5K_VERSION_MAC, AR5K_SREV_AR2313_R8 },
94 { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R6 },
95 { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R7 },
96 { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R1 },
97 { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R2 },
99 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
100 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
101 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
102 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
103 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
104 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
105 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
106 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
107 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
108 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
109 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
110 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
111 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
112 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
113 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
114 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
115 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
116 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
118 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
119 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
120 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
121 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
122 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
123 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
124 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
125 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
126 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
127 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
128 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
129 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
130 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
131 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
132 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
133 #ifdef CONFIG_ATHEROS_AR231X
134 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
135 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
137 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
140 static const struct ieee80211_rate ath5k_rates[] = {
142 .hw_value = ATH5K_RATE_CODE_1M, },
144 .hw_value = ATH5K_RATE_CODE_2M,
145 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
146 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
148 .hw_value = ATH5K_RATE_CODE_5_5M,
149 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
150 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
152 .hw_value = ATH5K_RATE_CODE_11M,
153 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
154 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
156 .hw_value = ATH5K_RATE_CODE_6M,
159 .hw_value = ATH5K_RATE_CODE_9M,
162 .hw_value = ATH5K_RATE_CODE_12M,
165 .hw_value = ATH5K_RATE_CODE_18M,
168 .hw_value = ATH5K_RATE_CODE_24M,
171 .hw_value = ATH5K_RATE_CODE_36M,
174 .hw_value = ATH5K_RATE_CODE_48M,
177 .hw_value = ATH5K_RATE_CODE_54M,
182 static inline void ath5k_txbuf_free_skb(struct ath5k_softc *sc,
183 struct ath5k_buf *bf)
188 dma_unmap_single(sc->dev, bf->skbaddr, bf->skb->len,
190 dev_kfree_skb_any(bf->skb);
193 bf->desc->ds_data = 0;
196 static inline void ath5k_rxbuf_free_skb(struct ath5k_softc *sc,
197 struct ath5k_buf *bf)
199 struct ath5k_hw *ah = sc->ah;
200 struct ath_common *common = ath5k_hw_common(ah);
205 dma_unmap_single(sc->dev, bf->skbaddr, common->rx_bufsize,
207 dev_kfree_skb_any(bf->skb);
210 bf->desc->ds_data = 0;
214 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
216 u64 tsf = ath5k_hw_get_tsf64(ah);
218 if ((tsf & 0x7fff) < rstamp)
221 return (tsf & ~0x7fff) | rstamp;
225 ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
227 const char *name = "xxxxx";
230 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
231 if (srev_names[i].sr_type != type)
234 if ((val & 0xf0) == srev_names[i].sr_val)
235 name = srev_names[i].sr_name;
237 if ((val & 0xff) == srev_names[i].sr_val) {
238 name = srev_names[i].sr_name;
245 static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset)
247 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
248 return ath5k_hw_reg_read(ah, reg_offset);
251 static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
253 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
254 ath5k_hw_reg_write(ah, val, reg_offset);
257 static const struct ath_ops ath5k_common_ops = {
258 .read = ath5k_ioread32,
259 .write = ath5k_iowrite32,
262 /***********************\
263 * Driver Initialization *
264 \***********************/
266 static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
268 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
269 struct ath5k_softc *sc = hw->priv;
270 struct ath_regulatory *regulatory = ath5k_hw_regulatory(sc->ah);
272 return ath_reg_notifier_apply(wiphy, request, regulatory);
275 /********************\
276 * Channel/mode setup *
277 \********************/
280 * Convert IEEE channel number to MHz frequency.
283 ath5k_ieee2mhz(short chan)
285 if (chan <= 14 || chan >= 27)
286 return ieee80211chan2mhz(chan);
288 return 2212 + chan * 20;
292 * Returns true for the channel numbers used without all_channels modparam.
294 static bool ath5k_is_standard_channel(short chan)
296 return ((chan <= 14) ||
298 ((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
300 ((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
302 ((chan & 3) == 1 && chan >= 149 && chan <= 165));
306 ath5k_copy_channels(struct ath5k_hw *ah,
307 struct ieee80211_channel *channels,
311 unsigned int i, count, size, chfreq, freq, ch;
313 if (!test_bit(mode, ah->ah_modes))
318 /* 1..220, but 2GHz frequencies are filtered by check_channel */
320 chfreq = CHANNEL_5GHZ;
325 chfreq = CHANNEL_2GHZ;
328 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
332 for (i = 0, count = 0; i < size && max > 0; i++) {
334 freq = ath5k_ieee2mhz(ch);
336 /* Check if channel is supported by the chipset */
337 if (!ath5k_channel_ok(ah, freq, chfreq))
340 if (!modparam_all_channels && !ath5k_is_standard_channel(ch))
343 /* Write channel info and increment counter */
344 channels[count].center_freq = freq;
345 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
346 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
350 channels[count].hw_value = chfreq | CHANNEL_OFDM;
353 channels[count].hw_value = CHANNEL_B;
364 ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
368 for (i = 0; i < AR5K_MAX_RATES; i++)
369 sc->rate_idx[b->band][i] = -1;
371 for (i = 0; i < b->n_bitrates; i++) {
372 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
373 if (b->bitrates[i].hw_value_short)
374 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
379 ath5k_setup_bands(struct ieee80211_hw *hw)
381 struct ath5k_softc *sc = hw->priv;
382 struct ath5k_hw *ah = sc->ah;
383 struct ieee80211_supported_band *sband;
384 int max_c, count_c = 0;
387 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
388 max_c = ARRAY_SIZE(sc->channels);
391 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
392 sband->band = IEEE80211_BAND_2GHZ;
393 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
395 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
397 memcpy(sband->bitrates, &ath5k_rates[0],
398 sizeof(struct ieee80211_rate) * 12);
399 sband->n_bitrates = 12;
401 sband->channels = sc->channels;
402 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
403 AR5K_MODE_11G, max_c);
405 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
406 count_c = sband->n_channels;
408 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
410 memcpy(sband->bitrates, &ath5k_rates[0],
411 sizeof(struct ieee80211_rate) * 4);
412 sband->n_bitrates = 4;
414 /* 5211 only supports B rates and uses 4bit rate codes
415 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
418 if (ah->ah_version == AR5K_AR5211) {
419 for (i = 0; i < 4; i++) {
420 sband->bitrates[i].hw_value =
421 sband->bitrates[i].hw_value & 0xF;
422 sband->bitrates[i].hw_value_short =
423 sband->bitrates[i].hw_value_short & 0xF;
427 sband->channels = sc->channels;
428 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
429 AR5K_MODE_11B, max_c);
431 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
432 count_c = sband->n_channels;
435 ath5k_setup_rate_idx(sc, sband);
437 /* 5GHz band, A mode */
438 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
439 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
440 sband->band = IEEE80211_BAND_5GHZ;
441 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
443 memcpy(sband->bitrates, &ath5k_rates[4],
444 sizeof(struct ieee80211_rate) * 8);
445 sband->n_bitrates = 8;
447 sband->channels = &sc->channels[count_c];
448 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
449 AR5K_MODE_11A, max_c);
451 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
453 ath5k_setup_rate_idx(sc, sband);
455 ath5k_debug_dump_bands(sc);
461 * Set/change channels. We always reset the chip.
462 * To accomplish this we must first cleanup any pending DMA,
463 * then restart stuff after a la ath5k_init.
465 * Called with sc->lock.
468 ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
470 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
471 "channel set, resetting (%u -> %u MHz)\n",
472 sc->curchan->center_freq, chan->center_freq);
475 * To switch channels clear any pending DMA operations;
476 * wait long enough for the RX fifo to drain, reset the
477 * hardware at the new frequency, and then re-enable
478 * the relevant bits of the h/w.
480 return ath5k_reset(sc, chan, true);
484 ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
488 if (mode == AR5K_MODE_11A) {
489 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
491 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
495 struct ath_vif_iter_data {
496 const u8 *hw_macaddr;
498 u8 active_mac[ETH_ALEN]; /* first active MAC */
499 bool need_set_hw_addr;
502 enum nl80211_iftype opmode;
505 static void ath_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
507 struct ath_vif_iter_data *iter_data = data;
509 struct ath5k_vif *avf = (void *)vif->drv_priv;
511 if (iter_data->hw_macaddr)
512 for (i = 0; i < ETH_ALEN; i++)
513 iter_data->mask[i] &=
514 ~(iter_data->hw_macaddr[i] ^ mac[i]);
516 if (!iter_data->found_active) {
517 iter_data->found_active = true;
518 memcpy(iter_data->active_mac, mac, ETH_ALEN);
521 if (iter_data->need_set_hw_addr && iter_data->hw_macaddr)
522 if (compare_ether_addr(iter_data->hw_macaddr, mac) == 0)
523 iter_data->need_set_hw_addr = false;
525 if (!iter_data->any_assoc) {
527 iter_data->any_assoc = true;
530 /* Calculate combined mode - when APs are active, operate in AP mode.
531 * Otherwise use the mode of the new interface. This can currently
532 * only deal with combinations of APs and STAs. Only one ad-hoc
533 * interfaces is allowed.
535 if (avf->opmode == NL80211_IFTYPE_AP)
536 iter_data->opmode = NL80211_IFTYPE_AP;
538 if (iter_data->opmode == NL80211_IFTYPE_UNSPECIFIED)
539 iter_data->opmode = avf->opmode;
542 static void ath5k_update_bssid_mask_and_opmode(struct ath5k_softc *sc,
543 struct ieee80211_vif *vif)
545 struct ath_common *common = ath5k_hw_common(sc->ah);
546 struct ath_vif_iter_data iter_data;
549 * Use the hardware MAC address as reference, the hardware uses it
550 * together with the BSSID mask when matching addresses.
552 iter_data.hw_macaddr = common->macaddr;
553 memset(&iter_data.mask, 0xff, ETH_ALEN);
554 iter_data.found_active = false;
555 iter_data.need_set_hw_addr = true;
556 iter_data.opmode = NL80211_IFTYPE_UNSPECIFIED;
559 ath_vif_iter(&iter_data, vif->addr, vif);
561 /* Get list of all active MAC addresses */
562 ieee80211_iterate_active_interfaces_atomic(sc->hw, ath_vif_iter,
564 memcpy(sc->bssidmask, iter_data.mask, ETH_ALEN);
566 sc->opmode = iter_data.opmode;
567 if (sc->opmode == NL80211_IFTYPE_UNSPECIFIED)
568 /* Nothing active, default to station mode */
569 sc->opmode = NL80211_IFTYPE_STATION;
571 ath5k_hw_set_opmode(sc->ah, sc->opmode);
572 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "mode setup opmode %d (%s)\n",
573 sc->opmode, ath_opmode_to_string(sc->opmode));
575 if (iter_data.need_set_hw_addr && iter_data.found_active)
576 ath5k_hw_set_lladdr(sc->ah, iter_data.active_mac);
578 if (ath5k_hw_hasbssidmask(sc->ah))
579 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
583 ath5k_mode_setup(struct ath5k_softc *sc, struct ieee80211_vif *vif)
585 struct ath5k_hw *ah = sc->ah;
588 /* configure rx filter */
589 rfilt = sc->filter_flags;
590 ath5k_hw_set_rx_filter(ah, rfilt);
591 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
593 ath5k_update_bssid_mask_and_opmode(sc, vif);
597 ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
601 /* return base rate on errors */
602 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
603 "hw_rix out of bounds: %x\n", hw_rix))
606 rix = sc->rate_idx[sc->curband->band][hw_rix];
607 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
618 struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
620 struct ath_common *common = ath5k_hw_common(sc->ah);
624 * Allocate buffer with headroom_needed space for the
625 * fake physical layer header at the start.
627 skb = ath_rxbuf_alloc(common,
632 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
637 *skb_addr = dma_map_single(sc->dev,
638 skb->data, common->rx_bufsize,
641 if (unlikely(dma_mapping_error(sc->dev, *skb_addr))) {
642 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
650 ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
652 struct ath5k_hw *ah = sc->ah;
653 struct sk_buff *skb = bf->skb;
654 struct ath5k_desc *ds;
658 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr);
665 * Setup descriptors. For receive we always terminate
666 * the descriptor list with a self-linked entry so we'll
667 * not get overrun under high load (as can happen with a
668 * 5212 when ANI processing enables PHY error frames).
670 * To ensure the last descriptor is self-linked we create
671 * each descriptor as self-linked and add it to the end. As
672 * each additional descriptor is added the previous self-linked
673 * entry is "fixed" naturally. This should be safe even
674 * if DMA is happening. When processing RX interrupts we
675 * never remove/process the last, self-linked, entry on the
676 * descriptor list. This ensures the hardware always has
677 * someplace to write a new frame.
680 ds->ds_link = bf->daddr; /* link to self */
681 ds->ds_data = bf->skbaddr;
682 ret = ath5k_hw_setup_rx_desc(ah, ds, ah->common.rx_bufsize, 0);
684 ATH5K_ERR(sc, "%s: could not setup RX desc\n", __func__);
688 if (sc->rxlink != NULL)
689 *sc->rxlink = bf->daddr;
690 sc->rxlink = &ds->ds_link;
694 static enum ath5k_pkt_type get_hw_packet_type(struct sk_buff *skb)
696 struct ieee80211_hdr *hdr;
697 enum ath5k_pkt_type htype;
700 hdr = (struct ieee80211_hdr *)skb->data;
701 fc = hdr->frame_control;
703 if (ieee80211_is_beacon(fc))
704 htype = AR5K_PKT_TYPE_BEACON;
705 else if (ieee80211_is_probe_resp(fc))
706 htype = AR5K_PKT_TYPE_PROBE_RESP;
707 else if (ieee80211_is_atim(fc))
708 htype = AR5K_PKT_TYPE_ATIM;
709 else if (ieee80211_is_pspoll(fc))
710 htype = AR5K_PKT_TYPE_PSPOLL;
712 htype = AR5K_PKT_TYPE_NORMAL;
718 ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
719 struct ath5k_txq *txq, int padsize)
721 struct ath5k_hw *ah = sc->ah;
722 struct ath5k_desc *ds = bf->desc;
723 struct sk_buff *skb = bf->skb;
724 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
725 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
726 struct ieee80211_rate *rate;
727 unsigned int mrr_rate[3], mrr_tries[3];
734 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
737 bf->skbaddr = dma_map_single(sc->dev, skb->data, skb->len,
740 rate = ieee80211_get_tx_rate(sc->hw, info);
746 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
747 flags |= AR5K_TXDESC_NOACK;
749 rc_flags = info->control.rates[0].flags;
750 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
751 rate->hw_value_short : rate->hw_value;
755 /* FIXME: If we are in g mode and rate is a CCK rate
756 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
757 * from tx power (value is in dB units already) */
758 if (info->control.hw_key) {
759 keyidx = info->control.hw_key->hw_key_idx;
760 pktlen += info->control.hw_key->icv_len;
762 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
763 flags |= AR5K_TXDESC_RTSENA;
764 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
765 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw,
766 info->control.vif, pktlen, info));
768 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
769 flags |= AR5K_TXDESC_CTSENA;
770 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
771 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw,
772 info->control.vif, pktlen, info));
774 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
775 ieee80211_get_hdrlen_from_skb(skb), padsize,
776 get_hw_packet_type(skb),
777 (sc->power_level * 2),
779 info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags,
784 memset(mrr_rate, 0, sizeof(mrr_rate));
785 memset(mrr_tries, 0, sizeof(mrr_tries));
786 for (i = 0; i < 3; i++) {
787 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
791 mrr_rate[i] = rate->hw_value;
792 mrr_tries[i] = info->control.rates[i + 1].count;
795 ath5k_hw_setup_mrr_tx_desc(ah, ds,
796 mrr_rate[0], mrr_tries[0],
797 mrr_rate[1], mrr_tries[1],
798 mrr_rate[2], mrr_tries[2]);
801 ds->ds_data = bf->skbaddr;
803 spin_lock_bh(&txq->lock);
804 list_add_tail(&bf->list, &txq->q);
806 if (txq->link == NULL) /* is this first packet? */
807 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
808 else /* no, so only link it */
809 *txq->link = bf->daddr;
811 txq->link = &ds->ds_link;
812 ath5k_hw_start_tx_dma(ah, txq->qnum);
814 spin_unlock_bh(&txq->lock);
818 dma_unmap_single(sc->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE);
822 /*******************\
823 * Descriptors setup *
824 \*******************/
827 ath5k_desc_alloc(struct ath5k_softc *sc)
829 struct ath5k_desc *ds;
830 struct ath5k_buf *bf;
835 /* allocate descriptors */
836 sc->desc_len = sizeof(struct ath5k_desc) *
837 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
839 sc->desc = dma_alloc_coherent(sc->dev, sc->desc_len,
840 &sc->desc_daddr, GFP_KERNEL);
841 if (sc->desc == NULL) {
842 ATH5K_ERR(sc, "can't allocate descriptors\n");
848 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
849 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
851 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
852 sizeof(struct ath5k_buf), GFP_KERNEL);
854 ATH5K_ERR(sc, "can't allocate bufptr\n");
860 INIT_LIST_HEAD(&sc->rxbuf);
861 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
864 list_add_tail(&bf->list, &sc->rxbuf);
867 INIT_LIST_HEAD(&sc->txbuf);
868 sc->txbuf_len = ATH_TXBUF;
869 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
873 list_add_tail(&bf->list, &sc->txbuf);
877 INIT_LIST_HEAD(&sc->bcbuf);
878 for (i = 0; i < ATH_BCBUF; i++, bf++, ds++, da += sizeof(*ds)) {
881 list_add_tail(&bf->list, &sc->bcbuf);
886 dma_free_coherent(sc->dev, sc->desc_len, sc->desc, sc->desc_daddr);
893 ath5k_desc_free(struct ath5k_softc *sc)
895 struct ath5k_buf *bf;
897 list_for_each_entry(bf, &sc->txbuf, list)
898 ath5k_txbuf_free_skb(sc, bf);
899 list_for_each_entry(bf, &sc->rxbuf, list)
900 ath5k_rxbuf_free_skb(sc, bf);
901 list_for_each_entry(bf, &sc->bcbuf, list)
902 ath5k_txbuf_free_skb(sc, bf);
904 /* Free memory associated with all descriptors */
905 dma_free_coherent(sc->dev, sc->desc_len, sc->desc, sc->desc_daddr);
918 static struct ath5k_txq *
919 ath5k_txq_setup(struct ath5k_softc *sc,
920 int qtype, int subtype)
922 struct ath5k_hw *ah = sc->ah;
923 struct ath5k_txq *txq;
924 struct ath5k_txq_info qi = {
925 .tqi_subtype = subtype,
926 /* XXX: default values not correct for B and XR channels,
928 .tqi_aifs = AR5K_TUNE_AIFS,
929 .tqi_cw_min = AR5K_TUNE_CWMIN,
930 .tqi_cw_max = AR5K_TUNE_CWMAX
935 * Enable interrupts only for EOL and DESC conditions.
936 * We mark tx descriptors to receive a DESC interrupt
937 * when a tx queue gets deep; otherwise we wait for the
938 * EOL to reap descriptors. Note that this is done to
939 * reduce interrupt load and this only defers reaping
940 * descriptors, never transmitting frames. Aside from
941 * reducing interrupts this also permits more concurrency.
942 * The only potential downside is if the tx queue backs
943 * up in which case the top half of the kernel may backup
944 * due to a lack of tx descriptors.
946 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
947 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
948 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
951 * NB: don't print a message, this happens
952 * normally on parts with too few tx queues
954 return ERR_PTR(qnum);
956 if (qnum >= ARRAY_SIZE(sc->txqs)) {
957 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
958 qnum, ARRAY_SIZE(sc->txqs));
959 ath5k_hw_release_tx_queue(ah, qnum);
960 return ERR_PTR(-EINVAL);
962 txq = &sc->txqs[qnum];
966 INIT_LIST_HEAD(&txq->q);
967 spin_lock_init(&txq->lock);
970 txq->txq_poll_mark = false;
973 return &sc->txqs[qnum];
977 ath5k_beaconq_setup(struct ath5k_hw *ah)
979 struct ath5k_txq_info qi = {
980 /* XXX: default values not correct for B and XR channels,
982 .tqi_aifs = AR5K_TUNE_AIFS,
983 .tqi_cw_min = AR5K_TUNE_CWMIN,
984 .tqi_cw_max = AR5K_TUNE_CWMAX,
985 /* NB: for dynamic turbo, don't enable any other interrupts */
986 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
989 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
993 ath5k_beaconq_config(struct ath5k_softc *sc)
995 struct ath5k_hw *ah = sc->ah;
996 struct ath5k_txq_info qi;
999 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1003 if (sc->opmode == NL80211_IFTYPE_AP ||
1004 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
1006 * Always burst out beacon and CAB traffic
1007 * (aifs = cwmin = cwmax = 0)
1012 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
1014 * Adhoc mode; backoff between 0 and (2 * cw_min).
1018 qi.tqi_cw_max = 2 * AR5K_TUNE_CWMIN;
1021 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1022 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1023 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1025 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
1027 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1028 "hardware queue!\n", __func__);
1031 ret = ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */
1035 /* reconfigure cabq with ready time to 80% of beacon_interval */
1036 ret = ath5k_hw_get_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1040 qi.tqi_ready_time = (sc->bintval * 80) / 100;
1041 ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1045 ret = ath5k_hw_reset_tx_queue(ah, AR5K_TX_QUEUE_ID_CAB);
1051 * ath5k_drain_tx_buffs - Empty tx buffers
1053 * @sc The &struct ath5k_softc
1055 * Empty tx buffers from all queues in preparation
1056 * of a reset or during shutdown.
1058 * NB: this assumes output has been stopped and
1059 * we do not need to block ath5k_tx_tasklet
1062 ath5k_drain_tx_buffs(struct ath5k_softc *sc)
1064 struct ath5k_txq *txq;
1065 struct ath5k_buf *bf, *bf0;
1068 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) {
1069 if (sc->txqs[i].setup) {
1071 spin_lock_bh(&txq->lock);
1072 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1073 ath5k_debug_printtxbuf(sc, bf);
1075 ath5k_txbuf_free_skb(sc, bf);
1077 spin_lock_bh(&sc->txbuflock);
1078 list_move_tail(&bf->list, &sc->txbuf);
1081 spin_unlock_bh(&sc->txbuflock);
1084 txq->txq_poll_mark = false;
1085 spin_unlock_bh(&txq->lock);
1091 ath5k_txq_release(struct ath5k_softc *sc)
1093 struct ath5k_txq *txq = sc->txqs;
1096 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1098 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1109 * Enable the receive h/w following a reset.
1112 ath5k_rx_start(struct ath5k_softc *sc)
1114 struct ath5k_hw *ah = sc->ah;
1115 struct ath_common *common = ath5k_hw_common(ah);
1116 struct ath5k_buf *bf;
1119 common->rx_bufsize = roundup(IEEE80211_MAX_FRAME_LEN, common->cachelsz);
1121 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n",
1122 common->cachelsz, common->rx_bufsize);
1124 spin_lock_bh(&sc->rxbuflock);
1126 list_for_each_entry(bf, &sc->rxbuf, list) {
1127 ret = ath5k_rxbuf_setup(sc, bf);
1129 spin_unlock_bh(&sc->rxbuflock);
1133 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1134 ath5k_hw_set_rxdp(ah, bf->daddr);
1135 spin_unlock_bh(&sc->rxbuflock);
1137 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
1138 ath5k_mode_setup(sc, NULL); /* set filters, etc. */
1139 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1147 * Disable the receive logic on PCU (DRU)
1148 * In preparation for a shutdown.
1150 * Note: Doesn't stop rx DMA, ath5k_hw_dma_stop
1154 ath5k_rx_stop(struct ath5k_softc *sc)
1156 struct ath5k_hw *ah = sc->ah;
1158 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1159 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
1161 ath5k_debug_printrxbuffs(sc, ah);
1165 ath5k_rx_decrypted(struct ath5k_softc *sc, struct sk_buff *skb,
1166 struct ath5k_rx_status *rs)
1168 struct ath5k_hw *ah = sc->ah;
1169 struct ath_common *common = ath5k_hw_common(ah);
1170 struct ieee80211_hdr *hdr = (void *)skb->data;
1171 unsigned int keyix, hlen;
1173 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1174 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1175 return RX_FLAG_DECRYPTED;
1177 /* Apparently when a default key is used to decrypt the packet
1178 the hw does not set the index used to decrypt. In such cases
1179 get the index from the packet. */
1180 hlen = ieee80211_hdrlen(hdr->frame_control);
1181 if (ieee80211_has_protected(hdr->frame_control) &&
1182 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1183 skb->len >= hlen + 4) {
1184 keyix = skb->data[hlen + 3] >> 6;
1186 if (test_bit(keyix, common->keymap))
1187 return RX_FLAG_DECRYPTED;
1195 ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1196 struct ieee80211_rx_status *rxs)
1198 struct ath_common *common = ath5k_hw_common(sc->ah);
1201 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1203 if (ieee80211_is_beacon(mgmt->frame_control) &&
1204 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
1205 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) == 0) {
1207 * Received an IBSS beacon with the same BSSID. Hardware *must*
1208 * have updated the local TSF. We have to work around various
1209 * hardware bugs, though...
1211 tsf = ath5k_hw_get_tsf64(sc->ah);
1212 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1213 hw_tu = TSF_TO_TU(tsf);
1215 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1216 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1217 (unsigned long long)bc_tstamp,
1218 (unsigned long long)rxs->mactime,
1219 (unsigned long long)(rxs->mactime - bc_tstamp),
1220 (unsigned long long)tsf);
1223 * Sometimes the HW will give us a wrong tstamp in the rx
1224 * status, causing the timestamp extension to go wrong.
1225 * (This seems to happen especially with beacon frames bigger
1226 * than 78 byte (incl. FCS))
1227 * But we know that the receive timestamp must be later than the
1228 * timestamp of the beacon since HW must have synced to that.
1230 * NOTE: here we assume mactime to be after the frame was
1231 * received, not like mac80211 which defines it at the start.
1233 if (bc_tstamp > rxs->mactime) {
1234 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1235 "fixing mactime from %llx to %llx\n",
1236 (unsigned long long)rxs->mactime,
1237 (unsigned long long)tsf);
1242 * Local TSF might have moved higher than our beacon timers,
1243 * in that case we have to update them to continue sending
1244 * beacons. This also takes care of synchronizing beacon sending
1245 * times with other stations.
1247 if (hw_tu >= sc->nexttbtt)
1248 ath5k_beacon_update_timers(sc, bc_tstamp);
1250 /* Check if the beacon timers are still correct, because a TSF
1251 * update might have created a window between them - for a
1252 * longer description see the comment of this function: */
1253 if (!ath5k_hw_check_beacon_timers(sc->ah, sc->bintval)) {
1254 ath5k_beacon_update_timers(sc, bc_tstamp);
1255 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1256 "fixed beacon timers after beacon receive\n");
1262 ath5k_update_beacon_rssi(struct ath5k_softc *sc, struct sk_buff *skb, int rssi)
1264 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1265 struct ath5k_hw *ah = sc->ah;
1266 struct ath_common *common = ath5k_hw_common(ah);
1268 /* only beacons from our BSSID */
1269 if (!ieee80211_is_beacon(mgmt->frame_control) ||
1270 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) != 0)
1273 ewma_add(&ah->ah_beacon_rssi_avg, rssi);
1275 /* in IBSS mode we should keep RSSI statistics per neighbour */
1276 /* le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS */
1280 * Compute padding position. skb must contain an IEEE 802.11 frame
1282 static int ath5k_common_padpos(struct sk_buff *skb)
1284 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
1285 __le16 frame_control = hdr->frame_control;
1288 if (ieee80211_has_a4(frame_control)) {
1291 if (ieee80211_is_data_qos(frame_control)) {
1292 padpos += IEEE80211_QOS_CTL_LEN;
1299 * This function expects an 802.11 frame and returns the number of
1300 * bytes added, or -1 if we don't have enough header room.
1302 static int ath5k_add_padding(struct sk_buff *skb)
1304 int padpos = ath5k_common_padpos(skb);
1305 int padsize = padpos & 3;
1307 if (padsize && skb->len>padpos) {
1309 if (skb_headroom(skb) < padsize)
1312 skb_push(skb, padsize);
1313 memmove(skb->data, skb->data+padsize, padpos);
1321 * The MAC header is padded to have 32-bit boundary if the
1322 * packet payload is non-zero. The general calculation for
1323 * padsize would take into account odd header lengths:
1324 * padsize = 4 - (hdrlen & 3); however, since only
1325 * even-length headers are used, padding can only be 0 or 2
1326 * bytes and we can optimize this a bit. We must not try to
1327 * remove padding from short control frames that do not have a
1330 * This function expects an 802.11 frame and returns the number of
1333 static int ath5k_remove_padding(struct sk_buff *skb)
1335 int padpos = ath5k_common_padpos(skb);
1336 int padsize = padpos & 3;
1338 if (padsize && skb->len>=padpos+padsize) {
1339 memmove(skb->data + padsize, skb->data, padpos);
1340 skb_pull(skb, padsize);
1348 ath5k_receive_frame(struct ath5k_softc *sc, struct sk_buff *skb,
1349 struct ath5k_rx_status *rs)
1351 struct ieee80211_rx_status *rxs;
1353 ath5k_remove_padding(skb);
1355 rxs = IEEE80211_SKB_RXCB(skb);
1358 if (unlikely(rs->rs_status & AR5K_RXERR_MIC))
1359 rxs->flag |= RX_FLAG_MMIC_ERROR;
1362 * always extend the mac timestamp, since this information is
1363 * also needed for proper IBSS merging.
1365 * XXX: it might be too late to do it here, since rs_tstamp is
1366 * 15bit only. that means TSF extension has to be done within
1367 * 32768usec (about 32ms). it might be necessary to move this to
1368 * the interrupt handler, like it is done in madwifi.
1370 * Unfortunately we don't know when the hardware takes the rx
1371 * timestamp (beginning of phy frame, data frame, end of rx?).
1372 * The only thing we know is that it is hardware specific...
1373 * On AR5213 it seems the rx timestamp is at the end of the
1374 * frame, but i'm not sure.
1376 * NOTE: mac80211 defines mactime at the beginning of the first
1377 * data symbol. Since we don't have any time references it's
1378 * impossible to comply to that. This affects IBSS merge only
1379 * right now, so it's not too bad...
1381 rxs->mactime = ath5k_extend_tsf(sc->ah, rs->rs_tstamp);
1382 rxs->flag |= RX_FLAG_TSFT;
1384 rxs->freq = sc->curchan->center_freq;
1385 rxs->band = sc->curband->band;
1387 rxs->signal = sc->ah->ah_noise_floor + rs->rs_rssi;
1389 rxs->antenna = rs->rs_antenna;
1391 if (rs->rs_antenna > 0 && rs->rs_antenna < 5)
1392 sc->stats.antenna_rx[rs->rs_antenna]++;
1394 sc->stats.antenna_rx[0]++; /* invalid */
1396 rxs->rate_idx = ath5k_hw_to_driver_rix(sc, rs->rs_rate);
1397 rxs->flag |= ath5k_rx_decrypted(sc, skb, rs);
1399 if (rxs->rate_idx >= 0 && rs->rs_rate ==
1400 sc->curband->bitrates[rxs->rate_idx].hw_value_short)
1401 rxs->flag |= RX_FLAG_SHORTPRE;
1403 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
1405 ath5k_update_beacon_rssi(sc, skb, rs->rs_rssi);
1407 /* check beacons in IBSS mode */
1408 if (sc->opmode == NL80211_IFTYPE_ADHOC)
1409 ath5k_check_ibss_tsf(sc, skb, rxs);
1411 ieee80211_rx(sc->hw, skb);
1414 /** ath5k_frame_receive_ok() - Do we want to receive this frame or not?
1416 * Check if we want to further process this frame or not. Also update
1417 * statistics. Return true if we want this frame, false if not.
1420 ath5k_receive_frame_ok(struct ath5k_softc *sc, struct ath5k_rx_status *rs)
1422 sc->stats.rx_all_count++;
1423 sc->stats.rx_bytes_count += rs->rs_datalen;
1425 if (unlikely(rs->rs_status)) {
1426 if (rs->rs_status & AR5K_RXERR_CRC)
1427 sc->stats.rxerr_crc++;
1428 if (rs->rs_status & AR5K_RXERR_FIFO)
1429 sc->stats.rxerr_fifo++;
1430 if (rs->rs_status & AR5K_RXERR_PHY) {
1431 sc->stats.rxerr_phy++;
1432 if (rs->rs_phyerr > 0 && rs->rs_phyerr < 32)
1433 sc->stats.rxerr_phy_code[rs->rs_phyerr]++;
1436 if (rs->rs_status & AR5K_RXERR_DECRYPT) {
1438 * Decrypt error. If the error occurred
1439 * because there was no hardware key, then
1440 * let the frame through so the upper layers
1441 * can process it. This is necessary for 5210
1442 * parts which have no way to setup a ``clear''
1445 * XXX do key cache faulting
1447 sc->stats.rxerr_decrypt++;
1448 if (rs->rs_keyix == AR5K_RXKEYIX_INVALID &&
1449 !(rs->rs_status & AR5K_RXERR_CRC))
1452 if (rs->rs_status & AR5K_RXERR_MIC) {
1453 sc->stats.rxerr_mic++;
1457 /* reject any frames with non-crypto errors */
1458 if (rs->rs_status & ~(AR5K_RXERR_DECRYPT))
1462 if (unlikely(rs->rs_more)) {
1463 sc->stats.rxerr_jumbo++;
1470 ath5k_tasklet_rx(unsigned long data)
1472 struct ath5k_rx_status rs = {};
1473 struct sk_buff *skb, *next_skb;
1474 dma_addr_t next_skb_addr;
1475 struct ath5k_softc *sc = (void *)data;
1476 struct ath5k_hw *ah = sc->ah;
1477 struct ath_common *common = ath5k_hw_common(ah);
1478 struct ath5k_buf *bf;
1479 struct ath5k_desc *ds;
1482 spin_lock(&sc->rxbuflock);
1483 if (list_empty(&sc->rxbuf)) {
1484 ATH5K_WARN(sc, "empty rx buf pool\n");
1488 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1489 BUG_ON(bf->skb == NULL);
1493 /* bail if HW is still using self-linked descriptor */
1494 if (ath5k_hw_get_rxdp(sc->ah) == bf->daddr)
1497 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
1498 if (unlikely(ret == -EINPROGRESS))
1500 else if (unlikely(ret)) {
1501 ATH5K_ERR(sc, "error in processing rx descriptor\n");
1502 sc->stats.rxerr_proc++;
1506 if (ath5k_receive_frame_ok(sc, &rs)) {
1507 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr);
1510 * If we can't replace bf->skb with a new skb under
1511 * memory pressure, just skip this packet
1516 dma_unmap_single(sc->dev, bf->skbaddr,
1520 skb_put(skb, rs.rs_datalen);
1522 ath5k_receive_frame(sc, skb, &rs);
1525 bf->skbaddr = next_skb_addr;
1528 list_move_tail(&bf->list, &sc->rxbuf);
1529 } while (ath5k_rxbuf_setup(sc, bf) == 0);
1531 spin_unlock(&sc->rxbuflock);
1539 static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
1540 struct ath5k_txq *txq)
1542 struct ath5k_softc *sc = hw->priv;
1543 struct ath5k_buf *bf;
1544 unsigned long flags;
1547 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
1550 * The hardware expects the header padded to 4 byte boundaries.
1551 * If this is not the case, we add the padding after the header.
1553 padsize = ath5k_add_padding(skb);
1555 ATH5K_ERR(sc, "tx hdrlen not %%4: not enough"
1556 " headroom to pad");
1560 if (txq->txq_len >= ATH5K_TXQ_LEN_MAX)
1561 ieee80211_stop_queue(hw, txq->qnum);
1563 spin_lock_irqsave(&sc->txbuflock, flags);
1564 if (list_empty(&sc->txbuf)) {
1565 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
1566 spin_unlock_irqrestore(&sc->txbuflock, flags);
1567 ieee80211_stop_queues(hw);
1570 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
1571 list_del(&bf->list);
1573 if (list_empty(&sc->txbuf))
1574 ieee80211_stop_queues(hw);
1575 spin_unlock_irqrestore(&sc->txbuflock, flags);
1579 if (ath5k_txbuf_setup(sc, bf, txq, padsize)) {
1581 spin_lock_irqsave(&sc->txbuflock, flags);
1582 list_add_tail(&bf->list, &sc->txbuf);
1584 spin_unlock_irqrestore(&sc->txbuflock, flags);
1587 return NETDEV_TX_OK;
1590 dev_kfree_skb_any(skb);
1591 return NETDEV_TX_OK;
1595 ath5k_tx_frame_completed(struct ath5k_softc *sc, struct sk_buff *skb,
1596 struct ath5k_tx_status *ts)
1598 struct ieee80211_tx_info *info;
1601 sc->stats.tx_all_count++;
1602 sc->stats.tx_bytes_count += skb->len;
1603 info = IEEE80211_SKB_CB(skb);
1605 ieee80211_tx_info_clear_status(info);
1606 for (i = 0; i < 4; i++) {
1607 struct ieee80211_tx_rate *r =
1608 &info->status.rates[i];
1610 if (ts->ts_rate[i]) {
1611 r->idx = ath5k_hw_to_driver_rix(sc, ts->ts_rate[i]);
1612 r->count = ts->ts_retry[i];
1619 /* count the successful attempt as well */
1620 info->status.rates[ts->ts_final_idx].count++;
1622 if (unlikely(ts->ts_status)) {
1623 sc->stats.ack_fail++;
1624 if (ts->ts_status & AR5K_TXERR_FILT) {
1625 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1626 sc->stats.txerr_filt++;
1628 if (ts->ts_status & AR5K_TXERR_XRETRY)
1629 sc->stats.txerr_retry++;
1630 if (ts->ts_status & AR5K_TXERR_FIFO)
1631 sc->stats.txerr_fifo++;
1633 info->flags |= IEEE80211_TX_STAT_ACK;
1634 info->status.ack_signal = ts->ts_rssi;
1638 * Remove MAC header padding before giving the frame
1641 ath5k_remove_padding(skb);
1643 if (ts->ts_antenna > 0 && ts->ts_antenna < 5)
1644 sc->stats.antenna_tx[ts->ts_antenna]++;
1646 sc->stats.antenna_tx[0]++; /* invalid */
1648 ieee80211_tx_status(sc->hw, skb);
1652 ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1654 struct ath5k_tx_status ts = {};
1655 struct ath5k_buf *bf, *bf0;
1656 struct ath5k_desc *ds;
1657 struct sk_buff *skb;
1660 spin_lock(&txq->lock);
1661 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1663 txq->txq_poll_mark = false;
1665 /* skb might already have been processed last time. */
1666 if (bf->skb != NULL) {
1669 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
1670 if (unlikely(ret == -EINPROGRESS))
1672 else if (unlikely(ret)) {
1674 "error %d while processing "
1675 "queue %u\n", ret, txq->qnum);
1682 dma_unmap_single(sc->dev, bf->skbaddr, skb->len,
1684 ath5k_tx_frame_completed(sc, skb, &ts);
1688 * It's possible that the hardware can say the buffer is
1689 * completed when it hasn't yet loaded the ds_link from
1690 * host memory and moved on.
1691 * Always keep the last descriptor to avoid HW races...
1693 if (ath5k_hw_get_txdp(sc->ah, txq->qnum) != bf->daddr) {
1694 spin_lock(&sc->txbuflock);
1695 list_move_tail(&bf->list, &sc->txbuf);
1698 spin_unlock(&sc->txbuflock);
1701 spin_unlock(&txq->lock);
1702 if (txq->txq_len < ATH5K_TXQ_LEN_LOW && txq->qnum < 4)
1703 ieee80211_wake_queue(sc->hw, txq->qnum);
1707 ath5k_tasklet_tx(unsigned long data)
1710 struct ath5k_softc *sc = (void *)data;
1712 for (i=0; i < AR5K_NUM_TX_QUEUES; i++)
1713 if (sc->txqs[i].setup && (sc->ah->ah_txq_isr & BIT(i)))
1714 ath5k_tx_processq(sc, &sc->txqs[i]);
1723 * Setup the beacon frame for transmit.
1726 ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1728 struct sk_buff *skb = bf->skb;
1729 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1730 struct ath5k_hw *ah = sc->ah;
1731 struct ath5k_desc *ds;
1735 const int padsize = 0;
1737 bf->skbaddr = dma_map_single(sc->dev, skb->data, skb->len,
1739 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1740 "skbaddr %llx\n", skb, skb->data, skb->len,
1741 (unsigned long long)bf->skbaddr);
1743 if (dma_mapping_error(sc->dev, bf->skbaddr)) {
1744 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
1749 antenna = ah->ah_tx_ant;
1751 flags = AR5K_TXDESC_NOACK;
1752 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
1753 ds->ds_link = bf->daddr; /* self-linked */
1754 flags |= AR5K_TXDESC_VEOL;
1759 * If we use multiple antennas on AP and use
1760 * the Sectored AP scenario, switch antenna every
1761 * 4 beacons to make sure everybody hears our AP.
1762 * When a client tries to associate, hw will keep
1763 * track of the tx antenna to be used for this client
1764 * automaticaly, based on ACKed packets.
1766 * Note: AP still listens and transmits RTS on the
1767 * default antenna which is supposed to be an omni.
1769 * Note2: On sectored scenarios it's possible to have
1770 * multiple antennas (1 omni -- the default -- and 14
1771 * sectors), so if we choose to actually support this
1772 * mode, we need to allow the user to set how many antennas
1773 * we have and tweak the code below to send beacons
1776 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
1777 antenna = sc->bsent & 4 ? 2 : 1;
1780 /* FIXME: If we are in g mode and rate is a CCK rate
1781 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1782 * from tx power (value is in dB units already) */
1783 ds->ds_data = bf->skbaddr;
1784 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
1785 ieee80211_get_hdrlen_from_skb(skb), padsize,
1786 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
1787 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
1788 1, AR5K_TXKEYIX_INVALID,
1789 antenna, flags, 0, 0);
1795 dma_unmap_single(sc->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE);
1800 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
1801 * this is called only once at config_bss time, for AP we do it every
1802 * SWBA interrupt so that the TIM will reflect buffered frames.
1804 * Called with the beacon lock.
1807 ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1810 struct ath5k_softc *sc = hw->priv;
1811 struct ath5k_vif *avf = (void *)vif->drv_priv;
1812 struct sk_buff *skb;
1814 if (WARN_ON(!vif)) {
1819 skb = ieee80211_beacon_get(hw, vif);
1826 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
1828 ath5k_txbuf_free_skb(sc, avf->bbuf);
1829 avf->bbuf->skb = skb;
1830 ret = ath5k_beacon_setup(sc, avf->bbuf);
1832 avf->bbuf->skb = NULL;
1838 * Transmit a beacon frame at SWBA. Dynamic updates to the
1839 * frame contents are done as needed and the slot time is
1840 * also adjusted based on current state.
1842 * This is called from software irq context (beacontq tasklets)
1843 * or user context from ath5k_beacon_config.
1846 ath5k_beacon_send(struct ath5k_softc *sc)
1848 struct ath5k_hw *ah = sc->ah;
1849 struct ieee80211_vif *vif;
1850 struct ath5k_vif *avf;
1851 struct ath5k_buf *bf;
1852 struct sk_buff *skb;
1854 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
1857 * Check if the previous beacon has gone out. If
1858 * not, don't don't try to post another: skip this
1859 * period and wait for the next. Missed beacons
1860 * indicate a problem and should not occur. If we
1861 * miss too many consecutive beacons reset the device.
1863 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
1865 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1866 "missed %u consecutive beacons\n", sc->bmisscount);
1867 if (sc->bmisscount > 10) { /* NB: 10 is a guess */
1868 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1869 "stuck beacon time (%u missed)\n",
1871 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
1872 "stuck beacon, resetting\n");
1873 ieee80211_queue_work(sc->hw, &sc->reset_work);
1877 if (unlikely(sc->bmisscount != 0)) {
1878 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1879 "resume beacon xmit after %u misses\n",
1884 if (sc->opmode == NL80211_IFTYPE_AP && sc->num_ap_vifs > 1) {
1885 u64 tsf = ath5k_hw_get_tsf64(ah);
1886 u32 tsftu = TSF_TO_TU(tsf);
1887 int slot = ((tsftu % sc->bintval) * ATH_BCBUF) / sc->bintval;
1888 vif = sc->bslot[(slot + 1) % ATH_BCBUF];
1889 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1890 "tsf %llx tsftu %x intval %u slot %u vif %p\n",
1891 (unsigned long long)tsf, tsftu, sc->bintval, slot, vif);
1892 } else /* only one interface */
1898 avf = (void *)vif->drv_priv;
1900 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
1901 sc->opmode == NL80211_IFTYPE_MONITOR)) {
1902 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
1907 * Stop any current dma and put the new frame on the queue.
1908 * This should never fail since we check above that no frames
1909 * are still pending on the queue.
1911 if (unlikely(ath5k_hw_stop_beacon_queue(ah, sc->bhalq))) {
1912 ATH5K_WARN(sc, "beacon queue %u didn't start/stop ?\n", sc->bhalq);
1913 /* NB: hw still stops DMA, so proceed */
1916 /* refresh the beacon for AP mode */
1917 if (sc->opmode == NL80211_IFTYPE_AP)
1918 ath5k_beacon_update(sc->hw, vif);
1920 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
1921 ath5k_hw_start_tx_dma(ah, sc->bhalq);
1922 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
1923 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
1925 skb = ieee80211_get_buffered_bc(sc->hw, vif);
1927 ath5k_tx_queue(sc->hw, skb, sc->cabq);
1928 skb = ieee80211_get_buffered_bc(sc->hw, vif);
1935 * ath5k_beacon_update_timers - update beacon timers
1937 * @sc: struct ath5k_softc pointer we are operating on
1938 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
1939 * beacon timer update based on the current HW TSF.
1941 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
1942 * of a received beacon or the current local hardware TSF and write it to the
1943 * beacon timer registers.
1945 * This is called in a variety of situations, e.g. when a beacon is received,
1946 * when a TSF update has been detected, but also when an new IBSS is created or
1947 * when we otherwise know we have to update the timers, but we keep it in this
1948 * function to have it all together in one place.
1951 ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
1953 struct ath5k_hw *ah = sc->ah;
1954 u32 nexttbtt, intval, hw_tu, bc_tu;
1957 intval = sc->bintval & AR5K_BEACON_PERIOD;
1958 if (sc->opmode == NL80211_IFTYPE_AP && sc->num_ap_vifs > 1) {
1959 intval /= ATH_BCBUF; /* staggered multi-bss beacons */
1961 ATH5K_WARN(sc, "intval %u is too low, min 15\n",
1964 if (WARN_ON(!intval))
1967 /* beacon TSF converted to TU */
1968 bc_tu = TSF_TO_TU(bc_tsf);
1970 /* current TSF converted to TU */
1971 hw_tsf = ath5k_hw_get_tsf64(ah);
1972 hw_tu = TSF_TO_TU(hw_tsf);
1974 #define FUDGE AR5K_TUNE_SW_BEACON_RESP + 3
1975 /* We use FUDGE to make sure the next TBTT is ahead of the current TU.
1976 * Since we later substract AR5K_TUNE_SW_BEACON_RESP (10) in the timer
1977 * configuration we need to make sure it is bigger than that. */
1981 * no beacons received, called internally.
1982 * just need to refresh timers based on HW TSF.
1984 nexttbtt = roundup(hw_tu + FUDGE, intval);
1985 } else if (bc_tsf == 0) {
1987 * no beacon received, probably called by ath5k_reset_tsf().
1988 * reset TSF to start with 0.
1991 intval |= AR5K_BEACON_RESET_TSF;
1992 } else if (bc_tsf > hw_tsf) {
1994 * beacon received, SW merge happend but HW TSF not yet updated.
1995 * not possible to reconfigure timers yet, but next time we
1996 * receive a beacon with the same BSSID, the hardware will
1997 * automatically update the TSF and then we need to reconfigure
2000 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2001 "need to wait for HW TSF sync\n");
2005 * most important case for beacon synchronization between STA.
2007 * beacon received and HW TSF has been already updated by HW.
2008 * update next TBTT based on the TSF of the beacon, but make
2009 * sure it is ahead of our local TSF timer.
2011 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2015 sc->nexttbtt = nexttbtt;
2017 intval |= AR5K_BEACON_ENA;
2018 ath5k_hw_init_beacon(ah, nexttbtt, intval);
2021 * debugging output last in order to preserve the time critical aspect
2025 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2026 "reconfigured timers based on HW TSF\n");
2027 else if (bc_tsf == 0)
2028 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2029 "reset HW TSF and timers\n");
2031 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2032 "updated timers based on beacon TSF\n");
2034 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2035 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2036 (unsigned long long) bc_tsf,
2037 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
2038 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2039 intval & AR5K_BEACON_PERIOD,
2040 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2041 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
2045 * ath5k_beacon_config - Configure the beacon queues and interrupts
2047 * @sc: struct ath5k_softc pointer we are operating on
2049 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2050 * interrupts to detect TSF updates only.
2053 ath5k_beacon_config(struct ath5k_softc *sc)
2055 struct ath5k_hw *ah = sc->ah;
2056 unsigned long flags;
2058 spin_lock_irqsave(&sc->block, flags);
2060 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
2062 if (sc->enable_beacon) {
2064 * In IBSS mode we use a self-linked tx descriptor and let the
2065 * hardware send the beacons automatically. We have to load it
2067 * We use the SWBA interrupt only to keep track of the beacon
2068 * timers in order to detect automatic TSF updates.
2070 ath5k_beaconq_config(sc);
2072 sc->imask |= AR5K_INT_SWBA;
2074 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2075 if (ath5k_hw_hasveol(ah))
2076 ath5k_beacon_send(sc);
2078 ath5k_beacon_update_timers(sc, -1);
2080 ath5k_hw_stop_beacon_queue(sc->ah, sc->bhalq);
2083 ath5k_hw_set_imr(ah, sc->imask);
2085 spin_unlock_irqrestore(&sc->block, flags);
2088 static void ath5k_tasklet_beacon(unsigned long data)
2090 struct ath5k_softc *sc = (struct ath5k_softc *) data;
2093 * Software beacon alert--time to send a beacon.
2095 * In IBSS mode we use this interrupt just to
2096 * keep track of the next TBTT (target beacon
2097 * transmission time) in order to detect wether
2098 * automatic TSF updates happened.
2100 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2101 /* XXX: only if VEOL suppported */
2102 u64 tsf = ath5k_hw_get_tsf64(sc->ah);
2103 sc->nexttbtt += sc->bintval;
2104 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2105 "SWBA nexttbtt: %x hw_tu: %x "
2109 (unsigned long long) tsf);
2111 spin_lock(&sc->block);
2112 ath5k_beacon_send(sc);
2113 spin_unlock(&sc->block);
2118 /********************\
2119 * Interrupt handling *
2120 \********************/
2123 ath5k_intr_calibration_poll(struct ath5k_hw *ah)
2125 if (time_is_before_eq_jiffies(ah->ah_cal_next_ani) &&
2126 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL)) {
2127 /* run ANI only when full calibration is not active */
2128 ah->ah_cal_next_ani = jiffies +
2129 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI);
2130 tasklet_schedule(&ah->ah_sc->ani_tasklet);
2132 } else if (time_is_before_eq_jiffies(ah->ah_cal_next_full)) {
2133 ah->ah_cal_next_full = jiffies +
2134 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL);
2135 tasklet_schedule(&ah->ah_sc->calib);
2137 /* we could use SWI to generate enough interrupts to meet our
2138 * calibration interval requirements, if necessary:
2139 * AR5K_REG_ENABLE_BITS(ah, AR5K_CR, AR5K_CR_SWI); */
2143 ath5k_intr(int irq, void *dev_id)
2145 struct ath5k_softc *sc = dev_id;
2146 struct ath5k_hw *ah = sc->ah;
2147 enum ath5k_int status;
2148 unsigned int counter = 1000;
2150 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2151 ((ath5k_get_bus_type(ah) != ATH_AHB) &&
2152 !ath5k_hw_is_intr_pending(ah))))
2156 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2157 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2159 if (unlikely(status & AR5K_INT_FATAL)) {
2161 * Fatal errors are unrecoverable.
2162 * Typically these are caused by DMA errors.
2164 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2165 "fatal int, resetting\n");
2166 ieee80211_queue_work(sc->hw, &sc->reset_work);
2167 } else if (unlikely(status & AR5K_INT_RXORN)) {
2169 * Receive buffers are full. Either the bus is busy or
2170 * the CPU is not fast enough to process all received
2172 * Older chipsets need a reset to come out of this
2173 * condition, but we treat it as RX for newer chips.
2174 * We don't know exactly which versions need a reset -
2175 * this guess is copied from the HAL.
2177 sc->stats.rxorn_intr++;
2178 if (ah->ah_mac_srev < AR5K_SREV_AR5212) {
2179 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2180 "rx overrun, resetting\n");
2181 ieee80211_queue_work(sc->hw, &sc->reset_work);
2184 tasklet_schedule(&sc->rxtq);
2186 if (status & AR5K_INT_SWBA) {
2187 tasklet_hi_schedule(&sc->beacontq);
2189 if (status & AR5K_INT_RXEOL) {
2191 * NB: the hardware should re-read the link when
2192 * RXE bit is written, but it doesn't work at
2193 * least on older hardware revs.
2195 sc->stats.rxeol_intr++;
2197 if (status & AR5K_INT_TXURN) {
2198 /* bump tx trigger level */
2199 ath5k_hw_update_tx_triglevel(ah, true);
2201 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
2202 tasklet_schedule(&sc->rxtq);
2203 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2204 | AR5K_INT_TXERR | AR5K_INT_TXEOL))
2205 tasklet_schedule(&sc->txtq);
2206 if (status & AR5K_INT_BMISS) {
2209 if (status & AR5K_INT_MIB) {
2210 sc->stats.mib_intr++;
2211 ath5k_hw_update_mib_counters(ah);
2212 ath5k_ani_mib_intr(ah);
2214 if (status & AR5K_INT_GPIO)
2215 tasklet_schedule(&sc->rf_kill.toggleq);
2219 if (ath5k_get_bus_type(ah) == ATH_AHB)
2222 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
2224 if (unlikely(!counter))
2225 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2227 ath5k_intr_calibration_poll(ah);
2233 * Periodically recalibrate the PHY to account
2234 * for temperature/environment changes.
2237 ath5k_tasklet_calibrate(unsigned long data)
2239 struct ath5k_softc *sc = (void *)data;
2240 struct ath5k_hw *ah = sc->ah;
2242 /* Only full calibration for now */
2243 ah->ah_cal_mask |= AR5K_CALIBRATION_FULL;
2245 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
2246 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2247 sc->curchan->hw_value);
2249 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2251 * Rfgain is out of bounds, reset the chip
2252 * to load new gain values.
2254 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
2255 ieee80211_queue_work(sc->hw, &sc->reset_work);
2257 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2258 ATH5K_ERR(sc, "calibration of channel %u failed\n",
2259 ieee80211_frequency_to_channel(
2260 sc->curchan->center_freq));
2262 /* Noise floor calibration interrupts rx/tx path while I/Q calibration
2264 * TODO: We should stop TX here, so that it doesn't interfere.
2265 * Note that stopping the queues is not enough to stop TX! */
2266 if (time_is_before_eq_jiffies(ah->ah_cal_next_nf)) {
2267 ah->ah_cal_next_nf = jiffies +
2268 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_NF);
2269 ath5k_hw_update_noise_floor(ah);
2272 ah->ah_cal_mask &= ~AR5K_CALIBRATION_FULL;
2277 ath5k_tasklet_ani(unsigned long data)
2279 struct ath5k_softc *sc = (void *)data;
2280 struct ath5k_hw *ah = sc->ah;
2282 ah->ah_cal_mask |= AR5K_CALIBRATION_ANI;
2283 ath5k_ani_calibration(ah);
2284 ah->ah_cal_mask &= ~AR5K_CALIBRATION_ANI;
2289 ath5k_tx_complete_poll_work(struct work_struct *work)
2291 struct ath5k_softc *sc = container_of(work, struct ath5k_softc,
2292 tx_complete_work.work);
2293 struct ath5k_txq *txq;
2295 bool needreset = false;
2297 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) {
2298 if (sc->txqs[i].setup) {
2300 spin_lock_bh(&txq->lock);
2301 if (txq->txq_len > 1) {
2302 if (txq->txq_poll_mark) {
2303 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT,
2304 "TX queue stuck %d\n",
2308 spin_unlock_bh(&txq->lock);
2311 txq->txq_poll_mark = true;
2314 spin_unlock_bh(&txq->lock);
2319 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2320 "TX queues stuck, resetting\n");
2321 ath5k_reset(sc, NULL, true);
2324 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
2325 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2329 /*************************\
2330 * Initialization routines *
2331 \*************************/
2334 ath5k_init_softc(struct ath5k_softc *sc, const struct ath_bus_ops *bus_ops)
2336 struct ieee80211_hw *hw = sc->hw;
2337 struct ath_common *common;
2341 /* Initialize driver private data */
2342 SET_IEEE80211_DEV(hw, sc->dev);
2343 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
2344 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2345 IEEE80211_HW_SIGNAL_DBM |
2346 IEEE80211_HW_REPORTS_TX_ACK_STATUS;
2348 hw->wiphy->interface_modes =
2349 BIT(NL80211_IFTYPE_AP) |
2350 BIT(NL80211_IFTYPE_STATION) |
2351 BIT(NL80211_IFTYPE_ADHOC) |
2352 BIT(NL80211_IFTYPE_MESH_POINT);
2354 hw->extra_tx_headroom = 2;
2355 hw->channel_change_time = 5000;
2358 * Mark the device as detached to avoid processing
2359 * interrupts until setup is complete.
2361 __set_bit(ATH_STAT_INVALID, sc->status);
2363 sc->opmode = NL80211_IFTYPE_STATION;
2365 mutex_init(&sc->lock);
2366 spin_lock_init(&sc->rxbuflock);
2367 spin_lock_init(&sc->txbuflock);
2368 spin_lock_init(&sc->block);
2371 /* Setup interrupt handler */
2372 ret = request_irq(sc->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
2374 ATH5K_ERR(sc, "request_irq failed\n");
2378 /* If we passed the test, malloc an ath5k_hw struct */
2379 sc->ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL);
2382 ATH5K_ERR(sc, "out of memory\n");
2387 sc->ah->ah_iobase = sc->iobase;
2388 common = ath5k_hw_common(sc->ah);
2389 common->ops = &ath5k_common_ops;
2390 common->bus_ops = bus_ops;
2391 common->ah = sc->ah;
2396 * Cache line size is used to size and align various
2397 * structures used to communicate with the hardware.
2399 ath5k_read_cachesize(common, &csz);
2400 common->cachelsz = csz << 2; /* convert to bytes */
2402 spin_lock_init(&common->cc_lock);
2404 /* Initialize device */
2405 ret = ath5k_hw_init(sc);
2409 /* set up multi-rate retry capabilities */
2410 if (sc->ah->ah_version == AR5K_AR5212) {
2412 hw->max_rate_tries = 11;
2415 hw->vif_data_size = sizeof(struct ath5k_vif);
2417 /* Finish private driver data initialization */
2418 ret = ath5k_init(hw);
2422 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
2423 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
2424 sc->ah->ah_mac_srev,
2425 sc->ah->ah_phy_revision);
2427 if (!sc->ah->ah_single_chip) {
2428 /* Single chip radio (!RF5111) */
2429 if (sc->ah->ah_radio_5ghz_revision &&
2430 !sc->ah->ah_radio_2ghz_revision) {
2431 /* No 5GHz support -> report 2GHz radio */
2432 if (!test_bit(AR5K_MODE_11A,
2433 sc->ah->ah_capabilities.cap_mode)) {
2434 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
2435 ath5k_chip_name(AR5K_VERSION_RAD,
2436 sc->ah->ah_radio_5ghz_revision),
2437 sc->ah->ah_radio_5ghz_revision);
2438 /* No 2GHz support (5110 and some
2439 * 5Ghz only cards) -> report 5Ghz radio */
2440 } else if (!test_bit(AR5K_MODE_11B,
2441 sc->ah->ah_capabilities.cap_mode)) {
2442 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
2443 ath5k_chip_name(AR5K_VERSION_RAD,
2444 sc->ah->ah_radio_5ghz_revision),
2445 sc->ah->ah_radio_5ghz_revision);
2446 /* Multiband radio */
2448 ATH5K_INFO(sc, "RF%s multiband radio found"
2450 ath5k_chip_name(AR5K_VERSION_RAD,
2451 sc->ah->ah_radio_5ghz_revision),
2452 sc->ah->ah_radio_5ghz_revision);
2455 /* Multi chip radio (RF5111 - RF2111) ->
2456 * report both 2GHz/5GHz radios */
2457 else if (sc->ah->ah_radio_5ghz_revision &&
2458 sc->ah->ah_radio_2ghz_revision){
2459 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
2460 ath5k_chip_name(AR5K_VERSION_RAD,
2461 sc->ah->ah_radio_5ghz_revision),
2462 sc->ah->ah_radio_5ghz_revision);
2463 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
2464 ath5k_chip_name(AR5K_VERSION_RAD,
2465 sc->ah->ah_radio_2ghz_revision),
2466 sc->ah->ah_radio_2ghz_revision);
2470 ath5k_debug_init_device(sc);
2472 /* ready to process interrupts */
2473 __clear_bit(ATH_STAT_INVALID, sc->status);
2477 ath5k_hw_deinit(sc->ah);
2481 free_irq(sc->irq, sc);
2487 ath5k_stop_locked(struct ath5k_softc *sc)
2489 struct ath5k_hw *ah = sc->ah;
2491 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2492 test_bit(ATH_STAT_INVALID, sc->status));
2495 * Shutdown the hardware and driver:
2496 * stop output from above
2497 * disable interrupts
2499 * turn off the radio
2500 * clear transmit machinery
2501 * clear receive machinery
2502 * drain and release tx queues
2503 * reclaim beacon resources
2504 * power down hardware
2506 * Note that some of this work is not possible if the
2507 * hardware is gone (invalid).
2509 ieee80211_stop_queues(sc->hw);
2511 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2513 ath5k_hw_set_imr(ah, 0);
2514 synchronize_irq(sc->irq);
2516 ath5k_hw_dma_stop(ah);
2517 ath5k_drain_tx_buffs(sc);
2518 ath5k_hw_phy_disable(ah);
2525 ath5k_init_hw(struct ath5k_softc *sc)
2527 struct ath5k_hw *ah = sc->ah;
2528 struct ath_common *common = ath5k_hw_common(ah);
2531 mutex_lock(&sc->lock);
2533 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2536 * Stop anything previously setup. This is safe
2537 * no matter this is the first time through or not.
2539 ath5k_stop_locked(sc);
2542 * The basic interface to setting the hardware in a good
2543 * state is ``reset''. On return the hardware is known to
2544 * be powered up and with interrupts disabled. This must
2545 * be followed by initialization of the appropriate bits
2546 * and then setup of the interrupt mask.
2548 sc->curchan = sc->hw->conf.channel;
2549 sc->curband = &sc->sbands[sc->curchan->band];
2550 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
2551 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
2552 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_MIB;
2554 ret = ath5k_reset(sc, NULL, false);
2558 ath5k_rfkill_hw_start(ah);
2561 * Reset the key cache since some parts do not reset the
2562 * contents on initial power up or resume from suspend.
2564 for (i = 0; i < common->keymax; i++)
2565 ath_hw_keyreset(common, (u16) i);
2567 /* Use higher rates for acks instead of base
2569 ah->ah_ack_bitrate_high = true;
2571 for (i = 0; i < ARRAY_SIZE(sc->bslot); i++)
2572 sc->bslot[i] = NULL;
2577 mutex_unlock(&sc->lock);
2579 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
2580 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2585 static void stop_tasklets(struct ath5k_softc *sc)
2587 tasklet_kill(&sc->rxtq);
2588 tasklet_kill(&sc->txtq);
2589 tasklet_kill(&sc->calib);
2590 tasklet_kill(&sc->beacontq);
2591 tasklet_kill(&sc->ani_tasklet);
2595 * Stop the device, grabbing the top-level lock to protect
2596 * against concurrent entry through ath5k_init (which can happen
2597 * if another thread does a system call and the thread doing the
2598 * stop is preempted).
2601 ath5k_stop_hw(struct ath5k_softc *sc)
2605 mutex_lock(&sc->lock);
2606 ret = ath5k_stop_locked(sc);
2607 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2609 * Don't set the card in full sleep mode!
2611 * a) When the device is in this state it must be carefully
2612 * woken up or references to registers in the PCI clock
2613 * domain may freeze the bus (and system). This varies
2614 * by chip and is mostly an issue with newer parts
2615 * (madwifi sources mentioned srev >= 0x78) that go to
2616 * sleep more quickly.
2618 * b) On older chips full sleep results a weird behaviour
2619 * during wakeup. I tested various cards with srev < 0x78
2620 * and they don't wake up after module reload, a second
2621 * module reload is needed to bring the card up again.
2623 * Until we figure out what's going on don't enable
2624 * full chip reset on any chip (this is what Legacy HAL
2625 * and Sam's HAL do anyway). Instead Perform a full reset
2626 * on the device (same as initial state after attach) and
2627 * leave it idle (keep MAC/BB on warm reset) */
2628 ret = ath5k_hw_on_hold(sc->ah);
2630 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2631 "putting device to sleep\n");
2635 mutex_unlock(&sc->lock);
2639 cancel_delayed_work_sync(&sc->tx_complete_work);
2641 ath5k_rfkill_hw_stop(sc->ah);
2647 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2648 * and change to the given channel.
2650 * This should be called with sc->lock.
2653 ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan,
2656 struct ath5k_hw *ah = sc->ah;
2659 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
2661 ath5k_hw_set_imr(ah, 0);
2662 synchronize_irq(sc->irq);
2665 /* Save ani mode and disable ANI durring
2666 * reset. If we don't we might get false
2667 * PHY error interrupts. */
2668 ani_mode = ah->ah_sc->ani_state.ani_mode;
2669 ath5k_ani_init(ah, ATH5K_ANI_MODE_OFF);
2671 /* We are going to empty hw queues
2672 * so we should also free any remaining
2674 ath5k_drain_tx_buffs(sc);
2677 sc->curband = &sc->sbands[chan->band];
2679 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, chan != NULL,
2682 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2686 ret = ath5k_rx_start(sc);
2688 ATH5K_ERR(sc, "can't start recv logic\n");
2692 ath5k_ani_init(ah, ani_mode);
2694 ah->ah_cal_next_full = jiffies;
2695 ah->ah_cal_next_ani = jiffies;
2696 ah->ah_cal_next_nf = jiffies;
2697 ewma_init(&ah->ah_beacon_rssi_avg, 1024, 8);
2700 * Change channels and update the h/w rate map if we're switching;
2701 * e.g. 11a to 11b/g.
2703 * We may be doing a reset in response to an ioctl that changes the
2704 * channel so update any state that might change as a result.
2708 /* ath5k_chan_change(sc, c); */
2710 ath5k_beacon_config(sc);
2711 /* intrs are enabled by ath5k_beacon_config */
2713 ieee80211_wake_queues(sc->hw);
2720 static void ath5k_reset_work(struct work_struct *work)
2722 struct ath5k_softc *sc = container_of(work, struct ath5k_softc,
2725 mutex_lock(&sc->lock);
2726 ath5k_reset(sc, NULL, true);
2727 mutex_unlock(&sc->lock);
2731 ath5k_init(struct ieee80211_hw *hw)
2734 struct ath5k_softc *sc = hw->priv;
2735 struct ath5k_hw *ah = sc->ah;
2736 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
2737 struct ath5k_txq *txq;
2738 u8 mac[ETH_ALEN] = {};
2743 * Check if the MAC has multi-rate retry support.
2744 * We do this by trying to setup a fake extended
2745 * descriptor. MACs that don't have support will
2746 * return false w/o doing anything. MACs that do
2747 * support it will return true w/o doing anything.
2749 ret = ath5k_hw_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
2754 __set_bit(ATH_STAT_MRRETRY, sc->status);
2757 * Collect the channel list. The 802.11 layer
2758 * is resposible for filtering this list based
2759 * on settings like the phy mode and regulatory
2760 * domain restrictions.
2762 ret = ath5k_setup_bands(hw);
2764 ATH5K_ERR(sc, "can't get channels\n");
2768 /* NB: setup here so ath5k_rate_update is happy */
2769 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
2770 ath5k_setcurmode(sc, AR5K_MODE_11A);
2772 ath5k_setcurmode(sc, AR5K_MODE_11B);
2775 * Allocate tx+rx descriptors and populate the lists.
2777 ret = ath5k_desc_alloc(sc);
2779 ATH5K_ERR(sc, "can't allocate descriptors\n");
2784 * Allocate hardware transmit queues: one queue for
2785 * beacon frames and one data queue for each QoS
2786 * priority. Note that hw functions handle resetting
2787 * these queues at the needed time.
2789 ret = ath5k_beaconq_setup(ah);
2791 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
2795 sc->cabq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0);
2796 if (IS_ERR(sc->cabq)) {
2797 ATH5K_ERR(sc, "can't setup cab queue\n");
2798 ret = PTR_ERR(sc->cabq);
2802 /* This order matches mac80211's queue priority, so we can
2803 * directly use the mac80211 queue number without any mapping */
2804 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VO);
2806 ATH5K_ERR(sc, "can't setup xmit queue\n");
2810 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VI);
2812 ATH5K_ERR(sc, "can't setup xmit queue\n");
2816 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
2818 ATH5K_ERR(sc, "can't setup xmit queue\n");
2822 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
2824 ATH5K_ERR(sc, "can't setup xmit queue\n");
2830 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
2831 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
2832 tasklet_init(&sc->calib, ath5k_tasklet_calibrate, (unsigned long)sc);
2833 tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc);
2834 tasklet_init(&sc->ani_tasklet, ath5k_tasklet_ani, (unsigned long)sc);
2836 INIT_WORK(&sc->reset_work, ath5k_reset_work);
2837 INIT_DELAYED_WORK(&sc->tx_complete_work, ath5k_tx_complete_poll_work);
2839 ret = ath5k_eeprom_read_mac(ah, mac);
2841 ATH5K_ERR(sc, "unable to read address from EEPROM\n");
2845 SET_IEEE80211_PERM_ADDR(hw, mac);
2846 memcpy(&sc->lladdr, mac, ETH_ALEN);
2847 /* All MAC address bits matter for ACKs */
2848 ath5k_update_bssid_mask_and_opmode(sc, NULL);
2850 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain;
2851 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier);
2853 ATH5K_ERR(sc, "can't initialize regulatory system\n");
2857 ret = ieee80211_register_hw(hw);
2859 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
2863 if (!ath_is_world_regd(regulatory))
2864 regulatory_hint(hw->wiphy, regulatory->alpha2);
2866 ath5k_init_leds(sc);
2868 ath5k_sysfs_register(sc);
2872 ath5k_txq_release(sc);
2874 ath5k_hw_release_tx_queue(ah, sc->bhalq);
2876 ath5k_desc_free(sc);
2882 ath5k_deinit_softc(struct ath5k_softc *sc)
2884 struct ieee80211_hw *hw = sc->hw;
2887 * NB: the order of these is important:
2888 * o call the 802.11 layer before detaching ath5k_hw to
2889 * ensure callbacks into the driver to delete global
2890 * key cache entries can be handled
2891 * o reclaim the tx queue data structures after calling
2892 * the 802.11 layer as we'll get called back to reclaim
2893 * node state and potentially want to use them
2894 * o to cleanup the tx queues the hal is called, so detach
2896 * XXX: ??? detach ath5k_hw ???
2897 * Other than that, it's straightforward...
2899 ath5k_debug_finish_device(sc);
2900 ieee80211_unregister_hw(hw);
2901 ath5k_desc_free(sc);
2902 ath5k_txq_release(sc);
2903 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
2904 ath5k_unregister_leds(sc);
2906 ath5k_sysfs_unregister(sc);
2908 * NB: can't reclaim these until after ieee80211_ifdetach
2909 * returns because we'll get called back to reclaim node
2910 * state and potentially want to use them.
2912 ath5k_hw_deinit(sc->ah);
2913 free_irq(sc->irq, sc);
2916 /********************\
2917 * Mac80211 functions *
2918 \********************/
2921 ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2923 struct ath5k_softc *sc = hw->priv;
2924 u16 qnum = skb_get_queue_mapping(skb);
2926 if (WARN_ON(qnum >= sc->ah->ah_capabilities.cap_queues.q_tx_num)) {
2927 dev_kfree_skb_any(skb);
2931 return ath5k_tx_queue(hw, skb, &sc->txqs[qnum]);
2934 static int ath5k_start(struct ieee80211_hw *hw)
2936 return ath5k_init_hw(hw->priv);
2939 static void ath5k_stop(struct ieee80211_hw *hw)
2941 ath5k_stop_hw(hw->priv);
2944 static int ath5k_add_interface(struct ieee80211_hw *hw,
2945 struct ieee80211_vif *vif)
2947 struct ath5k_softc *sc = hw->priv;
2949 struct ath5k_vif *avf = (void *)vif->drv_priv;
2951 mutex_lock(&sc->lock);
2953 if ((vif->type == NL80211_IFTYPE_AP ||
2954 vif->type == NL80211_IFTYPE_ADHOC)
2955 && (sc->num_ap_vifs + sc->num_adhoc_vifs) >= ATH_BCBUF) {
2960 /* Don't allow other interfaces if one ad-hoc is configured.
2961 * TODO: Fix the problems with ad-hoc and multiple other interfaces.
2962 * We would need to operate the HW in ad-hoc mode to allow TSF updates
2963 * for the IBSS, but this breaks with additional AP or STA interfaces
2965 if (sc->num_adhoc_vifs ||
2966 (sc->nvifs && vif->type == NL80211_IFTYPE_ADHOC)) {
2967 ATH5K_ERR(sc, "Only one single ad-hoc interface is allowed.\n");
2972 switch (vif->type) {
2973 case NL80211_IFTYPE_AP:
2974 case NL80211_IFTYPE_STATION:
2975 case NL80211_IFTYPE_ADHOC:
2976 case NL80211_IFTYPE_MESH_POINT:
2977 avf->opmode = vif->type;
2985 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "add interface mode %d\n", avf->opmode);
2987 /* Assign the vap/adhoc to a beacon xmit slot. */
2988 if ((avf->opmode == NL80211_IFTYPE_AP) ||
2989 (avf->opmode == NL80211_IFTYPE_ADHOC)) {
2992 WARN_ON(list_empty(&sc->bcbuf));
2993 avf->bbuf = list_first_entry(&sc->bcbuf, struct ath5k_buf,
2995 list_del(&avf->bbuf->list);
2998 for (slot = 0; slot < ATH_BCBUF; slot++) {
2999 if (!sc->bslot[slot]) {
3004 BUG_ON(sc->bslot[avf->bslot] != NULL);
3005 sc->bslot[avf->bslot] = vif;
3006 if (avf->opmode == NL80211_IFTYPE_AP)
3009 sc->num_adhoc_vifs++;
3012 /* Any MAC address is fine, all others are included through the
3015 memcpy(&sc->lladdr, vif->addr, ETH_ALEN);
3016 ath5k_hw_set_lladdr(sc->ah, vif->addr);
3018 memcpy(&avf->lladdr, vif->addr, ETH_ALEN);
3020 ath5k_mode_setup(sc, vif);
3024 mutex_unlock(&sc->lock);
3029 ath5k_remove_interface(struct ieee80211_hw *hw,
3030 struct ieee80211_vif *vif)
3032 struct ath5k_softc *sc = hw->priv;
3033 struct ath5k_vif *avf = (void *)vif->drv_priv;
3036 mutex_lock(&sc->lock);
3040 ath5k_txbuf_free_skb(sc, avf->bbuf);
3041 list_add_tail(&avf->bbuf->list, &sc->bcbuf);
3042 for (i = 0; i < ATH_BCBUF; i++) {
3043 if (sc->bslot[i] == vif) {
3044 sc->bslot[i] = NULL;
3050 if (avf->opmode == NL80211_IFTYPE_AP)
3052 else if (avf->opmode == NL80211_IFTYPE_ADHOC)
3053 sc->num_adhoc_vifs--;
3055 ath5k_update_bssid_mask_and_opmode(sc, NULL);
3056 mutex_unlock(&sc->lock);
3060 * TODO: Phy disable/diversity etc
3063 ath5k_config(struct ieee80211_hw *hw, u32 changed)
3065 struct ath5k_softc *sc = hw->priv;
3066 struct ath5k_hw *ah = sc->ah;
3067 struct ieee80211_conf *conf = &hw->conf;
3070 mutex_lock(&sc->lock);
3072 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
3073 ret = ath5k_chan_set(sc, conf->channel);
3078 if ((changed & IEEE80211_CONF_CHANGE_POWER) &&
3079 (sc->power_level != conf->power_level)) {
3080 sc->power_level = conf->power_level;
3083 ath5k_hw_set_txpower_limit(ah, (conf->power_level * 2));
3087 * 1) Move this on config_interface and handle each case
3088 * separately eg. when we have only one STA vif, use
3089 * AR5K_ANTMODE_SINGLE_AP
3091 * 2) Allow the user to change antenna mode eg. when only
3092 * one antenna is present
3094 * 3) Allow the user to set default/tx antenna when possible
3096 * 4) Default mode should handle 90% of the cases, together
3097 * with fixed a/b and single AP modes we should be able to
3098 * handle 99%. Sectored modes are extreme cases and i still
3099 * haven't found a usage for them. If we decide to support them,
3100 * then we must allow the user to set how many tx antennas we
3103 ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode);
3106 mutex_unlock(&sc->lock);
3110 static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw,
3111 struct netdev_hw_addr_list *mc_list)
3115 struct netdev_hw_addr *ha;
3120 netdev_hw_addr_list_for_each(ha, mc_list) {
3121 /* calculate XOR of eight 6-bit values */
3122 val = get_unaligned_le32(ha->addr + 0);
3123 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
3124 val = get_unaligned_le32(ha->addr + 3);
3125 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
3127 mfilt[pos / 32] |= (1 << (pos % 32));
3128 /* XXX: we might be able to just do this instead,
3129 * but not sure, needs testing, if we do use this we'd
3130 * neet to inform below to not reset the mcast */
3131 /* ath5k_hw_set_mcast_filterindex(ah,
3135 return ((u64)(mfilt[1]) << 32) | mfilt[0];
3138 static bool ath_any_vif_assoc(struct ath5k_softc *sc)
3140 struct ath_vif_iter_data iter_data;
3141 iter_data.hw_macaddr = NULL;
3142 iter_data.any_assoc = false;
3143 iter_data.need_set_hw_addr = false;
3144 iter_data.found_active = true;
3146 ieee80211_iterate_active_interfaces_atomic(sc->hw, ath_vif_iter,
3148 return iter_data.any_assoc;
3151 #define SUPPORTED_FIF_FLAGS \
3152 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
3153 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
3154 FIF_BCN_PRBRESP_PROMISC
3156 * o always accept unicast, broadcast, and multicast traffic
3157 * o multicast traffic for all BSSIDs will be enabled if mac80211
3159 * o maintain current state of phy ofdm or phy cck error reception.
3160 * If the hardware detects any of these type of errors then
3161 * ath5k_hw_get_rx_filter() will pass to us the respective
3162 * hardware filters to be able to receive these type of frames.
3163 * o probe request frames are accepted only when operating in
3164 * hostap, adhoc, or monitor modes
3165 * o enable promiscuous mode according to the interface state
3167 * - when operating in adhoc mode so the 802.11 layer creates
3168 * node table entries for peers,
3169 * - when operating in station mode for collecting rssi data when
3170 * the station is otherwise quiet, or
3173 static void ath5k_configure_filter(struct ieee80211_hw *hw,
3174 unsigned int changed_flags,
3175 unsigned int *new_flags,
3178 struct ath5k_softc *sc = hw->priv;
3179 struct ath5k_hw *ah = sc->ah;
3180 u32 mfilt[2], rfilt;
3182 mutex_lock(&sc->lock);
3184 mfilt[0] = multicast;
3185 mfilt[1] = multicast >> 32;
3187 /* Only deal with supported flags */
3188 changed_flags &= SUPPORTED_FIF_FLAGS;
3189 *new_flags &= SUPPORTED_FIF_FLAGS;
3191 /* If HW detects any phy or radar errors, leave those filters on.
3192 * Also, always enable Unicast, Broadcasts and Multicast
3193 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
3194 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
3195 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
3196 AR5K_RX_FILTER_MCAST);
3198 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
3199 if (*new_flags & FIF_PROMISC_IN_BSS) {
3200 __set_bit(ATH_STAT_PROMISC, sc->status);
3202 __clear_bit(ATH_STAT_PROMISC, sc->status);
3206 if (test_bit(ATH_STAT_PROMISC, sc->status))
3207 rfilt |= AR5K_RX_FILTER_PROM;
3209 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
3210 if (*new_flags & FIF_ALLMULTI) {
3215 /* This is the best we can do */
3216 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
3217 rfilt |= AR5K_RX_FILTER_PHYERR;
3219 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
3220 * and probes for any BSSID */
3221 if ((*new_flags & FIF_BCN_PRBRESP_PROMISC) || (sc->nvifs > 1))
3222 rfilt |= AR5K_RX_FILTER_BEACON;
3224 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
3225 * set we should only pass on control frames for this
3226 * station. This needs testing. I believe right now this
3227 * enables *all* control frames, which is OK.. but
3228 * but we should see if we can improve on granularity */
3229 if (*new_flags & FIF_CONTROL)
3230 rfilt |= AR5K_RX_FILTER_CONTROL;
3232 /* Additional settings per mode -- this is per ath5k */
3234 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
3236 switch (sc->opmode) {
3237 case NL80211_IFTYPE_MESH_POINT:
3238 rfilt |= AR5K_RX_FILTER_CONTROL |
3239 AR5K_RX_FILTER_BEACON |
3240 AR5K_RX_FILTER_PROBEREQ |
3241 AR5K_RX_FILTER_PROM;
3243 case NL80211_IFTYPE_AP:
3244 case NL80211_IFTYPE_ADHOC:
3245 rfilt |= AR5K_RX_FILTER_PROBEREQ |
3246 AR5K_RX_FILTER_BEACON;
3248 case NL80211_IFTYPE_STATION:
3250 rfilt |= AR5K_RX_FILTER_BEACON;
3256 ath5k_hw_set_rx_filter(ah, rfilt);
3258 /* Set multicast bits */
3259 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
3260 /* Set the cached hw filter flags, this will later actually
3262 sc->filter_flags = rfilt;
3264 mutex_unlock(&sc->lock);
3268 ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3269 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3270 struct ieee80211_key_conf *key)
3272 struct ath5k_softc *sc = hw->priv;
3273 struct ath5k_hw *ah = sc->ah;
3274 struct ath_common *common = ath5k_hw_common(ah);
3277 if (modparam_nohwcrypt)
3280 switch (key->cipher) {
3281 case WLAN_CIPHER_SUITE_WEP40:
3282 case WLAN_CIPHER_SUITE_WEP104:
3283 case WLAN_CIPHER_SUITE_TKIP:
3285 case WLAN_CIPHER_SUITE_CCMP:
3286 if (common->crypt_caps & ATH_CRYPT_CAP_CIPHER_AESCCM)
3294 mutex_lock(&sc->lock);
3298 ret = ath_key_config(common, vif, sta, key);
3300 key->hw_key_idx = ret;
3301 /* push IV and Michael MIC generation to stack */
3302 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
3303 if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
3304 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
3305 if (key->cipher == WLAN_CIPHER_SUITE_CCMP)
3306 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
3311 ath_key_delete(common, key);
3318 mutex_unlock(&sc->lock);
3323 ath5k_get_stats(struct ieee80211_hw *hw,
3324 struct ieee80211_low_level_stats *stats)
3326 struct ath5k_softc *sc = hw->priv;
3329 ath5k_hw_update_mib_counters(sc->ah);
3331 stats->dot11ACKFailureCount = sc->stats.ack_fail;
3332 stats->dot11RTSFailureCount = sc->stats.rts_fail;
3333 stats->dot11RTSSuccessCount = sc->stats.rts_ok;
3334 stats->dot11FCSErrorCount = sc->stats.fcs_error;
3339 static int ath5k_get_survey(struct ieee80211_hw *hw, int idx,
3340 struct survey_info *survey)
3342 struct ath5k_softc *sc = hw->priv;
3343 struct ieee80211_conf *conf = &hw->conf;
3344 struct ath_common *common = ath5k_hw_common(sc->ah);
3345 struct ath_cycle_counters *cc = &common->cc_survey;
3346 unsigned int div = common->clockrate * 1000;
3351 survey->channel = conf->channel;
3352 survey->filled = SURVEY_INFO_NOISE_DBM;
3353 survey->noise = sc->ah->ah_noise_floor;
3355 spin_lock_bh(&common->cc_lock);
3356 ath_hw_cycle_counters_update(common);
3357 if (cc->cycles > 0) {
3358 survey->filled |= SURVEY_INFO_CHANNEL_TIME |
3359 SURVEY_INFO_CHANNEL_TIME_BUSY |
3360 SURVEY_INFO_CHANNEL_TIME_RX |
3361 SURVEY_INFO_CHANNEL_TIME_TX;
3362 survey->channel_time += cc->cycles / div;
3363 survey->channel_time_busy += cc->rx_busy / div;
3364 survey->channel_time_rx += cc->rx_frame / div;
3365 survey->channel_time_tx += cc->tx_frame / div;
3367 memset(cc, 0, sizeof(*cc));
3368 spin_unlock_bh(&common->cc_lock);
3374 ath5k_get_tsf(struct ieee80211_hw *hw)
3376 struct ath5k_softc *sc = hw->priv;
3378 return ath5k_hw_get_tsf64(sc->ah);
3382 ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3384 struct ath5k_softc *sc = hw->priv;
3386 ath5k_hw_set_tsf64(sc->ah, tsf);
3390 ath5k_reset_tsf(struct ieee80211_hw *hw)
3392 struct ath5k_softc *sc = hw->priv;
3395 * in IBSS mode we need to update the beacon timers too.
3396 * this will also reset the TSF if we call it with 0
3398 if (sc->opmode == NL80211_IFTYPE_ADHOC)
3399 ath5k_beacon_update_timers(sc, 0);
3401 ath5k_hw_reset_tsf(sc->ah);
3405 set_beacon_filter(struct ieee80211_hw *hw, bool enable)
3407 struct ath5k_softc *sc = hw->priv;
3408 struct ath5k_hw *ah = sc->ah;
3410 rfilt = ath5k_hw_get_rx_filter(ah);
3412 rfilt |= AR5K_RX_FILTER_BEACON;
3414 rfilt &= ~AR5K_RX_FILTER_BEACON;
3415 ath5k_hw_set_rx_filter(ah, rfilt);
3416 sc->filter_flags = rfilt;
3419 static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
3420 struct ieee80211_vif *vif,
3421 struct ieee80211_bss_conf *bss_conf,
3424 struct ath5k_vif *avf = (void *)vif->drv_priv;
3425 struct ath5k_softc *sc = hw->priv;
3426 struct ath5k_hw *ah = sc->ah;
3427 struct ath_common *common = ath5k_hw_common(ah);
3428 unsigned long flags;
3430 mutex_lock(&sc->lock);
3432 if (changes & BSS_CHANGED_BSSID) {
3433 /* Cache for later use during resets */
3434 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
3436 ath5k_hw_set_bssid(ah);
3440 if (changes & BSS_CHANGED_BEACON_INT)
3441 sc->bintval = bss_conf->beacon_int;
3443 if (changes & BSS_CHANGED_ASSOC) {
3444 avf->assoc = bss_conf->assoc;
3445 if (bss_conf->assoc)
3446 sc->assoc = bss_conf->assoc;
3448 sc->assoc = ath_any_vif_assoc(sc);
3450 if (sc->opmode == NL80211_IFTYPE_STATION)
3451 set_beacon_filter(hw, sc->assoc);
3452 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3453 AR5K_LED_ASSOC : AR5K_LED_INIT);
3454 if (bss_conf->assoc) {
3455 ATH5K_DBG(sc, ATH5K_DEBUG_ANY,
3456 "Bss Info ASSOC %d, bssid: %pM\n",
3457 bss_conf->aid, common->curbssid);
3458 common->curaid = bss_conf->aid;
3459 ath5k_hw_set_bssid(ah);
3460 /* Once ANI is available you would start it here */
3464 if (changes & BSS_CHANGED_BEACON) {
3465 spin_lock_irqsave(&sc->block, flags);
3466 ath5k_beacon_update(hw, vif);
3467 spin_unlock_irqrestore(&sc->block, flags);
3470 if (changes & BSS_CHANGED_BEACON_ENABLED)
3471 sc->enable_beacon = bss_conf->enable_beacon;
3473 if (changes & (BSS_CHANGED_BEACON | BSS_CHANGED_BEACON_ENABLED |
3474 BSS_CHANGED_BEACON_INT))
3475 ath5k_beacon_config(sc);
3477 mutex_unlock(&sc->lock);
3480 static void ath5k_sw_scan_start(struct ieee80211_hw *hw)
3482 struct ath5k_softc *sc = hw->priv;
3484 ath5k_hw_set_ledstate(sc->ah, AR5K_LED_SCAN);
3487 static void ath5k_sw_scan_complete(struct ieee80211_hw *hw)
3489 struct ath5k_softc *sc = hw->priv;
3490 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3491 AR5K_LED_ASSOC : AR5K_LED_INIT);
3495 * ath5k_set_coverage_class - Set IEEE 802.11 coverage class
3497 * @hw: struct ieee80211_hw pointer
3498 * @coverage_class: IEEE 802.11 coverage class number
3500 * Mac80211 callback. Sets slot time, ACK timeout and CTS timeout for given
3501 * coverage class. The values are persistent, they are restored after device
3504 static void ath5k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
3506 struct ath5k_softc *sc = hw->priv;
3508 mutex_lock(&sc->lock);
3509 ath5k_hw_set_coverage_class(sc->ah, coverage_class);
3510 mutex_unlock(&sc->lock);
3513 static int ath5k_conf_tx(struct ieee80211_hw *hw, u16 queue,
3514 const struct ieee80211_tx_queue_params *params)
3516 struct ath5k_softc *sc = hw->priv;
3517 struct ath5k_hw *ah = sc->ah;
3518 struct ath5k_txq_info qi;
3521 if (queue >= ah->ah_capabilities.cap_queues.q_tx_num)
3524 mutex_lock(&sc->lock);
3526 ath5k_hw_get_tx_queueprops(ah, queue, &qi);
3528 qi.tqi_aifs = params->aifs;
3529 qi.tqi_cw_min = params->cw_min;
3530 qi.tqi_cw_max = params->cw_max;
3531 qi.tqi_burst_time = params->txop;
3533 ATH5K_DBG(sc, ATH5K_DEBUG_ANY,
3534 "Configure tx [queue %d], "
3535 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
3536 queue, params->aifs, params->cw_min,
3537 params->cw_max, params->txop);
3539 if (ath5k_hw_set_tx_queueprops(ah, queue, &qi)) {
3541 "Unable to update hardware queue %u!\n", queue);
3544 ath5k_hw_reset_tx_queue(ah, queue);
3546 mutex_unlock(&sc->lock);
3551 static int ath5k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
3553 struct ath5k_softc *sc = hw->priv;
3555 if (tx_ant == 1 && rx_ant == 1)
3556 ath5k_hw_set_antenna_mode(sc->ah, AR5K_ANTMODE_FIXED_A);
3557 else if (tx_ant == 2 && rx_ant == 2)
3558 ath5k_hw_set_antenna_mode(sc->ah, AR5K_ANTMODE_FIXED_B);
3559 else if ((tx_ant & 3) == 3 && (rx_ant & 3) == 3)
3560 ath5k_hw_set_antenna_mode(sc->ah, AR5K_ANTMODE_DEFAULT);
3566 static int ath5k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
3568 struct ath5k_softc *sc = hw->priv;
3570 switch (sc->ah->ah_ant_mode) {
3571 case AR5K_ANTMODE_FIXED_A:
3572 *tx_ant = 1; *rx_ant = 1; break;
3573 case AR5K_ANTMODE_FIXED_B:
3574 *tx_ant = 2; *rx_ant = 2; break;
3575 case AR5K_ANTMODE_DEFAULT:
3576 *tx_ant = 3; *rx_ant = 3; break;
3581 const struct ieee80211_ops ath5k_hw_ops = {
3583 .start = ath5k_start,
3585 .add_interface = ath5k_add_interface,
3586 .remove_interface = ath5k_remove_interface,
3587 .config = ath5k_config,
3588 .prepare_multicast = ath5k_prepare_multicast,
3589 .configure_filter = ath5k_configure_filter,
3590 .set_key = ath5k_set_key,
3591 .get_stats = ath5k_get_stats,
3592 .get_survey = ath5k_get_survey,
3593 .conf_tx = ath5k_conf_tx,
3594 .get_tsf = ath5k_get_tsf,
3595 .set_tsf = ath5k_set_tsf,
3596 .reset_tsf = ath5k_reset_tsf,
3597 .bss_info_changed = ath5k_bss_info_changed,
3598 .sw_scan_start = ath5k_sw_scan_start,
3599 .sw_scan_complete = ath5k_sw_scan_complete,
3600 .set_coverage_class = ath5k_set_coverage_class,
3601 .set_antenna = ath5k_set_antenna,
3602 .get_antenna = ath5k_get_antenna,
projects / firefly-linux-kernel-4.4.55.git / blob