2 * Copyright (c) 2004-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2012 Qualcomm Atheros, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include <linux/module.h>
19 #include <linux/mmc/card.h>
20 #include <linux/mmc/mmc.h>
21 #include <linux/mmc/host.h>
22 #include <linux/mmc/sdio_func.h>
23 #include <linux/mmc/sdio_ids.h>
24 #include <linux/mmc/sdio.h>
25 #include <linux/mmc/sd.h>
33 struct sdio_func *func;
38 struct list_head bus_req_freeq;
40 /* available bus requests */
41 struct bus_request bus_req[BUS_REQUEST_MAX_NUM];
47 /* protects access to dma_buffer */
48 struct mutex dma_buffer_mutex;
50 /* scatter request list head */
51 struct list_head scat_req;
53 atomic_t irq_handling;
54 wait_queue_head_t irq_wq;
60 const struct sdio_device_id *id;
61 struct work_struct wr_async_work;
62 struct list_head wr_asyncq;
63 spinlock_t wr_async_lock;
66 #define CMD53_ARG_READ 0
67 #define CMD53_ARG_WRITE 1
68 #define CMD53_ARG_BLOCK_BASIS 1
69 #define CMD53_ARG_FIXED_ADDRESS 0
70 #define CMD53_ARG_INCR_ADDRESS 1
72 static inline struct ath6kl_sdio *ath6kl_sdio_priv(struct ath6kl *ar)
78 * Macro to check if DMA buffer is WORD-aligned and DMA-able.
79 * Most host controllers assume the buffer is DMA'able and will
80 * bug-check otherwise (i.e. buffers on the stack). virt_addr_valid
81 * check fails on stack memory.
83 static inline bool buf_needs_bounce(u8 *buf)
85 return ((unsigned long) buf & 0x3) || !virt_addr_valid(buf);
88 static void ath6kl_sdio_set_mbox_info(struct ath6kl *ar)
90 struct ath6kl_mbox_info *mbox_info = &ar->mbox_info;
92 /* EP1 has an extended range */
93 mbox_info->htc_addr = HIF_MBOX_BASE_ADDR;
94 mbox_info->htc_ext_addr = HIF_MBOX0_EXT_BASE_ADDR;
95 mbox_info->htc_ext_sz = HIF_MBOX0_EXT_WIDTH;
96 mbox_info->block_size = HIF_MBOX_BLOCK_SIZE;
97 mbox_info->gmbox_addr = HIF_GMBOX_BASE_ADDR;
98 mbox_info->gmbox_sz = HIF_GMBOX_WIDTH;
101 static inline void ath6kl_sdio_set_cmd53_arg(u32 *arg, u8 rw, u8 func,
102 u8 mode, u8 opcode, u32 addr,
105 *arg = (((rw & 1) << 31) |
106 ((func & 0x7) << 28) |
108 ((opcode & 1) << 26) |
109 ((addr & 0x1FFFF) << 9) |
113 static inline void ath6kl_sdio_set_cmd52_arg(u32 *arg, u8 write, u8 raw,
114 unsigned int address,
119 *arg = ((write & 1) << 31) |
120 ((func & 0x7) << 28) |
123 ((address & 0x1FFFF) << 9) |
128 static int ath6kl_sdio_func0_cmd52_wr_byte(struct mmc_card *card,
129 unsigned int address,
132 struct mmc_command io_cmd;
134 memset(&io_cmd, 0, sizeof(io_cmd));
135 ath6kl_sdio_set_cmd52_arg(&io_cmd.arg, 1, 0, address, byte);
136 io_cmd.opcode = SD_IO_RW_DIRECT;
137 io_cmd.flags = MMC_RSP_R5 | MMC_CMD_AC;
139 return mmc_wait_for_cmd(card->host, &io_cmd, 0);
142 static int ath6kl_sdio_io(struct sdio_func *func, u32 request, u32 addr,
147 sdio_claim_host(func);
149 if (request & HIF_WRITE) {
150 /* FIXME: looks like ugly workaround for something */
151 if (addr >= HIF_MBOX_BASE_ADDR &&
152 addr <= HIF_MBOX_END_ADDR)
153 addr += (HIF_MBOX_WIDTH - len);
155 /* FIXME: this also looks like ugly workaround */
156 if (addr == HIF_MBOX0_EXT_BASE_ADDR)
157 addr += HIF_MBOX0_EXT_WIDTH - len;
159 if (request & HIF_FIXED_ADDRESS)
160 ret = sdio_writesb(func, addr, buf, len);
162 ret = sdio_memcpy_toio(func, addr, buf, len);
164 if (request & HIF_FIXED_ADDRESS)
165 ret = sdio_readsb(func, buf, addr, len);
167 ret = sdio_memcpy_fromio(func, buf, addr, len);
170 sdio_release_host(func);
172 ath6kl_dbg(ATH6KL_DBG_SDIO, "%s addr 0x%x%s buf 0x%p len %d\n",
173 request & HIF_WRITE ? "wr" : "rd", addr,
174 request & HIF_FIXED_ADDRESS ? " (fixed)" : "", buf, len);
175 ath6kl_dbg_dump(ATH6KL_DBG_SDIO_DUMP, NULL, "sdio ", buf, len);
180 static struct bus_request *ath6kl_sdio_alloc_busreq(struct ath6kl_sdio *ar_sdio)
182 struct bus_request *bus_req;
184 spin_lock_bh(&ar_sdio->lock);
186 if (list_empty(&ar_sdio->bus_req_freeq)) {
187 spin_unlock_bh(&ar_sdio->lock);
191 bus_req = list_first_entry(&ar_sdio->bus_req_freeq,
192 struct bus_request, list);
193 list_del(&bus_req->list);
195 spin_unlock_bh(&ar_sdio->lock);
196 ath6kl_dbg(ATH6KL_DBG_SCATTER, "%s: bus request 0x%p\n",
202 static void ath6kl_sdio_free_bus_req(struct ath6kl_sdio *ar_sdio,
203 struct bus_request *bus_req)
205 ath6kl_dbg(ATH6KL_DBG_SCATTER, "%s: bus request 0x%p\n",
208 spin_lock_bh(&ar_sdio->lock);
209 list_add_tail(&bus_req->list, &ar_sdio->bus_req_freeq);
210 spin_unlock_bh(&ar_sdio->lock);
213 static void ath6kl_sdio_setup_scat_data(struct hif_scatter_req *scat_req,
214 struct mmc_data *data)
216 struct scatterlist *sg;
219 data->blksz = HIF_MBOX_BLOCK_SIZE;
220 data->blocks = scat_req->len / HIF_MBOX_BLOCK_SIZE;
222 ath6kl_dbg(ATH6KL_DBG_SCATTER,
223 "hif-scatter: (%s) addr: 0x%X, (block len: %d, block count: %d) , (tot:%d,sg:%d)\n",
224 (scat_req->req & HIF_WRITE) ? "WR" : "RD", scat_req->addr,
225 data->blksz, data->blocks, scat_req->len,
226 scat_req->scat_entries);
228 data->flags = (scat_req->req & HIF_WRITE) ? MMC_DATA_WRITE :
231 /* fill SG entries */
232 sg = scat_req->sgentries;
233 sg_init_table(sg, scat_req->scat_entries);
235 /* assemble SG list */
236 for (i = 0; i < scat_req->scat_entries; i++, sg++) {
237 ath6kl_dbg(ATH6KL_DBG_SCATTER, "%d: addr:0x%p, len:%d\n",
238 i, scat_req->scat_list[i].buf,
239 scat_req->scat_list[i].len);
241 sg_set_buf(sg, scat_req->scat_list[i].buf,
242 scat_req->scat_list[i].len);
245 /* set scatter-gather table for request */
246 data->sg = scat_req->sgentries;
247 data->sg_len = scat_req->scat_entries;
250 static int ath6kl_sdio_scat_rw(struct ath6kl_sdio *ar_sdio,
251 struct bus_request *req)
253 struct mmc_request mmc_req;
254 struct mmc_command cmd;
255 struct mmc_data data;
256 struct hif_scatter_req *scat_req;
260 scat_req = req->scat_req;
262 if (scat_req->virt_scat) {
264 if (scat_req->req & HIF_BLOCK_BASIS)
265 len = round_down(len, HIF_MBOX_BLOCK_SIZE);
267 status = ath6kl_sdio_io(ar_sdio->func, scat_req->req,
268 scat_req->addr, scat_req->virt_dma_buf,
273 memset(&mmc_req, 0, sizeof(struct mmc_request));
274 memset(&cmd, 0, sizeof(struct mmc_command));
275 memset(&data, 0, sizeof(struct mmc_data));
277 ath6kl_sdio_setup_scat_data(scat_req, &data);
279 opcode = (scat_req->req & HIF_FIXED_ADDRESS) ?
280 CMD53_ARG_FIXED_ADDRESS : CMD53_ARG_INCR_ADDRESS;
282 rw = (scat_req->req & HIF_WRITE) ? CMD53_ARG_WRITE : CMD53_ARG_READ;
284 /* Fixup the address so that the last byte will fall on MBOX EOM */
285 if (scat_req->req & HIF_WRITE) {
286 if (scat_req->addr == HIF_MBOX_BASE_ADDR)
287 scat_req->addr += HIF_MBOX_WIDTH - scat_req->len;
289 /* Uses extended address range */
290 scat_req->addr += HIF_MBOX0_EXT_WIDTH - scat_req->len;
293 /* set command argument */
294 ath6kl_sdio_set_cmd53_arg(&cmd.arg, rw, ar_sdio->func->num,
295 CMD53_ARG_BLOCK_BASIS, opcode, scat_req->addr,
298 cmd.opcode = SD_IO_RW_EXTENDED;
299 cmd.flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_ADTC;
302 mmc_req.data = &data;
304 sdio_claim_host(ar_sdio->func);
306 mmc_set_data_timeout(&data, ar_sdio->func->card);
307 /* synchronous call to process request */
308 mmc_wait_for_req(ar_sdio->func->card->host, &mmc_req);
310 sdio_release_host(ar_sdio->func);
312 status = cmd.error ? cmd.error : data.error;
315 scat_req->status = status;
317 if (scat_req->status)
318 ath6kl_err("Scatter write request failed:%d\n",
321 if (scat_req->req & HIF_ASYNCHRONOUS)
322 scat_req->complete(ar_sdio->ar->htc_target, scat_req);
327 static int ath6kl_sdio_alloc_prep_scat_req(struct ath6kl_sdio *ar_sdio,
328 int n_scat_entry, int n_scat_req,
331 struct hif_scatter_req *s_req;
332 struct bus_request *bus_req;
333 int i, scat_req_sz, scat_list_sz, sg_sz, buf_sz;
336 scat_list_sz = (n_scat_entry - 1) * sizeof(struct hif_scatter_item);
337 scat_req_sz = sizeof(*s_req) + scat_list_sz;
340 sg_sz = sizeof(struct scatterlist) * n_scat_entry;
342 buf_sz = 2 * L1_CACHE_BYTES +
343 ATH6KL_MAX_TRANSFER_SIZE_PER_SCATTER;
345 for (i = 0; i < n_scat_req; i++) {
346 /* allocate the scatter request */
347 s_req = kzalloc(scat_req_sz, GFP_KERNEL);
352 virt_buf = kzalloc(buf_sz, GFP_KERNEL);
358 s_req->virt_dma_buf =
359 (u8 *)L1_CACHE_ALIGN((unsigned long)virt_buf);
361 /* allocate sglist */
362 s_req->sgentries = kzalloc(sg_sz, GFP_KERNEL);
364 if (!s_req->sgentries) {
370 /* allocate a bus request for this scatter request */
371 bus_req = ath6kl_sdio_alloc_busreq(ar_sdio);
373 kfree(s_req->sgentries);
374 kfree(s_req->virt_dma_buf);
379 /* assign the scatter request to this bus request */
380 bus_req->scat_req = s_req;
381 s_req->busrequest = bus_req;
383 s_req->virt_scat = virt_scat;
385 /* add it to the scatter pool */
386 hif_scatter_req_add(ar_sdio->ar, s_req);
392 static int ath6kl_sdio_read_write_sync(struct ath6kl *ar, u32 addr, u8 *buf,
393 u32 len, u32 request)
395 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
398 bool bounced = false;
400 if (request & HIF_BLOCK_BASIS)
401 len = round_down(len, HIF_MBOX_BLOCK_SIZE);
403 if (buf_needs_bounce(buf)) {
404 if (!ar_sdio->dma_buffer)
406 mutex_lock(&ar_sdio->dma_buffer_mutex);
407 tbuf = ar_sdio->dma_buffer;
409 if (request & HIF_WRITE)
410 memcpy(tbuf, buf, len);
416 ret = ath6kl_sdio_io(ar_sdio->func, request, addr, tbuf, len);
417 if ((request & HIF_READ) && bounced)
418 memcpy(buf, tbuf, len);
421 mutex_unlock(&ar_sdio->dma_buffer_mutex);
426 static void __ath6kl_sdio_write_async(struct ath6kl_sdio *ar_sdio,
427 struct bus_request *req)
430 ath6kl_sdio_scat_rw(ar_sdio, req);
435 status = ath6kl_sdio_read_write_sync(ar_sdio->ar, req->address,
436 req->buffer, req->length,
438 context = req->packet;
439 ath6kl_sdio_free_bus_req(ar_sdio, req);
440 ath6kl_hif_rw_comp_handler(context, status);
444 static void ath6kl_sdio_write_async_work(struct work_struct *work)
446 struct ath6kl_sdio *ar_sdio;
447 struct bus_request *req, *tmp_req;
449 ar_sdio = container_of(work, struct ath6kl_sdio, wr_async_work);
451 spin_lock_bh(&ar_sdio->wr_async_lock);
452 list_for_each_entry_safe(req, tmp_req, &ar_sdio->wr_asyncq, list) {
453 list_del(&req->list);
454 spin_unlock_bh(&ar_sdio->wr_async_lock);
455 __ath6kl_sdio_write_async(ar_sdio, req);
456 spin_lock_bh(&ar_sdio->wr_async_lock);
458 spin_unlock_bh(&ar_sdio->wr_async_lock);
461 static void ath6kl_sdio_irq_handler(struct sdio_func *func)
464 struct ath6kl_sdio *ar_sdio;
466 ath6kl_dbg(ATH6KL_DBG_SDIO, "irq\n");
468 ar_sdio = sdio_get_drvdata(func);
469 atomic_set(&ar_sdio->irq_handling, 1);
471 * Release the host during interrups so we can pick it back up when
472 * we process commands.
474 sdio_release_host(ar_sdio->func);
476 status = ath6kl_hif_intr_bh_handler(ar_sdio->ar);
477 sdio_claim_host(ar_sdio->func);
479 atomic_set(&ar_sdio->irq_handling, 0);
480 wake_up(&ar_sdio->irq_wq);
482 WARN_ON(status && status != -ECANCELED);
485 static int ath6kl_sdio_power_on(struct ath6kl *ar)
487 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
488 struct sdio_func *func = ar_sdio->func;
491 if (!ar_sdio->is_disabled)
494 ath6kl_dbg(ATH6KL_DBG_BOOT, "sdio power on\n");
496 sdio_claim_host(func);
498 ret = sdio_enable_func(func);
500 ath6kl_err("Unable to enable sdio func: %d)\n", ret);
501 sdio_release_host(func);
505 sdio_release_host(func);
508 * Wait for hardware to initialise. It should take a lot less than
509 * 10 ms but let's be conservative here.
513 ar_sdio->is_disabled = false;
518 static int ath6kl_sdio_power_off(struct ath6kl *ar)
520 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
523 if (ar_sdio->is_disabled)
526 ath6kl_dbg(ATH6KL_DBG_BOOT, "sdio power off\n");
528 /* Disable the card */
529 sdio_claim_host(ar_sdio->func);
530 ret = sdio_disable_func(ar_sdio->func);
531 sdio_release_host(ar_sdio->func);
536 ar_sdio->is_disabled = true;
541 static int ath6kl_sdio_write_async(struct ath6kl *ar, u32 address, u8 *buffer,
542 u32 length, u32 request,
543 struct htc_packet *packet)
545 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
546 struct bus_request *bus_req;
548 bus_req = ath6kl_sdio_alloc_busreq(ar_sdio);
553 bus_req->address = address;
554 bus_req->buffer = buffer;
555 bus_req->length = length;
556 bus_req->request = request;
557 bus_req->packet = packet;
559 spin_lock_bh(&ar_sdio->wr_async_lock);
560 list_add_tail(&bus_req->list, &ar_sdio->wr_asyncq);
561 spin_unlock_bh(&ar_sdio->wr_async_lock);
562 queue_work(ar->ath6kl_wq, &ar_sdio->wr_async_work);
567 static void ath6kl_sdio_irq_enable(struct ath6kl *ar)
569 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
572 sdio_claim_host(ar_sdio->func);
574 /* Register the isr */
575 ret = sdio_claim_irq(ar_sdio->func, ath6kl_sdio_irq_handler);
577 ath6kl_err("Failed to claim sdio irq: %d\n", ret);
579 sdio_release_host(ar_sdio->func);
582 static bool ath6kl_sdio_is_on_irq(struct ath6kl *ar)
584 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
586 return !atomic_read(&ar_sdio->irq_handling);
589 static void ath6kl_sdio_irq_disable(struct ath6kl *ar)
591 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
594 sdio_claim_host(ar_sdio->func);
596 if (atomic_read(&ar_sdio->irq_handling)) {
597 sdio_release_host(ar_sdio->func);
599 ret = wait_event_interruptible(ar_sdio->irq_wq,
600 ath6kl_sdio_is_on_irq(ar));
604 sdio_claim_host(ar_sdio->func);
607 ret = sdio_release_irq(ar_sdio->func);
609 ath6kl_err("Failed to release sdio irq: %d\n", ret);
611 sdio_release_host(ar_sdio->func);
614 static struct hif_scatter_req *ath6kl_sdio_scatter_req_get(struct ath6kl *ar)
616 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
617 struct hif_scatter_req *node = NULL;
619 spin_lock_bh(&ar_sdio->scat_lock);
621 if (!list_empty(&ar_sdio->scat_req)) {
622 node = list_first_entry(&ar_sdio->scat_req,
623 struct hif_scatter_req, list);
624 list_del(&node->list);
626 node->scat_q_depth = get_queue_depth(&ar_sdio->scat_req);
629 spin_unlock_bh(&ar_sdio->scat_lock);
634 static void ath6kl_sdio_scatter_req_add(struct ath6kl *ar,
635 struct hif_scatter_req *s_req)
637 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
639 spin_lock_bh(&ar_sdio->scat_lock);
641 list_add_tail(&s_req->list, &ar_sdio->scat_req);
643 spin_unlock_bh(&ar_sdio->scat_lock);
647 /* scatter gather read write request */
648 static int ath6kl_sdio_async_rw_scatter(struct ath6kl *ar,
649 struct hif_scatter_req *scat_req)
651 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
652 u32 request = scat_req->req;
658 ath6kl_dbg(ATH6KL_DBG_SCATTER,
659 "hif-scatter: total len: %d scatter entries: %d\n",
660 scat_req->len, scat_req->scat_entries);
662 if (request & HIF_SYNCHRONOUS)
663 status = ath6kl_sdio_scat_rw(ar_sdio, scat_req->busrequest);
665 spin_lock_bh(&ar_sdio->wr_async_lock);
666 list_add_tail(&scat_req->busrequest->list, &ar_sdio->wr_asyncq);
667 spin_unlock_bh(&ar_sdio->wr_async_lock);
668 queue_work(ar->ath6kl_wq, &ar_sdio->wr_async_work);
674 /* clean up scatter support */
675 static void ath6kl_sdio_cleanup_scatter(struct ath6kl *ar)
677 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
678 struct hif_scatter_req *s_req, *tmp_req;
680 /* empty the free list */
681 spin_lock_bh(&ar_sdio->scat_lock);
682 list_for_each_entry_safe(s_req, tmp_req, &ar_sdio->scat_req, list) {
683 list_del(&s_req->list);
684 spin_unlock_bh(&ar_sdio->scat_lock);
687 * FIXME: should we also call completion handler with
688 * ath6kl_hif_rw_comp_handler() with status -ECANCELED so
689 * that the packet is properly freed?
691 if (s_req->busrequest)
692 ath6kl_sdio_free_bus_req(ar_sdio, s_req->busrequest);
693 kfree(s_req->virt_dma_buf);
694 kfree(s_req->sgentries);
697 spin_lock_bh(&ar_sdio->scat_lock);
699 spin_unlock_bh(&ar_sdio->scat_lock);
702 /* setup of HIF scatter resources */
703 static int ath6kl_sdio_enable_scatter(struct ath6kl *ar)
705 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
706 struct htc_target *target = ar->htc_target;
708 bool virt_scat = false;
710 if (ar_sdio->scatter_enabled)
713 ar_sdio->scatter_enabled = true;
715 /* check if host supports scatter and it meets our requirements */
716 if (ar_sdio->func->card->host->max_segs < MAX_SCATTER_ENTRIES_PER_REQ) {
717 ath6kl_err("host only supports scatter of :%d entries, need: %d\n",
718 ar_sdio->func->card->host->max_segs,
719 MAX_SCATTER_ENTRIES_PER_REQ);
724 ret = ath6kl_sdio_alloc_prep_scat_req(ar_sdio,
725 MAX_SCATTER_ENTRIES_PER_REQ,
726 MAX_SCATTER_REQUESTS, virt_scat);
729 ath6kl_dbg(ATH6KL_DBG_BOOT,
730 "hif-scatter enabled requests %d entries %d\n",
731 MAX_SCATTER_REQUESTS,
732 MAX_SCATTER_ENTRIES_PER_REQ);
734 target->max_scat_entries = MAX_SCATTER_ENTRIES_PER_REQ;
735 target->max_xfer_szper_scatreq =
736 MAX_SCATTER_REQ_TRANSFER_SIZE;
738 ath6kl_sdio_cleanup_scatter(ar);
739 ath6kl_warn("hif scatter resource setup failed, trying virtual scatter method\n");
743 if (virt_scat || ret) {
744 ret = ath6kl_sdio_alloc_prep_scat_req(ar_sdio,
745 ATH6KL_SCATTER_ENTRIES_PER_REQ,
746 ATH6KL_SCATTER_REQS, virt_scat);
749 ath6kl_err("failed to alloc virtual scatter resources !\n");
750 ath6kl_sdio_cleanup_scatter(ar);
754 ath6kl_dbg(ATH6KL_DBG_BOOT,
755 "virtual scatter enabled requests %d entries %d\n",
756 ATH6KL_SCATTER_REQS, ATH6KL_SCATTER_ENTRIES_PER_REQ);
758 target->max_scat_entries = ATH6KL_SCATTER_ENTRIES_PER_REQ;
759 target->max_xfer_szper_scatreq =
760 ATH6KL_MAX_TRANSFER_SIZE_PER_SCATTER;
766 static int ath6kl_sdio_config(struct ath6kl *ar)
768 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
769 struct sdio_func *func = ar_sdio->func;
772 sdio_claim_host(func);
774 if ((ar_sdio->id->device & MANUFACTURER_ID_ATH6KL_BASE_MASK) >=
775 MANUFACTURER_ID_AR6003_BASE) {
776 /* enable 4-bit ASYNC interrupt on AR6003 or later */
777 ret = ath6kl_sdio_func0_cmd52_wr_byte(func->card,
778 CCCR_SDIO_IRQ_MODE_REG,
779 SDIO_IRQ_MODE_ASYNC_4BIT_IRQ);
781 ath6kl_err("Failed to enable 4-bit async irq mode %d\n",
786 ath6kl_dbg(ATH6KL_DBG_BOOT, "4-bit async irq mode enabled\n");
789 /* give us some time to enable, in ms */
790 func->enable_timeout = 100;
792 ret = sdio_set_block_size(func, HIF_MBOX_BLOCK_SIZE);
794 ath6kl_err("Set sdio block size %d failed: %d)\n",
795 HIF_MBOX_BLOCK_SIZE, ret);
800 sdio_release_host(func);
805 static int ath6kl_set_sdio_pm_caps(struct ath6kl *ar)
807 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
808 struct sdio_func *func = ar_sdio->func;
812 flags = sdio_get_host_pm_caps(func);
814 ath6kl_dbg(ATH6KL_DBG_SUSPEND, "sdio suspend pm_caps 0x%x\n", flags);
816 if (!(flags & MMC_PM_WAKE_SDIO_IRQ) ||
817 !(flags & MMC_PM_KEEP_POWER))
820 ret = sdio_set_host_pm_flags(func, MMC_PM_KEEP_POWER);
822 ath6kl_err("set sdio keep pwr flag failed: %d\n", ret);
826 /* sdio irq wakes up host */
827 ret = sdio_set_host_pm_flags(func, MMC_PM_WAKE_SDIO_IRQ);
829 ath6kl_err("set sdio wake irq flag failed: %d\n", ret);
834 static int ath6kl_sdio_suspend(struct ath6kl *ar, struct cfg80211_wowlan *wow)
836 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
837 struct sdio_func *func = ar_sdio->func;
839 bool try_deepsleep = false;
842 if (ar->state == ATH6KL_STATE_SCHED_SCAN) {
843 ath6kl_dbg(ATH6KL_DBG_SUSPEND, "sched scan is in progress\n");
845 ret = ath6kl_set_sdio_pm_caps(ar);
849 ret = ath6kl_cfg80211_suspend(ar,
850 ATH6KL_CFG_SUSPEND_SCHED_SCAN,
858 if (ar->suspend_mode == WLAN_POWER_STATE_WOW ||
859 (!ar->suspend_mode && wow)) {
861 ret = ath6kl_set_sdio_pm_caps(ar);
865 ret = ath6kl_cfg80211_suspend(ar, ATH6KL_CFG_SUSPEND_WOW, wow);
866 if (ret && ret != -ENOTCONN)
867 ath6kl_err("wow suspend failed: %d\n", ret);
869 if (ret && (!ar->wow_suspend_mode ||
870 ar->wow_suspend_mode == WLAN_POWER_STATE_DEEP_SLEEP))
871 try_deepsleep = true;
873 ar->wow_suspend_mode == WLAN_POWER_STATE_CUT_PWR)
879 if (ar->suspend_mode == WLAN_POWER_STATE_DEEP_SLEEP ||
880 !ar->suspend_mode || try_deepsleep) {
882 flags = sdio_get_host_pm_caps(func);
883 if (!(flags & MMC_PM_KEEP_POWER))
886 ret = sdio_set_host_pm_flags(func, MMC_PM_KEEP_POWER);
891 * Workaround to support Deep Sleep with MSM, set the host pm
892 * flag as MMC_PM_WAKE_SDIO_IRQ to allow SDCC deiver to disable
893 * the sdc2_clock and internally allows MSM to enter
894 * TCXO shutdown properly.
896 if ((flags & MMC_PM_WAKE_SDIO_IRQ)) {
897 ret = sdio_set_host_pm_flags(func,
898 MMC_PM_WAKE_SDIO_IRQ);
903 ret = ath6kl_cfg80211_suspend(ar, ATH6KL_CFG_SUSPEND_DEEPSLEEP,
912 return ath6kl_cfg80211_suspend(ar, ATH6KL_CFG_SUSPEND_CUTPOWER, NULL);
915 static int ath6kl_sdio_resume(struct ath6kl *ar)
918 case ATH6KL_STATE_OFF:
919 case ATH6KL_STATE_CUTPOWER:
920 ath6kl_dbg(ATH6KL_DBG_SUSPEND,
921 "sdio resume configuring sdio\n");
923 /* need to set sdio settings after power is cut from sdio */
924 ath6kl_sdio_config(ar);
927 case ATH6KL_STATE_ON:
930 case ATH6KL_STATE_DEEPSLEEP:
933 case ATH6KL_STATE_WOW:
936 case ATH6KL_STATE_SCHED_SCAN:
939 case ATH6KL_STATE_SUSPENDING:
942 case ATH6KL_STATE_RESUMING:
946 ath6kl_cfg80211_resume(ar);
951 /* set the window address register (using 4-byte register access ). */
952 static int ath6kl_set_addrwin_reg(struct ath6kl *ar, u32 reg_addr, u32 addr)
959 * Write bytes 1,2,3 of the register to set the upper address bytes,
960 * the LSB is written last to initiate the access cycle
963 for (i = 1; i <= 3; i++) {
965 * Fill the buffer with the address byte value we want to
968 memset(addr_val, ((u8 *)&addr)[i], 4);
971 * Hit each byte of the register address with a 4-byte
972 * write operation to the same address, this is a harmless
975 status = ath6kl_sdio_read_write_sync(ar, reg_addr + i, addr_val,
976 4, HIF_WR_SYNC_BYTE_FIX);
982 ath6kl_err("%s: failed to write initial bytes of 0x%x "
983 "to window reg: 0x%X\n", __func__,
989 * Write the address register again, this time write the whole
990 * 4-byte value. The effect here is that the LSB write causes the
991 * cycle to start, the extra 3 byte write to bytes 1,2,3 has no
992 * effect since we are writing the same values again
994 status = ath6kl_sdio_read_write_sync(ar, reg_addr, (u8 *)(&addr),
995 4, HIF_WR_SYNC_BYTE_INC);
998 ath6kl_err("%s: failed to write 0x%x to window reg: 0x%X\n",
999 __func__, addr, reg_addr);
1006 static int ath6kl_sdio_diag_read32(struct ath6kl *ar, u32 address, u32 *data)
1010 /* set window register to start read cycle */
1011 status = ath6kl_set_addrwin_reg(ar, WINDOW_READ_ADDR_ADDRESS,
1018 status = ath6kl_sdio_read_write_sync(ar, WINDOW_DATA_ADDRESS,
1019 (u8 *)data, sizeof(u32), HIF_RD_SYNC_BYTE_INC);
1021 ath6kl_err("%s: failed to read from window data addr\n",
1029 static int ath6kl_sdio_diag_write32(struct ath6kl *ar, u32 address,
1033 u32 val = (__force u32) data;
1035 /* set write data */
1036 status = ath6kl_sdio_read_write_sync(ar, WINDOW_DATA_ADDRESS,
1037 (u8 *) &val, sizeof(u32), HIF_WR_SYNC_BYTE_INC);
1039 ath6kl_err("%s: failed to write 0x%x to window data addr\n",
1044 /* set window register, which starts the write cycle */
1045 return ath6kl_set_addrwin_reg(ar, WINDOW_WRITE_ADDR_ADDRESS,
1049 static int ath6kl_sdio_bmi_credits(struct ath6kl *ar)
1052 unsigned long timeout;
1055 ar->bmi.cmd_credits = 0;
1057 /* Read the counter register to get the command credits */
1058 addr = COUNT_DEC_ADDRESS + (HTC_MAILBOX_NUM_MAX + ENDPOINT1) * 4;
1060 timeout = jiffies + msecs_to_jiffies(BMI_COMMUNICATION_TIMEOUT);
1061 while (time_before(jiffies, timeout) && !ar->bmi.cmd_credits) {
1064 * Hit the credit counter with a 4-byte access, the first byte
1065 * read will hit the counter and cause a decrement, while the
1066 * remaining 3 bytes has no effect. The rationale behind this
1067 * is to make all HIF accesses 4-byte aligned.
1069 ret = ath6kl_sdio_read_write_sync(ar, addr,
1070 (u8 *)&ar->bmi.cmd_credits, 4,
1071 HIF_RD_SYNC_BYTE_INC);
1073 ath6kl_err("Unable to decrement the command credit "
1074 "count register: %d\n", ret);
1078 /* The counter is only 8 bits.
1079 * Ignore anything in the upper 3 bytes
1081 ar->bmi.cmd_credits &= 0xFF;
1084 if (!ar->bmi.cmd_credits) {
1085 ath6kl_err("bmi communication timeout\n");
1092 static int ath6kl_bmi_get_rx_lkahd(struct ath6kl *ar)
1094 unsigned long timeout;
1098 timeout = jiffies + msecs_to_jiffies(BMI_COMMUNICATION_TIMEOUT);
1099 while ((time_before(jiffies, timeout)) && !rx_word) {
1100 ret = ath6kl_sdio_read_write_sync(ar,
1101 RX_LOOKAHEAD_VALID_ADDRESS,
1102 (u8 *)&rx_word, sizeof(rx_word),
1103 HIF_RD_SYNC_BYTE_INC);
1105 ath6kl_err("unable to read RX_LOOKAHEAD_VALID\n");
1109 /* all we really want is one bit */
1110 rx_word &= (1 << ENDPOINT1);
1114 ath6kl_err("bmi_recv_buf FIFO empty\n");
1121 static int ath6kl_sdio_bmi_write(struct ath6kl *ar, u8 *buf, u32 len)
1126 ret = ath6kl_sdio_bmi_credits(ar);
1130 addr = ar->mbox_info.htc_addr;
1132 ret = ath6kl_sdio_read_write_sync(ar, addr, buf, len,
1133 HIF_WR_SYNC_BYTE_INC);
1135 ath6kl_err("unable to send the bmi data to the device\n");
1140 static int ath6kl_sdio_bmi_read(struct ath6kl *ar, u8 *buf, u32 len)
1146 * During normal bootup, small reads may be required.
1147 * Rather than issue an HIF Read and then wait as the Target
1148 * adds successive bytes to the FIFO, we wait here until
1149 * we know that response data is available.
1151 * This allows us to cleanly timeout on an unexpected
1152 * Target failure rather than risk problems at the HIF level.
1153 * In particular, this avoids SDIO timeouts and possibly garbage
1154 * data on some host controllers. And on an interconnect
1155 * such as Compact Flash (as well as some SDIO masters) which
1156 * does not provide any indication on data timeout, it avoids
1157 * a potential hang or garbage response.
1159 * Synchronization is more difficult for reads larger than the
1160 * size of the MBOX FIFO (128B), because the Target is unable
1161 * to push the 129th byte of data until AFTER the Host posts an
1162 * HIF Read and removes some FIFO data. So for large reads the
1163 * Host proceeds to post an HIF Read BEFORE all the data is
1164 * actually available to read. Fortunately, large BMI reads do
1165 * not occur in practice -- they're supported for debug/development.
1167 * So Host/Target BMI synchronization is divided into these cases:
1168 * CASE 1: length < 4
1171 * CASE 2: 4 <= length <= 128
1172 * Wait for first 4 bytes to be in FIFO
1173 * If CONSERVATIVE_BMI_READ is enabled, also wait for
1174 * a BMI command credit, which indicates that the ENTIRE
1175 * response is available in the the FIFO
1177 * CASE 3: length > 128
1178 * Wait for the first 4 bytes to be in FIFO
1180 * For most uses, a small timeout should be sufficient and we will
1181 * usually see a response quickly; but there may be some unusual
1182 * (debug) cases of BMI_EXECUTE where we want an larger timeout.
1183 * For now, we use an unbounded busy loop while waiting for
1186 * If BMI_EXECUTE ever needs to support longer-latency execution,
1187 * especially in production, this code needs to be enhanced to sleep
1188 * and yield. Also note that BMI_COMMUNICATION_TIMEOUT is currently
1189 * a function of Host processor speed.
1191 if (len >= 4) { /* NB: Currently, always true */
1192 ret = ath6kl_bmi_get_rx_lkahd(ar);
1197 addr = ar->mbox_info.htc_addr;
1198 ret = ath6kl_sdio_read_write_sync(ar, addr, buf, len,
1199 HIF_RD_SYNC_BYTE_INC);
1201 ath6kl_err("Unable to read the bmi data from the device: %d\n",
1209 static void ath6kl_sdio_stop(struct ath6kl *ar)
1211 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
1212 struct bus_request *req, *tmp_req;
1215 /* FIXME: make sure that wq is not queued again */
1217 cancel_work_sync(&ar_sdio->wr_async_work);
1219 spin_lock_bh(&ar_sdio->wr_async_lock);
1221 list_for_each_entry_safe(req, tmp_req, &ar_sdio->wr_asyncq, list) {
1222 list_del(&req->list);
1224 if (req->scat_req) {
1225 /* this is a scatter gather request */
1226 req->scat_req->status = -ECANCELED;
1227 req->scat_req->complete(ar_sdio->ar->htc_target,
1230 context = req->packet;
1231 ath6kl_sdio_free_bus_req(ar_sdio, req);
1232 ath6kl_hif_rw_comp_handler(context, -ECANCELED);
1236 spin_unlock_bh(&ar_sdio->wr_async_lock);
1238 WARN_ON(get_queue_depth(&ar_sdio->scat_req) != 4);
1241 static const struct ath6kl_hif_ops ath6kl_sdio_ops = {
1242 .read_write_sync = ath6kl_sdio_read_write_sync,
1243 .write_async = ath6kl_sdio_write_async,
1244 .irq_enable = ath6kl_sdio_irq_enable,
1245 .irq_disable = ath6kl_sdio_irq_disable,
1246 .scatter_req_get = ath6kl_sdio_scatter_req_get,
1247 .scatter_req_add = ath6kl_sdio_scatter_req_add,
1248 .enable_scatter = ath6kl_sdio_enable_scatter,
1249 .scat_req_rw = ath6kl_sdio_async_rw_scatter,
1250 .cleanup_scatter = ath6kl_sdio_cleanup_scatter,
1251 .suspend = ath6kl_sdio_suspend,
1252 .resume = ath6kl_sdio_resume,
1253 .diag_read32 = ath6kl_sdio_diag_read32,
1254 .diag_write32 = ath6kl_sdio_diag_write32,
1255 .bmi_read = ath6kl_sdio_bmi_read,
1256 .bmi_write = ath6kl_sdio_bmi_write,
1257 .power_on = ath6kl_sdio_power_on,
1258 .power_off = ath6kl_sdio_power_off,
1259 .stop = ath6kl_sdio_stop,
1262 #ifdef CONFIG_PM_SLEEP
1265 * Empty handlers so that mmc subsystem doesn't remove us entirely during
1266 * suspend. We instead follow cfg80211 suspend/resume handlers.
1268 static int ath6kl_sdio_pm_suspend(struct device *device)
1270 ath6kl_dbg(ATH6KL_DBG_SUSPEND, "sdio pm suspend\n");
1275 static int ath6kl_sdio_pm_resume(struct device *device)
1277 ath6kl_dbg(ATH6KL_DBG_SUSPEND, "sdio pm resume\n");
1282 static SIMPLE_DEV_PM_OPS(ath6kl_sdio_pm_ops, ath6kl_sdio_pm_suspend,
1283 ath6kl_sdio_pm_resume);
1285 #define ATH6KL_SDIO_PM_OPS (&ath6kl_sdio_pm_ops)
1289 #define ATH6KL_SDIO_PM_OPS NULL
1291 #endif /* CONFIG_PM_SLEEP */
1293 static int ath6kl_sdio_probe(struct sdio_func *func,
1294 const struct sdio_device_id *id)
1297 struct ath6kl_sdio *ar_sdio;
1301 ath6kl_dbg(ATH6KL_DBG_BOOT,
1302 "sdio new func %d vendor 0x%x device 0x%x block 0x%x/0x%x\n",
1303 func->num, func->vendor, func->device,
1304 func->max_blksize, func->cur_blksize);
1306 ar_sdio = kzalloc(sizeof(struct ath6kl_sdio), GFP_KERNEL);
1310 ar_sdio->dma_buffer = kzalloc(HIF_DMA_BUFFER_SIZE, GFP_KERNEL);
1311 if (!ar_sdio->dma_buffer) {
1316 ar_sdio->func = func;
1317 sdio_set_drvdata(func, ar_sdio);
1320 ar_sdio->is_disabled = true;
1322 spin_lock_init(&ar_sdio->lock);
1323 spin_lock_init(&ar_sdio->scat_lock);
1324 spin_lock_init(&ar_sdio->wr_async_lock);
1325 mutex_init(&ar_sdio->dma_buffer_mutex);
1327 INIT_LIST_HEAD(&ar_sdio->scat_req);
1328 INIT_LIST_HEAD(&ar_sdio->bus_req_freeq);
1329 INIT_LIST_HEAD(&ar_sdio->wr_asyncq);
1331 INIT_WORK(&ar_sdio->wr_async_work, ath6kl_sdio_write_async_work);
1333 init_waitqueue_head(&ar_sdio->irq_wq);
1335 for (count = 0; count < BUS_REQUEST_MAX_NUM; count++)
1336 ath6kl_sdio_free_bus_req(ar_sdio, &ar_sdio->bus_req[count]);
1338 ar = ath6kl_core_create(&ar_sdio->func->dev);
1340 ath6kl_err("Failed to alloc ath6kl core\n");
1346 ar->hif_type = ATH6KL_HIF_TYPE_SDIO;
1347 ar->hif_priv = ar_sdio;
1348 ar->hif_ops = &ath6kl_sdio_ops;
1349 ar->bmi.max_data_size = 256;
1351 ath6kl_sdio_set_mbox_info(ar);
1353 ret = ath6kl_sdio_config(ar);
1355 ath6kl_err("Failed to config sdio: %d\n", ret);
1356 goto err_core_alloc;
1359 ret = ath6kl_core_init(ar);
1361 ath6kl_err("Failed to init ath6kl core\n");
1362 goto err_core_alloc;
1368 ath6kl_core_destroy(ar_sdio->ar);
1370 kfree(ar_sdio->dma_buffer);
1377 static void ath6kl_sdio_remove(struct sdio_func *func)
1379 struct ath6kl_sdio *ar_sdio;
1381 ath6kl_dbg(ATH6KL_DBG_BOOT,
1382 "sdio removed func %d vendor 0x%x device 0x%x\n",
1383 func->num, func->vendor, func->device);
1385 ar_sdio = sdio_get_drvdata(func);
1387 ath6kl_stop_txrx(ar_sdio->ar);
1388 cancel_work_sync(&ar_sdio->wr_async_work);
1390 ath6kl_core_cleanup(ar_sdio->ar);
1391 ath6kl_core_destroy(ar_sdio->ar);
1393 kfree(ar_sdio->dma_buffer);
1397 static const struct sdio_device_id ath6kl_sdio_devices[] = {
1398 {SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6003_BASE | 0x0))},
1399 {SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6003_BASE | 0x1))},
1400 {SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6004_BASE | 0x0))},
1401 {SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6004_BASE | 0x1))},
1405 MODULE_DEVICE_TABLE(sdio, ath6kl_sdio_devices);
1407 static struct sdio_driver ath6kl_sdio_driver = {
1408 .name = "ath6kl_sdio",
1409 .id_table = ath6kl_sdio_devices,
1410 .probe = ath6kl_sdio_probe,
1411 .remove = ath6kl_sdio_remove,
1412 .drv.pm = ATH6KL_SDIO_PM_OPS,
1415 static int __init ath6kl_sdio_init(void)
1419 ret = sdio_register_driver(&ath6kl_sdio_driver);
1421 ath6kl_err("sdio driver registration failed: %d\n", ret);
1426 static void __exit ath6kl_sdio_exit(void)
1428 sdio_unregister_driver(&ath6kl_sdio_driver);
1431 module_init(ath6kl_sdio_init);
1432 module_exit(ath6kl_sdio_exit);
1434 MODULE_AUTHOR("Atheros Communications, Inc.");
1435 MODULE_DESCRIPTION("Driver support for Atheros AR600x SDIO devices");
1436 MODULE_LICENSE("Dual BSD/GPL");
1438 MODULE_FIRMWARE(AR6003_HW_2_0_FW_DIR "/" AR6003_HW_2_0_OTP_FILE);
1439 MODULE_FIRMWARE(AR6003_HW_2_0_FW_DIR "/" AR6003_HW_2_0_FIRMWARE_FILE);
1440 MODULE_FIRMWARE(AR6003_HW_2_0_FW_DIR "/" AR6003_HW_2_0_PATCH_FILE);
1441 MODULE_FIRMWARE(AR6003_HW_2_0_BOARD_DATA_FILE);
1442 MODULE_FIRMWARE(AR6003_HW_2_0_DEFAULT_BOARD_DATA_FILE);
1443 MODULE_FIRMWARE(AR6003_HW_2_1_1_FW_DIR "/" AR6003_HW_2_1_1_OTP_FILE);
1444 MODULE_FIRMWARE(AR6003_HW_2_1_1_FW_DIR "/" AR6003_HW_2_1_1_FIRMWARE_FILE);
1445 MODULE_FIRMWARE(AR6003_HW_2_1_1_FW_DIR "/" AR6003_HW_2_1_1_PATCH_FILE);
1446 MODULE_FIRMWARE(AR6003_HW_2_1_1_BOARD_DATA_FILE);
1447 MODULE_FIRMWARE(AR6003_HW_2_1_1_DEFAULT_BOARD_DATA_FILE);
1448 MODULE_FIRMWARE(AR6004_HW_1_0_FW_DIR "/" AR6004_HW_1_0_FIRMWARE_FILE);
1449 MODULE_FIRMWARE(AR6004_HW_1_0_BOARD_DATA_FILE);
1450 MODULE_FIRMWARE(AR6004_HW_1_0_DEFAULT_BOARD_DATA_FILE);
1451 MODULE_FIRMWARE(AR6004_HW_1_1_FW_DIR "/" AR6004_HW_1_1_FIRMWARE_FILE);
1452 MODULE_FIRMWARE(AR6004_HW_1_1_BOARD_DATA_FILE);
1453 MODULE_FIRMWARE(AR6004_HW_1_1_DEFAULT_BOARD_DATA_FILE);