2 * Copyright (c) 2010-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <asm/unaligned.h>
19 #include "ar9003_phy.h"
20 #include "ar9003_eeprom.h"
22 #define COMP_HDR_LEN 4
23 #define COMP_CKSUM_LEN 2
25 #define LE16(x) __constant_cpu_to_le16(x)
26 #define LE32(x) __constant_cpu_to_le32(x)
28 /* Local defines to distinguish between extension and control CTL's */
29 #define EXT_ADDITIVE (0x8000)
30 #define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE)
31 #define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE)
32 #define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE)
34 #define SUB_NUM_CTL_MODES_AT_5G_40 2 /* excluding HT40, EXT-OFDM */
35 #define SUB_NUM_CTL_MODES_AT_2G_40 3 /* excluding HT40, EXT-OFDM, EXT-CCK */
37 #define CTL(_tpower, _flag) ((_tpower) | ((_flag) << 6))
39 #define EEPROM_DATA_LEN_9485 1088
41 static int ar9003_hw_power_interpolate(int32_t x,
42 int32_t *px, int32_t *py, u_int16_t np);
45 static const struct ar9300_eeprom ar9300_default = {
48 .macAddr = {0, 2, 3, 4, 5, 6},
49 .custData = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
50 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
52 .regDmn = { LE16(0), LE16(0x1f) },
53 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
55 .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
59 .blueToothOptions = 0,
61 .deviceType = 5, /* takes lower byte in eeprom location */
62 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
63 .params_for_tuning_caps = {0, 0},
64 .featureEnable = 0x0c,
66 * bit0 - enable tx temp comp - disabled
67 * bit1 - enable tx volt comp - disabled
68 * bit2 - enable fastClock - enabled
69 * bit3 - enable doubling - enabled
70 * bit4 - enable internal regulator - disabled
71 * bit5 - enable pa predistortion - disabled
73 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
74 .eepromWriteEnableGpio = 3,
77 .rxBandSelectGpio = 0xff,
82 /* ar9300_modal_eep_header 2g */
83 /* 4 idle,t1,t2,b(4 bits per setting) */
84 .antCtrlCommon = LE32(0x110),
85 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
86 .antCtrlCommon2 = LE32(0x22222),
89 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
90 * rx1, rx12, b (2 bits each)
92 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
95 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
96 * for ar9280 (0xa20c/b20c 5:0)
98 .xatten1DB = {0, 0, 0},
101 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
102 * for ar9280 (0xa20c/b20c 16:12
104 .xatten1Margin = {0, 0, 0},
109 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
110 * channels in usual fbin coding format
112 .spurChans = {0, 0, 0, 0, 0},
115 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
116 * if the register is per chain
118 .noiseFloorThreshCh = {-1, 0, 0},
119 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
122 .txFrameToDataStart = 0x0e,
123 .txFrameToPaOn = 0x0e,
124 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
126 .switchSettling = 0x2c,
127 .adcDesiredSize = -30,
130 .txFrameToXpaOn = 0xe,
132 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
133 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
135 0, 0, 0, 0, 0, 0, 0, 0,
139 .ant_div_control = 0,
140 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
147 /* ar9300_cal_data_per_freq_op_loop 2g */
149 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
150 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
151 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
153 .calTarget_freqbin_Cck = {
157 .calTarget_freqbin_2G = {
162 .calTarget_freqbin_2GHT20 = {
167 .calTarget_freqbin_2GHT40 = {
172 .calTargetPowerCck = {
173 /* 1L-5L,5S,11L,11S */
174 { {36, 36, 36, 36} },
175 { {36, 36, 36, 36} },
177 .calTargetPower2G = {
179 { {32, 32, 28, 24} },
180 { {32, 32, 28, 24} },
181 { {32, 32, 28, 24} },
183 .calTargetPower2GHT20 = {
184 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
185 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
186 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
188 .calTargetPower2GHT40 = {
189 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
190 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
191 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
194 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
195 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
225 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
226 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
227 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
228 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
232 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
233 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
234 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
239 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
240 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
246 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
247 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
248 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
249 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
253 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
254 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
255 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
259 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
260 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
261 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
266 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
267 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
268 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
273 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
274 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
275 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
276 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
280 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
281 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
282 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
284 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
285 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
286 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
288 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
289 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
290 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
292 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
293 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
294 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
297 /* 4 idle,t1,t2,b (4 bits per setting) */
298 .antCtrlCommon = LE32(0x110),
299 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
300 .antCtrlCommon2 = LE32(0x22222),
301 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
303 LE16(0x000), LE16(0x000), LE16(0x000),
305 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
306 .xatten1DB = {0, 0, 0},
309 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
310 * for merlin (0xa20c/b20c 16:12
312 .xatten1Margin = {0, 0, 0},
315 /* spurChans spur channels in usual fbin coding format */
316 .spurChans = {0, 0, 0, 0, 0},
317 /* noiseFloorThreshCh Check if the register is per chain */
318 .noiseFloorThreshCh = {-1, 0, 0},
319 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
322 .txFrameToDataStart = 0x0e,
323 .txFrameToPaOn = 0x0e,
324 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
326 .switchSettling = 0x2d,
327 .adcDesiredSize = -30,
330 .txFrameToXpaOn = 0xe,
332 .papdRateMaskHt20 = LE32(0x0c80c080),
333 .papdRateMaskHt40 = LE32(0x0080c080),
335 0, 0, 0, 0, 0, 0, 0, 0,
341 .xatten1DBLow = {0, 0, 0},
342 .xatten1MarginLow = {0, 0, 0},
343 .xatten1DBHigh = {0, 0, 0},
344 .xatten1MarginHigh = {0, 0, 0}
389 .calTarget_freqbin_5G = {
399 .calTarget_freqbin_5GHT20 = {
409 .calTarget_freqbin_5GHT40 = {
419 .calTargetPower5G = {
421 { {20, 20, 20, 10} },
422 { {20, 20, 20, 10} },
423 { {20, 20, 20, 10} },
424 { {20, 20, 20, 10} },
425 { {20, 20, 20, 10} },
426 { {20, 20, 20, 10} },
427 { {20, 20, 20, 10} },
428 { {20, 20, 20, 10} },
430 .calTargetPower5GHT20 = {
432 * 0_8_16,1-3_9-11_17-19,
433 * 4,5,6,7,12,13,14,15,20,21,22,23
435 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
436 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
437 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
438 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
439 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
440 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
441 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
442 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
444 .calTargetPower5GHT40 = {
446 * 0_8_16,1-3_9-11_17-19,
447 * 4,5,6,7,12,13,14,15,20,21,22,23
449 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
450 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
451 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
452 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
453 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
454 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
455 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
456 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
459 0x10, 0x16, 0x18, 0x40, 0x46,
460 0x48, 0x30, 0x36, 0x38
464 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
465 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
466 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
467 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
468 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
469 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
470 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
471 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
474 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
475 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
476 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
477 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
478 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
479 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
480 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
481 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
485 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
486 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
487 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
488 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
489 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
490 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
491 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
492 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
496 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
497 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
498 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
499 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
500 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
501 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
502 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
503 /* Data[3].ctlEdges[7].bChannel */ 0xFF,
507 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
508 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
509 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
510 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
511 /* Data[4].ctlEdges[4].bChannel */ 0xFF,
512 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
513 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
514 /* Data[4].ctlEdges[7].bChannel */ 0xFF,
518 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
519 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
520 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
521 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
522 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
523 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
524 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
525 /* Data[5].ctlEdges[7].bChannel */ 0xFF
529 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
530 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
531 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
532 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
533 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
534 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
535 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
536 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
540 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
541 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
542 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
543 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
544 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
545 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
546 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
547 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
551 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
552 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
553 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
554 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
555 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
556 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
557 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
558 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
564 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
565 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
570 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
571 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
576 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
577 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
582 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
583 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
588 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
589 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
594 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
595 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
600 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
601 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
606 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
607 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
612 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
613 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
619 static const struct ar9300_eeprom ar9300_x113 = {
621 .templateVersion = 6,
622 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
623 .custData = {"x113-023-f0000"},
625 .regDmn = { LE16(0), LE16(0x1f) },
626 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
628 .opFlags = AR5416_OPFLAGS_11A,
632 .blueToothOptions = 0,
634 .deviceType = 5, /* takes lower byte in eeprom location */
635 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
636 .params_for_tuning_caps = {0, 0},
637 .featureEnable = 0x0d,
639 * bit0 - enable tx temp comp - disabled
640 * bit1 - enable tx volt comp - disabled
641 * bit2 - enable fastClock - enabled
642 * bit3 - enable doubling - enabled
643 * bit4 - enable internal regulator - disabled
644 * bit5 - enable pa predistortion - disabled
646 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
647 .eepromWriteEnableGpio = 6,
648 .wlanDisableGpio = 0,
650 .rxBandSelectGpio = 0xff,
655 /* ar9300_modal_eep_header 2g */
656 /* 4 idle,t1,t2,b(4 bits per setting) */
657 .antCtrlCommon = LE32(0x110),
658 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
659 .antCtrlCommon2 = LE32(0x44444),
662 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
663 * rx1, rx12, b (2 bits each)
665 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
668 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
669 * for ar9280 (0xa20c/b20c 5:0)
671 .xatten1DB = {0, 0, 0},
674 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
675 * for ar9280 (0xa20c/b20c 16:12
677 .xatten1Margin = {0, 0, 0},
682 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
683 * channels in usual fbin coding format
685 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
688 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
689 * if the register is per chain
691 .noiseFloorThreshCh = {-1, 0, 0},
692 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
695 .txFrameToDataStart = 0x0e,
696 .txFrameToPaOn = 0x0e,
697 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
699 .switchSettling = 0x2c,
700 .adcDesiredSize = -30,
703 .txFrameToXpaOn = 0xe,
705 .papdRateMaskHt20 = LE32(0x0c80c080),
706 .papdRateMaskHt40 = LE32(0x0080c080),
708 0, 0, 0, 0, 0, 0, 0, 0,
712 .ant_div_control = 0,
713 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
720 /* ar9300_cal_data_per_freq_op_loop 2g */
722 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
723 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
724 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
726 .calTarget_freqbin_Cck = {
730 .calTarget_freqbin_2G = {
735 .calTarget_freqbin_2GHT20 = {
740 .calTarget_freqbin_2GHT40 = {
745 .calTargetPowerCck = {
746 /* 1L-5L,5S,11L,11S */
747 { {34, 34, 34, 34} },
748 { {34, 34, 34, 34} },
750 .calTargetPower2G = {
752 { {34, 34, 32, 32} },
753 { {34, 34, 32, 32} },
754 { {34, 34, 32, 32} },
756 .calTargetPower2GHT20 = {
757 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
758 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
759 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
761 .calTargetPower2GHT40 = {
762 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
763 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
764 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
767 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
768 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
798 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
799 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
800 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
801 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
805 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
806 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
807 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
812 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
813 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
819 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
820 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
821 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
822 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
826 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
827 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
828 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
832 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
833 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
834 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
839 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
840 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
841 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
846 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
847 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
848 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
849 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
853 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
854 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
855 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
857 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
858 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
859 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
861 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
862 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
863 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
865 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
866 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
867 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
870 /* 4 idle,t1,t2,b (4 bits per setting) */
871 .antCtrlCommon = LE32(0x220),
872 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
873 .antCtrlCommon2 = LE32(0x11111),
874 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
876 LE16(0x150), LE16(0x150), LE16(0x150),
878 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
879 .xatten1DB = {0, 0, 0},
882 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
883 * for merlin (0xa20c/b20c 16:12
885 .xatten1Margin = {0, 0, 0},
888 /* spurChans spur channels in usual fbin coding format */
889 .spurChans = {FREQ2FBIN(5500, 0), 0, 0, 0, 0},
890 /* noiseFloorThreshCh Check if the register is per chain */
891 .noiseFloorThreshCh = {-1, 0, 0},
892 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
895 .txFrameToDataStart = 0x0e,
896 .txFrameToPaOn = 0x0e,
897 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
899 .switchSettling = 0x2d,
900 .adcDesiredSize = -30,
903 .txFrameToXpaOn = 0xe,
905 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
906 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
908 0, 0, 0, 0, 0, 0, 0, 0,
913 .tempSlopeHigh = 105,
914 .xatten1DBLow = {0, 0, 0},
915 .xatten1MarginLow = {0, 0, 0},
916 .xatten1DBHigh = {0, 0, 0},
917 .xatten1MarginHigh = {0, 0, 0}
962 .calTarget_freqbin_5G = {
972 .calTarget_freqbin_5GHT20 = {
982 .calTarget_freqbin_5GHT40 = {
992 .calTargetPower5G = {
994 { {42, 40, 40, 34} },
995 { {42, 40, 40, 34} },
996 { {42, 40, 40, 34} },
997 { {42, 40, 40, 34} },
998 { {42, 40, 40, 34} },
999 { {42, 40, 40, 34} },
1000 { {42, 40, 40, 34} },
1001 { {42, 40, 40, 34} },
1003 .calTargetPower5GHT20 = {
1005 * 0_8_16,1-3_9-11_17-19,
1006 * 4,5,6,7,12,13,14,15,20,21,22,23
1008 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1009 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1010 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1011 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1012 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1013 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1014 { {38, 38, 38, 38, 32, 28, 38, 38, 32, 28, 38, 38, 32, 26} },
1015 { {36, 36, 36, 36, 32, 28, 36, 36, 32, 28, 36, 36, 32, 26} },
1017 .calTargetPower5GHT40 = {
1019 * 0_8_16,1-3_9-11_17-19,
1020 * 4,5,6,7,12,13,14,15,20,21,22,23
1022 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1023 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1024 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1025 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1026 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1027 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1028 { {36, 36, 36, 36, 30, 26, 36, 36, 30, 26, 36, 36, 30, 24} },
1029 { {34, 34, 34, 34, 30, 26, 34, 34, 30, 26, 34, 34, 30, 24} },
1032 0x10, 0x16, 0x18, 0x40, 0x46,
1033 0x48, 0x30, 0x36, 0x38
1037 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1038 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1039 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1040 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1041 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
1042 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1043 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1044 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1047 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1048 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1049 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1050 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1051 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
1052 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1053 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1054 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1058 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1059 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1060 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1061 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
1062 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
1063 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
1064 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
1065 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
1069 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1070 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1071 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
1072 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
1073 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1074 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1075 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
1076 /* Data[3].ctlEdges[7].bChannel */ 0xFF,
1080 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1081 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1082 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
1083 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
1084 /* Data[4].ctlEdges[4].bChannel */ 0xFF,
1085 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
1086 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
1087 /* Data[4].ctlEdges[7].bChannel */ 0xFF,
1091 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1092 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
1093 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
1094 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1095 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
1096 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1097 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
1098 /* Data[5].ctlEdges[7].bChannel */ 0xFF
1102 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1103 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1104 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
1105 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
1106 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1107 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
1108 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
1109 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
1113 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1114 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1115 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
1116 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1117 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
1118 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1119 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1120 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1124 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1125 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1126 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1127 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1128 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
1129 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1130 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
1131 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
1134 .ctlPowerData_5G = {
1137 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1138 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1143 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1144 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1149 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1150 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1155 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1156 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1161 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1162 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1167 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1168 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1173 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1174 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1179 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1180 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1185 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
1186 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1193 static const struct ar9300_eeprom ar9300_h112 = {
1195 .templateVersion = 3,
1196 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
1197 .custData = {"h112-241-f0000"},
1199 .regDmn = { LE16(0), LE16(0x1f) },
1200 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
1202 .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
1206 .blueToothOptions = 0,
1208 .deviceType = 5, /* takes lower byte in eeprom location */
1209 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
1210 .params_for_tuning_caps = {0, 0},
1211 .featureEnable = 0x0d,
1213 * bit0 - enable tx temp comp - disabled
1214 * bit1 - enable tx volt comp - disabled
1215 * bit2 - enable fastClock - enabled
1216 * bit3 - enable doubling - enabled
1217 * bit4 - enable internal regulator - disabled
1218 * bit5 - enable pa predistortion - disabled
1220 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
1221 .eepromWriteEnableGpio = 6,
1222 .wlanDisableGpio = 0,
1224 .rxBandSelectGpio = 0xff,
1229 /* ar9300_modal_eep_header 2g */
1230 /* 4 idle,t1,t2,b(4 bits per setting) */
1231 .antCtrlCommon = LE32(0x110),
1232 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
1233 .antCtrlCommon2 = LE32(0x44444),
1236 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
1237 * rx1, rx12, b (2 bits each)
1239 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
1242 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
1243 * for ar9280 (0xa20c/b20c 5:0)
1245 .xatten1DB = {0, 0, 0},
1248 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
1249 * for ar9280 (0xa20c/b20c 16:12
1251 .xatten1Margin = {0, 0, 0},
1256 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
1257 * channels in usual fbin coding format
1259 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
1262 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
1263 * if the register is per chain
1265 .noiseFloorThreshCh = {-1, 0, 0},
1266 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
1269 .txFrameToDataStart = 0x0e,
1270 .txFrameToPaOn = 0x0e,
1271 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1273 .switchSettling = 0x2c,
1274 .adcDesiredSize = -30,
1277 .txFrameToXpaOn = 0xe,
1279 .papdRateMaskHt20 = LE32(0x0c80c080),
1280 .papdRateMaskHt40 = LE32(0x0080c080),
1282 0, 0, 0, 0, 0, 0, 0, 0,
1286 .ant_div_control = 0,
1287 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
1294 /* ar9300_cal_data_per_freq_op_loop 2g */
1296 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1297 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1298 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1300 .calTarget_freqbin_Cck = {
1304 .calTarget_freqbin_2G = {
1309 .calTarget_freqbin_2GHT20 = {
1314 .calTarget_freqbin_2GHT40 = {
1319 .calTargetPowerCck = {
1320 /* 1L-5L,5S,11L,11S */
1321 { {34, 34, 34, 34} },
1322 { {34, 34, 34, 34} },
1324 .calTargetPower2G = {
1326 { {34, 34, 32, 32} },
1327 { {34, 34, 32, 32} },
1328 { {34, 34, 32, 32} },
1330 .calTargetPower2GHT20 = {
1331 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1332 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1333 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1335 .calTargetPower2GHT40 = {
1336 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1337 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1338 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1341 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
1342 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
1372 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1373 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1374 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1375 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
1379 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1380 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1381 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1386 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1387 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1393 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
1394 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
1395 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
1396 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
1400 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1401 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1402 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1406 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1407 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1408 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1413 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1414 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1415 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1420 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
1421 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
1422 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
1423 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
1426 .ctlPowerData_2G = {
1427 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1428 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1429 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
1431 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
1432 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1433 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1435 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
1436 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1437 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1439 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1440 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
1441 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
1444 /* 4 idle,t1,t2,b (4 bits per setting) */
1445 .antCtrlCommon = LE32(0x220),
1446 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
1447 .antCtrlCommon2 = LE32(0x44444),
1448 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
1450 LE16(0x150), LE16(0x150), LE16(0x150),
1452 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
1453 .xatten1DB = {0, 0, 0},
1456 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
1457 * for merlin (0xa20c/b20c 16:12
1459 .xatten1Margin = {0, 0, 0},
1462 /* spurChans spur channels in usual fbin coding format */
1463 .spurChans = {0, 0, 0, 0, 0},
1464 /* noiseFloorThreshCh Check if the register is per chain */
1465 .noiseFloorThreshCh = {-1, 0, 0},
1466 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
1469 .txFrameToDataStart = 0x0e,
1470 .txFrameToPaOn = 0x0e,
1471 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1473 .switchSettling = 0x2d,
1474 .adcDesiredSize = -30,
1477 .txFrameToXpaOn = 0xe,
1479 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
1480 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
1482 0, 0, 0, 0, 0, 0, 0, 0,
1487 .tempSlopeHigh = 50,
1488 .xatten1DBLow = {0, 0, 0},
1489 .xatten1MarginLow = {0, 0, 0},
1490 .xatten1DBHigh = {0, 0, 0},
1491 .xatten1MarginHigh = {0, 0, 0}
1536 .calTarget_freqbin_5G = {
1546 .calTarget_freqbin_5GHT20 = {
1556 .calTarget_freqbin_5GHT40 = {
1566 .calTargetPower5G = {
1568 { {30, 30, 28, 24} },
1569 { {30, 30, 28, 24} },
1570 { {30, 30, 28, 24} },
1571 { {30, 30, 28, 24} },
1572 { {30, 30, 28, 24} },
1573 { {30, 30, 28, 24} },
1574 { {30, 30, 28, 24} },
1575 { {30, 30, 28, 24} },
1577 .calTargetPower5GHT20 = {
1579 * 0_8_16,1-3_9-11_17-19,
1580 * 4,5,6,7,12,13,14,15,20,21,22,23
1582 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
1583 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
1584 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
1585 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
1586 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
1587 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
1588 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
1589 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
1591 .calTargetPower5GHT40 = {
1593 * 0_8_16,1-3_9-11_17-19,
1594 * 4,5,6,7,12,13,14,15,20,21,22,23
1596 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
1597 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
1598 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
1599 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
1600 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
1601 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
1602 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
1603 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
1606 0x10, 0x16, 0x18, 0x40, 0x46,
1607 0x48, 0x30, 0x36, 0x38
1611 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1612 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1613 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1614 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1615 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
1616 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1617 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1618 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1621 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1622 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1623 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1624 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1625 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
1626 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1627 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1628 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1632 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1633 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1634 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1635 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
1636 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
1637 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
1638 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
1639 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
1643 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1644 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1645 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
1646 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
1647 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1648 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1649 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
1650 /* Data[3].ctlEdges[7].bChannel */ 0xFF,
1654 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1655 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1656 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
1657 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
1658 /* Data[4].ctlEdges[4].bChannel */ 0xFF,
1659 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
1660 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
1661 /* Data[4].ctlEdges[7].bChannel */ 0xFF,
1665 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1666 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
1667 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
1668 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1669 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
1670 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1671 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
1672 /* Data[5].ctlEdges[7].bChannel */ 0xFF
1676 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1677 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1678 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
1679 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
1680 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1681 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
1682 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
1683 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
1687 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1688 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1689 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
1690 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1691 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
1692 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1693 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1694 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1698 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1699 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1700 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1701 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1702 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
1703 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1704 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
1705 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
1708 .ctlPowerData_5G = {
1711 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1712 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1717 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1718 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1723 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1724 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1729 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1730 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1735 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1736 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1741 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1742 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1747 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1748 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1753 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1754 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1759 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
1760 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1767 static const struct ar9300_eeprom ar9300_x112 = {
1769 .templateVersion = 5,
1770 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
1771 .custData = {"x112-041-f0000"},
1773 .regDmn = { LE16(0), LE16(0x1f) },
1774 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
1776 .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
1780 .blueToothOptions = 0,
1782 .deviceType = 5, /* takes lower byte in eeprom location */
1783 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
1784 .params_for_tuning_caps = {0, 0},
1785 .featureEnable = 0x0d,
1787 * bit0 - enable tx temp comp - disabled
1788 * bit1 - enable tx volt comp - disabled
1789 * bit2 - enable fastclock - enabled
1790 * bit3 - enable doubling - enabled
1791 * bit4 - enable internal regulator - disabled
1792 * bit5 - enable pa predistortion - disabled
1794 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
1795 .eepromWriteEnableGpio = 6,
1796 .wlanDisableGpio = 0,
1798 .rxBandSelectGpio = 0xff,
1803 /* ar9300_modal_eep_header 2g */
1804 /* 4 idle,t1,t2,b(4 bits per setting) */
1805 .antCtrlCommon = LE32(0x110),
1806 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
1807 .antCtrlCommon2 = LE32(0x22222),
1810 * antCtrlChain[ar9300_max_chains]; 6 idle, t, r,
1811 * rx1, rx12, b (2 bits each)
1813 .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) },
1816 * xatten1DB[AR9300_max_chains]; 3 xatten1_db
1817 * for ar9280 (0xa20c/b20c 5:0)
1819 .xatten1DB = {0x1b, 0x1b, 0x1b},
1822 * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin
1823 * for ar9280 (0xa20c/b20c 16:12
1825 .xatten1Margin = {0x15, 0x15, 0x15},
1830 * spurChans[OSPrey_eeprom_modal_sPURS]; spur
1831 * channels in usual fbin coding format
1833 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
1836 * noiseFloorThreshch[ar9300_max_cHAINS]; 3 Check
1837 * if the register is per chain
1839 .noiseFloorThreshCh = {-1, 0, 0},
1840 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
1843 .txFrameToDataStart = 0x0e,
1844 .txFrameToPaOn = 0x0e,
1845 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1847 .switchSettling = 0x2c,
1848 .adcDesiredSize = -30,
1851 .txFrameToXpaOn = 0xe,
1853 .papdRateMaskHt20 = LE32(0x0c80c080),
1854 .papdRateMaskHt40 = LE32(0x0080c080),
1856 0, 0, 0, 0, 0, 0, 0, 0,
1860 .ant_div_control = 0,
1861 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
1868 /* ar9300_cal_data_per_freq_op_loop 2g */
1870 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1871 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1872 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1874 .calTarget_freqbin_Cck = {
1878 .calTarget_freqbin_2G = {
1883 .calTarget_freqbin_2GHT20 = {
1888 .calTarget_freqbin_2GHT40 = {
1893 .calTargetPowerCck = {
1894 /* 1L-5L,5S,11L,11s */
1895 { {38, 38, 38, 38} },
1896 { {38, 38, 38, 38} },
1898 .calTargetPower2G = {
1900 { {38, 38, 36, 34} },
1901 { {38, 38, 36, 34} },
1902 { {38, 38, 34, 32} },
1904 .calTargetPower2GHT20 = {
1905 { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
1906 { {36, 36, 36, 36, 36, 34, 36, 34, 32, 30, 30, 30, 28, 26} },
1907 { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
1909 .calTargetPower2GHT40 = {
1910 { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
1911 { {36, 36, 36, 36, 34, 32, 34, 32, 30, 28, 28, 28, 28, 24} },
1912 { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
1915 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
1916 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
1946 /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1947 /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1948 /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1949 /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(2484, 1),
1953 /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1954 /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1955 /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1960 /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1961 /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1967 /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(2422, 1),
1968 /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(2427, 1),
1969 /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(2447, 1),
1970 /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(2462, 1),
1974 /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1975 /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1976 /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1980 /* Data[9].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1981 /* Data[9].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1982 /* Data[9].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1987 /* Data[10].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1988 /* Data[10].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1989 /* Data[10].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1994 /* Data[11].ctledges[0].bchannel */ FREQ2FBIN(2422, 1),
1995 /* Data[11].ctledges[1].bchannel */ FREQ2FBIN(2427, 1),
1996 /* Data[11].ctledges[2].bchannel */ FREQ2FBIN(2447, 1),
1997 /* Data[11].ctledges[3].bchannel */ FREQ2FBIN(2462, 1),
2000 .ctlPowerData_2G = {
2001 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2002 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2003 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
2005 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
2006 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2007 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2009 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
2010 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2011 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2013 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2014 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2015 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2018 /* 4 idle,t1,t2,b (4 bits per setting) */
2019 .antCtrlCommon = LE32(0x110),
2020 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
2021 .antCtrlCommon2 = LE32(0x22222),
2022 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
2024 LE16(0x0), LE16(0x0), LE16(0x0),
2026 /* xatten1DB 3 xatten1_db for ar9280 (0xa20c/b20c 5:0) */
2027 .xatten1DB = {0x13, 0x19, 0x17},
2030 * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin
2031 * for merlin (0xa20c/b20c 16:12
2033 .xatten1Margin = {0x19, 0x19, 0x19},
2036 /* spurChans spur channels in usual fbin coding format */
2037 .spurChans = {0, 0, 0, 0, 0},
2038 /* noiseFloorThreshch check if the register is per chain */
2039 .noiseFloorThreshCh = {-1, 0, 0},
2040 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
2043 .txFrameToDataStart = 0x0e,
2044 .txFrameToPaOn = 0x0e,
2045 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2047 .switchSettling = 0x2d,
2048 .adcDesiredSize = -30,
2051 .txFrameToXpaOn = 0xe,
2053 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
2054 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
2056 0, 0, 0, 0, 0, 0, 0, 0,
2061 .tempSlopeHigh = 105,
2062 .xatten1DBLow = {0x10, 0x14, 0x10},
2063 .xatten1MarginLow = {0x19, 0x19 , 0x19},
2064 .xatten1DBHigh = {0x1d, 0x20, 0x24},
2065 .xatten1MarginHigh = {0x10, 0x10, 0x10}
2110 .calTarget_freqbin_5G = {
2120 .calTarget_freqbin_5GHT20 = {
2130 .calTarget_freqbin_5GHT40 = {
2140 .calTargetPower5G = {
2142 { {32, 32, 28, 26} },
2143 { {32, 32, 28, 26} },
2144 { {32, 32, 28, 26} },
2145 { {32, 32, 26, 24} },
2146 { {32, 32, 26, 24} },
2147 { {32, 32, 24, 22} },
2148 { {30, 30, 24, 22} },
2149 { {30, 30, 24, 22} },
2151 .calTargetPower5GHT20 = {
2153 * 0_8_16,1-3_9-11_17-19,
2154 * 4,5,6,7,12,13,14,15,20,21,22,23
2156 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2157 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2158 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2159 { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 22, 22, 20, 20} },
2160 { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 20, 18, 16, 16} },
2161 { {32, 32, 32, 32, 28, 26, 32, 24, 20, 16, 18, 16, 14, 14} },
2162 { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
2163 { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
2165 .calTargetPower5GHT40 = {
2167 * 0_8_16,1-3_9-11_17-19,
2168 * 4,5,6,7,12,13,14,15,20,21,22,23
2170 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2171 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2172 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2173 { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 22, 22, 20, 20} },
2174 { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 20, 18, 16, 16} },
2175 { {32, 32, 32, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2176 { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2177 { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2180 0x10, 0x16, 0x18, 0x40, 0x46,
2181 0x48, 0x30, 0x36, 0x38
2185 /* Data[0].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2186 /* Data[0].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2187 /* Data[0].ctledges[2].bchannel */ FREQ2FBIN(5280, 0),
2188 /* Data[0].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2189 /* Data[0].ctledges[4].bchannel */ FREQ2FBIN(5600, 0),
2190 /* Data[0].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2191 /* Data[0].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2192 /* Data[0].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2195 /* Data[1].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2196 /* Data[1].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2197 /* Data[1].ctledges[2].bchannel */ FREQ2FBIN(5280, 0),
2198 /* Data[1].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2199 /* Data[1].ctledges[4].bchannel */ FREQ2FBIN(5520, 0),
2200 /* Data[1].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2201 /* Data[1].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2202 /* Data[1].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2206 /* Data[2].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2207 /* Data[2].ctledges[1].bchannel */ FREQ2FBIN(5230, 0),
2208 /* Data[2].ctledges[2].bchannel */ FREQ2FBIN(5270, 0),
2209 /* Data[2].ctledges[3].bchannel */ FREQ2FBIN(5310, 0),
2210 /* Data[2].ctledges[4].bchannel */ FREQ2FBIN(5510, 0),
2211 /* Data[2].ctledges[5].bchannel */ FREQ2FBIN(5550, 0),
2212 /* Data[2].ctledges[6].bchannel */ FREQ2FBIN(5670, 0),
2213 /* Data[2].ctledges[7].bchannel */ FREQ2FBIN(5755, 0)
2217 /* Data[3].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2218 /* Data[3].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
2219 /* Data[3].ctledges[2].bchannel */ FREQ2FBIN(5260, 0),
2220 /* Data[3].ctledges[3].bchannel */ FREQ2FBIN(5320, 0),
2221 /* Data[3].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
2222 /* Data[3].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2223 /* Data[3].ctledges[6].bchannel */ 0xFF,
2224 /* Data[3].ctledges[7].bchannel */ 0xFF,
2228 /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2229 /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2230 /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(5500, 0),
2231 /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(5700, 0),
2232 /* Data[4].ctledges[4].bchannel */ 0xFF,
2233 /* Data[4].ctledges[5].bchannel */ 0xFF,
2234 /* Data[4].ctledges[6].bchannel */ 0xFF,
2235 /* Data[4].ctledges[7].bchannel */ 0xFF,
2239 /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2240 /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(5270, 0),
2241 /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(5310, 0),
2242 /* Data[5].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
2243 /* Data[5].ctledges[4].bchannel */ FREQ2FBIN(5590, 0),
2244 /* Data[5].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
2245 /* Data[5].ctledges[6].bchannel */ 0xFF,
2246 /* Data[5].ctledges[7].bchannel */ 0xFF
2250 /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2251 /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
2252 /* Data[6].ctledges[2].bchannel */ FREQ2FBIN(5220, 0),
2253 /* Data[6].ctledges[3].bchannel */ FREQ2FBIN(5260, 0),
2254 /* Data[6].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
2255 /* Data[6].ctledges[5].bchannel */ FREQ2FBIN(5600, 0),
2256 /* Data[6].ctledges[6].bchannel */ FREQ2FBIN(5700, 0),
2257 /* Data[6].ctledges[7].bchannel */ FREQ2FBIN(5745, 0)
2261 /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2262 /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2263 /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(5320, 0),
2264 /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2265 /* Data[7].ctledges[4].bchannel */ FREQ2FBIN(5560, 0),
2266 /* Data[7].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2267 /* Data[7].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2268 /* Data[7].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2272 /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2273 /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(5230, 0),
2274 /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(5270, 0),
2275 /* Data[8].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
2276 /* Data[8].ctledges[4].bchannel */ FREQ2FBIN(5550, 0),
2277 /* Data[8].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
2278 /* Data[8].ctledges[6].bchannel */ FREQ2FBIN(5755, 0),
2279 /* Data[8].ctledges[7].bchannel */ FREQ2FBIN(5795, 0)
2282 .ctlPowerData_5G = {
2285 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2286 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2291 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2292 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2297 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2298 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2303 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2304 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2309 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2310 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2315 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2316 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2321 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2322 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2327 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2328 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2333 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
2334 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2340 static const struct ar9300_eeprom ar9300_h116 = {
2342 .templateVersion = 4,
2343 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
2344 .custData = {"h116-041-f0000"},
2346 .regDmn = { LE16(0), LE16(0x1f) },
2347 .txrxMask = 0x33, /* 4 bits tx and 4 bits rx */
2349 .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
2353 .blueToothOptions = 0,
2355 .deviceType = 5, /* takes lower byte in eeprom location */
2356 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
2357 .params_for_tuning_caps = {0, 0},
2358 .featureEnable = 0x0d,
2360 * bit0 - enable tx temp comp - disabled
2361 * bit1 - enable tx volt comp - disabled
2362 * bit2 - enable fastClock - enabled
2363 * bit3 - enable doubling - enabled
2364 * bit4 - enable internal regulator - disabled
2365 * bit5 - enable pa predistortion - disabled
2367 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
2368 .eepromWriteEnableGpio = 6,
2369 .wlanDisableGpio = 0,
2371 .rxBandSelectGpio = 0xff,
2376 /* ar9300_modal_eep_header 2g */
2377 /* 4 idle,t1,t2,b(4 bits per setting) */
2378 .antCtrlCommon = LE32(0x110),
2379 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
2380 .antCtrlCommon2 = LE32(0x44444),
2383 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
2384 * rx1, rx12, b (2 bits each)
2386 .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) },
2389 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
2390 * for ar9280 (0xa20c/b20c 5:0)
2392 .xatten1DB = {0x1f, 0x1f, 0x1f},
2395 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
2396 * for ar9280 (0xa20c/b20c 16:12
2398 .xatten1Margin = {0x12, 0x12, 0x12},
2403 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
2404 * channels in usual fbin coding format
2406 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
2409 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
2410 * if the register is per chain
2412 .noiseFloorThreshCh = {-1, 0, 0},
2413 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
2416 .txFrameToDataStart = 0x0e,
2417 .txFrameToPaOn = 0x0e,
2418 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2420 .switchSettling = 0x2c,
2421 .adcDesiredSize = -30,
2424 .txFrameToXpaOn = 0xe,
2426 .papdRateMaskHt20 = LE32(0x0c80C080),
2427 .papdRateMaskHt40 = LE32(0x0080C080),
2429 0, 0, 0, 0, 0, 0, 0, 0,
2433 .ant_div_control = 0,
2434 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
2441 /* ar9300_cal_data_per_freq_op_loop 2g */
2443 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2444 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2445 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2447 .calTarget_freqbin_Cck = {
2451 .calTarget_freqbin_2G = {
2456 .calTarget_freqbin_2GHT20 = {
2461 .calTarget_freqbin_2GHT40 = {
2466 .calTargetPowerCck = {
2467 /* 1L-5L,5S,11L,11S */
2468 { {34, 34, 34, 34} },
2469 { {34, 34, 34, 34} },
2471 .calTargetPower2G = {
2473 { {34, 34, 32, 32} },
2474 { {34, 34, 32, 32} },
2475 { {34, 34, 32, 32} },
2477 .calTargetPower2GHT20 = {
2478 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2479 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2480 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2482 .calTargetPower2GHT40 = {
2483 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2484 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2485 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2488 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
2489 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
2519 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2520 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2521 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2522 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
2526 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2527 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2528 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2533 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2534 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2540 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
2541 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
2542 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
2543 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
2547 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2548 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2549 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2553 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2554 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2555 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2560 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2561 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2562 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2567 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
2568 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
2569 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
2570 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
2573 .ctlPowerData_2G = {
2574 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2575 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2576 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
2578 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
2579 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2580 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2582 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
2583 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2584 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2586 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2587 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2588 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2591 /* 4 idle,t1,t2,b (4 bits per setting) */
2592 .antCtrlCommon = LE32(0x220),
2593 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
2594 .antCtrlCommon2 = LE32(0x44444),
2595 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
2597 LE16(0x150), LE16(0x150), LE16(0x150),
2599 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
2600 .xatten1DB = {0x19, 0x19, 0x19},
2603 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
2604 * for merlin (0xa20c/b20c 16:12
2606 .xatten1Margin = {0x14, 0x14, 0x14},
2609 /* spurChans spur channels in usual fbin coding format */
2610 .spurChans = {0, 0, 0, 0, 0},
2611 /* noiseFloorThreshCh Check if the register is per chain */
2612 .noiseFloorThreshCh = {-1, 0, 0},
2613 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
2616 .txFrameToDataStart = 0x0e,
2617 .txFrameToPaOn = 0x0e,
2618 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2620 .switchSettling = 0x2d,
2621 .adcDesiredSize = -30,
2624 .txFrameToXpaOn = 0xe,
2626 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
2627 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
2629 0, 0, 0, 0, 0, 0, 0, 0,
2634 .tempSlopeHigh = 50,
2635 .xatten1DBLow = {0, 0, 0},
2636 .xatten1MarginLow = {0, 0, 0},
2637 .xatten1DBHigh = {0, 0, 0},
2638 .xatten1MarginHigh = {0, 0, 0}
2683 .calTarget_freqbin_5G = {
2693 .calTarget_freqbin_5GHT20 = {
2703 .calTarget_freqbin_5GHT40 = {
2713 .calTargetPower5G = {
2715 { {30, 30, 28, 24} },
2716 { {30, 30, 28, 24} },
2717 { {30, 30, 28, 24} },
2718 { {30, 30, 28, 24} },
2719 { {30, 30, 28, 24} },
2720 { {30, 30, 28, 24} },
2721 { {30, 30, 28, 24} },
2722 { {30, 30, 28, 24} },
2724 .calTargetPower5GHT20 = {
2726 * 0_8_16,1-3_9-11_17-19,
2727 * 4,5,6,7,12,13,14,15,20,21,22,23
2729 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
2730 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
2731 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
2732 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
2733 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
2734 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
2735 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
2736 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
2738 .calTargetPower5GHT40 = {
2740 * 0_8_16,1-3_9-11_17-19,
2741 * 4,5,6,7,12,13,14,15,20,21,22,23
2743 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
2744 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
2745 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
2746 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
2747 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
2748 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
2749 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
2750 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
2753 0x10, 0x16, 0x18, 0x40, 0x46,
2754 0x48, 0x30, 0x36, 0x38
2758 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2759 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2760 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
2761 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2762 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
2763 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2764 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2765 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2768 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2769 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2770 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
2771 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2772 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
2773 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2774 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2775 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2779 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2780 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
2781 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
2782 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
2783 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
2784 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
2785 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
2786 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
2790 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2791 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
2792 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
2793 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
2794 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
2795 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2796 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
2797 /* Data[3].ctlEdges[7].bChannel */ 0xFF,
2801 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2802 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2803 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
2804 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
2805 /* Data[4].ctlEdges[4].bChannel */ 0xFF,
2806 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
2807 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
2808 /* Data[4].ctlEdges[7].bChannel */ 0xFF,
2812 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2813 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
2814 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
2815 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
2816 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
2817 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
2818 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
2819 /* Data[5].ctlEdges[7].bChannel */ 0xFF
2823 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2824 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
2825 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
2826 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
2827 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
2828 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
2829 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
2830 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
2834 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2835 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2836 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
2837 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2838 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
2839 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2840 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2841 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2845 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2846 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
2847 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
2848 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
2849 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
2850 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
2851 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
2852 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
2855 .ctlPowerData_5G = {
2858 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2859 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2864 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2865 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2870 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2871 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2876 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2877 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2882 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2883 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2888 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2889 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2894 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2895 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2900 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2901 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2906 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
2907 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2914 static const struct ar9300_eeprom *ar9300_eep_templates[] = {
2922 static const struct ar9300_eeprom *ar9003_eeprom_struct_find_by_id(int id)
2924 #define N_LOOP (sizeof(ar9300_eep_templates) / sizeof(ar9300_eep_templates[0]))
2927 for (it = 0; it < N_LOOP; it++)
2928 if (ar9300_eep_templates[it]->templateVersion == id)
2929 return ar9300_eep_templates[it];
2934 static int ath9k_hw_ar9300_check_eeprom(struct ath_hw *ah)
2939 static int interpolate(int x, int xa, int xb, int ya, int yb)
2941 int bf, factor, plus;
2943 bf = 2 * (yb - ya) * (x - xa) / (xb - xa);
2946 return ya + factor + plus;
2949 static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah,
2950 enum eeprom_param param)
2952 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
2953 struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;
2957 return get_unaligned_be16(eep->macAddr);
2959 return get_unaligned_be16(eep->macAddr + 2);
2961 return get_unaligned_be16(eep->macAddr + 4);
2963 return le16_to_cpu(pBase->regDmn[0]);
2965 return pBase->deviceCap;
2967 return pBase->opCapFlags.opFlags;
2969 return pBase->rfSilent;
2971 return (pBase->txrxMask >> 4) & 0xf;
2973 return pBase->txrxMask & 0xf;
2974 case EEP_DRIVE_STRENGTH:
2975 #define AR9300_EEP_BASE_DRIV_STRENGTH 0x1
2976 return pBase->miscConfiguration & AR9300_EEP_BASE_DRIV_STRENGTH;
2977 case EEP_INTERNAL_REGULATOR:
2978 /* Bit 4 is internal regulator flag */
2979 return (pBase->featureEnable & 0x10) >> 4;
2981 return le32_to_cpu(pBase->swreg);
2983 return !!(pBase->featureEnable & BIT(5));
2984 case EEP_CHAIN_MASK_REDUCE:
2985 return (pBase->miscConfiguration >> 0x3) & 0x1;
2986 case EEP_ANT_DIV_CTL1:
2987 return eep->base_ext1.ant_div_control;
2988 case EEP_ANTENNA_GAIN_5G:
2989 return eep->modalHeader5G.antennaGain;
2990 case EEP_ANTENNA_GAIN_2G:
2991 return eep->modalHeader2G.antennaGain;
2992 case EEP_QUICK_DROP:
2993 return pBase->miscConfiguration & BIT(1);
2999 static bool ar9300_eeprom_read_byte(struct ath_common *common, int address,
3004 if (unlikely(!ath9k_hw_nvram_read(common, address / 2, &val)))
3007 *buffer = (val >> (8 * (address % 2))) & 0xff;
3011 static bool ar9300_eeprom_read_word(struct ath_common *common, int address,
3016 if (unlikely(!ath9k_hw_nvram_read(common, address / 2, &val)))
3019 buffer[0] = val >> 8;
3020 buffer[1] = val & 0xff;
3025 static bool ar9300_read_eeprom(struct ath_hw *ah, int address, u8 *buffer,
3028 struct ath_common *common = ath9k_hw_common(ah);
3031 if ((address < 0) || ((address + count) / 2 > AR9300_EEPROM_SIZE - 1)) {
3032 ath_dbg(common, EEPROM, "eeprom address not in range\n");
3037 * Since we're reading the bytes in reverse order from a little-endian
3038 * word stream, an even address means we only use the lower half of
3039 * the 16-bit word at that address
3041 if (address % 2 == 0) {
3042 if (!ar9300_eeprom_read_byte(common, address--, buffer++))
3048 for (i = 0; i < count / 2; i++) {
3049 if (!ar9300_eeprom_read_word(common, address, buffer))
3057 if (!ar9300_eeprom_read_byte(common, address, buffer))
3063 ath_dbg(common, EEPROM, "unable to read eeprom region at offset %d\n",
3068 static bool ar9300_otp_read_word(struct ath_hw *ah, int addr, u32 *data)
3070 REG_READ(ah, AR9300_OTP_BASE + (4 * addr));
3072 if (!ath9k_hw_wait(ah, AR9300_OTP_STATUS, AR9300_OTP_STATUS_TYPE,
3073 AR9300_OTP_STATUS_VALID, 1000))
3076 *data = REG_READ(ah, AR9300_OTP_READ_DATA);
3080 static bool ar9300_read_otp(struct ath_hw *ah, int address, u8 *buffer,
3086 for (i = 0; i < count; i++) {
3087 int offset = 8 * ((address - i) % 4);
3088 if (!ar9300_otp_read_word(ah, (address - i) / 4, &data))
3091 buffer[i] = (data >> offset) & 0xff;
3098 static void ar9300_comp_hdr_unpack(u8 *best, int *code, int *reference,
3099 int *length, int *major, int *minor)
3101 unsigned long value[4];
3107 *code = ((value[0] >> 5) & 0x0007);
3108 *reference = (value[0] & 0x001f) | ((value[1] >> 2) & 0x0020);
3109 *length = ((value[1] << 4) & 0x07f0) | ((value[2] >> 4) & 0x000f);
3110 *major = (value[2] & 0x000f);
3111 *minor = (value[3] & 0x00ff);
3114 static u16 ar9300_comp_cksum(u8 *data, int dsize)
3116 int it, checksum = 0;
3118 for (it = 0; it < dsize; it++) {
3119 checksum += data[it];
3126 static bool ar9300_uncompress_block(struct ath_hw *ah,
3136 struct ath_common *common = ath9k_hw_common(ah);
3140 for (it = 0; it < size; it += (length+2)) {
3144 length = block[it+1];
3147 if (length > 0 && spot >= 0 && spot+length <= mdataSize) {
3148 ath_dbg(common, EEPROM,
3149 "Restore at %d: spot=%d offset=%d length=%d\n",
3150 it, spot, offset, length);
3151 memcpy(&mptr[spot], &block[it+2], length);
3153 } else if (length > 0) {
3154 ath_dbg(common, EEPROM,
3155 "Bad restore at %d: spot=%d offset=%d length=%d\n",
3156 it, spot, offset, length);
3163 static int ar9300_compress_decision(struct ath_hw *ah,
3168 u8 *word, int length, int mdata_size)
3170 struct ath_common *common = ath9k_hw_common(ah);
3171 const struct ar9300_eeprom *eep = NULL;
3175 if (length != mdata_size) {
3176 ath_dbg(common, EEPROM,
3177 "EEPROM structure size mismatch memory=%d eeprom=%d\n",
3178 mdata_size, length);
3181 memcpy(mptr, word + COMP_HDR_LEN, length);
3182 ath_dbg(common, EEPROM,
3183 "restored eeprom %d: uncompressed, length %d\n",
3186 case _CompressBlock:
3187 if (reference == 0) {
3189 eep = ar9003_eeprom_struct_find_by_id(reference);
3191 ath_dbg(common, EEPROM,
3192 "can't find reference eeprom struct %d\n",
3196 memcpy(mptr, eep, mdata_size);
3198 ath_dbg(common, EEPROM,
3199 "restore eeprom %d: block, reference %d, length %d\n",
3200 it, reference, length);
3201 ar9300_uncompress_block(ah, mptr, mdata_size,
3202 (word + COMP_HDR_LEN), length);
3205 ath_dbg(common, EEPROM, "unknown compression code %d\n", code);
3211 typedef bool (*eeprom_read_op)(struct ath_hw *ah, int address, u8 *buffer,
3214 static bool ar9300_check_header(void *data)
3217 return !(*word == 0 || *word == ~0);
3220 static bool ar9300_check_eeprom_header(struct ath_hw *ah, eeprom_read_op read,
3225 if (!read(ah, base_addr, header, 4))
3228 return ar9300_check_header(header);
3231 static int ar9300_eeprom_restore_flash(struct ath_hw *ah, u8 *mptr,
3234 struct ath_common *common = ath9k_hw_common(ah);
3235 u16 *data = (u16 *) mptr;
3238 for (i = 0; i < mdata_size / 2; i++, data++)
3239 ath9k_hw_nvram_read(common, i, data);
3244 * Read the configuration data from the eeprom.
3245 * The data can be put in any specified memory buffer.
3247 * Returns -1 on error.
3248 * Returns address of next memory location on success.
3250 static int ar9300_eeprom_restore_internal(struct ath_hw *ah,
3251 u8 *mptr, int mdata_size)
3258 int reference, length, major, minor;
3261 u16 checksum, mchecksum;
3262 struct ath_common *common = ath9k_hw_common(ah);
3263 eeprom_read_op read;
3265 if (ath9k_hw_use_flash(ah))
3266 return ar9300_eeprom_restore_flash(ah, mptr, mdata_size);
3268 word = kzalloc(2048, GFP_KERNEL);
3272 memcpy(mptr, &ar9300_default, mdata_size);
3274 read = ar9300_read_eeprom;
3275 if (AR_SREV_9485(ah))
3276 cptr = AR9300_BASE_ADDR_4K;
3277 else if (AR_SREV_9330(ah))
3278 cptr = AR9300_BASE_ADDR_512;
3280 cptr = AR9300_BASE_ADDR;
3281 ath_dbg(common, EEPROM, "Trying EEPROM access at Address 0x%04x\n",
3283 if (ar9300_check_eeprom_header(ah, read, cptr))
3286 cptr = AR9300_BASE_ADDR_512;
3287 ath_dbg(common, EEPROM, "Trying EEPROM access at Address 0x%04x\n",
3289 if (ar9300_check_eeprom_header(ah, read, cptr))
3292 read = ar9300_read_otp;
3293 cptr = AR9300_BASE_ADDR;
3294 ath_dbg(common, EEPROM, "Trying OTP access at Address 0x%04x\n", cptr);
3295 if (ar9300_check_eeprom_header(ah, read, cptr))
3298 cptr = AR9300_BASE_ADDR_512;
3299 ath_dbg(common, EEPROM, "Trying OTP access at Address 0x%04x\n", cptr);
3300 if (ar9300_check_eeprom_header(ah, read, cptr))
3306 ath_dbg(common, EEPROM, "Found valid EEPROM data\n");
3308 for (it = 0; it < MSTATE; it++) {
3309 if (!read(ah, cptr, word, COMP_HDR_LEN))
3312 if (!ar9300_check_header(word))
3315 ar9300_comp_hdr_unpack(word, &code, &reference,
3316 &length, &major, &minor);
3317 ath_dbg(common, EEPROM,
3318 "Found block at %x: code=%d ref=%d length=%d major=%d minor=%d\n",
3319 cptr, code, reference, length, major, minor);
3320 if ((!AR_SREV_9485(ah) && length >= 1024) ||
3321 (AR_SREV_9485(ah) && length > EEPROM_DATA_LEN_9485)) {
3322 ath_dbg(common, EEPROM, "Skipping bad header\n");
3323 cptr -= COMP_HDR_LEN;
3328 read(ah, cptr, word, COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
3329 checksum = ar9300_comp_cksum(&word[COMP_HDR_LEN], length);
3330 mchecksum = get_unaligned_le16(&word[COMP_HDR_LEN + osize]);
3331 ath_dbg(common, EEPROM, "checksum %x %x\n",
3332 checksum, mchecksum);
3333 if (checksum == mchecksum) {
3334 ar9300_compress_decision(ah, it, code, reference, mptr,
3335 word, length, mdata_size);
3337 ath_dbg(common, EEPROM,
3338 "skipping block with bad checksum\n");
3340 cptr -= (COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
3352 * Restore the configuration structure by reading the eeprom.
3353 * This function destroys any existing in-memory structure
3356 static bool ath9k_hw_ar9300_fill_eeprom(struct ath_hw *ah)
3358 u8 *mptr = (u8 *) &ah->eeprom.ar9300_eep;
3360 if (ar9300_eeprom_restore_internal(ah, mptr,
3361 sizeof(struct ar9300_eeprom)) < 0)
3367 #if defined(CONFIG_ATH9K_DEBUGFS) || defined(CONFIG_ATH9K_HTC_DEBUGFS)
3368 static u32 ar9003_dump_modal_eeprom(char *buf, u32 len, u32 size,
3369 struct ar9300_modal_eep_header *modal_hdr)
3371 PR_EEP("Chain0 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[0]));
3372 PR_EEP("Chain1 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[1]));
3373 PR_EEP("Chain2 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[2]));
3374 PR_EEP("Ant. Common Control", le32_to_cpu(modal_hdr->antCtrlCommon));
3375 PR_EEP("Ant. Common Control2", le32_to_cpu(modal_hdr->antCtrlCommon2));
3376 PR_EEP("Ant. Gain", modal_hdr->antennaGain);
3377 PR_EEP("Switch Settle", modal_hdr->switchSettling);
3378 PR_EEP("Chain0 xatten1DB", modal_hdr->xatten1DB[0]);
3379 PR_EEP("Chain1 xatten1DB", modal_hdr->xatten1DB[1]);
3380 PR_EEP("Chain2 xatten1DB", modal_hdr->xatten1DB[2]);
3381 PR_EEP("Chain0 xatten1Margin", modal_hdr->xatten1Margin[0]);
3382 PR_EEP("Chain1 xatten1Margin", modal_hdr->xatten1Margin[1]);
3383 PR_EEP("Chain2 xatten1Margin", modal_hdr->xatten1Margin[2]);
3384 PR_EEP("Temp Slope", modal_hdr->tempSlope);
3385 PR_EEP("Volt Slope", modal_hdr->voltSlope);
3386 PR_EEP("spur Channels0", modal_hdr->spurChans[0]);
3387 PR_EEP("spur Channels1", modal_hdr->spurChans[1]);
3388 PR_EEP("spur Channels2", modal_hdr->spurChans[2]);
3389 PR_EEP("spur Channels3", modal_hdr->spurChans[3]);
3390 PR_EEP("spur Channels4", modal_hdr->spurChans[4]);
3391 PR_EEP("Chain0 NF Threshold", modal_hdr->noiseFloorThreshCh[0]);
3392 PR_EEP("Chain1 NF Threshold", modal_hdr->noiseFloorThreshCh[1]);
3393 PR_EEP("Chain2 NF Threshold", modal_hdr->noiseFloorThreshCh[2]);
3394 PR_EEP("Quick Drop", modal_hdr->quick_drop);
3395 PR_EEP("txEndToXpaOff", modal_hdr->txEndToXpaOff);
3396 PR_EEP("xPA Bias Level", modal_hdr->xpaBiasLvl);
3397 PR_EEP("txFrameToDataStart", modal_hdr->txFrameToDataStart);
3398 PR_EEP("txFrameToPaOn", modal_hdr->txFrameToPaOn);
3399 PR_EEP("txFrameToXpaOn", modal_hdr->txFrameToXpaOn);
3400 PR_EEP("txClip", modal_hdr->txClip);
3401 PR_EEP("ADC Desired size", modal_hdr->adcDesiredSize);
3406 static u32 ath9k_hw_ar9003_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
3407 u8 *buf, u32 len, u32 size)
3409 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3410 struct ar9300_base_eep_hdr *pBase;
3412 if (!dump_base_hdr) {
3413 len += snprintf(buf + len, size - len,
3414 "%20s :\n", "2GHz modal Header");
3415 len = ar9003_dump_modal_eeprom(buf, len, size,
3416 &eep->modalHeader2G);
3417 len += snprintf(buf + len, size - len,
3418 "%20s :\n", "5GHz modal Header");
3419 len = ar9003_dump_modal_eeprom(buf, len, size,
3420 &eep->modalHeader5G);
3424 pBase = &eep->baseEepHeader;
3426 PR_EEP("EEPROM Version", ah->eeprom.ar9300_eep.eepromVersion);
3427 PR_EEP("RegDomain1", le16_to_cpu(pBase->regDmn[0]));
3428 PR_EEP("RegDomain2", le16_to_cpu(pBase->regDmn[1]));
3429 PR_EEP("TX Mask", (pBase->txrxMask >> 4));
3430 PR_EEP("RX Mask", (pBase->txrxMask & 0x0f));
3431 PR_EEP("Allow 5GHz", !!(pBase->opCapFlags.opFlags &
3432 AR5416_OPFLAGS_11A));
3433 PR_EEP("Allow 2GHz", !!(pBase->opCapFlags.opFlags &
3434 AR5416_OPFLAGS_11G));
3435 PR_EEP("Disable 2GHz HT20", !!(pBase->opCapFlags.opFlags &
3436 AR5416_OPFLAGS_N_2G_HT20));
3437 PR_EEP("Disable 2GHz HT40", !!(pBase->opCapFlags.opFlags &
3438 AR5416_OPFLAGS_N_2G_HT40));
3439 PR_EEP("Disable 5Ghz HT20", !!(pBase->opCapFlags.opFlags &
3440 AR5416_OPFLAGS_N_5G_HT20));
3441 PR_EEP("Disable 5Ghz HT40", !!(pBase->opCapFlags.opFlags &
3442 AR5416_OPFLAGS_N_5G_HT40));
3443 PR_EEP("Big Endian", !!(pBase->opCapFlags.eepMisc & 0x01));
3444 PR_EEP("RF Silent", pBase->rfSilent);
3445 PR_EEP("BT option", pBase->blueToothOptions);
3446 PR_EEP("Device Cap", pBase->deviceCap);
3447 PR_EEP("Device Type", pBase->deviceType);
3448 PR_EEP("Power Table Offset", pBase->pwrTableOffset);
3449 PR_EEP("Tuning Caps1", pBase->params_for_tuning_caps[0]);
3450 PR_EEP("Tuning Caps2", pBase->params_for_tuning_caps[1]);
3451 PR_EEP("Enable Tx Temp Comp", !!(pBase->featureEnable & BIT(0)));
3452 PR_EEP("Enable Tx Volt Comp", !!(pBase->featureEnable & BIT(1)));
3453 PR_EEP("Enable fast clock", !!(pBase->featureEnable & BIT(2)));
3454 PR_EEP("Enable doubling", !!(pBase->featureEnable & BIT(3)));
3455 PR_EEP("Internal regulator", !!(pBase->featureEnable & BIT(4)));
3456 PR_EEP("Enable Paprd", !!(pBase->featureEnable & BIT(5)));
3457 PR_EEP("Driver Strength", !!(pBase->miscConfiguration & BIT(0)));
3458 PR_EEP("Quick Drop", !!(pBase->miscConfiguration & BIT(1)));
3459 PR_EEP("Chain mask Reduce", (pBase->miscConfiguration >> 0x3) & 0x1);
3460 PR_EEP("Write enable Gpio", pBase->eepromWriteEnableGpio);
3461 PR_EEP("WLAN Disable Gpio", pBase->wlanDisableGpio);
3462 PR_EEP("WLAN LED Gpio", pBase->wlanLedGpio);
3463 PR_EEP("Rx Band Select Gpio", pBase->rxBandSelectGpio);
3464 PR_EEP("Tx Gain", pBase->txrxgain >> 4);
3465 PR_EEP("Rx Gain", pBase->txrxgain & 0xf);
3466 PR_EEP("SW Reg", le32_to_cpu(pBase->swreg));
3468 len += snprintf(buf + len, size - len, "%20s : %pM\n", "MacAddress",
3469 ah->eeprom.ar9300_eep.macAddr);
3477 static u32 ath9k_hw_ar9003_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
3478 u8 *buf, u32 len, u32 size)
3484 /* XXX: review hardware docs */
3485 static int ath9k_hw_ar9300_get_eeprom_ver(struct ath_hw *ah)
3487 return ah->eeprom.ar9300_eep.eepromVersion;
3490 /* XXX: could be read from the eepromVersion, not sure yet */
3491 static int ath9k_hw_ar9300_get_eeprom_rev(struct ath_hw *ah)
3496 static s32 ar9003_hw_xpa_bias_level_get(struct ath_hw *ah, bool is2ghz)
3498 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3501 return eep->modalHeader2G.xpaBiasLvl;
3503 return eep->modalHeader5G.xpaBiasLvl;
3506 static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz)
3508 int bias = ar9003_hw_xpa_bias_level_get(ah, is2ghz);
3510 if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah))
3511 REG_RMW_FIELD(ah, AR_CH0_TOP2, AR_CH0_TOP2_XPABIASLVL, bias);
3512 else if (AR_SREV_9462(ah))
3513 REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
3515 REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
3516 REG_RMW_FIELD(ah, AR_CH0_THERM,
3517 AR_CH0_THERM_XPABIASLVL_MSB,
3519 REG_RMW_FIELD(ah, AR_CH0_THERM,
3520 AR_CH0_THERM_XPASHORT2GND, 1);
3524 static u16 ar9003_switch_com_spdt_get(struct ath_hw *ah, bool is_2ghz)
3526 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3530 val = eep->modalHeader2G.switchcomspdt;
3532 val = eep->modalHeader5G.switchcomspdt;
3533 return le16_to_cpu(val);
3537 static u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, bool is2ghz)
3539 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3543 val = eep->modalHeader2G.antCtrlCommon;
3545 val = eep->modalHeader5G.antCtrlCommon;
3546 return le32_to_cpu(val);
3549 static u32 ar9003_hw_ant_ctrl_common_2_get(struct ath_hw *ah, bool is2ghz)
3551 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3555 val = eep->modalHeader2G.antCtrlCommon2;
3557 val = eep->modalHeader5G.antCtrlCommon2;
3558 return le32_to_cpu(val);
3561 static u16 ar9003_hw_ant_ctrl_chain_get(struct ath_hw *ah,
3565 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3568 if (chain >= 0 && chain < AR9300_MAX_CHAINS) {
3570 val = eep->modalHeader2G.antCtrlChain[chain];
3572 val = eep->modalHeader5G.antCtrlChain[chain];
3575 return le16_to_cpu(val);
3578 static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
3583 static const u32 switch_chain_reg[AR9300_MAX_CHAINS] = {
3584 AR_PHY_SWITCH_CHAIN_0,
3585 AR_PHY_SWITCH_CHAIN_1,
3586 AR_PHY_SWITCH_CHAIN_2,
3589 u32 value = ar9003_hw_ant_ctrl_common_get(ah, is2ghz);
3591 if (AR_SREV_9462(ah)) {
3592 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM,
3593 AR_SWITCH_TABLE_COM_AR9462_ALL, value);
3595 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM,
3596 AR_SWITCH_TABLE_COM_ALL, value);
3600 * AR9462 defines new switch table for BT/WLAN,
3601 * here's new field name in XXX.ref for both 2G and 5G.
3602 * Register: [GLB_CONTROL] GLB_CONTROL (@0x20044)
3603 * 15:12 R/W SWITCH_TABLE_COM_SPDT_WLAN_RX
3604 * SWITCH_TABLE_COM_SPDT_WLAN_RX
3606 * 11:8 R/W SWITCH_TABLE_COM_SPDT_WLAN_TX
3607 * SWITCH_TABLE_COM_SPDT_WLAN_TX
3609 * 7:4 R/W SWITCH_TABLE_COM_SPDT_WLAN_IDLE
3610 * SWITCH_TABLE_COM_SPDT_WLAN_IDLE
3612 if (AR_SREV_9462_20_OR_LATER(ah)) {
3613 value = ar9003_switch_com_spdt_get(ah, is2ghz);
3614 REG_RMW_FIELD(ah, AR_PHY_GLB_CONTROL,
3615 AR_SWITCH_TABLE_COM_SPDT_ALL, value);
3616 REG_SET_BIT(ah, AR_PHY_GLB_CONTROL, AR_BTCOEX_CTRL_SPDT_ENABLE);
3619 value = ar9003_hw_ant_ctrl_common_2_get(ah, is2ghz);
3620 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2, AR_SWITCH_TABLE_COM2_ALL, value);
3622 for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
3623 if ((ah->rxchainmask & BIT(chain)) ||
3624 (ah->txchainmask & BIT(chain))) {
3625 value = ar9003_hw_ant_ctrl_chain_get(ah, chain,
3627 REG_RMW_FIELD(ah, switch_chain_reg[chain],
3628 AR_SWITCH_TABLE_ALL, value);
3632 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
3633 value = ath9k_hw_ar9300_get_eeprom(ah, EEP_ANT_DIV_CTL1);
3635 * main_lnaconf, alt_lnaconf, main_tb, alt_tb
3636 * are the fields present
3638 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
3639 regval &= (~AR_ANT_DIV_CTRL_ALL);
3640 regval |= (value & 0x3f) << AR_ANT_DIV_CTRL_ALL_S;
3642 regval &= (~AR_PHY_9485_ANT_DIV_LNADIV);
3643 regval |= ((value >> 6) & 0x1) <<
3644 AR_PHY_9485_ANT_DIV_LNADIV_S;
3645 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
3647 /*enable fast_div */
3648 regval = REG_READ(ah, AR_PHY_CCK_DETECT);
3649 regval &= (~AR_FAST_DIV_ENABLE);
3650 regval |= ((value >> 7) & 0x1) <<
3651 AR_FAST_DIV_ENABLE_S;
3652 REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);
3654 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
3655 /* check whether antenna diversity is enabled */
3656 if ((ant_div_ctl1 >> 0x6) == 0x3) {
3657 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
3659 * clear bits 25-30 main_lnaconf, alt_lnaconf,
3662 regval &= (~(AR_PHY_9485_ANT_DIV_MAIN_LNACONF |
3663 AR_PHY_9485_ANT_DIV_ALT_LNACONF |
3664 AR_PHY_9485_ANT_DIV_ALT_GAINTB |
3665 AR_PHY_9485_ANT_DIV_MAIN_GAINTB));
3666 /* by default use LNA1 for the main antenna */
3667 regval |= (AR_PHY_9485_ANT_DIV_LNA1 <<
3668 AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S);
3669 regval |= (AR_PHY_9485_ANT_DIV_LNA2 <<
3670 AR_PHY_9485_ANT_DIV_ALT_LNACONF_S);
3671 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
3679 static void ar9003_hw_drive_strength_apply(struct ath_hw *ah)
3684 drive_strength = ath9k_hw_ar9300_get_eeprom(ah, EEP_DRIVE_STRENGTH);
3686 if (!drive_strength)
3689 reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS1);
3697 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS1, reg);
3699 reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS2);
3710 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS2, reg);
3712 reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS4);
3717 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS4, reg);
3720 static u16 ar9003_hw_atten_chain_get(struct ath_hw *ah, int chain,
3721 struct ath9k_channel *chan)
3725 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3727 if (chain >= 0 && chain < 3) {
3728 if (IS_CHAN_2GHZ(chan))
3729 return eep->modalHeader2G.xatten1DB[chain];
3730 else if (eep->base_ext2.xatten1DBLow[chain] != 0) {
3731 t[0] = eep->base_ext2.xatten1DBLow[chain];
3733 t[1] = eep->modalHeader5G.xatten1DB[chain];
3735 t[2] = eep->base_ext2.xatten1DBHigh[chain];
3737 value = ar9003_hw_power_interpolate((s32) chan->channel,
3741 return eep->modalHeader5G.xatten1DB[chain];
3748 static u16 ar9003_hw_atten_chain_get_margin(struct ath_hw *ah, int chain,
3749 struct ath9k_channel *chan)
3753 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3755 if (chain >= 0 && chain < 3) {
3756 if (IS_CHAN_2GHZ(chan))
3757 return eep->modalHeader2G.xatten1Margin[chain];
3758 else if (eep->base_ext2.xatten1MarginLow[chain] != 0) {
3759 t[0] = eep->base_ext2.xatten1MarginLow[chain];
3761 t[1] = eep->modalHeader5G.xatten1Margin[chain];
3763 t[2] = eep->base_ext2.xatten1MarginHigh[chain];
3765 value = ar9003_hw_power_interpolate((s32) chan->channel,
3769 return eep->modalHeader5G.xatten1Margin[chain];
3775 static void ar9003_hw_atten_apply(struct ath_hw *ah, struct ath9k_channel *chan)
3779 unsigned long ext_atten_reg[3] = {AR_PHY_EXT_ATTEN_CTL_0,
3780 AR_PHY_EXT_ATTEN_CTL_1,
3781 AR_PHY_EXT_ATTEN_CTL_2,
3784 /* Test value. if 0 then attenuation is unused. Don't load anything. */
3785 for (i = 0; i < 3; i++) {
3786 if (ah->txchainmask & BIT(i)) {
3787 value = ar9003_hw_atten_chain_get(ah, i, chan);
3788 REG_RMW_FIELD(ah, ext_atten_reg[i],
3789 AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB, value);
3791 value = ar9003_hw_atten_chain_get_margin(ah, i, chan);
3792 REG_RMW_FIELD(ah, ext_atten_reg[i],
3793 AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN,
3799 static bool is_pmu_set(struct ath_hw *ah, u32 pmu_reg, int pmu_set)
3803 while (pmu_set != REG_READ(ah, pmu_reg)) {
3806 REG_WRITE(ah, pmu_reg, pmu_set);
3813 void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)
3815 int internal_regulator =
3816 ath9k_hw_ar9300_get_eeprom(ah, EEP_INTERNAL_REGULATOR);
3819 if (internal_regulator) {
3820 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
3823 reg_pmu_set = REG_READ(ah, AR_PHY_PMU2) & ~AR_PHY_PMU2_PGM;
3824 REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
3825 if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
3828 if (AR_SREV_9330(ah)) {
3829 if (ah->is_clk_25mhz) {
3830 reg_pmu_set = (3 << 1) | (8 << 4) |
3831 (3 << 8) | (1 << 14) |
3832 (6 << 17) | (1 << 20) |
3835 reg_pmu_set = (4 << 1) | (7 << 4) |
3836 (3 << 8) | (1 << 14) |
3837 (6 << 17) | (1 << 20) |
3841 reg_pmu_set = (5 << 1) | (7 << 4) |
3842 (2 << 8) | (2 << 14) |
3843 (6 << 17) | (1 << 20) |
3844 (3 << 24) | (1 << 28);
3847 REG_WRITE(ah, AR_PHY_PMU1, reg_pmu_set);
3848 if (!is_pmu_set(ah, AR_PHY_PMU1, reg_pmu_set))
3851 reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2) & ~0xFFC00000)
3853 REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
3854 if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
3857 reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2) & ~0x00200000)
3859 REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
3860 if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
3862 } else if (AR_SREV_9462(ah)) {
3863 reg_val = ath9k_hw_ar9300_get_eeprom(ah, EEP_SWREG);
3864 REG_WRITE(ah, AR_PHY_PMU1, reg_val);
3866 /* Internal regulator is ON. Write swreg register. */
3867 reg_val = ath9k_hw_ar9300_get_eeprom(ah, EEP_SWREG);
3868 REG_WRITE(ah, AR_RTC_REG_CONTROL1,
3869 REG_READ(ah, AR_RTC_REG_CONTROL1) &
3870 (~AR_RTC_REG_CONTROL1_SWREG_PROGRAM));
3871 REG_WRITE(ah, AR_RTC_REG_CONTROL0, reg_val);
3872 /* Set REG_CONTROL1.SWREG_PROGRAM */
3873 REG_WRITE(ah, AR_RTC_REG_CONTROL1,
3875 AR_RTC_REG_CONTROL1) |
3876 AR_RTC_REG_CONTROL1_SWREG_PROGRAM);
3879 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
3880 REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0);
3881 while (REG_READ_FIELD(ah, AR_PHY_PMU2,
3885 REG_RMW_FIELD(ah, AR_PHY_PMU1, AR_PHY_PMU1_PWD, 0x1);
3886 while (!REG_READ_FIELD(ah, AR_PHY_PMU1,
3889 REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0x1);
3890 while (!REG_READ_FIELD(ah, AR_PHY_PMU2,
3893 } else if (AR_SREV_9462(ah))
3894 REG_RMW_FIELD(ah, AR_PHY_PMU1, AR_PHY_PMU1_PWD, 0x1);
3896 reg_val = REG_READ(ah, AR_RTC_SLEEP_CLK) |
3897 AR_RTC_FORCE_SWREG_PRD;
3898 REG_WRITE(ah, AR_RTC_SLEEP_CLK, reg_val);
3904 static void ar9003_hw_apply_tuning_caps(struct ath_hw *ah)
3906 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3907 u8 tuning_caps_param = eep->baseEepHeader.params_for_tuning_caps[0];
3909 if (eep->baseEepHeader.featureEnable & 0x40) {
3910 tuning_caps_param &= 0x7f;
3911 REG_RMW_FIELD(ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPINDAC,
3913 REG_RMW_FIELD(ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPOUTDAC,
3918 static void ar9003_hw_quick_drop_apply(struct ath_hw *ah, u16 freq)
3920 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3921 int quick_drop = ath9k_hw_ar9300_get_eeprom(ah, EEP_QUICK_DROP);
3922 s32 t[3], f[3] = {5180, 5500, 5785};
3928 quick_drop = eep->modalHeader2G.quick_drop;
3930 t[0] = eep->base_ext1.quick_drop_low;
3931 t[1] = eep->modalHeader5G.quick_drop;
3932 t[2] = eep->base_ext1.quick_drop_high;
3933 quick_drop = ar9003_hw_power_interpolate(freq, f, t, 3);
3935 REG_RMW_FIELD(ah, AR_PHY_AGC, AR_PHY_AGC_QUICK_DROP, quick_drop);
3938 static void ar9003_hw_txend_to_xpa_off_apply(struct ath_hw *ah, u16 freq)
3940 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3943 value = (freq < 4000) ? eep->modalHeader2G.txEndToXpaOff :
3944 eep->modalHeader5G.txEndToXpaOff;
3946 REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL,
3947 AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF, value);
3948 REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL,
3949 AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF, value);
3952 static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah,
3953 struct ath9k_channel *chan)
3955 ar9003_hw_xpa_bias_level_apply(ah, IS_CHAN_2GHZ(chan));
3956 ar9003_hw_ant_ctrl_apply(ah, IS_CHAN_2GHZ(chan));
3957 ar9003_hw_drive_strength_apply(ah);
3958 ar9003_hw_atten_apply(ah, chan);
3959 ar9003_hw_quick_drop_apply(ah, chan->channel);
3960 if (!AR_SREV_9330(ah) && !AR_SREV_9340(ah))
3961 ar9003_hw_internal_regulator_apply(ah);
3962 if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah))
3963 ar9003_hw_apply_tuning_caps(ah);
3964 ar9003_hw_txend_to_xpa_off_apply(ah, chan->channel);
3967 static void ath9k_hw_ar9300_set_addac(struct ath_hw *ah,
3968 struct ath9k_channel *chan)
3973 * Returns the interpolated y value corresponding to the specified x value
3974 * from the np ordered pairs of data (px,py).
3975 * The pairs do not have to be in any order.
3976 * If the specified x value is less than any of the px,
3977 * the returned y value is equal to the py for the lowest px.
3978 * If the specified x value is greater than any of the px,
3979 * the returned y value is equal to the py for the highest px.
3981 static int ar9003_hw_power_interpolate(int32_t x,
3982 int32_t *px, int32_t *py, u_int16_t np)
3985 int lx = 0, ly = 0, lhave = 0;
3986 int hx = 0, hy = 0, hhave = 0;
3993 /* identify best lower and higher x calibration measurement */
3994 for (ip = 0; ip < np; ip++) {
3997 /* this measurement is higher than our desired x */
3999 if (!hhave || dx > (x - hx)) {
4000 /* new best higher x measurement */
4006 /* this measurement is lower than our desired x */
4008 if (!lhave || dx < (x - lx)) {
4009 /* new best lower x measurement */
4017 /* the low x is good */
4019 /* so is the high x */
4021 /* they're the same, so just pick one */
4024 else /* interpolate */
4025 y = interpolate(x, lx, hx, ly, hy);
4026 } else /* only low is good, use it */
4028 } else if (hhave) /* only high is good, use it */
4030 else /* nothing is good,this should never happen unless np=0, ???? */
4035 static u8 ar9003_hw_eeprom_get_tgt_pwr(struct ath_hw *ah,
4036 u16 rateIndex, u16 freq, bool is2GHz)
4039 s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS];
4040 s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS];
4041 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4042 struct cal_tgt_pow_legacy *pEepromTargetPwr;
4046 numPiers = AR9300_NUM_2G_20_TARGET_POWERS;
4047 pEepromTargetPwr = eep->calTargetPower2G;
4048 pFreqBin = eep->calTarget_freqbin_2G;
4050 numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
4051 pEepromTargetPwr = eep->calTargetPower5G;
4052 pFreqBin = eep->calTarget_freqbin_5G;
4056 * create array of channels and targetpower from
4057 * targetpower piers stored on eeprom
4059 for (i = 0; i < numPiers; i++) {
4060 freqArray[i] = ath9k_hw_fbin2freq(pFreqBin[i], is2GHz);
4061 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
4064 /* interpolate to get target power for given frequency */
4065 return (u8) ar9003_hw_power_interpolate((s32) freq,
4067 targetPowerArray, numPiers);
4070 static u8 ar9003_hw_eeprom_get_ht20_tgt_pwr(struct ath_hw *ah,
4072 u16 freq, bool is2GHz)
4075 s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS];
4076 s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS];
4077 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4078 struct cal_tgt_pow_ht *pEepromTargetPwr;
4082 numPiers = AR9300_NUM_2G_20_TARGET_POWERS;
4083 pEepromTargetPwr = eep->calTargetPower2GHT20;
4084 pFreqBin = eep->calTarget_freqbin_2GHT20;
4086 numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
4087 pEepromTargetPwr = eep->calTargetPower5GHT20;
4088 pFreqBin = eep->calTarget_freqbin_5GHT20;
4092 * create array of channels and targetpower
4093 * from targetpower piers stored on eeprom
4095 for (i = 0; i < numPiers; i++) {
4096 freqArray[i] = ath9k_hw_fbin2freq(pFreqBin[i], is2GHz);
4097 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
4100 /* interpolate to get target power for given frequency */
4101 return (u8) ar9003_hw_power_interpolate((s32) freq,
4103 targetPowerArray, numPiers);
4106 static u8 ar9003_hw_eeprom_get_ht40_tgt_pwr(struct ath_hw *ah,
4108 u16 freq, bool is2GHz)
4111 s32 targetPowerArray[AR9300_NUM_5G_40_TARGET_POWERS];
4112 s32 freqArray[AR9300_NUM_5G_40_TARGET_POWERS];
4113 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4114 struct cal_tgt_pow_ht *pEepromTargetPwr;
4118 numPiers = AR9300_NUM_2G_40_TARGET_POWERS;
4119 pEepromTargetPwr = eep->calTargetPower2GHT40;
4120 pFreqBin = eep->calTarget_freqbin_2GHT40;
4122 numPiers = AR9300_NUM_5G_40_TARGET_POWERS;
4123 pEepromTargetPwr = eep->calTargetPower5GHT40;
4124 pFreqBin = eep->calTarget_freqbin_5GHT40;
4128 * create array of channels and targetpower from
4129 * targetpower piers stored on eeprom
4131 for (i = 0; i < numPiers; i++) {
4132 freqArray[i] = ath9k_hw_fbin2freq(pFreqBin[i], is2GHz);
4133 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
4136 /* interpolate to get target power for given frequency */
4137 return (u8) ar9003_hw_power_interpolate((s32) freq,
4139 targetPowerArray, numPiers);
4142 static u8 ar9003_hw_eeprom_get_cck_tgt_pwr(struct ath_hw *ah,
4143 u16 rateIndex, u16 freq)
4145 u16 numPiers = AR9300_NUM_2G_CCK_TARGET_POWERS, i;
4146 s32 targetPowerArray[AR9300_NUM_2G_CCK_TARGET_POWERS];
4147 s32 freqArray[AR9300_NUM_2G_CCK_TARGET_POWERS];
4148 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4149 struct cal_tgt_pow_legacy *pEepromTargetPwr = eep->calTargetPowerCck;
4150 u8 *pFreqBin = eep->calTarget_freqbin_Cck;
4153 * create array of channels and targetpower from
4154 * targetpower piers stored on eeprom
4156 for (i = 0; i < numPiers; i++) {
4157 freqArray[i] = ath9k_hw_fbin2freq(pFreqBin[i], 1);
4158 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
4161 /* interpolate to get target power for given frequency */
4162 return (u8) ar9003_hw_power_interpolate((s32) freq,
4164 targetPowerArray, numPiers);
4167 /* Set tx power registers to array of values passed in */
4168 static int ar9003_hw_tx_power_regwrite(struct ath_hw *ah, u8 * pPwrArray)
4170 #define POW_SM(_r, _s) (((_r) & 0x3f) << (_s))
4171 /* make sure forced gain is not set */
4172 REG_WRITE(ah, AR_PHY_TX_FORCED_GAIN, 0);
4174 /* Write the OFDM power per rate set */
4176 /* 6 (LSB), 9, 12, 18 (MSB) */
4177 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(0),
4178 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 24) |
4179 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 16) |
4180 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 8) |
4181 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0));
4183 /* 24 (LSB), 36, 48, 54 (MSB) */
4184 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(1),
4185 POW_SM(pPwrArray[ALL_TARGET_LEGACY_54], 24) |
4186 POW_SM(pPwrArray[ALL_TARGET_LEGACY_48], 16) |
4187 POW_SM(pPwrArray[ALL_TARGET_LEGACY_36], 8) |
4188 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0));
4190 /* Write the CCK power per rate set */
4192 /* 1L (LSB), reserved, 2L, 2S (MSB) */
4193 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(2),
4194 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 24) |
4195 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16) |
4196 /* POW_SM(txPowerTimes2, 8) | this is reserved for AR9003 */
4197 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0));
4199 /* 5.5L (LSB), 5.5S, 11L, 11S (MSB) */
4200 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(3),
4201 POW_SM(pPwrArray[ALL_TARGET_LEGACY_11S], 24) |
4202 POW_SM(pPwrArray[ALL_TARGET_LEGACY_11L], 16) |
4203 POW_SM(pPwrArray[ALL_TARGET_LEGACY_5S], 8) |
4204 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0)
4207 /* Write the power for duplicated frames - HT40 */
4209 /* dup40_cck (LSB), dup40_ofdm, ext20_cck, ext20_ofdm (MSB) */
4210 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(8),
4211 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 24) |
4212 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16) |
4213 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 8) |
4214 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0)
4217 /* Write the HT20 power per rate set */
4219 /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */
4220 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(4),
4221 POW_SM(pPwrArray[ALL_TARGET_HT20_5], 24) |
4222 POW_SM(pPwrArray[ALL_TARGET_HT20_4], 16) |
4223 POW_SM(pPwrArray[ALL_TARGET_HT20_1_3_9_11_17_19], 8) |
4224 POW_SM(pPwrArray[ALL_TARGET_HT20_0_8_16], 0)
4227 /* 6 (LSB), 7, 12, 13 (MSB) */
4228 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(5),
4229 POW_SM(pPwrArray[ALL_TARGET_HT20_13], 24) |
4230 POW_SM(pPwrArray[ALL_TARGET_HT20_12], 16) |
4231 POW_SM(pPwrArray[ALL_TARGET_HT20_7], 8) |
4232 POW_SM(pPwrArray[ALL_TARGET_HT20_6], 0)
4235 /* 14 (LSB), 15, 20, 21 */
4236 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(9),
4237 POW_SM(pPwrArray[ALL_TARGET_HT20_21], 24) |
4238 POW_SM(pPwrArray[ALL_TARGET_HT20_20], 16) |
4239 POW_SM(pPwrArray[ALL_TARGET_HT20_15], 8) |
4240 POW_SM(pPwrArray[ALL_TARGET_HT20_14], 0)
4243 /* Mixed HT20 and HT40 rates */
4245 /* HT20 22 (LSB), HT20 23, HT40 22, HT40 23 (MSB) */
4246 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(10),
4247 POW_SM(pPwrArray[ALL_TARGET_HT40_23], 24) |
4248 POW_SM(pPwrArray[ALL_TARGET_HT40_22], 16) |
4249 POW_SM(pPwrArray[ALL_TARGET_HT20_23], 8) |
4250 POW_SM(pPwrArray[ALL_TARGET_HT20_22], 0)
4254 * Write the HT40 power per rate set
4255 * correct PAR difference between HT40 and HT20/LEGACY
4256 * 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB)
4258 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(6),
4259 POW_SM(pPwrArray[ALL_TARGET_HT40_5], 24) |
4260 POW_SM(pPwrArray[ALL_TARGET_HT40_4], 16) |
4261 POW_SM(pPwrArray[ALL_TARGET_HT40_1_3_9_11_17_19], 8) |
4262 POW_SM(pPwrArray[ALL_TARGET_HT40_0_8_16], 0)
4265 /* 6 (LSB), 7, 12, 13 (MSB) */
4266 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(7),
4267 POW_SM(pPwrArray[ALL_TARGET_HT40_13], 24) |
4268 POW_SM(pPwrArray[ALL_TARGET_HT40_12], 16) |
4269 POW_SM(pPwrArray[ALL_TARGET_HT40_7], 8) |
4270 POW_SM(pPwrArray[ALL_TARGET_HT40_6], 0)
4273 /* 14 (LSB), 15, 20, 21 */
4274 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(11),
4275 POW_SM(pPwrArray[ALL_TARGET_HT40_21], 24) |
4276 POW_SM(pPwrArray[ALL_TARGET_HT40_20], 16) |
4277 POW_SM(pPwrArray[ALL_TARGET_HT40_15], 8) |
4278 POW_SM(pPwrArray[ALL_TARGET_HT40_14], 0)
4285 static void ar9003_hw_get_legacy_target_powers(struct ath_hw *ah, u16 freq,
4286 u8 *targetPowerValT2,
4289 targetPowerValT2[ALL_TARGET_LEGACY_6_24] =
4290 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_6_24, freq,
4292 targetPowerValT2[ALL_TARGET_LEGACY_36] =
4293 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_36, freq,
4295 targetPowerValT2[ALL_TARGET_LEGACY_48] =
4296 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_48, freq,
4298 targetPowerValT2[ALL_TARGET_LEGACY_54] =
4299 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_54, freq,
4303 static void ar9003_hw_get_cck_target_powers(struct ath_hw *ah, u16 freq,
4304 u8 *targetPowerValT2)
4306 targetPowerValT2[ALL_TARGET_LEGACY_1L_5L] =
4307 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_1L_5L,
4309 targetPowerValT2[ALL_TARGET_LEGACY_5S] =
4310 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_5S, freq);
4311 targetPowerValT2[ALL_TARGET_LEGACY_11L] =
4312 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11L, freq);
4313 targetPowerValT2[ALL_TARGET_LEGACY_11S] =
4314 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11S, freq);
4317 static void ar9003_hw_get_ht20_target_powers(struct ath_hw *ah, u16 freq,
4318 u8 *targetPowerValT2, bool is2GHz)
4320 targetPowerValT2[ALL_TARGET_HT20_0_8_16] =
4321 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
4323 targetPowerValT2[ALL_TARGET_HT20_1_3_9_11_17_19] =
4324 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19,
4326 targetPowerValT2[ALL_TARGET_HT20_4] =
4327 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_4, freq,
4329 targetPowerValT2[ALL_TARGET_HT20_5] =
4330 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_5, freq,
4332 targetPowerValT2[ALL_TARGET_HT20_6] =
4333 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_6, freq,
4335 targetPowerValT2[ALL_TARGET_HT20_7] =
4336 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_7, freq,
4338 targetPowerValT2[ALL_TARGET_HT20_12] =
4339 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_12, freq,
4341 targetPowerValT2[ALL_TARGET_HT20_13] =
4342 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_13, freq,
4344 targetPowerValT2[ALL_TARGET_HT20_14] =
4345 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_14, freq,
4347 targetPowerValT2[ALL_TARGET_HT20_15] =
4348 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_15, freq,
4350 targetPowerValT2[ALL_TARGET_HT20_20] =
4351 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_20, freq,
4353 targetPowerValT2[ALL_TARGET_HT20_21] =
4354 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_21, freq,
4356 targetPowerValT2[ALL_TARGET_HT20_22] =
4357 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_22, freq,
4359 targetPowerValT2[ALL_TARGET_HT20_23] =
4360 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
4364 static void ar9003_hw_get_ht40_target_powers(struct ath_hw *ah,
4366 u8 *targetPowerValT2,
4369 /* XXX: hard code for now, need to get from eeprom struct */
4370 u8 ht40PowerIncForPdadc = 0;
4372 targetPowerValT2[ALL_TARGET_HT40_0_8_16] =
4373 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
4374 is2GHz) + ht40PowerIncForPdadc;
4375 targetPowerValT2[ALL_TARGET_HT40_1_3_9_11_17_19] =
4376 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19,
4378 is2GHz) + ht40PowerIncForPdadc;
4379 targetPowerValT2[ALL_TARGET_HT40_4] =
4380 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_4, freq,
4381 is2GHz) + ht40PowerIncForPdadc;
4382 targetPowerValT2[ALL_TARGET_HT40_5] =
4383 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_5, freq,
4384 is2GHz) + ht40PowerIncForPdadc;
4385 targetPowerValT2[ALL_TARGET_HT40_6] =
4386 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_6, freq,
4387 is2GHz) + ht40PowerIncForPdadc;
4388 targetPowerValT2[ALL_TARGET_HT40_7] =
4389 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_7, freq,
4390 is2GHz) + ht40PowerIncForPdadc;
4391 targetPowerValT2[ALL_TARGET_HT40_12] =
4392 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_12, freq,
4393 is2GHz) + ht40PowerIncForPdadc;
4394 targetPowerValT2[ALL_TARGET_HT40_13] =
4395 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_13, freq,
4396 is2GHz) + ht40PowerIncForPdadc;
4397 targetPowerValT2[ALL_TARGET_HT40_14] =
4398 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_14, freq,
4399 is2GHz) + ht40PowerIncForPdadc;
4400 targetPowerValT2[ALL_TARGET_HT40_15] =
4401 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_15, freq,
4402 is2GHz) + ht40PowerIncForPdadc;
4403 targetPowerValT2[ALL_TARGET_HT40_20] =
4404 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_20, freq,
4405 is2GHz) + ht40PowerIncForPdadc;
4406 targetPowerValT2[ALL_TARGET_HT40_21] =
4407 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_21, freq,
4408 is2GHz) + ht40PowerIncForPdadc;
4409 targetPowerValT2[ALL_TARGET_HT40_22] =
4410 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_22, freq,
4411 is2GHz) + ht40PowerIncForPdadc;
4412 targetPowerValT2[ALL_TARGET_HT40_23] =
4413 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
4414 is2GHz) + ht40PowerIncForPdadc;
4417 static void ar9003_hw_get_target_power_eeprom(struct ath_hw *ah,
4418 struct ath9k_channel *chan,
4419 u8 *targetPowerValT2)
4421 bool is2GHz = IS_CHAN_2GHZ(chan);
4423 struct ath_common *common = ath9k_hw_common(ah);
4424 u16 freq = chan->channel;
4427 ar9003_hw_get_cck_target_powers(ah, freq, targetPowerValT2);
4429 ar9003_hw_get_legacy_target_powers(ah, freq, targetPowerValT2, is2GHz);
4430 ar9003_hw_get_ht20_target_powers(ah, freq, targetPowerValT2, is2GHz);
4432 if (IS_CHAN_HT40(chan))
4433 ar9003_hw_get_ht40_target_powers(ah, freq, targetPowerValT2,
4436 for (i = 0; i < ar9300RateSize; i++) {
4437 ath_dbg(common, EEPROM, "TPC[%02d] 0x%08x\n",
4438 i, targetPowerValT2[i]);
4442 static int ar9003_hw_cal_pier_get(struct ath_hw *ah,
4448 int *ptemperature, int *pvoltage)
4451 struct ar9300_cal_data_per_freq_op_loop *pCalPierStruct;
4453 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4454 struct ath_common *common = ath9k_hw_common(ah);
4456 if (ichain >= AR9300_MAX_CHAINS) {
4457 ath_dbg(common, EEPROM,
4458 "Invalid chain index, must be less than %d\n",
4463 if (mode) { /* 5GHz */
4464 if (ipier >= AR9300_NUM_5G_CAL_PIERS) {
4465 ath_dbg(common, EEPROM,
4466 "Invalid 5GHz cal pier index, must be less than %d\n",
4467 AR9300_NUM_5G_CAL_PIERS);
4470 pCalPier = &(eep->calFreqPier5G[ipier]);
4471 pCalPierStruct = &(eep->calPierData5G[ichain][ipier]);
4474 if (ipier >= AR9300_NUM_2G_CAL_PIERS) {
4475 ath_dbg(common, EEPROM,
4476 "Invalid 2GHz cal pier index, must be less than %d\n",
4477 AR9300_NUM_2G_CAL_PIERS);
4481 pCalPier = &(eep->calFreqPier2G[ipier]);
4482 pCalPierStruct = &(eep->calPierData2G[ichain][ipier]);
4486 *pfrequency = ath9k_hw_fbin2freq(*pCalPier, is2GHz);
4487 *pcorrection = pCalPierStruct->refPower;
4488 *ptemperature = pCalPierStruct->tempMeas;
4489 *pvoltage = pCalPierStruct->voltMeas;
4494 static int ar9003_hw_power_control_override(struct ath_hw *ah,
4497 int *voltage, int *temperature)
4500 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4503 REG_RMW(ah, AR_PHY_TPC_11_B0,
4504 (correction[0] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4505 AR_PHY_TPC_OLPC_GAIN_DELTA);
4506 if (ah->caps.tx_chainmask & BIT(1))
4507 REG_RMW(ah, AR_PHY_TPC_11_B1,
4508 (correction[1] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4509 AR_PHY_TPC_OLPC_GAIN_DELTA);
4510 if (ah->caps.tx_chainmask & BIT(2))
4511 REG_RMW(ah, AR_PHY_TPC_11_B2,
4512 (correction[2] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4513 AR_PHY_TPC_OLPC_GAIN_DELTA);
4515 /* enable open loop power control on chip */
4516 REG_RMW(ah, AR_PHY_TPC_6_B0,
4517 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4518 AR_PHY_TPC_6_ERROR_EST_MODE);
4519 if (ah->caps.tx_chainmask & BIT(1))
4520 REG_RMW(ah, AR_PHY_TPC_6_B1,
4521 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4522 AR_PHY_TPC_6_ERROR_EST_MODE);
4523 if (ah->caps.tx_chainmask & BIT(2))
4524 REG_RMW(ah, AR_PHY_TPC_6_B2,
4525 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4526 AR_PHY_TPC_6_ERROR_EST_MODE);
4529 * enable temperature compensation
4530 * Need to use register names
4532 if (frequency < 4000)
4533 tempSlope = eep->modalHeader2G.tempSlope;
4534 else if (eep->base_ext2.tempSlopeLow != 0) {
4535 t[0] = eep->base_ext2.tempSlopeLow;
4537 t[1] = eep->modalHeader5G.tempSlope;
4539 t[2] = eep->base_ext2.tempSlopeHigh;
4541 tempSlope = ar9003_hw_power_interpolate((s32) frequency,
4544 tempSlope = eep->modalHeader5G.tempSlope;
4546 REG_RMW_FIELD(ah, AR_PHY_TPC_19, AR_PHY_TPC_19_ALPHA_THERM, tempSlope);
4548 if (AR_SREV_9462_20(ah))
4549 REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1,
4550 AR_PHY_TPC_19_B1_ALPHA_THERM, tempSlope);
4553 REG_RMW_FIELD(ah, AR_PHY_TPC_18, AR_PHY_TPC_18_THERM_CAL_VALUE,
4559 /* Apply the recorded correction values. */
4560 static int ar9003_hw_calibration_apply(struct ath_hw *ah, int frequency)
4562 int ichain, ipier, npier;
4564 int lfrequency[AR9300_MAX_CHAINS],
4565 lcorrection[AR9300_MAX_CHAINS],
4566 ltemperature[AR9300_MAX_CHAINS], lvoltage[AR9300_MAX_CHAINS];
4567 int hfrequency[AR9300_MAX_CHAINS],
4568 hcorrection[AR9300_MAX_CHAINS],
4569 htemperature[AR9300_MAX_CHAINS], hvoltage[AR9300_MAX_CHAINS];
4571 int correction[AR9300_MAX_CHAINS],
4572 voltage[AR9300_MAX_CHAINS], temperature[AR9300_MAX_CHAINS];
4573 int pfrequency, pcorrection, ptemperature, pvoltage;
4574 struct ath_common *common = ath9k_hw_common(ah);
4576 mode = (frequency >= 4000);
4578 npier = AR9300_NUM_5G_CAL_PIERS;
4580 npier = AR9300_NUM_2G_CAL_PIERS;
4582 for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4583 lfrequency[ichain] = 0;
4584 hfrequency[ichain] = 100000;
4586 /* identify best lower and higher frequency calibration measurement */
4587 for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4588 for (ipier = 0; ipier < npier; ipier++) {
4589 if (!ar9003_hw_cal_pier_get(ah, mode, ipier, ichain,
4590 &pfrequency, &pcorrection,
4591 &ptemperature, &pvoltage)) {
4592 fdiff = frequency - pfrequency;
4595 * this measurement is higher than
4596 * our desired frequency
4599 if (hfrequency[ichain] <= 0 ||
4600 hfrequency[ichain] >= 100000 ||
4602 (frequency - hfrequency[ichain])) {
4605 * frequency measurement
4607 hfrequency[ichain] = pfrequency;
4608 hcorrection[ichain] =
4610 htemperature[ichain] =
4612 hvoltage[ichain] = pvoltage;
4616 if (lfrequency[ichain] <= 0
4618 (frequency - lfrequency[ichain])) {
4621 * frequency measurement
4623 lfrequency[ichain] = pfrequency;
4624 lcorrection[ichain] =
4626 ltemperature[ichain] =
4628 lvoltage[ichain] = pvoltage;
4636 for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4637 ath_dbg(common, EEPROM, "ch=%d f=%d low=%d %d h=%d %d\n",
4638 ichain, frequency, lfrequency[ichain],
4639 lcorrection[ichain], hfrequency[ichain],
4640 hcorrection[ichain]);
4641 /* they're the same, so just pick one */
4642 if (hfrequency[ichain] == lfrequency[ichain]) {
4643 correction[ichain] = lcorrection[ichain];
4644 voltage[ichain] = lvoltage[ichain];
4645 temperature[ichain] = ltemperature[ichain];
4647 /* the low frequency is good */
4648 else if (frequency - lfrequency[ichain] < 1000) {
4649 /* so is the high frequency, interpolate */
4650 if (hfrequency[ichain] - frequency < 1000) {
4652 correction[ichain] = interpolate(frequency,
4655 lcorrection[ichain],
4656 hcorrection[ichain]);
4658 temperature[ichain] = interpolate(frequency,
4661 ltemperature[ichain],
4662 htemperature[ichain]);
4664 voltage[ichain] = interpolate(frequency,
4670 /* only low is good, use it */
4672 correction[ichain] = lcorrection[ichain];
4673 temperature[ichain] = ltemperature[ichain];
4674 voltage[ichain] = lvoltage[ichain];
4677 /* only high is good, use it */
4678 else if (hfrequency[ichain] - frequency < 1000) {
4679 correction[ichain] = hcorrection[ichain];
4680 temperature[ichain] = htemperature[ichain];
4681 voltage[ichain] = hvoltage[ichain];
4682 } else { /* nothing is good, presume 0???? */
4683 correction[ichain] = 0;
4684 temperature[ichain] = 0;
4685 voltage[ichain] = 0;
4689 ar9003_hw_power_control_override(ah, frequency, correction, voltage,
4692 ath_dbg(common, EEPROM,
4693 "for frequency=%d, calibration correction = %d %d %d\n",
4694 frequency, correction[0], correction[1], correction[2]);
4699 static u16 ar9003_hw_get_direct_edge_power(struct ar9300_eeprom *eep,
4704 struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G;
4705 struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G;
4708 return CTL_EDGE_TPOWER(ctl_2g[idx].ctlEdges[edge]);
4710 return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge]);
4713 static u16 ar9003_hw_get_indirect_edge_power(struct ar9300_eeprom *eep,
4719 struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G;
4720 struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G;
4722 u8 *ctl_freqbin = is2GHz ?
4723 &eep->ctl_freqbin_2G[idx][0] :
4724 &eep->ctl_freqbin_5G[idx][0];
4727 if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 1) < freq &&
4728 CTL_EDGE_FLAGS(ctl_2g[idx].ctlEdges[edge - 1]))
4729 return CTL_EDGE_TPOWER(ctl_2g[idx].ctlEdges[edge - 1]);
4731 if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 0) < freq &&
4732 CTL_EDGE_FLAGS(ctl_5g[idx].ctlEdges[edge - 1]))
4733 return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge - 1]);
4736 return MAX_RATE_POWER;
4740 * Find the maximum conformance test limit for the given channel and CTL info
4742 static u16 ar9003_hw_get_max_edge_power(struct ar9300_eeprom *eep,
4743 u16 freq, int idx, bool is2GHz)
4745 u16 twiceMaxEdgePower = MAX_RATE_POWER;
4746 u8 *ctl_freqbin = is2GHz ?
4747 &eep->ctl_freqbin_2G[idx][0] :
4748 &eep->ctl_freqbin_5G[idx][0];
4749 u16 num_edges = is2GHz ?
4750 AR9300_NUM_BAND_EDGES_2G : AR9300_NUM_BAND_EDGES_5G;
4753 /* Get the edge power */
4755 (edge < num_edges) && (ctl_freqbin[edge] != AR5416_BCHAN_UNUSED);
4758 * If there's an exact channel match or an inband flag set
4759 * on the lower channel use the given rdEdgePower
4761 if (freq == ath9k_hw_fbin2freq(ctl_freqbin[edge], is2GHz)) {
4763 ar9003_hw_get_direct_edge_power(eep, idx,
4766 } else if ((edge > 0) &&
4767 (freq < ath9k_hw_fbin2freq(ctl_freqbin[edge],
4770 ar9003_hw_get_indirect_edge_power(eep, idx,
4774 * Leave loop - no more affecting edges possible in
4775 * this monotonic increasing list
4780 return twiceMaxEdgePower;
4783 static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah,
4784 struct ath9k_channel *chan,
4785 u8 *pPwrArray, u16 cfgCtl,
4786 u8 antenna_reduction,
4789 struct ath_common *common = ath9k_hw_common(ah);
4790 struct ar9300_eeprom *pEepData = &ah->eeprom.ar9300_eep;
4791 u16 twiceMaxEdgePower;
4793 u16 scaledPower = 0, minCtlPower;
4794 static const u16 ctlModesFor11a[] = {
4795 CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40
4797 static const u16 ctlModesFor11g[] = {
4798 CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT,
4799 CTL_11G_EXT, CTL_2GHT40
4802 const u16 *pCtlMode;
4804 struct chan_centers centers;
4807 u16 twiceMinEdgePower;
4808 bool is2ghz = IS_CHAN_2GHZ(chan);
4810 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
4811 scaledPower = ath9k_hw_get_scaled_power(ah, powerLimit,
4815 /* Setup for CTL modes */
4816 /* CTL_11B, CTL_11G, CTL_2GHT20 */
4818 ARRAY_SIZE(ctlModesFor11g) -
4819 SUB_NUM_CTL_MODES_AT_2G_40;
4820 pCtlMode = ctlModesFor11g;
4821 if (IS_CHAN_HT40(chan))
4823 numCtlModes = ARRAY_SIZE(ctlModesFor11g);
4825 /* Setup for CTL modes */
4826 /* CTL_11A, CTL_5GHT20 */
4827 numCtlModes = ARRAY_SIZE(ctlModesFor11a) -
4828 SUB_NUM_CTL_MODES_AT_5G_40;
4829 pCtlMode = ctlModesFor11a;
4830 if (IS_CHAN_HT40(chan))
4832 numCtlModes = ARRAY_SIZE(ctlModesFor11a);
4836 * For MIMO, need to apply regulatory caps individually across
4837 * dynamically running modes: CCK, OFDM, HT20, HT40
4839 * The outer loop walks through each possible applicable runtime mode.
4840 * The inner loop walks through each ctlIndex entry in EEPROM.
4841 * The ctl value is encoded as [7:4] == test group, [3:0] == test mode.
4843 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
4844 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
4845 (pCtlMode[ctlMode] == CTL_2GHT40);
4847 freq = centers.synth_center;
4848 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
4849 freq = centers.ext_center;
4851 freq = centers.ctl_center;
4853 ath_dbg(common, REGULATORY,
4854 "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, EXT_ADDITIVE %d\n",
4855 ctlMode, numCtlModes, isHt40CtlMode,
4856 (pCtlMode[ctlMode] & EXT_ADDITIVE));
4858 /* walk through each CTL index stored in EEPROM */
4860 ctlIndex = pEepData->ctlIndex_2G;
4861 ctlNum = AR9300_NUM_CTLS_2G;
4863 ctlIndex = pEepData->ctlIndex_5G;
4864 ctlNum = AR9300_NUM_CTLS_5G;
4867 twiceMaxEdgePower = MAX_RATE_POWER;
4868 for (i = 0; (i < ctlNum) && ctlIndex[i]; i++) {
4869 ath_dbg(common, REGULATORY,
4870 "LOOP-Ctlidx %d: cfgCtl 0x%2.2x pCtlMode 0x%2.2x ctlIndex 0x%2.2x chan %d\n",
4871 i, cfgCtl, pCtlMode[ctlMode], ctlIndex[i],
4875 * compare test group from regulatory
4876 * channel list with test mode from pCtlMode
4879 if ((((cfgCtl & ~CTL_MODE_M) |
4880 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
4882 (((cfgCtl & ~CTL_MODE_M) |
4883 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
4884 ((ctlIndex[i] & CTL_MODE_M) |
4887 ar9003_hw_get_max_edge_power(pEepData,
4891 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL)
4893 * Find the minimum of all CTL
4894 * edge powers that apply to
4898 min(twiceMaxEdgePower,
4909 minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
4911 ath_dbg(common, REGULATORY,
4912 "SEL-Min ctlMode %d pCtlMode %d 2xMaxEdge %d sP %d minCtlPwr %d\n",
4913 ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
4914 scaledPower, minCtlPower);
4916 /* Apply ctl mode to correct target power set */
4917 switch (pCtlMode[ctlMode]) {
4919 for (i = ALL_TARGET_LEGACY_1L_5L;
4920 i <= ALL_TARGET_LEGACY_11S; i++)
4922 (u8)min((u16)pPwrArray[i],
4927 for (i = ALL_TARGET_LEGACY_6_24;
4928 i <= ALL_TARGET_LEGACY_54; i++)
4930 (u8)min((u16)pPwrArray[i],
4935 for (i = ALL_TARGET_HT20_0_8_16;
4936 i <= ALL_TARGET_HT20_21; i++)
4938 (u8)min((u16)pPwrArray[i],
4940 pPwrArray[ALL_TARGET_HT20_22] =
4941 (u8)min((u16)pPwrArray[ALL_TARGET_HT20_22],
4943 pPwrArray[ALL_TARGET_HT20_23] =
4944 (u8)min((u16)pPwrArray[ALL_TARGET_HT20_23],
4949 for (i = ALL_TARGET_HT40_0_8_16;
4950 i <= ALL_TARGET_HT40_23; i++)
4952 (u8)min((u16)pPwrArray[i],
4958 } /* end ctl mode checking */
4961 static inline u8 mcsidx_to_tgtpwridx(unsigned int mcs_idx, u8 base_pwridx)
4963 u8 mod_idx = mcs_idx % 8;
4966 return mod_idx ? (base_pwridx + 1) : base_pwridx;
4968 return base_pwridx + 4 * (mcs_idx / 8) + mod_idx - 2;
4971 static void ath9k_hw_ar9300_set_txpower(struct ath_hw *ah,
4972 struct ath9k_channel *chan, u16 cfgCtl,
4973 u8 twiceAntennaReduction,
4974 u8 powerLimit, bool test)
4976 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
4977 struct ath_common *common = ath9k_hw_common(ah);
4978 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4979 struct ar9300_modal_eep_header *modal_hdr;
4980 u8 targetPowerValT2[ar9300RateSize];
4981 u8 target_power_val_t2_eep[ar9300RateSize];
4982 unsigned int i = 0, paprd_scale_factor = 0;
4983 u8 pwr_idx, min_pwridx = 0;
4985 memset(targetPowerValT2, 0 , sizeof(targetPowerValT2));
4988 * Get target powers from EEPROM - our baseline for TX Power
4990 ar9003_hw_get_target_power_eeprom(ah, chan, targetPowerValT2);
4992 if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) {
4993 if (IS_CHAN_2GHZ(chan))
4994 modal_hdr = &eep->modalHeader2G;
4996 modal_hdr = &eep->modalHeader5G;
4998 ah->paprd_ratemask =
4999 le32_to_cpu(modal_hdr->papdRateMaskHt20) &
5000 AR9300_PAPRD_RATE_MASK;
5002 ah->paprd_ratemask_ht40 =
5003 le32_to_cpu(modal_hdr->papdRateMaskHt40) &
5004 AR9300_PAPRD_RATE_MASK;
5006 paprd_scale_factor = ar9003_get_paprd_scale_factor(ah, chan);
5007 min_pwridx = IS_CHAN_HT40(chan) ? ALL_TARGET_HT40_0_8_16 :
5008 ALL_TARGET_HT20_0_8_16;
5010 if (!ah->paprd_table_write_done) {
5011 memcpy(target_power_val_t2_eep, targetPowerValT2,
5012 sizeof(targetPowerValT2));
5013 for (i = 0; i < 24; i++) {
5014 pwr_idx = mcsidx_to_tgtpwridx(i, min_pwridx);
5015 if (ah->paprd_ratemask & (1 << i)) {
5016 if (targetPowerValT2[pwr_idx] &&
5017 targetPowerValT2[pwr_idx] ==
5018 target_power_val_t2_eep[pwr_idx])
5019 targetPowerValT2[pwr_idx] -=
5024 memcpy(target_power_val_t2_eep, targetPowerValT2,
5025 sizeof(targetPowerValT2));
5028 ar9003_hw_set_power_per_rate_table(ah, chan,
5029 targetPowerValT2, cfgCtl,
5030 twiceAntennaReduction,
5033 if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) {
5034 for (i = 0; i < ar9300RateSize; i++) {
5035 if ((ah->paprd_ratemask & (1 << i)) &&
5036 (abs(targetPowerValT2[i] -
5037 target_power_val_t2_eep[i]) >
5038 paprd_scale_factor)) {
5039 ah->paprd_ratemask &= ~(1 << i);
5040 ath_dbg(common, EEPROM,
5041 "paprd disabled for mcs %d\n", i);
5046 regulatory->max_power_level = 0;
5047 for (i = 0; i < ar9300RateSize; i++) {
5048 if (targetPowerValT2[i] > regulatory->max_power_level)
5049 regulatory->max_power_level = targetPowerValT2[i];
5052 ath9k_hw_update_regulatory_maxpower(ah);
5057 for (i = 0; i < ar9300RateSize; i++) {
5058 ath_dbg(common, EEPROM, "TPC[%02d] 0x%08x\n",
5059 i, targetPowerValT2[i]);
5062 /* Write target power array to registers */
5063 ar9003_hw_tx_power_regwrite(ah, targetPowerValT2);
5064 ar9003_hw_calibration_apply(ah, chan->channel);
5066 if (IS_CHAN_2GHZ(chan)) {
5067 if (IS_CHAN_HT40(chan))
5068 i = ALL_TARGET_HT40_0_8_16;
5070 i = ALL_TARGET_HT20_0_8_16;
5072 if (IS_CHAN_HT40(chan))
5073 i = ALL_TARGET_HT40_7;
5075 i = ALL_TARGET_HT20_7;
5077 ah->paprd_target_power = targetPowerValT2[i];
5080 static u16 ath9k_hw_ar9300_get_spur_channel(struct ath_hw *ah,
5086 s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah)
5088 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
5090 return (eep->baseEepHeader.txrxgain >> 4) & 0xf; /* bits 7:4 */
5093 s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah)
5095 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
5097 return (eep->baseEepHeader.txrxgain) & 0xf; /* bits 3:0 */
5100 u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, bool is_2ghz)
5102 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
5105 return eep->modalHeader2G.spurChans;
5107 return eep->modalHeader5G.spurChans;
5110 unsigned int ar9003_get_paprd_scale_factor(struct ath_hw *ah,
5111 struct ath9k_channel *chan)
5113 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
5115 if (IS_CHAN_2GHZ(chan))
5116 return MS(le32_to_cpu(eep->modalHeader2G.papdRateMaskHt20),
5117 AR9300_PAPRD_SCALE_1);
5119 if (chan->channel >= 5700)
5120 return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt20),
5121 AR9300_PAPRD_SCALE_1);
5122 else if (chan->channel >= 5400)
5123 return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt40),
5124 AR9300_PAPRD_SCALE_2);
5126 return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt40),
5127 AR9300_PAPRD_SCALE_1);
5131 const struct eeprom_ops eep_ar9300_ops = {
5132 .check_eeprom = ath9k_hw_ar9300_check_eeprom,
5133 .get_eeprom = ath9k_hw_ar9300_get_eeprom,
5134 .fill_eeprom = ath9k_hw_ar9300_fill_eeprom,
5135 .dump_eeprom = ath9k_hw_ar9003_dump_eeprom,
5136 .get_eeprom_ver = ath9k_hw_ar9300_get_eeprom_ver,
5137 .get_eeprom_rev = ath9k_hw_ar9300_get_eeprom_rev,
5138 .set_board_values = ath9k_hw_ar9300_set_board_values,
5139 .set_addac = ath9k_hw_ar9300_set_addac,
5140 .set_txpower = ath9k_hw_ar9300_set_txpower,
5141 .get_spur_channel = ath9k_hw_ar9300_get_spur_channel