2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include "ar9003_mac.h"
19 #include "ar9003_2p2_initvals.h"
20 #include "ar9485_initvals.h"
21 #include "ar9340_initvals.h"
22 #include "ar9330_1p1_initvals.h"
23 #include "ar9330_1p2_initvals.h"
24 #include "ar955x_1p0_initvals.h"
25 #include "ar9580_1p0_initvals.h"
26 #include "ar9462_2p0_initvals.h"
28 /* General hardware code for the AR9003 hadware family */
31 * The AR9003 family uses a new INI format (pre, core, post
32 * arrays per subsystem). This provides support for the
33 * AR9003 2.2 chipsets.
35 static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
37 #define PCIE_PLL_ON_CREQ_DIS_L1_2P0 \
38 ar9462_pciephy_pll_on_clkreq_disable_L1_2p0
40 #define AR9462_BB_CTX_COEFJ(x) \
41 ar9462_##x##_baseband_core_txfir_coeff_japan_2484
43 #define AR9462_BBC_TXIFR_COEFFJ \
44 ar9462_2p0_baseband_core_txfir_coeff_japan_2484
45 if (AR_SREV_9330_11(ah)) {
47 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
49 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
50 ar9331_1p1_mac_postamble);
53 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
54 ar9331_1p1_baseband_core);
55 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
56 ar9331_1p1_baseband_postamble);
59 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
60 ar9331_1p1_radio_core);
63 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
64 ar9331_1p1_soc_preamble);
65 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
66 ar9331_1p1_soc_postamble);
69 INIT_INI_ARRAY(&ah->iniModesRxGain,
70 ar9331_common_rx_gain_1p1);
71 INIT_INI_ARRAY(&ah->iniModesTxGain,
72 ar9331_modes_lowest_ob_db_tx_gain_1p1);
74 /* additional clock settings */
76 INIT_INI_ARRAY(&ah->iniAdditional,
79 INIT_INI_ARRAY(&ah->iniAdditional,
81 } else if (AR_SREV_9330_12(ah)) {
83 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
85 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
86 ar9331_1p2_mac_postamble);
89 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
90 ar9331_1p2_baseband_core);
91 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
92 ar9331_1p2_baseband_postamble);
95 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
96 ar9331_1p2_radio_core);
99 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
100 ar9331_1p2_soc_preamble);
101 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
102 ar9331_1p2_soc_postamble);
105 INIT_INI_ARRAY(&ah->iniModesRxGain,
106 ar9331_common_rx_gain_1p2);
107 INIT_INI_ARRAY(&ah->iniModesTxGain,
108 ar9331_modes_lowest_ob_db_tx_gain_1p2);
110 /* additional clock settings */
111 if (ah->is_clk_25mhz)
112 INIT_INI_ARRAY(&ah->iniAdditional,
113 ar9331_1p2_xtal_25M);
115 INIT_INI_ARRAY(&ah->iniAdditional,
116 ar9331_1p2_xtal_40M);
117 } else if (AR_SREV_9340(ah)) {
119 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
120 ar9340_1p0_mac_core);
121 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
122 ar9340_1p0_mac_postamble);
125 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
126 ar9340_1p0_baseband_core);
127 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
128 ar9340_1p0_baseband_postamble);
131 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
132 ar9340_1p0_radio_core);
133 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
134 ar9340_1p0_radio_postamble);
137 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
138 ar9340_1p0_soc_preamble);
139 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
140 ar9340_1p0_soc_postamble);
143 INIT_INI_ARRAY(&ah->iniModesRxGain,
144 ar9340Common_wo_xlna_rx_gain_table_1p0);
145 INIT_INI_ARRAY(&ah->iniModesTxGain,
146 ar9340Modes_high_ob_db_tx_gain_table_1p0);
148 INIT_INI_ARRAY(&ah->iniModesFastClock,
149 ar9340Modes_fast_clock_1p0);
151 if (!ah->is_clk_25mhz)
152 INIT_INI_ARRAY(&ah->iniAdditional,
153 ar9340_1p0_radio_core_40M);
154 } else if (AR_SREV_9485_11(ah)) {
156 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
157 ar9485_1_1_mac_core);
158 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
159 ar9485_1_1_mac_postamble);
162 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], ar9485_1_1);
163 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
164 ar9485_1_1_baseband_core);
165 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
166 ar9485_1_1_baseband_postamble);
169 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
170 ar9485_1_1_radio_core);
171 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
172 ar9485_1_1_radio_postamble);
175 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
176 ar9485_1_1_soc_preamble);
179 INIT_INI_ARRAY(&ah->iniModesRxGain,
180 ar9485Common_wo_xlna_rx_gain_1_1);
181 INIT_INI_ARRAY(&ah->iniModesTxGain,
182 ar9485_modes_lowest_ob_db_tx_gain_1_1);
184 /* Load PCIE SERDES settings from INI */
188 INIT_INI_ARRAY(&ah->iniPcieSerdes,
189 ar9485_1_1_pcie_phy_clkreq_disable_L1);
193 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
194 ar9485_1_1_pcie_phy_clkreq_disable_L1);
195 } else if (AR_SREV_9462_20(ah)) {
197 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9462_2p0_mac_core);
198 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
199 ar9462_2p0_mac_postamble);
201 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
202 ar9462_2p0_baseband_core);
203 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
204 ar9462_2p0_baseband_postamble);
206 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
207 ar9462_2p0_radio_core);
208 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
209 ar9462_2p0_radio_postamble);
210 INIT_INI_ARRAY(&ah->ini_radio_post_sys2ant,
211 ar9462_2p0_radio_postamble_sys2ant);
213 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
214 ar9462_2p0_soc_preamble);
215 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
216 ar9462_2p0_soc_postamble);
218 INIT_INI_ARRAY(&ah->iniModesRxGain,
219 ar9462_common_rx_gain_table_2p0);
221 /* Awake -> Sleep Setting */
222 INIT_INI_ARRAY(&ah->iniPcieSerdes,
223 PCIE_PLL_ON_CREQ_DIS_L1_2P0);
224 /* Sleep -> Awake Setting */
225 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
226 PCIE_PLL_ON_CREQ_DIS_L1_2P0);
228 /* Fast clock modal settings */
229 INIT_INI_ARRAY(&ah->iniModesFastClock,
230 ar9462_modes_fast_clock_2p0);
232 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
233 AR9462_BB_CTX_COEFJ(2p0));
235 INIT_INI_ARRAY(&ah->ini_japan2484, AR9462_BBC_TXIFR_COEFFJ);
236 } else if (AR_SREV_9550(ah)) {
238 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
239 ar955x_1p0_mac_core);
240 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
241 ar955x_1p0_mac_postamble);
244 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
245 ar955x_1p0_baseband_core);
246 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
247 ar955x_1p0_baseband_postamble);
250 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
251 ar955x_1p0_radio_core);
252 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
253 ar955x_1p0_radio_postamble);
256 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
257 ar955x_1p0_soc_preamble);
258 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
259 ar955x_1p0_soc_postamble);
262 INIT_INI_ARRAY(&ah->iniModesRxGain,
263 ar955x_1p0_common_wo_xlna_rx_gain_table);
264 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
265 ar955x_1p0_common_wo_xlna_rx_gain_bounds);
266 INIT_INI_ARRAY(&ah->iniModesTxGain,
267 ar955x_1p0_modes_xpa_tx_gain_table);
269 /* Fast clock modal settings */
270 INIT_INI_ARRAY(&ah->iniModesFastClock,
271 ar955x_1p0_modes_fast_clock);
272 } else if (AR_SREV_9580(ah)) {
274 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
275 ar9580_1p0_mac_core);
276 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
277 ar9580_1p0_mac_postamble);
280 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
281 ar9580_1p0_baseband_core);
282 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
283 ar9580_1p0_baseband_postamble);
286 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
287 ar9580_1p0_radio_core);
288 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
289 ar9580_1p0_radio_postamble);
292 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
293 ar9580_1p0_soc_preamble);
294 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
295 ar9580_1p0_soc_postamble);
298 INIT_INI_ARRAY(&ah->iniModesRxGain,
299 ar9580_1p0_rx_gain_table);
300 INIT_INI_ARRAY(&ah->iniModesTxGain,
301 ar9580_1p0_low_ob_db_tx_gain_table);
303 INIT_INI_ARRAY(&ah->iniModesFastClock,
304 ar9580_1p0_modes_fast_clock);
307 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
308 ar9300_2p2_mac_core);
309 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
310 ar9300_2p2_mac_postamble);
313 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
314 ar9300_2p2_baseband_core);
315 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
316 ar9300_2p2_baseband_postamble);
319 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
320 ar9300_2p2_radio_core);
321 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
322 ar9300_2p2_radio_postamble);
325 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
326 ar9300_2p2_soc_preamble);
327 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
328 ar9300_2p2_soc_postamble);
331 INIT_INI_ARRAY(&ah->iniModesRxGain,
332 ar9300Common_rx_gain_table_2p2);
333 INIT_INI_ARRAY(&ah->iniModesTxGain,
334 ar9300Modes_lowest_ob_db_tx_gain_table_2p2);
336 /* Load PCIE SERDES settings from INI */
340 INIT_INI_ARRAY(&ah->iniPcieSerdes,
341 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2);
345 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
346 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2);
348 /* Fast clock modal settings */
349 INIT_INI_ARRAY(&ah->iniModesFastClock,
350 ar9300Modes_fast_clock_2p2);
354 static void ar9003_tx_gain_table_mode0(struct ath_hw *ah)
356 if (AR_SREV_9330_12(ah))
357 INIT_INI_ARRAY(&ah->iniModesTxGain,
358 ar9331_modes_lowest_ob_db_tx_gain_1p2);
359 else if (AR_SREV_9330_11(ah))
360 INIT_INI_ARRAY(&ah->iniModesTxGain,
361 ar9331_modes_lowest_ob_db_tx_gain_1p1);
362 else if (AR_SREV_9340(ah))
363 INIT_INI_ARRAY(&ah->iniModesTxGain,
364 ar9340Modes_lowest_ob_db_tx_gain_table_1p0);
365 else if (AR_SREV_9485_11(ah))
366 INIT_INI_ARRAY(&ah->iniModesTxGain,
367 ar9485_modes_lowest_ob_db_tx_gain_1_1);
368 else if (AR_SREV_9550(ah))
369 INIT_INI_ARRAY(&ah->iniModesTxGain,
370 ar955x_1p0_modes_xpa_tx_gain_table);
371 else if (AR_SREV_9580(ah))
372 INIT_INI_ARRAY(&ah->iniModesTxGain,
373 ar9580_1p0_lowest_ob_db_tx_gain_table);
374 else if (AR_SREV_9462_20(ah))
375 INIT_INI_ARRAY(&ah->iniModesTxGain,
376 ar9462_modes_low_ob_db_tx_gain_table_2p0);
378 INIT_INI_ARRAY(&ah->iniModesTxGain,
379 ar9300Modes_lowest_ob_db_tx_gain_table_2p2);
382 static void ar9003_tx_gain_table_mode1(struct ath_hw *ah)
384 if (AR_SREV_9330_12(ah))
385 INIT_INI_ARRAY(&ah->iniModesTxGain,
386 ar9331_modes_high_ob_db_tx_gain_1p2);
387 else if (AR_SREV_9330_11(ah))
388 INIT_INI_ARRAY(&ah->iniModesTxGain,
389 ar9331_modes_high_ob_db_tx_gain_1p1);
390 else if (AR_SREV_9340(ah))
391 INIT_INI_ARRAY(&ah->iniModesTxGain,
392 ar9340Modes_high_ob_db_tx_gain_table_1p0);
393 else if (AR_SREV_9485_11(ah))
394 INIT_INI_ARRAY(&ah->iniModesTxGain,
395 ar9485Modes_high_ob_db_tx_gain_1_1);
396 else if (AR_SREV_9580(ah))
397 INIT_INI_ARRAY(&ah->iniModesTxGain,
398 ar9580_1p0_high_ob_db_tx_gain_table);
399 else if (AR_SREV_9550(ah))
400 INIT_INI_ARRAY(&ah->iniModesTxGain,
401 ar955x_1p0_modes_no_xpa_tx_gain_table);
402 else if (AR_SREV_9462_20(ah))
403 INIT_INI_ARRAY(&ah->iniModesTxGain,
404 ar9462_modes_high_ob_db_tx_gain_table_2p0);
406 INIT_INI_ARRAY(&ah->iniModesTxGain,
407 ar9300Modes_high_ob_db_tx_gain_table_2p2);
410 static void ar9003_tx_gain_table_mode2(struct ath_hw *ah)
412 if (AR_SREV_9330_12(ah))
413 INIT_INI_ARRAY(&ah->iniModesTxGain,
414 ar9331_modes_low_ob_db_tx_gain_1p2);
415 else if (AR_SREV_9330_11(ah))
416 INIT_INI_ARRAY(&ah->iniModesTxGain,
417 ar9331_modes_low_ob_db_tx_gain_1p1);
418 else if (AR_SREV_9340(ah))
419 INIT_INI_ARRAY(&ah->iniModesTxGain,
420 ar9340Modes_low_ob_db_tx_gain_table_1p0);
421 else if (AR_SREV_9485_11(ah))
422 INIT_INI_ARRAY(&ah->iniModesTxGain,
423 ar9485Modes_low_ob_db_tx_gain_1_1);
424 else if (AR_SREV_9580(ah))
425 INIT_INI_ARRAY(&ah->iniModesTxGain,
426 ar9580_1p0_low_ob_db_tx_gain_table);
428 INIT_INI_ARRAY(&ah->iniModesTxGain,
429 ar9300Modes_low_ob_db_tx_gain_table_2p2);
432 static void ar9003_tx_gain_table_mode3(struct ath_hw *ah)
434 if (AR_SREV_9330_12(ah))
435 INIT_INI_ARRAY(&ah->iniModesTxGain,
436 ar9331_modes_high_power_tx_gain_1p2);
437 else if (AR_SREV_9330_11(ah))
438 INIT_INI_ARRAY(&ah->iniModesTxGain,
439 ar9331_modes_high_power_tx_gain_1p1);
440 else if (AR_SREV_9340(ah))
441 INIT_INI_ARRAY(&ah->iniModesTxGain,
442 ar9340Modes_high_power_tx_gain_table_1p0);
443 else if (AR_SREV_9485_11(ah))
444 INIT_INI_ARRAY(&ah->iniModesTxGain,
445 ar9485Modes_high_power_tx_gain_1_1);
446 else if (AR_SREV_9580(ah))
447 INIT_INI_ARRAY(&ah->iniModesTxGain,
448 ar9580_1p0_high_power_tx_gain_table);
450 INIT_INI_ARRAY(&ah->iniModesTxGain,
451 ar9300Modes_high_power_tx_gain_table_2p2);
454 static void ar9003_tx_gain_table_mode4(struct ath_hw *ah)
456 if (AR_SREV_9340(ah))
457 INIT_INI_ARRAY(&ah->iniModesTxGain,
458 ar9340Modes_mixed_ob_db_tx_gain_table_1p0);
459 else if (AR_SREV_9580(ah))
460 INIT_INI_ARRAY(&ah->iniModesTxGain,
461 ar9580_1p0_mixed_ob_db_tx_gain_table);
464 static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
466 switch (ar9003_hw_get_tx_gain_idx(ah)) {
469 ar9003_tx_gain_table_mode0(ah);
472 ar9003_tx_gain_table_mode1(ah);
475 ar9003_tx_gain_table_mode2(ah);
478 ar9003_tx_gain_table_mode3(ah);
481 ar9003_tx_gain_table_mode4(ah);
486 static void ar9003_rx_gain_table_mode0(struct ath_hw *ah)
488 if (AR_SREV_9330_12(ah))
489 INIT_INI_ARRAY(&ah->iniModesRxGain,
490 ar9331_common_rx_gain_1p2);
491 else if (AR_SREV_9330_11(ah))
492 INIT_INI_ARRAY(&ah->iniModesRxGain,
493 ar9331_common_rx_gain_1p1);
494 else if (AR_SREV_9340(ah))
495 INIT_INI_ARRAY(&ah->iniModesRxGain,
496 ar9340Common_rx_gain_table_1p0);
497 else if (AR_SREV_9485_11(ah))
498 INIT_INI_ARRAY(&ah->iniModesRxGain,
499 ar9485Common_wo_xlna_rx_gain_1_1);
500 else if (AR_SREV_9550(ah)) {
501 INIT_INI_ARRAY(&ah->iniModesRxGain,
502 ar955x_1p0_common_rx_gain_table);
503 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
504 ar955x_1p0_common_rx_gain_bounds);
505 } else if (AR_SREV_9580(ah))
506 INIT_INI_ARRAY(&ah->iniModesRxGain,
507 ar9580_1p0_rx_gain_table);
508 else if (AR_SREV_9462_20(ah))
509 INIT_INI_ARRAY(&ah->iniModesRxGain,
510 ar9462_common_rx_gain_table_2p0);
512 INIT_INI_ARRAY(&ah->iniModesRxGain,
513 ar9300Common_rx_gain_table_2p2);
516 static void ar9003_rx_gain_table_mode1(struct ath_hw *ah)
518 if (AR_SREV_9330_12(ah))
519 INIT_INI_ARRAY(&ah->iniModesRxGain,
520 ar9331_common_wo_xlna_rx_gain_1p2);
521 else if (AR_SREV_9330_11(ah))
522 INIT_INI_ARRAY(&ah->iniModesRxGain,
523 ar9331_common_wo_xlna_rx_gain_1p1);
524 else if (AR_SREV_9340(ah))
525 INIT_INI_ARRAY(&ah->iniModesRxGain,
526 ar9340Common_wo_xlna_rx_gain_table_1p0);
527 else if (AR_SREV_9485_11(ah))
528 INIT_INI_ARRAY(&ah->iniModesRxGain,
529 ar9485Common_wo_xlna_rx_gain_1_1);
530 else if (AR_SREV_9462_20(ah))
531 INIT_INI_ARRAY(&ah->iniModesRxGain,
532 ar9462_common_wo_xlna_rx_gain_table_2p0);
533 else if (AR_SREV_9550(ah)) {
534 INIT_INI_ARRAY(&ah->iniModesRxGain,
535 ar955x_1p0_common_wo_xlna_rx_gain_table);
536 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
537 ar955x_1p0_common_wo_xlna_rx_gain_bounds);
538 } else if (AR_SREV_9580(ah))
539 INIT_INI_ARRAY(&ah->iniModesRxGain,
540 ar9580_1p0_wo_xlna_rx_gain_table);
542 INIT_INI_ARRAY(&ah->iniModesRxGain,
543 ar9300Common_wo_xlna_rx_gain_table_2p2);
546 static void ar9003_rx_gain_table_mode2(struct ath_hw *ah)
548 if (AR_SREV_9462_20(ah))
549 INIT_INI_ARRAY(&ah->iniModesRxGain,
550 ar9462_common_mixed_rx_gain_table_2p0);
553 static void ar9003_rx_gain_table_apply(struct ath_hw *ah)
555 switch (ar9003_hw_get_rx_gain_idx(ah)) {
558 ar9003_rx_gain_table_mode0(ah);
561 ar9003_rx_gain_table_mode1(ah);
564 ar9003_rx_gain_table_mode2(ah);
569 /* set gain table pointers according to values read from the eeprom */
570 static void ar9003_hw_init_mode_gain_regs(struct ath_hw *ah)
572 ar9003_tx_gain_table_apply(ah);
573 ar9003_rx_gain_table_apply(ah);
577 * Helper for ASPM support.
579 * Disable PLL when in L0s as well as receiver clock when in L1.
580 * This power saving option must be enabled through the SerDes.
582 * Programming the SerDes must go through the same 288 bit serial shift
583 * register as the other analog registers. Hence the 9 writes.
585 static void ar9003_hw_configpcipowersave(struct ath_hw *ah,
588 /* Nothing to do on restore for 11N */
589 if (!power_off /* !restore */) {
590 /* set bit 19 to allow forcing of pcie core into L1 state */
591 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
593 /* Several PCIe massages to ensure proper behaviour */
594 if (ah->config.pcie_waen)
595 REG_WRITE(ah, AR_WA, ah->config.pcie_waen);
597 REG_WRITE(ah, AR_WA, ah->WARegVal);
601 * Configire PCIE after Ini init. SERDES values now come from ini file
602 * This enables PCIe low power mode.
604 if (ah->config.pcieSerDesWrite) {
606 struct ar5416IniArray *array;
608 array = power_off ? &ah->iniPcieSerdes :
609 &ah->iniPcieSerdesLowPower;
611 for (i = 0; i < array->ia_rows; i++) {
614 INI_RA(array, i, 1));
619 /* Sets up the AR9003 hardware familiy callbacks */
620 void ar9003_hw_attach_ops(struct ath_hw *ah)
622 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
623 struct ath_hw_ops *ops = ath9k_hw_ops(ah);
625 priv_ops->init_mode_regs = ar9003_hw_init_mode_regs;
626 priv_ops->init_mode_gain_regs = ar9003_hw_init_mode_gain_regs;
628 ops->config_pci_powersave = ar9003_hw_configpcipowersave;
630 ar9003_hw_attach_phy_ops(ah);
631 ar9003_hw_attach_calib_ops(ah);
632 ar9003_hw_attach_mac_ops(ah);