drivers/net/wireless/ath/ath9k/ar9003_phy.c

   1 /*
   2  * Copyright (c) 2010-2011 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/export.h>
  18 #include "hw.h"
  19 #include "ar9003_phy.h"
  20
  21 static const int firstep_table[] =
  22 /* level:  0   1   2   3   4   5   6   7   8  */
  23         { -4, -2,  0,  2,  4,  6,  8, 10, 12 }; /* lvl 0-8, default 2 */
  24
  25 static const int cycpwrThr1_table[] =
  26 /* level:  0   1   2   3   4   5   6   7   8  */
  27         { -6, -4, -2,  0,  2,  4,  6,  8 };     /* lvl 0-7, default 3 */
  28
  29 /*
  30  * register values to turn OFDM weak signal detection OFF
  31  */
  32 static const int m1ThreshLow_off = 127;
  33 static const int m2ThreshLow_off = 127;
  34 static const int m1Thresh_off = 127;
  35 static const int m2Thresh_off = 127;
  36 static const int m2CountThr_off =  31;
  37 static const int m2CountThrLow_off =  63;
  38 static const int m1ThreshLowExt_off = 127;
  39 static const int m2ThreshLowExt_off = 127;
  40 static const int m1ThreshExt_off = 127;
  41 static const int m2ThreshExt_off = 127;
  42
  43 /**
  44  * ar9003_hw_set_channel - set channel on single-chip device
  45  * @ah: atheros hardware structure
  46  * @chan:
  47  *
  48  * This is the function to change channel on single-chip devices, that is
  49  * for AR9300 family of chipsets.
  50  *
  51  * This function takes the channel value in MHz and sets
  52  * hardware channel value. Assumes writes have been enabled to analog bus.
  53  *
  54  * Actual Expression,
  55  *
  56  * For 2GHz channel,
  57  * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
  58  * (freq_ref = 40MHz)
  59  *
  60  * For 5GHz channel,
  61  * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
  62  * (freq_ref = 40MHz/(24>>amodeRefSel))
  63  *
  64  * For 5GHz channels which are 5MHz spaced,
  65  * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
  66  * (freq_ref = 40MHz)
  67  */
  68 static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
  69 {
  70         u16 bMode, fracMode = 0, aModeRefSel = 0;
  71         u32 freq, chan_frac, div, channelSel = 0, reg32 = 0;
  72         struct chan_centers centers;
  73         int loadSynthChannel;
  74
  75         ath9k_hw_get_channel_centers(ah, chan, &centers);
  76         freq = centers.synth_center;
  77
  78         if (freq < 4800) {     /* 2 GHz, fractional mode */
  79                 if (AR_SREV_9330(ah)) {
  80                         if (ah->is_clk_25mhz)
  81                                 div = 75;
  82                         else
  83                                 div = 120;
  84
  85                         channelSel = (freq * 4) / div;
  86                         chan_frac = (((freq * 4) % div) * 0x20000) / div;
  87                         channelSel = (channelSel << 17) | chan_frac;
  88                 } else if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
  89                         /*
  90                          * freq_ref = 40 / (refdiva >> amoderefsel);
  91                          * where refdiva=1 and amoderefsel=0
  92                          * ndiv = ((chan_mhz * 4) / 3) / freq_ref;
  93                          * chansel = int(ndiv), chanfrac = (ndiv - chansel) * 0x20000
  94                          */
  95                         channelSel = (freq * 4) / 120;
  96                         chan_frac = (((freq * 4) % 120) * 0x20000) / 120;
  97                         channelSel = (channelSel << 17) | chan_frac;
  98                 } else if (AR_SREV_9340(ah)) {
  99                         if (ah->is_clk_25mhz) {
 100                                 channelSel = (freq * 2) / 75;
 101                                 chan_frac = (((freq * 2) % 75) * 0x20000) / 75;
 102                                 channelSel = (channelSel << 17) | chan_frac;
 103                         } else {
 104                                 channelSel = CHANSEL_2G(freq) >> 1;
 105                         }
 106                 } else if (AR_SREV_9550(ah)) {
 107                         if (ah->is_clk_25mhz)
 108                                 div = 75;
 109                         else
 110                                 div = 120;
 111
 112                         channelSel = (freq * 4) / div;
 113                         chan_frac = (((freq * 4) % div) * 0x20000) / div;
 114                         channelSel = (channelSel << 17) | chan_frac;
 115                 } else {
 116                         channelSel = CHANSEL_2G(freq);
 117                 }
 118                 /* Set to 2G mode */
 119                 bMode = 1;
 120         } else {
 121                 if ((AR_SREV_9340(ah) || AR_SREV_9550(ah)) &&
 122                     ah->is_clk_25mhz) {
 123                         channelSel = freq / 75;
 124                         chan_frac = ((freq % 75) * 0x20000) / 75;
 125                         channelSel = (channelSel << 17) | chan_frac;
 126                 } else {
 127                         channelSel = CHANSEL_5G(freq);
 128                         /* Doubler is ON, so, divide channelSel by 2. */
 129                         channelSel >>= 1;
 130                 }
 131                 /* Set to 5G mode */
 132                 bMode = 0;
 133         }
 134
 135         /* Enable fractional mode for all channels */
 136         fracMode = 1;
 137         aModeRefSel = 0;
 138         loadSynthChannel = 0;
 139
 140         reg32 = (bMode << 29);
 141         REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
 142
 143         /* Enable Long shift Select for Synthesizer */
 144         REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH4,
 145                       AR_PHY_SYNTH4_LONG_SHIFT_SELECT, 1);
 146
 147         /* Program Synth. setting */
 148         reg32 = (channelSel << 2) | (fracMode << 30) |
 149                 (aModeRefSel << 28) | (loadSynthChannel << 31);
 150         REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
 151
 152         /* Toggle Load Synth channel bit */
 153         loadSynthChannel = 1;
 154         reg32 = (channelSel << 2) | (fracMode << 30) |
 155                 (aModeRefSel << 28) | (loadSynthChannel << 31);
 156         REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
 157
 158         ah->curchan = chan;
 159
 160         return 0;
 161 }
 162
 163 /**
 164  * ar9003_hw_spur_mitigate_mrc_cck - convert baseband spur frequency
 165  * @ah: atheros hardware structure
 166  * @chan:
 167  *
 168  * For single-chip solutions. Converts to baseband spur frequency given the
 169  * input channel frequency and compute register settings below.
 170  *
 171  * Spur mitigation for MRC CCK
 172  */
 173 static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah,
 174                                             struct ath9k_channel *chan)
 175 {
 176         static const u32 spur_freq[4] = { 2420, 2440, 2464, 2480 };
 177         int cur_bb_spur, negative = 0, cck_spur_freq;
 178         int i;
 179         int range, max_spur_cnts, synth_freq;
 180         u8 *spur_fbin_ptr = ar9003_get_spur_chan_ptr(ah, IS_CHAN_2GHZ(chan));
 181
 182         /*
 183          * Need to verify range +/- 10 MHz in control channel, otherwise spur
 184          * is out-of-band and can be ignored.
 185          */
 186
 187         if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
 188             AR_SREV_9550(ah)) {
 189                 if (spur_fbin_ptr[0] == 0) /* No spur */
 190                         return;
 191                 max_spur_cnts = 5;
 192                 if (IS_CHAN_HT40(chan)) {
 193                         range = 19;
 194                         if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
 195                                            AR_PHY_GC_DYN2040_PRI_CH) == 0)
 196                                 synth_freq = chan->channel + 10;
 197                         else
 198                                 synth_freq = chan->channel - 10;
 199                 } else {
 200                         range = 10;
 201                         synth_freq = chan->channel;
 202                 }
 203         } else {
 204                 range = AR_SREV_9462(ah) ? 5 : 10;
 205                 max_spur_cnts = 4;
 206                 synth_freq = chan->channel;
 207         }
 208
 209         for (i = 0; i < max_spur_cnts; i++) {
 210                 if (AR_SREV_9462(ah) && (i == 0 || i == 3))
 211                         continue;
 212
 213                 negative = 0;
 214                 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
 215                     AR_SREV_9550(ah))
 216                         cur_bb_spur = ath9k_hw_fbin2freq(spur_fbin_ptr[i],
 217                                                          IS_CHAN_2GHZ(chan));
 218                 else
 219                         cur_bb_spur = spur_freq[i];
 220
 221                 cur_bb_spur -= synth_freq;
 222                 if (cur_bb_spur < 0) {
 223                         negative = 1;
 224                         cur_bb_spur = -cur_bb_spur;
 225                 }
 226                 if (cur_bb_spur < range) {
 227                         cck_spur_freq = (int)((cur_bb_spur << 19) / 11);
 228
 229                         if (negative == 1)
 230                                 cck_spur_freq = -cck_spur_freq;
 231
 232                         cck_spur_freq = cck_spur_freq & 0xfffff;
 233
 234                         REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
 235                                       AR_PHY_AGC_CONTROL_YCOK_MAX, 0x7);
 236                         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 237                                       AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR, 0x7f);
 238                         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 239                                       AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE,
 240                                       0x2);
 241                         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 242                                       AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT,
 243                                       0x1);
 244                         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 245                                       AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ,
 246                                       cck_spur_freq);
 247
 248                         return;
 249                 }
 250         }
 251
 252         REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
 253                       AR_PHY_AGC_CONTROL_YCOK_MAX, 0x5);
 254         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 255                       AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 0x0);
 256         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 257                       AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0x0);
 258 }
 259
 260 /* Clean all spur register fields */
 261 static void ar9003_hw_spur_ofdm_clear(struct ath_hw *ah)
 262 {
 263         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 264                       AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0);
 265         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 266                       AR_PHY_TIMING11_SPUR_FREQ_SD, 0);
 267         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 268                       AR_PHY_TIMING11_SPUR_DELTA_PHASE, 0);
 269         REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
 270                       AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, 0);
 271         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 272                       AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0);
 273         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 274                       AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0);
 275         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 276                       AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0);
 277         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 278                       AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 0);
 279         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 280                       AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 0);
 281
 282         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 283                       AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0);
 284         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 285                       AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0);
 286         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 287                       AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0);
 288         REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
 289                       AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, 0);
 290         REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
 291                       AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, 0);
 292         REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
 293                       AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, 0);
 294         REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
 295                       AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0);
 296         REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
 297                       AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0);
 298         REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
 299                       AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0);
 300         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 301                       AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0);
 302 }
 303
 304 static void ar9003_hw_spur_ofdm(struct ath_hw *ah,
 305                                 int freq_offset,
 306                                 int spur_freq_sd,
 307                                 int spur_delta_phase,
 308                                 int spur_subchannel_sd,
 309                                 int range,
 310                                 int synth_freq)
 311 {
 312         int mask_index = 0;
 313
 314         /* OFDM Spur mitigation */
 315         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 316                  AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0x1);
 317         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 318                       AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd);
 319         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 320                       AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase);
 321         REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
 322                       AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, spur_subchannel_sd);
 323         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 324                       AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0x1);
 325
 326         if (!(AR_SREV_9565(ah) && range == 10 && synth_freq == 2437))
 327                 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 328                               AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0x1);
 329
 330         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 331                       AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0x1);
 332         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 333                       AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, 34);
 334         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 335                       AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 1);
 336
 337         if (!AR_SREV_9340(ah) &&
 338             REG_READ_FIELD(ah, AR_PHY_MODE,
 339                            AR_PHY_MODE_DYNAMIC) == 0x1)
 340                 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 341                               AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 1);
 342
 343         mask_index = (freq_offset << 4) / 5;
 344         if (mask_index < 0)
 345                 mask_index = mask_index - 1;
 346
 347         mask_index = mask_index & 0x7f;
 348
 349         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 350                       AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0x1);
 351         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 352                       AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0x1);
 353         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 354                       AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0x1);
 355         REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
 356                       AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, mask_index);
 357         REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
 358                       AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, mask_index);
 359         REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
 360                       AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, mask_index);
 361         REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
 362                       AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0xc);
 363         REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
 364                       AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0xc);
 365         REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
 366                       AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
 367         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 368                       AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0xff);
 369 }
 370
 371 static void ar9003_hw_spur_ofdm_9565(struct ath_hw *ah,
 372                                      int freq_offset)
 373 {
 374         int mask_index = 0;
 375
 376         mask_index = (freq_offset << 4) / 5;
 377         if (mask_index < 0)
 378                 mask_index = mask_index - 1;
 379
 380         mask_index = mask_index & 0x7f;
 381
 382         REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
 383                       AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B,
 384                       mask_index);
 385
 386         /* A == B */
 387         REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_B,
 388                       AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A,
 389                       mask_index);
 390
 391         REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
 392                       AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B,
 393                       mask_index);
 394         REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
 395                       AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_B, 0xe);
 396         REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
 397                       AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_B, 0xe);
 398
 399         /* A == B */
 400         REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_B,
 401                       AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
 402 }
 403
 404 static void ar9003_hw_spur_ofdm_work(struct ath_hw *ah,
 405                                      struct ath9k_channel *chan,
 406                                      int freq_offset,
 407                                      int range,
 408                                      int synth_freq)
 409 {
 410         int spur_freq_sd = 0;
 411         int spur_subchannel_sd = 0;
 412         int spur_delta_phase = 0;
 413
 414         if (IS_CHAN_HT40(chan)) {
 415                 if (freq_offset < 0) {
 416                         if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
 417                                            AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
 418                                 spur_subchannel_sd = 1;
 419                         else
 420                                 spur_subchannel_sd = 0;
 421
 422                         spur_freq_sd = ((freq_offset + 10) << 9) / 11;
 423
 424                 } else {
 425                         if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
 426                             AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
 427                                 spur_subchannel_sd = 0;
 428                         else
 429                                 spur_subchannel_sd = 1;
 430
 431                         spur_freq_sd = ((freq_offset - 10) << 9) / 11;
 432
 433                 }
 434
 435                 spur_delta_phase = (freq_offset << 17) / 5;
 436
 437         } else {
 438                 spur_subchannel_sd = 0;
 439                 spur_freq_sd = (freq_offset << 9) /11;
 440                 spur_delta_phase = (freq_offset << 18) / 5;
 441         }
 442
 443         spur_freq_sd = spur_freq_sd & 0x3ff;
 444         spur_delta_phase = spur_delta_phase & 0xfffff;
 445
 446         ar9003_hw_spur_ofdm(ah,
 447                             freq_offset,
 448                             spur_freq_sd,
 449                             spur_delta_phase,
 450                             spur_subchannel_sd,
 451                             range, synth_freq);
 452 }
 453
 454 /* Spur mitigation for OFDM */
 455 static void ar9003_hw_spur_mitigate_ofdm(struct ath_hw *ah,
 456                                          struct ath9k_channel *chan)
 457 {
 458         int synth_freq;
 459         int range = 10;
 460         int freq_offset = 0;
 461         int mode;
 462         u8* spurChansPtr;
 463         unsigned int i;
 464         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
 465
 466         if (IS_CHAN_5GHZ(chan)) {
 467                 spurChansPtr = &(eep->modalHeader5G.spurChans[0]);
 468                 mode = 0;
 469         }
 470         else {
 471                 spurChansPtr = &(eep->modalHeader2G.spurChans[0]);
 472                 mode = 1;
 473         }
 474
 475         if (spurChansPtr[0] == 0)
 476                 return; /* No spur in the mode */
 477
 478         if (IS_CHAN_HT40(chan)) {
 479                 range = 19;
 480                 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
 481                                    AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
 482                         synth_freq = chan->channel - 10;
 483                 else
 484                         synth_freq = chan->channel + 10;
 485         } else {
 486                 range = 10;
 487                 synth_freq = chan->channel;
 488         }
 489
 490         ar9003_hw_spur_ofdm_clear(ah);
 491
 492         for (i = 0; i < AR_EEPROM_MODAL_SPURS && spurChansPtr[i]; i++) {
 493                 freq_offset = ath9k_hw_fbin2freq(spurChansPtr[i], mode);
 494                 freq_offset -= synth_freq;
 495                 if (abs(freq_offset) < range) {
 496                         ar9003_hw_spur_ofdm_work(ah, chan, freq_offset,
 497                                                  range, synth_freq);
 498
 499                         if (AR_SREV_9565(ah) && (i < 4)) {
 500                                 freq_offset = ath9k_hw_fbin2freq(spurChansPtr[i + 1],
 501                                                                  mode);
 502                                 freq_offset -= synth_freq;
 503                                 if (abs(freq_offset) < range)
 504                                         ar9003_hw_spur_ofdm_9565(ah, freq_offset);
 505                         }
 506
 507                         break;
 508                 }
 509         }
 510 }
 511
 512 static void ar9003_hw_spur_mitigate(struct ath_hw *ah,
 513                                     struct ath9k_channel *chan)
 514 {
 515         if (!AR_SREV_9565(ah))
 516                 ar9003_hw_spur_mitigate_mrc_cck(ah, chan);
 517         ar9003_hw_spur_mitigate_ofdm(ah, chan);
 518 }
 519
 520 static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah,
 521                                          struct ath9k_channel *chan)
 522 {
 523         u32 pll;
 524
 525         pll = SM(0x5, AR_RTC_9300_PLL_REFDIV);
 526
 527         if (chan && IS_CHAN_HALF_RATE(chan))
 528                 pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL);
 529         else if (chan && IS_CHAN_QUARTER_RATE(chan))
 530                 pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL);
 531
 532         pll |= SM(0x2c, AR_RTC_9300_PLL_DIV);
 533
 534         return pll;
 535 }
 536
 537 static void ar9003_hw_set_channel_regs(struct ath_hw *ah,
 538                                        struct ath9k_channel *chan)
 539 {
 540         u32 phymode;
 541         u32 enableDacFifo = 0;
 542
 543         enableDacFifo =
 544                 (REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO);
 545
 546         /* Enable 11n HT, 20 MHz */
 547         phymode = AR_PHY_GC_HT_EN | AR_PHY_GC_SINGLE_HT_LTF1 |
 548                   AR_PHY_GC_SHORT_GI_40 | enableDacFifo;
 549
 550         /* Configure baseband for dynamic 20/40 operation */
 551         if (IS_CHAN_HT40(chan)) {
 552                 phymode |= AR_PHY_GC_DYN2040_EN;
 553                 /* Configure control (primary) channel at +-10MHz */
 554                 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
 555                     (chan->chanmode == CHANNEL_G_HT40PLUS))
 556                         phymode |= AR_PHY_GC_DYN2040_PRI_CH;
 557
 558         }
 559
 560         /* make sure we preserve INI settings */
 561         phymode |= REG_READ(ah, AR_PHY_GEN_CTRL);
 562         /* turn off Green Field detection for STA for now */
 563         phymode &= ~AR_PHY_GC_GF_DETECT_EN;
 564
 565         REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode);
 566
 567         /* Configure MAC for 20/40 operation */
 568         ath9k_hw_set11nmac2040(ah);
 569
 570         /* global transmit timeout (25 TUs default)*/
 571         REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
 572         /* carrier sense timeout */
 573         REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
 574 }
 575
 576 static void ar9003_hw_init_bb(struct ath_hw *ah,
 577                               struct ath9k_channel *chan)
 578 {
 579         u32 synthDelay;
 580
 581         /*
 582          * Wait for the frequency synth to settle (synth goes on
 583          * via AR_PHY_ACTIVE_EN).  Read the phy active delay register.
 584          * Value is in 100ns increments.
 585          */
 586         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
 587
 588         /* Activate the PHY (includes baseband activate + synthesizer on) */
 589         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
 590         ath9k_hw_synth_delay(ah, chan, synthDelay);
 591 }
 592
 593 void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx)
 594 {
 595         if (ah->caps.tx_chainmask == 5 || ah->caps.rx_chainmask == 5)
 596                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
 597                             AR_PHY_SWAP_ALT_CHAIN);
 598
 599         REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx);
 600         REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx);
 601
 602         if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7))
 603                 tx = 3;
 604
 605         REG_WRITE(ah, AR_SELFGEN_MASK, tx);
 606 }
 607
 608 /*
 609  * Override INI values with chip specific configuration.
 610  */
 611 static void ar9003_hw_override_ini(struct ath_hw *ah)
 612 {
 613         u32 val;
 614
 615         /*
 616          * Set the RX_ABORT and RX_DIS and clear it only after
 617          * RXE is set for MAC. This prevents frames with
 618          * corrupted descriptor status.
 619          */
 620         REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
 621
 622         /*
 623          * For AR9280 and above, there is a new feature that allows
 624          * Multicast search based on both MAC Address and Key ID. By default,
 625          * this feature is enabled. But since the driver is not using this
 626          * feature, we switch it off; otherwise multicast search based on
 627          * MAC addr only will fail.
 628          */
 629         val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE);
 630         REG_WRITE(ah, AR_PCU_MISC_MODE2,
 631                   val | AR_AGG_WEP_ENABLE_FIX | AR_AGG_WEP_ENABLE);
 632
 633         REG_SET_BIT(ah, AR_PHY_CCK_DETECT,
 634                     AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
 635 }
 636
 637 static void ar9003_hw_prog_ini(struct ath_hw *ah,
 638                                struct ar5416IniArray *iniArr,
 639                                int column)
 640 {
 641         unsigned int i, regWrites = 0;
 642
 643         /* New INI format: Array may be undefined (pre, core, post arrays) */
 644         if (!iniArr->ia_array)
 645                 return;
 646
 647         /*
 648          * New INI format: Pre, core, and post arrays for a given subsystem
 649          * may be modal (> 2 columns) or non-modal (2 columns). Determine if
 650          * the array is non-modal and force the column to 1.
 651          */
 652         if (column >= iniArr->ia_columns)
 653                 column = 1;
 654
 655         for (i = 0; i < iniArr->ia_rows; i++) {
 656                 u32 reg = INI_RA(iniArr, i, 0);
 657                 u32 val = INI_RA(iniArr, i, column);
 658
 659                 REG_WRITE(ah, reg, val);
 660
 661                 DO_DELAY(regWrites);
 662         }
 663 }
 664
 665 static int ar9550_hw_get_modes_txgain_index(struct ath_hw *ah,
 666                                             struct ath9k_channel *chan)
 667 {
 668         int ret;
 669
 670         switch (chan->chanmode) {
 671         case CHANNEL_A:
 672         case CHANNEL_A_HT20:
 673                 if (chan->channel <= 5350)
 674                         ret = 1;
 675                 else if ((chan->channel > 5350) && (chan->channel <= 5600))
 676                         ret = 3;
 677                 else
 678                         ret = 5;
 679                 break;
 680
 681         case CHANNEL_A_HT40PLUS:
 682         case CHANNEL_A_HT40MINUS:
 683                 if (chan->channel <= 5350)
 684                         ret = 2;
 685                 else if ((chan->channel > 5350) && (chan->channel <= 5600))
 686                         ret = 4;
 687                 else
 688                         ret = 6;
 689                 break;
 690
 691         case CHANNEL_G:
 692         case CHANNEL_G_HT20:
 693         case CHANNEL_B:
 694                 ret = 8;
 695                 break;
 696
 697         case CHANNEL_G_HT40PLUS:
 698         case CHANNEL_G_HT40MINUS:
 699                 ret = 7;
 700                 break;
 701
 702         default:
 703                 ret = -EINVAL;
 704         }
 705
 706         return ret;
 707 }
 708
 709 static int ar9003_hw_process_ini(struct ath_hw *ah,
 710                                  struct ath9k_channel *chan)
 711 {
 712         unsigned int regWrites = 0, i;
 713         u32 modesIndex;
 714
 715         switch (chan->chanmode) {
 716         case CHANNEL_A:
 717         case CHANNEL_A_HT20:
 718                 modesIndex = 1;
 719                 break;
 720         case CHANNEL_A_HT40PLUS:
 721         case CHANNEL_A_HT40MINUS:
 722                 modesIndex = 2;
 723                 break;
 724         case CHANNEL_G:
 725         case CHANNEL_G_HT20:
 726         case CHANNEL_B:
 727                 modesIndex = 4;
 728                 break;
 729         case CHANNEL_G_HT40PLUS:
 730         case CHANNEL_G_HT40MINUS:
 731                 modesIndex = 3;
 732                 break;
 733
 734         default:
 735                 return -EINVAL;
 736         }
 737
 738         /*
 739          * SOC, MAC, BB, RADIO initvals.
 740          */
 741         for (i = 0; i < ATH_INI_NUM_SPLIT; i++) {
 742                 ar9003_hw_prog_ini(ah, &ah->iniSOC[i], modesIndex);
 743                 ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex);
 744                 ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex);
 745                 ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex);
 746                 if (i == ATH_INI_POST && AR_SREV_9462_20(ah))
 747                         ar9003_hw_prog_ini(ah,
 748                                            &ah->ini_radio_post_sys2ant,
 749                                            modesIndex);
 750         }
 751
 752         /*
 753          * RXGAIN initvals.
 754          */
 755         REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites);
 756
 757         if (AR_SREV_9462_20(ah)) {
 758                 /*
 759                  * 5G-XLNA
 760                  */
 761                 if ((ar9003_hw_get_rx_gain_idx(ah) == 2) ||
 762                     (ar9003_hw_get_rx_gain_idx(ah) == 3)) {
 763                         REG_WRITE_ARRAY(&ah->ini_modes_rxgain_5g_xlna,
 764                                         modesIndex, regWrites);
 765                 }
 766         }
 767
 768         if (AR_SREV_9550(ah))
 769                 REG_WRITE_ARRAY(&ah->ini_modes_rx_gain_bounds, modesIndex,
 770                                 regWrites);
 771
 772         /*
 773          * TXGAIN initvals.
 774          */
 775         if (AR_SREV_9550(ah)) {
 776                 int modes_txgain_index;
 777
 778                 modes_txgain_index = ar9550_hw_get_modes_txgain_index(ah, chan);
 779                 if (modes_txgain_index < 0)
 780                         return -EINVAL;
 781
 782                 REG_WRITE_ARRAY(&ah->iniModesTxGain, modes_txgain_index,
 783                                 regWrites);
 784         } else {
 785                 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
 786         }
 787
 788         /*
 789          * For 5GHz channels requiring Fast Clock, apply
 790          * different modal values.
 791          */
 792         if (IS_CHAN_A_FAST_CLOCK(ah, chan))
 793                 REG_WRITE_ARRAY(&ah->iniModesFastClock,
 794                                 modesIndex, regWrites);
 795
 796         /*
 797          * Clock frequency initvals.
 798          */
 799         REG_WRITE_ARRAY(&ah->iniAdditional, 1, regWrites);
 800
 801         /*
 802          * JAPAN regulatory.
 803          */
 804         if (chan->channel == 2484)
 805                 ar9003_hw_prog_ini(ah, &ah->iniCckfirJapan2484, 1);
 806
 807         if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
 808                 REG_WRITE(ah, AR_GLB_SWREG_DISCONT_MODE,
 809                           AR_GLB_SWREG_DISCONT_EN_BT_WLAN);
 810
 811         ah->modes_index = modesIndex;
 812         ar9003_hw_override_ini(ah);
 813         ar9003_hw_set_channel_regs(ah, chan);
 814         ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
 815         ath9k_hw_apply_txpower(ah, chan, false);
 816
 817         if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
 818                 if (REG_READ_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_0,
 819                                    AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL))
 820                         ah->enabled_cals |= TX_IQ_CAL;
 821                 else
 822                         ah->enabled_cals &= ~TX_IQ_CAL;
 823
 824                 if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE)
 825                         ah->enabled_cals |= TX_CL_CAL;
 826                 else
 827                         ah->enabled_cals &= ~TX_CL_CAL;
 828         }
 829
 830         return 0;
 831 }
 832
 833 static void ar9003_hw_set_rfmode(struct ath_hw *ah,
 834                                  struct ath9k_channel *chan)
 835 {
 836         u32 rfMode = 0;
 837
 838         if (chan == NULL)
 839                 return;
 840
 841         rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
 842                 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
 843
 844         if (IS_CHAN_A_FAST_CLOCK(ah, chan))
 845                 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
 846         if (IS_CHAN_QUARTER_RATE(chan))
 847                 rfMode |= AR_PHY_MODE_QUARTER;
 848         if (IS_CHAN_HALF_RATE(chan))
 849                 rfMode |= AR_PHY_MODE_HALF;
 850
 851         if (rfMode & (AR_PHY_MODE_QUARTER | AR_PHY_MODE_HALF))
 852                 REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL,
 853                               AR_PHY_FRAME_CTL_CF_OVERLAP_WINDOW, 3);
 854
 855         REG_WRITE(ah, AR_PHY_MODE, rfMode);
 856 }
 857
 858 static void ar9003_hw_mark_phy_inactive(struct ath_hw *ah)
 859 {
 860         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
 861 }
 862
 863 static void ar9003_hw_set_delta_slope(struct ath_hw *ah,
 864                                       struct ath9k_channel *chan)
 865 {
 866         u32 coef_scaled, ds_coef_exp, ds_coef_man;
 867         u32 clockMhzScaled = 0x64000000;
 868         struct chan_centers centers;
 869
 870         /*
 871          * half and quarter rate can divide the scaled clock by 2 or 4
 872          * scale for selected channel bandwidth
 873          */
 874         if (IS_CHAN_HALF_RATE(chan))
 875                 clockMhzScaled = clockMhzScaled >> 1;
 876         else if (IS_CHAN_QUARTER_RATE(chan))
 877                 clockMhzScaled = clockMhzScaled >> 2;
 878
 879         /*
 880          * ALGO -> coef = 1e8/fcarrier*fclock/40;
 881          * scaled coef to provide precision for this floating calculation
 882          */
 883         ath9k_hw_get_channel_centers(ah, chan, &centers);
 884         coef_scaled = clockMhzScaled / centers.synth_center;
 885
 886         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
 887                                       &ds_coef_exp);
 888
 889         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
 890                       AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
 891         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
 892                       AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
 893
 894         /*
 895          * For Short GI,
 896          * scaled coeff is 9/10 that of normal coeff
 897          */
 898         coef_scaled = (9 * coef_scaled) / 10;
 899
 900         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
 901                                       &ds_coef_exp);
 902
 903         /* for short gi */
 904         REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
 905                       AR_PHY_SGI_DSC_MAN, ds_coef_man);
 906         REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
 907                       AR_PHY_SGI_DSC_EXP, ds_coef_exp);
 908 }
 909
 910 static bool ar9003_hw_rfbus_req(struct ath_hw *ah)
 911 {
 912         REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
 913         return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
 914                              AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT);
 915 }
 916
 917 /*
 918  * Wait for the frequency synth to settle (synth goes on via PHY_ACTIVE_EN).
 919  * Read the phy active delay register. Value is in 100ns increments.
 920  */
 921 static void ar9003_hw_rfbus_done(struct ath_hw *ah)
 922 {
 923         u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
 924
 925         ath9k_hw_synth_delay(ah, ah->curchan, synthDelay);
 926
 927         REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
 928 }
 929
 930 static bool ar9003_hw_ani_control(struct ath_hw *ah,
 931                                   enum ath9k_ani_cmd cmd, int param)
 932 {
 933         struct ath_common *common = ath9k_hw_common(ah);
 934         struct ath9k_channel *chan = ah->curchan;
 935         struct ar5416AniState *aniState = &ah->ani;
 936         int m1ThreshLow, m2ThreshLow;
 937         int m1Thresh, m2Thresh;
 938         int m2CountThr, m2CountThrLow;
 939         int m1ThreshLowExt, m2ThreshLowExt;
 940         int m1ThreshExt, m2ThreshExt;
 941         s32 value, value2;
 942
 943         switch (cmd & ah->ani_function) {
 944         case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
 945                 /*
 946                  * on == 1 means ofdm weak signal detection is ON
 947                  * on == 1 is the default, for less noise immunity
 948                  *
 949                  * on == 0 means ofdm weak signal detection is OFF
 950                  * on == 0 means more noise imm
 951                  */
 952                 u32 on = param ? 1 : 0;
 953
 954                 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
 955                         goto skip_ws_det;
 956
 957                 m1ThreshLow = on ?
 958                         aniState->iniDef.m1ThreshLow : m1ThreshLow_off;
 959                 m2ThreshLow = on ?
 960                         aniState->iniDef.m2ThreshLow : m2ThreshLow_off;
 961                 m1Thresh = on ?
 962                         aniState->iniDef.m1Thresh : m1Thresh_off;
 963                 m2Thresh = on ?
 964                         aniState->iniDef.m2Thresh : m2Thresh_off;
 965                 m2CountThr = on ?
 966                         aniState->iniDef.m2CountThr : m2CountThr_off;
 967                 m2CountThrLow = on ?
 968                         aniState->iniDef.m2CountThrLow : m2CountThrLow_off;
 969                 m1ThreshLowExt = on ?
 970                         aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off;
 971                 m2ThreshLowExt = on ?
 972                         aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off;
 973                 m1ThreshExt = on ?
 974                         aniState->iniDef.m1ThreshExt : m1ThreshExt_off;
 975                 m2ThreshExt = on ?
 976                         aniState->iniDef.m2ThreshExt : m2ThreshExt_off;
 977
 978                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
 979                               AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
 980                               m1ThreshLow);
 981                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
 982                               AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
 983                               m2ThreshLow);
 984                 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
 985                               AR_PHY_SFCORR_M1_THRESH,
 986                               m1Thresh);
 987                 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
 988                               AR_PHY_SFCORR_M2_THRESH,
 989                               m2Thresh);
 990                 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
 991                               AR_PHY_SFCORR_M2COUNT_THR,
 992                               m2CountThr);
 993                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
 994                               AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
 995                               m2CountThrLow);
 996                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
 997                               AR_PHY_SFCORR_EXT_M1_THRESH_LOW,
 998                               m1ThreshLowExt);
 999                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1000                               AR_PHY_SFCORR_EXT_M2_THRESH_LOW,
1001                               m2ThreshLowExt);
1002                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1003                               AR_PHY_SFCORR_EXT_M1_THRESH,
1004                               m1ThreshExt);
1005                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1006                               AR_PHY_SFCORR_EXT_M2_THRESH,
1007                               m2ThreshExt);
1008 skip_ws_det:
1009                 if (on)
1010                         REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
1011                                     AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1012                 else
1013                         REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
1014                                     AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1015
1016                 if (on != aniState->ofdmWeakSigDetect) {
1017                         ath_dbg(common, ANI,
1018                                 "** ch %d: ofdm weak signal: %s=>%s\n",
1019                                 chan->channel,
1020                                 aniState->ofdmWeakSigDetect ?
1021                                 "on" : "off",
1022                                 on ? "on" : "off");
1023                         if (on)
1024                                 ah->stats.ast_ani_ofdmon++;
1025                         else
1026                                 ah->stats.ast_ani_ofdmoff++;
1027                         aniState->ofdmWeakSigDetect = on;
1028                 }
1029                 break;
1030         }
1031         case ATH9K_ANI_FIRSTEP_LEVEL:{
1032                 u32 level = param;
1033
1034                 if (level >= ARRAY_SIZE(firstep_table)) {
1035                         ath_dbg(common, ANI,
1036                                 "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%u > %zu)\n",
1037                                 level, ARRAY_SIZE(firstep_table));
1038                         return false;
1039                 }
1040
1041                 /*
1042                  * make register setting relative to default
1043                  * from INI file & cap value
1044                  */
1045                 value = firstep_table[level] -
1046                         firstep_table[ATH9K_ANI_FIRSTEP_LVL] +
1047                         aniState->iniDef.firstep;
1048                 if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN)
1049                         value = ATH9K_SIG_FIRSTEP_SETTING_MIN;
1050                 if (value > ATH9K_SIG_FIRSTEP_SETTING_MAX)
1051                         value = ATH9K_SIG_FIRSTEP_SETTING_MAX;
1052                 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
1053                               AR_PHY_FIND_SIG_FIRSTEP,
1054                               value);
1055                 /*
1056                  * we need to set first step low register too
1057                  * make register setting relative to default
1058                  * from INI file & cap value
1059                  */
1060                 value2 = firstep_table[level] -
1061                          firstep_table[ATH9K_ANI_FIRSTEP_LVL] +
1062                          aniState->iniDef.firstepLow;
1063                 if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN)
1064                         value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN;
1065                 if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX)
1066                         value2 = ATH9K_SIG_FIRSTEP_SETTING_MAX;
1067
1068                 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW,
1069                               AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW, value2);
1070
1071                 if (level != aniState->firstepLevel) {
1072                         ath_dbg(common, ANI,
1073                                 "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n",
1074                                 chan->channel,
1075                                 aniState->firstepLevel,
1076                                 level,
1077                                 ATH9K_ANI_FIRSTEP_LVL,
1078                                 value,
1079                                 aniState->iniDef.firstep);
1080                         ath_dbg(common, ANI,
1081                                 "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n",
1082                                 chan->channel,
1083                                 aniState->firstepLevel,
1084                                 level,
1085                                 ATH9K_ANI_FIRSTEP_LVL,
1086                                 value2,
1087                                 aniState->iniDef.firstepLow);
1088                         if (level > aniState->firstepLevel)
1089                                 ah->stats.ast_ani_stepup++;
1090                         else if (level < aniState->firstepLevel)
1091                                 ah->stats.ast_ani_stepdown++;
1092                         aniState->firstepLevel = level;
1093                 }
1094                 break;
1095         }
1096         case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
1097                 u32 level = param;
1098
1099                 if (level >= ARRAY_SIZE(cycpwrThr1_table)) {
1100                         ath_dbg(common, ANI,
1101                                 "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%u > %zu)\n",
1102                                 level, ARRAY_SIZE(cycpwrThr1_table));
1103                         return false;
1104                 }
1105                 /*
1106                  * make register setting relative to default
1107                  * from INI file & cap value
1108                  */
1109                 value = cycpwrThr1_table[level] -
1110                         cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] +
1111                         aniState->iniDef.cycpwrThr1;
1112                 if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
1113                         value = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
1114                 if (value > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
1115                         value = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
1116                 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
1117                               AR_PHY_TIMING5_CYCPWR_THR1,
1118                               value);
1119
1120                 /*
1121                  * set AR_PHY_EXT_CCA for extension channel
1122                  * make register setting relative to default
1123                  * from INI file & cap value
1124                  */
1125                 value2 = cycpwrThr1_table[level] -
1126                          cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] +
1127                          aniState->iniDef.cycpwrThr1Ext;
1128                 if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
1129                         value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
1130                 if (value2 > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
1131                         value2 = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
1132                 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
1133                               AR_PHY_EXT_CYCPWR_THR1, value2);
1134
1135                 if (level != aniState->spurImmunityLevel) {
1136                         ath_dbg(common, ANI,
1137                                 "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n",
1138                                 chan->channel,
1139                                 aniState->spurImmunityLevel,
1140                                 level,
1141                                 ATH9K_ANI_SPUR_IMMUNE_LVL,
1142                                 value,
1143                                 aniState->iniDef.cycpwrThr1);
1144                         ath_dbg(common, ANI,
1145                                 "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n",
1146                                 chan->channel,
1147                                 aniState->spurImmunityLevel,
1148                                 level,
1149                                 ATH9K_ANI_SPUR_IMMUNE_LVL,
1150                                 value2,
1151                                 aniState->iniDef.cycpwrThr1Ext);
1152                         if (level > aniState->spurImmunityLevel)
1153                                 ah->stats.ast_ani_spurup++;
1154                         else if (level < aniState->spurImmunityLevel)
1155                                 ah->stats.ast_ani_spurdown++;
1156                         aniState->spurImmunityLevel = level;
1157                 }
1158                 break;
1159         }
1160         case ATH9K_ANI_MRC_CCK:{
1161                 /*
1162                  * is_on == 1 means MRC CCK ON (default, less noise imm)
1163                  * is_on == 0 means MRC CCK is OFF (more noise imm)
1164                  */
1165                 bool is_on = param ? 1 : 0;
1166                 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
1167                               AR_PHY_MRC_CCK_ENABLE, is_on);
1168                 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
1169                               AR_PHY_MRC_CCK_MUX_REG, is_on);
1170                 if (is_on != aniState->mrcCCK) {
1171                         ath_dbg(common, ANI, "** ch %d: MRC CCK: %s=>%s\n",
1172                                 chan->channel,
1173                                 aniState->mrcCCK ? "on" : "off",
1174                                 is_on ? "on" : "off");
1175                 if (is_on)
1176                         ah->stats.ast_ani_ccklow++;
1177                 else
1178                         ah->stats.ast_ani_cckhigh++;
1179                 aniState->mrcCCK = is_on;
1180                 }
1181         break;
1182         }
1183         case ATH9K_ANI_PRESENT:
1184                 break;
1185         default:
1186                 ath_dbg(common, ANI, "invalid cmd %u\n", cmd);
1187                 return false;
1188         }
1189
1190         ath_dbg(common, ANI,
1191                 "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n",
1192                 aniState->spurImmunityLevel,
1193                 aniState->ofdmWeakSigDetect ? "on" : "off",
1194                 aniState->firstepLevel,
1195                 aniState->mrcCCK ? "on" : "off",
1196                 aniState->listenTime,
1197                 aniState->ofdmPhyErrCount,
1198                 aniState->cckPhyErrCount);
1199         return true;
1200 }
1201
1202 static void ar9003_hw_do_getnf(struct ath_hw *ah,
1203                               int16_t nfarray[NUM_NF_READINGS])
1204 {
1205 #define AR_PHY_CH_MINCCA_PWR    0x1FF00000
1206 #define AR_PHY_CH_MINCCA_PWR_S  20
1207 #define AR_PHY_CH_EXT_MINCCA_PWR 0x01FF0000
1208 #define AR_PHY_CH_EXT_MINCCA_PWR_S 16
1209
1210         int16_t nf;
1211         int i;
1212
1213         for (i = 0; i < AR9300_MAX_CHAINS; i++) {
1214                 if (ah->rxchainmask & BIT(i)) {
1215                         nf = MS(REG_READ(ah, ah->nf_regs[i]),
1216                                          AR_PHY_CH_MINCCA_PWR);
1217                         nfarray[i] = sign_extend32(nf, 8);
1218
1219                         if (IS_CHAN_HT40(ah->curchan)) {
1220                                 u8 ext_idx = AR9300_MAX_CHAINS + i;
1221
1222                                 nf = MS(REG_READ(ah, ah->nf_regs[ext_idx]),
1223                                                  AR_PHY_CH_EXT_MINCCA_PWR);
1224                                 nfarray[ext_idx] = sign_extend32(nf, 8);
1225                         }
1226                 }
1227         }
1228 }
1229
1230 static void ar9003_hw_set_nf_limits(struct ath_hw *ah)
1231 {
1232         ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ;
1233         ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ;
1234         ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9300_2GHZ;
1235         ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ;
1236         ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ;
1237         ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9300_5GHZ;
1238
1239         if (AR_SREV_9330(ah))
1240                 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9330_2GHZ;
1241
1242         if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
1243                 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_2GHZ;
1244                 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9462_2GHZ;
1245                 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_5GHZ;
1246                 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9462_5GHZ;
1247         }
1248 }
1249
1250 /*
1251  * Initialize the ANI register values with default (ini) values.
1252  * This routine is called during a (full) hardware reset after
1253  * all the registers are initialised from the INI.
1254  */
1255 static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah)
1256 {
1257         struct ar5416AniState *aniState;
1258         struct ath_common *common = ath9k_hw_common(ah);
1259         struct ath9k_channel *chan = ah->curchan;
1260         struct ath9k_ani_default *iniDef;
1261         u32 val;
1262
1263         aniState = &ah->ani;
1264         iniDef = &aniState->iniDef;
1265
1266         ath_dbg(common, ANI, "ver %d.%d opmode %u chan %d Mhz/0x%x\n",
1267                 ah->hw_version.macVersion,
1268                 ah->hw_version.macRev,
1269                 ah->opmode,
1270                 chan->channel,
1271                 chan->channelFlags);
1272
1273         val = REG_READ(ah, AR_PHY_SFCORR);
1274         iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
1275         iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH);
1276         iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR);
1277
1278         val = REG_READ(ah, AR_PHY_SFCORR_LOW);
1279         iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW);
1280         iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW);
1281         iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW);
1282
1283         val = REG_READ(ah, AR_PHY_SFCORR_EXT);
1284         iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH);
1285         iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH);
1286         iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW);
1287         iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW);
1288         iniDef->firstep = REG_READ_FIELD(ah,
1289                                          AR_PHY_FIND_SIG,
1290                                          AR_PHY_FIND_SIG_FIRSTEP);
1291         iniDef->firstepLow = REG_READ_FIELD(ah,
1292                                             AR_PHY_FIND_SIG_LOW,
1293                                             AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW);
1294         iniDef->cycpwrThr1 = REG_READ_FIELD(ah,
1295                                             AR_PHY_TIMING5,
1296                                             AR_PHY_TIMING5_CYCPWR_THR1);
1297         iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah,
1298                                                AR_PHY_EXT_CCA,
1299                                                AR_PHY_EXT_CYCPWR_THR1);
1300
1301         /* these levels just got reset to defaults by the INI */
1302         aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL;
1303         aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL;
1304         aniState->ofdmWeakSigDetect = true;
1305         aniState->mrcCCK = true;
1306 }
1307
1308 static void ar9003_hw_set_radar_params(struct ath_hw *ah,
1309                                        struct ath_hw_radar_conf *conf)
1310 {
1311         u32 radar_0 = 0, radar_1 = 0;
1312
1313         if (!conf) {
1314                 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA);
1315                 return;
1316         }
1317
1318         radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA;
1319         radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR);
1320         radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI);
1321         radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT);
1322         radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI);
1323         radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND);
1324
1325         radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI;
1326         radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK;
1327         radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN);
1328         radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH);
1329         radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH);
1330
1331         REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);
1332         REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);
1333         if (conf->ext_channel)
1334                 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1335         else
1336                 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1337 }
1338
1339 static void ar9003_hw_set_radar_conf(struct ath_hw *ah)
1340 {
1341         struct ath_hw_radar_conf *conf = &ah->radar_conf;
1342
1343         conf->fir_power = -28;
1344         conf->radar_rssi = 0;
1345         conf->pulse_height = 10;
1346         conf->pulse_rssi = 24;
1347         conf->pulse_inband = 8;
1348         conf->pulse_maxlen = 255;
1349         conf->pulse_inband_step = 12;
1350         conf->radar_inband = 8;
1351 }
1352
1353 static void ar9003_hw_antdiv_comb_conf_get(struct ath_hw *ah,
1354                                            struct ath_hw_antcomb_conf *antconf)
1355 {
1356         u32 regval;
1357
1358         regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1359         antconf->main_lna_conf = (regval & AR_PHY_ANT_DIV_MAIN_LNACONF) >>
1360                                   AR_PHY_ANT_DIV_MAIN_LNACONF_S;
1361         antconf->alt_lna_conf = (regval & AR_PHY_ANT_DIV_ALT_LNACONF) >>
1362                                  AR_PHY_ANT_DIV_ALT_LNACONF_S;
1363         antconf->fast_div_bias = (regval & AR_PHY_ANT_FAST_DIV_BIAS) >>
1364                                   AR_PHY_ANT_FAST_DIV_BIAS_S;
1365
1366         if (AR_SREV_9330_11(ah)) {
1367                 antconf->lna1_lna2_delta = -9;
1368                 antconf->div_group = 1;
1369         } else if (AR_SREV_9485(ah)) {
1370                 antconf->lna1_lna2_delta = -9;
1371                 antconf->div_group = 2;
1372         } else if (AR_SREV_9565(ah)) {
1373                 antconf->lna1_lna2_delta = -3;
1374                 antconf->div_group = 3;
1375         } else {
1376                 antconf->lna1_lna2_delta = -3;
1377                 antconf->div_group = 0;
1378         }
1379 }
1380
1381 static void ar9003_hw_antdiv_comb_conf_set(struct ath_hw *ah,
1382                                    struct ath_hw_antcomb_conf *antconf)
1383 {
1384         u32 regval;
1385
1386         regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1387         regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF |
1388                     AR_PHY_ANT_DIV_ALT_LNACONF |
1389                     AR_PHY_ANT_FAST_DIV_BIAS |
1390                     AR_PHY_ANT_DIV_MAIN_GAINTB |
1391                     AR_PHY_ANT_DIV_ALT_GAINTB);
1392         regval |= ((antconf->main_lna_conf << AR_PHY_ANT_DIV_MAIN_LNACONF_S)
1393                    & AR_PHY_ANT_DIV_MAIN_LNACONF);
1394         regval |= ((antconf->alt_lna_conf << AR_PHY_ANT_DIV_ALT_LNACONF_S)
1395                    & AR_PHY_ANT_DIV_ALT_LNACONF);
1396         regval |= ((antconf->fast_div_bias << AR_PHY_ANT_FAST_DIV_BIAS_S)
1397                    & AR_PHY_ANT_FAST_DIV_BIAS);
1398         regval |= ((antconf->main_gaintb << AR_PHY_ANT_DIV_MAIN_GAINTB_S)
1399                    & AR_PHY_ANT_DIV_MAIN_GAINTB);
1400         regval |= ((antconf->alt_gaintb << AR_PHY_ANT_DIV_ALT_GAINTB_S)
1401                    & AR_PHY_ANT_DIV_ALT_GAINTB);
1402
1403         REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1404 }
1405
1406 static void ar9003_hw_antctrl_shared_chain_lnadiv(struct ath_hw *ah,
1407                                                   bool enable)
1408 {
1409         u8 ant_div_ctl1;
1410         u32 regval;
1411
1412         if (!AR_SREV_9565(ah))
1413                 return;
1414
1415         ah->shared_chain_lnadiv = enable;
1416         ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
1417
1418         regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1419         regval &= (~AR_ANT_DIV_CTRL_ALL);
1420         regval |= (ant_div_ctl1 & 0x3f) << AR_ANT_DIV_CTRL_ALL_S;
1421         regval &= ~AR_PHY_ANT_DIV_LNADIV;
1422         regval |= ((ant_div_ctl1 >> 6) & 0x1) << AR_PHY_ANT_DIV_LNADIV_S;
1423
1424         if (enable)
1425                 regval |= AR_ANT_DIV_ENABLE;
1426
1427         REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1428
1429         regval = REG_READ(ah, AR_PHY_CCK_DETECT);
1430         regval &= ~AR_FAST_DIV_ENABLE;
1431         regval |= ((ant_div_ctl1 >> 7) & 0x1) << AR_FAST_DIV_ENABLE_S;
1432
1433         if (enable)
1434                 regval |= AR_FAST_DIV_ENABLE;
1435
1436         REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);
1437
1438         if (enable) {
1439                 REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1440                             (1 << AR_PHY_ANT_SW_RX_PROT_S));
1441                 if (ah->curchan && IS_CHAN_2GHZ(ah->curchan))
1442                         REG_SET_BIT(ah, AR_PHY_RESTART,
1443                                     AR_PHY_RESTART_ENABLE_DIV_M2FLAG);
1444                 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV,
1445                             AR_BTCOEX_WL_LNADIV_FORCE_ON);
1446         } else {
1447                 REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL, AR_ANT_DIV_ENABLE);
1448                 REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1449                             (1 << AR_PHY_ANT_SW_RX_PROT_S));
1450                 REG_CLR_BIT(ah, AR_PHY_CCK_DETECT, AR_FAST_DIV_ENABLE);
1451                 REG_CLR_BIT(ah, AR_BTCOEX_WL_LNADIV,
1452                             AR_BTCOEX_WL_LNADIV_FORCE_ON);
1453
1454                 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1455                 regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF |
1456                         AR_PHY_ANT_DIV_ALT_LNACONF |
1457                         AR_PHY_ANT_DIV_MAIN_GAINTB |
1458                         AR_PHY_ANT_DIV_ALT_GAINTB);
1459                 regval |= (AR_PHY_ANT_DIV_LNA1 << AR_PHY_ANT_DIV_MAIN_LNACONF_S);
1460                 regval |= (AR_PHY_ANT_DIV_LNA2 << AR_PHY_ANT_DIV_ALT_LNACONF_S);
1461                 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1462         }
1463 }
1464
1465 static int ar9003_hw_fast_chan_change(struct ath_hw *ah,
1466                                       struct ath9k_channel *chan,
1467                                       u8 *ini_reloaded)
1468 {
1469         unsigned int regWrites = 0;
1470         u32 modesIndex;
1471
1472         switch (chan->chanmode) {
1473         case CHANNEL_A:
1474         case CHANNEL_A_HT20:
1475                 modesIndex = 1;
1476                 break;
1477         case CHANNEL_A_HT40PLUS:
1478         case CHANNEL_A_HT40MINUS:
1479                 modesIndex = 2;
1480                 break;
1481         case CHANNEL_G:
1482         case CHANNEL_G_HT20:
1483         case CHANNEL_B:
1484                 modesIndex = 4;
1485                 break;
1486         case CHANNEL_G_HT40PLUS:
1487         case CHANNEL_G_HT40MINUS:
1488                 modesIndex = 3;
1489                 break;
1490
1491         default:
1492                 return -EINVAL;
1493         }
1494
1495         if (modesIndex == ah->modes_index) {
1496                 *ini_reloaded = false;
1497                 goto set_rfmode;
1498         }
1499
1500         ar9003_hw_prog_ini(ah, &ah->iniSOC[ATH_INI_POST], modesIndex);
1501         ar9003_hw_prog_ini(ah, &ah->iniMac[ATH_INI_POST], modesIndex);
1502         ar9003_hw_prog_ini(ah, &ah->iniBB[ATH_INI_POST], modesIndex);
1503         ar9003_hw_prog_ini(ah, &ah->iniRadio[ATH_INI_POST], modesIndex);
1504
1505         if (AR_SREV_9462_20(ah))
1506                 ar9003_hw_prog_ini(ah, &ah->ini_radio_post_sys2ant,
1507                                    modesIndex);
1508
1509         REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1510
1511         /*
1512          * For 5GHz channels requiring Fast Clock, apply
1513          * different modal values.
1514          */
1515         if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1516                 REG_WRITE_ARRAY(&ah->iniModesFastClock, modesIndex, regWrites);
1517
1518         if (AR_SREV_9565(ah))
1519                 REG_WRITE_ARRAY(&ah->iniModesFastClock, 1, regWrites);
1520
1521         REG_WRITE_ARRAY(&ah->iniAdditional, 1, regWrites);
1522
1523         ah->modes_index = modesIndex;
1524         *ini_reloaded = true;
1525
1526 set_rfmode:
1527         ar9003_hw_set_rfmode(ah, chan);
1528         return 0;
1529 }
1530
1531 static void ar9003_hw_spectral_scan_config(struct ath_hw *ah,
1532                                            struct ath_spec_scan *param)
1533 {
1534         u8 count;
1535
1536         if (!param->enabled) {
1537                 REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1538                             AR_PHY_SPECTRAL_SCAN_ENABLE);
1539                 return;
1540         }
1541
1542         REG_SET_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_FFT_ENA);
1543         REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENABLE);
1544
1545         /* on AR93xx and newer, count = 0 will make the the chip send
1546          * spectral samples endlessly. Check if this really was intended,
1547          * and fix otherwise.
1548          */
1549         count = param->count;
1550         if (param->endless)
1551                 count = 0;
1552         else if (param->count == 0)
1553                 count = 1;
1554
1555         if (param->short_repeat)
1556                 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1557                             AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT);
1558         else
1559                 REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1560                             AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT);
1561
1562         REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
1563                       AR_PHY_SPECTRAL_SCAN_COUNT, count);
1564         REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
1565                       AR_PHY_SPECTRAL_SCAN_PERIOD, param->period);
1566         REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
1567                       AR_PHY_SPECTRAL_SCAN_FFT_PERIOD, param->fft_period);
1568
1569         return;
1570 }
1571
1572 static void ar9003_hw_spectral_scan_trigger(struct ath_hw *ah)
1573 {
1574         /* Activate spectral scan */
1575         REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1576                     AR_PHY_SPECTRAL_SCAN_ACTIVE);
1577 }
1578
1579 static void ar9003_hw_spectral_scan_wait(struct ath_hw *ah)
1580 {
1581         struct ath_common *common = ath9k_hw_common(ah);
1582
1583         /* Poll for spectral scan complete */
1584         if (!ath9k_hw_wait(ah, AR_PHY_SPECTRAL_SCAN,
1585                            AR_PHY_SPECTRAL_SCAN_ACTIVE,
1586                            0, AH_WAIT_TIMEOUT)) {
1587                 ath_err(common, "spectral scan wait failed\n");
1588                 return;
1589         }
1590 }
1591
1592 void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
1593 {
1594         struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
1595         struct ath_hw_ops *ops = ath9k_hw_ops(ah);
1596         static const u32 ar9300_cca_regs[6] = {
1597                 AR_PHY_CCA_0,
1598                 AR_PHY_CCA_1,
1599                 AR_PHY_CCA_2,
1600                 AR_PHY_EXT_CCA,
1601                 AR_PHY_EXT_CCA_1,
1602                 AR_PHY_EXT_CCA_2,
1603         };
1604
1605         priv_ops->rf_set_freq = ar9003_hw_set_channel;
1606         priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate;
1607         priv_ops->compute_pll_control = ar9003_hw_compute_pll_control;
1608         priv_ops->set_channel_regs = ar9003_hw_set_channel_regs;
1609         priv_ops->init_bb = ar9003_hw_init_bb;
1610         priv_ops->process_ini = ar9003_hw_process_ini;
1611         priv_ops->set_rfmode = ar9003_hw_set_rfmode;
1612         priv_ops->mark_phy_inactive = ar9003_hw_mark_phy_inactive;
1613         priv_ops->set_delta_slope = ar9003_hw_set_delta_slope;
1614         priv_ops->rfbus_req = ar9003_hw_rfbus_req;
1615         priv_ops->rfbus_done = ar9003_hw_rfbus_done;
1616         priv_ops->ani_control = ar9003_hw_ani_control;
1617         priv_ops->do_getnf = ar9003_hw_do_getnf;
1618         priv_ops->ani_cache_ini_regs = ar9003_hw_ani_cache_ini_regs;
1619         priv_ops->set_radar_params = ar9003_hw_set_radar_params;
1620         priv_ops->fast_chan_change = ar9003_hw_fast_chan_change;
1621
1622         ops->antdiv_comb_conf_get = ar9003_hw_antdiv_comb_conf_get;
1623         ops->antdiv_comb_conf_set = ar9003_hw_antdiv_comb_conf_set;
1624         ops->antctrl_shared_chain_lnadiv = ar9003_hw_antctrl_shared_chain_lnadiv;
1625         ops->spectral_scan_config = ar9003_hw_spectral_scan_config;
1626         ops->spectral_scan_trigger = ar9003_hw_spectral_scan_trigger;
1627         ops->spectral_scan_wait = ar9003_hw_spectral_scan_wait;
1628
1629         ar9003_hw_set_nf_limits(ah);
1630         ar9003_hw_set_radar_conf(ah);
1631         memcpy(ah->nf_regs, ar9300_cca_regs, sizeof(ah->nf_regs));
1632 }
1633
1634 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah)
1635 {
1636         struct ath_common *common = ath9k_hw_common(ah);
1637         u32 idle_tmo_ms = ah->bb_watchdog_timeout_ms;
1638         u32 val, idle_count;
1639
1640         if (!idle_tmo_ms) {
1641                 /* disable IRQ, disable chip-reset for BB panic */
1642                 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
1643                           REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) &
1644                           ~(AR_PHY_WATCHDOG_RST_ENABLE |
1645                             AR_PHY_WATCHDOG_IRQ_ENABLE));
1646
1647                 /* disable watchdog in non-IDLE mode, disable in IDLE mode */
1648                 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
1649                           REG_READ(ah, AR_PHY_WATCHDOG_CTL_1) &
1650                           ~(AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
1651                             AR_PHY_WATCHDOG_IDLE_ENABLE));
1652
1653                 ath_dbg(common, RESET, "Disabled BB Watchdog\n");
1654                 return;
1655         }
1656
1657         /* enable IRQ, disable chip-reset for BB watchdog */
1658         val = REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) & AR_PHY_WATCHDOG_CNTL2_MASK;
1659         REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
1660                   (val | AR_PHY_WATCHDOG_IRQ_ENABLE) &
1661                   ~AR_PHY_WATCHDOG_RST_ENABLE);
1662
1663         /* bound limit to 10 secs */
1664         if (idle_tmo_ms > 10000)
1665                 idle_tmo_ms = 10000;
1666
1667         /*
1668          * The time unit for watchdog event is 2^15 44/88MHz cycles.
1669          *
1670          * For HT20 we have a time unit of 2^15/44 MHz = .74 ms per tick
1671          * For HT40 we have a time unit of 2^15/88 MHz = .37 ms per tick
1672          *
1673          * Given we use fast clock now in 5 GHz, these time units should
1674          * be common for both 2 GHz and 5 GHz.
1675          */
1676         idle_count = (100 * idle_tmo_ms) / 74;
1677         if (ah->curchan && IS_CHAN_HT40(ah->curchan))
1678                 idle_count = (100 * idle_tmo_ms) / 37;
1679
1680         /*
1681          * enable watchdog in non-IDLE mode, disable in IDLE mode,
1682          * set idle time-out.
1683          */
1684         REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
1685                   AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
1686                   AR_PHY_WATCHDOG_IDLE_MASK |
1687                   (AR_PHY_WATCHDOG_NON_IDLE_MASK & (idle_count << 2)));
1688
1689         ath_dbg(common, RESET, "Enabled BB Watchdog timeout (%u ms)\n",
1690                 idle_tmo_ms);
1691 }
1692
1693 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah)
1694 {
1695         /*
1696          * we want to avoid printing in ISR context so we save the
1697          * watchdog status to be printed later in bottom half context.
1698          */
1699         ah->bb_watchdog_last_status = REG_READ(ah, AR_PHY_WATCHDOG_STATUS);
1700
1701         /*
1702          * the watchdog timer should reset on status read but to be sure
1703          * sure we write 0 to the watchdog status bit.
1704          */
1705         REG_WRITE(ah, AR_PHY_WATCHDOG_STATUS,
1706                   ah->bb_watchdog_last_status & ~AR_PHY_WATCHDOG_STATUS_CLR);
1707 }
1708
1709 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah)
1710 {
1711         struct ath_common *common = ath9k_hw_common(ah);
1712         u32 status;
1713
1714         if (likely(!(common->debug_mask & ATH_DBG_RESET)))
1715                 return;
1716
1717         status = ah->bb_watchdog_last_status;
1718         ath_dbg(common, RESET,
1719                 "\n==== BB update: BB status=0x%08x ====\n", status);
1720         ath_dbg(common, RESET,
1721                 "** BB state: wd=%u det=%u rdar=%u rOFDM=%d rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n",
1722                 MS(status, AR_PHY_WATCHDOG_INFO),
1723                 MS(status, AR_PHY_WATCHDOG_DET_HANG),
1724                 MS(status, AR_PHY_WATCHDOG_RADAR_SM),
1725                 MS(status, AR_PHY_WATCHDOG_RX_OFDM_SM),
1726                 MS(status, AR_PHY_WATCHDOG_RX_CCK_SM),
1727                 MS(status, AR_PHY_WATCHDOG_TX_OFDM_SM),
1728                 MS(status, AR_PHY_WATCHDOG_TX_CCK_SM),
1729                 MS(status, AR_PHY_WATCHDOG_AGC_SM),
1730                 MS(status, AR_PHY_WATCHDOG_SRCH_SM));
1731
1732         ath_dbg(common, RESET, "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n",
1733                 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1),
1734                 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2));
1735         ath_dbg(common, RESET, "** BB mode: BB_gen_controls=0x%08x **\n",
1736                 REG_READ(ah, AR_PHY_GEN_CTRL));
1737
1738 #define PCT(_field) (common->cc_survey._field * 100 / common->cc_survey.cycles)
1739         if (common->cc_survey.cycles)
1740                 ath_dbg(common, RESET,
1741                         "** BB busy times: rx_clear=%d%%, rx_frame=%d%%, tx_frame=%d%% **\n",
1742                         PCT(rx_busy), PCT(rx_frame), PCT(tx_frame));
1743
1744         ath_dbg(common, RESET, "==== BB update: done ====\n\n");
1745 }
1746 EXPORT_SYMBOL(ar9003_hw_bb_watchdog_dbg_info);
1747
1748 void ar9003_hw_disable_phy_restart(struct ath_hw *ah)
1749 {
1750         u32 val;
1751
1752         /* While receiving unsupported rate frame rx state machine
1753          * gets into a state 0xb and if phy_restart happens in that
1754          * state, BB would go hang. If RXSM is in 0xb state after
1755          * first bb panic, ensure to disable the phy_restart.
1756          */
1757         if (!((MS(ah->bb_watchdog_last_status,
1758                   AR_PHY_WATCHDOG_RX_OFDM_SM) == 0xb) ||
1759             ah->bb_hang_rx_ofdm))
1760                 return;
1761
1762         ah->bb_hang_rx_ofdm = true;
1763         val = REG_READ(ah, AR_PHY_RESTART);
1764         val &= ~AR_PHY_RESTART_ENA;
1765
1766         REG_WRITE(ah, AR_PHY_RESTART, val);
1767 }
1768 EXPORT_SYMBOL(ar9003_hw_disable_phy_restart);