drivers/net/wireless/ath/ath9k/ar9003_phy.c

   1 /*
   2  * Copyright (c) 2010-2011 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/export.h>
  18 #include "hw.h"
  19 #include "ar9003_phy.h"
  20
  21 static const int firstep_table[] =
  22 /* level:  0   1   2   3   4   5   6   7   8  */
  23         { -4, -2,  0,  2,  4,  6,  8, 10, 12 }; /* lvl 0-8, default 2 */
  24
  25 static const int cycpwrThr1_table[] =
  26 /* level:  0   1   2   3   4   5   6   7   8  */
  27         { -6, -4, -2,  0,  2,  4,  6,  8 };     /* lvl 0-7, default 3 */
  28
  29 /*
  30  * register values to turn OFDM weak signal detection OFF
  31  */
  32 static const int m1ThreshLow_off = 127;
  33 static const int m2ThreshLow_off = 127;
  34 static const int m1Thresh_off = 127;
  35 static const int m2Thresh_off = 127;
  36 static const int m2CountThr_off =  31;
  37 static const int m2CountThrLow_off =  63;
  38 static const int m1ThreshLowExt_off = 127;
  39 static const int m2ThreshLowExt_off = 127;
  40 static const int m1ThreshExt_off = 127;
  41 static const int m2ThreshExt_off = 127;
  42
  43 /**
  44  * ar9003_hw_set_channel - set channel on single-chip device
  45  * @ah: atheros hardware structure
  46  * @chan:
  47  *
  48  * This is the function to change channel on single-chip devices, that is
  49  * for AR9300 family of chipsets.
  50  *
  51  * This function takes the channel value in MHz and sets
  52  * hardware channel value. Assumes writes have been enabled to analog bus.
  53  *
  54  * Actual Expression,
  55  *
  56  * For 2GHz channel,
  57  * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
  58  * (freq_ref = 40MHz)
  59  *
  60  * For 5GHz channel,
  61  * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
  62  * (freq_ref = 40MHz/(24>>amodeRefSel))
  63  *
  64  * For 5GHz channels which are 5MHz spaced,
  65  * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
  66  * (freq_ref = 40MHz)
  67  */
  68 static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
  69 {
  70         u16 bMode, fracMode = 0, aModeRefSel = 0;
  71         u32 freq, chan_frac, div, channelSel = 0, reg32 = 0;
  72         struct chan_centers centers;
  73         int loadSynthChannel;
  74
  75         ath9k_hw_get_channel_centers(ah, chan, &centers);
  76         freq = centers.synth_center;
  77
  78         if (freq < 4800) {     /* 2 GHz, fractional mode */
  79                 if (AR_SREV_9330(ah)) {
  80                         if (ah->is_clk_25mhz)
  81                                 div = 75;
  82                         else
  83                                 div = 120;
  84
  85                         channelSel = (freq * 4) / div;
  86                         chan_frac = (((freq * 4) % div) * 0x20000) / div;
  87                         channelSel = (channelSel << 17) | chan_frac;
  88                 } else if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
  89                         /*
  90                          * freq_ref = 40 / (refdiva >> amoderefsel);
  91                          * where refdiva=1 and amoderefsel=0
  92                          * ndiv = ((chan_mhz * 4) / 3) / freq_ref;
  93                          * chansel = int(ndiv), chanfrac = (ndiv - chansel) * 0x20000
  94                          */
  95                         channelSel = (freq * 4) / 120;
  96                         chan_frac = (((freq * 4) % 120) * 0x20000) / 120;
  97                         channelSel = (channelSel << 17) | chan_frac;
  98                 } else if (AR_SREV_9340(ah)) {
  99                         if (ah->is_clk_25mhz) {
 100                                 channelSel = (freq * 2) / 75;
 101                                 chan_frac = (((freq * 2) % 75) * 0x20000) / 75;
 102                                 channelSel = (channelSel << 17) | chan_frac;
 103                         } else {
 104                                 channelSel = CHANSEL_2G(freq) >> 1;
 105                         }
 106                 } else if (AR_SREV_9550(ah)) {
 107                         if (ah->is_clk_25mhz)
 108                                 div = 75;
 109                         else
 110                                 div = 120;
 111
 112                         channelSel = (freq * 4) / div;
 113                         chan_frac = (((freq * 4) % div) * 0x20000) / div;
 114                         channelSel = (channelSel << 17) | chan_frac;
 115                 } else {
 116                         channelSel = CHANSEL_2G(freq);
 117                 }
 118                 /* Set to 2G mode */
 119                 bMode = 1;
 120         } else {
 121                 if ((AR_SREV_9340(ah) || AR_SREV_9550(ah)) &&
 122                     ah->is_clk_25mhz) {
 123                         channelSel = freq / 75;
 124                         chan_frac = ((freq % 75) * 0x20000) / 75;
 125                         channelSel = (channelSel << 17) | chan_frac;
 126                 } else {
 127                         channelSel = CHANSEL_5G(freq);
 128                         /* Doubler is ON, so, divide channelSel by 2. */
 129                         channelSel >>= 1;
 130                 }
 131                 /* Set to 5G mode */
 132                 bMode = 0;
 133         }
 134
 135         /* Enable fractional mode for all channels */
 136         fracMode = 1;
 137         aModeRefSel = 0;
 138         loadSynthChannel = 0;
 139
 140         reg32 = (bMode << 29);
 141         REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
 142
 143         /* Enable Long shift Select for Synthesizer */
 144         REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH4,
 145                       AR_PHY_SYNTH4_LONG_SHIFT_SELECT, 1);
 146
 147         /* Program Synth. setting */
 148         reg32 = (channelSel << 2) | (fracMode << 30) |
 149                 (aModeRefSel << 28) | (loadSynthChannel << 31);
 150         REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
 151
 152         /* Toggle Load Synth channel bit */
 153         loadSynthChannel = 1;
 154         reg32 = (channelSel << 2) | (fracMode << 30) |
 155                 (aModeRefSel << 28) | (loadSynthChannel << 31);
 156         REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
 157
 158         ah->curchan = chan;
 159
 160         return 0;
 161 }
 162
 163 /**
 164  * ar9003_hw_spur_mitigate_mrc_cck - convert baseband spur frequency
 165  * @ah: atheros hardware structure
 166  * @chan:
 167  *
 168  * For single-chip solutions. Converts to baseband spur frequency given the
 169  * input channel frequency and compute register settings below.
 170  *
 171  * Spur mitigation for MRC CCK
 172  */
 173 static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah,
 174                                             struct ath9k_channel *chan)
 175 {
 176         static const u32 spur_freq[4] = { 2420, 2440, 2464, 2480 };
 177         int cur_bb_spur, negative = 0, cck_spur_freq;
 178         int i;
 179         int range, max_spur_cnts, synth_freq;
 180         u8 *spur_fbin_ptr = ar9003_get_spur_chan_ptr(ah, IS_CHAN_2GHZ(chan));
 181
 182         /*
 183          * Need to verify range +/- 10 MHz in control channel, otherwise spur
 184          * is out-of-band and can be ignored.
 185          */
 186
 187         if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
 188             AR_SREV_9550(ah)) {
 189                 if (spur_fbin_ptr[0] == 0) /* No spur */
 190                         return;
 191                 max_spur_cnts = 5;
 192                 if (IS_CHAN_HT40(chan)) {
 193                         range = 19;
 194                         if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
 195                                            AR_PHY_GC_DYN2040_PRI_CH) == 0)
 196                                 synth_freq = chan->channel + 10;
 197                         else
 198                                 synth_freq = chan->channel - 10;
 199                 } else {
 200                         range = 10;
 201                         synth_freq = chan->channel;
 202                 }
 203         } else {
 204                 range = AR_SREV_9462(ah) ? 5 : 10;
 205                 max_spur_cnts = 4;
 206                 synth_freq = chan->channel;
 207         }
 208
 209         for (i = 0; i < max_spur_cnts; i++) {
 210                 if (AR_SREV_9462(ah) && (i == 0 || i == 3))
 211                         continue;
 212
 213                 negative = 0;
 214                 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
 215                     AR_SREV_9550(ah))
 216                         cur_bb_spur = ath9k_hw_fbin2freq(spur_fbin_ptr[i],
 217                                                          IS_CHAN_2GHZ(chan));
 218                 else
 219                         cur_bb_spur = spur_freq[i];
 220
 221                 cur_bb_spur -= synth_freq;
 222                 if (cur_bb_spur < 0) {
 223                         negative = 1;
 224                         cur_bb_spur = -cur_bb_spur;
 225                 }
 226                 if (cur_bb_spur < range) {
 227                         cck_spur_freq = (int)((cur_bb_spur << 19) / 11);
 228
 229                         if (negative == 1)
 230                                 cck_spur_freq = -cck_spur_freq;
 231
 232                         cck_spur_freq = cck_spur_freq & 0xfffff;
 233
 234                         REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
 235                                       AR_PHY_AGC_CONTROL_YCOK_MAX, 0x7);
 236                         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 237                                       AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR, 0x7f);
 238                         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 239                                       AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE,
 240                                       0x2);
 241                         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 242                                       AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT,
 243                                       0x1);
 244                         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 245                                       AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ,
 246                                       cck_spur_freq);
 247
 248                         return;
 249                 }
 250         }
 251
 252         REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
 253                       AR_PHY_AGC_CONTROL_YCOK_MAX, 0x5);
 254         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 255                       AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 0x0);
 256         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 257                       AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0x0);
 258 }
 259
 260 /* Clean all spur register fields */
 261 static void ar9003_hw_spur_ofdm_clear(struct ath_hw *ah)
 262 {
 263         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 264                       AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0);
 265         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 266                       AR_PHY_TIMING11_SPUR_FREQ_SD, 0);
 267         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 268                       AR_PHY_TIMING11_SPUR_DELTA_PHASE, 0);
 269         REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
 270                       AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, 0);
 271         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 272                       AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0);
 273         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 274                       AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0);
 275         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 276                       AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0);
 277         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 278                       AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 0);
 279         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 280                       AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 0);
 281
 282         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 283                       AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0);
 284         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 285                       AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0);
 286         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 287                       AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0);
 288         REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
 289                       AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, 0);
 290         REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
 291                       AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, 0);
 292         REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
 293                       AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, 0);
 294         REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
 295                       AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0);
 296         REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
 297                       AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0);
 298         REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
 299                       AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0);
 300         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 301                       AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0);
 302 }
 303
 304 static void ar9003_hw_spur_ofdm(struct ath_hw *ah,
 305                                 int freq_offset,
 306                                 int spur_freq_sd,
 307                                 int spur_delta_phase,
 308                                 int spur_subchannel_sd,
 309                                 int range,
 310                                 int synth_freq)
 311 {
 312         int mask_index = 0;
 313
 314         /* OFDM Spur mitigation */
 315         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 316                  AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0x1);
 317         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 318                       AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd);
 319         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 320                       AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase);
 321         REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
 322                       AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, spur_subchannel_sd);
 323         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 324                       AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0x1);
 325
 326         if (!(AR_SREV_9565(ah) && range == 10 && synth_freq == 2437))
 327                 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 328                               AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0x1);
 329
 330         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 331                       AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0x1);
 332         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 333                       AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, 34);
 334         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 335                       AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 1);
 336
 337         if (!AR_SREV_9340(ah) &&
 338             REG_READ_FIELD(ah, AR_PHY_MODE,
 339                            AR_PHY_MODE_DYNAMIC) == 0x1)
 340                 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 341                               AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 1);
 342
 343         mask_index = (freq_offset << 4) / 5;
 344         if (mask_index < 0)
 345                 mask_index = mask_index - 1;
 346
 347         mask_index = mask_index & 0x7f;
 348
 349         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 350                       AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0x1);
 351         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 352                       AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0x1);
 353         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 354                       AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0x1);
 355         REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
 356                       AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, mask_index);
 357         REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
 358                       AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, mask_index);
 359         REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
 360                       AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, mask_index);
 361         REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
 362                       AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0xc);
 363         REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
 364                       AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0xc);
 365         REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
 366                       AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
 367         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 368                       AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0xff);
 369 }
 370
 371 static void ar9003_hw_spur_ofdm_9565(struct ath_hw *ah,
 372                                      int freq_offset)
 373 {
 374         int mask_index = 0;
 375
 376         mask_index = (freq_offset << 4) / 5;
 377         if (mask_index < 0)
 378                 mask_index = mask_index - 1;
 379
 380         mask_index = mask_index & 0x7f;
 381
 382         REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
 383                       AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B,
 384                       mask_index);
 385
 386         /* A == B */
 387         REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_B,
 388                       AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A,
 389                       mask_index);
 390
 391         REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
 392                       AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B,
 393                       mask_index);
 394         REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
 395                       AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_B, 0xe);
 396         REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
 397                       AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_B, 0xe);
 398
 399         /* A == B */
 400         REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_B,
 401                       AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
 402 }
 403
 404 static void ar9003_hw_spur_ofdm_work(struct ath_hw *ah,
 405                                      struct ath9k_channel *chan,
 406                                      int freq_offset,
 407                                      int range,
 408                                      int synth_freq)
 409 {
 410         int spur_freq_sd = 0;
 411         int spur_subchannel_sd = 0;
 412         int spur_delta_phase = 0;
 413
 414         if (IS_CHAN_HT40(chan)) {
 415                 if (freq_offset < 0) {
 416                         if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
 417                                            AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
 418                                 spur_subchannel_sd = 1;
 419                         else
 420                                 spur_subchannel_sd = 0;
 421
 422                         spur_freq_sd = ((freq_offset + 10) << 9) / 11;
 423
 424                 } else {
 425                         if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
 426                             AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
 427                                 spur_subchannel_sd = 0;
 428                         else
 429                                 spur_subchannel_sd = 1;
 430
 431                         spur_freq_sd = ((freq_offset - 10) << 9) / 11;
 432
 433                 }
 434
 435                 spur_delta_phase = (freq_offset << 17) / 5;
 436
 437         } else {
 438                 spur_subchannel_sd = 0;
 439                 spur_freq_sd = (freq_offset << 9) /11;
 440                 spur_delta_phase = (freq_offset << 18) / 5;
 441         }
 442
 443         spur_freq_sd = spur_freq_sd & 0x3ff;
 444         spur_delta_phase = spur_delta_phase & 0xfffff;
 445
 446         ar9003_hw_spur_ofdm(ah,
 447                             freq_offset,
 448                             spur_freq_sd,
 449                             spur_delta_phase,
 450                             spur_subchannel_sd,
 451                             range, synth_freq);
 452 }
 453
 454 /* Spur mitigation for OFDM */
 455 static void ar9003_hw_spur_mitigate_ofdm(struct ath_hw *ah,
 456                                          struct ath9k_channel *chan)
 457 {
 458         int synth_freq;
 459         int range = 10;
 460         int freq_offset = 0;
 461         int mode;
 462         u8* spurChansPtr;
 463         unsigned int i;
 464         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
 465
 466         if (IS_CHAN_5GHZ(chan)) {
 467                 spurChansPtr = &(eep->modalHeader5G.spurChans[0]);
 468                 mode = 0;
 469         }
 470         else {
 471                 spurChansPtr = &(eep->modalHeader2G.spurChans[0]);
 472                 mode = 1;
 473         }
 474
 475         if (spurChansPtr[0] == 0)
 476                 return; /* No spur in the mode */
 477
 478         if (IS_CHAN_HT40(chan)) {
 479                 range = 19;
 480                 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
 481                                    AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
 482                         synth_freq = chan->channel - 10;
 483                 else
 484                         synth_freq = chan->channel + 10;
 485         } else {
 486                 range = 10;
 487                 synth_freq = chan->channel;
 488         }
 489
 490         ar9003_hw_spur_ofdm_clear(ah);
 491
 492         for (i = 0; i < AR_EEPROM_MODAL_SPURS && spurChansPtr[i]; i++) {
 493                 freq_offset = ath9k_hw_fbin2freq(spurChansPtr[i], mode);
 494                 freq_offset -= synth_freq;
 495                 if (abs(freq_offset) < range) {
 496                         ar9003_hw_spur_ofdm_work(ah, chan, freq_offset,
 497                                                  range, synth_freq);
 498
 499                         if (AR_SREV_9565(ah) && (i < 4)) {
 500                                 freq_offset = ath9k_hw_fbin2freq(spurChansPtr[i + 1],
 501                                                                  mode);
 502                                 freq_offset -= synth_freq;
 503                                 if (abs(freq_offset) < range)
 504                                         ar9003_hw_spur_ofdm_9565(ah, freq_offset);
 505                         }
 506
 507                         break;
 508                 }
 509         }
 510 }
 511
 512 static void ar9003_hw_spur_mitigate(struct ath_hw *ah,
 513                                     struct ath9k_channel *chan)
 514 {
 515         if (!AR_SREV_9565(ah))
 516                 ar9003_hw_spur_mitigate_mrc_cck(ah, chan);
 517         ar9003_hw_spur_mitigate_ofdm(ah, chan);
 518 }
 519
 520 static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah,
 521                                          struct ath9k_channel *chan)
 522 {
 523         u32 pll;
 524
 525         pll = SM(0x5, AR_RTC_9300_PLL_REFDIV);
 526
 527         if (chan && IS_CHAN_HALF_RATE(chan))
 528                 pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL);
 529         else if (chan && IS_CHAN_QUARTER_RATE(chan))
 530                 pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL);
 531
 532         pll |= SM(0x2c, AR_RTC_9300_PLL_DIV);
 533
 534         return pll;
 535 }
 536
 537 static void ar9003_hw_set_channel_regs(struct ath_hw *ah,
 538                                        struct ath9k_channel *chan)
 539 {
 540         u32 phymode;
 541         u32 enableDacFifo = 0;
 542
 543         enableDacFifo =
 544                 (REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO);
 545
 546         /* Enable 11n HT, 20 MHz */
 547         phymode = AR_PHY_GC_HT_EN | AR_PHY_GC_SINGLE_HT_LTF1 |
 548                   AR_PHY_GC_SHORT_GI_40 | enableDacFifo;
 549
 550         /* Configure baseband for dynamic 20/40 operation */
 551         if (IS_CHAN_HT40(chan)) {
 552                 phymode |= AR_PHY_GC_DYN2040_EN;
 553                 /* Configure control (primary) channel at +-10MHz */
 554                 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
 555                     (chan->chanmode == CHANNEL_G_HT40PLUS))
 556                         phymode |= AR_PHY_GC_DYN2040_PRI_CH;
 557
 558         }
 559
 560         /* make sure we preserve INI settings */
 561         phymode |= REG_READ(ah, AR_PHY_GEN_CTRL);
 562         /* turn off Green Field detection for STA for now */
 563         phymode &= ~AR_PHY_GC_GF_DETECT_EN;
 564
 565         REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode);
 566
 567         /* Configure MAC for 20/40 operation */
 568         ath9k_hw_set11nmac2040(ah);
 569
 570         /* global transmit timeout (25 TUs default)*/
 571         REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
 572         /* carrier sense timeout */
 573         REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
 574 }
 575
 576 static void ar9003_hw_init_bb(struct ath_hw *ah,
 577                               struct ath9k_channel *chan)
 578 {
 579         u32 synthDelay;
 580
 581         /*
 582          * Wait for the frequency synth to settle (synth goes on
 583          * via AR_PHY_ACTIVE_EN).  Read the phy active delay register.
 584          * Value is in 100ns increments.
 585          */
 586         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
 587
 588         /* Activate the PHY (includes baseband activate + synthesizer on) */
 589         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
 590         ath9k_hw_synth_delay(ah, chan, synthDelay);
 591 }
 592
 593 void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx)
 594 {
 595         if (ah->caps.tx_chainmask == 5 || ah->caps.rx_chainmask == 5)
 596                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
 597                             AR_PHY_SWAP_ALT_CHAIN);
 598
 599         REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx);
 600         REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx);
 601
 602         if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7))
 603                 tx = 3;
 604
 605         REG_WRITE(ah, AR_SELFGEN_MASK, tx);
 606 }
 607
 608 /*
 609  * Override INI values with chip specific configuration.
 610  */
 611 static void ar9003_hw_override_ini(struct ath_hw *ah)
 612 {
 613         u32 val;
 614
 615         /*
 616          * Set the RX_ABORT and RX_DIS and clear it only after
 617          * RXE is set for MAC. This prevents frames with
 618          * corrupted descriptor status.
 619          */
 620         REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
 621
 622         /*
 623          * For AR9280 and above, there is a new feature that allows
 624          * Multicast search based on both MAC Address and Key ID. By default,
 625          * this feature is enabled. But since the driver is not using this
 626          * feature, we switch it off; otherwise multicast search based on
 627          * MAC addr only will fail.
 628          */
 629         val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE);
 630         val |= AR_AGG_WEP_ENABLE_FIX |
 631                AR_AGG_WEP_ENABLE |
 632                AR_PCU_MISC_MODE2_CFP_IGNORE;
 633         REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
 634
 635         REG_SET_BIT(ah, AR_PHY_CCK_DETECT,
 636                     AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
 637
 638         if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
 639                 REG_WRITE(ah, AR_GLB_SWREG_DISCONT_MODE,
 640                           AR_GLB_SWREG_DISCONT_EN_BT_WLAN);
 641
 642                 if (REG_READ_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_0,
 643                                    AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL))
 644                         ah->enabled_cals |= TX_IQ_CAL;
 645                 else
 646                         ah->enabled_cals &= ~TX_IQ_CAL;
 647
 648                 if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE)
 649                         ah->enabled_cals |= TX_CL_CAL;
 650                 else
 651                         ah->enabled_cals &= ~TX_CL_CAL;
 652         }
 653 }
 654
 655 static void ar9003_hw_prog_ini(struct ath_hw *ah,
 656                                struct ar5416IniArray *iniArr,
 657                                int column)
 658 {
 659         unsigned int i, regWrites = 0;
 660
 661         /* New INI format: Array may be undefined (pre, core, post arrays) */
 662         if (!iniArr->ia_array)
 663                 return;
 664
 665         /*
 666          * New INI format: Pre, core, and post arrays for a given subsystem
 667          * may be modal (> 2 columns) or non-modal (2 columns). Determine if
 668          * the array is non-modal and force the column to 1.
 669          */
 670         if (column >= iniArr->ia_columns)
 671                 column = 1;
 672
 673         for (i = 0; i < iniArr->ia_rows; i++) {
 674                 u32 reg = INI_RA(iniArr, i, 0);
 675                 u32 val = INI_RA(iniArr, i, column);
 676
 677                 REG_WRITE(ah, reg, val);
 678
 679                 DO_DELAY(regWrites);
 680         }
 681 }
 682
 683 static int ar9550_hw_get_modes_txgain_index(struct ath_hw *ah,
 684                                             struct ath9k_channel *chan)
 685 {
 686         int ret;
 687
 688         switch (chan->chanmode) {
 689         case CHANNEL_A:
 690         case CHANNEL_A_HT20:
 691                 if (chan->channel <= 5350)
 692                         ret = 1;
 693                 else if ((chan->channel > 5350) && (chan->channel <= 5600))
 694                         ret = 3;
 695                 else
 696                         ret = 5;
 697                 break;
 698
 699         case CHANNEL_A_HT40PLUS:
 700         case CHANNEL_A_HT40MINUS:
 701                 if (chan->channel <= 5350)
 702                         ret = 2;
 703                 else if ((chan->channel > 5350) && (chan->channel <= 5600))
 704                         ret = 4;
 705                 else
 706                         ret = 6;
 707                 break;
 708
 709         case CHANNEL_G:
 710         case CHANNEL_G_HT20:
 711         case CHANNEL_B:
 712                 ret = 8;
 713                 break;
 714
 715         case CHANNEL_G_HT40PLUS:
 716         case CHANNEL_G_HT40MINUS:
 717                 ret = 7;
 718                 break;
 719
 720         default:
 721                 ret = -EINVAL;
 722         }
 723
 724         return ret;
 725 }
 726
 727 static int ar9003_hw_process_ini(struct ath_hw *ah,
 728                                  struct ath9k_channel *chan)
 729 {
 730         unsigned int regWrites = 0, i;
 731         u32 modesIndex;
 732
 733         switch (chan->chanmode) {
 734         case CHANNEL_A:
 735         case CHANNEL_A_HT20:
 736                 modesIndex = 1;
 737                 break;
 738         case CHANNEL_A_HT40PLUS:
 739         case CHANNEL_A_HT40MINUS:
 740                 modesIndex = 2;
 741                 break;
 742         case CHANNEL_G:
 743         case CHANNEL_G_HT20:
 744         case CHANNEL_B:
 745                 modesIndex = 4;
 746                 break;
 747         case CHANNEL_G_HT40PLUS:
 748         case CHANNEL_G_HT40MINUS:
 749                 modesIndex = 3;
 750                 break;
 751
 752         default:
 753                 return -EINVAL;
 754         }
 755
 756         /*
 757          * SOC, MAC, BB, RADIO initvals.
 758          */
 759         for (i = 0; i < ATH_INI_NUM_SPLIT; i++) {
 760                 ar9003_hw_prog_ini(ah, &ah->iniSOC[i], modesIndex);
 761                 ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex);
 762                 ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex);
 763                 ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex);
 764                 if (i == ATH_INI_POST && AR_SREV_9462_20_OR_LATER(ah))
 765                         ar9003_hw_prog_ini(ah,
 766                                            &ah->ini_radio_post_sys2ant,
 767                                            modesIndex);
 768         }
 769
 770         /*
 771          * RXGAIN initvals.
 772          */
 773         REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites);
 774
 775         if (AR_SREV_9462_20_OR_LATER(ah)) {
 776                 /*
 777                  * CUS217 mix LNA mode.
 778                  */
 779                 if (ar9003_hw_get_rx_gain_idx(ah) == 2) {
 780                         REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_core,
 781                                         1, regWrites);
 782                         REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_postamble,
 783                                         modesIndex, regWrites);
 784                 }
 785
 786                 /*
 787                  * 5G-XLNA
 788                  */
 789                 if ((ar9003_hw_get_rx_gain_idx(ah) == 2) ||
 790                     (ar9003_hw_get_rx_gain_idx(ah) == 3)) {
 791                         REG_WRITE_ARRAY(&ah->ini_modes_rxgain_5g_xlna,
 792                                         modesIndex, regWrites);
 793                 }
 794         }
 795
 796         if (AR_SREV_9550(ah))
 797                 REG_WRITE_ARRAY(&ah->ini_modes_rx_gain_bounds, modesIndex,
 798                                 regWrites);
 799
 800         /*
 801          * TXGAIN initvals.
 802          */
 803         if (AR_SREV_9550(ah)) {
 804                 int modes_txgain_index;
 805
 806                 modes_txgain_index = ar9550_hw_get_modes_txgain_index(ah, chan);
 807                 if (modes_txgain_index < 0)
 808                         return -EINVAL;
 809
 810                 REG_WRITE_ARRAY(&ah->iniModesTxGain, modes_txgain_index,
 811                                 regWrites);
 812         } else {
 813                 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
 814         }
 815
 816         /*
 817          * For 5GHz channels requiring Fast Clock, apply
 818          * different modal values.
 819          */
 820         if (IS_CHAN_A_FAST_CLOCK(ah, chan))
 821                 REG_WRITE_ARRAY(&ah->iniModesFastClock,
 822                                 modesIndex, regWrites);
 823
 824         /*
 825          * Clock frequency initvals.
 826          */
 827         REG_WRITE_ARRAY(&ah->iniAdditional, 1, regWrites);
 828
 829         /*
 830          * JAPAN regulatory.
 831          */
 832         if (chan->channel == 2484)
 833                 ar9003_hw_prog_ini(ah, &ah->iniCckfirJapan2484, 1);
 834
 835         ah->modes_index = modesIndex;
 836         ar9003_hw_override_ini(ah);
 837         ar9003_hw_set_channel_regs(ah, chan);
 838         ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
 839         ath9k_hw_apply_txpower(ah, chan, false);
 840
 841         return 0;
 842 }
 843
 844 static void ar9003_hw_set_rfmode(struct ath_hw *ah,
 845                                  struct ath9k_channel *chan)
 846 {
 847         u32 rfMode = 0;
 848
 849         if (chan == NULL)
 850                 return;
 851
 852         rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
 853                 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
 854
 855         if (IS_CHAN_A_FAST_CLOCK(ah, chan))
 856                 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
 857         if (IS_CHAN_QUARTER_RATE(chan))
 858                 rfMode |= AR_PHY_MODE_QUARTER;
 859         if (IS_CHAN_HALF_RATE(chan))
 860                 rfMode |= AR_PHY_MODE_HALF;
 861
 862         if (rfMode & (AR_PHY_MODE_QUARTER | AR_PHY_MODE_HALF))
 863                 REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL,
 864                               AR_PHY_FRAME_CTL_CF_OVERLAP_WINDOW, 3);
 865
 866         REG_WRITE(ah, AR_PHY_MODE, rfMode);
 867 }
 868
 869 static void ar9003_hw_mark_phy_inactive(struct ath_hw *ah)
 870 {
 871         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
 872 }
 873
 874 static void ar9003_hw_set_delta_slope(struct ath_hw *ah,
 875                                       struct ath9k_channel *chan)
 876 {
 877         u32 coef_scaled, ds_coef_exp, ds_coef_man;
 878         u32 clockMhzScaled = 0x64000000;
 879         struct chan_centers centers;
 880
 881         /*
 882          * half and quarter rate can divide the scaled clock by 2 or 4
 883          * scale for selected channel bandwidth
 884          */
 885         if (IS_CHAN_HALF_RATE(chan))
 886                 clockMhzScaled = clockMhzScaled >> 1;
 887         else if (IS_CHAN_QUARTER_RATE(chan))
 888                 clockMhzScaled = clockMhzScaled >> 2;
 889
 890         /*
 891          * ALGO -> coef = 1e8/fcarrier*fclock/40;
 892          * scaled coef to provide precision for this floating calculation
 893          */
 894         ath9k_hw_get_channel_centers(ah, chan, &centers);
 895         coef_scaled = clockMhzScaled / centers.synth_center;
 896
 897         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
 898                                       &ds_coef_exp);
 899
 900         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
 901                       AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
 902         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
 903                       AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
 904
 905         /*
 906          * For Short GI,
 907          * scaled coeff is 9/10 that of normal coeff
 908          */
 909         coef_scaled = (9 * coef_scaled) / 10;
 910
 911         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
 912                                       &ds_coef_exp);
 913
 914         /* for short gi */
 915         REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
 916                       AR_PHY_SGI_DSC_MAN, ds_coef_man);
 917         REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
 918                       AR_PHY_SGI_DSC_EXP, ds_coef_exp);
 919 }
 920
 921 static bool ar9003_hw_rfbus_req(struct ath_hw *ah)
 922 {
 923         REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
 924         return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
 925                              AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT);
 926 }
 927
 928 /*
 929  * Wait for the frequency synth to settle (synth goes on via PHY_ACTIVE_EN).
 930  * Read the phy active delay register. Value is in 100ns increments.
 931  */
 932 static void ar9003_hw_rfbus_done(struct ath_hw *ah)
 933 {
 934         u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
 935
 936         ath9k_hw_synth_delay(ah, ah->curchan, synthDelay);
 937
 938         REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
 939 }
 940
 941 static bool ar9003_hw_ani_control(struct ath_hw *ah,
 942                                   enum ath9k_ani_cmd cmd, int param)
 943 {
 944         struct ath_common *common = ath9k_hw_common(ah);
 945         struct ath9k_channel *chan = ah->curchan;
 946         struct ar5416AniState *aniState = &ah->ani;
 947         int m1ThreshLow, m2ThreshLow;
 948         int m1Thresh, m2Thresh;
 949         int m2CountThr, m2CountThrLow;
 950         int m1ThreshLowExt, m2ThreshLowExt;
 951         int m1ThreshExt, m2ThreshExt;
 952         s32 value, value2;
 953
 954         switch (cmd & ah->ani_function) {
 955         case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
 956                 /*
 957                  * on == 1 means ofdm weak signal detection is ON
 958                  * on == 1 is the default, for less noise immunity
 959                  *
 960                  * on == 0 means ofdm weak signal detection is OFF
 961                  * on == 0 means more noise imm
 962                  */
 963                 u32 on = param ? 1 : 0;
 964
 965                 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
 966                         goto skip_ws_det;
 967
 968                 m1ThreshLow = on ?
 969                         aniState->iniDef.m1ThreshLow : m1ThreshLow_off;
 970                 m2ThreshLow = on ?
 971                         aniState->iniDef.m2ThreshLow : m2ThreshLow_off;
 972                 m1Thresh = on ?
 973                         aniState->iniDef.m1Thresh : m1Thresh_off;
 974                 m2Thresh = on ?
 975                         aniState->iniDef.m2Thresh : m2Thresh_off;
 976                 m2CountThr = on ?
 977                         aniState->iniDef.m2CountThr : m2CountThr_off;
 978                 m2CountThrLow = on ?
 979                         aniState->iniDef.m2CountThrLow : m2CountThrLow_off;
 980                 m1ThreshLowExt = on ?
 981                         aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off;
 982                 m2ThreshLowExt = on ?
 983                         aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off;
 984                 m1ThreshExt = on ?
 985                         aniState->iniDef.m1ThreshExt : m1ThreshExt_off;
 986                 m2ThreshExt = on ?
 987                         aniState->iniDef.m2ThreshExt : m2ThreshExt_off;
 988
 989                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
 990                               AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
 991                               m1ThreshLow);
 992                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
 993                               AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
 994                               m2ThreshLow);
 995                 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
 996                               AR_PHY_SFCORR_M1_THRESH,
 997                               m1Thresh);
 998                 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
 999                               AR_PHY_SFCORR_M2_THRESH,
1000                               m2Thresh);
1001                 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1002                               AR_PHY_SFCORR_M2COUNT_THR,
1003                               m2CountThr);
1004                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1005                               AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
1006                               m2CountThrLow);
1007                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1008                               AR_PHY_SFCORR_EXT_M1_THRESH_LOW,
1009                               m1ThreshLowExt);
1010                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1011                               AR_PHY_SFCORR_EXT_M2_THRESH_LOW,
1012                               m2ThreshLowExt);
1013                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1014                               AR_PHY_SFCORR_EXT_M1_THRESH,
1015                               m1ThreshExt);
1016                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1017                               AR_PHY_SFCORR_EXT_M2_THRESH,
1018                               m2ThreshExt);
1019 skip_ws_det:
1020                 if (on)
1021                         REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
1022                                     AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1023                 else
1024                         REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
1025                                     AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1026
1027                 if (on != aniState->ofdmWeakSigDetect) {
1028                         ath_dbg(common, ANI,
1029                                 "** ch %d: ofdm weak signal: %s=>%s\n",
1030                                 chan->channel,
1031                                 aniState->ofdmWeakSigDetect ?
1032                                 "on" : "off",
1033                                 on ? "on" : "off");
1034                         if (on)
1035                                 ah->stats.ast_ani_ofdmon++;
1036                         else
1037                                 ah->stats.ast_ani_ofdmoff++;
1038                         aniState->ofdmWeakSigDetect = on;
1039                 }
1040                 break;
1041         }
1042         case ATH9K_ANI_FIRSTEP_LEVEL:{
1043                 u32 level = param;
1044
1045                 if (level >= ARRAY_SIZE(firstep_table)) {
1046                         ath_dbg(common, ANI,
1047                                 "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%u > %zu)\n",
1048                                 level, ARRAY_SIZE(firstep_table));
1049                         return false;
1050                 }
1051
1052                 /*
1053                  * make register setting relative to default
1054                  * from INI file & cap value
1055                  */
1056                 value = firstep_table[level] -
1057                         firstep_table[ATH9K_ANI_FIRSTEP_LVL] +
1058                         aniState->iniDef.firstep;
1059                 if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN)
1060                         value = ATH9K_SIG_FIRSTEP_SETTING_MIN;
1061                 if (value > ATH9K_SIG_FIRSTEP_SETTING_MAX)
1062                         value = ATH9K_SIG_FIRSTEP_SETTING_MAX;
1063                 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
1064                               AR_PHY_FIND_SIG_FIRSTEP,
1065                               value);
1066                 /*
1067                  * we need to set first step low register too
1068                  * make register setting relative to default
1069                  * from INI file & cap value
1070                  */
1071                 value2 = firstep_table[level] -
1072                          firstep_table[ATH9K_ANI_FIRSTEP_LVL] +
1073                          aniState->iniDef.firstepLow;
1074                 if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN)
1075                         value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN;
1076                 if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX)
1077                         value2 = ATH9K_SIG_FIRSTEP_SETTING_MAX;
1078
1079                 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW,
1080                               AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW, value2);
1081
1082                 if (level != aniState->firstepLevel) {
1083                         ath_dbg(common, ANI,
1084                                 "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n",
1085                                 chan->channel,
1086                                 aniState->firstepLevel,
1087                                 level,
1088                                 ATH9K_ANI_FIRSTEP_LVL,
1089                                 value,
1090                                 aniState->iniDef.firstep);
1091                         ath_dbg(common, ANI,
1092                                 "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n",
1093                                 chan->channel,
1094                                 aniState->firstepLevel,
1095                                 level,
1096                                 ATH9K_ANI_FIRSTEP_LVL,
1097                                 value2,
1098                                 aniState->iniDef.firstepLow);
1099                         if (level > aniState->firstepLevel)
1100                                 ah->stats.ast_ani_stepup++;
1101                         else if (level < aniState->firstepLevel)
1102                                 ah->stats.ast_ani_stepdown++;
1103                         aniState->firstepLevel = level;
1104                 }
1105                 break;
1106         }
1107         case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
1108                 u32 level = param;
1109
1110                 if (level >= ARRAY_SIZE(cycpwrThr1_table)) {
1111                         ath_dbg(common, ANI,
1112                                 "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%u > %zu)\n",
1113                                 level, ARRAY_SIZE(cycpwrThr1_table));
1114                         return false;
1115                 }
1116                 /*
1117                  * make register setting relative to default
1118                  * from INI file & cap value
1119                  */
1120                 value = cycpwrThr1_table[level] -
1121                         cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] +
1122                         aniState->iniDef.cycpwrThr1;
1123                 if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
1124                         value = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
1125                 if (value > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
1126                         value = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
1127                 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
1128                               AR_PHY_TIMING5_CYCPWR_THR1,
1129                               value);
1130
1131                 /*
1132                  * set AR_PHY_EXT_CCA for extension channel
1133                  * make register setting relative to default
1134                  * from INI file & cap value
1135                  */
1136                 value2 = cycpwrThr1_table[level] -
1137                          cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] +
1138                          aniState->iniDef.cycpwrThr1Ext;
1139                 if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
1140                         value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
1141                 if (value2 > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
1142                         value2 = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
1143                 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
1144                               AR_PHY_EXT_CYCPWR_THR1, value2);
1145
1146                 if (level != aniState->spurImmunityLevel) {
1147                         ath_dbg(common, ANI,
1148                                 "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n",
1149                                 chan->channel,
1150                                 aniState->spurImmunityLevel,
1151                                 level,
1152                                 ATH9K_ANI_SPUR_IMMUNE_LVL,
1153                                 value,
1154                                 aniState->iniDef.cycpwrThr1);
1155                         ath_dbg(common, ANI,
1156                                 "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n",
1157                                 chan->channel,
1158                                 aniState->spurImmunityLevel,
1159                                 level,
1160                                 ATH9K_ANI_SPUR_IMMUNE_LVL,
1161                                 value2,
1162                                 aniState->iniDef.cycpwrThr1Ext);
1163                         if (level > aniState->spurImmunityLevel)
1164                                 ah->stats.ast_ani_spurup++;
1165                         else if (level < aniState->spurImmunityLevel)
1166                                 ah->stats.ast_ani_spurdown++;
1167                         aniState->spurImmunityLevel = level;
1168                 }
1169                 break;
1170         }
1171         case ATH9K_ANI_MRC_CCK:{
1172                 /*
1173                  * is_on == 1 means MRC CCK ON (default, less noise imm)
1174                  * is_on == 0 means MRC CCK is OFF (more noise imm)
1175                  */
1176                 bool is_on = param ? 1 : 0;
1177
1178                 if (ah->caps.rx_chainmask == 1)
1179                         break;
1180
1181                 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
1182                               AR_PHY_MRC_CCK_ENABLE, is_on);
1183                 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
1184                               AR_PHY_MRC_CCK_MUX_REG, is_on);
1185                 if (is_on != aniState->mrcCCK) {
1186                         ath_dbg(common, ANI, "** ch %d: MRC CCK: %s=>%s\n",
1187                                 chan->channel,
1188                                 aniState->mrcCCK ? "on" : "off",
1189                                 is_on ? "on" : "off");
1190                 if (is_on)
1191                         ah->stats.ast_ani_ccklow++;
1192                 else
1193                         ah->stats.ast_ani_cckhigh++;
1194                 aniState->mrcCCK = is_on;
1195                 }
1196         break;
1197         }
1198         default:
1199                 ath_dbg(common, ANI, "invalid cmd %u\n", cmd);
1200                 return false;
1201         }
1202
1203         ath_dbg(common, ANI,
1204                 "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n",
1205                 aniState->spurImmunityLevel,
1206                 aniState->ofdmWeakSigDetect ? "on" : "off",
1207                 aniState->firstepLevel,
1208                 aniState->mrcCCK ? "on" : "off",
1209                 aniState->listenTime,
1210                 aniState->ofdmPhyErrCount,
1211                 aniState->cckPhyErrCount);
1212         return true;
1213 }
1214
1215 static void ar9003_hw_do_getnf(struct ath_hw *ah,
1216                               int16_t nfarray[NUM_NF_READINGS])
1217 {
1218 #define AR_PHY_CH_MINCCA_PWR    0x1FF00000
1219 #define AR_PHY_CH_MINCCA_PWR_S  20
1220 #define AR_PHY_CH_EXT_MINCCA_PWR 0x01FF0000
1221 #define AR_PHY_CH_EXT_MINCCA_PWR_S 16
1222
1223         int16_t nf;
1224         int i;
1225
1226         for (i = 0; i < AR9300_MAX_CHAINS; i++) {
1227                 if (ah->rxchainmask & BIT(i)) {
1228                         nf = MS(REG_READ(ah, ah->nf_regs[i]),
1229                                          AR_PHY_CH_MINCCA_PWR);
1230                         nfarray[i] = sign_extend32(nf, 8);
1231
1232                         if (IS_CHAN_HT40(ah->curchan)) {
1233                                 u8 ext_idx = AR9300_MAX_CHAINS + i;
1234
1235                                 nf = MS(REG_READ(ah, ah->nf_regs[ext_idx]),
1236                                                  AR_PHY_CH_EXT_MINCCA_PWR);
1237                                 nfarray[ext_idx] = sign_extend32(nf, 8);
1238                         }
1239                 }
1240         }
1241 }
1242
1243 static void ar9003_hw_set_nf_limits(struct ath_hw *ah)
1244 {
1245         ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ;
1246         ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ;
1247         ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9300_2GHZ;
1248         ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ;
1249         ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ;
1250         ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9300_5GHZ;
1251
1252         if (AR_SREV_9330(ah))
1253                 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9330_2GHZ;
1254
1255         if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
1256                 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_2GHZ;
1257                 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9462_2GHZ;
1258                 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_5GHZ;
1259                 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9462_5GHZ;
1260         }
1261 }
1262
1263 /*
1264  * Initialize the ANI register values with default (ini) values.
1265  * This routine is called during a (full) hardware reset after
1266  * all the registers are initialised from the INI.
1267  */
1268 static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah)
1269 {
1270         struct ar5416AniState *aniState;
1271         struct ath_common *common = ath9k_hw_common(ah);
1272         struct ath9k_channel *chan = ah->curchan;
1273         struct ath9k_ani_default *iniDef;
1274         u32 val;
1275
1276         aniState = &ah->ani;
1277         iniDef = &aniState->iniDef;
1278
1279         ath_dbg(common, ANI, "ver %d.%d opmode %u chan %d Mhz/0x%x\n",
1280                 ah->hw_version.macVersion,
1281                 ah->hw_version.macRev,
1282                 ah->opmode,
1283                 chan->channel,
1284                 chan->channelFlags);
1285
1286         val = REG_READ(ah, AR_PHY_SFCORR);
1287         iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
1288         iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH);
1289         iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR);
1290
1291         val = REG_READ(ah, AR_PHY_SFCORR_LOW);
1292         iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW);
1293         iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW);
1294         iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW);
1295
1296         val = REG_READ(ah, AR_PHY_SFCORR_EXT);
1297         iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH);
1298         iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH);
1299         iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW);
1300         iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW);
1301         iniDef->firstep = REG_READ_FIELD(ah,
1302                                          AR_PHY_FIND_SIG,
1303                                          AR_PHY_FIND_SIG_FIRSTEP);
1304         iniDef->firstepLow = REG_READ_FIELD(ah,
1305                                             AR_PHY_FIND_SIG_LOW,
1306                                             AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW);
1307         iniDef->cycpwrThr1 = REG_READ_FIELD(ah,
1308                                             AR_PHY_TIMING5,
1309                                             AR_PHY_TIMING5_CYCPWR_THR1);
1310         iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah,
1311                                                AR_PHY_EXT_CCA,
1312                                                AR_PHY_EXT_CYCPWR_THR1);
1313
1314         /* these levels just got reset to defaults by the INI */
1315         aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL;
1316         aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL;
1317         aniState->ofdmWeakSigDetect = true;
1318         aniState->mrcCCK = true;
1319 }
1320
1321 static void ar9003_hw_set_radar_params(struct ath_hw *ah,
1322                                        struct ath_hw_radar_conf *conf)
1323 {
1324         u32 radar_0 = 0, radar_1 = 0;
1325
1326         if (!conf) {
1327                 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA);
1328                 return;
1329         }
1330
1331         radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA;
1332         radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR);
1333         radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI);
1334         radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT);
1335         radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI);
1336         radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND);
1337
1338         radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI;
1339         radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK;
1340         radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN);
1341         radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH);
1342         radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH);
1343
1344         REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);
1345         REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);
1346         if (conf->ext_channel)
1347                 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1348         else
1349                 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1350 }
1351
1352 static void ar9003_hw_set_radar_conf(struct ath_hw *ah)
1353 {
1354         struct ath_hw_radar_conf *conf = &ah->radar_conf;
1355
1356         conf->fir_power = -28;
1357         conf->radar_rssi = 0;
1358         conf->pulse_height = 10;
1359         conf->pulse_rssi = 24;
1360         conf->pulse_inband = 8;
1361         conf->pulse_maxlen = 255;
1362         conf->pulse_inband_step = 12;
1363         conf->radar_inband = 8;
1364 }
1365
1366 static void ar9003_hw_antdiv_comb_conf_get(struct ath_hw *ah,
1367                                            struct ath_hw_antcomb_conf *antconf)
1368 {
1369         u32 regval;
1370
1371         regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1372         antconf->main_lna_conf = (regval & AR_PHY_ANT_DIV_MAIN_LNACONF) >>
1373                                   AR_PHY_ANT_DIV_MAIN_LNACONF_S;
1374         antconf->alt_lna_conf = (regval & AR_PHY_ANT_DIV_ALT_LNACONF) >>
1375                                  AR_PHY_ANT_DIV_ALT_LNACONF_S;
1376         antconf->fast_div_bias = (regval & AR_PHY_ANT_FAST_DIV_BIAS) >>
1377                                   AR_PHY_ANT_FAST_DIV_BIAS_S;
1378
1379         if (AR_SREV_9330_11(ah)) {
1380                 antconf->lna1_lna2_switch_delta = -1;
1381                 antconf->lna1_lna2_delta = -9;
1382                 antconf->div_group = 1;
1383         } else if (AR_SREV_9485(ah)) {
1384                 antconf->lna1_lna2_switch_delta = -1;
1385                 antconf->lna1_lna2_delta = -9;
1386                 antconf->div_group = 2;
1387         } else if (AR_SREV_9565(ah)) {
1388                 antconf->lna1_lna2_switch_delta = 3;
1389                 antconf->lna1_lna2_delta = -9;
1390                 antconf->div_group = 3;
1391         } else {
1392                 antconf->lna1_lna2_switch_delta = -1;
1393                 antconf->lna1_lna2_delta = -3;
1394                 antconf->div_group = 0;
1395         }
1396 }
1397
1398 static void ar9003_hw_antdiv_comb_conf_set(struct ath_hw *ah,
1399                                    struct ath_hw_antcomb_conf *antconf)
1400 {
1401         u32 regval;
1402
1403         regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1404         regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF |
1405                     AR_PHY_ANT_DIV_ALT_LNACONF |
1406                     AR_PHY_ANT_FAST_DIV_BIAS |
1407                     AR_PHY_ANT_DIV_MAIN_GAINTB |
1408                     AR_PHY_ANT_DIV_ALT_GAINTB);
1409         regval |= ((antconf->main_lna_conf << AR_PHY_ANT_DIV_MAIN_LNACONF_S)
1410                    & AR_PHY_ANT_DIV_MAIN_LNACONF);
1411         regval |= ((antconf->alt_lna_conf << AR_PHY_ANT_DIV_ALT_LNACONF_S)
1412                    & AR_PHY_ANT_DIV_ALT_LNACONF);
1413         regval |= ((antconf->fast_div_bias << AR_PHY_ANT_FAST_DIV_BIAS_S)
1414                    & AR_PHY_ANT_FAST_DIV_BIAS);
1415         regval |= ((antconf->main_gaintb << AR_PHY_ANT_DIV_MAIN_GAINTB_S)
1416                    & AR_PHY_ANT_DIV_MAIN_GAINTB);
1417         regval |= ((antconf->alt_gaintb << AR_PHY_ANT_DIV_ALT_GAINTB_S)
1418                    & AR_PHY_ANT_DIV_ALT_GAINTB);
1419
1420         REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1421 }
1422
1423 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
1424
1425 static void ar9003_hw_set_bt_ant_diversity(struct ath_hw *ah, bool enable)
1426 {
1427         struct ath9k_hw_capabilities *pCap = &ah->caps;
1428         u8 ant_div_ctl1;
1429         u32 regval;
1430
1431         if (!AR_SREV_9485(ah) && !AR_SREV_9565(ah))
1432                 return;
1433
1434         if (AR_SREV_9485(ah)) {
1435                 regval = ar9003_hw_ant_ctrl_common_2_get(ah,
1436                                                  IS_CHAN_2GHZ(ah->curchan));
1437                 if (enable) {
1438                         regval &= ~AR_SWITCH_TABLE_COM2_ALL;
1439                         regval |= ah->config.ant_ctrl_comm2g_switch_enable;
1440                 }
1441                 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2,
1442                               AR_SWITCH_TABLE_COM2_ALL, regval);
1443         }
1444
1445         ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
1446
1447         /*
1448          * Set MAIN/ALT LNA conf.
1449          * Set MAIN/ALT gain_tb.
1450          */
1451         regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1452         regval &= (~AR_ANT_DIV_CTRL_ALL);
1453         regval |= (ant_div_ctl1 & 0x3f) << AR_ANT_DIV_CTRL_ALL_S;
1454         REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1455
1456         if (AR_SREV_9485_11_OR_LATER(ah)) {
1457                 /*
1458                  * Enable LNA diversity.
1459                  */
1460                 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1461                 regval &= ~AR_PHY_ANT_DIV_LNADIV;
1462                 regval |= ((ant_div_ctl1 >> 6) & 0x1) << AR_PHY_ANT_DIV_LNADIV_S;
1463                 if (enable)
1464                         regval |= AR_ANT_DIV_ENABLE;
1465
1466                 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1467
1468                 /*
1469                  * Enable fast antenna diversity.
1470                  */
1471                 regval = REG_READ(ah, AR_PHY_CCK_DETECT);
1472                 regval &= ~AR_FAST_DIV_ENABLE;
1473                 regval |= ((ant_div_ctl1 >> 7) & 0x1) << AR_FAST_DIV_ENABLE_S;
1474                 if (enable)
1475                         regval |= AR_FAST_DIV_ENABLE;
1476
1477                 REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);
1478
1479                 if (pCap->hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) {
1480                         regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1481                         regval &= (~(AR_PHY_ANT_DIV_MAIN_LNACONF |
1482                                      AR_PHY_ANT_DIV_ALT_LNACONF |
1483                                      AR_PHY_ANT_DIV_ALT_GAINTB |
1484                                      AR_PHY_ANT_DIV_MAIN_GAINTB));
1485                         /*
1486                          * Set MAIN to LNA1 and ALT to LNA2 at the
1487                          * beginning.
1488                          */
1489                         regval |= (ATH_ANT_DIV_COMB_LNA1 <<
1490                                    AR_PHY_ANT_DIV_MAIN_LNACONF_S);
1491                         regval |= (ATH_ANT_DIV_COMB_LNA2 <<
1492                                    AR_PHY_ANT_DIV_ALT_LNACONF_S);
1493                         REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1494                 }
1495         } else if (AR_SREV_9565(ah)) {
1496                 if (enable) {
1497                         REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1498                                     AR_ANT_DIV_ENABLE);
1499                         REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1500                                     (1 << AR_PHY_ANT_SW_RX_PROT_S));
1501                         REG_SET_BIT(ah, AR_PHY_CCK_DETECT,
1502                                     AR_FAST_DIV_ENABLE);
1503                         REG_SET_BIT(ah, AR_PHY_RESTART,
1504                                     AR_PHY_RESTART_ENABLE_DIV_M2FLAG);
1505                         REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV,
1506                                     AR_BTCOEX_WL_LNADIV_FORCE_ON);
1507                 } else {
1508                         REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1509                                     AR_ANT_DIV_ENABLE);
1510                         REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1511                                     (1 << AR_PHY_ANT_SW_RX_PROT_S));
1512                         REG_CLR_BIT(ah, AR_PHY_CCK_DETECT,
1513                                     AR_FAST_DIV_ENABLE);
1514                         REG_CLR_BIT(ah, AR_PHY_RESTART,
1515                                     AR_PHY_RESTART_ENABLE_DIV_M2FLAG);
1516                         REG_CLR_BIT(ah, AR_BTCOEX_WL_LNADIV,
1517                                     AR_BTCOEX_WL_LNADIV_FORCE_ON);
1518
1519                         regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1520                         regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF |
1521                                     AR_PHY_ANT_DIV_ALT_LNACONF |
1522                                     AR_PHY_ANT_DIV_MAIN_GAINTB |
1523                                     AR_PHY_ANT_DIV_ALT_GAINTB);
1524                         regval |= (ATH_ANT_DIV_COMB_LNA1 <<
1525                                    AR_PHY_ANT_DIV_MAIN_LNACONF_S);
1526                         regval |= (ATH_ANT_DIV_COMB_LNA2 <<
1527                                    AR_PHY_ANT_DIV_ALT_LNACONF_S);
1528                         REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1529                 }
1530         }
1531 }
1532
1533 #endif
1534
1535 static int ar9003_hw_fast_chan_change(struct ath_hw *ah,
1536                                       struct ath9k_channel *chan,
1537                                       u8 *ini_reloaded)
1538 {
1539         unsigned int regWrites = 0;
1540         u32 modesIndex;
1541
1542         switch (chan->chanmode) {
1543         case CHANNEL_A:
1544         case CHANNEL_A_HT20:
1545                 modesIndex = 1;
1546                 break;
1547         case CHANNEL_A_HT40PLUS:
1548         case CHANNEL_A_HT40MINUS:
1549                 modesIndex = 2;
1550                 break;
1551         case CHANNEL_G:
1552         case CHANNEL_G_HT20:
1553         case CHANNEL_B:
1554                 modesIndex = 4;
1555                 break;
1556         case CHANNEL_G_HT40PLUS:
1557         case CHANNEL_G_HT40MINUS:
1558                 modesIndex = 3;
1559                 break;
1560
1561         default:
1562                 return -EINVAL;
1563         }
1564
1565         if (modesIndex == ah->modes_index) {
1566                 *ini_reloaded = false;
1567                 goto set_rfmode;
1568         }
1569
1570         ar9003_hw_prog_ini(ah, &ah->iniSOC[ATH_INI_POST], modesIndex);
1571         ar9003_hw_prog_ini(ah, &ah->iniMac[ATH_INI_POST], modesIndex);
1572         ar9003_hw_prog_ini(ah, &ah->iniBB[ATH_INI_POST], modesIndex);
1573         ar9003_hw_prog_ini(ah, &ah->iniRadio[ATH_INI_POST], modesIndex);
1574
1575         if (AR_SREV_9462_20_OR_LATER(ah))
1576                 ar9003_hw_prog_ini(ah, &ah->ini_radio_post_sys2ant,
1577                                    modesIndex);
1578
1579         REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1580
1581         if (AR_SREV_9462_20_OR_LATER(ah)) {
1582                 /*
1583                  * CUS217 mix LNA mode.
1584                  */
1585                 if (ar9003_hw_get_rx_gain_idx(ah) == 2) {
1586                         REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_core,
1587                                         1, regWrites);
1588                         REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_postamble,
1589                                         modesIndex, regWrites);
1590                 }
1591         }
1592
1593         /*
1594          * For 5GHz channels requiring Fast Clock, apply
1595          * different modal values.
1596          */
1597         if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1598                 REG_WRITE_ARRAY(&ah->iniModesFastClock, modesIndex, regWrites);
1599
1600         if (AR_SREV_9565(ah))
1601                 REG_WRITE_ARRAY(&ah->iniModesFastClock, 1, regWrites);
1602
1603         /*
1604          * JAPAN regulatory.
1605          */
1606         if (chan->channel == 2484)
1607                 ar9003_hw_prog_ini(ah, &ah->iniCckfirJapan2484, 1);
1608
1609         ah->modes_index = modesIndex;
1610         *ini_reloaded = true;
1611
1612 set_rfmode:
1613         ar9003_hw_set_rfmode(ah, chan);
1614         return 0;
1615 }
1616
1617 static void ar9003_hw_spectral_scan_config(struct ath_hw *ah,
1618                                            struct ath_spec_scan *param)
1619 {
1620         u8 count;
1621
1622         if (!param->enabled) {
1623                 REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1624                             AR_PHY_SPECTRAL_SCAN_ENABLE);
1625                 return;
1626         }
1627
1628         REG_SET_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_FFT_ENA);
1629         REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENABLE);
1630
1631         /* on AR93xx and newer, count = 0 will make the the chip send
1632          * spectral samples endlessly. Check if this really was intended,
1633          * and fix otherwise.
1634          */
1635         count = param->count;
1636         if (param->endless)
1637                 count = 0;
1638         else if (param->count == 0)
1639                 count = 1;
1640
1641         if (param->short_repeat)
1642                 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1643                             AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT);
1644         else
1645                 REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1646                             AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT);
1647
1648         REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
1649                       AR_PHY_SPECTRAL_SCAN_COUNT, count);
1650         REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
1651                       AR_PHY_SPECTRAL_SCAN_PERIOD, param->period);
1652         REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
1653                       AR_PHY_SPECTRAL_SCAN_FFT_PERIOD, param->fft_period);
1654
1655         return;
1656 }
1657
1658 static void ar9003_hw_spectral_scan_trigger(struct ath_hw *ah)
1659 {
1660         /* Activate spectral scan */
1661         REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1662                     AR_PHY_SPECTRAL_SCAN_ACTIVE);
1663 }
1664
1665 static void ar9003_hw_spectral_scan_wait(struct ath_hw *ah)
1666 {
1667         struct ath_common *common = ath9k_hw_common(ah);
1668
1669         /* Poll for spectral scan complete */
1670         if (!ath9k_hw_wait(ah, AR_PHY_SPECTRAL_SCAN,
1671                            AR_PHY_SPECTRAL_SCAN_ACTIVE,
1672                            0, AH_WAIT_TIMEOUT)) {
1673                 ath_err(common, "spectral scan wait failed\n");
1674                 return;
1675         }
1676 }
1677
1678 void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
1679 {
1680         struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
1681         struct ath_hw_ops *ops = ath9k_hw_ops(ah);
1682         static const u32 ar9300_cca_regs[6] = {
1683                 AR_PHY_CCA_0,
1684                 AR_PHY_CCA_1,
1685                 AR_PHY_CCA_2,
1686                 AR_PHY_EXT_CCA,
1687                 AR_PHY_EXT_CCA_1,
1688                 AR_PHY_EXT_CCA_2,
1689         };
1690
1691         priv_ops->rf_set_freq = ar9003_hw_set_channel;
1692         priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate;
1693         priv_ops->compute_pll_control = ar9003_hw_compute_pll_control;
1694         priv_ops->set_channel_regs = ar9003_hw_set_channel_regs;
1695         priv_ops->init_bb = ar9003_hw_init_bb;
1696         priv_ops->process_ini = ar9003_hw_process_ini;
1697         priv_ops->set_rfmode = ar9003_hw_set_rfmode;
1698         priv_ops->mark_phy_inactive = ar9003_hw_mark_phy_inactive;
1699         priv_ops->set_delta_slope = ar9003_hw_set_delta_slope;
1700         priv_ops->rfbus_req = ar9003_hw_rfbus_req;
1701         priv_ops->rfbus_done = ar9003_hw_rfbus_done;
1702         priv_ops->ani_control = ar9003_hw_ani_control;
1703         priv_ops->do_getnf = ar9003_hw_do_getnf;
1704         priv_ops->ani_cache_ini_regs = ar9003_hw_ani_cache_ini_regs;
1705         priv_ops->set_radar_params = ar9003_hw_set_radar_params;
1706         priv_ops->fast_chan_change = ar9003_hw_fast_chan_change;
1707
1708         ops->antdiv_comb_conf_get = ar9003_hw_antdiv_comb_conf_get;
1709         ops->antdiv_comb_conf_set = ar9003_hw_antdiv_comb_conf_set;
1710         ops->spectral_scan_config = ar9003_hw_spectral_scan_config;
1711         ops->spectral_scan_trigger = ar9003_hw_spectral_scan_trigger;
1712         ops->spectral_scan_wait = ar9003_hw_spectral_scan_wait;
1713
1714 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
1715         ops->set_bt_ant_diversity = ar9003_hw_set_bt_ant_diversity;
1716 #endif
1717
1718         ar9003_hw_set_nf_limits(ah);
1719         ar9003_hw_set_radar_conf(ah);
1720         memcpy(ah->nf_regs, ar9300_cca_regs, sizeof(ah->nf_regs));
1721 }
1722
1723 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah)
1724 {
1725         struct ath_common *common = ath9k_hw_common(ah);
1726         u32 idle_tmo_ms = ah->bb_watchdog_timeout_ms;
1727         u32 val, idle_count;
1728
1729         if (!idle_tmo_ms) {
1730                 /* disable IRQ, disable chip-reset for BB panic */
1731                 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
1732                           REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) &
1733                           ~(AR_PHY_WATCHDOG_RST_ENABLE |
1734                             AR_PHY_WATCHDOG_IRQ_ENABLE));
1735
1736                 /* disable watchdog in non-IDLE mode, disable in IDLE mode */
1737                 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
1738                           REG_READ(ah, AR_PHY_WATCHDOG_CTL_1) &
1739                           ~(AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
1740                             AR_PHY_WATCHDOG_IDLE_ENABLE));
1741
1742                 ath_dbg(common, RESET, "Disabled BB Watchdog\n");
1743                 return;
1744         }
1745
1746         /* enable IRQ, disable chip-reset for BB watchdog */
1747         val = REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) & AR_PHY_WATCHDOG_CNTL2_MASK;
1748         REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
1749                   (val | AR_PHY_WATCHDOG_IRQ_ENABLE) &
1750                   ~AR_PHY_WATCHDOG_RST_ENABLE);
1751
1752         /* bound limit to 10 secs */
1753         if (idle_tmo_ms > 10000)
1754                 idle_tmo_ms = 10000;
1755
1756         /*
1757          * The time unit for watchdog event is 2^15 44/88MHz cycles.
1758          *
1759          * For HT20 we have a time unit of 2^15/44 MHz = .74 ms per tick
1760          * For HT40 we have a time unit of 2^15/88 MHz = .37 ms per tick
1761          *
1762          * Given we use fast clock now in 5 GHz, these time units should
1763          * be common for both 2 GHz and 5 GHz.
1764          */
1765         idle_count = (100 * idle_tmo_ms) / 74;
1766         if (ah->curchan && IS_CHAN_HT40(ah->curchan))
1767                 idle_count = (100 * idle_tmo_ms) / 37;
1768
1769         /*
1770          * enable watchdog in non-IDLE mode, disable in IDLE mode,
1771          * set idle time-out.
1772          */
1773         REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
1774                   AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
1775                   AR_PHY_WATCHDOG_IDLE_MASK |
1776                   (AR_PHY_WATCHDOG_NON_IDLE_MASK & (idle_count << 2)));
1777
1778         ath_dbg(common, RESET, "Enabled BB Watchdog timeout (%u ms)\n",
1779                 idle_tmo_ms);
1780 }
1781
1782 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah)
1783 {
1784         /*
1785          * we want to avoid printing in ISR context so we save the
1786          * watchdog status to be printed later in bottom half context.
1787          */
1788         ah->bb_watchdog_last_status = REG_READ(ah, AR_PHY_WATCHDOG_STATUS);
1789
1790         /*
1791          * the watchdog timer should reset on status read but to be sure
1792          * sure we write 0 to the watchdog status bit.
1793          */
1794         REG_WRITE(ah, AR_PHY_WATCHDOG_STATUS,
1795                   ah->bb_watchdog_last_status & ~AR_PHY_WATCHDOG_STATUS_CLR);
1796 }
1797
1798 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah)
1799 {
1800         struct ath_common *common = ath9k_hw_common(ah);
1801         u32 status;
1802
1803         if (likely(!(common->debug_mask & ATH_DBG_RESET)))
1804                 return;
1805
1806         status = ah->bb_watchdog_last_status;
1807         ath_dbg(common, RESET,
1808                 "\n==== BB update: BB status=0x%08x ====\n", status);
1809         ath_dbg(common, RESET,
1810                 "** BB state: wd=%u det=%u rdar=%u rOFDM=%d rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n",
1811                 MS(status, AR_PHY_WATCHDOG_INFO),
1812                 MS(status, AR_PHY_WATCHDOG_DET_HANG),
1813                 MS(status, AR_PHY_WATCHDOG_RADAR_SM),
1814                 MS(status, AR_PHY_WATCHDOG_RX_OFDM_SM),
1815                 MS(status, AR_PHY_WATCHDOG_RX_CCK_SM),
1816                 MS(status, AR_PHY_WATCHDOG_TX_OFDM_SM),
1817                 MS(status, AR_PHY_WATCHDOG_TX_CCK_SM),
1818                 MS(status, AR_PHY_WATCHDOG_AGC_SM),
1819                 MS(status, AR_PHY_WATCHDOG_SRCH_SM));
1820
1821         ath_dbg(common, RESET, "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n",
1822                 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1),
1823                 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2));
1824         ath_dbg(common, RESET, "** BB mode: BB_gen_controls=0x%08x **\n",
1825                 REG_READ(ah, AR_PHY_GEN_CTRL));
1826
1827 #define PCT(_field) (common->cc_survey._field * 100 / common->cc_survey.cycles)
1828         if (common->cc_survey.cycles)
1829                 ath_dbg(common, RESET,
1830                         "** BB busy times: rx_clear=%d%%, rx_frame=%d%%, tx_frame=%d%% **\n",
1831                         PCT(rx_busy), PCT(rx_frame), PCT(tx_frame));
1832
1833         ath_dbg(common, RESET, "==== BB update: done ====\n\n");
1834 }
1835 EXPORT_SYMBOL(ar9003_hw_bb_watchdog_dbg_info);
1836
1837 void ar9003_hw_disable_phy_restart(struct ath_hw *ah)
1838 {
1839         u32 val;
1840
1841         /* While receiving unsupported rate frame rx state machine
1842          * gets into a state 0xb and if phy_restart happens in that
1843          * state, BB would go hang. If RXSM is in 0xb state after
1844          * first bb panic, ensure to disable the phy_restart.
1845          */
1846         if (!((MS(ah->bb_watchdog_last_status,
1847                   AR_PHY_WATCHDOG_RX_OFDM_SM) == 0xb) ||
1848             ah->bb_hang_rx_ofdm))
1849                 return;
1850
1851         ah->bb_hang_rx_ofdm = true;
1852         val = REG_READ(ah, AR_PHY_RESTART);
1853         val &= ~AR_PHY_RESTART_ENA;
1854
1855         REG_WRITE(ah, AR_PHY_RESTART, val);
1856 }
1857 EXPORT_SYMBOL(ar9003_hw_disable_phy_restart);