2 * Copyright (c) 2002-2010 Atheros Communications, Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21 * Channel Register Map
23 #define AR_CHAN_BASE 0x9800
25 #define AR_PHY_TIMING1 (AR_CHAN_BASE + 0x0)
26 #define AR_PHY_TIMING2 (AR_CHAN_BASE + 0x4)
27 #define AR_PHY_TIMING3 (AR_CHAN_BASE + 0x8)
28 #define AR_PHY_TIMING4 (AR_CHAN_BASE + 0xc)
29 #define AR_PHY_TIMING5 (AR_CHAN_BASE + 0x10)
30 #define AR_PHY_TIMING6 (AR_CHAN_BASE + 0x14)
31 #define AR_PHY_TIMING11 (AR_CHAN_BASE + 0x18)
32 #define AR_PHY_SPUR_REG (AR_CHAN_BASE + 0x1c)
33 #define AR_PHY_RX_IQCAL_CORR_B0 (AR_CHAN_BASE + 0xdc)
34 #define AR_PHY_TX_IQCAL_CONTROL_3 (AR_CHAN_BASE + 0xb0)
36 #define AR_PHY_TIMING11_SPUR_FREQ_SD 0x3FF00000
37 #define AR_PHY_TIMING11_SPUR_FREQ_SD_S 20
39 #define AR_PHY_TIMING11_SPUR_DELTA_PHASE 0x000FFFFF
40 #define AR_PHY_TIMING11_SPUR_DELTA_PHASE_S 0
42 #define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC 0x40000000
43 #define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC_S 30
45 #define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR 0x80000000
46 #define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR_S 31
48 #define AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT 0x4000000
49 #define AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT_S 26
51 #define AR_PHY_SPUR_REG_ENABLE_MASK_PPM 0x20000 /* bins move with freq offset */
52 #define AR_PHY_SPUR_REG_ENABLE_MASK_PPM_S 17
53 #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH 0x000000FF
54 #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S 0
55 #define AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI 0x00000100
56 #define AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI_S 8
57 #define AR_PHY_SPUR_REG_MASK_RATE_CNTL 0x03FC0000
58 #define AR_PHY_SPUR_REG_MASK_RATE_CNTL_S 18
60 #define AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN 0x20000000
61 #define AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN_S 29
63 #define AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN 0x80000000
64 #define AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN_S 31
66 #define AR_PHY_FIND_SIG_LOW (AR_CHAN_BASE + 0x20)
68 #define AR_PHY_SFCORR (AR_CHAN_BASE + 0x24)
69 #define AR_PHY_SFCORR_LOW (AR_CHAN_BASE + 0x28)
70 #define AR_PHY_SFCORR_EXT (AR_CHAN_BASE + 0x2c)
72 #define AR_PHY_EXT_CCA (AR_CHAN_BASE + 0x30)
73 #define AR_PHY_RADAR_0 (AR_CHAN_BASE + 0x34)
74 #define AR_PHY_RADAR_1 (AR_CHAN_BASE + 0x38)
75 #define AR_PHY_RADAR_EXT (AR_CHAN_BASE + 0x3c)
76 #define AR_PHY_MULTICHAIN_CTRL (AR_CHAN_BASE + 0x80)
77 #define AR_PHY_PERCHAIN_CSD (AR_CHAN_BASE + 0x84)
79 #define AR_PHY_TX_PHASE_RAMP_0 (AR_CHAN_BASE + 0xd0)
80 #define AR_PHY_ADC_GAIN_DC_CORR_0 (AR_CHAN_BASE + 0xd4)
81 #define AR_PHY_IQ_ADC_MEAS_0_B0 (AR_CHAN_BASE + 0xc0)
82 #define AR_PHY_IQ_ADC_MEAS_1_B0 (AR_CHAN_BASE + 0xc4)
83 #define AR_PHY_IQ_ADC_MEAS_2_B0 (AR_CHAN_BASE + 0xc8)
84 #define AR_PHY_IQ_ADC_MEAS_3_B0 (AR_CHAN_BASE + 0xcc)
86 /* The following registers changed position from AR9300 1.0 to AR9300 2.0 */
87 #define AR_PHY_TX_PHASE_RAMP_0_9300_10 (AR_CHAN_BASE + 0xd0 - 0x10)
88 #define AR_PHY_ADC_GAIN_DC_CORR_0_9300_10 (AR_CHAN_BASE + 0xd4 - 0x10)
89 #define AR_PHY_IQ_ADC_MEAS_0_B0_9300_10 (AR_CHAN_BASE + 0xc0 + 0x8)
90 #define AR_PHY_IQ_ADC_MEAS_1_B0_9300_10 (AR_CHAN_BASE + 0xc4 + 0x8)
91 #define AR_PHY_IQ_ADC_MEAS_2_B0_9300_10 (AR_CHAN_BASE + 0xc8 + 0x8)
92 #define AR_PHY_IQ_ADC_MEAS_3_B0_9300_10 (AR_CHAN_BASE + 0xcc + 0x8)
94 #define AR_PHY_TX_CRC (AR_CHAN_BASE + 0xa0)
95 #define AR_PHY_TST_DAC_CONST (AR_CHAN_BASE + 0xa4)
96 #define AR_PHY_SPUR_REPORT_0 (AR_CHAN_BASE + 0xa8)
97 #define AR_PHY_CHAN_INFO_TAB_0 (AR_CHAN_BASE + 0x300)
100 * Channel Field Definitions
102 #define AR_PHY_TIMING2_USE_FORCE_PPM 0x00001000
103 #define AR_PHY_TIMING2_FORCE_PPM_VAL 0x00000fff
104 #define AR_PHY_TIMING3_DSC_MAN 0xFFFE0000
105 #define AR_PHY_TIMING3_DSC_MAN_S 17
106 #define AR_PHY_TIMING3_DSC_EXP 0x0001E000
107 #define AR_PHY_TIMING3_DSC_EXP_S 13
108 #define AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX 0xF000
109 #define AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX_S 12
110 #define AR_PHY_TIMING4_DO_CAL 0x10000
112 #define AR_PHY_TIMING4_ENABLE_PILOT_MASK 0x10000000
113 #define AR_PHY_TIMING4_ENABLE_PILOT_MASK_S 28
114 #define AR_PHY_TIMING4_ENABLE_CHAN_MASK 0x20000000
115 #define AR_PHY_TIMING4_ENABLE_CHAN_MASK_S 29
117 #define AR_PHY_TIMING4_ENABLE_SPUR_FILTER 0x40000000
118 #define AR_PHY_TIMING4_ENABLE_SPUR_FILTER_S 30
119 #define AR_PHY_TIMING4_ENABLE_SPUR_RSSI 0x80000000
120 #define AR_PHY_TIMING4_ENABLE_SPUR_RSSI_S 31
122 #define AR_PHY_NEW_ADC_GAIN_CORR_ENABLE 0x40000000
123 #define AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE 0x80000000
124 #define AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW 0x00000001
125 #define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW 0x00003F00
126 #define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_S 8
127 #define AR_PHY_SFCORR_LOW_M1_THRESH_LOW 0x001FC000
128 #define AR_PHY_SFCORR_LOW_M1_THRESH_LOW_S 14
129 #define AR_PHY_SFCORR_LOW_M2_THRESH_LOW 0x0FE00000
130 #define AR_PHY_SFCORR_LOW_M2_THRESH_LOW_S 21
131 #define AR_PHY_SFCORR_M2COUNT_THR 0x0000001F
132 #define AR_PHY_SFCORR_M2COUNT_THR_S 0
133 #define AR_PHY_SFCORR_M1_THRESH 0x00FE0000
134 #define AR_PHY_SFCORR_M1_THRESH_S 17
135 #define AR_PHY_SFCORR_M2_THRESH 0x7F000000
136 #define AR_PHY_SFCORR_M2_THRESH_S 24
137 #define AR_PHY_SFCORR_EXT_M1_THRESH 0x0000007F
138 #define AR_PHY_SFCORR_EXT_M1_THRESH_S 0
139 #define AR_PHY_SFCORR_EXT_M2_THRESH 0x00003F80
140 #define AR_PHY_SFCORR_EXT_M2_THRESH_S 7
141 #define AR_PHY_SFCORR_EXT_M1_THRESH_LOW 0x001FC000
142 #define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_S 14
143 #define AR_PHY_SFCORR_EXT_M2_THRESH_LOW 0x0FE00000
144 #define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_S 21
145 #define AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD 0x10000000
146 #define AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD_S 28
147 #define AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S 28
148 #define AR_PHY_EXT_CCA_THRESH62 0x007F0000
149 #define AR_PHY_EXT_CCA_THRESH62_S 16
150 #define AR_PHY_EXT_MINCCA_PWR 0x01FF0000
151 #define AR_PHY_EXT_MINCCA_PWR_S 16
152 #define AR_PHY_EXT_CYCPWR_THR1 0x0000FE00L
153 #define AR_PHY_EXT_CYCPWR_THR1_S 9
154 #define AR_PHY_TIMING5_CYCPWR_THR1 0x000000FE
155 #define AR_PHY_TIMING5_CYCPWR_THR1_S 1
156 #define AR_PHY_TIMING5_CYCPWR_THR1_ENABLE 0x00000001
157 #define AR_PHY_TIMING5_CYCPWR_THR1_ENABLE_S 0
158 #define AR_PHY_TIMING5_CYCPWR_THR1A 0x007F0000
159 #define AR_PHY_TIMING5_CYCPWR_THR1A_S 16
160 #define AR_PHY_TIMING5_RSSI_THR1A (0x7F << 16)
161 #define AR_PHY_TIMING5_RSSI_THR1A_S 16
162 #define AR_PHY_TIMING5_RSSI_THR1A_ENA (0x1 << 15)
163 #define AR_PHY_RADAR_0_ENA 0x00000001
164 #define AR_PHY_RADAR_0_FFT_ENA 0x80000000
165 #define AR_PHY_RADAR_0_INBAND 0x0000003e
166 #define AR_PHY_RADAR_0_INBAND_S 1
167 #define AR_PHY_RADAR_0_PRSSI 0x00000FC0
168 #define AR_PHY_RADAR_0_PRSSI_S 6
169 #define AR_PHY_RADAR_0_HEIGHT 0x0003F000
170 #define AR_PHY_RADAR_0_HEIGHT_S 12
171 #define AR_PHY_RADAR_0_RRSSI 0x00FC0000
172 #define AR_PHY_RADAR_0_RRSSI_S 18
173 #define AR_PHY_RADAR_0_FIRPWR 0x7F000000
174 #define AR_PHY_RADAR_0_FIRPWR_S 24
175 #define AR_PHY_RADAR_1_RELPWR_ENA 0x00800000
176 #define AR_PHY_RADAR_1_USE_FIR128 0x00400000
177 #define AR_PHY_RADAR_1_RELPWR_THRESH 0x003F0000
178 #define AR_PHY_RADAR_1_RELPWR_THRESH_S 16
179 #define AR_PHY_RADAR_1_BLOCK_CHECK 0x00008000
180 #define AR_PHY_RADAR_1_MAX_RRSSI 0x00004000
181 #define AR_PHY_RADAR_1_RELSTEP_CHECK 0x00002000
182 #define AR_PHY_RADAR_1_RELSTEP_THRESH 0x00001F00
183 #define AR_PHY_RADAR_1_RELSTEP_THRESH_S 8
184 #define AR_PHY_RADAR_1_MAXLEN 0x000000FF
185 #define AR_PHY_RADAR_1_MAXLEN_S 0
186 #define AR_PHY_RADAR_EXT_ENA 0x00004000
187 #define AR_PHY_RADAR_DC_PWR_THRESH 0x007f8000
188 #define AR_PHY_RADAR_DC_PWR_THRESH_S 15
189 #define AR_PHY_RADAR_LB_DC_CAP 0x7f800000
190 #define AR_PHY_RADAR_LB_DC_CAP_S 23
191 #define AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW (0x3f << 6)
192 #define AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW_S 6
193 #define AR_PHY_FIND_SIG_LOW_FIRPWR (0x7f << 12)
194 #define AR_PHY_FIND_SIG_LOW_FIRPWR_S 12
195 #define AR_PHY_FIND_SIG_LOW_FIRPWR_SIGN_BIT 19
196 #define AR_PHY_FIND_SIG_LOW_RELSTEP 0x1f
197 #define AR_PHY_FIND_SIG_LOW_RELSTEP_S 0
198 #define AR_PHY_FIND_SIG_LOW_RELSTEP_SIGN_BIT 5
199 #define AR_PHY_CHAN_INFO_TAB_S2_READ 0x00000008
200 #define AR_PHY_CHAN_INFO_TAB_S2_READ_S 3
201 #define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF 0x0000007F
202 #define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF_S 0
203 #define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF 0x00003F80
204 #define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF_S 7
205 #define AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE 0x00004000
206 #define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF 0x003f8000
207 #define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF_S 15
208 #define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF 0x1fc00000
209 #define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF_S 22
214 #define AR_MRC_BASE 0x9c00
216 #define AR_PHY_TIMING_3A (AR_MRC_BASE + 0x0)
217 #define AR_PHY_LDPC_CNTL1 (AR_MRC_BASE + 0x4)
218 #define AR_PHY_LDPC_CNTL2 (AR_MRC_BASE + 0x8)
219 #define AR_PHY_PILOT_SPUR_MASK (AR_MRC_BASE + 0xc)
220 #define AR_PHY_CHAN_SPUR_MASK (AR_MRC_BASE + 0x10)
221 #define AR_PHY_SGI_DELTA (AR_MRC_BASE + 0x14)
222 #define AR_PHY_ML_CNTL_1 (AR_MRC_BASE + 0x18)
223 #define AR_PHY_ML_CNTL_2 (AR_MRC_BASE + 0x1c)
224 #define AR_PHY_TST_ADC (AR_MRC_BASE + 0x20)
226 #define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A 0x00000FE0
227 #define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_S 5
228 #define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A 0x1F
229 #define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A_S 0
231 #define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A 0x00000FE0
232 #define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A_S 5
233 #define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A 0x1F
234 #define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A_S 0
237 * MRC Feild Definitions
239 #define AR_PHY_SGI_DSC_MAN 0x0007FFF0
240 #define AR_PHY_SGI_DSC_MAN_S 4
241 #define AR_PHY_SGI_DSC_EXP 0x0000000F
242 #define AR_PHY_SGI_DSC_EXP_S 0
246 #define AR_BBB_BASE 0x9d00
251 #define AR_AGC_BASE 0x9e00
253 #define AR_PHY_SETTLING (AR_AGC_BASE + 0x0)
254 #define AR_PHY_FORCEMAX_GAINS_0 (AR_AGC_BASE + 0x4)
255 #define AR_PHY_GAINS_MINOFF0 (AR_AGC_BASE + 0x8)
256 #define AR_PHY_DESIRED_SZ (AR_AGC_BASE + 0xc)
257 #define AR_PHY_FIND_SIG (AR_AGC_BASE + 0x10)
258 #define AR_PHY_AGC (AR_AGC_BASE + 0x14)
259 #define AR_PHY_EXT_ATTEN_CTL_0 (AR_AGC_BASE + 0x18)
260 #define AR_PHY_CCA_0 (AR_AGC_BASE + 0x1c)
261 #define AR_PHY_EXT_CCA0 (AR_AGC_BASE + 0x20)
262 #define AR_PHY_RESTART (AR_AGC_BASE + 0x24)
264 #define AR_PHY_MC_GAIN_CTRL (AR_AGC_BASE + 0x28)
265 #define AR_ANT_DIV_CTRL_ALL 0x7e000000
266 #define AR_ANT_DIV_CTRL_ALL_S 25
267 #define AR_ANT_DIV_ENABLE 0x1000000
268 #define AR_ANT_DIV_ENABLE_S 24
270 #define AR_PHY_EXTCHN_PWRTHR1 (AR_AGC_BASE + 0x2c)
271 #define AR_PHY_EXT_CHN_WIN (AR_AGC_BASE + 0x30)
272 #define AR_PHY_20_40_DET_THR (AR_AGC_BASE + 0x34)
273 #define AR_PHY_RIFS_SRCH (AR_AGC_BASE + 0x38)
274 #define AR_PHY_PEAK_DET_CTRL_1 (AR_AGC_BASE + 0x3c)
275 #define AR_PHY_PEAK_DET_CTRL_2 (AR_AGC_BASE + 0x40)
276 #define AR_PHY_RX_GAIN_BOUNDS_1 (AR_AGC_BASE + 0x44)
277 #define AR_PHY_RX_GAIN_BOUNDS_2 (AR_AGC_BASE + 0x48)
278 #define AR_PHY_RSSI_0 (AR_AGC_BASE + 0x180)
279 #define AR_PHY_SPUR_CCK_REP0 (AR_AGC_BASE + 0x184)
281 #define AR_PHY_CCK_DETECT (AR_AGC_BASE + 0x1c0)
282 #define AR_FAST_DIV_ENABLE 0x2000
283 #define AR_FAST_DIV_ENABLE_S 13
285 #define AR_PHY_DAG_CTRLCCK (AR_AGC_BASE + 0x1c4)
286 #define AR_PHY_IQCORR_CTRL_CCK (AR_AGC_BASE + 0x1c8)
288 #define AR_PHY_CCK_SPUR_MIT (AR_AGC_BASE + 0x1cc)
289 #define AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR 0x000001fe
290 #define AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR_S 1
291 #define AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE 0x60000000
292 #define AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE_S 29
293 #define AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT 0x00000001
294 #define AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT_S 0
295 #define AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ 0x1ffffe00
296 #define AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ_S 9
298 #define AR_PHY_MRC_CCK_CTRL (AR_AGC_BASE + 0x1d0)
299 #define AR_PHY_MRC_CCK_ENABLE 0x00000001
300 #define AR_PHY_MRC_CCK_ENABLE_S 0
301 #define AR_PHY_MRC_CCK_MUX_REG 0x00000002
302 #define AR_PHY_MRC_CCK_MUX_REG_S 1
304 #define AR_PHY_RX_OCGAIN (AR_AGC_BASE + 0x200)
306 #define AR_PHY_CCA_NOM_VAL_9300_2GHZ -110
307 #define AR_PHY_CCA_NOM_VAL_9300_5GHZ -115
308 #define AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ -125
309 #define AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ -125
310 #define AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ -95
311 #define AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ -100
314 * AGC Field Definitions
316 #define AR_PHY_EXT_ATTEN_CTL_RXTX_MARGIN 0x00FC0000
317 #define AR_PHY_EXT_ATTEN_CTL_RXTX_MARGIN_S 18
318 #define AR_PHY_EXT_ATTEN_CTL_BSW_MARGIN 0x00003C00
319 #define AR_PHY_EXT_ATTEN_CTL_BSW_MARGIN_S 10
320 #define AR_PHY_EXT_ATTEN_CTL_BSW_ATTEN 0x0000001F
321 #define AR_PHY_EXT_ATTEN_CTL_BSW_ATTEN_S 0
322 #define AR_PHY_EXT_ATTEN_CTL_XATTEN2_MARGIN 0x003E0000
323 #define AR_PHY_EXT_ATTEN_CTL_XATTEN2_MARGIN_S 17
324 #define AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN 0x0001F000
325 #define AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN_S 12
326 #define AR_PHY_EXT_ATTEN_CTL_XATTEN2_DB 0x00000FC0
327 #define AR_PHY_EXT_ATTEN_CTL_XATTEN2_DB_S 6
328 #define AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB 0x0000003F
329 #define AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB_S 0
330 #define AR_PHY_RXGAIN_TXRX_ATTEN 0x0003F000
331 #define AR_PHY_RXGAIN_TXRX_ATTEN_S 12
332 #define AR_PHY_RXGAIN_TXRX_RF_MAX 0x007C0000
333 #define AR_PHY_RXGAIN_TXRX_RF_MAX_S 18
334 #define AR9280_PHY_RXGAIN_TXRX_ATTEN 0x00003F80
335 #define AR9280_PHY_RXGAIN_TXRX_ATTEN_S 7
336 #define AR9280_PHY_RXGAIN_TXRX_MARGIN 0x001FC000
337 #define AR9280_PHY_RXGAIN_TXRX_MARGIN_S 14
338 #define AR_PHY_SETTLING_SWITCH 0x00003F80
339 #define AR_PHY_SETTLING_SWITCH_S 7
340 #define AR_PHY_DESIRED_SZ_ADC 0x000000FF
341 #define AR_PHY_DESIRED_SZ_ADC_S 0
342 #define AR_PHY_DESIRED_SZ_PGA 0x0000FF00
343 #define AR_PHY_DESIRED_SZ_PGA_S 8
344 #define AR_PHY_DESIRED_SZ_TOT_DES 0x0FF00000
345 #define AR_PHY_DESIRED_SZ_TOT_DES_S 20
346 #define AR_PHY_MINCCA_PWR 0x1FF00000
347 #define AR_PHY_MINCCA_PWR_S 20
348 #define AR_PHY_CCA_THRESH62 0x0007F000
349 #define AR_PHY_CCA_THRESH62_S 12
350 #define AR9280_PHY_MINCCA_PWR 0x1FF00000
351 #define AR9280_PHY_MINCCA_PWR_S 20
352 #define AR9280_PHY_CCA_THRESH62 0x000FF000
353 #define AR9280_PHY_CCA_THRESH62_S 12
354 #define AR_PHY_EXT_CCA0_THRESH62 0x000000FF
355 #define AR_PHY_EXT_CCA0_THRESH62_S 0
356 #define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK 0x0000003F
357 #define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S 0
358 #define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME 0x00001FC0
359 #define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_S 6
360 #define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV 0x2000
362 #define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR 0x00000200
363 #define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR_S 9
364 #define AR_PHY_DAG_CTRLCCK_RSSI_THR 0x0001FC00
365 #define AR_PHY_DAG_CTRLCCK_RSSI_THR_S 10
367 #define AR_PHY_RIFS_INIT_DELAY 0x3ff0000
368 #define AR_PHY_AGC_COARSE_LOW 0x00007F80
369 #define AR_PHY_AGC_COARSE_LOW_S 7
370 #define AR_PHY_AGC_COARSE_HIGH 0x003F8000
371 #define AR_PHY_AGC_COARSE_HIGH_S 15
372 #define AR_PHY_AGC_COARSE_PWR_CONST 0x0000007F
373 #define AR_PHY_AGC_COARSE_PWR_CONST_S 0
374 #define AR_PHY_FIND_SIG_FIRSTEP 0x0003F000
375 #define AR_PHY_FIND_SIG_FIRSTEP_S 12
376 #define AR_PHY_FIND_SIG_FIRPWR 0x03FC0000
377 #define AR_PHY_FIND_SIG_FIRPWR_S 18
378 #define AR_PHY_FIND_SIG_FIRPWR_SIGN_BIT 25
379 #define AR_PHY_FIND_SIG_RELPWR (0x1f << 6)
380 #define AR_PHY_FIND_SIG_RELPWR_S 6
381 #define AR_PHY_FIND_SIG_RELPWR_SIGN_BIT 11
382 #define AR_PHY_FIND_SIG_RELSTEP 0x1f
383 #define AR_PHY_FIND_SIG_RELSTEP_S 0
384 #define AR_PHY_FIND_SIG_RELSTEP_SIGN_BIT 5
385 #define AR_PHY_RESTART_DIV_GC 0x001C0000
386 #define AR_PHY_RESTART_DIV_GC_S 18
387 #define AR_PHY_RESTART_ENA 0x01
388 #define AR_PHY_DC_RESTART_DIS 0x40000000
390 #define AR_PHY_TPC_OLPC_GAIN_DELTA_PAL_ON 0xFF000000
391 #define AR_PHY_TPC_OLPC_GAIN_DELTA_PAL_ON_S 24
392 #define AR_PHY_TPC_OLPC_GAIN_DELTA 0x00FF0000
393 #define AR_PHY_TPC_OLPC_GAIN_DELTA_S 16
395 #define AR_PHY_TPC_6_ERROR_EST_MODE 0x03000000
396 #define AR_PHY_TPC_6_ERROR_EST_MODE_S 24
401 #define AR_SM_BASE 0xa200
403 #define AR_PHY_D2_CHIP_ID (AR_SM_BASE + 0x0)
404 #define AR_PHY_GEN_CTRL (AR_SM_BASE + 0x4)
405 #define AR_PHY_MODE (AR_SM_BASE + 0x8)
406 #define AR_PHY_ACTIVE (AR_SM_BASE + 0xc)
407 #define AR_PHY_SPUR_MASK_A (AR_SM_BASE + 0x20)
408 #define AR_PHY_SPUR_MASK_B (AR_SM_BASE + 0x24)
409 #define AR_PHY_SPECTRAL_SCAN (AR_SM_BASE + 0x28)
410 #define AR_PHY_RADAR_BW_FILTER (AR_SM_BASE + 0x2c)
411 #define AR_PHY_SEARCH_START_DELAY (AR_SM_BASE + 0x30)
412 #define AR_PHY_MAX_RX_LEN (AR_SM_BASE + 0x34)
413 #define AR_PHY_FRAME_CTL (AR_SM_BASE + 0x38)
414 #define AR_PHY_RFBUS_REQ (AR_SM_BASE + 0x3c)
415 #define AR_PHY_RFBUS_GRANT (AR_SM_BASE + 0x40)
416 #define AR_PHY_RIFS (AR_SM_BASE + 0x44)
417 #define AR_PHY_RX_CLR_DELAY (AR_SM_BASE + 0x50)
418 #define AR_PHY_RX_DELAY (AR_SM_BASE + 0x54)
420 #define AR_PHY_XPA_TIMING_CTL (AR_SM_BASE + 0x64)
421 #define AR_PHY_MISC_PA_CTL (AR_SM_BASE + 0x80)
422 #define AR_PHY_SWITCH_CHAIN_0 (AR_SM_BASE + 0x84)
423 #define AR_PHY_SWITCH_COM (AR_SM_BASE + 0x88)
424 #define AR_PHY_SWITCH_COM_2 (AR_SM_BASE + 0x8c)
425 #define AR_PHY_RX_CHAINMASK (AR_SM_BASE + 0xa0)
426 #define AR_PHY_CAL_CHAINMASK (AR_SM_BASE + 0xc0)
427 #define AR_PHY_CALMODE (AR_SM_BASE + 0xc8)
428 #define AR_PHY_FCAL_1 (AR_SM_BASE + 0xcc)
429 #define AR_PHY_FCAL_2_0 (AR_SM_BASE + 0xd0)
430 #define AR_PHY_DFT_TONE_CTL_0 (AR_SM_BASE + 0xd4)
431 #define AR_PHY_CL_CAL_CTL (AR_SM_BASE + 0xd8)
432 #define AR_PHY_CL_TAB_0 (AR_SM_BASE + 0x100)
433 #define AR_PHY_SYNTH_CONTROL (AR_SM_BASE + 0x140)
434 #define AR_PHY_ADDAC_CLK_SEL (AR_SM_BASE + 0x144)
435 #define AR_PHY_PLL_CTL (AR_SM_BASE + 0x148)
436 #define AR_PHY_ANALOG_SWAP (AR_SM_BASE + 0x14c)
437 #define AR_PHY_ADDAC_PARA_CTL (AR_SM_BASE + 0x150)
438 #define AR_PHY_XPA_CFG (AR_SM_BASE + 0x158)
440 #define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A 0x0001FC00
441 #define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A_S 10
442 #define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A 0x3FF
443 #define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A_S 0
445 #define AR_PHY_TEST (AR_SM_BASE + 0x160)
447 #define AR_PHY_TEST_BBB_OBS_SEL 0x780000
448 #define AR_PHY_TEST_BBB_OBS_SEL_S 19
450 #define AR_PHY_TEST_RX_OBS_SEL_BIT5_S 23
451 #define AR_PHY_TEST_RX_OBS_SEL_BIT5 (1 << AR_PHY_TEST_RX_OBS_SEL_BIT5_S)
453 #define AR_PHY_TEST_CHAIN_SEL 0xC0000000
454 #define AR_PHY_TEST_CHAIN_SEL_S 30
456 #define AR_PHY_TEST_CTL_STATUS (AR_SM_BASE + 0x164)
457 #define AR_PHY_TEST_CTL_TSTDAC_EN 0x1
458 #define AR_PHY_TEST_CTL_TSTDAC_EN_S 0
459 #define AR_PHY_TEST_CTL_TX_OBS_SEL 0x1C
460 #define AR_PHY_TEST_CTL_TX_OBS_SEL_S 2
461 #define AR_PHY_TEST_CTL_TX_OBS_MUX_SEL 0x60
462 #define AR_PHY_TEST_CTL_TX_OBS_MUX_SEL_S 5
463 #define AR_PHY_TEST_CTL_TSTADC_EN 0x100
464 #define AR_PHY_TEST_CTL_TSTADC_EN_S 8
465 #define AR_PHY_TEST_CTL_RX_OBS_SEL 0x3C00
466 #define AR_PHY_TEST_CTL_RX_OBS_SEL_S 10
469 #define AR_PHY_TSTDAC (AR_SM_BASE + 0x168)
471 #define AR_PHY_CHAN_STATUS (AR_SM_BASE + 0x16c)
473 #define AR_PHY_CHAN_INFO_MEMORY (AR_SM_BASE + 0x170)
474 #define AR_PHY_CHAN_INFO_MEMORY_CHANINFOMEM_S2_READ 0x00000008
475 #define AR_PHY_CHAN_INFO_MEMORY_CHANINFOMEM_S2_READ_S 3
477 #define AR_PHY_CHNINFO_NOISEPWR (AR_SM_BASE + 0x174)
478 #define AR_PHY_CHNINFO_GAINDIFF (AR_SM_BASE + 0x178)
479 #define AR_PHY_CHNINFO_FINETIM (AR_SM_BASE + 0x17c)
480 #define AR_PHY_CHAN_INFO_GAIN_0 (AR_SM_BASE + 0x180)
481 #define AR_PHY_SCRAMBLER_SEED (AR_SM_BASE + 0x190)
482 #define AR_PHY_CCK_TX_CTRL (AR_SM_BASE + 0x194)
484 #define AR_PHY_HEAVYCLIP_CTL (AR_SM_BASE + 0x1a4)
485 #define AR_PHY_HEAVYCLIP_20 (AR_SM_BASE + 0x1a8)
486 #define AR_PHY_HEAVYCLIP_40 (AR_SM_BASE + 0x1ac)
487 #define AR_PHY_ILLEGAL_TXRATE (AR_SM_BASE + 0x1b0)
489 #define AR_PHY_PWRTX_MAX (AR_SM_BASE + 0x1f0)
490 #define AR_PHY_POWER_TX_SUB (AR_SM_BASE + 0x1f4)
492 #define AR_PHY_TPC_1 (AR_SM_BASE + 0x1f8)
493 #define AR_PHY_TPC_1_FORCED_DAC_GAIN 0x0000003e
494 #define AR_PHY_TPC_1_FORCED_DAC_GAIN_S 1
495 #define AR_PHY_TPC_1_FORCE_DAC_GAIN 0x00000001
496 #define AR_PHY_TPC_1_FORCE_DAC_GAIN_S 0
498 #define AR_PHY_TPC_4_B0 (AR_SM_BASE + 0x204)
499 #define AR_PHY_TPC_5_B0 (AR_SM_BASE + 0x208)
500 #define AR_PHY_TPC_6_B0 (AR_SM_BASE + 0x20c)
502 #define AR_PHY_TPC_11_B0 (AR_SM_BASE + 0x220)
503 #define AR_PHY_TPC_11_B1 (AR_SM1_BASE + 0x220)
504 #define AR_PHY_TPC_11_B2 (AR_SM2_BASE + 0x220)
505 #define AR_PHY_TPC_11_OLPC_GAIN_DELTA 0x00ff0000
506 #define AR_PHY_TPC_11_OLPC_GAIN_DELTA_S 16
508 #define AR_PHY_TPC_12 (AR_SM_BASE + 0x224)
509 #define AR_PHY_TPC_12_DESIRED_SCALE_HT40_5 0x3e000000
510 #define AR_PHY_TPC_12_DESIRED_SCALE_HT40_5_S 25
512 #define AR_PHY_TPC_18 (AR_SM_BASE + 0x23c)
513 #define AR_PHY_TPC_18_THERM_CAL_VALUE 0x000000ff
514 #define AR_PHY_TPC_18_THERM_CAL_VALUE_S 0
515 #define AR_PHY_TPC_18_VOLT_CAL_VALUE 0x0000ff00
516 #define AR_PHY_TPC_18_VOLT_CAL_VALUE_S 8
518 #define AR_PHY_TPC_19 (AR_SM_BASE + 0x240)
519 #define AR_PHY_TPC_19_ALPHA_VOLT 0x001f0000
520 #define AR_PHY_TPC_19_ALPHA_VOLT_S 16
521 #define AR_PHY_TPC_19_ALPHA_THERM 0xff
522 #define AR_PHY_TPC_19_ALPHA_THERM_S 0
524 #define AR_PHY_TX_FORCED_GAIN (AR_SM_BASE + 0x258)
525 #define AR_PHY_TX_FORCED_GAIN_FORCE_TX_GAIN 0x00000001
526 #define AR_PHY_TX_FORCED_GAIN_FORCE_TX_GAIN_S 0
527 #define AR_PHY_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN 0x0000000e
528 #define AR_PHY_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN_S 1
529 #define AR_PHY_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN 0x00000030
530 #define AR_PHY_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN_S 4
531 #define AR_PHY_TX_FORCED_GAIN_FORCED_TXMXRGAIN 0x000003c0
532 #define AR_PHY_TX_FORCED_GAIN_FORCED_TXMXRGAIN_S 6
533 #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNA 0x00003c00
534 #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNA_S 10
535 #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNB 0x0003c000
536 #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNB_S 14
537 #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNC 0x003c0000
538 #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNC_S 18
539 #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGND 0x00c00000
540 #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGND_S 22
541 #define AR_PHY_TX_FORCED_GAIN_FORCED_ENABLE_PAL 0x01000000
542 #define AR_PHY_TX_FORCED_GAIN_FORCED_ENABLE_PAL_S 24
545 #define AR_PHY_PDADC_TAB_0 (AR_SM_BASE + 0x280)
547 #define AR_PHY_TXGAIN_TABLE (AR_SM_BASE + 0x300)
549 #define AR_PHY_TX_IQCAL_START_9485 (AR_SM_BASE + 0x3c4)
550 #define AR_PHY_TX_IQCAL_START_DO_CAL_9485 0x80000000
551 #define AR_PHY_TX_IQCAL_START_DO_CAL_9485_S 31
552 #define AR_PHY_TX_IQCAL_CONTROL_1_9485 (AR_SM_BASE + 0x3c8)
553 #define AR_PHY_TX_IQCAL_STATUS_B0_9485 (AR_SM_BASE + 0x3f0)
555 #define AR_PHY_TX_IQCAL_CONTROL_1 (AR_SM_BASE + 0x448)
556 #define AR_PHY_TX_IQCAL_START (AR_SM_BASE + 0x440)
557 #define AR_PHY_TX_IQCAL_STATUS_B0 (AR_SM_BASE + 0x48c)
558 #define AR_PHY_TX_IQCAL_CORR_COEFF_B0(_i) (AR_SM_BASE + \
559 (AR_SREV_9485(ah) ? \
560 0x3d0 : 0x450) + ((_i) << 2))
562 #define AR_PHY_WATCHDOG_STATUS (AR_SM_BASE + 0x5c0)
563 #define AR_PHY_WATCHDOG_CTL_1 (AR_SM_BASE + 0x5c4)
564 #define AR_PHY_WATCHDOG_CTL_2 (AR_SM_BASE + 0x5c8)
565 #define AR_PHY_WATCHDOG_CTL (AR_SM_BASE + 0x5cc)
566 #define AR_PHY_ONLY_WARMRESET (AR_SM_BASE + 0x5d0)
567 #define AR_PHY_ONLY_CTL (AR_SM_BASE + 0x5d4)
568 #define AR_PHY_ECO_CTRL (AR_SM_BASE + 0x5dc)
570 #define AR_PHY_BB_THERM_ADC_1 (AR_SM_BASE + 0x248)
571 #define AR_PHY_BB_THERM_ADC_1_INIT_THERM 0x000000ff
572 #define AR_PHY_BB_THERM_ADC_1_INIT_THERM_S 0
574 #define AR_PHY_BB_THERM_ADC_4 (AR_SM_BASE + 0x254)
575 #define AR_PHY_BB_THERM_ADC_4_LATEST_THERM_VALUE 0x000000ff
576 #define AR_PHY_BB_THERM_ADC_4_LATEST_THERM_VALUE_S 0
577 #define AR_PHY_BB_THERM_ADC_4_LATEST_VOLT_VALUE 0x0000ff00
578 #define AR_PHY_BB_THERM_ADC_4_LATEST_VOLT_VALUE_S 8
581 #define AR_PHY_65NM_CH0_SYNTH4 0x1608c
582 #define AR_PHY_SYNTH4_LONG_SHIFT_SELECT 0x00000002
583 #define AR_PHY_SYNTH4_LONG_SHIFT_SELECT_S 1
584 #define AR_PHY_65NM_CH0_SYNTH7 0x16098
585 #define AR_PHY_65NM_CH0_BIAS1 0x160c0
586 #define AR_PHY_65NM_CH0_BIAS2 0x160c4
587 #define AR_PHY_65NM_CH0_BIAS4 0x160cc
588 #define AR_PHY_65NM_CH0_RXTX4 0x1610c
589 #define AR_PHY_65NM_CH0_THERM (AR_SREV_9485(ah) ? 0x1628c : 0x16290)
591 #define AR_PHY_65NM_CH0_THERM_LOCAL 0x80000000
592 #define AR_PHY_65NM_CH0_THERM_LOCAL_S 31
593 #define AR_PHY_65NM_CH0_THERM_START 0x20000000
594 #define AR_PHY_65NM_CH0_THERM_START_S 29
595 #define AR_PHY_65NM_CH0_THERM_SAR_ADC_OUT 0x0000ff00
596 #define AR_PHY_65NM_CH0_THERM_SAR_ADC_OUT_S 8
598 #define AR_PHY_65NM_CH0_RXTX1 0x16100
599 #define AR_PHY_65NM_CH0_RXTX2 0x16104
600 #define AR_PHY_65NM_CH1_RXTX1 0x16500
601 #define AR_PHY_65NM_CH1_RXTX2 0x16504
602 #define AR_PHY_65NM_CH2_RXTX1 0x16900
603 #define AR_PHY_65NM_CH2_RXTX2 0x16904
605 #define AR_CH0_TOP2 (AR_SREV_9485(ah) ? 0x00016284 : 0x0001628c)
606 #define AR_CH0_TOP2_XPABIASLVL 0xf000
607 #define AR_CH0_TOP2_XPABIASLVL_S 12
609 #define AR_CH0_XTAL (AR_SREV_9485(ah) ? 0x16290 : 0x16294)
610 #define AR_CH0_XTAL_CAPINDAC 0x7f000000
611 #define AR_CH0_XTAL_CAPINDAC_S 24
612 #define AR_CH0_XTAL_CAPOUTDAC 0x00fe0000
613 #define AR_CH0_XTAL_CAPOUTDAC_S 17
615 #define AR_PHY_PMU1 0x16c40
616 #define AR_PHY_PMU1_PWD 0x1
617 #define AR_PHY_PMU1_PWD_S 0
619 #define AR_PHY_PMU2 0x16c44
620 #define AR_PHY_PMU2_PGM 0x00200000
621 #define AR_PHY_PMU2_PGM_S 21
623 #define AR_PHY_RX1DB_BIQUAD_LONG_SHIFT 0x00380000
624 #define AR_PHY_RX1DB_BIQUAD_LONG_SHIFT_S 19
625 #define AR_PHY_RX6DB_BIQUAD_LONG_SHIFT 0x00c00000
626 #define AR_PHY_RX6DB_BIQUAD_LONG_SHIFT_S 22
627 #define AR_PHY_LNAGAIN_LONG_SHIFT 0xe0000000
628 #define AR_PHY_LNAGAIN_LONG_SHIFT_S 29
629 #define AR_PHY_MXRGAIN_LONG_SHIFT 0x03000000
630 #define AR_PHY_MXRGAIN_LONG_SHIFT_S 24
631 #define AR_PHY_VGAGAIN_LONG_SHIFT 0x1c000000
632 #define AR_PHY_VGAGAIN_LONG_SHIFT_S 26
633 #define AR_PHY_SCFIR_GAIN_LONG_SHIFT 0x00000001
634 #define AR_PHY_SCFIR_GAIN_LONG_SHIFT_S 0
635 #define AR_PHY_MANRXGAIN_LONG_SHIFT 0x00000002
636 #define AR_PHY_MANRXGAIN_LONG_SHIFT_S 1
639 * SM Field Definitions
641 #define AR_PHY_CL_CAL_ENABLE 0x00000002
642 #define AR_PHY_PARALLEL_CAL_ENABLE 0x00000001
643 #define AR_PHY_TPCRG1_PD_CAL_ENABLE 0x00400000
644 #define AR_PHY_TPCRG1_PD_CAL_ENABLE_S 22
646 #define AR_PHY_ADDAC_PARACTL_OFF_PWDADC 0x00008000
648 #define AR_PHY_FCAL20_CAP_STATUS_0 0x01f00000
649 #define AR_PHY_FCAL20_CAP_STATUS_0_S 20
651 #define AR_PHY_RFBUS_REQ_EN 0x00000001 /* request for RF bus */
652 #define AR_PHY_RFBUS_GRANT_EN 0x00000001 /* RF bus granted */
653 #define AR_PHY_GC_TURBO_MODE 0x00000001 /* set turbo mode bits */
654 #define AR_PHY_GC_TURBO_SHORT 0x00000002 /* set short symbols to turbo mode setting */
655 #define AR_PHY_GC_DYN2040_EN 0x00000004 /* enable dyn 20/40 mode */
656 #define AR_PHY_GC_DYN2040_PRI_ONLY 0x00000008 /* dyn 20/40 - primary only */
657 #define AR_PHY_GC_DYN2040_PRI_CH 0x00000010 /* dyn 20/40 - primary ch offset (0=+10MHz, 1=-10MHz)*/
658 #define AR_PHY_GC_DYN2040_PRI_CH_S 4
659 #define AR_PHY_GC_DYN2040_EXT_CH 0x00000020 /* dyn 20/40 - ext ch spacing (0=20MHz/ 1=25MHz) */
660 #define AR_PHY_GC_HT_EN 0x00000040 /* ht enable */
661 #define AR_PHY_GC_SHORT_GI_40 0x00000080 /* allow short GI for HT 40 */
662 #define AR_PHY_GC_WALSH 0x00000100 /* walsh spatial spreading for 2 chains,2 streams TX */
663 #define AR_PHY_GC_SINGLE_HT_LTF1 0x00000200 /* single length (4us) 1st HT long training symbol */
664 #define AR_PHY_GC_GF_DETECT_EN 0x00000400 /* enable Green Field detection. Only affects rx, not tx */
665 #define AR_PHY_GC_ENABLE_DAC_FIFO 0x00000800 /* fifo between bb and dac */
666 #define AR_PHY_RX_DELAY_DELAY 0x00003FFF /* delay from wakeup to rx ena */
668 #define AR_PHY_CALMODE_IQ 0x00000000
669 #define AR_PHY_CALMODE_ADC_GAIN 0x00000001
670 #define AR_PHY_CALMODE_ADC_DC_PER 0x00000002
671 #define AR_PHY_CALMODE_ADC_DC_INIT 0x00000003
672 #define AR_PHY_SWAP_ALT_CHAIN 0x00000040
673 #define AR_PHY_MODE_OFDM 0x00000000
674 #define AR_PHY_MODE_CCK 0x00000001
675 #define AR_PHY_MODE_DYNAMIC 0x00000004
676 #define AR_PHY_MODE_DYNAMIC_S 2
677 #define AR_PHY_MODE_HALF 0x00000020
678 #define AR_PHY_MODE_QUARTER 0x00000040
679 #define AR_PHY_MAC_CLK_MODE 0x00000080
680 #define AR_PHY_MODE_DYN_CCK_DISABLE 0x00000100
681 #define AR_PHY_MODE_SVD_HALF 0x00000200
682 #define AR_PHY_ACTIVE_EN 0x00000001
683 #define AR_PHY_ACTIVE_DIS 0x00000000
684 #define AR_PHY_FORCE_XPA_CFG 0x000000001
685 #define AR_PHY_FORCE_XPA_CFG_S 0
686 #define AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF 0xFF000000
687 #define AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF_S 24
688 #define AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF 0x00FF0000
689 #define AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF_S 16
690 #define AR_PHY_XPA_TIMING_CTL_FRAME_XPAB_ON 0x0000FF00
691 #define AR_PHY_XPA_TIMING_CTL_FRAME_XPAB_ON_S 8
692 #define AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON 0x000000FF
693 #define AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON_S 0
694 #define AR_PHY_TX_END_TO_A2_RX_ON 0x00FF0000
695 #define AR_PHY_TX_END_TO_A2_RX_ON_S 16
696 #define AR_PHY_TX_END_DATA_START 0x000000FF
697 #define AR_PHY_TX_END_DATA_START_S 0
698 #define AR_PHY_TX_END_PA_ON 0x0000FF00
699 #define AR_PHY_TX_END_PA_ON_S 8
700 #define AR_PHY_TPCRG5_PD_GAIN_OVERLAP 0x0000000F
701 #define AR_PHY_TPCRG5_PD_GAIN_OVERLAP_S 0
702 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1 0x000003F0
703 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1_S 4
704 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2 0x0000FC00
705 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2_S 10
706 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3 0x003F0000
707 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3_S 16
708 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4 0x0FC00000
709 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4_S 22
710 #define AR_PHY_TPCRG1_NUM_PD_GAIN 0x0000c000
711 #define AR_PHY_TPCRG1_NUM_PD_GAIN_S 14
712 #define AR_PHY_TPCRG1_PD_GAIN_1 0x00030000
713 #define AR_PHY_TPCRG1_PD_GAIN_1_S 16
714 #define AR_PHY_TPCRG1_PD_GAIN_2 0x000C0000
715 #define AR_PHY_TPCRG1_PD_GAIN_2_S 18
716 #define AR_PHY_TPCRG1_PD_GAIN_3 0x00300000
717 #define AR_PHY_TPCRG1_PD_GAIN_3_S 20
718 #define AR_PHY_TPCGR1_FORCED_DAC_GAIN 0x0000003e
719 #define AR_PHY_TPCGR1_FORCED_DAC_GAIN_S 1
720 #define AR_PHY_TPCGR1_FORCE_DAC_GAIN 0x00000001
721 #define AR_PHY_TXGAIN_FORCE 0x00000001
722 #define AR_PHY_TXGAIN_FORCE_S 0
723 #define AR_PHY_TXGAIN_FORCED_PADVGNRA 0x00003c00
724 #define AR_PHY_TXGAIN_FORCED_PADVGNRA_S 10
725 #define AR_PHY_TXGAIN_FORCED_PADVGNRB 0x0003c000
726 #define AR_PHY_TXGAIN_FORCED_PADVGNRB_S 14
727 #define AR_PHY_TXGAIN_FORCED_PADVGNRD 0x00c00000
728 #define AR_PHY_TXGAIN_FORCED_PADVGNRD_S 22
729 #define AR_PHY_TXGAIN_FORCED_TXMXRGAIN 0x000003c0
730 #define AR_PHY_TXGAIN_FORCED_TXMXRGAIN_S 6
731 #define AR_PHY_TXGAIN_FORCED_TXBB1DBGAIN 0x0000000e
732 #define AR_PHY_TXGAIN_FORCED_TXBB1DBGAIN_S 1
734 #define AR_PHY_POWER_TX_RATE1 0x9934
735 #define AR_PHY_POWER_TX_RATE2 0x9938
736 #define AR_PHY_POWER_TX_RATE_MAX 0x993c
737 #define AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE 0x00000040
738 #define PHY_AGC_CLR 0x10000000
739 #define RFSILENT_BB 0x00002000
740 #define AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK 0xFFF
741 #define AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_SIGNED_BIT 0x800
742 #define AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT 320
743 #define AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK 0x0001
744 #define AR_PHY_RX_DELAY_DELAY 0x00003FFF
745 #define AR_PHY_CCK_TX_CTRL_JAPAN 0x00000010
746 #define AR_PHY_SPECTRAL_SCAN_ENABLE 0x00000001
747 #define AR_PHY_SPECTRAL_SCAN_ENABLE_S 0
748 #define AR_PHY_SPECTRAL_SCAN_ACTIVE 0x00000002
749 #define AR_PHY_SPECTRAL_SCAN_ACTIVE_S 1
750 #define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD 0x000000F0
751 #define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD_S 4
752 #define AR_PHY_SPECTRAL_SCAN_PERIOD 0x0000FF00
753 #define AR_PHY_SPECTRAL_SCAN_PERIOD_S 8
754 #define AR_PHY_SPECTRAL_SCAN_COUNT 0x00FF0000
755 #define AR_PHY_SPECTRAL_SCAN_COUNT_S 16
756 #define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT 0x01000000
757 #define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT_S 24
758 #define AR_PHY_CHANNEL_STATUS_RX_CLEAR 0x00000004
759 #define AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT 0x01fc0000
760 #define AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_S 18
761 #define AR_PHY_TX_IQCAL_START_DO_CAL 0x00000001
762 #define AR_PHY_TX_IQCAL_START_DO_CAL_S 0
764 #define AR_PHY_TX_IQCAL_STATUS_FAILED 0x00000001
765 #define AR_PHY_CALIBRATED_GAINS_0 0x3e
766 #define AR_PHY_CALIBRATED_GAINS_0_S 1
768 #define AR_PHY_TX_IQCAL_CORR_COEFF_00_COEFF_TABLE 0x00003fff
769 #define AR_PHY_TX_IQCAL_CORR_COEFF_00_COEFF_TABLE_S 0
770 #define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE 0x0fffc000
771 #define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE_S 14
773 #define AR_PHY_65NM_CH0_RXTX4_THERM_ON 0x10000000
774 #define AR_PHY_65NM_CH0_RXTX4_THERM_ON_S 28
777 * Channel 1 Register Map
779 #define AR_CHAN1_BASE 0xa800
781 #define AR_PHY_EXT_CCA_1 (AR_CHAN1_BASE + 0x30)
782 #define AR_PHY_TX_PHASE_RAMP_1 (AR_CHAN1_BASE + 0xd0)
783 #define AR_PHY_ADC_GAIN_DC_CORR_1 (AR_CHAN1_BASE + 0xd4)
785 #define AR_PHY_SPUR_REPORT_1 (AR_CHAN1_BASE + 0xa8)
786 #define AR_PHY_CHAN_INFO_TAB_1 (AR_CHAN1_BASE + 0x300)
787 #define AR_PHY_RX_IQCAL_CORR_B1 (AR_CHAN1_BASE + 0xdc)
790 * Channel 1 Field Definitions
792 #define AR_PHY_CH1_EXT_MINCCA_PWR 0x01FF0000
793 #define AR_PHY_CH1_EXT_MINCCA_PWR_S 16
798 #define AR_AGC1_BASE 0xae00
800 #define AR_PHY_FORCEMAX_GAINS_1 (AR_AGC1_BASE + 0x4)
801 #define AR_PHY_EXT_ATTEN_CTL_1 (AR_AGC1_BASE + 0x18)
802 #define AR_PHY_CCA_1 (AR_AGC1_BASE + 0x1c)
803 #define AR_PHY_CCA_CTRL_1 (AR_AGC1_BASE + 0x20)
804 #define AR_PHY_RSSI_1 (AR_AGC1_BASE + 0x180)
805 #define AR_PHY_SPUR_CCK_REP_1 (AR_AGC1_BASE + 0x184)
806 #define AR_PHY_RX_OCGAIN_2 (AR_AGC1_BASE + 0x200)
809 * AGC 1 Field Definitions
811 #define AR_PHY_CH1_MINCCA_PWR 0x1FF00000
812 #define AR_PHY_CH1_MINCCA_PWR_S 20
817 #define AR_SM1_BASE 0xb200
819 #define AR_PHY_SWITCH_CHAIN_1 (AR_SM1_BASE + 0x84)
820 #define AR_PHY_FCAL_2_1 (AR_SM1_BASE + 0xd0)
821 #define AR_PHY_DFT_TONE_CTL_1 (AR_SM1_BASE + 0xd4)
822 #define AR_PHY_CL_TAB_1 (AR_SM1_BASE + 0x100)
823 #define AR_PHY_CHAN_INFO_GAIN_1 (AR_SM1_BASE + 0x180)
824 #define AR_PHY_TPC_4_B1 (AR_SM1_BASE + 0x204)
825 #define AR_PHY_TPC_5_B1 (AR_SM1_BASE + 0x208)
826 #define AR_PHY_TPC_6_B1 (AR_SM1_BASE + 0x20c)
827 #define AR_PHY_TPC_11_B1 (AR_SM1_BASE + 0x220)
828 #define AR_PHY_PDADC_TAB_1 (AR_SM1_BASE + 0x240)
829 #define AR_PHY_TX_IQCAL_STATUS_B1 (AR_SM1_BASE + 0x48c)
830 #define AR_PHY_TX_IQCAL_CORR_COEFF_B1(_i) (AR_SM_BASE + 0x450 + ((_i) << 2))
833 * Channel 2 Register Map
835 #define AR_CHAN2_BASE 0xb800
837 #define AR_PHY_EXT_CCA_2 (AR_CHAN2_BASE + 0x30)
838 #define AR_PHY_TX_PHASE_RAMP_2 (AR_CHAN2_BASE + 0xd0)
839 #define AR_PHY_ADC_GAIN_DC_CORR_2 (AR_CHAN2_BASE + 0xd4)
841 #define AR_PHY_SPUR_REPORT_2 (AR_CHAN2_BASE + 0xa8)
842 #define AR_PHY_CHAN_INFO_TAB_2 (AR_CHAN2_BASE + 0x300)
843 #define AR_PHY_RX_IQCAL_CORR_B2 (AR_CHAN2_BASE + 0xdc)
846 * Channel 2 Field Definitions
848 #define AR_PHY_CH2_EXT_MINCCA_PWR 0x01FF0000
849 #define AR_PHY_CH2_EXT_MINCCA_PWR_S 16
853 #define AR_AGC2_BASE 0xbe00
855 #define AR_PHY_FORCEMAX_GAINS_2 (AR_AGC2_BASE + 0x4)
856 #define AR_PHY_EXT_ATTEN_CTL_2 (AR_AGC2_BASE + 0x18)
857 #define AR_PHY_CCA_2 (AR_AGC2_BASE + 0x1c)
858 #define AR_PHY_CCA_CTRL_2 (AR_AGC2_BASE + 0x20)
859 #define AR_PHY_RSSI_2 (AR_AGC2_BASE + 0x180)
862 * AGC 2 Field Definitions
864 #define AR_PHY_CH2_MINCCA_PWR 0x1FF00000
865 #define AR_PHY_CH2_MINCCA_PWR_S 20
870 #define AR_SM2_BASE 0xc200
872 #define AR_PHY_SWITCH_CHAIN_2 (AR_SM2_BASE + 0x84)
873 #define AR_PHY_FCAL_2_2 (AR_SM2_BASE + 0xd0)
874 #define AR_PHY_DFT_TONE_CTL_2 (AR_SM2_BASE + 0xd4)
875 #define AR_PHY_CL_TAB_2 (AR_SM2_BASE + 0x100)
876 #define AR_PHY_CHAN_INFO_GAIN_2 (AR_SM2_BASE + 0x180)
877 #define AR_PHY_TPC_4_B2 (AR_SM2_BASE + 0x204)
878 #define AR_PHY_TPC_5_B2 (AR_SM2_BASE + 0x208)
879 #define AR_PHY_TPC_6_B2 (AR_SM2_BASE + 0x20c)
880 #define AR_PHY_TPC_11_B2 (AR_SM2_BASE + 0x220)
881 #define AR_PHY_PDADC_TAB_2 (AR_SM2_BASE + 0x240)
882 #define AR_PHY_TX_IQCAL_STATUS_B2 (AR_SM2_BASE + 0x48c)
883 #define AR_PHY_TX_IQCAL_CORR_COEFF_B2(_i) (AR_SM2_BASE + 0x450 + ((_i) << 2))
885 #define AR_PHY_TX_IQCAL_STATUS_B2_FAILED 0x00000001
890 #define AR_AGC3_BASE 0xce00
892 #define AR_PHY_RSSI_3 (AR_AGC3_BASE + 0x180)
895 * Misc helper defines
897 #define AR_PHY_CHAIN_OFFSET (AR_CHAN1_BASE - AR_CHAN_BASE)
899 #define AR_PHY_NEW_ADC_DC_GAIN_CORR(_i) (AR_PHY_ADC_GAIN_DC_CORR_0 + (AR_PHY_CHAIN_OFFSET * (_i)))
900 #define AR_PHY_NEW_ADC_DC_GAIN_CORR_9300_10(_i) (AR_PHY_ADC_GAIN_DC_CORR_0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i)))
901 #define AR_PHY_SWITCH_CHAIN(_i) (AR_PHY_SWITCH_CHAIN_0 + (AR_PHY_CHAIN_OFFSET * (_i)))
902 #define AR_PHY_EXT_ATTEN_CTL(_i) (AR_PHY_EXT_ATTEN_CTL_0 + (AR_PHY_CHAIN_OFFSET * (_i)))
904 #define AR_PHY_RXGAIN(_i) (AR_PHY_FORCEMAX_GAINS_0 + (AR_PHY_CHAIN_OFFSET * (_i)))
905 #define AR_PHY_TPCRG5(_i) (AR_PHY_TPC_5_B0 + (AR_PHY_CHAIN_OFFSET * (_i)))
906 #define AR_PHY_PDADC_TAB(_i) (AR_PHY_PDADC_TAB_0 + (AR_PHY_CHAIN_OFFSET * (_i)))
908 #define AR_PHY_CAL_MEAS_0(_i) (AR_PHY_IQ_ADC_MEAS_0_B0 + (AR_PHY_CHAIN_OFFSET * (_i)))
909 #define AR_PHY_CAL_MEAS_1(_i) (AR_PHY_IQ_ADC_MEAS_1_B0 + (AR_PHY_CHAIN_OFFSET * (_i)))
910 #define AR_PHY_CAL_MEAS_2(_i) (AR_PHY_IQ_ADC_MEAS_2_B0 + (AR_PHY_CHAIN_OFFSET * (_i)))
911 #define AR_PHY_CAL_MEAS_3(_i) (AR_PHY_IQ_ADC_MEAS_3_B0 + (AR_PHY_CHAIN_OFFSET * (_i)))
912 #define AR_PHY_CAL_MEAS_0_9300_10(_i) (AR_PHY_IQ_ADC_MEAS_0_B0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i)))
913 #define AR_PHY_CAL_MEAS_1_9300_10(_i) (AR_PHY_IQ_ADC_MEAS_1_B0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i)))
914 #define AR_PHY_CAL_MEAS_2_9300_10(_i) (AR_PHY_IQ_ADC_MEAS_2_B0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i)))
915 #define AR_PHY_CAL_MEAS_3_9300_10(_i) (AR_PHY_IQ_ADC_MEAS_3_B0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i)))
917 #define AR_PHY_WATCHDOG_NON_IDLE_ENABLE 0x00000001
918 #define AR_PHY_WATCHDOG_IDLE_ENABLE 0x00000002
919 #define AR_PHY_WATCHDOG_IDLE_MASK 0xFFFF0000
920 #define AR_PHY_WATCHDOG_NON_IDLE_MASK 0x0000FFFC
922 #define AR_PHY_WATCHDOG_RST_ENABLE 0x00000002
923 #define AR_PHY_WATCHDOG_IRQ_ENABLE 0x00000004
924 #define AR_PHY_WATCHDOG_CNTL2_MASK 0xFFFFFFF9
926 #define AR_PHY_WATCHDOG_INFO 0x00000007
927 #define AR_PHY_WATCHDOG_INFO_S 0
928 #define AR_PHY_WATCHDOG_DET_HANG 0x00000008
929 #define AR_PHY_WATCHDOG_DET_HANG_S 3
930 #define AR_PHY_WATCHDOG_RADAR_SM 0x000000F0
931 #define AR_PHY_WATCHDOG_RADAR_SM_S 4
932 #define AR_PHY_WATCHDOG_RX_OFDM_SM 0x00000F00
933 #define AR_PHY_WATCHDOG_RX_OFDM_SM_S 8
934 #define AR_PHY_WATCHDOG_RX_CCK_SM 0x0000F000
935 #define AR_PHY_WATCHDOG_RX_CCK_SM_S 12
936 #define AR_PHY_WATCHDOG_TX_OFDM_SM 0x000F0000
937 #define AR_PHY_WATCHDOG_TX_OFDM_SM_S 16
938 #define AR_PHY_WATCHDOG_TX_CCK_SM 0x00F00000
939 #define AR_PHY_WATCHDOG_TX_CCK_SM_S 20
940 #define AR_PHY_WATCHDOG_AGC_SM 0x0F000000
941 #define AR_PHY_WATCHDOG_AGC_SM_S 24
942 #define AR_PHY_WATCHDOG_SRCH_SM 0xF0000000
943 #define AR_PHY_WATCHDOG_SRCH_SM_S 28
945 #define AR_PHY_WATCHDOG_STATUS_CLR 0x00000008
950 #define AR_PHY_XPA_TIMING_CTL (AR_SM_BASE + 0x64)
952 #define AR_PHY_PAPRD_AM2AM (AR_CHAN_BASE + 0xe4)
953 #define AR_PHY_PAPRD_AM2AM_MASK 0x01ffffff
954 #define AR_PHY_PAPRD_AM2AM_MASK_S 0
956 #define AR_PHY_PAPRD_AM2PM (AR_CHAN_BASE + 0xe8)
957 #define AR_PHY_PAPRD_AM2PM_MASK 0x01ffffff
958 #define AR_PHY_PAPRD_AM2PM_MASK_S 0
960 #define AR_PHY_PAPRD_HT40 (AR_CHAN_BASE + 0xec)
961 #define AR_PHY_PAPRD_HT40_MASK 0x01ffffff
962 #define AR_PHY_PAPRD_HT40_MASK_S 0
964 #define AR_PHY_PAPRD_CTRL0_B0 (AR_CHAN_BASE + 0xf0)
965 #define AR_PHY_PAPRD_CTRL0_B1 (AR_CHAN1_BASE + 0xf0)
966 #define AR_PHY_PAPRD_CTRL0_B2 (AR_CHAN2_BASE + 0xf0)
967 #define AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE 0x00000001
968 #define AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE_S 0
969 #define AR_PHY_PAPRD_CTRL0_USE_SINGLE_TABLE_MASK 0x00000002
970 #define AR_PHY_PAPRD_CTRL0_USE_SINGLE_TABLE_MASK_S 1
971 #define AR_PHY_PAPRD_CTRL0_PAPRD_MAG_THRSH 0xf8000000
972 #define AR_PHY_PAPRD_CTRL0_PAPRD_MAG_THRSH_S 27
974 #define AR_PHY_PAPRD_CTRL1_B0 (AR_CHAN_BASE + 0xf4)
975 #define AR_PHY_PAPRD_CTRL1_B1 (AR_CHAN1_BASE + 0xf4)
976 #define AR_PHY_PAPRD_CTRL1_B2 (AR_CHAN2_BASE + 0xf4)
977 #define AR_PHY_PAPRD_CTRL1_ADAPTIVE_SCALING_ENA 0x00000001
978 #define AR_PHY_PAPRD_CTRL1_ADAPTIVE_SCALING_ENA_S 0
979 #define AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2AM_ENABLE 0x00000002
980 #define AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2AM_ENABLE_S 1
981 #define AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2PM_ENABLE 0x00000004
982 #define AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2PM_ENABLE_S 2
983 #define AR_PHY_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL 0x000001f8
984 #define AR_PHY_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL_S 3
985 #define AR_PHY_PAPRD_CTRL1_PA_GAIN_SCALE_FACT_MASK 0x0001fe00
986 #define AR_PHY_PAPRD_CTRL1_PA_GAIN_SCALE_FACT_MASK_S 9
987 #define AR_PHY_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACT 0x0ffe0000
988 #define AR_PHY_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACT_S 17
990 #define AR_PHY_PAPRD_TRAINER_CNTL1 (AR_SM_BASE + \
991 (AR_SREV_9485(ah) ? \
993 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_CF_PAPRD_TRAIN_ENABLE 0x00000001
994 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_CF_PAPRD_TRAIN_ENABLE_S 0
995 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING 0x0000007e
996 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING_S 1
997 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE 0x00000100
998 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE_S 8
999 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE 0x00000200
1000 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE_S 9
1001 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE 0x00000400
1002 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE_S 10
1003 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_ENABLE 0x00000800
1004 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_ENABLE_S 11
1005 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP 0x0003f000
1006 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP_S 12
1008 #define AR_PHY_PAPRD_TRAINER_CNTL2 (AR_SM_BASE + \
1009 (AR_SREV_9485(ah) ? \
1011 #define AR_PHY_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN 0xFFFFFFFF
1012 #define AR_PHY_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_S 0
1014 #define AR_PHY_PAPRD_TRAINER_CNTL3 (AR_SM_BASE + \
1015 (AR_SREV_9485(ah) ? \
1017 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE 0x0000003f
1018 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE_S 0
1019 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP 0x00000fc0
1020 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP_S 6
1021 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL 0x0001f000
1022 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL_S 12
1023 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES 0x000e0000
1024 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES_S 17
1025 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN 0x00f00000
1026 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN_S 20
1027 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN 0x0f000000
1028 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN_S 24
1029 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE 0x20000000
1030 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE_S 29
1032 #define AR_PHY_PAPRD_TRAINER_CNTL4 (AR_SM_BASE + \
1033 (AR_SREV_9485(ah) ? \
1035 #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES 0x03ff0000
1036 #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES_S 16
1037 #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA 0x0000f000
1038 #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA_S 12
1039 #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR 0x00000fff
1040 #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR_S 0
1042 #define AR_PHY_PAPRD_PRE_POST_SCALE_0_B0 (AR_CHAN_BASE + 0x100)
1043 #define AR_PHY_PAPRD_PRE_POST_SCALE_1_B0 (AR_CHAN_BASE + 0x104)
1044 #define AR_PHY_PAPRD_PRE_POST_SCALE_2_B0 (AR_CHAN_BASE + 0x108)
1045 #define AR_PHY_PAPRD_PRE_POST_SCALE_3_B0 (AR_CHAN_BASE + 0x10c)
1046 #define AR_PHY_PAPRD_PRE_POST_SCALE_4_B0 (AR_CHAN_BASE + 0x110)
1047 #define AR_PHY_PAPRD_PRE_POST_SCALE_5_B0 (AR_CHAN_BASE + 0x114)
1048 #define AR_PHY_PAPRD_PRE_POST_SCALE_6_B0 (AR_CHAN_BASE + 0x118)
1049 #define AR_PHY_PAPRD_PRE_POST_SCALE_7_B0 (AR_CHAN_BASE + 0x11c)
1050 #define AR_PHY_PAPRD_PRE_POST_SCALING 0x3FFFF
1051 #define AR_PHY_PAPRD_PRE_POST_SCALING_S 0
1053 #define AR_PHY_PAPRD_TRAINER_STAT1 (AR_SM_BASE + 0x4a0)
1054 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE 0x00000001
1055 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE_S 0
1056 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_INCOMPLETE 0x00000002
1057 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_INCOMPLETE_S 1
1058 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_CORR_ERR 0x00000004
1059 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_CORR_ERR_S 2
1060 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_ACTIVE 0x00000008
1061 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_ACTIVE_S 3
1062 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_RX_GAIN_IDX 0x000001f0
1063 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_RX_GAIN_IDX_S 4
1064 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR 0x0001fe00
1065 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR_S 9
1067 #define AR_PHY_PAPRD_TRAINER_STAT2 (AR_SM_BASE + 0x4a4)
1068 #define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL 0x0000ffff
1069 #define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL_S 0
1070 #define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_COARSE_IDX 0x001f0000
1071 #define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_COARSE_IDX_S 16
1072 #define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_FINE_IDX 0x00600000
1073 #define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_FINE_IDX_S 21
1075 #define AR_PHY_PAPRD_TRAINER_STAT3 (AR_SM_BASE + 0x4a8)
1076 #define AR_PHY_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT 0x000fffff
1077 #define AR_PHY_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT_S 0
1079 #define AR_PHY_PAPRD_MEM_TAB_B0 (AR_CHAN_BASE + 0x120)
1080 #define AR_PHY_PAPRD_MEM_TAB_B1 (AR_CHAN1_BASE + 0x120)
1081 #define AR_PHY_PAPRD_MEM_TAB_B2 (AR_CHAN2_BASE + 0x120)
1083 #define AR_PHY_PA_GAIN123_B0 (AR_CHAN_BASE + 0xf8)
1084 #define AR_PHY_PA_GAIN123_B1 (AR_CHAN1_BASE + 0xf8)
1085 #define AR_PHY_PA_GAIN123_B2 (AR_CHAN2_BASE + 0xf8)
1086 #define AR_PHY_PA_GAIN123_PA_GAIN1 0x3FF
1087 #define AR_PHY_PA_GAIN123_PA_GAIN1_S 0
1089 #define AR_PHY_POWERTX_RATE5 (AR_SM_BASE + 0x1d0)
1090 #define AR_PHY_POWERTX_RATE5_POWERTXHT20_0 0x3F
1091 #define AR_PHY_POWERTX_RATE5_POWERTXHT20_0_S 0
1093 #define AR_PHY_POWERTX_RATE6 (AR_SM_BASE + 0x1d4)
1094 #define AR_PHY_POWERTX_RATE6_POWERTXHT20_5 0x3F00
1095 #define AR_PHY_POWERTX_RATE6_POWERTXHT20_5_S 8
1097 #define AR_PHY_POWERTX_RATE8 (AR_SM_BASE + 0x1dc)
1098 #define AR_PHY_POWERTX_RATE8_POWERTXHT40_5 0x3F00
1099 #define AR_PHY_POWERTX_RATE8_POWERTXHT40_5_S 8
1101 void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx);
1103 #endif /* AR9003_PHY_H */