2 * Copyright (c) 2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 ATH_BT_COEX_MODE_LEGACY, /* legacy rx_clear mode */
21 ATH_BT_COEX_MODE_UNSLOTTED, /* untimed/unslotted mode */
22 ATH_BT_COEX_MODE_SLOTTED, /* slotted mode */
23 ATH_BT_COEX_MODE_DISALBED, /* coexistence disabled */
26 struct ath_btcoex_config {
28 bool bt_txstate_extend;
29 bool bt_txframe_extend;
30 enum ath_bt_mode bt_mode; /* coexistence mode */
31 bool bt_quiet_collision;
32 bool bt_rxclear_polarity; /* invert rx_clear as WLAN_ACTIVE*/
34 u8 bt_first_slot_time;
35 bool bt_hold_rx_clear;
38 static const u16 ath_subsysid_tbl[] = {
39 AR9280_COEX2WIRE_SUBSYSID,
40 AT9285_COEX3WIRE_SA_SUBSYSID,
41 AT9285_COEX3WIRE_DA_SUBSYSID
45 * Checks the subsystem id of the device to see if it
48 bool ath9k_hw_btcoex_supported(struct ath_hw *ah)
52 if (!ah->hw_version.subsysid)
55 for (i = 0; i < ARRAY_SIZE(ath_subsysid_tbl); i++)
56 if (ah->hw_version.subsysid == ath_subsysid_tbl[i])
62 void ath9k_hw_init_btcoex_hw(struct ath_hw *ah, int qnum)
64 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
65 const struct ath_btcoex_config ath_bt_config = {
67 .bt_txstate_extend = true,
68 .bt_txframe_extend = true,
69 .bt_mode = ATH_BT_COEX_MODE_SLOTTED,
70 .bt_quiet_collision = true,
71 .bt_rxclear_polarity = true,
72 .bt_priority_time = 2,
73 .bt_first_slot_time = 5,
74 .bt_hold_rx_clear = true,
78 btcoex_hw->bt_coex_mode =
79 (btcoex_hw->bt_coex_mode & AR_BT_QCU_THRESH) |
80 SM(ath_bt_config.bt_time_extend, AR_BT_TIME_EXTEND) |
81 SM(ath_bt_config.bt_txstate_extend, AR_BT_TXSTATE_EXTEND) |
82 SM(ath_bt_config.bt_txframe_extend, AR_BT_TX_FRAME_EXTEND) |
83 SM(ath_bt_config.bt_mode, AR_BT_MODE) |
84 SM(ath_bt_config.bt_quiet_collision, AR_BT_QUIET) |
85 SM(ath_bt_config.bt_rxclear_polarity, AR_BT_RX_CLEAR_POLARITY) |
86 SM(ath_bt_config.bt_priority_time, AR_BT_PRIORITY_TIME) |
87 SM(ath_bt_config.bt_first_slot_time, AR_BT_FIRST_SLOT_TIME) |
88 SM(qnum, AR_BT_QCU_THRESH);
90 btcoex_hw->bt_coex_mode2 =
91 SM(ath_bt_config.bt_hold_rx_clear, AR_BT_HOLD_RX_CLEAR) |
92 SM(ATH_BTCOEX_BMISS_THRESH, AR_BT_BCN_MISS_THRESH) |
95 for (i = 0; i < 32; i++)
96 ah->hw_gen_timers.gen_timer_index[(debruijn32 << i) >> 27] = i;
98 EXPORT_SYMBOL(ath9k_hw_init_btcoex_hw);
100 void ath9k_hw_btcoex_init_2wire(struct ath_hw *ah)
102 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
104 /* connect bt_active to baseband */
105 REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL,
106 (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF |
107 AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF));
109 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
110 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);
112 /* Set input mux for bt_active to gpio pin */
113 REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
114 AR_GPIO_INPUT_MUX1_BT_ACTIVE,
115 btcoex_hw->btactive_gpio);
117 /* Configure the desired gpio port for input */
118 ath9k_hw_cfg_gpio_input(ah, btcoex_hw->btactive_gpio);
120 EXPORT_SYMBOL(ath9k_hw_btcoex_init_2wire);
122 void ath9k_hw_btcoex_init_3wire(struct ath_hw *ah)
124 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
127 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
128 (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB |
129 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB));
131 /* Set input mux for bt_prority_async and
132 * bt_active_async to GPIO pins */
133 REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
134 AR_GPIO_INPUT_MUX1_BT_ACTIVE,
135 btcoex_hw->btactive_gpio);
137 REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
138 AR_GPIO_INPUT_MUX1_BT_PRIORITY,
139 btcoex_hw->btpriority_gpio);
141 /* Configure the desired GPIO ports for input */
143 ath9k_hw_cfg_gpio_input(ah, btcoex_hw->btactive_gpio);
144 ath9k_hw_cfg_gpio_input(ah, btcoex_hw->btpriority_gpio);
146 EXPORT_SYMBOL(ath9k_hw_btcoex_init_3wire);
148 static void ath9k_hw_btcoex_enable_2wire(struct ath_hw *ah)
150 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
152 /* Configure the desired GPIO port for TX_FRAME output */
153 ath9k_hw_cfg_output(ah, btcoex_hw->wlanactive_gpio,
154 AR_GPIO_OUTPUT_MUX_AS_TX_FRAME);
157 void ath9k_hw_btcoex_set_weight(struct ath_hw *ah,
161 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
163 btcoex_hw->bt_coex_weights = SM(bt_weight, AR_BTCOEX_BT_WGHT) |
164 SM(wlan_weight, AR_BTCOEX_WL_WGHT);
166 EXPORT_SYMBOL(ath9k_hw_btcoex_set_weight);
168 static void ath9k_hw_btcoex_enable_3wire(struct ath_hw *ah)
170 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
174 * Program coex mode and weight registers to
177 REG_WRITE(ah, AR_BT_COEX_MODE, btcoex_hw->bt_coex_mode);
178 REG_WRITE(ah, AR_BT_COEX_WEIGHT, btcoex_hw->bt_coex_weights);
179 REG_WRITE(ah, AR_BT_COEX_MODE2, btcoex_hw->bt_coex_mode2);
181 if (AR_SREV_9271(ah)) {
182 val = REG_READ(ah, 0x50040);
184 REG_WRITE(ah, 0x50040, val);
187 REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1);
188 REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0);
190 ath9k_hw_cfg_output(ah, btcoex_hw->wlanactive_gpio,
191 AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL);
194 void ath9k_hw_btcoex_enable(struct ath_hw *ah)
196 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
198 switch (btcoex_hw->scheme) {
199 case ATH_BTCOEX_CFG_NONE:
201 case ATH_BTCOEX_CFG_2WIRE:
202 ath9k_hw_btcoex_enable_2wire(ah);
204 case ATH_BTCOEX_CFG_3WIRE:
205 ath9k_hw_btcoex_enable_3wire(ah);
209 REG_RMW(ah, AR_GPIO_PDPU,
210 (0x2 << (btcoex_hw->btactive_gpio * 2)),
211 (0x3 << (btcoex_hw->btactive_gpio * 2)));
213 ah->btcoex_hw.enabled = true;
215 EXPORT_SYMBOL(ath9k_hw_btcoex_enable);
217 void ath9k_hw_btcoex_disable(struct ath_hw *ah)
219 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
221 ath9k_hw_set_gpio(ah, btcoex_hw->wlanactive_gpio, 0);
223 ath9k_hw_cfg_output(ah, btcoex_hw->wlanactive_gpio,
224 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
226 if (btcoex_hw->scheme == ATH_BTCOEX_CFG_3WIRE) {
227 REG_WRITE(ah, AR_BT_COEX_MODE, AR_BT_QUIET | AR_BT_MODE);
228 REG_WRITE(ah, AR_BT_COEX_WEIGHT, 0);
229 REG_WRITE(ah, AR_BT_COEX_MODE2, 0);
232 ah->btcoex_hw.enabled = false;
234 EXPORT_SYMBOL(ath9k_hw_btcoex_disable);