drivers/net/wireless/ath/ath9k/eeprom_def.c

   1 /*
   2  * Copyright (c) 2008-2009 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include "hw.h"
  18 #include "ar9002_phy.h"
  19
  20 static void ath9k_get_txgain_index(struct ath_hw *ah,
  21                 struct ath9k_channel *chan,
  22                 struct calDataPerFreqOpLoop *rawDatasetOpLoop,
  23                 u8 *calChans,  u16 availPiers, u8 *pwr, u8 *pcdacIdx)
  24 {
  25         u8 pcdac, i = 0;
  26         u16 idxL = 0, idxR = 0, numPiers;
  27         bool match;
  28         struct chan_centers centers;
  29
  30         ath9k_hw_get_channel_centers(ah, chan, &centers);
  31
  32         for (numPiers = 0; numPiers < availPiers; numPiers++)
  33                 if (calChans[numPiers] == AR5416_BCHAN_UNUSED)
  34                         break;
  35
  36         match = ath9k_hw_get_lower_upper_index(
  37                         (u8)FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan)),
  38                         calChans, numPiers, &idxL, &idxR);
  39         if (match) {
  40                 pcdac = rawDatasetOpLoop[idxL].pcdac[0][0];
  41                 *pwr = rawDatasetOpLoop[idxL].pwrPdg[0][0];
  42         } else {
  43                 pcdac = rawDatasetOpLoop[idxR].pcdac[0][0];
  44                 *pwr = (rawDatasetOpLoop[idxL].pwrPdg[0][0] +
  45                                 rawDatasetOpLoop[idxR].pwrPdg[0][0])/2;
  46         }
  47
  48         while (pcdac > ah->originalGain[i] &&
  49                         i < (AR9280_TX_GAIN_TABLE_SIZE - 1))
  50                 i++;
  51
  52         *pcdacIdx = i;
  53         return;
  54 }
  55
  56 static void ath9k_olc_get_pdadcs(struct ath_hw *ah,
  57                                 u32 initTxGain,
  58                                 int txPower,
  59                                 u8 *pPDADCValues)
  60 {
  61         u32 i;
  62         u32 offset;
  63
  64         REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL6_0,
  65                         AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);
  66         REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL6_1,
  67                         AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);
  68
  69         REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL7,
  70                         AR_PHY_TX_PWRCTRL_INIT_TX_GAIN, initTxGain);
  71
  72         offset = txPower;
  73         for (i = 0; i < AR5416_NUM_PDADC_VALUES; i++)
  74                 if (i < offset)
  75                         pPDADCValues[i] = 0x0;
  76                 else
  77                         pPDADCValues[i] = 0xFF;
  78 }
  79
  80 static int ath9k_hw_def_get_eeprom_ver(struct ath_hw *ah)
  81 {
  82         return ((ah->eeprom.def.baseEepHeader.version >> 12) & 0xF);
  83 }
  84
  85 static int ath9k_hw_def_get_eeprom_rev(struct ath_hw *ah)
  86 {
  87         return ((ah->eeprom.def.baseEepHeader.version) & 0xFFF);
  88 }
  89
  90 static bool ath9k_hw_def_fill_eeprom(struct ath_hw *ah)
  91 {
  92 #define SIZE_EEPROM_DEF (sizeof(struct ar5416_eeprom_def) / sizeof(u16))
  93         struct ath_common *common = ath9k_hw_common(ah);
  94         u16 *eep_data = (u16 *)&ah->eeprom.def;
  95         int addr, ar5416_eep_start_loc = 0x100;
  96
  97         for (addr = 0; addr < SIZE_EEPROM_DEF; addr++) {
  98                 if (!ath9k_hw_nvram_read(common, addr + ar5416_eep_start_loc,
  99                                          eep_data)) {
 100                         ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
 101                                   "Unable to read eeprom region\n");
 102                         return false;
 103                 }
 104                 eep_data++;
 105         }
 106         return true;
 107 #undef SIZE_EEPROM_DEF
 108 }
 109
 110 static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
 111 {
 112         struct ar5416_eeprom_def *eep =
 113                 (struct ar5416_eeprom_def *) &ah->eeprom.def;
 114         struct ath_common *common = ath9k_hw_common(ah);
 115         u16 *eepdata, temp, magic, magic2;
 116         u32 sum = 0, el;
 117         bool need_swap = false;
 118         int i, addr, size;
 119
 120         if (!ath9k_hw_nvram_read(common, AR5416_EEPROM_MAGIC_OFFSET, &magic)) {
 121                 ath_print(common, ATH_DBG_FATAL, "Reading Magic # failed\n");
 122                 return false;
 123         }
 124
 125         if (!ath9k_hw_use_flash(ah)) {
 126                 ath_print(common, ATH_DBG_EEPROM,
 127                           "Read Magic = 0x%04X\n", magic);
 128
 129                 if (magic != AR5416_EEPROM_MAGIC) {
 130                         magic2 = swab16(magic);
 131
 132                         if (magic2 == AR5416_EEPROM_MAGIC) {
 133                                 size = sizeof(struct ar5416_eeprom_def);
 134                                 need_swap = true;
 135                                 eepdata = (u16 *) (&ah->eeprom);
 136
 137                                 for (addr = 0; addr < size / sizeof(u16); addr++) {
 138                                         temp = swab16(*eepdata);
 139                                         *eepdata = temp;
 140                                         eepdata++;
 141                                 }
 142                         } else {
 143                                 ath_print(common, ATH_DBG_FATAL,
 144                                           "Invalid EEPROM Magic. "
 145                                           "Endianness mismatch.\n");
 146                                 return -EINVAL;
 147                         }
 148                 }
 149         }
 150
 151         ath_print(common, ATH_DBG_EEPROM, "need_swap = %s.\n",
 152                   need_swap ? "True" : "False");
 153
 154         if (need_swap)
 155                 el = swab16(ah->eeprom.def.baseEepHeader.length);
 156         else
 157                 el = ah->eeprom.def.baseEepHeader.length;
 158
 159         if (el > sizeof(struct ar5416_eeprom_def))
 160                 el = sizeof(struct ar5416_eeprom_def) / sizeof(u16);
 161         else
 162                 el = el / sizeof(u16);
 163
 164         eepdata = (u16 *)(&ah->eeprom);
 165
 166         for (i = 0; i < el; i++)
 167                 sum ^= *eepdata++;
 168
 169         if (need_swap) {
 170                 u32 integer, j;
 171                 u16 word;
 172
 173                 ath_print(common, ATH_DBG_EEPROM,
 174                           "EEPROM Endianness is not native.. Changing.\n");
 175
 176                 word = swab16(eep->baseEepHeader.length);
 177                 eep->baseEepHeader.length = word;
 178
 179                 word = swab16(eep->baseEepHeader.checksum);
 180                 eep->baseEepHeader.checksum = word;
 181
 182                 word = swab16(eep->baseEepHeader.version);
 183                 eep->baseEepHeader.version = word;
 184
 185                 word = swab16(eep->baseEepHeader.regDmn[0]);
 186                 eep->baseEepHeader.regDmn[0] = word;
 187
 188                 word = swab16(eep->baseEepHeader.regDmn[1]);
 189                 eep->baseEepHeader.regDmn[1] = word;
 190
 191                 word = swab16(eep->baseEepHeader.rfSilent);
 192                 eep->baseEepHeader.rfSilent = word;
 193
 194                 word = swab16(eep->baseEepHeader.blueToothOptions);
 195                 eep->baseEepHeader.blueToothOptions = word;
 196
 197                 word = swab16(eep->baseEepHeader.deviceCap);
 198                 eep->baseEepHeader.deviceCap = word;
 199
 200                 for (j = 0; j < ARRAY_SIZE(eep->modalHeader); j++) {
 201                         struct modal_eep_header *pModal =
 202                                 &eep->modalHeader[j];
 203                         integer = swab32(pModal->antCtrlCommon);
 204                         pModal->antCtrlCommon = integer;
 205
 206                         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
 207                                 integer = swab32(pModal->antCtrlChain[i]);
 208                                 pModal->antCtrlChain[i] = integer;
 209                         }
 210
 211                         for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) {
 212                                 word = swab16(pModal->spurChans[i].spurChan);
 213                                 pModal->spurChans[i].spurChan = word;
 214                         }
 215                 }
 216         }
 217
 218         if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER ||
 219             ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
 220                 ath_print(common, ATH_DBG_FATAL,
 221                           "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
 222                         sum, ah->eep_ops->get_eeprom_ver(ah));
 223                 return -EINVAL;
 224         }
 225
 226         /* Enable fixup for AR_AN_TOP2 if necessary */
 227         if (AR_SREV_9280_10_OR_LATER(ah) &&
 228             (eep->baseEepHeader.version & 0xff) > 0x0a &&
 229             eep->baseEepHeader.pwdclkind == 0)
 230                 ah->need_an_top2_fixup = 1;
 231
 232         return 0;
 233 }
 234
 235 static u32 ath9k_hw_def_get_eeprom(struct ath_hw *ah,
 236                                    enum eeprom_param param)
 237 {
 238         struct ar5416_eeprom_def *eep = &ah->eeprom.def;
 239         struct modal_eep_header *pModal = eep->modalHeader;
 240         struct base_eep_header *pBase = &eep->baseEepHeader;
 241
 242         switch (param) {
 243         case EEP_NFTHRESH_5:
 244                 return pModal[0].noiseFloorThreshCh[0];
 245         case EEP_NFTHRESH_2:
 246                 return pModal[1].noiseFloorThreshCh[0];
 247         case EEP_MAC_LSW:
 248                 return pBase->macAddr[0] << 8 | pBase->macAddr[1];
 249         case EEP_MAC_MID:
 250                 return pBase->macAddr[2] << 8 | pBase->macAddr[3];
 251         case EEP_MAC_MSW:
 252                 return pBase->macAddr[4] << 8 | pBase->macAddr[5];
 253         case EEP_REG_0:
 254                 return pBase->regDmn[0];
 255         case EEP_REG_1:
 256                 return pBase->regDmn[1];
 257         case EEP_OP_CAP:
 258                 return pBase->deviceCap;
 259         case EEP_OP_MODE:
 260                 return pBase->opCapFlags;
 261         case EEP_RF_SILENT:
 262                 return pBase->rfSilent;
 263         case EEP_OB_5:
 264                 return pModal[0].ob;
 265         case EEP_DB_5:
 266                 return pModal[0].db;
 267         case EEP_OB_2:
 268                 return pModal[1].ob;
 269         case EEP_DB_2:
 270                 return pModal[1].db;
 271         case EEP_MINOR_REV:
 272                 return AR5416_VER_MASK;
 273         case EEP_TX_MASK:
 274                 return pBase->txMask;
 275         case EEP_RX_MASK:
 276                 return pBase->rxMask;
 277         case EEP_RXGAIN_TYPE:
 278                 return pBase->rxGainType;
 279         case EEP_TXGAIN_TYPE:
 280                 return pBase->txGainType;
 281         case EEP_OL_PWRCTRL:
 282                 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
 283                         return pBase->openLoopPwrCntl ? true : false;
 284                 else
 285                         return false;
 286         case EEP_RC_CHAIN_MASK:
 287                 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
 288                         return pBase->rcChainMask;
 289                 else
 290                         return 0;
 291         case EEP_DAC_HPWR_5G:
 292                 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_20)
 293                         return pBase->dacHiPwrMode_5G;
 294                 else
 295                         return 0;
 296         case EEP_FRAC_N_5G:
 297                 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_22)
 298                         return pBase->frac_n_5g;
 299                 else
 300                         return 0;
 301         case EEP_PWR_TABLE_OFFSET:
 302                 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_21)
 303                         return pBase->pwr_table_offset;
 304                 else
 305                         return AR5416_PWR_TABLE_OFFSET_DB;
 306         default:
 307                 return 0;
 308         }
 309 }
 310
 311 static void ath9k_hw_def_set_gain(struct ath_hw *ah,
 312                                   struct modal_eep_header *pModal,
 313                                   struct ar5416_eeprom_def *eep,
 314                                   u8 txRxAttenLocal, int regChainOffset, int i)
 315 {
 316         if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) {
 317                 txRxAttenLocal = pModal->txRxAttenCh[i];
 318
 319                 if (AR_SREV_9280_10_OR_LATER(ah)) {
 320                         REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
 321                               AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
 322                               pModal->bswMargin[i]);
 323                         REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
 324                               AR_PHY_GAIN_2GHZ_XATTEN1_DB,
 325                               pModal->bswAtten[i]);
 326                         REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
 327                               AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
 328                               pModal->xatten2Margin[i]);
 329                         REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
 330                               AR_PHY_GAIN_2GHZ_XATTEN2_DB,
 331                               pModal->xatten2Db[i]);
 332                 } else {
 333                         REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
 334                           (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) &
 335                            ~AR_PHY_GAIN_2GHZ_BSW_MARGIN)
 336                           | SM(pModal-> bswMargin[i],
 337                                AR_PHY_GAIN_2GHZ_BSW_MARGIN));
 338                         REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
 339                           (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) &
 340                            ~AR_PHY_GAIN_2GHZ_BSW_ATTEN)
 341                           | SM(pModal->bswAtten[i],
 342                                AR_PHY_GAIN_2GHZ_BSW_ATTEN));
 343                 }
 344         }
 345
 346         if (AR_SREV_9280_10_OR_LATER(ah)) {
 347                 REG_RMW_FIELD(ah,
 348                       AR_PHY_RXGAIN + regChainOffset,
 349                       AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
 350                 REG_RMW_FIELD(ah,
 351                       AR_PHY_RXGAIN + regChainOffset,
 352                       AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[i]);
 353         } else {
 354                 REG_WRITE(ah,
 355                           AR_PHY_RXGAIN + regChainOffset,
 356                           (REG_READ(ah, AR_PHY_RXGAIN + regChainOffset) &
 357                            ~AR_PHY_RXGAIN_TXRX_ATTEN)
 358                           | SM(txRxAttenLocal, AR_PHY_RXGAIN_TXRX_ATTEN));
 359                 REG_WRITE(ah,
 360                           AR_PHY_GAIN_2GHZ + regChainOffset,
 361                           (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) &
 362                            ~AR_PHY_GAIN_2GHZ_RXTX_MARGIN) |
 363                           SM(pModal->rxTxMarginCh[i], AR_PHY_GAIN_2GHZ_RXTX_MARGIN));
 364         }
 365 }
 366
 367 static void ath9k_hw_def_set_board_values(struct ath_hw *ah,
 368                                           struct ath9k_channel *chan)
 369 {
 370         struct modal_eep_header *pModal;
 371         struct ar5416_eeprom_def *eep = &ah->eeprom.def;
 372         int i, regChainOffset;
 373         u8 txRxAttenLocal;
 374
 375         pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
 376         txRxAttenLocal = IS_CHAN_2GHZ(chan) ? 23 : 44;
 377
 378         REG_WRITE(ah, AR_PHY_SWITCH_COM,
 379                   ah->eep_ops->get_eeprom_antenna_cfg(ah, chan));
 380
 381         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
 382                 if (AR_SREV_9280(ah)) {
 383                         if (i >= 2)
 384                                 break;
 385                 }
 386
 387                 if (AR_SREV_5416_20_OR_LATER(ah) &&
 388                     (ah->rxchainmask == 5 || ah->txchainmask == 5) && (i != 0))
 389                         regChainOffset = (i == 1) ? 0x2000 : 0x1000;
 390                 else
 391                         regChainOffset = i * 0x1000;
 392
 393                 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
 394                           pModal->antCtrlChain[i]);
 395
 396                 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,
 397                           (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) &
 398                            ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
 399                              AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
 400                           SM(pModal->iqCalICh[i],
 401                              AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
 402                           SM(pModal->iqCalQCh[i],
 403                              AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
 404
 405                 if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah))
 406                         ath9k_hw_def_set_gain(ah, pModal, eep, txRxAttenLocal,
 407                                               regChainOffset, i);
 408         }
 409
 410         if (AR_SREV_9280_10_OR_LATER(ah)) {
 411                 if (IS_CHAN_2GHZ(chan)) {
 412                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
 413                                                   AR_AN_RF2G1_CH0_OB,
 414                                                   AR_AN_RF2G1_CH0_OB_S,
 415                                                   pModal->ob);
 416                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
 417                                                   AR_AN_RF2G1_CH0_DB,
 418                                                   AR_AN_RF2G1_CH0_DB_S,
 419                                                   pModal->db);
 420                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1,
 421                                                   AR_AN_RF2G1_CH1_OB,
 422                                                   AR_AN_RF2G1_CH1_OB_S,
 423                                                   pModal->ob_ch1);
 424                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1,
 425                                                   AR_AN_RF2G1_CH1_DB,
 426                                                   AR_AN_RF2G1_CH1_DB_S,
 427                                                   pModal->db_ch1);
 428                 } else {
 429                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0,
 430                                                   AR_AN_RF5G1_CH0_OB5,
 431                                                   AR_AN_RF5G1_CH0_OB5_S,
 432                                                   pModal->ob);
 433                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0,
 434                                                   AR_AN_RF5G1_CH0_DB5,
 435                                                   AR_AN_RF5G1_CH0_DB5_S,
 436                                                   pModal->db);
 437                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1,
 438                                                   AR_AN_RF5G1_CH1_OB5,
 439                                                   AR_AN_RF5G1_CH1_OB5_S,
 440                                                   pModal->ob_ch1);
 441                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1,
 442                                                   AR_AN_RF5G1_CH1_DB5,
 443                                                   AR_AN_RF5G1_CH1_DB5_S,
 444                                                   pModal->db_ch1);
 445                 }
 446                 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
 447                                           AR_AN_TOP2_XPABIAS_LVL,
 448                                           AR_AN_TOP2_XPABIAS_LVL_S,
 449                                           pModal->xpaBiasLvl);
 450                 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
 451                                           AR_AN_TOP2_LOCALBIAS,
 452                                           AR_AN_TOP2_LOCALBIAS_S,
 453                                           pModal->local_bias);
 454                 REG_RMW_FIELD(ah, AR_PHY_XPA_CFG, AR_PHY_FORCE_XPA_CFG,
 455                               pModal->force_xpaon);
 456         }
 457
 458         REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
 459                       pModal->switchSettling);
 460         REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
 461                       pModal->adcDesiredSize);
 462
 463         if (!AR_SREV_9280_10_OR_LATER(ah))
 464                 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
 465                               AR_PHY_DESIRED_SZ_PGA,
 466                               pModal->pgaDesiredSize);
 467
 468         REG_WRITE(ah, AR_PHY_RF_CTL4,
 469                   SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF)
 470                   | SM(pModal->txEndToXpaOff,
 471                        AR_PHY_RF_CTL4_TX_END_XPAB_OFF)
 472                   | SM(pModal->txFrameToXpaOn,
 473                        AR_PHY_RF_CTL4_FRAME_XPAA_ON)
 474                   | SM(pModal->txFrameToXpaOn,
 475                        AR_PHY_RF_CTL4_FRAME_XPAB_ON));
 476
 477         REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
 478                       pModal->txEndToRxOn);
 479
 480         if (AR_SREV_9280_10_OR_LATER(ah)) {
 481                 REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
 482                               pModal->thresh62);
 483                 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0,
 484                               AR_PHY_EXT_CCA0_THRESH62,
 485                               pModal->thresh62);
 486         } else {
 487                 REG_RMW_FIELD(ah, AR_PHY_CCA, AR_PHY_CCA_THRESH62,
 488                               pModal->thresh62);
 489                 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
 490                               AR_PHY_EXT_CCA_THRESH62,
 491                               pModal->thresh62);
 492         }
 493
 494         if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_2) {
 495                 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,
 496                               AR_PHY_TX_END_DATA_START,
 497                               pModal->txFrameToDataStart);
 498                 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON,
 499                               pModal->txFrameToPaOn);
 500         }
 501
 502         if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) {
 503                 if (IS_CHAN_HT40(chan))
 504                         REG_RMW_FIELD(ah, AR_PHY_SETTLING,
 505                                       AR_PHY_SETTLING_SWITCH,
 506                                       pModal->swSettleHt40);
 507         }
 508
 509         if (AR_SREV_9280_20_OR_LATER(ah) &&
 510             AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
 511                 REG_RMW_FIELD(ah, AR_PHY_CCK_TX_CTRL,
 512                               AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK,
 513                               pModal->miscBits);
 514
 515
 516         if (AR_SREV_9280_20(ah) && AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_20) {
 517                 if (IS_CHAN_2GHZ(chan))
 518                         REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE,
 519                                         eep->baseEepHeader.dacLpMode);
 520                 else if (eep->baseEepHeader.dacHiPwrMode_5G)
 521                         REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE, 0);
 522                 else
 523                         REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE,
 524                                       eep->baseEepHeader.dacLpMode);
 525
 526                 udelay(100);
 527
 528                 REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, AR_PHY_FRAME_CTL_TX_CLIP,
 529                               pModal->miscBits >> 2);
 530
 531                 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL9,
 532                               AR_PHY_TX_DESIRED_SCALE_CCK,
 533                               eep->baseEepHeader.desiredScaleCCK);
 534         }
 535 }
 536
 537 static void ath9k_hw_def_set_addac(struct ath_hw *ah,
 538                                    struct ath9k_channel *chan)
 539 {
 540 #define XPA_LVL_FREQ(cnt) (pModal->xpaBiasLvlFreq[cnt])
 541         struct modal_eep_header *pModal;
 542         struct ar5416_eeprom_def *eep = &ah->eeprom.def;
 543         u8 biaslevel;
 544
 545         if (ah->hw_version.macVersion != AR_SREV_VERSION_9160)
 546                 return;
 547
 548         if (ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_MINOR_VER_7)
 549                 return;
 550
 551         pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
 552
 553         if (pModal->xpaBiasLvl != 0xff) {
 554                 biaslevel = pModal->xpaBiasLvl;
 555         } else {
 556                 u16 resetFreqBin, freqBin, freqCount = 0;
 557                 struct chan_centers centers;
 558
 559                 ath9k_hw_get_channel_centers(ah, chan, &centers);
 560
 561                 resetFreqBin = FREQ2FBIN(centers.synth_center,
 562                                          IS_CHAN_2GHZ(chan));
 563                 freqBin = XPA_LVL_FREQ(0) & 0xff;
 564                 biaslevel = (u8) (XPA_LVL_FREQ(0) >> 14);
 565
 566                 freqCount++;
 567
 568                 while (freqCount < 3) {
 569                         if (XPA_LVL_FREQ(freqCount) == 0x0)
 570                                 break;
 571
 572                         freqBin = XPA_LVL_FREQ(freqCount) & 0xff;
 573                         if (resetFreqBin >= freqBin)
 574                                 biaslevel = (u8)(XPA_LVL_FREQ(freqCount) >> 14);
 575                         else
 576                                 break;
 577                         freqCount++;
 578                 }
 579         }
 580
 581         if (IS_CHAN_2GHZ(chan)) {
 582                 INI_RA(&ah->iniAddac, 7, 1) = (INI_RA(&ah->iniAddac,
 583                                         7, 1) & (~0x18)) | biaslevel << 3;
 584         } else {
 585                 INI_RA(&ah->iniAddac, 6, 1) = (INI_RA(&ah->iniAddac,
 586                                         6, 1) & (~0xc0)) | biaslevel << 6;
 587         }
 588 #undef XPA_LVL_FREQ
 589 }
 590
 591 static void ath9k_hw_get_def_gain_boundaries_pdadcs(struct ath_hw *ah,
 592                                 struct ath9k_channel *chan,
 593                                 struct cal_data_per_freq *pRawDataSet,
 594                                 u8 *bChans, u16 availPiers,
 595                                 u16 tPdGainOverlap, int16_t *pMinCalPower,
 596                                 u16 *pPdGainBoundaries, u8 *pPDADCValues,
 597                                 u16 numXpdGains)
 598 {
 599         int i, j, k;
 600         int16_t ss;
 601         u16 idxL = 0, idxR = 0, numPiers;
 602         static u8 vpdTableL[AR5416_NUM_PD_GAINS]
 603                 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
 604         static u8 vpdTableR[AR5416_NUM_PD_GAINS]
 605                 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
 606         static u8 vpdTableI[AR5416_NUM_PD_GAINS]
 607                 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
 608
 609         u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
 610         u8 minPwrT4[AR5416_NUM_PD_GAINS];
 611         u8 maxPwrT4[AR5416_NUM_PD_GAINS];
 612         int16_t vpdStep;
 613         int16_t tmpVal;
 614         u16 sizeCurrVpdTable, maxIndex, tgtIndex;
 615         bool match;
 616         int16_t minDelta = 0;
 617         struct chan_centers centers;
 618
 619         ath9k_hw_get_channel_centers(ah, chan, &centers);
 620
 621         for (numPiers = 0; numPiers < availPiers; numPiers++) {
 622                 if (bChans[numPiers] == AR5416_BCHAN_UNUSED)
 623                         break;
 624         }
 625
 626         match = ath9k_hw_get_lower_upper_index((u8)FREQ2FBIN(centers.synth_center,
 627                                                              IS_CHAN_2GHZ(chan)),
 628                                                bChans, numPiers, &idxL, &idxR);
 629
 630         if (match) {
 631                 for (i = 0; i < numXpdGains; i++) {
 632                         minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
 633                         maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
 634                         ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
 635                                         pRawDataSet[idxL].pwrPdg[i],
 636                                         pRawDataSet[idxL].vpdPdg[i],
 637                                         AR5416_PD_GAIN_ICEPTS,
 638                                         vpdTableI[i]);
 639                 }
 640         } else {
 641                 for (i = 0; i < numXpdGains; i++) {
 642                         pVpdL = pRawDataSet[idxL].vpdPdg[i];
 643                         pPwrL = pRawDataSet[idxL].pwrPdg[i];
 644                         pVpdR = pRawDataSet[idxR].vpdPdg[i];
 645                         pPwrR = pRawDataSet[idxR].pwrPdg[i];
 646
 647                         minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
 648
 649                         maxPwrT4[i] =
 650                                 min(pPwrL[AR5416_PD_GAIN_ICEPTS - 1],
 651                                     pPwrR[AR5416_PD_GAIN_ICEPTS - 1]);
 652
 653
 654                         ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
 655                                                 pPwrL, pVpdL,
 656                                                 AR5416_PD_GAIN_ICEPTS,
 657                                                 vpdTableL[i]);
 658                         ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
 659                                                 pPwrR, pVpdR,
 660                                                 AR5416_PD_GAIN_ICEPTS,
 661                                                 vpdTableR[i]);
 662
 663                         for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
 664                                 vpdTableI[i][j] =
 665                                         (u8)(ath9k_hw_interpolate((u16)
 666                                              FREQ2FBIN(centers.
 667                                                        synth_center,
 668                                                        IS_CHAN_2GHZ
 669                                                        (chan)),
 670                                              bChans[idxL], bChans[idxR],
 671                                              vpdTableL[i][j], vpdTableR[i][j]));
 672                         }
 673                 }
 674         }
 675
 676         *pMinCalPower = (int16_t)(minPwrT4[0] / 2);
 677
 678         k = 0;
 679
 680         for (i = 0; i < numXpdGains; i++) {
 681                 if (i == (numXpdGains - 1))
 682                         pPdGainBoundaries[i] =
 683                                 (u16)(maxPwrT4[i] / 2);
 684                 else
 685                         pPdGainBoundaries[i] =
 686                                 (u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4);
 687
 688                 pPdGainBoundaries[i] =
 689                         min((u16)AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]);
 690
 691                 if ((i == 0) && !AR_SREV_5416_20_OR_LATER(ah)) {
 692                         minDelta = pPdGainBoundaries[0] - 23;
 693                         pPdGainBoundaries[0] = 23;
 694                 } else {
 695                         minDelta = 0;
 696                 }
 697
 698                 if (i == 0) {
 699                         if (AR_SREV_9280_10_OR_LATER(ah))
 700                                 ss = (int16_t)(0 - (minPwrT4[i] / 2));
 701                         else
 702                                 ss = 0;
 703                 } else {
 704                         ss = (int16_t)((pPdGainBoundaries[i - 1] -
 705                                         (minPwrT4[i] / 2)) -
 706                                        tPdGainOverlap + 1 + minDelta);
 707                 }
 708                 vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
 709                 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
 710
 711                 while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
 712                         tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
 713                         pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
 714                         ss++;
 715                 }
 716
 717                 sizeCurrVpdTable = (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
 718                 tgtIndex = (u8)(pPdGainBoundaries[i] + tPdGainOverlap -
 719                                 (minPwrT4[i] / 2));
 720                 maxIndex = (tgtIndex < sizeCurrVpdTable) ?
 721                         tgtIndex : sizeCurrVpdTable;
 722
 723                 while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
 724                         pPDADCValues[k++] = vpdTableI[i][ss++];
 725                 }
 726
 727                 vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
 728                                     vpdTableI[i][sizeCurrVpdTable - 2]);
 729                 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
 730
 731                 if (tgtIndex > maxIndex) {
 732                         while ((ss <= tgtIndex) &&
 733                                (k < (AR5416_NUM_PDADC_VALUES - 1))) {
 734                                 tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] +
 735                                                     (ss - maxIndex + 1) * vpdStep));
 736                                 pPDADCValues[k++] = (u8)((tmpVal > 255) ?
 737                                                          255 : tmpVal);
 738                                 ss++;
 739                         }
 740                 }
 741         }
 742
 743         while (i < AR5416_PD_GAINS_IN_MASK) {
 744                 pPdGainBoundaries[i] = pPdGainBoundaries[i - 1];
 745                 i++;
 746         }
 747
 748         while (k < AR5416_NUM_PDADC_VALUES) {
 749                 pPDADCValues[k] = pPDADCValues[k - 1];
 750                 k++;
 751         }
 752
 753         return;
 754 }
 755
 756 static int16_t ath9k_change_gain_boundary_setting(struct ath_hw *ah,
 757                                 u16 *gb,
 758                                 u16 numXpdGain,
 759                                 u16 pdGainOverlap_t2,
 760                                 int8_t pwr_table_offset,
 761                                 int16_t *diff)
 762
 763 {
 764         u16 k;
 765
 766         /* Prior to writing the boundaries or the pdadc vs. power table
 767          * into the chip registers the default starting point on the pdadc
 768          * vs. power table needs to be checked and the curve boundaries
 769          * adjusted accordingly
 770          */
 771         if (AR_SREV_9280_20_OR_LATER(ah)) {
 772                 u16 gb_limit;
 773
 774                 if (AR5416_PWR_TABLE_OFFSET_DB != pwr_table_offset) {
 775                         /* get the difference in dB */
 776                         *diff = (u16)(pwr_table_offset - AR5416_PWR_TABLE_OFFSET_DB);
 777                         /* get the number of half dB steps */
 778                         *diff *= 2;
 779                         /* change the original gain boundary settings
 780                          * by the number of half dB steps
 781                          */
 782                         for (k = 0; k < numXpdGain; k++)
 783                                 gb[k] = (u16)(gb[k] - *diff);
 784                 }
 785                 /* Because of a hardware limitation, ensure the gain boundary
 786                  * is not larger than (63 - overlap)
 787                  */
 788                 gb_limit = (u16)(AR5416_MAX_RATE_POWER - pdGainOverlap_t2);
 789
 790                 for (k = 0; k < numXpdGain; k++)
 791                         gb[k] = (u16)min(gb_limit, gb[k]);
 792         }
 793
 794         return *diff;
 795 }
 796
 797 static void ath9k_adjust_pdadc_values(struct ath_hw *ah,
 798                                       int8_t pwr_table_offset,
 799                                       int16_t diff,
 800                                       u8 *pdadcValues)
 801 {
 802 #define NUM_PDADC(diff) (AR5416_NUM_PDADC_VALUES - diff)
 803         u16 k;
 804
 805         /* If this is a board that has a pwrTableOffset that differs from
 806          * the default AR5416_PWR_TABLE_OFFSET_DB then the start of the
 807          * pdadc vs pwr table needs to be adjusted prior to writing to the
 808          * chip.
 809          */
 810         if (AR_SREV_9280_20_OR_LATER(ah)) {
 811                 if (AR5416_PWR_TABLE_OFFSET_DB != pwr_table_offset) {
 812                         /* shift the table to start at the new offset */
 813                         for (k = 0; k < (u16)NUM_PDADC(diff); k++ ) {
 814                                 pdadcValues[k] = pdadcValues[k + diff];
 815                         }
 816
 817                         /* fill the back of the table */
 818                         for (k = (u16)NUM_PDADC(diff); k < NUM_PDADC(0); k++) {
 819                                 pdadcValues[k] = pdadcValues[NUM_PDADC(diff)];
 820                         }
 821                 }
 822         }
 823 #undef NUM_PDADC
 824 }
 825
 826 static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
 827                                   struct ath9k_channel *chan,
 828                                   int16_t *pTxPowerIndexOffset)
 829 {
 830 #define SM_PD_GAIN(x) SM(0x38, AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##x)
 831 #define SM_PDGAIN_B(x, y) \
 832                 SM((gainBoundaries[x]), AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##y)
 833         struct ath_common *common = ath9k_hw_common(ah);
 834         struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
 835         struct cal_data_per_freq *pRawDataset;
 836         u8 *pCalBChans = NULL;
 837         u16 pdGainOverlap_t2;
 838         static u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
 839         u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK];
 840         u16 numPiers, i, j;
 841         int16_t tMinCalPower, diff = 0;
 842         u16 numXpdGain, xpdMask;
 843         u16 xpdGainValues[AR5416_NUM_PD_GAINS] = { 0, 0, 0, 0 };
 844         u32 reg32, regOffset, regChainOffset;
 845         int16_t modalIdx;
 846         int8_t pwr_table_offset;
 847
 848         modalIdx = IS_CHAN_2GHZ(chan) ? 1 : 0;
 849         xpdMask = pEepData->modalHeader[modalIdx].xpdGain;
 850
 851         pwr_table_offset = ah->eep_ops->get_eeprom(ah, EEP_PWR_TABLE_OFFSET);
 852
 853         if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
 854             AR5416_EEP_MINOR_VER_2) {
 855                 pdGainOverlap_t2 =
 856                         pEepData->modalHeader[modalIdx].pdGainOverlap;
 857         } else {
 858                 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5),
 859                                             AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
 860         }
 861
 862         if (IS_CHAN_2GHZ(chan)) {
 863                 pCalBChans = pEepData->calFreqPier2G;
 864                 numPiers = AR5416_NUM_2G_CAL_PIERS;
 865         } else {
 866                 pCalBChans = pEepData->calFreqPier5G;
 867                 numPiers = AR5416_NUM_5G_CAL_PIERS;
 868         }
 869
 870         if (OLC_FOR_AR9280_20_LATER && IS_CHAN_2GHZ(chan)) {
 871                 pRawDataset = pEepData->calPierData2G[0];
 872                 ah->initPDADC = ((struct calDataPerFreqOpLoop *)
 873                                  pRawDataset)->vpdPdg[0][0];
 874         }
 875
 876         numXpdGain = 0;
 877
 878         for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
 879                 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
 880                         if (numXpdGain >= AR5416_NUM_PD_GAINS)
 881                                 break;
 882                         xpdGainValues[numXpdGain] =
 883                                 (u16)(AR5416_PD_GAINS_IN_MASK - i);
 884                         numXpdGain++;
 885                 }
 886         }
 887
 888         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
 889                       (numXpdGain - 1) & 0x3);
 890         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
 891                       xpdGainValues[0]);
 892         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
 893                       xpdGainValues[1]);
 894         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3,
 895                       xpdGainValues[2]);
 896
 897         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
 898                 if (AR_SREV_5416_20_OR_LATER(ah) &&
 899                     (ah->rxchainmask == 5 || ah->txchainmask == 5) &&
 900                     (i != 0)) {
 901                         regChainOffset = (i == 1) ? 0x2000 : 0x1000;
 902                 } else
 903                         regChainOffset = i * 0x1000;
 904
 905                 if (pEepData->baseEepHeader.txMask & (1 << i)) {
 906                         if (IS_CHAN_2GHZ(chan))
 907                                 pRawDataset = pEepData->calPierData2G[i];
 908                         else
 909                                 pRawDataset = pEepData->calPierData5G[i];
 910
 911
 912                         if (OLC_FOR_AR9280_20_LATER) {
 913                                 u8 pcdacIdx;
 914                                 u8 txPower;
 915
 916                                 ath9k_get_txgain_index(ah, chan,
 917                                 (struct calDataPerFreqOpLoop *)pRawDataset,
 918                                 pCalBChans, numPiers, &txPower, &pcdacIdx);
 919                                 ath9k_olc_get_pdadcs(ah, pcdacIdx,
 920                                                      txPower/2, pdadcValues);
 921                         } else {
 922                                 ath9k_hw_get_def_gain_boundaries_pdadcs(ah,
 923                                                         chan, pRawDataset,
 924                                                         pCalBChans, numPiers,
 925                                                         pdGainOverlap_t2,
 926                                                         &tMinCalPower,
 927                                                         gainBoundaries,
 928                                                         pdadcValues,
 929                                                         numXpdGain);
 930                         }
 931
 932                         diff = ath9k_change_gain_boundary_setting(ah,
 933                                                            gainBoundaries,
 934                                                            numXpdGain,
 935                                                            pdGainOverlap_t2,
 936                                                            pwr_table_offset,
 937                                                            &diff);
 938
 939                         if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah)) {
 940                                 if (OLC_FOR_AR9280_20_LATER) {
 941                                         REG_WRITE(ah,
 942                                                 AR_PHY_TPCRG5 + regChainOffset,
 943                                                 SM(0x6,
 944                                                 AR_PHY_TPCRG5_PD_GAIN_OVERLAP) |
 945                                                 SM_PD_GAIN(1) | SM_PD_GAIN(2) |
 946                                                 SM_PD_GAIN(3) | SM_PD_GAIN(4));
 947                                 } else {
 948                                         REG_WRITE(ah,
 949                                                 AR_PHY_TPCRG5 + regChainOffset,
 950                                                 SM(pdGainOverlap_t2,
 951                                                 AR_PHY_TPCRG5_PD_GAIN_OVERLAP)|
 952                                                 SM_PDGAIN_B(0, 1) |
 953                                                 SM_PDGAIN_B(1, 2) |
 954                                                 SM_PDGAIN_B(2, 3) |
 955                                                 SM_PDGAIN_B(3, 4));
 956                                 }
 957                         }
 958
 959
 960                         ath9k_adjust_pdadc_values(ah, pwr_table_offset,
 961                                                   diff, pdadcValues);
 962
 963                         regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset;
 964                         for (j = 0; j < 32; j++) {
 965                                 reg32 = ((pdadcValues[4 * j + 0] & 0xFF) << 0) |
 966                                         ((pdadcValues[4 * j + 1] & 0xFF) << 8) |
 967                                         ((pdadcValues[4 * j + 2] & 0xFF) << 16)|
 968                                         ((pdadcValues[4 * j + 3] & 0xFF) << 24);
 969                                 REG_WRITE(ah, regOffset, reg32);
 970
 971                                 ath_print(common, ATH_DBG_EEPROM,
 972                                           "PDADC (%d,%4x): %4.4x %8.8x\n",
 973                                           i, regChainOffset, regOffset,
 974                                           reg32);
 975                                 ath_print(common, ATH_DBG_EEPROM,
 976                                           "PDADC: Chain %d | PDADC %3d "
 977                                           "Value %3d | PDADC %3d Value %3d | "
 978                                           "PDADC %3d Value %3d | PDADC %3d "
 979                                           "Value %3d |\n",
 980                                           i, 4 * j, pdadcValues[4 * j],
 981                                           4 * j + 1, pdadcValues[4 * j + 1],
 982                                           4 * j + 2, pdadcValues[4 * j + 2],
 983                                           4 * j + 3,
 984                                           pdadcValues[4 * j + 3]);
 985
 986                                 regOffset += 4;
 987                         }
 988                 }
 989         }
 990
 991         *pTxPowerIndexOffset = 0;
 992 #undef SM_PD_GAIN
 993 #undef SM_PDGAIN_B
 994 }
 995
 996 static void ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah,
 997                                                   struct ath9k_channel *chan,
 998                                                   int16_t *ratesArray,
 999                                                   u16 cfgCtl,
1000                                                   u16 AntennaReduction,
1001                                                   u16 twiceMaxRegulatoryPower,
1002                                                   u16 powerLimit)
1003 {
1004 #define REDUCE_SCALED_POWER_BY_TWO_CHAIN     6  /* 10*log10(2)*2 */
1005 #define REDUCE_SCALED_POWER_BY_THREE_CHAIN   9 /* 10*log10(3)*2 */
1006
1007         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1008         struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
1009         u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
1010         static const u16 tpScaleReductionTable[5] =
1011                 { 0, 3, 6, 9, AR5416_MAX_RATE_POWER };
1012
1013         int i;
1014         int16_t twiceLargestAntenna;
1015         struct cal_ctl_data *rep;
1016         struct cal_target_power_leg targetPowerOfdm, targetPowerCck = {
1017                 0, { 0, 0, 0, 0}
1018         };
1019         struct cal_target_power_leg targetPowerOfdmExt = {
1020                 0, { 0, 0, 0, 0} }, targetPowerCckExt = {
1021                 0, { 0, 0, 0, 0 }
1022         };
1023         struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = {
1024                 0, {0, 0, 0, 0}
1025         };
1026         u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
1027         u16 ctlModesFor11a[] =
1028                 { CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40 };
1029         u16 ctlModesFor11g[] =
1030                 { CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT,
1031                   CTL_2GHT40
1032                 };
1033         u16 numCtlModes, *pCtlMode, ctlMode, freq;
1034         struct chan_centers centers;
1035         int tx_chainmask;
1036         u16 twiceMinEdgePower;
1037
1038         tx_chainmask = ah->txchainmask;
1039
1040         ath9k_hw_get_channel_centers(ah, chan, &centers);
1041
1042         twiceLargestAntenna = max(
1043                 pEepData->modalHeader
1044                         [IS_CHAN_2GHZ(chan)].antennaGainCh[0],
1045                 pEepData->modalHeader
1046                         [IS_CHAN_2GHZ(chan)].antennaGainCh[1]);
1047
1048         twiceLargestAntenna = max((u8)twiceLargestAntenna,
1049                                   pEepData->modalHeader
1050                                   [IS_CHAN_2GHZ(chan)].antennaGainCh[2]);
1051
1052         twiceLargestAntenna = (int16_t)min(AntennaReduction -
1053                                            twiceLargestAntenna, 0);
1054
1055         maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
1056
1057         if (regulatory->tp_scale != ATH9K_TP_SCALE_MAX) {
1058                 maxRegAllowedPower -=
1059                         (tpScaleReductionTable[(regulatory->tp_scale)] * 2);
1060         }
1061
1062         scaledPower = min(powerLimit, maxRegAllowedPower);
1063
1064         switch (ar5416_get_ntxchains(tx_chainmask)) {
1065         case 1:
1066                 break;
1067         case 2:
1068                 scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN;
1069                 break;
1070         case 3:
1071                 scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN;
1072                 break;
1073         }
1074
1075         scaledPower = max((u16)0, scaledPower);
1076
1077         if (IS_CHAN_2GHZ(chan)) {
1078                 numCtlModes = ARRAY_SIZE(ctlModesFor11g) -
1079                         SUB_NUM_CTL_MODES_AT_2G_40;
1080                 pCtlMode = ctlModesFor11g;
1081
1082                 ath9k_hw_get_legacy_target_powers(ah, chan,
1083                         pEepData->calTargetPowerCck,
1084                         AR5416_NUM_2G_CCK_TARGET_POWERS,
1085                         &targetPowerCck, 4, false);
1086                 ath9k_hw_get_legacy_target_powers(ah, chan,
1087                         pEepData->calTargetPower2G,
1088                         AR5416_NUM_2G_20_TARGET_POWERS,
1089                         &targetPowerOfdm, 4, false);
1090                 ath9k_hw_get_target_powers(ah, chan,
1091                         pEepData->calTargetPower2GHT20,
1092                         AR5416_NUM_2G_20_TARGET_POWERS,
1093                         &targetPowerHt20, 8, false);
1094
1095                 if (IS_CHAN_HT40(chan)) {
1096                         numCtlModes = ARRAY_SIZE(ctlModesFor11g);
1097                         ath9k_hw_get_target_powers(ah, chan,
1098                                 pEepData->calTargetPower2GHT40,
1099                                 AR5416_NUM_2G_40_TARGET_POWERS,
1100                                 &targetPowerHt40, 8, true);
1101                         ath9k_hw_get_legacy_target_powers(ah, chan,
1102                                 pEepData->calTargetPowerCck,
1103                                 AR5416_NUM_2G_CCK_TARGET_POWERS,
1104                                 &targetPowerCckExt, 4, true);
1105                         ath9k_hw_get_legacy_target_powers(ah, chan,
1106                                 pEepData->calTargetPower2G,
1107                                 AR5416_NUM_2G_20_TARGET_POWERS,
1108                                 &targetPowerOfdmExt, 4, true);
1109                 }
1110         } else {
1111                 numCtlModes = ARRAY_SIZE(ctlModesFor11a) -
1112                         SUB_NUM_CTL_MODES_AT_5G_40;
1113                 pCtlMode = ctlModesFor11a;
1114
1115                 ath9k_hw_get_legacy_target_powers(ah, chan,
1116                         pEepData->calTargetPower5G,
1117                         AR5416_NUM_5G_20_TARGET_POWERS,
1118                         &targetPowerOfdm, 4, false);
1119                 ath9k_hw_get_target_powers(ah, chan,
1120                         pEepData->calTargetPower5GHT20,
1121                         AR5416_NUM_5G_20_TARGET_POWERS,
1122                         &targetPowerHt20, 8, false);
1123
1124                 if (IS_CHAN_HT40(chan)) {
1125                         numCtlModes = ARRAY_SIZE(ctlModesFor11a);
1126                         ath9k_hw_get_target_powers(ah, chan,
1127                                 pEepData->calTargetPower5GHT40,
1128                                 AR5416_NUM_5G_40_TARGET_POWERS,
1129                                 &targetPowerHt40, 8, true);
1130                         ath9k_hw_get_legacy_target_powers(ah, chan,
1131                                 pEepData->calTargetPower5G,
1132                                 AR5416_NUM_5G_20_TARGET_POWERS,
1133                                 &targetPowerOfdmExt, 4, true);
1134                 }
1135         }
1136
1137         for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
1138                 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
1139                         (pCtlMode[ctlMode] == CTL_2GHT40);
1140                 if (isHt40CtlMode)
1141                         freq = centers.synth_center;
1142                 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
1143                         freq = centers.ext_center;
1144                 else
1145                         freq = centers.ctl_center;
1146
1147                 if (ah->eep_ops->get_eeprom_ver(ah) == 14 &&
1148                     ah->eep_ops->get_eeprom_rev(ah) <= 2)
1149                         twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
1150
1151                 for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i]; i++) {
1152                         if ((((cfgCtl & ~CTL_MODE_M) |
1153                               (pCtlMode[ctlMode] & CTL_MODE_M)) ==
1154                              pEepData->ctlIndex[i]) ||
1155                             (((cfgCtl & ~CTL_MODE_M) |
1156                               (pCtlMode[ctlMode] & CTL_MODE_M)) ==
1157                              ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))) {
1158                                 rep = &(pEepData->ctlData[i]);
1159
1160                                 twiceMinEdgePower = ath9k_hw_get_max_edge_power(freq,
1161                                 rep->ctlEdges[ar5416_get_ntxchains(tx_chainmask) - 1],
1162                                 IS_CHAN_2GHZ(chan), AR5416_NUM_BAND_EDGES);
1163
1164                                 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
1165                                         twiceMaxEdgePower = min(twiceMaxEdgePower,
1166                                                                 twiceMinEdgePower);
1167                                 } else {
1168                                         twiceMaxEdgePower = twiceMinEdgePower;
1169                                         break;
1170                                 }
1171                         }
1172                 }
1173
1174                 minCtlPower = min(twiceMaxEdgePower, scaledPower);
1175
1176                 switch (pCtlMode[ctlMode]) {
1177                 case CTL_11B:
1178                         for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) {
1179                                 targetPowerCck.tPow2x[i] =
1180                                         min((u16)targetPowerCck.tPow2x[i],
1181                                             minCtlPower);
1182                         }
1183                         break;
1184                 case CTL_11A:
1185                 case CTL_11G:
1186                         for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); i++) {
1187                                 targetPowerOfdm.tPow2x[i] =
1188                                         min((u16)targetPowerOfdm.tPow2x[i],
1189                                             minCtlPower);
1190                         }
1191                         break;
1192                 case CTL_5GHT20:
1193                 case CTL_2GHT20:
1194                         for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) {
1195                                 targetPowerHt20.tPow2x[i] =
1196                                         min((u16)targetPowerHt20.tPow2x[i],
1197                                             minCtlPower);
1198                         }
1199                         break;
1200                 case CTL_11B_EXT:
1201                         targetPowerCckExt.tPow2x[0] = min((u16)
1202                                         targetPowerCckExt.tPow2x[0],
1203                                         minCtlPower);
1204                         break;
1205                 case CTL_11A_EXT:
1206                 case CTL_11G_EXT:
1207                         targetPowerOfdmExt.tPow2x[0] = min((u16)
1208                                         targetPowerOfdmExt.tPow2x[0],
1209                                         minCtlPower);
1210                         break;
1211                 case CTL_5GHT40:
1212                 case CTL_2GHT40:
1213                         for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
1214                                 targetPowerHt40.tPow2x[i] =
1215                                         min((u16)targetPowerHt40.tPow2x[i],
1216                                             minCtlPower);
1217                         }
1218                         break;
1219                 default:
1220                         break;
1221                 }
1222         }
1223
1224         ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] =
1225                 ratesArray[rate18mb] = ratesArray[rate24mb] =
1226                 targetPowerOfdm.tPow2x[0];
1227         ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
1228         ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
1229         ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
1230         ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
1231
1232         for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++)
1233                 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
1234
1235         if (IS_CHAN_2GHZ(chan)) {
1236                 ratesArray[rate1l] = targetPowerCck.tPow2x[0];
1237                 ratesArray[rate2s] = ratesArray[rate2l] =
1238                         targetPowerCck.tPow2x[1];
1239                 ratesArray[rate5_5s] = ratesArray[rate5_5l] =
1240                         targetPowerCck.tPow2x[2];
1241                 ratesArray[rate11s] = ratesArray[rate11l] =
1242                         targetPowerCck.tPow2x[3];
1243         }
1244         if (IS_CHAN_HT40(chan)) {
1245                 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
1246                         ratesArray[rateHt40_0 + i] =
1247                                 targetPowerHt40.tPow2x[i];
1248                 }
1249                 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
1250                 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
1251                 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
1252                 if (IS_CHAN_2GHZ(chan)) {
1253                         ratesArray[rateExtCck] =
1254                                 targetPowerCckExt.tPow2x[0];
1255                 }
1256         }
1257 }
1258
1259 static void ath9k_hw_def_set_txpower(struct ath_hw *ah,
1260                                     struct ath9k_channel *chan,
1261                                     u16 cfgCtl,
1262                                     u8 twiceAntennaReduction,
1263                                     u8 twiceMaxRegulatoryPower,
1264                                     u8 powerLimit)
1265 {
1266 #define RT_AR_DELTA(x) (ratesArray[x] - cck_ofdm_delta)
1267         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1268         struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
1269         struct modal_eep_header *pModal =
1270                 &(pEepData->modalHeader[IS_CHAN_2GHZ(chan)]);
1271         int16_t ratesArray[Ar5416RateSize];
1272         int16_t txPowerIndexOffset = 0;
1273         u8 ht40PowerIncForPdadc = 2;
1274         int i, cck_ofdm_delta = 0;
1275
1276         memset(ratesArray, 0, sizeof(ratesArray));
1277
1278         if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1279             AR5416_EEP_MINOR_VER_2) {
1280                 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
1281         }
1282
1283         ath9k_hw_set_def_power_per_rate_table(ah, chan,
1284                                                &ratesArray[0], cfgCtl,
1285                                                twiceAntennaReduction,
1286                                                twiceMaxRegulatoryPower,
1287                                                powerLimit);
1288
1289         ath9k_hw_set_def_power_cal_table(ah, chan, &txPowerIndexOffset);
1290
1291         for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
1292                 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
1293                 if (ratesArray[i] > AR5416_MAX_RATE_POWER)
1294                         ratesArray[i] = AR5416_MAX_RATE_POWER;
1295         }
1296
1297         if (AR_SREV_9280_10_OR_LATER(ah)) {
1298                 for (i = 0; i < Ar5416RateSize; i++) {
1299                         int8_t pwr_table_offset;
1300
1301                         pwr_table_offset = ah->eep_ops->get_eeprom(ah,
1302                                                         EEP_PWR_TABLE_OFFSET);
1303                         ratesArray[i] -= pwr_table_offset * 2;
1304                 }
1305         }
1306
1307         REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
1308                   ATH9K_POW_SM(ratesArray[rate18mb], 24)
1309                   | ATH9K_POW_SM(ratesArray[rate12mb], 16)
1310                   | ATH9K_POW_SM(ratesArray[rate9mb], 8)
1311                   | ATH9K_POW_SM(ratesArray[rate6mb], 0));
1312         REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
1313                   ATH9K_POW_SM(ratesArray[rate54mb], 24)
1314                   | ATH9K_POW_SM(ratesArray[rate48mb], 16)
1315                   | ATH9K_POW_SM(ratesArray[rate36mb], 8)
1316                   | ATH9K_POW_SM(ratesArray[rate24mb], 0));
1317
1318         if (IS_CHAN_2GHZ(chan)) {
1319                 if (OLC_FOR_AR9280_20_LATER) {
1320                         cck_ofdm_delta = 2;
1321                         REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
1322                                 ATH9K_POW_SM(RT_AR_DELTA(rate2s), 24)
1323                                 | ATH9K_POW_SM(RT_AR_DELTA(rate2l), 16)
1324                                 | ATH9K_POW_SM(ratesArray[rateXr], 8)
1325                                 | ATH9K_POW_SM(RT_AR_DELTA(rate1l), 0));
1326                         REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
1327                                 ATH9K_POW_SM(RT_AR_DELTA(rate11s), 24)
1328                                 | ATH9K_POW_SM(RT_AR_DELTA(rate11l), 16)
1329                                 | ATH9K_POW_SM(RT_AR_DELTA(rate5_5s), 8)
1330                                 | ATH9K_POW_SM(RT_AR_DELTA(rate5_5l), 0));
1331                 } else {
1332                         REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
1333                                 ATH9K_POW_SM(ratesArray[rate2s], 24)
1334                                 | ATH9K_POW_SM(ratesArray[rate2l], 16)
1335                                 | ATH9K_POW_SM(ratesArray[rateXr], 8)
1336                                 | ATH9K_POW_SM(ratesArray[rate1l], 0));
1337                         REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
1338                                 ATH9K_POW_SM(ratesArray[rate11s], 24)
1339                                 | ATH9K_POW_SM(ratesArray[rate11l], 16)
1340                                 | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
1341                                 | ATH9K_POW_SM(ratesArray[rate5_5l], 0));
1342                 }
1343         }
1344
1345         REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
1346                   ATH9K_POW_SM(ratesArray[rateHt20_3], 24)
1347                   | ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
1348                   | ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
1349                   | ATH9K_POW_SM(ratesArray[rateHt20_0], 0));
1350         REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
1351                   ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
1352                   | ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
1353                   | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
1354                   | ATH9K_POW_SM(ratesArray[rateHt20_4], 0));
1355
1356         if (IS_CHAN_HT40(chan)) {
1357                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
1358                           ATH9K_POW_SM(ratesArray[rateHt40_3] +
1359                                        ht40PowerIncForPdadc, 24)
1360                           | ATH9K_POW_SM(ratesArray[rateHt40_2] +
1361                                          ht40PowerIncForPdadc, 16)
1362                           | ATH9K_POW_SM(ratesArray[rateHt40_1] +
1363                                          ht40PowerIncForPdadc, 8)
1364                           | ATH9K_POW_SM(ratesArray[rateHt40_0] +
1365                                          ht40PowerIncForPdadc, 0));
1366                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
1367                           ATH9K_POW_SM(ratesArray[rateHt40_7] +
1368                                        ht40PowerIncForPdadc, 24)
1369                           | ATH9K_POW_SM(ratesArray[rateHt40_6] +
1370                                          ht40PowerIncForPdadc, 16)
1371                           | ATH9K_POW_SM(ratesArray[rateHt40_5] +
1372                                          ht40PowerIncForPdadc, 8)
1373                           | ATH9K_POW_SM(ratesArray[rateHt40_4] +
1374                                          ht40PowerIncForPdadc, 0));
1375                 if (OLC_FOR_AR9280_20_LATER) {
1376                         REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
1377                                 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
1378                                 | ATH9K_POW_SM(RT_AR_DELTA(rateExtCck), 16)
1379                                 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
1380                                 | ATH9K_POW_SM(RT_AR_DELTA(rateDupCck), 0));
1381                 } else {
1382                         REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
1383                                 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
1384                                 | ATH9K_POW_SM(ratesArray[rateExtCck], 16)
1385                                 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
1386                                 | ATH9K_POW_SM(ratesArray[rateDupCck], 0));
1387                 }
1388         }
1389
1390         REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
1391                   ATH9K_POW_SM(pModal->pwrDecreaseFor3Chain, 6)
1392                   | ATH9K_POW_SM(pModal->pwrDecreaseFor2Chain, 0));
1393
1394         i = rate6mb;
1395
1396         if (IS_CHAN_HT40(chan))
1397                 i = rateHt40_0;
1398         else if (IS_CHAN_HT20(chan))
1399                 i = rateHt20_0;
1400
1401         if (AR_SREV_9280_10_OR_LATER(ah))
1402                 regulatory->max_power_level =
1403                         ratesArray[i] + AR5416_PWR_TABLE_OFFSET_DB * 2;
1404         else
1405                 regulatory->max_power_level = ratesArray[i];
1406
1407         switch(ar5416_get_ntxchains(ah->txchainmask)) {
1408         case 1:
1409                 break;
1410         case 2:
1411                 regulatory->max_power_level += INCREASE_MAXPOW_BY_TWO_CHAIN;
1412                 break;
1413         case 3:
1414                 regulatory->max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN;
1415                 break;
1416         default:
1417                 ath_print(ath9k_hw_common(ah), ATH_DBG_EEPROM,
1418                           "Invalid chainmask configuration\n");
1419                 break;
1420         }
1421 }
1422
1423 static u8 ath9k_hw_def_get_num_ant_config(struct ath_hw *ah,
1424                                           enum ieee80211_band freq_band)
1425 {
1426         struct ar5416_eeprom_def *eep = &ah->eeprom.def;
1427         struct modal_eep_header *pModal =
1428                 &(eep->modalHeader[ATH9K_HAL_FREQ_BAND_2GHZ == freq_band]);
1429         struct base_eep_header *pBase = &eep->baseEepHeader;
1430         u8 num_ant_config;
1431
1432         num_ant_config = 1;
1433
1434         if (pBase->version >= 0x0E0D)
1435                 if (pModal->useAnt1)
1436                         num_ant_config += 1;
1437
1438         return num_ant_config;
1439 }
1440
1441 static u16 ath9k_hw_def_get_eeprom_antenna_cfg(struct ath_hw *ah,
1442                                                struct ath9k_channel *chan)
1443 {
1444         struct ar5416_eeprom_def *eep = &ah->eeprom.def;
1445         struct modal_eep_header *pModal =
1446                 &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
1447
1448         return pModal->antCtrlCommon & 0xFFFF;
1449 }
1450
1451 static u16 ath9k_hw_def_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
1452 {
1453 #define EEP_DEF_SPURCHAN \
1454         (ah->eeprom.def.modalHeader[is2GHz].spurChans[i].spurChan)
1455         struct ath_common *common = ath9k_hw_common(ah);
1456
1457         u16 spur_val = AR_NO_SPUR;
1458
1459         ath_print(common, ATH_DBG_ANI,
1460                   "Getting spur idx %d is2Ghz. %d val %x\n",
1461                   i, is2GHz, ah->config.spurchans[i][is2GHz]);
1462
1463         switch (ah->config.spurmode) {
1464         case SPUR_DISABLE:
1465                 break;
1466         case SPUR_ENABLE_IOCTL:
1467                 spur_val = ah->config.spurchans[i][is2GHz];
1468                 ath_print(common, ATH_DBG_ANI,
1469                           "Getting spur val from new loc. %d\n", spur_val);
1470                 break;
1471         case SPUR_ENABLE_EEPROM:
1472                 spur_val = EEP_DEF_SPURCHAN;
1473                 break;
1474         }
1475
1476         return spur_val;
1477
1478 #undef EEP_DEF_SPURCHAN
1479 }
1480
1481 const struct eeprom_ops eep_def_ops = {
1482         .check_eeprom           = ath9k_hw_def_check_eeprom,
1483         .get_eeprom             = ath9k_hw_def_get_eeprom,
1484         .fill_eeprom            = ath9k_hw_def_fill_eeprom,
1485         .get_eeprom_ver         = ath9k_hw_def_get_eeprom_ver,
1486         .get_eeprom_rev         = ath9k_hw_def_get_eeprom_rev,
1487         .get_num_ant_config     = ath9k_hw_def_get_num_ant_config,
1488         .get_eeprom_antenna_cfg = ath9k_hw_def_get_eeprom_antenna_cfg,
1489         .set_board_values       = ath9k_hw_def_set_board_values,
1490         .set_addac              = ath9k_hw_def_set_addac,
1491         .set_txpower            = ath9k_hw_def_set_txpower,
1492         .get_spur_channel       = ath9k_hw_def_get_spur_channel
1493 };