drivers/net/wireless/ath/ath9k/hw.c

   1 /*
   2  * Copyright (c) 2008-2010 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/io.h>
  18 #include <asm/unaligned.h>
  19
  20 #include "hw.h"
  21 #include "hw-ops.h"
  22 #include "rc.h"
  23 #include "ar9003_mac.h"
  24
  25 #define ATH9K_CLOCK_RATE_CCK            22
  26 #define ATH9K_CLOCK_RATE_5GHZ_OFDM      40
  27 #define ATH9K_CLOCK_RATE_2GHZ_OFDM      44
  28
  29 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
  30
  31 MODULE_AUTHOR("Atheros Communications");
  32 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
  33 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
  34 MODULE_LICENSE("Dual BSD/GPL");
  35
  36 static int __init ath9k_init(void)
  37 {
  38         return 0;
  39 }
  40 module_init(ath9k_init);
  41
  42 static void __exit ath9k_exit(void)
  43 {
  44         return;
  45 }
  46 module_exit(ath9k_exit);
  47
  48 /* Private hardware callbacks */
  49
  50 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
  51 {
  52         ath9k_hw_private_ops(ah)->init_cal_settings(ah);
  53 }
  54
  55 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
  56 {
  57         ath9k_hw_private_ops(ah)->init_mode_regs(ah);
  58 }
  59
  60 static bool ath9k_hw_macversion_supported(struct ath_hw *ah)
  61 {
  62         struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
  63
  64         return priv_ops->macversion_supported(ah->hw_version.macVersion);
  65 }
  66
  67 static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
  68                                         struct ath9k_channel *chan)
  69 {
  70         return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
  71 }
  72
  73 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
  74 {
  75         if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
  76                 return;
  77
  78         ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
  79 }
  80
  81 /********************/
  82 /* Helper Functions */
  83 /********************/
  84
  85 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
  86 {
  87         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
  88
  89         if (!ah->curchan) /* should really check for CCK instead */
  90                 return usecs *ATH9K_CLOCK_RATE_CCK;
  91         if (conf->channel->band == IEEE80211_BAND_2GHZ)
  92                 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
  93         return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
  94 }
  95
  96 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
  97 {
  98         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
  99
 100         if (conf_is_ht40(conf))
 101                 return ath9k_hw_mac_clks(ah, usecs) * 2;
 102         else
 103                 return ath9k_hw_mac_clks(ah, usecs);
 104 }
 105
 106 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
 107 {
 108         int i;
 109
 110         BUG_ON(timeout < AH_TIME_QUANTUM);
 111
 112         for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
 113                 if ((REG_READ(ah, reg) & mask) == val)
 114                         return true;
 115
 116                 udelay(AH_TIME_QUANTUM);
 117         }
 118
 119         ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
 120                   "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
 121                   timeout, reg, REG_READ(ah, reg), mask, val);
 122
 123         return false;
 124 }
 125 EXPORT_SYMBOL(ath9k_hw_wait);
 126
 127 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
 128 {
 129         u32 retval;
 130         int i;
 131
 132         for (i = 0, retval = 0; i < n; i++) {
 133                 retval = (retval << 1) | (val & 1);
 134                 val >>= 1;
 135         }
 136         return retval;
 137 }
 138
 139 bool ath9k_get_channel_edges(struct ath_hw *ah,
 140                              u16 flags, u16 *low,
 141                              u16 *high)
 142 {
 143         struct ath9k_hw_capabilities *pCap = &ah->caps;
 144
 145         if (flags & CHANNEL_5GHZ) {
 146                 *low = pCap->low_5ghz_chan;
 147                 *high = pCap->high_5ghz_chan;
 148                 return true;
 149         }
 150         if ((flags & CHANNEL_2GHZ)) {
 151                 *low = pCap->low_2ghz_chan;
 152                 *high = pCap->high_2ghz_chan;
 153                 return true;
 154         }
 155         return false;
 156 }
 157
 158 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
 159                            u8 phy, int kbps,
 160                            u32 frameLen, u16 rateix,
 161                            bool shortPreamble)
 162 {
 163         u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
 164
 165         if (kbps == 0)
 166                 return 0;
 167
 168         switch (phy) {
 169         case WLAN_RC_PHY_CCK:
 170                 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
 171                 if (shortPreamble)
 172                         phyTime >>= 1;
 173                 numBits = frameLen << 3;
 174                 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
 175                 break;
 176         case WLAN_RC_PHY_OFDM:
 177                 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
 178                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
 179                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 180                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 181                         txTime = OFDM_SIFS_TIME_QUARTER
 182                                 + OFDM_PREAMBLE_TIME_QUARTER
 183                                 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
 184                 } else if (ah->curchan &&
 185                            IS_CHAN_HALF_RATE(ah->curchan)) {
 186                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
 187                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 188                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 189                         txTime = OFDM_SIFS_TIME_HALF +
 190                                 OFDM_PREAMBLE_TIME_HALF
 191                                 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
 192                 } else {
 193                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
 194                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 195                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 196                         txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
 197                                 + (numSymbols * OFDM_SYMBOL_TIME);
 198                 }
 199                 break;
 200         default:
 201                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
 202                           "Unknown phy %u (rate ix %u)\n", phy, rateix);
 203                 txTime = 0;
 204                 break;
 205         }
 206
 207         return txTime;
 208 }
 209 EXPORT_SYMBOL(ath9k_hw_computetxtime);
 210
 211 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
 212                                   struct ath9k_channel *chan,
 213                                   struct chan_centers *centers)
 214 {
 215         int8_t extoff;
 216
 217         if (!IS_CHAN_HT40(chan)) {
 218                 centers->ctl_center = centers->ext_center =
 219                         centers->synth_center = chan->channel;
 220                 return;
 221         }
 222
 223         if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
 224             (chan->chanmode == CHANNEL_G_HT40PLUS)) {
 225                 centers->synth_center =
 226                         chan->channel + HT40_CHANNEL_CENTER_SHIFT;
 227                 extoff = 1;
 228         } else {
 229                 centers->synth_center =
 230                         chan->channel - HT40_CHANNEL_CENTER_SHIFT;
 231                 extoff = -1;
 232         }
 233
 234         centers->ctl_center =
 235                 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
 236         /* 25 MHz spacing is supported by hw but not on upper layers */
 237         centers->ext_center =
 238                 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
 239 }
 240
 241 /******************/
 242 /* Chip Revisions */
 243 /******************/
 244
 245 static void ath9k_hw_read_revisions(struct ath_hw *ah)
 246 {
 247         u32 val;
 248
 249         val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
 250
 251         if (val == 0xFF) {
 252                 val = REG_READ(ah, AR_SREV);
 253                 ah->hw_version.macVersion =
 254                         (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
 255                 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
 256                 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
 257         } else {
 258                 if (!AR_SREV_9100(ah))
 259                         ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
 260
 261                 ah->hw_version.macRev = val & AR_SREV_REVISION;
 262
 263                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
 264                         ah->is_pciexpress = true;
 265         }
 266 }
 267
 268 /************************************/
 269 /* HW Attach, Detach, Init Routines */
 270 /************************************/
 271
 272 static void ath9k_hw_disablepcie(struct ath_hw *ah)
 273 {
 274         if (AR_SREV_9100(ah))
 275                 return;
 276
 277         ENABLE_REGWRITE_BUFFER(ah);
 278
 279         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
 280         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
 281         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
 282         REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
 283         REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
 284         REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
 285         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
 286         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
 287         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
 288
 289         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
 290
 291         REGWRITE_BUFFER_FLUSH(ah);
 292         DISABLE_REGWRITE_BUFFER(ah);
 293 }
 294
 295 /* This should work for all families including legacy */
 296 static bool ath9k_hw_chip_test(struct ath_hw *ah)
 297 {
 298         struct ath_common *common = ath9k_hw_common(ah);
 299         u32 regAddr[2] = { AR_STA_ID0 };
 300         u32 regHold[2];
 301         u32 patternData[4] = { 0x55555555,
 302                                0xaaaaaaaa,
 303                                0x66666666,
 304                                0x99999999 };
 305         int i, j, loop_max;
 306
 307         if (!AR_SREV_9300_20_OR_LATER(ah)) {
 308                 loop_max = 2;
 309                 regAddr[1] = AR_PHY_BASE + (8 << 2);
 310         } else
 311                 loop_max = 1;
 312
 313         for (i = 0; i < loop_max; i++) {
 314                 u32 addr = regAddr[i];
 315                 u32 wrData, rdData;
 316
 317                 regHold[i] = REG_READ(ah, addr);
 318                 for (j = 0; j < 0x100; j++) {
 319                         wrData = (j << 16) | j;
 320                         REG_WRITE(ah, addr, wrData);
 321                         rdData = REG_READ(ah, addr);
 322                         if (rdData != wrData) {
 323                                 ath_print(common, ATH_DBG_FATAL,
 324                                           "address test failed "
 325                                           "addr: 0x%08x - wr:0x%08x != "
 326                                           "rd:0x%08x\n",
 327                                           addr, wrData, rdData);
 328                                 return false;
 329                         }
 330                 }
 331                 for (j = 0; j < 4; j++) {
 332                         wrData = patternData[j];
 333                         REG_WRITE(ah, addr, wrData);
 334                         rdData = REG_READ(ah, addr);
 335                         if (wrData != rdData) {
 336                                 ath_print(common, ATH_DBG_FATAL,
 337                                           "address test failed "
 338                                           "addr: 0x%08x - wr:0x%08x != "
 339                                           "rd:0x%08x\n",
 340                                           addr, wrData, rdData);
 341                                 return false;
 342                         }
 343                 }
 344                 REG_WRITE(ah, regAddr[i], regHold[i]);
 345         }
 346         udelay(100);
 347
 348         return true;
 349 }
 350
 351 static void ath9k_hw_init_config(struct ath_hw *ah)
 352 {
 353         int i;
 354
 355         ah->config.dma_beacon_response_time = 2;
 356         ah->config.sw_beacon_response_time = 10;
 357         ah->config.additional_swba_backoff = 0;
 358         ah->config.ack_6mb = 0x0;
 359         ah->config.cwm_ignore_extcca = 0;
 360         ah->config.pcie_powersave_enable = 0;
 361         ah->config.pcie_clock_req = 0;
 362         ah->config.pcie_waen = 0;
 363         ah->config.analog_shiftreg = 1;
 364         ah->config.ofdm_trig_low = 200;
 365         ah->config.ofdm_trig_high = 500;
 366         ah->config.cck_trig_high = 200;
 367         ah->config.cck_trig_low = 100;
 368
 369         /*
 370          * For now ANI is disabled for AR9003, it is still
 371          * being tested.
 372          */
 373         if (!AR_SREV_9300_20_OR_LATER(ah))
 374                 ah->config.enable_ani = 1;
 375
 376         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
 377                 ah->config.spurchans[i][0] = AR_NO_SPUR;
 378                 ah->config.spurchans[i][1] = AR_NO_SPUR;
 379         }
 380
 381         if (ah->hw_version.devid != AR2427_DEVID_PCIE)
 382                 ah->config.ht_enable = 1;
 383         else
 384                 ah->config.ht_enable = 0;
 385
 386         ah->config.rx_intr_mitigation = true;
 387
 388         /*
 389          * We need this for PCI devices only (Cardbus, PCI, miniPCI)
 390          * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
 391          * This means we use it for all AR5416 devices, and the few
 392          * minor PCI AR9280 devices out there.
 393          *
 394          * Serialization is required because these devices do not handle
 395          * well the case of two concurrent reads/writes due to the latency
 396          * involved. During one read/write another read/write can be issued
 397          * on another CPU while the previous read/write may still be working
 398          * on our hardware, if we hit this case the hardware poops in a loop.
 399          * We prevent this by serializing reads and writes.
 400          *
 401          * This issue is not present on PCI-Express devices or pre-AR5416
 402          * devices (legacy, 802.11abg).
 403          */
 404         if (num_possible_cpus() > 1)
 405                 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
 406 }
 407
 408 static void ath9k_hw_init_defaults(struct ath_hw *ah)
 409 {
 410         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
 411
 412         regulatory->country_code = CTRY_DEFAULT;
 413         regulatory->power_limit = MAX_RATE_POWER;
 414         regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
 415
 416         ah->hw_version.magic = AR5416_MAGIC;
 417         ah->hw_version.subvendorid = 0;
 418
 419         ah->ah_flags = 0;
 420         if (!AR_SREV_9100(ah))
 421                 ah->ah_flags = AH_USE_EEPROM;
 422
 423         ah->atim_window = 0;
 424         ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
 425         ah->beacon_interval = 100;
 426         ah->enable_32kHz_clock = DONT_USE_32KHZ;
 427         ah->slottime = (u32) -1;
 428         ah->globaltxtimeout = (u32) -1;
 429         ah->power_mode = ATH9K_PM_UNDEFINED;
 430 }
 431
 432 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
 433 {
 434         struct ath_common *common = ath9k_hw_common(ah);
 435         u32 sum;
 436         int i;
 437         u16 eeval;
 438         u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
 439
 440         sum = 0;
 441         for (i = 0; i < 3; i++) {
 442                 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
 443                 sum += eeval;
 444                 common->macaddr[2 * i] = eeval >> 8;
 445                 common->macaddr[2 * i + 1] = eeval & 0xff;
 446         }
 447         if (sum == 0 || sum == 0xffff * 3)
 448                 return -EADDRNOTAVAIL;
 449
 450         return 0;
 451 }
 452
 453 static int ath9k_hw_post_init(struct ath_hw *ah)
 454 {
 455         int ecode;
 456
 457         if (!AR_SREV_9271(ah)) {
 458                 if (!ath9k_hw_chip_test(ah))
 459                         return -ENODEV;
 460         }
 461
 462         if (!AR_SREV_9300_20_OR_LATER(ah)) {
 463                 ecode = ar9002_hw_rf_claim(ah);
 464                 if (ecode != 0)
 465                         return ecode;
 466         }
 467
 468         ecode = ath9k_hw_eeprom_init(ah);
 469         if (ecode != 0)
 470                 return ecode;
 471
 472         ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
 473                   "Eeprom VER: %d, REV: %d\n",
 474                   ah->eep_ops->get_eeprom_ver(ah),
 475                   ah->eep_ops->get_eeprom_rev(ah));
 476
 477         ecode = ath9k_hw_rf_alloc_ext_banks(ah);
 478         if (ecode) {
 479                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
 480                           "Failed allocating banks for "
 481                           "external radio\n");
 482                 return ecode;
 483         }
 484
 485         if (!AR_SREV_9100(ah)) {
 486                 ath9k_hw_ani_setup(ah);
 487                 ath9k_hw_ani_init(ah);
 488         }
 489
 490         return 0;
 491 }
 492
 493 static void ath9k_hw_attach_ops(struct ath_hw *ah)
 494 {
 495         if (AR_SREV_9300_20_OR_LATER(ah))
 496                 ar9003_hw_attach_ops(ah);
 497         else
 498                 ar9002_hw_attach_ops(ah);
 499 }
 500
 501 /* Called for all hardware families */
 502 static int __ath9k_hw_init(struct ath_hw *ah)
 503 {
 504         struct ath_common *common = ath9k_hw_common(ah);
 505         int r = 0;
 506
 507         if (ah->hw_version.devid == AR5416_AR9100_DEVID)
 508                 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
 509
 510         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
 511                 ath_print(common, ATH_DBG_FATAL,
 512                           "Couldn't reset chip\n");
 513                 return -EIO;
 514         }
 515
 516         ath9k_hw_init_defaults(ah);
 517         ath9k_hw_init_config(ah);
 518
 519         ath9k_hw_attach_ops(ah);
 520
 521         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
 522                 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
 523                 return -EIO;
 524         }
 525
 526         if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
 527                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
 528                     (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
 529                         ah->config.serialize_regmode =
 530                                 SER_REG_MODE_ON;
 531                 } else {
 532                         ah->config.serialize_regmode =
 533                                 SER_REG_MODE_OFF;
 534                 }
 535         }
 536
 537         ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
 538                 ah->config.serialize_regmode);
 539
 540         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
 541                 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
 542         else
 543                 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
 544
 545         if (!ath9k_hw_macversion_supported(ah)) {
 546                 ath_print(common, ATH_DBG_FATAL,
 547                           "Mac Chip Rev 0x%02x.%x is not supported by "
 548                           "this driver\n", ah->hw_version.macVersion,
 549                           ah->hw_version.macRev);
 550                 return -EOPNOTSUPP;
 551         }
 552
 553         if (AR_SREV_9271(ah) || AR_SREV_9100(ah))
 554                 ah->is_pciexpress = false;
 555
 556         ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
 557         ath9k_hw_init_cal_settings(ah);
 558
 559         ah->ani_function = ATH9K_ANI_ALL;
 560         if (AR_SREV_9280_10_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
 561                 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
 562
 563         ath9k_hw_init_mode_regs(ah);
 564
 565         if (ah->is_pciexpress)
 566                 ath9k_hw_configpcipowersave(ah, 0, 0);
 567         else
 568                 ath9k_hw_disablepcie(ah);
 569
 570         if (!AR_SREV_9300_20_OR_LATER(ah))
 571                 ar9002_hw_cck_chan14_spread(ah);
 572
 573         r = ath9k_hw_post_init(ah);
 574         if (r)
 575                 return r;
 576
 577         ath9k_hw_init_mode_gain_regs(ah);
 578         r = ath9k_hw_fill_cap_info(ah);
 579         if (r)
 580                 return r;
 581
 582         r = ath9k_hw_init_macaddr(ah);
 583         if (r) {
 584                 ath_print(common, ATH_DBG_FATAL,
 585                           "Failed to initialize MAC address\n");
 586                 return r;
 587         }
 588
 589         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
 590                 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
 591         else
 592                 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
 593
 594         if (AR_SREV_9300_20_OR_LATER(ah))
 595                 ar9003_hw_set_nf_limits(ah);
 596
 597         ath9k_init_nfcal_hist_buffer(ah);
 598
 599         common->state = ATH_HW_INITIALIZED;
 600
 601         return 0;
 602 }
 603
 604 int ath9k_hw_init(struct ath_hw *ah)
 605 {
 606         int ret;
 607         struct ath_common *common = ath9k_hw_common(ah);
 608
 609         /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
 610         switch (ah->hw_version.devid) {
 611         case AR5416_DEVID_PCI:
 612         case AR5416_DEVID_PCIE:
 613         case AR5416_AR9100_DEVID:
 614         case AR9160_DEVID_PCI:
 615         case AR9280_DEVID_PCI:
 616         case AR9280_DEVID_PCIE:
 617         case AR9285_DEVID_PCIE:
 618         case AR9287_DEVID_PCI:
 619         case AR9287_DEVID_PCIE:
 620         case AR2427_DEVID_PCIE:
 621         case AR9300_DEVID_PCIE:
 622                 break;
 623         default:
 624                 if (common->bus_ops->ath_bus_type == ATH_USB)
 625                         break;
 626                 ath_print(common, ATH_DBG_FATAL,
 627                           "Hardware device ID 0x%04x not supported\n",
 628                           ah->hw_version.devid);
 629                 return -EOPNOTSUPP;
 630         }
 631
 632         ret = __ath9k_hw_init(ah);
 633         if (ret) {
 634                 ath_print(common, ATH_DBG_FATAL,
 635                           "Unable to initialize hardware; "
 636                           "initialization status: %d\n", ret);
 637                 return ret;
 638         }
 639
 640         return 0;
 641 }
 642 EXPORT_SYMBOL(ath9k_hw_init);
 643
 644 static void ath9k_hw_init_qos(struct ath_hw *ah)
 645 {
 646         ENABLE_REGWRITE_BUFFER(ah);
 647
 648         REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
 649         REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
 650
 651         REG_WRITE(ah, AR_QOS_NO_ACK,
 652                   SM(2, AR_QOS_NO_ACK_TWO_BIT) |
 653                   SM(5, AR_QOS_NO_ACK_BIT_OFF) |
 654                   SM(0, AR_QOS_NO_ACK_BYTE_OFF));
 655
 656         REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
 657         REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
 658         REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
 659         REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
 660         REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
 661
 662         REGWRITE_BUFFER_FLUSH(ah);
 663         DISABLE_REGWRITE_BUFFER(ah);
 664 }
 665
 666 static void ath9k_hw_init_pll(struct ath_hw *ah,
 667                               struct ath9k_channel *chan)
 668 {
 669         u32 pll = ath9k_hw_compute_pll_control(ah, chan);
 670
 671         REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
 672
 673         /* Switch the core clock for ar9271 to 117Mhz */
 674         if (AR_SREV_9271(ah)) {
 675                 udelay(500);
 676                 REG_WRITE(ah, 0x50040, 0x304);
 677         }
 678
 679         udelay(RTC_PLL_SETTLE_DELAY);
 680
 681         REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
 682 }
 683
 684 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
 685                                           enum nl80211_iftype opmode)
 686 {
 687         u32 imr_reg = AR_IMR_TXERR |
 688                 AR_IMR_TXURN |
 689                 AR_IMR_RXERR |
 690                 AR_IMR_RXORN |
 691                 AR_IMR_BCNMISC;
 692
 693         if (AR_SREV_9300_20_OR_LATER(ah)) {
 694                 imr_reg |= AR_IMR_RXOK_HP;
 695                 if (ah->config.rx_intr_mitigation)
 696                         imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
 697                 else
 698                         imr_reg |= AR_IMR_RXOK_LP;
 699
 700         } else {
 701                 if (ah->config.rx_intr_mitigation)
 702                         imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
 703                 else
 704                         imr_reg |= AR_IMR_RXOK;
 705         }
 706
 707         if (ah->config.tx_intr_mitigation)
 708                 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
 709         else
 710                 imr_reg |= AR_IMR_TXOK;
 711
 712         if (opmode == NL80211_IFTYPE_AP)
 713                 imr_reg |= AR_IMR_MIB;
 714
 715         ENABLE_REGWRITE_BUFFER(ah);
 716
 717         REG_WRITE(ah, AR_IMR, imr_reg);
 718         ah->imrs2_reg |= AR_IMR_S2_GTT;
 719         REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
 720
 721         if (!AR_SREV_9100(ah)) {
 722                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
 723                 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
 724                 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
 725         }
 726
 727         REGWRITE_BUFFER_FLUSH(ah);
 728         DISABLE_REGWRITE_BUFFER(ah);
 729
 730         if (AR_SREV_9300_20_OR_LATER(ah)) {
 731                 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
 732                 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
 733                 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
 734                 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
 735         }
 736 }
 737
 738 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
 739 {
 740         u32 val = ath9k_hw_mac_to_clks(ah, us);
 741         val = min(val, (u32) 0xFFFF);
 742         REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
 743 }
 744
 745 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
 746 {
 747         u32 val = ath9k_hw_mac_to_clks(ah, us);
 748         val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
 749         REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
 750 }
 751
 752 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
 753 {
 754         u32 val = ath9k_hw_mac_to_clks(ah, us);
 755         val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
 756         REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
 757 }
 758
 759 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
 760 {
 761         if (tu > 0xFFFF) {
 762                 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
 763                           "bad global tx timeout %u\n", tu);
 764                 ah->globaltxtimeout = (u32) -1;
 765                 return false;
 766         } else {
 767                 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
 768                 ah->globaltxtimeout = tu;
 769                 return true;
 770         }
 771 }
 772
 773 void ath9k_hw_init_global_settings(struct ath_hw *ah)
 774 {
 775         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
 776         int acktimeout;
 777         int slottime;
 778         int sifstime;
 779
 780         ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
 781                   ah->misc_mode);
 782
 783         if (ah->misc_mode != 0)
 784                 REG_WRITE(ah, AR_PCU_MISC,
 785                           REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
 786
 787         if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
 788                 sifstime = 16;
 789         else
 790                 sifstime = 10;
 791
 792         /* As defined by IEEE 802.11-2007 17.3.8.6 */
 793         slottime = ah->slottime + 3 * ah->coverage_class;
 794         acktimeout = slottime + sifstime;
 795
 796         /*
 797          * Workaround for early ACK timeouts, add an offset to match the
 798          * initval's 64us ack timeout value.
 799          * This was initially only meant to work around an issue with delayed
 800          * BA frames in some implementations, but it has been found to fix ACK
 801          * timeout issues in other cases as well.
 802          */
 803         if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
 804                 acktimeout += 64 - sifstime - ah->slottime;
 805
 806         ath9k_hw_setslottime(ah, slottime);
 807         ath9k_hw_set_ack_timeout(ah, acktimeout);
 808         ath9k_hw_set_cts_timeout(ah, acktimeout);
 809         if (ah->globaltxtimeout != (u32) -1)
 810                 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
 811 }
 812 EXPORT_SYMBOL(ath9k_hw_init_global_settings);
 813
 814 void ath9k_hw_deinit(struct ath_hw *ah)
 815 {
 816         struct ath_common *common = ath9k_hw_common(ah);
 817
 818         if (common->state < ATH_HW_INITIALIZED)
 819                 goto free_hw;
 820
 821         if (!AR_SREV_9100(ah))
 822                 ath9k_hw_ani_disable(ah);
 823
 824         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
 825
 826 free_hw:
 827         ath9k_hw_rf_free_ext_banks(ah);
 828 }
 829 EXPORT_SYMBOL(ath9k_hw_deinit);
 830
 831 /*******/
 832 /* INI */
 833 /*******/
 834
 835 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
 836 {
 837         u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
 838
 839         if (IS_CHAN_B(chan))
 840                 ctl |= CTL_11B;
 841         else if (IS_CHAN_G(chan))
 842                 ctl |= CTL_11G;
 843         else
 844                 ctl |= CTL_11A;
 845
 846         return ctl;
 847 }
 848
 849 /****************************************/
 850 /* Reset and Channel Switching Routines */
 851 /****************************************/
 852
 853 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
 854 {
 855         struct ath_common *common = ath9k_hw_common(ah);
 856         u32 regval;
 857
 858         ENABLE_REGWRITE_BUFFER(ah);
 859
 860         /*
 861          * set AHB_MODE not to do cacheline prefetches
 862         */
 863         if (!AR_SREV_9300_20_OR_LATER(ah)) {
 864                 regval = REG_READ(ah, AR_AHB_MODE);
 865                 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
 866         }
 867
 868         /*
 869          * let mac dma reads be in 128 byte chunks
 870          */
 871         regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
 872         REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
 873
 874         REGWRITE_BUFFER_FLUSH(ah);
 875         DISABLE_REGWRITE_BUFFER(ah);
 876
 877         /*
 878          * Restore TX Trigger Level to its pre-reset value.
 879          * The initial value depends on whether aggregation is enabled, and is
 880          * adjusted whenever underruns are detected.
 881          */
 882         if (!AR_SREV_9300_20_OR_LATER(ah))
 883                 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
 884
 885         ENABLE_REGWRITE_BUFFER(ah);
 886
 887         /*
 888          * let mac dma writes be in 128 byte chunks
 889          */
 890         regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
 891         REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
 892
 893         /*
 894          * Setup receive FIFO threshold to hold off TX activities
 895          */
 896         REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
 897
 898         if (AR_SREV_9300_20_OR_LATER(ah)) {
 899                 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
 900                 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
 901
 902                 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
 903                         ah->caps.rx_status_len);
 904         }
 905
 906         /*
 907          * reduce the number of usable entries in PCU TXBUF to avoid
 908          * wrap around issues.
 909          */
 910         if (AR_SREV_9285(ah)) {
 911                 /* For AR9285 the number of Fifos are reduced to half.
 912                  * So set the usable tx buf size also to half to
 913                  * avoid data/delimiter underruns
 914                  */
 915                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
 916                           AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
 917         } else if (!AR_SREV_9271(ah)) {
 918                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
 919                           AR_PCU_TXBUF_CTRL_USABLE_SIZE);
 920         }
 921
 922         REGWRITE_BUFFER_FLUSH(ah);
 923         DISABLE_REGWRITE_BUFFER(ah);
 924
 925         if (AR_SREV_9300_20_OR_LATER(ah))
 926                 ath9k_hw_reset_txstatus_ring(ah);
 927 }
 928
 929 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
 930 {
 931         u32 val;
 932
 933         val = REG_READ(ah, AR_STA_ID1);
 934         val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
 935         switch (opmode) {
 936         case NL80211_IFTYPE_AP:
 937                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
 938                           | AR_STA_ID1_KSRCH_MODE);
 939                 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
 940                 break;
 941         case NL80211_IFTYPE_ADHOC:
 942         case NL80211_IFTYPE_MESH_POINT:
 943                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
 944                           | AR_STA_ID1_KSRCH_MODE);
 945                 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
 946                 break;
 947         case NL80211_IFTYPE_STATION:
 948         case NL80211_IFTYPE_MONITOR:
 949                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
 950                 break;
 951         }
 952 }
 953
 954 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
 955                                    u32 *coef_mantissa, u32 *coef_exponent)
 956 {
 957         u32 coef_exp, coef_man;
 958
 959         for (coef_exp = 31; coef_exp > 0; coef_exp--)
 960                 if ((coef_scaled >> coef_exp) & 0x1)
 961                         break;
 962
 963         coef_exp = 14 - (coef_exp - COEF_SCALE_S);
 964
 965         coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
 966
 967         *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
 968         *coef_exponent = coef_exp - 16;
 969 }
 970
 971 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
 972 {
 973         u32 rst_flags;
 974         u32 tmpReg;
 975
 976         if (AR_SREV_9100(ah)) {
 977                 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
 978                 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
 979                 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
 980                 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
 981                 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
 982         }
 983
 984         ENABLE_REGWRITE_BUFFER(ah);
 985
 986         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
 987                   AR_RTC_FORCE_WAKE_ON_INT);
 988
 989         if (AR_SREV_9100(ah)) {
 990                 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
 991                         AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
 992         } else {
 993                 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
 994                 if (tmpReg &
 995                     (AR_INTR_SYNC_LOCAL_TIMEOUT |
 996                      AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
 997                         u32 val;
 998                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
 999
1000                         val = AR_RC_HOSTIF;
1001                         if (!AR_SREV_9300_20_OR_LATER(ah))
1002                                 val |= AR_RC_AHB;
1003                         REG_WRITE(ah, AR_RC, val);
1004
1005                 } else if (!AR_SREV_9300_20_OR_LATER(ah))
1006                         REG_WRITE(ah, AR_RC, AR_RC_AHB);
1007
1008                 rst_flags = AR_RTC_RC_MAC_WARM;
1009                 if (type == ATH9K_RESET_COLD)
1010                         rst_flags |= AR_RTC_RC_MAC_COLD;
1011         }
1012
1013         REG_WRITE(ah, AR_RTC_RC, rst_flags);
1014
1015         REGWRITE_BUFFER_FLUSH(ah);
1016         DISABLE_REGWRITE_BUFFER(ah);
1017
1018         udelay(50);
1019
1020         REG_WRITE(ah, AR_RTC_RC, 0);
1021         if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1022                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1023                           "RTC stuck in MAC reset\n");
1024                 return false;
1025         }
1026
1027         if (!AR_SREV_9100(ah))
1028                 REG_WRITE(ah, AR_RC, 0);
1029
1030         if (AR_SREV_9100(ah))
1031                 udelay(50);
1032
1033         return true;
1034 }
1035
1036 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1037 {
1038         ENABLE_REGWRITE_BUFFER(ah);
1039
1040         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1041                   AR_RTC_FORCE_WAKE_ON_INT);
1042
1043         if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1044                 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1045
1046         REG_WRITE(ah, AR_RTC_RESET, 0);
1047
1048         REGWRITE_BUFFER_FLUSH(ah);
1049         DISABLE_REGWRITE_BUFFER(ah);
1050
1051         if (!AR_SREV_9300_20_OR_LATER(ah))
1052                 udelay(2);
1053
1054         if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1055                 REG_WRITE(ah, AR_RC, 0);
1056
1057         REG_WRITE(ah, AR_RTC_RESET, 1);
1058
1059         if (!ath9k_hw_wait(ah,
1060                            AR_RTC_STATUS,
1061                            AR_RTC_STATUS_M,
1062                            AR_RTC_STATUS_ON,
1063                            AH_WAIT_TIMEOUT)) {
1064                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1065                           "RTC not waking up\n");
1066                 return false;
1067         }
1068
1069         ath9k_hw_read_revisions(ah);
1070
1071         return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1072 }
1073
1074 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1075 {
1076         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1077                   AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1078
1079         switch (type) {
1080         case ATH9K_RESET_POWER_ON:
1081                 return ath9k_hw_set_reset_power_on(ah);
1082         case ATH9K_RESET_WARM:
1083         case ATH9K_RESET_COLD:
1084                 return ath9k_hw_set_reset(ah, type);
1085         default:
1086                 return false;
1087         }
1088 }
1089
1090 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1091                                 struct ath9k_channel *chan)
1092 {
1093         if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1094                 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1095                         return false;
1096         } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1097                 return false;
1098
1099         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1100                 return false;
1101
1102         ah->chip_fullsleep = false;
1103         ath9k_hw_init_pll(ah, chan);
1104         ath9k_hw_set_rfmode(ah, chan);
1105
1106         return true;
1107 }
1108
1109 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1110                                     struct ath9k_channel *chan)
1111 {
1112         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1113         struct ath_common *common = ath9k_hw_common(ah);
1114         struct ieee80211_channel *channel = chan->chan;
1115         u32 qnum;
1116         int r;
1117
1118         for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1119                 if (ath9k_hw_numtxpending(ah, qnum)) {
1120                         ath_print(common, ATH_DBG_QUEUE,
1121                                   "Transmit frames pending on "
1122                                   "queue %d\n", qnum);
1123                         return false;
1124                 }
1125         }
1126
1127         if (!ath9k_hw_rfbus_req(ah)) {
1128                 ath_print(common, ATH_DBG_FATAL,
1129                           "Could not kill baseband RX\n");
1130                 return false;
1131         }
1132
1133         ath9k_hw_set_channel_regs(ah, chan);
1134
1135         r = ath9k_hw_rf_set_freq(ah, chan);
1136         if (r) {
1137                 ath_print(common, ATH_DBG_FATAL,
1138                           "Failed to set channel\n");
1139                 return false;
1140         }
1141
1142         ah->eep_ops->set_txpower(ah, chan,
1143                              ath9k_regd_get_ctl(regulatory, chan),
1144                              channel->max_antenna_gain * 2,
1145                              channel->max_power * 2,
1146                              min((u32) MAX_RATE_POWER,
1147                              (u32) regulatory->power_limit));
1148
1149         ath9k_hw_rfbus_done(ah);
1150
1151         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1152                 ath9k_hw_set_delta_slope(ah, chan);
1153
1154         ath9k_hw_spur_mitigate_freq(ah, chan);
1155
1156         if (!chan->oneTimeCalsDone)
1157                 chan->oneTimeCalsDone = true;
1158
1159         return true;
1160 }
1161
1162 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1163                     bool bChannelChange)
1164 {
1165         struct ath_common *common = ath9k_hw_common(ah);
1166         u32 saveLedState;
1167         struct ath9k_channel *curchan = ah->curchan;
1168         u32 saveDefAntenna;
1169         u32 macStaId1;
1170         u64 tsf = 0;
1171         int i, r;
1172
1173         ah->txchainmask = common->tx_chainmask;
1174         ah->rxchainmask = common->rx_chainmask;
1175
1176         if (!ah->chip_fullsleep) {
1177                 ath9k_hw_abortpcurecv(ah);
1178                 if (!ath9k_hw_stopdmarecv(ah))
1179                         ath_print(common, ATH_DBG_XMIT,
1180                                 "Failed to stop receive dma\n");
1181         }
1182
1183         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1184                 return -EIO;
1185
1186         if (curchan && !ah->chip_fullsleep)
1187                 ath9k_hw_getnf(ah, curchan);
1188
1189         if (bChannelChange &&
1190             (ah->chip_fullsleep != true) &&
1191             (ah->curchan != NULL) &&
1192             (chan->channel != ah->curchan->channel) &&
1193             ((chan->channelFlags & CHANNEL_ALL) ==
1194              (ah->curchan->channelFlags & CHANNEL_ALL)) &&
1195              !(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) ||
1196              IS_CHAN_A_5MHZ_SPACED(ah->curchan))) {
1197
1198                 if (ath9k_hw_channel_change(ah, chan)) {
1199                         ath9k_hw_loadnf(ah, ah->curchan);
1200                         ath9k_hw_start_nfcal(ah);
1201                         return 0;
1202                 }
1203         }
1204
1205         saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1206         if (saveDefAntenna == 0)
1207                 saveDefAntenna = 1;
1208
1209         macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1210
1211         /* For chips on which RTC reset is done, save TSF before it gets cleared */
1212         if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1213                 tsf = ath9k_hw_gettsf64(ah);
1214
1215         saveLedState = REG_READ(ah, AR_CFG_LED) &
1216                 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1217                  AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1218
1219         ath9k_hw_mark_phy_inactive(ah);
1220
1221         /* Only required on the first reset */
1222         if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1223                 REG_WRITE(ah,
1224                           AR9271_RESET_POWER_DOWN_CONTROL,
1225                           AR9271_RADIO_RF_RST);
1226                 udelay(50);
1227         }
1228
1229         if (!ath9k_hw_chip_reset(ah, chan)) {
1230                 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
1231                 return -EINVAL;
1232         }
1233
1234         /* Only required on the first reset */
1235         if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1236                 ah->htc_reset_init = false;
1237                 REG_WRITE(ah,
1238                           AR9271_RESET_POWER_DOWN_CONTROL,
1239                           AR9271_GATE_MAC_CTL);
1240                 udelay(50);
1241         }
1242
1243         /* Restore TSF */
1244         if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1245                 ath9k_hw_settsf64(ah, tsf);
1246
1247         if (AR_SREV_9280_10_OR_LATER(ah))
1248                 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1249
1250         r = ath9k_hw_process_ini(ah, chan);
1251         if (r)
1252                 return r;
1253
1254         /* Setup MFP options for CCMP */
1255         if (AR_SREV_9280_20_OR_LATER(ah)) {
1256                 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1257                  * frames when constructing CCMP AAD. */
1258                 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1259                               0xc7ff);
1260                 ah->sw_mgmt_crypto = false;
1261         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1262                 /* Disable hardware crypto for management frames */
1263                 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1264                             AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1265                 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1266                             AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1267                 ah->sw_mgmt_crypto = true;
1268         } else
1269                 ah->sw_mgmt_crypto = true;
1270
1271         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1272                 ath9k_hw_set_delta_slope(ah, chan);
1273
1274         ath9k_hw_spur_mitigate_freq(ah, chan);
1275         ah->eep_ops->set_board_values(ah, chan);
1276
1277         ath9k_hw_set_operating_mode(ah, ah->opmode);
1278
1279         ENABLE_REGWRITE_BUFFER(ah);
1280
1281         REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1282         REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
1283                   | macStaId1
1284                   | AR_STA_ID1_RTS_USE_DEF
1285                   | (ah->config.
1286                      ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
1287                   | ah->sta_id1_defaults);
1288         ath_hw_setbssidmask(common);
1289         REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1290         ath9k_hw_write_associd(ah);
1291         REG_WRITE(ah, AR_ISR, ~0);
1292         REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1293
1294         REGWRITE_BUFFER_FLUSH(ah);
1295         DISABLE_REGWRITE_BUFFER(ah);
1296
1297         r = ath9k_hw_rf_set_freq(ah, chan);
1298         if (r)
1299                 return r;
1300
1301         ENABLE_REGWRITE_BUFFER(ah);
1302
1303         for (i = 0; i < AR_NUM_DCU; i++)
1304                 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1305
1306         REGWRITE_BUFFER_FLUSH(ah);
1307         DISABLE_REGWRITE_BUFFER(ah);
1308
1309         ah->intr_txqs = 0;
1310         for (i = 0; i < ah->caps.total_queues; i++)
1311                 ath9k_hw_resettxqueue(ah, i);
1312
1313         ath9k_hw_init_interrupt_masks(ah, ah->opmode);
1314         ath9k_hw_init_qos(ah);
1315
1316         if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1317                 ath9k_enable_rfkill(ah);
1318
1319         ath9k_hw_init_global_settings(ah);
1320
1321         if (!AR_SREV_9300_20_OR_LATER(ah)) {
1322                 ar9002_hw_enable_async_fifo(ah);
1323                 ar9002_hw_enable_wep_aggregation(ah);
1324         }
1325
1326         REG_WRITE(ah, AR_STA_ID1,
1327                   REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
1328
1329         ath9k_hw_set_dma(ah);
1330
1331         REG_WRITE(ah, AR_OBS, 8);
1332
1333         if (ah->config.rx_intr_mitigation) {
1334                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1335                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1336         }
1337
1338         if (ah->config.tx_intr_mitigation) {
1339                 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1340                 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1341         }
1342
1343         ath9k_hw_init_bb(ah, chan);
1344
1345         if (!ath9k_hw_init_cal(ah, chan))
1346                 return -EIO;
1347
1348         ENABLE_REGWRITE_BUFFER(ah);
1349
1350         ath9k_hw_restore_chainmask(ah);
1351         REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1352
1353         REGWRITE_BUFFER_FLUSH(ah);
1354         DISABLE_REGWRITE_BUFFER(ah);
1355
1356         /*
1357          * For big endian systems turn on swapping for descriptors
1358          */
1359         if (AR_SREV_9100(ah)) {
1360                 u32 mask;
1361                 mask = REG_READ(ah, AR_CFG);
1362                 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1363                         ath_print(common, ATH_DBG_RESET,
1364                                 "CFG Byte Swap Set 0x%x\n", mask);
1365                 } else {
1366                         mask =
1367                                 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1368                         REG_WRITE(ah, AR_CFG, mask);
1369                         ath_print(common, ATH_DBG_RESET,
1370                                 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
1371                 }
1372         } else {
1373                 /* Configure AR9271 target WLAN */
1374                 if (AR_SREV_9271(ah))
1375                         REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1376 #ifdef __BIG_ENDIAN
1377                 else
1378                         REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1379 #endif
1380         }
1381
1382         if (ah->btcoex_hw.enabled)
1383                 ath9k_hw_btcoex_enable(ah);
1384
1385         if (AR_SREV_9300_20_OR_LATER(ah)) {
1386                 ath9k_hw_loadnf(ah, curchan);
1387                 ath9k_hw_start_nfcal(ah);
1388         }
1389
1390         return 0;
1391 }
1392 EXPORT_SYMBOL(ath9k_hw_reset);
1393
1394 /************************/
1395 /* Key Cache Management */
1396 /************************/
1397
1398 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
1399 {
1400         u32 keyType;
1401
1402         if (entry >= ah->caps.keycache_size) {
1403                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1404                           "keychache entry %u out of range\n", entry);
1405                 return false;
1406         }
1407
1408         keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
1409
1410         REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
1411         REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
1412         REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
1413         REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
1414         REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
1415         REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
1416         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
1417         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
1418
1419         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
1420                 u16 micentry = entry + 64;
1421
1422                 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
1423                 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
1424                 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
1425                 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
1426
1427         }
1428
1429         return true;
1430 }
1431 EXPORT_SYMBOL(ath9k_hw_keyreset);
1432
1433 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
1434 {
1435         u32 macHi, macLo;
1436
1437         if (entry >= ah->caps.keycache_size) {
1438                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1439                           "keychache entry %u out of range\n", entry);
1440                 return false;
1441         }
1442
1443         if (mac != NULL) {
1444                 macHi = (mac[5] << 8) | mac[4];
1445                 macLo = (mac[3] << 24) |
1446                         (mac[2] << 16) |
1447                         (mac[1] << 8) |
1448                         mac[0];
1449                 macLo >>= 1;
1450                 macLo |= (macHi & 1) << 31;
1451                 macHi >>= 1;
1452         } else {
1453                 macLo = macHi = 0;
1454         }
1455         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
1456         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
1457
1458         return true;
1459 }
1460 EXPORT_SYMBOL(ath9k_hw_keysetmac);
1461
1462 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
1463                                  const struct ath9k_keyval *k,
1464                                  const u8 *mac)
1465 {
1466         const struct ath9k_hw_capabilities *pCap = &ah->caps;
1467         struct ath_common *common = ath9k_hw_common(ah);
1468         u32 key0, key1, key2, key3, key4;
1469         u32 keyType;
1470
1471         if (entry >= pCap->keycache_size) {
1472                 ath_print(common, ATH_DBG_FATAL,
1473                           "keycache entry %u out of range\n", entry);
1474                 return false;
1475         }
1476
1477         switch (k->kv_type) {
1478         case ATH9K_CIPHER_AES_OCB:
1479                 keyType = AR_KEYTABLE_TYPE_AES;
1480                 break;
1481         case ATH9K_CIPHER_AES_CCM:
1482                 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
1483                         ath_print(common, ATH_DBG_ANY,
1484                                   "AES-CCM not supported by mac rev 0x%x\n",
1485                                   ah->hw_version.macRev);
1486                         return false;
1487                 }
1488                 keyType = AR_KEYTABLE_TYPE_CCM;
1489                 break;
1490         case ATH9K_CIPHER_TKIP:
1491                 keyType = AR_KEYTABLE_TYPE_TKIP;
1492                 if (ATH9K_IS_MIC_ENABLED(ah)
1493                     && entry + 64 >= pCap->keycache_size) {
1494                         ath_print(common, ATH_DBG_ANY,
1495                                   "entry %u inappropriate for TKIP\n", entry);
1496                         return false;
1497                 }
1498                 break;
1499         case ATH9K_CIPHER_WEP:
1500                 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
1501                         ath_print(common, ATH_DBG_ANY,
1502                                   "WEP key length %u too small\n", k->kv_len);
1503                         return false;
1504                 }
1505                 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
1506                         keyType = AR_KEYTABLE_TYPE_40;
1507                 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
1508                         keyType = AR_KEYTABLE_TYPE_104;
1509                 else
1510                         keyType = AR_KEYTABLE_TYPE_128;
1511                 break;
1512         case ATH9K_CIPHER_CLR:
1513                 keyType = AR_KEYTABLE_TYPE_CLR;
1514                 break;
1515         default:
1516                 ath_print(common, ATH_DBG_FATAL,
1517                           "cipher %u not supported\n", k->kv_type);
1518                 return false;
1519         }
1520
1521         key0 = get_unaligned_le32(k->kv_val + 0);
1522         key1 = get_unaligned_le16(k->kv_val + 4);
1523         key2 = get_unaligned_le32(k->kv_val + 6);
1524         key3 = get_unaligned_le16(k->kv_val + 10);
1525         key4 = get_unaligned_le32(k->kv_val + 12);
1526         if (k->kv_len <= WLAN_KEY_LEN_WEP104)
1527                 key4 &= 0xff;
1528
1529         /*
1530          * Note: Key cache registers access special memory area that requires
1531          * two 32-bit writes to actually update the values in the internal
1532          * memory. Consequently, the exact order and pairs used here must be
1533          * maintained.
1534          */
1535
1536         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
1537                 u16 micentry = entry + 64;
1538
1539                 /*
1540                  * Write inverted key[47:0] first to avoid Michael MIC errors
1541                  * on frames that could be sent or received at the same time.
1542                  * The correct key will be written in the end once everything
1543                  * else is ready.
1544                  */
1545                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
1546                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
1547
1548                 /* Write key[95:48] */
1549                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
1550                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
1551
1552                 /* Write key[127:96] and key type */
1553                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
1554                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
1555
1556                 /* Write MAC address for the entry */
1557                 (void) ath9k_hw_keysetmac(ah, entry, mac);
1558
1559                 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
1560                         /*
1561                          * TKIP uses two key cache entries:
1562                          * Michael MIC TX/RX keys in the same key cache entry
1563                          * (idx = main index + 64):
1564                          * key0 [31:0] = RX key [31:0]
1565                          * key1 [15:0] = TX key [31:16]
1566                          * key1 [31:16] = reserved
1567                          * key2 [31:0] = RX key [63:32]
1568                          * key3 [15:0] = TX key [15:0]
1569                          * key3 [31:16] = reserved
1570                          * key4 [31:0] = TX key [63:32]
1571                          */
1572                         u32 mic0, mic1, mic2, mic3, mic4;
1573
1574                         mic0 = get_unaligned_le32(k->kv_mic + 0);
1575                         mic2 = get_unaligned_le32(k->kv_mic + 4);
1576                         mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
1577                         mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
1578                         mic4 = get_unaligned_le32(k->kv_txmic + 4);
1579
1580                         /* Write RX[31:0] and TX[31:16] */
1581                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
1582                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
1583
1584                         /* Write RX[63:32] and TX[15:0] */
1585                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
1586                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
1587
1588                         /* Write TX[63:32] and keyType(reserved) */
1589                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
1590                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
1591                                   AR_KEYTABLE_TYPE_CLR);
1592
1593                 } else {
1594                         /*
1595                          * TKIP uses four key cache entries (two for group
1596                          * keys):
1597                          * Michael MIC TX/RX keys are in different key cache
1598                          * entries (idx = main index + 64 for TX and
1599                          * main index + 32 + 96 for RX):
1600                          * key0 [31:0] = TX/RX MIC key [31:0]
1601                          * key1 [31:0] = reserved
1602                          * key2 [31:0] = TX/RX MIC key [63:32]
1603                          * key3 [31:0] = reserved
1604                          * key4 [31:0] = reserved
1605                          *
1606                          * Upper layer code will call this function separately
1607                          * for TX and RX keys when these registers offsets are
1608                          * used.
1609                          */
1610                         u32 mic0, mic2;
1611
1612                         mic0 = get_unaligned_le32(k->kv_mic + 0);
1613                         mic2 = get_unaligned_le32(k->kv_mic + 4);
1614
1615                         /* Write MIC key[31:0] */
1616                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
1617                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
1618
1619                         /* Write MIC key[63:32] */
1620                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
1621                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
1622
1623                         /* Write TX[63:32] and keyType(reserved) */
1624                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
1625                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
1626                                   AR_KEYTABLE_TYPE_CLR);
1627                 }
1628
1629                 /* MAC address registers are reserved for the MIC entry */
1630                 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
1631                 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
1632
1633                 /*
1634                  * Write the correct (un-inverted) key[47:0] last to enable
1635                  * TKIP now that all other registers are set with correct
1636                  * values.
1637                  */
1638                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
1639                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
1640         } else {
1641                 /* Write key[47:0] */
1642                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
1643                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
1644
1645                 /* Write key[95:48] */
1646                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
1647                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
1648
1649                 /* Write key[127:96] and key type */
1650                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
1651                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
1652
1653                 /* Write MAC address for the entry */
1654                 (void) ath9k_hw_keysetmac(ah, entry, mac);
1655         }
1656
1657         return true;
1658 }
1659 EXPORT_SYMBOL(ath9k_hw_set_keycache_entry);
1660
1661 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
1662 {
1663         if (entry < ah->caps.keycache_size) {
1664                 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
1665                 if (val & AR_KEYTABLE_VALID)
1666                         return true;
1667         }
1668         return false;
1669 }
1670 EXPORT_SYMBOL(ath9k_hw_keyisvalid);
1671
1672 /******************************/
1673 /* Power Management (Chipset) */
1674 /******************************/
1675
1676 /*
1677  * Notify Power Mgt is disabled in self-generated frames.
1678  * If requested, force chip to sleep.
1679  */
1680 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
1681 {
1682         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1683         if (setChip) {
1684                 /*
1685                  * Clear the RTC force wake bit to allow the
1686                  * mac to go to sleep.
1687                  */
1688                 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1689                             AR_RTC_FORCE_WAKE_EN);
1690                 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1691                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1692
1693                 /* Shutdown chip. Active low */
1694                 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
1695                         REG_CLR_BIT(ah, (AR_RTC_RESET),
1696                                     AR_RTC_RESET_EN);
1697         }
1698 }
1699
1700 /*
1701  * Notify Power Management is enabled in self-generating
1702  * frames. If request, set power mode of chip to
1703  * auto/normal.  Duration in units of 128us (1/8 TU).
1704  */
1705 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
1706 {
1707         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1708         if (setChip) {
1709                 struct ath9k_hw_capabilities *pCap = &ah->caps;
1710
1711                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1712                         /* Set WakeOnInterrupt bit; clear ForceWake bit */
1713                         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1714                                   AR_RTC_FORCE_WAKE_ON_INT);
1715                 } else {
1716                         /*
1717                          * Clear the RTC force wake bit to allow the
1718                          * mac to go to sleep.
1719                          */
1720                         REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1721                                     AR_RTC_FORCE_WAKE_EN);
1722                 }
1723         }
1724 }
1725
1726 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
1727 {
1728         u32 val;
1729         int i;
1730
1731         if (setChip) {
1732                 if ((REG_READ(ah, AR_RTC_STATUS) &
1733                      AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
1734                         if (ath9k_hw_set_reset_reg(ah,
1735                                            ATH9K_RESET_POWER_ON) != true) {
1736                                 return false;
1737                         }
1738                         if (!AR_SREV_9300_20_OR_LATER(ah))
1739                                 ath9k_hw_init_pll(ah, NULL);
1740                 }
1741                 if (AR_SREV_9100(ah))
1742                         REG_SET_BIT(ah, AR_RTC_RESET,
1743                                     AR_RTC_RESET_EN);
1744
1745                 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1746                             AR_RTC_FORCE_WAKE_EN);
1747                 udelay(50);
1748
1749                 for (i = POWER_UP_TIME / 50; i > 0; i--) {
1750                         val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
1751                         if (val == AR_RTC_STATUS_ON)
1752                                 break;
1753                         udelay(50);
1754                         REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1755                                     AR_RTC_FORCE_WAKE_EN);
1756                 }
1757                 if (i == 0) {
1758                         ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1759                                   "Failed to wakeup in %uus\n",
1760                                   POWER_UP_TIME / 20);
1761                         return false;
1762                 }
1763         }
1764
1765         REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1766
1767         return true;
1768 }
1769
1770 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
1771 {
1772         struct ath_common *common = ath9k_hw_common(ah);
1773         int status = true, setChip = true;
1774         static const char *modes[] = {
1775                 "AWAKE",
1776                 "FULL-SLEEP",
1777                 "NETWORK SLEEP",
1778                 "UNDEFINED"
1779         };
1780
1781         if (ah->power_mode == mode)
1782                 return status;
1783
1784         ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
1785                   modes[ah->power_mode], modes[mode]);
1786
1787         switch (mode) {
1788         case ATH9K_PM_AWAKE:
1789                 status = ath9k_hw_set_power_awake(ah, setChip);
1790                 break;
1791         case ATH9K_PM_FULL_SLEEP:
1792                 ath9k_set_power_sleep(ah, setChip);
1793                 ah->chip_fullsleep = true;
1794                 break;
1795         case ATH9K_PM_NETWORK_SLEEP:
1796                 ath9k_set_power_network_sleep(ah, setChip);
1797                 break;
1798         default:
1799                 ath_print(common, ATH_DBG_FATAL,
1800                           "Unknown power mode %u\n", mode);
1801                 return false;
1802         }
1803         ah->power_mode = mode;
1804
1805         return status;
1806 }
1807 EXPORT_SYMBOL(ath9k_hw_setpower);
1808
1809 /*******************/
1810 /* Beacon Handling */
1811 /*******************/
1812
1813 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
1814 {
1815         int flags = 0;
1816
1817         ah->beacon_interval = beacon_period;
1818
1819         ENABLE_REGWRITE_BUFFER(ah);
1820
1821         switch (ah->opmode) {
1822         case NL80211_IFTYPE_STATION:
1823         case NL80211_IFTYPE_MONITOR:
1824                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
1825                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
1826                 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
1827                 flags |= AR_TBTT_TIMER_EN;
1828                 break;
1829         case NL80211_IFTYPE_ADHOC:
1830         case NL80211_IFTYPE_MESH_POINT:
1831                 REG_SET_BIT(ah, AR_TXCFG,
1832                             AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
1833                 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
1834                           TU_TO_USEC(next_beacon +
1835                                      (ah->atim_window ? ah->
1836                                       atim_window : 1)));
1837                 flags |= AR_NDP_TIMER_EN;
1838         case NL80211_IFTYPE_AP:
1839                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
1840                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
1841                           TU_TO_USEC(next_beacon -
1842                                      ah->config.
1843                                      dma_beacon_response_time));
1844                 REG_WRITE(ah, AR_NEXT_SWBA,
1845                           TU_TO_USEC(next_beacon -
1846                                      ah->config.
1847                                      sw_beacon_response_time));
1848                 flags |=
1849                         AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
1850                 break;
1851         default:
1852                 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
1853                           "%s: unsupported opmode: %d\n",
1854                           __func__, ah->opmode);
1855                 return;
1856                 break;
1857         }
1858
1859         REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
1860         REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
1861         REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
1862         REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
1863
1864         REGWRITE_BUFFER_FLUSH(ah);
1865         DISABLE_REGWRITE_BUFFER(ah);
1866
1867         beacon_period &= ~ATH9K_BEACON_ENA;
1868         if (beacon_period & ATH9K_BEACON_RESET_TSF) {
1869                 ath9k_hw_reset_tsf(ah);
1870         }
1871
1872         REG_SET_BIT(ah, AR_TIMER_MODE, flags);
1873 }
1874 EXPORT_SYMBOL(ath9k_hw_beaconinit);
1875
1876 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
1877                                     const struct ath9k_beacon_state *bs)
1878 {
1879         u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
1880         struct ath9k_hw_capabilities *pCap = &ah->caps;
1881         struct ath_common *common = ath9k_hw_common(ah);
1882
1883         ENABLE_REGWRITE_BUFFER(ah);
1884
1885         REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
1886
1887         REG_WRITE(ah, AR_BEACON_PERIOD,
1888                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1889         REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
1890                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1891
1892         REGWRITE_BUFFER_FLUSH(ah);
1893         DISABLE_REGWRITE_BUFFER(ah);
1894
1895         REG_RMW_FIELD(ah, AR_RSSI_THR,
1896                       AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
1897
1898         beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
1899
1900         if (bs->bs_sleepduration > beaconintval)
1901                 beaconintval = bs->bs_sleepduration;
1902
1903         dtimperiod = bs->bs_dtimperiod;
1904         if (bs->bs_sleepduration > dtimperiod)
1905                 dtimperiod = bs->bs_sleepduration;
1906
1907         if (beaconintval == dtimperiod)
1908                 nextTbtt = bs->bs_nextdtim;
1909         else
1910                 nextTbtt = bs->bs_nexttbtt;
1911
1912         ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
1913         ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
1914         ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
1915         ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
1916
1917         ENABLE_REGWRITE_BUFFER(ah);
1918
1919         REG_WRITE(ah, AR_NEXT_DTIM,
1920                   TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
1921         REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
1922
1923         REG_WRITE(ah, AR_SLEEP1,
1924                   SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
1925                   | AR_SLEEP1_ASSUME_DTIM);
1926
1927         if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
1928                 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
1929         else
1930                 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
1931
1932         REG_WRITE(ah, AR_SLEEP2,
1933                   SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
1934
1935         REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
1936         REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
1937
1938         REGWRITE_BUFFER_FLUSH(ah);
1939         DISABLE_REGWRITE_BUFFER(ah);
1940
1941         REG_SET_BIT(ah, AR_TIMER_MODE,
1942                     AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
1943                     AR_DTIM_TIMER_EN);
1944
1945         /* TSF Out of Range Threshold */
1946         REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
1947 }
1948 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
1949
1950 /*******************/
1951 /* HW Capabilities */
1952 /*******************/
1953
1954 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
1955 {
1956         struct ath9k_hw_capabilities *pCap = &ah->caps;
1957         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1958         struct ath_common *common = ath9k_hw_common(ah);
1959         struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
1960
1961         u16 capField = 0, eeval;
1962
1963         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
1964         regulatory->current_rd = eeval;
1965
1966         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
1967         if (AR_SREV_9285_10_OR_LATER(ah))
1968                 eeval |= AR9285_RDEXT_DEFAULT;
1969         regulatory->current_rd_ext = eeval;
1970
1971         capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
1972
1973         if (ah->opmode != NL80211_IFTYPE_AP &&
1974             ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
1975                 if (regulatory->current_rd == 0x64 ||
1976                     regulatory->current_rd == 0x65)
1977                         regulatory->current_rd += 5;
1978                 else if (regulatory->current_rd == 0x41)
1979                         regulatory->current_rd = 0x43;
1980                 ath_print(common, ATH_DBG_REGULATORY,
1981                           "regdomain mapped to 0x%x\n", regulatory->current_rd);
1982         }
1983
1984         eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
1985         if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
1986                 ath_print(common, ATH_DBG_FATAL,
1987                           "no band has been marked as supported in EEPROM.\n");
1988                 return -EINVAL;
1989         }
1990
1991         bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
1992
1993         if (eeval & AR5416_OPFLAGS_11A) {
1994                 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
1995                 if (ah->config.ht_enable) {
1996                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
1997                                 set_bit(ATH9K_MODE_11NA_HT20,
1998                                         pCap->wireless_modes);
1999                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
2000                                 set_bit(ATH9K_MODE_11NA_HT40PLUS,
2001                                         pCap->wireless_modes);
2002                                 set_bit(ATH9K_MODE_11NA_HT40MINUS,
2003                                         pCap->wireless_modes);
2004                         }
2005                 }
2006         }
2007
2008         if (eeval & AR5416_OPFLAGS_11G) {
2009                 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
2010                 if (ah->config.ht_enable) {
2011                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
2012                                 set_bit(ATH9K_MODE_11NG_HT20,
2013                                         pCap->wireless_modes);
2014                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
2015                                 set_bit(ATH9K_MODE_11NG_HT40PLUS,
2016                                         pCap->wireless_modes);
2017                                 set_bit(ATH9K_MODE_11NG_HT40MINUS,
2018                                         pCap->wireless_modes);
2019                         }
2020                 }
2021         }
2022
2023         pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
2024         /*
2025          * For AR9271 we will temporarilly uses the rx chainmax as read from
2026          * the EEPROM.
2027          */
2028         if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
2029             !(eeval & AR5416_OPFLAGS_11A) &&
2030             !(AR_SREV_9271(ah)))
2031                 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
2032                 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
2033         else
2034                 /* Use rx_chainmask from EEPROM. */
2035                 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
2036
2037         if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
2038                 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
2039
2040         pCap->low_2ghz_chan = 2312;
2041         pCap->high_2ghz_chan = 2732;
2042
2043         pCap->low_5ghz_chan = 4920;
2044         pCap->high_5ghz_chan = 6100;
2045
2046         pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
2047         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
2048         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
2049
2050         pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
2051         pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
2052         pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
2053
2054         if (ah->config.ht_enable)
2055                 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2056         else
2057                 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
2058
2059         pCap->hw_caps |= ATH9K_HW_CAP_GTT;
2060         pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
2061         pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
2062         pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
2063
2064         if (capField & AR_EEPROM_EEPCAP_MAXQCU)
2065                 pCap->total_queues =
2066                         MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
2067         else
2068                 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
2069
2070         if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
2071                 pCap->keycache_size =
2072                         1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
2073         else
2074                 pCap->keycache_size = AR_KEYTABLE_SIZE;
2075
2076         pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
2077
2078         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
2079                 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
2080         else
2081                 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
2082
2083         if (AR_SREV_9271(ah))
2084                 pCap->num_gpio_pins = AR9271_NUM_GPIO;
2085         else if (AR_SREV_9285_10_OR_LATER(ah))
2086                 pCap->num_gpio_pins = AR9285_NUM_GPIO;
2087         else if (AR_SREV_9280_10_OR_LATER(ah))
2088                 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2089         else
2090                 pCap->num_gpio_pins = AR_NUM_GPIO;
2091
2092         if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
2093                 pCap->hw_caps |= ATH9K_HW_CAP_CST;
2094                 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
2095         } else {
2096                 pCap->rts_aggr_limit = (8 * 1024);
2097         }
2098
2099         pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
2100
2101 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2102         ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2103         if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2104                 ah->rfkill_gpio =
2105                         MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2106                 ah->rfkill_polarity =
2107                         MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
2108
2109                 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
2110         }
2111 #endif
2112         if (AR_SREV_9271(ah))
2113                 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2114         else
2115                 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
2116
2117         if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
2118                 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2119         else
2120                 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
2121
2122         if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
2123                 pCap->reg_cap =
2124                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
2125                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
2126                         AR_EEPROM_EEREGCAP_EN_KK_U2 |
2127                         AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
2128         } else {
2129                 pCap->reg_cap =
2130                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
2131                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
2132         }
2133
2134         /* Advertise midband for AR5416 with FCC midband set in eeprom */
2135         if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
2136             AR_SREV_5416(ah))
2137                 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
2138
2139         pCap->num_antcfg_5ghz =
2140                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
2141         pCap->num_antcfg_2ghz =
2142                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
2143
2144         if (AR_SREV_9280_10_OR_LATER(ah) &&
2145             ath9k_hw_btcoex_supported(ah)) {
2146                 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
2147                 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
2148
2149                 if (AR_SREV_9285(ah)) {
2150                         btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
2151                         btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
2152                 } else {
2153                         btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
2154                 }
2155         } else {
2156                 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
2157         }
2158
2159         if (AR_SREV_9300_20_OR_LATER(ah)) {
2160                 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_LDPC;
2161                 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2162                 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2163                 pCap->rx_status_len = sizeof(struct ar9003_rxs);
2164                 pCap->tx_desc_len = sizeof(struct ar9003_txc);
2165                 pCap->txs_len = sizeof(struct ar9003_txs);
2166         } else {
2167                 pCap->tx_desc_len = sizeof(struct ath_desc);
2168         }
2169
2170         if (AR_SREV_9300_20_OR_LATER(ah))
2171                 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2172
2173         return 0;
2174 }
2175
2176 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
2177                             u32 capability, u32 *result)
2178 {
2179         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2180         switch (type) {
2181         case ATH9K_CAP_CIPHER:
2182                 switch (capability) {
2183                 case ATH9K_CIPHER_AES_CCM:
2184                 case ATH9K_CIPHER_AES_OCB:
2185                 case ATH9K_CIPHER_TKIP:
2186                 case ATH9K_CIPHER_WEP:
2187                 case ATH9K_CIPHER_MIC:
2188                 case ATH9K_CIPHER_CLR:
2189                         return true;
2190                 default:
2191                         return false;
2192                 }
2193         case ATH9K_CAP_TKIP_MIC:
2194                 switch (capability) {
2195                 case 0:
2196                         return true;
2197                 case 1:
2198                         return (ah->sta_id1_defaults &
2199                                 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
2200                         false;
2201                 }
2202         case ATH9K_CAP_TKIP_SPLIT:
2203                 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
2204                         false : true;
2205         case ATH9K_CAP_MCAST_KEYSRCH:
2206                 switch (capability) {
2207                 case 0:
2208                         return true;
2209                 case 1:
2210                         if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
2211                                 return false;
2212                         } else {
2213                                 return (ah->sta_id1_defaults &
2214                                         AR_STA_ID1_MCAST_KSRCH) ? true :
2215                                         false;
2216                         }
2217                 }
2218                 return false;
2219         case ATH9K_CAP_TXPOW:
2220                 switch (capability) {
2221                 case 0:
2222                         return 0;
2223                 case 1:
2224                         *result = regulatory->power_limit;
2225                         return 0;
2226                 case 2:
2227                         *result = regulatory->max_power_level;
2228                         return 0;
2229                 case 3:
2230                         *result = regulatory->tp_scale;
2231                         return 0;
2232                 }
2233                 return false;
2234         case ATH9K_CAP_DS:
2235                 return (AR_SREV_9280_20_OR_LATER(ah) &&
2236                         (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
2237                         ? false : true;
2238         default:
2239                 return false;
2240         }
2241 }
2242 EXPORT_SYMBOL(ath9k_hw_getcapability);
2243
2244 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
2245                             u32 capability, u32 setting, int *status)
2246 {
2247         switch (type) {
2248         case ATH9K_CAP_TKIP_MIC:
2249                 if (setting)
2250                         ah->sta_id1_defaults |=
2251                                 AR_STA_ID1_CRPT_MIC_ENABLE;
2252                 else
2253                         ah->sta_id1_defaults &=
2254                                 ~AR_STA_ID1_CRPT_MIC_ENABLE;
2255                 return true;
2256         case ATH9K_CAP_MCAST_KEYSRCH:
2257                 if (setting)
2258                         ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
2259                 else
2260                         ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
2261                 return true;
2262         default:
2263                 return false;
2264         }
2265 }
2266 EXPORT_SYMBOL(ath9k_hw_setcapability);
2267
2268 /****************************/
2269 /* GPIO / RFKILL / Antennae */
2270 /****************************/
2271
2272 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
2273                                          u32 gpio, u32 type)
2274 {
2275         int addr;
2276         u32 gpio_shift, tmp;
2277
2278         if (gpio > 11)
2279                 addr = AR_GPIO_OUTPUT_MUX3;
2280         else if (gpio > 5)
2281                 addr = AR_GPIO_OUTPUT_MUX2;
2282         else
2283                 addr = AR_GPIO_OUTPUT_MUX1;
2284
2285         gpio_shift = (gpio % 6) * 5;
2286
2287         if (AR_SREV_9280_20_OR_LATER(ah)
2288             || (addr != AR_GPIO_OUTPUT_MUX1)) {
2289                 REG_RMW(ah, addr, (type << gpio_shift),
2290                         (0x1f << gpio_shift));
2291         } else {
2292                 tmp = REG_READ(ah, addr);
2293                 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2294                 tmp &= ~(0x1f << gpio_shift);
2295                 tmp |= (type << gpio_shift);
2296                 REG_WRITE(ah, addr, tmp);
2297         }
2298 }
2299
2300 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
2301 {
2302         u32 gpio_shift;
2303
2304         BUG_ON(gpio >= ah->caps.num_gpio_pins);
2305
2306         gpio_shift = gpio << 1;
2307
2308         REG_RMW(ah,
2309                 AR_GPIO_OE_OUT,
2310                 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2311                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2312 }
2313 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
2314
2315 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
2316 {
2317 #define MS_REG_READ(x, y) \
2318         (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2319
2320         if (gpio >= ah->caps.num_gpio_pins)
2321                 return 0xffffffff;
2322
2323         if (AR_SREV_9300_20_OR_LATER(ah))
2324                 return MS_REG_READ(AR9300, gpio) != 0;
2325         else if (AR_SREV_9271(ah))
2326                 return MS_REG_READ(AR9271, gpio) != 0;
2327         else if (AR_SREV_9287_10_OR_LATER(ah))
2328                 return MS_REG_READ(AR9287, gpio) != 0;
2329         else if (AR_SREV_9285_10_OR_LATER(ah))
2330                 return MS_REG_READ(AR9285, gpio) != 0;
2331         else if (AR_SREV_9280_10_OR_LATER(ah))
2332                 return MS_REG_READ(AR928X, gpio) != 0;
2333         else
2334                 return MS_REG_READ(AR, gpio) != 0;
2335 }
2336 EXPORT_SYMBOL(ath9k_hw_gpio_get);
2337
2338 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
2339                          u32 ah_signal_type)
2340 {
2341         u32 gpio_shift;
2342
2343         ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
2344
2345         gpio_shift = 2 * gpio;
2346
2347         REG_RMW(ah,
2348                 AR_GPIO_OE_OUT,
2349                 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2350                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2351 }
2352 EXPORT_SYMBOL(ath9k_hw_cfg_output);
2353
2354 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
2355 {
2356         if (AR_SREV_9271(ah))
2357                 val = ~val;
2358
2359         REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2360                 AR_GPIO_BIT(gpio));
2361 }
2362 EXPORT_SYMBOL(ath9k_hw_set_gpio);
2363
2364 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
2365 {
2366         return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
2367 }
2368 EXPORT_SYMBOL(ath9k_hw_getdefantenna);
2369
2370 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
2371 {
2372         REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
2373 }
2374 EXPORT_SYMBOL(ath9k_hw_setantenna);
2375
2376 /*********************/
2377 /* General Operation */
2378 /*********************/
2379
2380 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
2381 {
2382         u32 bits = REG_READ(ah, AR_RX_FILTER);
2383         u32 phybits = REG_READ(ah, AR_PHY_ERR);
2384
2385         if (phybits & AR_PHY_ERR_RADAR)
2386                 bits |= ATH9K_RX_FILTER_PHYRADAR;
2387         if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2388                 bits |= ATH9K_RX_FILTER_PHYERR;
2389
2390         return bits;
2391 }
2392 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
2393
2394 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
2395 {
2396         u32 phybits;
2397
2398         ENABLE_REGWRITE_BUFFER(ah);
2399
2400         REG_WRITE(ah, AR_RX_FILTER, bits);
2401
2402         phybits = 0;
2403         if (bits & ATH9K_RX_FILTER_PHYRADAR)
2404                 phybits |= AR_PHY_ERR_RADAR;
2405         if (bits & ATH9K_RX_FILTER_PHYERR)
2406                 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2407         REG_WRITE(ah, AR_PHY_ERR, phybits);
2408
2409         if (phybits)
2410                 REG_WRITE(ah, AR_RXCFG,
2411                           REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
2412         else
2413                 REG_WRITE(ah, AR_RXCFG,
2414                           REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
2415
2416         REGWRITE_BUFFER_FLUSH(ah);
2417         DISABLE_REGWRITE_BUFFER(ah);
2418 }
2419 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
2420
2421 bool ath9k_hw_phy_disable(struct ath_hw *ah)
2422 {
2423         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2424                 return false;
2425
2426         ath9k_hw_init_pll(ah, NULL);
2427         return true;
2428 }
2429 EXPORT_SYMBOL(ath9k_hw_phy_disable);
2430
2431 bool ath9k_hw_disable(struct ath_hw *ah)
2432 {
2433         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2434                 return false;
2435
2436         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2437                 return false;
2438
2439         ath9k_hw_init_pll(ah, NULL);
2440         return true;
2441 }
2442 EXPORT_SYMBOL(ath9k_hw_disable);
2443
2444 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
2445 {
2446         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2447         struct ath9k_channel *chan = ah->curchan;
2448         struct ieee80211_channel *channel = chan->chan;
2449
2450         regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
2451
2452         ah->eep_ops->set_txpower(ah, chan,
2453                                  ath9k_regd_get_ctl(regulatory, chan),
2454                                  channel->max_antenna_gain * 2,
2455                                  channel->max_power * 2,
2456                                  min((u32) MAX_RATE_POWER,
2457                                  (u32) regulatory->power_limit));
2458 }
2459 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
2460
2461 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
2462 {
2463         memcpy(ath9k_hw_common(ah)->macaddr, mac, ETH_ALEN);
2464 }
2465 EXPORT_SYMBOL(ath9k_hw_setmac);
2466
2467 void ath9k_hw_setopmode(struct ath_hw *ah)
2468 {
2469         ath9k_hw_set_operating_mode(ah, ah->opmode);
2470 }
2471 EXPORT_SYMBOL(ath9k_hw_setopmode);
2472
2473 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
2474 {
2475         REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2476         REG_WRITE(ah, AR_MCAST_FIL1, filter1);
2477 }
2478 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
2479
2480 void ath9k_hw_write_associd(struct ath_hw *ah)
2481 {
2482         struct ath_common *common = ath9k_hw_common(ah);
2483
2484         REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2485         REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2486                   ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2487 }
2488 EXPORT_SYMBOL(ath9k_hw_write_associd);
2489
2490 #define ATH9K_MAX_TSF_READ 10
2491
2492 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
2493 {
2494         u32 tsf_lower, tsf_upper1, tsf_upper2;
2495         int i;
2496
2497         tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2498         for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2499                 tsf_lower = REG_READ(ah, AR_TSF_L32);
2500                 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2501                 if (tsf_upper2 == tsf_upper1)
2502                         break;
2503                 tsf_upper1 = tsf_upper2;
2504         }
2505
2506         WARN_ON( i == ATH9K_MAX_TSF_READ );
2507
2508         return (((u64)tsf_upper1 << 32) | tsf_lower);
2509 }
2510 EXPORT_SYMBOL(ath9k_hw_gettsf64);
2511
2512 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
2513 {
2514         REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
2515         REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
2516 }
2517 EXPORT_SYMBOL(ath9k_hw_settsf64);
2518
2519 void ath9k_hw_reset_tsf(struct ath_hw *ah)
2520 {
2521         if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2522                            AH_TSF_WRITE_TIMEOUT))
2523                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
2524                           "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
2525
2526         REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2527 }
2528 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
2529
2530 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
2531 {
2532         if (setting)
2533                 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
2534         else
2535                 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
2536 }
2537 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
2538
2539 /*
2540  *  Extend 15-bit time stamp from rx descriptor to
2541  *  a full 64-bit TSF using the current h/w TSF.
2542 */
2543 u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp)
2544 {
2545         u64 tsf;
2546
2547         tsf = ath9k_hw_gettsf64(ah);
2548         if ((tsf & 0x7fff) < rstamp)
2549                 tsf -= 0x8000;
2550         return (tsf & ~0x7fff) | rstamp;
2551 }
2552 EXPORT_SYMBOL(ath9k_hw_extend_tsf);
2553
2554 void ath9k_hw_set11nmac2040(struct ath_hw *ah)
2555 {
2556         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
2557         u32 macmode;
2558
2559         if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
2560                 macmode = AR_2040_JOINED_RX_CLEAR;
2561         else
2562                 macmode = 0;
2563
2564         REG_WRITE(ah, AR_2040_MODE, macmode);
2565 }
2566
2567 /* HW Generic timers configuration */
2568
2569 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2570 {
2571         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2572         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2573         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2574         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2575         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2576         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2577         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2578         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2579         {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2580         {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2581                                 AR_NDP2_TIMER_MODE, 0x0002},
2582         {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2583                                 AR_NDP2_TIMER_MODE, 0x0004},
2584         {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2585                                 AR_NDP2_TIMER_MODE, 0x0008},
2586         {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2587                                 AR_NDP2_TIMER_MODE, 0x0010},
2588         {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2589                                 AR_NDP2_TIMER_MODE, 0x0020},
2590         {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2591                                 AR_NDP2_TIMER_MODE, 0x0040},
2592         {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2593                                 AR_NDP2_TIMER_MODE, 0x0080}
2594 };
2595
2596 /* HW generic timer primitives */
2597
2598 /* compute and clear index of rightmost 1 */
2599 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2600 {
2601         u32 b;
2602
2603         b = *mask;
2604         b &= (0-b);
2605         *mask &= ~b;
2606         b *= debruijn32;
2607         b >>= 27;
2608
2609         return timer_table->gen_timer_index[b];
2610 }
2611
2612 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
2613 {
2614         return REG_READ(ah, AR_TSF_L32);
2615 }
2616 EXPORT_SYMBOL(ath9k_hw_gettsf32);
2617
2618 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2619                                           void (*trigger)(void *),
2620                                           void (*overflow)(void *),
2621                                           void *arg,
2622                                           u8 timer_index)
2623 {
2624         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2625         struct ath_gen_timer *timer;
2626
2627         timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2628
2629         if (timer == NULL) {
2630                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2631                           "Failed to allocate memory"
2632                           "for hw timer[%d]\n", timer_index);
2633                 return NULL;
2634         }
2635
2636         /* allocate a hardware generic timer slot */
2637         timer_table->timers[timer_index] = timer;
2638         timer->index = timer_index;
2639         timer->trigger = trigger;
2640         timer->overflow = overflow;
2641         timer->arg = arg;
2642
2643         return timer;
2644 }
2645 EXPORT_SYMBOL(ath_gen_timer_alloc);
2646
2647 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2648                               struct ath_gen_timer *timer,
2649                               u32 timer_next,
2650                               u32 timer_period)
2651 {
2652         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2653         u32 tsf;
2654
2655         BUG_ON(!timer_period);
2656
2657         set_bit(timer->index, &timer_table->timer_mask.timer_bits);
2658
2659         tsf = ath9k_hw_gettsf32(ah);
2660
2661         ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
2662                   "curent tsf %x period %x"
2663                   "timer_next %x\n", tsf, timer_period, timer_next);
2664
2665         /*
2666          * Pull timer_next forward if the current TSF already passed it
2667          * because of software latency
2668          */
2669         if (timer_next < tsf)
2670                 timer_next = tsf + timer_period;
2671
2672         /*
2673          * Program generic timer registers
2674          */
2675         REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
2676                  timer_next);
2677         REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
2678                   timer_period);
2679         REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2680                     gen_tmr_configuration[timer->index].mode_mask);
2681
2682         /* Enable both trigger and thresh interrupt masks */
2683         REG_SET_BIT(ah, AR_IMR_S5,
2684                 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2685                 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2686 }
2687 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
2688
2689 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
2690 {
2691         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2692
2693         if ((timer->index < AR_FIRST_NDP_TIMER) ||
2694                 (timer->index >= ATH_MAX_GEN_TIMER)) {
2695                 return;
2696         }
2697
2698         /* Clear generic timer enable bits. */
2699         REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2700                         gen_tmr_configuration[timer->index].mode_mask);
2701
2702         /* Disable both trigger and thresh interrupt masks */
2703         REG_CLR_BIT(ah, AR_IMR_S5,
2704                 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2705                 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2706
2707         clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
2708 }
2709 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
2710
2711 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
2712 {
2713         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2714
2715         /* free the hardware generic timer slot */
2716         timer_table->timers[timer->index] = NULL;
2717         kfree(timer);
2718 }
2719 EXPORT_SYMBOL(ath_gen_timer_free);
2720
2721 /*
2722  * Generic Timer Interrupts handling
2723  */
2724 void ath_gen_timer_isr(struct ath_hw *ah)
2725 {
2726         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2727         struct ath_gen_timer *timer;
2728         struct ath_common *common = ath9k_hw_common(ah);
2729         u32 trigger_mask, thresh_mask, index;
2730
2731         /* get hardware generic timer interrupt status */
2732         trigger_mask = ah->intr_gen_timer_trigger;
2733         thresh_mask = ah->intr_gen_timer_thresh;
2734         trigger_mask &= timer_table->timer_mask.val;
2735         thresh_mask &= timer_table->timer_mask.val;
2736
2737         trigger_mask &= ~thresh_mask;
2738
2739         while (thresh_mask) {
2740                 index = rightmost_index(timer_table, &thresh_mask);
2741                 timer = timer_table->timers[index];
2742                 BUG_ON(!timer);
2743                 ath_print(common, ATH_DBG_HWTIMER,
2744                           "TSF overflow for Gen timer %d\n", index);
2745                 timer->overflow(timer->arg);
2746         }
2747
2748         while (trigger_mask) {
2749                 index = rightmost_index(timer_table, &trigger_mask);
2750                 timer = timer_table->timers[index];
2751                 BUG_ON(!timer);
2752                 ath_print(common, ATH_DBG_HWTIMER,
2753                           "Gen timer[%d] trigger\n", index);
2754                 timer->trigger(timer->arg);
2755         }
2756 }
2757 EXPORT_SYMBOL(ath_gen_timer_isr);
2758
2759 /********/
2760 /* HTC  */
2761 /********/
2762
2763 void ath9k_hw_htc_resetinit(struct ath_hw *ah)
2764 {
2765         ah->htc_reset_init = true;
2766 }
2767 EXPORT_SYMBOL(ath9k_hw_htc_resetinit);
2768
2769 static struct {
2770         u32 version;
2771         const char * name;
2772 } ath_mac_bb_names[] = {
2773         /* Devices with external radios */
2774         { AR_SREV_VERSION_5416_PCI,     "5416" },
2775         { AR_SREV_VERSION_5416_PCIE,    "5418" },
2776         { AR_SREV_VERSION_9100,         "9100" },
2777         { AR_SREV_VERSION_9160,         "9160" },
2778         /* Single-chip solutions */
2779         { AR_SREV_VERSION_9280,         "9280" },
2780         { AR_SREV_VERSION_9285,         "9285" },
2781         { AR_SREV_VERSION_9287,         "9287" },
2782         { AR_SREV_VERSION_9271,         "9271" },
2783         { AR_SREV_VERSION_9300,         "9300" },
2784 };
2785
2786 /* For devices with external radios */
2787 static struct {
2788         u16 version;
2789         const char * name;
2790 } ath_rf_names[] = {
2791         { 0,                            "5133" },
2792         { AR_RAD5133_SREV_MAJOR,        "5133" },
2793         { AR_RAD5122_SREV_MAJOR,        "5122" },
2794         { AR_RAD2133_SREV_MAJOR,        "2133" },
2795         { AR_RAD2122_SREV_MAJOR,        "2122" }
2796 };
2797
2798 /*
2799  * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2800  */
2801 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2802 {
2803         int i;
2804
2805         for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2806                 if (ath_mac_bb_names[i].version == mac_bb_version) {
2807                         return ath_mac_bb_names[i].name;
2808                 }
2809         }
2810
2811         return "????";
2812 }
2813
2814 /*
2815  * Return the RF name. "????" is returned if the RF is unknown.
2816  * Used for devices with external radios.
2817  */
2818 static const char *ath9k_hw_rf_name(u16 rf_version)
2819 {
2820         int i;
2821
2822         for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2823                 if (ath_rf_names[i].version == rf_version) {
2824                         return ath_rf_names[i].name;
2825                 }
2826         }
2827
2828         return "????";
2829 }
2830
2831 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
2832 {
2833         int used;
2834
2835         /* chipsets >= AR9280 are single-chip */
2836         if (AR_SREV_9280_10_OR_LATER(ah)) {
2837                 used = snprintf(hw_name, len,
2838                                "Atheros AR%s Rev:%x",
2839                                ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2840                                ah->hw_version.macRev);
2841         }
2842         else {
2843                 used = snprintf(hw_name, len,
2844                                "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
2845                                ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2846                                ah->hw_version.macRev,
2847                                ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
2848                                                 AR_RADIO_SREV_MAJOR)),
2849                                ah->hw_version.phyRev);
2850         }
2851
2852         hw_name[used] = '\0';
2853 }
2854 EXPORT_SYMBOL(ath9k_hw_name);