2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include <asm/unaligned.h>
24 #define ATH9K_CLOCK_RATE_CCK 22
25 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
26 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
28 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
29 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan);
30 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
31 struct ar5416_eeprom_def *pEepData,
34 MODULE_AUTHOR("Atheros Communications");
35 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
36 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
37 MODULE_LICENSE("Dual BSD/GPL");
39 static int __init ath9k_init(void)
43 module_init(ath9k_init);
45 static void __exit ath9k_exit(void)
49 module_exit(ath9k_exit);
51 /********************/
52 /* Helper Functions */
53 /********************/
55 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
57 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
59 if (!ah->curchan) /* should really check for CCK instead */
60 return usecs *ATH9K_CLOCK_RATE_CCK;
61 if (conf->channel->band == IEEE80211_BAND_2GHZ)
62 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
63 return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
66 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
68 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
70 if (conf_is_ht40(conf))
71 return ath9k_hw_mac_clks(ah, usecs) * 2;
73 return ath9k_hw_mac_clks(ah, usecs);
76 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
80 BUG_ON(timeout < AH_TIME_QUANTUM);
82 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
83 if ((REG_READ(ah, reg) & mask) == val)
86 udelay(AH_TIME_QUANTUM);
89 ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
90 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
91 timeout, reg, REG_READ(ah, reg), mask, val);
95 EXPORT_SYMBOL(ath9k_hw_wait);
97 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
102 for (i = 0, retval = 0; i < n; i++) {
103 retval = (retval << 1) | (val & 1);
109 bool ath9k_get_channel_edges(struct ath_hw *ah,
113 struct ath9k_hw_capabilities *pCap = &ah->caps;
115 if (flags & CHANNEL_5GHZ) {
116 *low = pCap->low_5ghz_chan;
117 *high = pCap->high_5ghz_chan;
120 if ((flags & CHANNEL_2GHZ)) {
121 *low = pCap->low_2ghz_chan;
122 *high = pCap->high_2ghz_chan;
128 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
130 u32 frameLen, u16 rateix,
133 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
139 case WLAN_RC_PHY_CCK:
140 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
143 numBits = frameLen << 3;
144 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
146 case WLAN_RC_PHY_OFDM:
147 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
148 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
149 numBits = OFDM_PLCP_BITS + (frameLen << 3);
150 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
151 txTime = OFDM_SIFS_TIME_QUARTER
152 + OFDM_PREAMBLE_TIME_QUARTER
153 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
154 } else if (ah->curchan &&
155 IS_CHAN_HALF_RATE(ah->curchan)) {
156 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
157 numBits = OFDM_PLCP_BITS + (frameLen << 3);
158 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
159 txTime = OFDM_SIFS_TIME_HALF +
160 OFDM_PREAMBLE_TIME_HALF
161 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
163 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
164 numBits = OFDM_PLCP_BITS + (frameLen << 3);
165 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
166 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
167 + (numSymbols * OFDM_SYMBOL_TIME);
171 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
172 "Unknown phy %u (rate ix %u)\n", phy, rateix);
179 EXPORT_SYMBOL(ath9k_hw_computetxtime);
181 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
182 struct ath9k_channel *chan,
183 struct chan_centers *centers)
187 if (!IS_CHAN_HT40(chan)) {
188 centers->ctl_center = centers->ext_center =
189 centers->synth_center = chan->channel;
193 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
194 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
195 centers->synth_center =
196 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
199 centers->synth_center =
200 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
204 centers->ctl_center =
205 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
206 /* 25 MHz spacing is supported by hw but not on upper layers */
207 centers->ext_center =
208 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
215 static void ath9k_hw_read_revisions(struct ath_hw *ah)
219 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
222 val = REG_READ(ah, AR_SREV);
223 ah->hw_version.macVersion =
224 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
225 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
226 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
228 if (!AR_SREV_9100(ah))
229 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
231 ah->hw_version.macRev = val & AR_SREV_REVISION;
233 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
234 ah->is_pciexpress = true;
238 static int ath9k_hw_get_radiorev(struct ath_hw *ah)
243 REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
245 for (i = 0; i < 8; i++)
246 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
247 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
248 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
250 return ath9k_hw_reverse_bits(val, 8);
253 /************************************/
254 /* HW Attach, Detach, Init Routines */
255 /************************************/
257 static void ath9k_hw_disablepcie(struct ath_hw *ah)
259 if (AR_SREV_9100(ah))
262 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
263 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
264 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
265 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
266 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
267 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
268 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
269 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
270 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
272 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
275 static bool ath9k_hw_chip_test(struct ath_hw *ah)
277 struct ath_common *common = ath9k_hw_common(ah);
278 u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
280 u32 patternData[4] = { 0x55555555,
286 for (i = 0; i < 2; i++) {
287 u32 addr = regAddr[i];
290 regHold[i] = REG_READ(ah, addr);
291 for (j = 0; j < 0x100; j++) {
292 wrData = (j << 16) | j;
293 REG_WRITE(ah, addr, wrData);
294 rdData = REG_READ(ah, addr);
295 if (rdData != wrData) {
296 ath_print(common, ATH_DBG_FATAL,
297 "address test failed "
298 "addr: 0x%08x - wr:0x%08x != "
300 addr, wrData, rdData);
304 for (j = 0; j < 4; j++) {
305 wrData = patternData[j];
306 REG_WRITE(ah, addr, wrData);
307 rdData = REG_READ(ah, addr);
308 if (wrData != rdData) {
309 ath_print(common, ATH_DBG_FATAL,
310 "address test failed "
311 "addr: 0x%08x - wr:0x%08x != "
313 addr, wrData, rdData);
317 REG_WRITE(ah, regAddr[i], regHold[i]);
324 static void ath9k_hw_init_config(struct ath_hw *ah)
328 ah->config.dma_beacon_response_time = 2;
329 ah->config.sw_beacon_response_time = 10;
330 ah->config.additional_swba_backoff = 0;
331 ah->config.ack_6mb = 0x0;
332 ah->config.cwm_ignore_extcca = 0;
333 ah->config.pcie_powersave_enable = 0;
334 ah->config.pcie_clock_req = 0;
335 ah->config.pcie_waen = 0;
336 ah->config.analog_shiftreg = 1;
337 ah->config.ofdm_trig_low = 200;
338 ah->config.ofdm_trig_high = 500;
339 ah->config.cck_trig_high = 200;
340 ah->config.cck_trig_low = 100;
341 ah->config.enable_ani = 1;
343 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
344 ah->config.spurchans[i][0] = AR_NO_SPUR;
345 ah->config.spurchans[i][1] = AR_NO_SPUR;
348 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
349 ah->config.ht_enable = 1;
351 ah->config.ht_enable = 0;
353 ah->config.rx_intr_mitigation = true;
356 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
357 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
358 * This means we use it for all AR5416 devices, and the few
359 * minor PCI AR9280 devices out there.
361 * Serialization is required because these devices do not handle
362 * well the case of two concurrent reads/writes due to the latency
363 * involved. During one read/write another read/write can be issued
364 * on another CPU while the previous read/write may still be working
365 * on our hardware, if we hit this case the hardware poops in a loop.
366 * We prevent this by serializing reads and writes.
368 * This issue is not present on PCI-Express devices or pre-AR5416
369 * devices (legacy, 802.11abg).
371 if (num_possible_cpus() > 1)
372 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
374 EXPORT_SYMBOL(ath9k_hw_init);
376 static void ath9k_hw_init_defaults(struct ath_hw *ah)
378 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
380 regulatory->country_code = CTRY_DEFAULT;
381 regulatory->power_limit = MAX_RATE_POWER;
382 regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
384 ah->hw_version.magic = AR5416_MAGIC;
385 ah->hw_version.subvendorid = 0;
388 if (ah->hw_version.devid == AR5416_AR9100_DEVID)
389 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
390 if (!AR_SREV_9100(ah))
391 ah->ah_flags = AH_USE_EEPROM;
394 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
395 ah->beacon_interval = 100;
396 ah->enable_32kHz_clock = DONT_USE_32KHZ;
397 ah->slottime = (u32) -1;
398 ah->globaltxtimeout = (u32) -1;
399 ah->power_mode = ATH9K_PM_UNDEFINED;
402 static int ath9k_hw_rf_claim(struct ath_hw *ah)
406 REG_WRITE(ah, AR_PHY(0), 0x00000007);
408 val = ath9k_hw_get_radiorev(ah);
409 switch (val & AR_RADIO_SREV_MAJOR) {
411 val = AR_RAD5133_SREV_MAJOR;
413 case AR_RAD5133_SREV_MAJOR:
414 case AR_RAD5122_SREV_MAJOR:
415 case AR_RAD2133_SREV_MAJOR:
416 case AR_RAD2122_SREV_MAJOR:
419 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
420 "Radio Chip Rev 0x%02X not supported\n",
421 val & AR_RADIO_SREV_MAJOR);
425 ah->hw_version.analog5GhzRev = val;
430 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
432 struct ath_common *common = ath9k_hw_common(ah);
438 for (i = 0; i < 3; i++) {
439 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
441 common->macaddr[2 * i] = eeval >> 8;
442 common->macaddr[2 * i + 1] = eeval & 0xff;
444 if (sum == 0 || sum == 0xffff * 3)
445 return -EADDRNOTAVAIL;
450 static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
454 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
455 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
457 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
458 INIT_INI_ARRAY(&ah->iniModesRxGain,
459 ar9280Modes_backoff_13db_rxgain_9280_2,
460 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
461 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
462 INIT_INI_ARRAY(&ah->iniModesRxGain,
463 ar9280Modes_backoff_23db_rxgain_9280_2,
464 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
466 INIT_INI_ARRAY(&ah->iniModesRxGain,
467 ar9280Modes_original_rxgain_9280_2,
468 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
470 INIT_INI_ARRAY(&ah->iniModesRxGain,
471 ar9280Modes_original_rxgain_9280_2,
472 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
476 static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
480 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
481 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
483 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
484 INIT_INI_ARRAY(&ah->iniModesTxGain,
485 ar9280Modes_high_power_tx_gain_9280_2,
486 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
488 INIT_INI_ARRAY(&ah->iniModesTxGain,
489 ar9280Modes_original_tx_gain_9280_2,
490 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
492 INIT_INI_ARRAY(&ah->iniModesTxGain,
493 ar9280Modes_original_tx_gain_9280_2,
494 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
498 static int ath9k_hw_post_init(struct ath_hw *ah)
502 if (!AR_SREV_9271(ah)) {
503 if (!ath9k_hw_chip_test(ah))
507 ecode = ath9k_hw_rf_claim(ah);
511 ecode = ath9k_hw_eeprom_init(ah);
515 ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
516 "Eeprom VER: %d, REV: %d\n",
517 ah->eep_ops->get_eeprom_ver(ah),
518 ah->eep_ops->get_eeprom_rev(ah));
520 if (!AR_SREV_9280_10_OR_LATER(ah)) {
521 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
523 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
524 "Failed allocating banks for "
530 if (!AR_SREV_9100(ah)) {
531 ath9k_hw_ani_setup(ah);
532 ath9k_hw_ani_init(ah);
538 static bool ath9k_hw_devid_supported(u16 devid)
541 case AR5416_DEVID_PCI:
542 case AR5416_DEVID_PCIE:
543 case AR5416_AR9100_DEVID:
544 case AR9160_DEVID_PCI:
545 case AR9280_DEVID_PCI:
546 case AR9280_DEVID_PCIE:
547 case AR9285_DEVID_PCIE:
548 case AR5416_DEVID_AR9287_PCI:
549 case AR5416_DEVID_AR9287_PCIE:
550 case AR2427_DEVID_PCIE:
558 static bool ath9k_hw_macversion_supported(u32 macversion)
560 switch (macversion) {
561 case AR_SREV_VERSION_5416_PCI:
562 case AR_SREV_VERSION_5416_PCIE:
563 case AR_SREV_VERSION_9160:
564 case AR_SREV_VERSION_9100:
565 case AR_SREV_VERSION_9280:
566 case AR_SREV_VERSION_9285:
567 case AR_SREV_VERSION_9287:
568 case AR_SREV_VERSION_9271:
576 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
578 if (AR_SREV_9160_10_OR_LATER(ah)) {
579 if (AR_SREV_9280_10_OR_LATER(ah)) {
580 ah->iq_caldata.calData = &iq_cal_single_sample;
581 ah->adcgain_caldata.calData =
582 &adc_gain_cal_single_sample;
583 ah->adcdc_caldata.calData =
584 &adc_dc_cal_single_sample;
585 ah->adcdc_calinitdata.calData =
588 ah->iq_caldata.calData = &iq_cal_multi_sample;
589 ah->adcgain_caldata.calData =
590 &adc_gain_cal_multi_sample;
591 ah->adcdc_caldata.calData =
592 &adc_dc_cal_multi_sample;
593 ah->adcdc_calinitdata.calData =
596 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
600 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
602 if (AR_SREV_9271(ah)) {
603 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271,
604 ARRAY_SIZE(ar9271Modes_9271), 6);
605 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271,
606 ARRAY_SIZE(ar9271Common_9271), 2);
607 INIT_INI_ARRAY(&ah->iniCommon_normal_cck_fir_coeff_9271,
608 ar9271Common_normal_cck_fir_coeff_9271,
609 ARRAY_SIZE(ar9271Common_normal_cck_fir_coeff_9271), 2);
610 INIT_INI_ARRAY(&ah->iniCommon_japan_2484_cck_fir_coeff_9271,
611 ar9271Common_japan_2484_cck_fir_coeff_9271,
612 ARRAY_SIZE(ar9271Common_japan_2484_cck_fir_coeff_9271), 2);
613 INIT_INI_ARRAY(&ah->iniModes_9271_1_0_only,
614 ar9271Modes_9271_1_0_only,
615 ARRAY_SIZE(ar9271Modes_9271_1_0_only), 6);
616 INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg,
617 ARRAY_SIZE(ar9271Modes_9271_ANI_reg), 6);
618 INIT_INI_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
619 ar9271Modes_high_power_tx_gain_9271,
620 ARRAY_SIZE(ar9271Modes_high_power_tx_gain_9271), 6);
621 INIT_INI_ARRAY(&ah->iniModes_normal_power_tx_gain_9271,
622 ar9271Modes_normal_power_tx_gain_9271,
623 ARRAY_SIZE(ar9271Modes_normal_power_tx_gain_9271), 6);
627 if (AR_SREV_9287_11_OR_LATER(ah)) {
628 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
629 ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
630 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
631 ARRAY_SIZE(ar9287Common_9287_1_1), 2);
632 if (ah->config.pcie_clock_req)
633 INIT_INI_ARRAY(&ah->iniPcieSerdes,
634 ar9287PciePhy_clkreq_off_L1_9287_1_1,
635 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
637 INIT_INI_ARRAY(&ah->iniPcieSerdes,
638 ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
639 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
641 } else if (AR_SREV_9287_10_OR_LATER(ah)) {
642 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0,
643 ARRAY_SIZE(ar9287Modes_9287_1_0), 6);
644 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0,
645 ARRAY_SIZE(ar9287Common_9287_1_0), 2);
647 if (ah->config.pcie_clock_req)
648 INIT_INI_ARRAY(&ah->iniPcieSerdes,
649 ar9287PciePhy_clkreq_off_L1_9287_1_0,
650 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2);
652 INIT_INI_ARRAY(&ah->iniPcieSerdes,
653 ar9287PciePhy_clkreq_always_on_L1_9287_1_0,
654 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0),
656 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
659 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
660 ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
661 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
662 ARRAY_SIZE(ar9285Common_9285_1_2), 2);
664 if (ah->config.pcie_clock_req) {
665 INIT_INI_ARRAY(&ah->iniPcieSerdes,
666 ar9285PciePhy_clkreq_off_L1_9285_1_2,
667 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
669 INIT_INI_ARRAY(&ah->iniPcieSerdes,
670 ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
671 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
674 } else if (AR_SREV_9285_10_OR_LATER(ah)) {
675 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
676 ARRAY_SIZE(ar9285Modes_9285), 6);
677 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
678 ARRAY_SIZE(ar9285Common_9285), 2);
680 if (ah->config.pcie_clock_req) {
681 INIT_INI_ARRAY(&ah->iniPcieSerdes,
682 ar9285PciePhy_clkreq_off_L1_9285,
683 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
685 INIT_INI_ARRAY(&ah->iniPcieSerdes,
686 ar9285PciePhy_clkreq_always_on_L1_9285,
687 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
689 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
690 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
691 ARRAY_SIZE(ar9280Modes_9280_2), 6);
692 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
693 ARRAY_SIZE(ar9280Common_9280_2), 2);
695 if (ah->config.pcie_clock_req) {
696 INIT_INI_ARRAY(&ah->iniPcieSerdes,
697 ar9280PciePhy_clkreq_off_L1_9280,
698 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
700 INIT_INI_ARRAY(&ah->iniPcieSerdes,
701 ar9280PciePhy_clkreq_always_on_L1_9280,
702 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
704 INIT_INI_ARRAY(&ah->iniModesAdditional,
705 ar9280Modes_fast_clock_9280_2,
706 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
707 } else if (AR_SREV_9280_10_OR_LATER(ah)) {
708 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
709 ARRAY_SIZE(ar9280Modes_9280), 6);
710 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
711 ARRAY_SIZE(ar9280Common_9280), 2);
712 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
713 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
714 ARRAY_SIZE(ar5416Modes_9160), 6);
715 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
716 ARRAY_SIZE(ar5416Common_9160), 2);
717 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
718 ARRAY_SIZE(ar5416Bank0_9160), 2);
719 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
720 ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
721 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
722 ARRAY_SIZE(ar5416Bank1_9160), 2);
723 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
724 ARRAY_SIZE(ar5416Bank2_9160), 2);
725 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
726 ARRAY_SIZE(ar5416Bank3_9160), 3);
727 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
728 ARRAY_SIZE(ar5416Bank6_9160), 3);
729 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
730 ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
731 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
732 ARRAY_SIZE(ar5416Bank7_9160), 2);
733 if (AR_SREV_9160_11(ah)) {
734 INIT_INI_ARRAY(&ah->iniAddac,
736 ARRAY_SIZE(ar5416Addac_91601_1), 2);
738 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
739 ARRAY_SIZE(ar5416Addac_9160), 2);
741 } else if (AR_SREV_9100_OR_LATER(ah)) {
742 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
743 ARRAY_SIZE(ar5416Modes_9100), 6);
744 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
745 ARRAY_SIZE(ar5416Common_9100), 2);
746 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
747 ARRAY_SIZE(ar5416Bank0_9100), 2);
748 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
749 ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
750 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
751 ARRAY_SIZE(ar5416Bank1_9100), 2);
752 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
753 ARRAY_SIZE(ar5416Bank2_9100), 2);
754 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
755 ARRAY_SIZE(ar5416Bank3_9100), 3);
756 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
757 ARRAY_SIZE(ar5416Bank6_9100), 3);
758 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
759 ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
760 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
761 ARRAY_SIZE(ar5416Bank7_9100), 2);
762 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
763 ARRAY_SIZE(ar5416Addac_9100), 2);
765 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
766 ARRAY_SIZE(ar5416Modes), 6);
767 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
768 ARRAY_SIZE(ar5416Common), 2);
769 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
770 ARRAY_SIZE(ar5416Bank0), 2);
771 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
772 ARRAY_SIZE(ar5416BB_RfGain), 3);
773 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
774 ARRAY_SIZE(ar5416Bank1), 2);
775 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
776 ARRAY_SIZE(ar5416Bank2), 2);
777 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
778 ARRAY_SIZE(ar5416Bank3), 3);
779 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
780 ARRAY_SIZE(ar5416Bank6), 3);
781 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
782 ARRAY_SIZE(ar5416Bank6TPC), 3);
783 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
784 ARRAY_SIZE(ar5416Bank7), 2);
785 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
786 ARRAY_SIZE(ar5416Addac), 2);
790 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
792 if (AR_SREV_9287_11_OR_LATER(ah))
793 INIT_INI_ARRAY(&ah->iniModesRxGain,
794 ar9287Modes_rx_gain_9287_1_1,
795 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
796 else if (AR_SREV_9287_10(ah))
797 INIT_INI_ARRAY(&ah->iniModesRxGain,
798 ar9287Modes_rx_gain_9287_1_0,
799 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);
800 else if (AR_SREV_9280_20(ah))
801 ath9k_hw_init_rxgain_ini(ah);
803 if (AR_SREV_9287_11_OR_LATER(ah)) {
804 INIT_INI_ARRAY(&ah->iniModesTxGain,
805 ar9287Modes_tx_gain_9287_1_1,
806 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
807 } else if (AR_SREV_9287_10(ah)) {
808 INIT_INI_ARRAY(&ah->iniModesTxGain,
809 ar9287Modes_tx_gain_9287_1_0,
810 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);
811 } else if (AR_SREV_9280_20(ah)) {
812 ath9k_hw_init_txgain_ini(ah);
813 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
814 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
817 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
818 if (AR_SREV_9285E_20(ah)) {
819 INIT_INI_ARRAY(&ah->iniModesTxGain,
820 ar9285Modes_XE2_0_high_power,
822 ar9285Modes_XE2_0_high_power), 6);
824 INIT_INI_ARRAY(&ah->iniModesTxGain,
825 ar9285Modes_high_power_tx_gain_9285_1_2,
827 ar9285Modes_high_power_tx_gain_9285_1_2), 6);
830 if (AR_SREV_9285E_20(ah)) {
831 INIT_INI_ARRAY(&ah->iniModesTxGain,
832 ar9285Modes_XE2_0_normal_power,
834 ar9285Modes_XE2_0_normal_power), 6);
836 INIT_INI_ARRAY(&ah->iniModesTxGain,
837 ar9285Modes_original_tx_gain_9285_1_2,
839 ar9285Modes_original_tx_gain_9285_1_2), 6);
845 static void ath9k_hw_init_eeprom_fix(struct ath_hw *ah)
849 if (ah->hw_version.devid == AR9280_DEVID_PCI) {
852 for (i = 0; i < ah->iniModes.ia_rows; i++) {
853 u32 reg = INI_RA(&ah->iniModes, i, 0);
855 for (j = 1; j < ah->iniModes.ia_columns; j++) {
856 u32 val = INI_RA(&ah->iniModes, i, j);
858 INI_RA(&ah->iniModes, i, j) =
859 ath9k_hw_ini_fixup(ah,
867 int ath9k_hw_init(struct ath_hw *ah)
869 struct ath_common *common = ath9k_hw_common(ah);
872 if (common->bus_ops->ath_bus_type != ATH_USB) {
873 if (!ath9k_hw_devid_supported(ah->hw_version.devid)) {
874 ath_print(common, ATH_DBG_FATAL,
875 "Unsupported device ID: 0x%0x\n",
876 ah->hw_version.devid);
881 ath9k_hw_init_defaults(ah);
882 ath9k_hw_init_config(ah);
884 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
885 ath_print(common, ATH_DBG_FATAL,
886 "Couldn't reset chip\n");
890 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
891 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
895 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
896 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
897 (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
898 ah->config.serialize_regmode =
901 ah->config.serialize_regmode =
906 ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
907 ah->config.serialize_regmode);
909 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
910 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
912 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
914 if (!ath9k_hw_macversion_supported(ah->hw_version.macVersion)) {
915 ath_print(common, ATH_DBG_FATAL,
916 "Mac Chip Rev 0x%02x.%x is not supported by "
917 "this driver\n", ah->hw_version.macVersion,
918 ah->hw_version.macRev);
922 if (AR_SREV_9100(ah)) {
923 ah->iq_caldata.calData = &iq_cal_multi_sample;
924 ah->supp_cals = IQ_MISMATCH_CAL;
925 ah->is_pciexpress = false;
928 if (AR_SREV_9271(ah))
929 ah->is_pciexpress = false;
931 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
933 ath9k_hw_init_cal_settings(ah);
935 ah->ani_function = ATH9K_ANI_ALL;
936 if (AR_SREV_9280_10_OR_LATER(ah)) {
937 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
938 ah->ath9k_hw_rf_set_freq = &ath9k_hw_ar9280_set_channel;
939 ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_9280_spur_mitigate;
941 ah->ath9k_hw_rf_set_freq = &ath9k_hw_set_channel;
942 ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_spur_mitigate;
945 ath9k_hw_init_mode_regs(ah);
947 if (ah->is_pciexpress)
948 ath9k_hw_configpcipowersave(ah, 0, 0);
950 ath9k_hw_disablepcie(ah);
952 /* Support for Japan ch.14 (2484) spread */
953 if (AR_SREV_9287_11_OR_LATER(ah)) {
954 INIT_INI_ARRAY(&ah->iniCckfirNormal,
955 ar9287Common_normal_cck_fir_coeff_92871_1,
956 ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_92871_1), 2);
957 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
958 ar9287Common_japan_2484_cck_fir_coeff_92871_1,
959 ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_92871_1), 2);
962 r = ath9k_hw_post_init(ah);
966 ath9k_hw_init_mode_gain_regs(ah);
967 r = ath9k_hw_fill_cap_info(ah);
971 ath9k_hw_init_eeprom_fix(ah);
973 r = ath9k_hw_init_macaddr(ah);
975 ath_print(common, ATH_DBG_FATAL,
976 "Failed to initialize MAC address\n");
980 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
981 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
983 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
985 ath9k_init_nfcal_hist_buffer(ah);
987 common->state = ATH_HW_INITIALIZED;
992 static void ath9k_hw_init_bb(struct ath_hw *ah,
993 struct ath9k_channel *chan)
997 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
999 synthDelay = (4 * synthDelay) / 22;
1003 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
1005 udelay(synthDelay + BASE_ACTIVATE_DELAY);
1008 static void ath9k_hw_init_qos(struct ath_hw *ah)
1010 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
1011 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
1013 REG_WRITE(ah, AR_QOS_NO_ACK,
1014 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
1015 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
1016 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
1018 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
1019 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
1020 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
1021 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
1022 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
1025 static void ath9k_hw_init_pll(struct ath_hw *ah,
1026 struct ath9k_channel *chan)
1030 if (AR_SREV_9100(ah)) {
1031 if (chan && IS_CHAN_5GHZ(chan))
1036 if (AR_SREV_9280_10_OR_LATER(ah)) {
1037 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1039 if (chan && IS_CHAN_HALF_RATE(chan))
1040 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1041 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1042 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1044 if (chan && IS_CHAN_5GHZ(chan)) {
1045 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
1048 if (AR_SREV_9280_20(ah)) {
1049 if (((chan->channel % 20) == 0)
1050 || ((chan->channel % 10) == 0))
1056 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
1059 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1061 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1063 if (chan && IS_CHAN_HALF_RATE(chan))
1064 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1065 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1066 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1068 if (chan && IS_CHAN_5GHZ(chan))
1069 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1071 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1073 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1075 if (chan && IS_CHAN_HALF_RATE(chan))
1076 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1077 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1078 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1080 if (chan && IS_CHAN_5GHZ(chan))
1081 pll |= SM(0xa, AR_RTC_PLL_DIV);
1083 pll |= SM(0xb, AR_RTC_PLL_DIV);
1086 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
1088 /* Switch the core clock for ar9271 to 117Mhz */
1089 if (AR_SREV_9271(ah)) {
1091 REG_WRITE(ah, 0x50040, 0x304);
1094 udelay(RTC_PLL_SETTLE_DELAY);
1096 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1099 static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
1101 int rx_chainmask, tx_chainmask;
1103 rx_chainmask = ah->rxchainmask;
1104 tx_chainmask = ah->txchainmask;
1106 switch (rx_chainmask) {
1108 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1109 AR_PHY_SWAP_ALT_CHAIN);
1111 if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) {
1112 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1113 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1119 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1120 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1126 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1127 if (tx_chainmask == 0x5) {
1128 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1129 AR_PHY_SWAP_ALT_CHAIN);
1131 if (AR_SREV_9100(ah))
1132 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1133 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1136 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1137 enum nl80211_iftype opmode)
1139 u32 imr_reg = AR_IMR_TXERR |
1145 if (ah->config.rx_intr_mitigation)
1146 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1148 imr_reg |= AR_IMR_RXOK;
1150 imr_reg |= AR_IMR_TXOK;
1152 if (opmode == NL80211_IFTYPE_AP)
1153 imr_reg |= AR_IMR_MIB;
1155 REG_WRITE(ah, AR_IMR, imr_reg);
1156 ah->imrs2_reg |= AR_IMR_S2_GTT;
1157 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
1159 if (!AR_SREV_9100(ah)) {
1160 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1161 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1162 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1166 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
1168 u32 val = ath9k_hw_mac_to_clks(ah, us);
1169 val = min(val, (u32) 0xFFFF);
1170 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
1173 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1175 u32 val = ath9k_hw_mac_to_clks(ah, us);
1176 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
1177 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
1180 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1182 u32 val = ath9k_hw_mac_to_clks(ah, us);
1183 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
1184 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
1187 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1190 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
1191 "bad global tx timeout %u\n", tu);
1192 ah->globaltxtimeout = (u32) -1;
1195 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1196 ah->globaltxtimeout = tu;
1201 void ath9k_hw_init_global_settings(struct ath_hw *ah)
1203 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
1208 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
1211 if (ah->misc_mode != 0)
1212 REG_WRITE(ah, AR_PCU_MISC,
1213 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
1215 if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
1220 /* As defined by IEEE 802.11-2007 17.3.8.6 */
1221 slottime = ah->slottime + 3 * ah->coverage_class;
1222 acktimeout = slottime + sifstime;
1225 * Workaround for early ACK timeouts, add an offset to match the
1226 * initval's 64us ack timeout value.
1227 * This was initially only meant to work around an issue with delayed
1228 * BA frames in some implementations, but it has been found to fix ACK
1229 * timeout issues in other cases as well.
1231 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
1232 acktimeout += 64 - sifstime - ah->slottime;
1234 ath9k_hw_setslottime(ah, slottime);
1235 ath9k_hw_set_ack_timeout(ah, acktimeout);
1236 ath9k_hw_set_cts_timeout(ah, acktimeout);
1237 if (ah->globaltxtimeout != (u32) -1)
1238 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1240 EXPORT_SYMBOL(ath9k_hw_init_global_settings);
1242 void ath9k_hw_deinit(struct ath_hw *ah)
1244 struct ath_common *common = ath9k_hw_common(ah);
1246 if (common->state < ATH_HW_INITIALIZED)
1249 if (!AR_SREV_9100(ah))
1250 ath9k_hw_ani_disable(ah);
1252 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1255 if (!AR_SREV_9280_10_OR_LATER(ah))
1256 ath9k_hw_rf_free_ext_banks(ah);
1258 EXPORT_SYMBOL(ath9k_hw_deinit);
1264 static void ath9k_hw_override_ini(struct ath_hw *ah,
1265 struct ath9k_channel *chan)
1270 * Set the RX_ABORT and RX_DIS and clear if off only after
1271 * RXE is set for MAC. This prevents frames with corrupted
1272 * descriptor status.
1274 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1276 if (AR_SREV_9280_10_OR_LATER(ah)) {
1277 val = REG_READ(ah, AR_PCU_MISC_MODE2);
1279 if (!AR_SREV_9271(ah))
1280 val &= ~AR_PCU_MISC_MODE2_HWWAR1;
1282 if (AR_SREV_9287_10_OR_LATER(ah))
1283 val = val & (~AR_PCU_MISC_MODE2_HWWAR2);
1285 REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
1288 if (!AR_SREV_5416_20_OR_LATER(ah) ||
1289 AR_SREV_9280_10_OR_LATER(ah))
1292 * Disable BB clock gating
1293 * Necessary to avoid issues on AR5416 2.0
1295 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1298 * Disable RIFS search on some chips to avoid baseband
1301 if (AR_SREV_9100(ah) || AR_SREV_9160(ah)) {
1302 val = REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS);
1303 val &= ~AR_PHY_RIFS_INIT_DELAY;
1304 REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val);
1308 static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
1309 struct ar5416_eeprom_def *pEepData,
1312 struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1313 struct ath_common *common = ath9k_hw_common(ah);
1315 switch (ah->hw_version.devid) {
1316 case AR9280_DEVID_PCI:
1317 if (reg == 0x7894) {
1318 ath_print(common, ATH_DBG_EEPROM,
1319 "ini VAL: %x EEPROM: %x\n", value,
1320 (pBase->version & 0xff));
1322 if ((pBase->version & 0xff) > 0x0a) {
1323 ath_print(common, ATH_DBG_EEPROM,
1326 value &= ~AR_AN_TOP2_PWDCLKIND;
1327 value |= AR_AN_TOP2_PWDCLKIND &
1328 (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1330 ath_print(common, ATH_DBG_EEPROM,
1331 "PWDCLKIND Earlier Rev\n");
1334 ath_print(common, ATH_DBG_EEPROM,
1335 "final ini VAL: %x\n", value);
1343 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
1344 struct ar5416_eeprom_def *pEepData,
1347 if (ah->eep_map == EEP_MAP_4KBITS)
1350 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1353 static void ath9k_olc_init(struct ath_hw *ah)
1357 if (OLC_FOR_AR9287_10_LATER) {
1358 REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,
1359 AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);
1360 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0,
1361 AR9287_AN_TXPC0_TXPCMODE,
1362 AR9287_AN_TXPC0_TXPCMODE_S,
1363 AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE);
1366 for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
1367 ah->originalGain[i] =
1368 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
1374 static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
1375 struct ath9k_channel *chan)
1377 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1379 if (IS_CHAN_B(chan))
1381 else if (IS_CHAN_G(chan))
1389 static int ath9k_hw_process_ini(struct ath_hw *ah,
1390 struct ath9k_channel *chan)
1392 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1393 int i, regWrites = 0;
1394 struct ieee80211_channel *channel = chan->chan;
1395 u32 modesIndex, freqIndex;
1397 switch (chan->chanmode) {
1399 case CHANNEL_A_HT20:
1403 case CHANNEL_A_HT40PLUS:
1404 case CHANNEL_A_HT40MINUS:
1409 case CHANNEL_G_HT20:
1414 case CHANNEL_G_HT40PLUS:
1415 case CHANNEL_G_HT40MINUS:
1424 /* Set correct baseband to analog shift setting to access analog chips */
1425 REG_WRITE(ah, AR_PHY(0), 0x00000007);
1427 /* Write ADDAC shifts */
1428 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1429 ah->eep_ops->set_addac(ah, chan);
1431 if (AR_SREV_5416_22_OR_LATER(ah)) {
1432 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
1434 struct ar5416IniArray temp;
1436 sizeof(u32) * ah->iniAddac.ia_rows *
1437 ah->iniAddac.ia_columns;
1439 /* For AR5416 2.0/2.1 */
1440 memcpy(ah->addac5416_21,
1441 ah->iniAddac.ia_array, addacSize);
1443 /* override CLKDRV value at [row, column] = [31, 1] */
1444 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
1446 temp.ia_array = ah->addac5416_21;
1447 temp.ia_columns = ah->iniAddac.ia_columns;
1448 temp.ia_rows = ah->iniAddac.ia_rows;
1449 REG_WRITE_ARRAY(&temp, 1, regWrites);
1452 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1454 for (i = 0; i < ah->iniModes.ia_rows; i++) {
1455 u32 reg = INI_RA(&ah->iniModes, i, 0);
1456 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
1458 REG_WRITE(ah, reg, val);
1460 if (reg >= 0x7800 && reg < 0x78a0
1461 && ah->config.analog_shiftreg) {
1465 DO_DELAY(regWrites);
1468 if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah))
1469 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
1471 if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
1472 AR_SREV_9287_10_OR_LATER(ah))
1473 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1475 if (AR_SREV_9271_10(ah))
1476 REG_WRITE_ARRAY(&ah->iniModes_9271_1_0_only,
1477 modesIndex, regWrites);
1479 /* Write common array parameters */
1480 for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1481 u32 reg = INI_RA(&ah->iniCommon, i, 0);
1482 u32 val = INI_RA(&ah->iniCommon, i, 1);
1484 REG_WRITE(ah, reg, val);
1486 if (reg >= 0x7800 && reg < 0x78a0
1487 && ah->config.analog_shiftreg) {
1491 DO_DELAY(regWrites);
1494 if (AR_SREV_9271(ah)) {
1495 if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) == 1)
1496 REG_WRITE_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
1497 modesIndex, regWrites);
1499 REG_WRITE_ARRAY(&ah->iniModes_normal_power_tx_gain_9271,
1500 modesIndex, regWrites);
1503 ath9k_hw_write_regs(ah, freqIndex, regWrites);
1505 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1506 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
1510 ath9k_hw_override_ini(ah, chan);
1511 ath9k_hw_set_regs(ah, chan);
1512 ath9k_hw_init_chain_masks(ah);
1514 if (OLC_FOR_AR9280_20_LATER)
1518 ah->eep_ops->set_txpower(ah, chan,
1519 ath9k_regd_get_ctl(regulatory, chan),
1520 channel->max_antenna_gain * 2,
1521 channel->max_power * 2,
1522 min((u32) MAX_RATE_POWER,
1523 (u32) regulatory->power_limit));
1525 /* Write analog registers */
1526 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1527 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1528 "ar5416SetRfRegs failed\n");
1535 /****************************************/
1536 /* Reset and Channel Switching Routines */
1537 /****************************************/
1539 static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
1546 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1547 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1549 if (!AR_SREV_9280_10_OR_LATER(ah))
1550 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1551 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1553 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1554 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1556 REG_WRITE(ah, AR_PHY_MODE, rfMode);
1559 static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
1561 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1564 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1569 * set AHB_MODE not to do cacheline prefetches
1571 regval = REG_READ(ah, AR_AHB_MODE);
1572 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1575 * let mac dma reads be in 128 byte chunks
1577 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1578 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1581 * Restore TX Trigger Level to its pre-reset value.
1582 * The initial value depends on whether aggregation is enabled, and is
1583 * adjusted whenever underruns are detected.
1585 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1588 * let mac dma writes be in 128 byte chunks
1590 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1591 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1594 * Setup receive FIFO threshold to hold off TX activities
1596 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1599 * reduce the number of usable entries in PCU TXBUF to avoid
1600 * wrap around issues.
1602 if (AR_SREV_9285(ah)) {
1603 /* For AR9285 the number of Fifos are reduced to half.
1604 * So set the usable tx buf size also to half to
1605 * avoid data/delimiter underruns
1607 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1608 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1609 } else if (!AR_SREV_9271(ah)) {
1610 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1611 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1615 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1619 val = REG_READ(ah, AR_STA_ID1);
1620 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1622 case NL80211_IFTYPE_AP:
1623 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1624 | AR_STA_ID1_KSRCH_MODE);
1625 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1627 case NL80211_IFTYPE_ADHOC:
1628 case NL80211_IFTYPE_MESH_POINT:
1629 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1630 | AR_STA_ID1_KSRCH_MODE);
1631 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1633 case NL80211_IFTYPE_STATION:
1634 case NL80211_IFTYPE_MONITOR:
1635 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1640 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
1645 u32 coef_exp, coef_man;
1647 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1648 if ((coef_scaled >> coef_exp) & 0x1)
1651 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1653 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1655 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1656 *coef_exponent = coef_exp - 16;
1659 static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
1660 struct ath9k_channel *chan)
1662 u32 coef_scaled, ds_coef_exp, ds_coef_man;
1663 u32 clockMhzScaled = 0x64000000;
1664 struct chan_centers centers;
1666 if (IS_CHAN_HALF_RATE(chan))
1667 clockMhzScaled = clockMhzScaled >> 1;
1668 else if (IS_CHAN_QUARTER_RATE(chan))
1669 clockMhzScaled = clockMhzScaled >> 2;
1671 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
1672 coef_scaled = clockMhzScaled / centers.synth_center;
1674 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1677 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1678 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1679 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1680 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1682 coef_scaled = (9 * coef_scaled) / 10;
1684 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1687 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1688 AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1689 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1690 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1693 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1698 if (AR_SREV_9100(ah)) {
1699 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1700 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1701 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1702 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1703 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1706 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1707 AR_RTC_FORCE_WAKE_ON_INT);
1709 if (AR_SREV_9100(ah)) {
1710 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1711 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1713 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1715 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1716 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1717 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1718 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1720 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1723 rst_flags = AR_RTC_RC_MAC_WARM;
1724 if (type == ATH9K_RESET_COLD)
1725 rst_flags |= AR_RTC_RC_MAC_COLD;
1728 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1731 REG_WRITE(ah, AR_RTC_RC, 0);
1732 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1733 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1734 "RTC stuck in MAC reset\n");
1738 if (!AR_SREV_9100(ah))
1739 REG_WRITE(ah, AR_RC, 0);
1741 if (AR_SREV_9100(ah))
1747 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1749 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1750 AR_RTC_FORCE_WAKE_ON_INT);
1752 if (!AR_SREV_9100(ah))
1753 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1755 REG_WRITE(ah, AR_RTC_RESET, 0);
1758 if (!AR_SREV_9100(ah))
1759 REG_WRITE(ah, AR_RC, 0);
1761 REG_WRITE(ah, AR_RTC_RESET, 1);
1763 if (!ath9k_hw_wait(ah,
1768 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1769 "RTC not waking up\n");
1773 ath9k_hw_read_revisions(ah);
1775 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1778 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1780 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1781 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1784 case ATH9K_RESET_POWER_ON:
1785 return ath9k_hw_set_reset_power_on(ah);
1786 case ATH9K_RESET_WARM:
1787 case ATH9K_RESET_COLD:
1788 return ath9k_hw_set_reset(ah, type);
1794 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan)
1797 u32 enableDacFifo = 0;
1799 if (AR_SREV_9285_10_OR_LATER(ah))
1800 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1801 AR_PHY_FC_ENABLE_DAC_FIFO);
1803 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1804 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1806 if (IS_CHAN_HT40(chan)) {
1807 phymode |= AR_PHY_FC_DYN2040_EN;
1809 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1810 (chan->chanmode == CHANNEL_G_HT40PLUS))
1811 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1814 REG_WRITE(ah, AR_PHY_TURBO, phymode);
1816 ath9k_hw_set11nmac2040(ah);
1818 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1819 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1822 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1823 struct ath9k_channel *chan)
1825 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1826 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1828 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1831 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1834 ah->chip_fullsleep = false;
1835 ath9k_hw_init_pll(ah, chan);
1836 ath9k_hw_set_rfmode(ah, chan);
1841 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1842 struct ath9k_channel *chan)
1844 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1845 struct ath_common *common = ath9k_hw_common(ah);
1846 struct ieee80211_channel *channel = chan->chan;
1847 u32 synthDelay, qnum;
1850 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1851 if (ath9k_hw_numtxpending(ah, qnum)) {
1852 ath_print(common, ATH_DBG_QUEUE,
1853 "Transmit frames pending on "
1854 "queue %d\n", qnum);
1859 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1860 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1861 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
1862 ath_print(common, ATH_DBG_FATAL,
1863 "Could not kill baseband RX\n");
1867 ath9k_hw_set_regs(ah, chan);
1869 r = ah->ath9k_hw_rf_set_freq(ah, chan);
1871 ath_print(common, ATH_DBG_FATAL,
1872 "Failed to set channel\n");
1876 ah->eep_ops->set_txpower(ah, chan,
1877 ath9k_regd_get_ctl(regulatory, chan),
1878 channel->max_antenna_gain * 2,
1879 channel->max_power * 2,
1880 min((u32) MAX_RATE_POWER,
1881 (u32) regulatory->power_limit));
1883 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1884 if (IS_CHAN_B(chan))
1885 synthDelay = (4 * synthDelay) / 22;
1889 udelay(synthDelay + BASE_ACTIVATE_DELAY);
1891 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1893 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1894 ath9k_hw_set_delta_slope(ah, chan);
1896 ah->ath9k_hw_spur_mitigate_freq(ah, chan);
1898 if (!chan->oneTimeCalsDone)
1899 chan->oneTimeCalsDone = true;
1904 static void ath9k_enable_rfkill(struct ath_hw *ah)
1906 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
1907 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
1909 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
1910 AR_GPIO_INPUT_MUX2_RFSILENT);
1912 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
1913 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
1916 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1917 bool bChannelChange)
1919 struct ath_common *common = ath9k_hw_common(ah);
1921 struct ath9k_channel *curchan = ah->curchan;
1925 int i, rx_chainmask, r;
1927 ah->txchainmask = common->tx_chainmask;
1928 ah->rxchainmask = common->rx_chainmask;
1930 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1933 if (curchan && !ah->chip_fullsleep)
1934 ath9k_hw_getnf(ah, curchan);
1936 if (bChannelChange &&
1937 (ah->chip_fullsleep != true) &&
1938 (ah->curchan != NULL) &&
1939 (chan->channel != ah->curchan->channel) &&
1940 ((chan->channelFlags & CHANNEL_ALL) ==
1941 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
1942 !(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) ||
1943 IS_CHAN_A_5MHZ_SPACED(ah->curchan))) {
1945 if (ath9k_hw_channel_change(ah, chan)) {
1946 ath9k_hw_loadnf(ah, ah->curchan);
1947 ath9k_hw_start_nfcal(ah);
1952 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1953 if (saveDefAntenna == 0)
1956 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1958 /* For chips on which RTC reset is done, save TSF before it gets cleared */
1959 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1960 tsf = ath9k_hw_gettsf64(ah);
1962 saveLedState = REG_READ(ah, AR_CFG_LED) &
1963 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1964 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1966 ath9k_hw_mark_phy_inactive(ah);
1968 /* Only required on the first reset */
1969 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1971 AR9271_RESET_POWER_DOWN_CONTROL,
1972 AR9271_RADIO_RF_RST);
1976 if (!ath9k_hw_chip_reset(ah, chan)) {
1977 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
1981 /* Only required on the first reset */
1982 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1983 ah->htc_reset_init = false;
1985 AR9271_RESET_POWER_DOWN_CONTROL,
1986 AR9271_GATE_MAC_CTL);
1991 if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1992 ath9k_hw_settsf64(ah, tsf);
1994 if (AR_SREV_9280_10_OR_LATER(ah))
1995 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1997 if (AR_SREV_9287_12_OR_LATER(ah)) {
1998 /* Enable ASYNC FIFO */
1999 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2000 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
2001 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
2002 REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2003 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
2004 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2005 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
2007 r = ath9k_hw_process_ini(ah, chan);
2011 /* Setup MFP options for CCMP */
2012 if (AR_SREV_9280_20_OR_LATER(ah)) {
2013 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
2014 * frames when constructing CCMP AAD. */
2015 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
2017 ah->sw_mgmt_crypto = false;
2018 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2019 /* Disable hardware crypto for management frames */
2020 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
2021 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
2022 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2023 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
2024 ah->sw_mgmt_crypto = true;
2026 ah->sw_mgmt_crypto = true;
2028 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2029 ath9k_hw_set_delta_slope(ah, chan);
2031 ah->ath9k_hw_spur_mitigate_freq(ah, chan);
2032 ah->eep_ops->set_board_values(ah, chan);
2034 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
2035 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
2037 | AR_STA_ID1_RTS_USE_DEF
2039 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2040 | ah->sta_id1_defaults);
2041 ath9k_hw_set_operating_mode(ah, ah->opmode);
2043 ath_hw_setbssidmask(common);
2045 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2047 ath9k_hw_write_associd(ah);
2049 REG_WRITE(ah, AR_ISR, ~0);
2051 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2053 r = ah->ath9k_hw_rf_set_freq(ah, chan);
2057 for (i = 0; i < AR_NUM_DCU; i++)
2058 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2061 for (i = 0; i < ah->caps.total_queues; i++)
2062 ath9k_hw_resettxqueue(ah, i);
2064 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
2065 ath9k_hw_init_qos(ah);
2067 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2068 ath9k_enable_rfkill(ah);
2070 ath9k_hw_init_global_settings(ah);
2072 if (AR_SREV_9287_12_OR_LATER(ah)) {
2073 REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
2074 AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
2075 REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
2076 AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
2077 REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
2078 AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
2080 REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
2081 REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
2083 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
2084 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
2085 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
2086 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
2088 if (AR_SREV_9287_12_OR_LATER(ah)) {
2089 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2090 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
2093 REG_WRITE(ah, AR_STA_ID1,
2094 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2096 ath9k_hw_set_dma(ah);
2098 REG_WRITE(ah, AR_OBS, 8);
2100 if (ah->config.rx_intr_mitigation) {
2101 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2102 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2105 ath9k_hw_init_bb(ah, chan);
2107 if (!ath9k_hw_init_cal(ah, chan))
2110 rx_chainmask = ah->rxchainmask;
2111 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2112 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2113 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2116 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2119 * For big endian systems turn on swapping for descriptors
2121 if (AR_SREV_9100(ah)) {
2123 mask = REG_READ(ah, AR_CFG);
2124 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2125 ath_print(common, ATH_DBG_RESET,
2126 "CFG Byte Swap Set 0x%x\n", mask);
2129 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2130 REG_WRITE(ah, AR_CFG, mask);
2131 ath_print(common, ATH_DBG_RESET,
2132 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
2135 /* Configure AR9271 target WLAN */
2136 if (AR_SREV_9271(ah))
2137 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
2140 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2144 if (ah->btcoex_hw.enabled)
2145 ath9k_hw_btcoex_enable(ah);
2149 EXPORT_SYMBOL(ath9k_hw_reset);
2151 /************************/
2152 /* Key Cache Management */
2153 /************************/
2155 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
2159 if (entry >= ah->caps.keycache_size) {
2160 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2161 "keychache entry %u out of range\n", entry);
2165 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2167 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2168 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2169 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2170 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2171 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2172 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2173 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2174 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2176 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2177 u16 micentry = entry + 64;
2179 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2180 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2181 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2182 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2188 EXPORT_SYMBOL(ath9k_hw_keyreset);
2190 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
2194 if (entry >= ah->caps.keycache_size) {
2195 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2196 "keychache entry %u out of range\n", entry);
2201 macHi = (mac[5] << 8) | mac[4];
2202 macLo = (mac[3] << 24) |
2207 macLo |= (macHi & 1) << 31;
2212 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2213 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2217 EXPORT_SYMBOL(ath9k_hw_keysetmac);
2219 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2220 const struct ath9k_keyval *k,
2223 const struct ath9k_hw_capabilities *pCap = &ah->caps;
2224 struct ath_common *common = ath9k_hw_common(ah);
2225 u32 key0, key1, key2, key3, key4;
2228 if (entry >= pCap->keycache_size) {
2229 ath_print(common, ATH_DBG_FATAL,
2230 "keycache entry %u out of range\n", entry);
2234 switch (k->kv_type) {
2235 case ATH9K_CIPHER_AES_OCB:
2236 keyType = AR_KEYTABLE_TYPE_AES;
2238 case ATH9K_CIPHER_AES_CCM:
2239 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2240 ath_print(common, ATH_DBG_ANY,
2241 "AES-CCM not supported by mac rev 0x%x\n",
2242 ah->hw_version.macRev);
2245 keyType = AR_KEYTABLE_TYPE_CCM;
2247 case ATH9K_CIPHER_TKIP:
2248 keyType = AR_KEYTABLE_TYPE_TKIP;
2249 if (ATH9K_IS_MIC_ENABLED(ah)
2250 && entry + 64 >= pCap->keycache_size) {
2251 ath_print(common, ATH_DBG_ANY,
2252 "entry %u inappropriate for TKIP\n", entry);
2256 case ATH9K_CIPHER_WEP:
2257 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
2258 ath_print(common, ATH_DBG_ANY,
2259 "WEP key length %u too small\n", k->kv_len);
2262 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
2263 keyType = AR_KEYTABLE_TYPE_40;
2264 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2265 keyType = AR_KEYTABLE_TYPE_104;
2267 keyType = AR_KEYTABLE_TYPE_128;
2269 case ATH9K_CIPHER_CLR:
2270 keyType = AR_KEYTABLE_TYPE_CLR;
2273 ath_print(common, ATH_DBG_FATAL,
2274 "cipher %u not supported\n", k->kv_type);
2278 key0 = get_unaligned_le32(k->kv_val + 0);
2279 key1 = get_unaligned_le16(k->kv_val + 4);
2280 key2 = get_unaligned_le32(k->kv_val + 6);
2281 key3 = get_unaligned_le16(k->kv_val + 10);
2282 key4 = get_unaligned_le32(k->kv_val + 12);
2283 if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2287 * Note: Key cache registers access special memory area that requires
2288 * two 32-bit writes to actually update the values in the internal
2289 * memory. Consequently, the exact order and pairs used here must be
2293 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2294 u16 micentry = entry + 64;
2297 * Write inverted key[47:0] first to avoid Michael MIC errors
2298 * on frames that could be sent or received at the same time.
2299 * The correct key will be written in the end once everything
2302 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2303 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2305 /* Write key[95:48] */
2306 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2307 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2309 /* Write key[127:96] and key type */
2310 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2311 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2313 /* Write MAC address for the entry */
2314 (void) ath9k_hw_keysetmac(ah, entry, mac);
2316 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
2318 * TKIP uses two key cache entries:
2319 * Michael MIC TX/RX keys in the same key cache entry
2320 * (idx = main index + 64):
2321 * key0 [31:0] = RX key [31:0]
2322 * key1 [15:0] = TX key [31:16]
2323 * key1 [31:16] = reserved
2324 * key2 [31:0] = RX key [63:32]
2325 * key3 [15:0] = TX key [15:0]
2326 * key3 [31:16] = reserved
2327 * key4 [31:0] = TX key [63:32]
2329 u32 mic0, mic1, mic2, mic3, mic4;
2331 mic0 = get_unaligned_le32(k->kv_mic + 0);
2332 mic2 = get_unaligned_le32(k->kv_mic + 4);
2333 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2334 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2335 mic4 = get_unaligned_le32(k->kv_txmic + 4);
2337 /* Write RX[31:0] and TX[31:16] */
2338 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2339 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2341 /* Write RX[63:32] and TX[15:0] */
2342 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2343 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2345 /* Write TX[63:32] and keyType(reserved) */
2346 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2347 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2348 AR_KEYTABLE_TYPE_CLR);
2352 * TKIP uses four key cache entries (two for group
2354 * Michael MIC TX/RX keys are in different key cache
2355 * entries (idx = main index + 64 for TX and
2356 * main index + 32 + 96 for RX):
2357 * key0 [31:0] = TX/RX MIC key [31:0]
2358 * key1 [31:0] = reserved
2359 * key2 [31:0] = TX/RX MIC key [63:32]
2360 * key3 [31:0] = reserved
2361 * key4 [31:0] = reserved
2363 * Upper layer code will call this function separately
2364 * for TX and RX keys when these registers offsets are
2369 mic0 = get_unaligned_le32(k->kv_mic + 0);
2370 mic2 = get_unaligned_le32(k->kv_mic + 4);
2372 /* Write MIC key[31:0] */
2373 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2374 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2376 /* Write MIC key[63:32] */
2377 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2378 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2380 /* Write TX[63:32] and keyType(reserved) */
2381 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2382 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2383 AR_KEYTABLE_TYPE_CLR);
2386 /* MAC address registers are reserved for the MIC entry */
2387 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2388 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2391 * Write the correct (un-inverted) key[47:0] last to enable
2392 * TKIP now that all other registers are set with correct
2395 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2396 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2398 /* Write key[47:0] */
2399 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2400 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2402 /* Write key[95:48] */
2403 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2404 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2406 /* Write key[127:96] and key type */
2407 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2408 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2410 /* Write MAC address for the entry */
2411 (void) ath9k_hw_keysetmac(ah, entry, mac);
2416 EXPORT_SYMBOL(ath9k_hw_set_keycache_entry);
2418 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
2420 if (entry < ah->caps.keycache_size) {
2421 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2422 if (val & AR_KEYTABLE_VALID)
2427 EXPORT_SYMBOL(ath9k_hw_keyisvalid);
2429 /******************************/
2430 /* Power Management (Chipset) */
2431 /******************************/
2433 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
2435 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2437 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2438 AR_RTC_FORCE_WAKE_EN);
2439 if (!AR_SREV_9100(ah))
2440 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2442 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
2443 REG_CLR_BIT(ah, (AR_RTC_RESET),
2448 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2450 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2452 struct ath9k_hw_capabilities *pCap = &ah->caps;
2454 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2455 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2456 AR_RTC_FORCE_WAKE_ON_INT);
2458 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2459 AR_RTC_FORCE_WAKE_EN);
2464 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2470 if ((REG_READ(ah, AR_RTC_STATUS) &
2471 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2472 if (ath9k_hw_set_reset_reg(ah,
2473 ATH9K_RESET_POWER_ON) != true) {
2476 ath9k_hw_init_pll(ah, NULL);
2478 if (AR_SREV_9100(ah))
2479 REG_SET_BIT(ah, AR_RTC_RESET,
2482 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2483 AR_RTC_FORCE_WAKE_EN);
2486 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2487 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2488 if (val == AR_RTC_STATUS_ON)
2491 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2492 AR_RTC_FORCE_WAKE_EN);
2495 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2496 "Failed to wakeup in %uus\n",
2497 POWER_UP_TIME / 20);
2502 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2507 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2509 struct ath_common *common = ath9k_hw_common(ah);
2510 int status = true, setChip = true;
2511 static const char *modes[] = {
2518 if (ah->power_mode == mode)
2521 ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
2522 modes[ah->power_mode], modes[mode]);
2525 case ATH9K_PM_AWAKE:
2526 status = ath9k_hw_set_power_awake(ah, setChip);
2528 case ATH9K_PM_FULL_SLEEP:
2529 ath9k_set_power_sleep(ah, setChip);
2530 ah->chip_fullsleep = true;
2532 case ATH9K_PM_NETWORK_SLEEP:
2533 ath9k_set_power_network_sleep(ah, setChip);
2536 ath_print(common, ATH_DBG_FATAL,
2537 "Unknown power mode %u\n", mode);
2540 ah->power_mode = mode;
2544 EXPORT_SYMBOL(ath9k_hw_setpower);
2547 * Helper for ASPM support.
2549 * Disable PLL when in L0s as well as receiver clock when in L1.
2550 * This power saving option must be enabled through the SerDes.
2552 * Programming the SerDes must go through the same 288 bit serial shift
2553 * register as the other analog registers. Hence the 9 writes.
2555 void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off)
2560 if (ah->is_pciexpress != true)
2563 /* Do not touch SerDes registers */
2564 if (ah->config.pcie_powersave_enable == 2)
2567 /* Nothing to do on restore for 11N */
2569 if (AR_SREV_9280_20_OR_LATER(ah)) {
2571 * AR9280 2.0 or later chips use SerDes values from the
2572 * initvals.h initialized depending on chipset during
2575 for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
2576 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
2577 INI_RA(&ah->iniPcieSerdes, i, 1));
2579 } else if (AR_SREV_9280(ah) &&
2580 (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
2581 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2582 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2584 /* RX shut off when elecidle is asserted */
2585 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2586 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2587 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2589 /* Shut off CLKREQ active in L1 */
2590 if (ah->config.pcie_clock_req)
2591 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2593 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2595 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2596 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2597 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2599 /* Load the new settings */
2600 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2603 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2604 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2606 /* RX shut off when elecidle is asserted */
2607 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2608 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2609 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2612 * Ignore ah->ah_config.pcie_clock_req setting for
2615 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2617 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2618 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2619 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2621 /* Load the new settings */
2622 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2627 /* set bit 19 to allow forcing of pcie core into L1 state */
2628 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2630 /* Several PCIe massages to ensure proper behaviour */
2631 if (ah->config.pcie_waen) {
2632 val = ah->config.pcie_waen;
2634 val &= (~AR_WA_D3_L1_DISABLE);
2636 if (AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
2638 val = AR9285_WA_DEFAULT;
2640 val &= (~AR_WA_D3_L1_DISABLE);
2641 } else if (AR_SREV_9280(ah)) {
2643 * On AR9280 chips bit 22 of 0x4004 needs to be
2644 * set otherwise card may disappear.
2646 val = AR9280_WA_DEFAULT;
2648 val &= (~AR_WA_D3_L1_DISABLE);
2650 val = AR_WA_DEFAULT;
2653 REG_WRITE(ah, AR_WA, val);
2658 * Set PCIe workaround bits
2659 * bit 14 in WA register (disable L1) should only
2660 * be set when device enters D3 and be cleared
2661 * when device comes back to D0.
2663 if (ah->config.pcie_waen) {
2664 if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)
2665 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
2667 if (((AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
2668 AR_SREV_9287(ah)) &&
2669 (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) ||
2670 (AR_SREV_9280(ah) &&
2671 (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) {
2672 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
2677 EXPORT_SYMBOL(ath9k_hw_configpcipowersave);
2679 /**********************/
2680 /* Interrupt Handling */
2681 /**********************/
2683 bool ath9k_hw_intrpend(struct ath_hw *ah)
2687 if (AR_SREV_9100(ah))
2690 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
2691 if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
2694 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
2695 if ((host_isr & AR_INTR_SYNC_DEFAULT)
2696 && (host_isr != AR_INTR_SPURIOUS))
2701 EXPORT_SYMBOL(ath9k_hw_intrpend);
2703 bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
2707 struct ath9k_hw_capabilities *pCap = &ah->caps;
2709 bool fatal_int = false;
2710 struct ath_common *common = ath9k_hw_common(ah);
2712 if (!AR_SREV_9100(ah)) {
2713 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
2714 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
2715 == AR_RTC_STATUS_ON) {
2716 isr = REG_READ(ah, AR_ISR);
2720 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
2721 AR_INTR_SYNC_DEFAULT;
2725 if (!isr && !sync_cause)
2729 isr = REG_READ(ah, AR_ISR);
2733 if (isr & AR_ISR_BCNMISC) {
2735 isr2 = REG_READ(ah, AR_ISR_S2);
2736 if (isr2 & AR_ISR_S2_TIM)
2737 mask2 |= ATH9K_INT_TIM;
2738 if (isr2 & AR_ISR_S2_DTIM)
2739 mask2 |= ATH9K_INT_DTIM;
2740 if (isr2 & AR_ISR_S2_DTIMSYNC)
2741 mask2 |= ATH9K_INT_DTIMSYNC;
2742 if (isr2 & (AR_ISR_S2_CABEND))
2743 mask2 |= ATH9K_INT_CABEND;
2744 if (isr2 & AR_ISR_S2_GTT)
2745 mask2 |= ATH9K_INT_GTT;
2746 if (isr2 & AR_ISR_S2_CST)
2747 mask2 |= ATH9K_INT_CST;
2748 if (isr2 & AR_ISR_S2_TSFOOR)
2749 mask2 |= ATH9K_INT_TSFOOR;
2752 isr = REG_READ(ah, AR_ISR_RAC);
2753 if (isr == 0xffffffff) {
2758 *masked = isr & ATH9K_INT_COMMON;
2760 if (ah->config.rx_intr_mitigation) {
2761 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
2762 *masked |= ATH9K_INT_RX;
2765 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
2766 *masked |= ATH9K_INT_RX;
2768 (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
2772 *masked |= ATH9K_INT_TX;
2774 s0_s = REG_READ(ah, AR_ISR_S0_S);
2775 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
2776 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
2778 s1_s = REG_READ(ah, AR_ISR_S1_S);
2779 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
2780 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
2783 if (isr & AR_ISR_RXORN) {
2784 ath_print(common, ATH_DBG_INTERRUPT,
2785 "receive FIFO overrun interrupt\n");
2788 if (!AR_SREV_9100(ah)) {
2789 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2790 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
2791 if (isr5 & AR_ISR_S5_TIM_TIMER)
2792 *masked |= ATH9K_INT_TIM_TIMER;
2799 if (AR_SREV_9100(ah))
2802 if (isr & AR_ISR_GENTMR) {
2805 s5_s = REG_READ(ah, AR_ISR_S5_S);
2806 if (isr & AR_ISR_GENTMR) {
2807 ah->intr_gen_timer_trigger =
2808 MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
2810 ah->intr_gen_timer_thresh =
2811 MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
2813 if (ah->intr_gen_timer_trigger)
2814 *masked |= ATH9K_INT_GENTIMER;
2822 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
2826 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
2827 ath_print(common, ATH_DBG_ANY,
2828 "received PCI FATAL interrupt\n");
2830 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
2831 ath_print(common, ATH_DBG_ANY,
2832 "received PCI PERR interrupt\n");
2834 *masked |= ATH9K_INT_FATAL;
2836 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
2837 ath_print(common, ATH_DBG_INTERRUPT,
2838 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
2839 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
2840 REG_WRITE(ah, AR_RC, 0);
2841 *masked |= ATH9K_INT_FATAL;
2843 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
2844 ath_print(common, ATH_DBG_INTERRUPT,
2845 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
2848 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
2849 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
2854 EXPORT_SYMBOL(ath9k_hw_getisr);
2856 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
2858 enum ath9k_int omask = ah->imask;
2860 struct ath9k_hw_capabilities *pCap = &ah->caps;
2861 struct ath_common *common = ath9k_hw_common(ah);
2863 ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
2865 if (omask & ATH9K_INT_GLOBAL) {
2866 ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n");
2867 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
2868 (void) REG_READ(ah, AR_IER);
2869 if (!AR_SREV_9100(ah)) {
2870 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
2871 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
2873 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
2874 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
2878 mask = ints & ATH9K_INT_COMMON;
2881 if (ints & ATH9K_INT_TX) {
2882 if (ah->txok_interrupt_mask)
2883 mask |= AR_IMR_TXOK;
2884 if (ah->txdesc_interrupt_mask)
2885 mask |= AR_IMR_TXDESC;
2886 if (ah->txerr_interrupt_mask)
2887 mask |= AR_IMR_TXERR;
2888 if (ah->txeol_interrupt_mask)
2889 mask |= AR_IMR_TXEOL;
2891 if (ints & ATH9K_INT_RX) {
2892 mask |= AR_IMR_RXERR;
2893 if (ah->config.rx_intr_mitigation)
2894 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
2896 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
2897 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
2898 mask |= AR_IMR_GENTMR;
2901 if (ints & (ATH9K_INT_BMISC)) {
2902 mask |= AR_IMR_BCNMISC;
2903 if (ints & ATH9K_INT_TIM)
2904 mask2 |= AR_IMR_S2_TIM;
2905 if (ints & ATH9K_INT_DTIM)
2906 mask2 |= AR_IMR_S2_DTIM;
2907 if (ints & ATH9K_INT_DTIMSYNC)
2908 mask2 |= AR_IMR_S2_DTIMSYNC;
2909 if (ints & ATH9K_INT_CABEND)
2910 mask2 |= AR_IMR_S2_CABEND;
2911 if (ints & ATH9K_INT_TSFOOR)
2912 mask2 |= AR_IMR_S2_TSFOOR;
2915 if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
2916 mask |= AR_IMR_BCNMISC;
2917 if (ints & ATH9K_INT_GTT)
2918 mask2 |= AR_IMR_S2_GTT;
2919 if (ints & ATH9K_INT_CST)
2920 mask2 |= AR_IMR_S2_CST;
2923 ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
2924 REG_WRITE(ah, AR_IMR, mask);
2925 ah->imrs2_reg &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC |
2926 AR_IMR_S2_CABEND | AR_IMR_S2_CABTO |
2927 AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST);
2928 ah->imrs2_reg |= mask2;
2929 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
2931 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2932 if (ints & ATH9K_INT_TIM_TIMER)
2933 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2935 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2938 if (ints & ATH9K_INT_GLOBAL) {
2939 ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n");
2940 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
2941 if (!AR_SREV_9100(ah)) {
2942 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
2944 REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
2947 REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
2948 AR_INTR_SYNC_DEFAULT);
2949 REG_WRITE(ah, AR_INTR_SYNC_MASK,
2950 AR_INTR_SYNC_DEFAULT);
2952 ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
2953 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
2958 EXPORT_SYMBOL(ath9k_hw_set_interrupts);
2960 /*******************/
2961 /* Beacon Handling */
2962 /*******************/
2964 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
2968 ah->beacon_interval = beacon_period;
2970 switch (ah->opmode) {
2971 case NL80211_IFTYPE_STATION:
2972 case NL80211_IFTYPE_MONITOR:
2973 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
2974 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
2975 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
2976 flags |= AR_TBTT_TIMER_EN;
2978 case NL80211_IFTYPE_ADHOC:
2979 case NL80211_IFTYPE_MESH_POINT:
2980 REG_SET_BIT(ah, AR_TXCFG,
2981 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
2982 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
2983 TU_TO_USEC(next_beacon +
2984 (ah->atim_window ? ah->
2986 flags |= AR_NDP_TIMER_EN;
2987 case NL80211_IFTYPE_AP:
2988 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
2989 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
2990 TU_TO_USEC(next_beacon -
2992 dma_beacon_response_time));
2993 REG_WRITE(ah, AR_NEXT_SWBA,
2994 TU_TO_USEC(next_beacon -
2996 sw_beacon_response_time));
2998 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3001 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
3002 "%s: unsupported opmode: %d\n",
3003 __func__, ah->opmode);
3008 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3009 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3010 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3011 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3013 beacon_period &= ~ATH9K_BEACON_ENA;
3014 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
3015 ath9k_hw_reset_tsf(ah);
3018 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3020 EXPORT_SYMBOL(ath9k_hw_beaconinit);
3022 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
3023 const struct ath9k_beacon_state *bs)
3025 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
3026 struct ath9k_hw_capabilities *pCap = &ah->caps;
3027 struct ath_common *common = ath9k_hw_common(ah);
3029 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3031 REG_WRITE(ah, AR_BEACON_PERIOD,
3032 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3033 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3034 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3036 REG_RMW_FIELD(ah, AR_RSSI_THR,
3037 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3039 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3041 if (bs->bs_sleepduration > beaconintval)
3042 beaconintval = bs->bs_sleepduration;
3044 dtimperiod = bs->bs_dtimperiod;
3045 if (bs->bs_sleepduration > dtimperiod)
3046 dtimperiod = bs->bs_sleepduration;
3048 if (beaconintval == dtimperiod)
3049 nextTbtt = bs->bs_nextdtim;
3051 nextTbtt = bs->bs_nexttbtt;
3053 ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3054 ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3055 ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3056 ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3058 REG_WRITE(ah, AR_NEXT_DTIM,
3059 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3060 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
3062 REG_WRITE(ah, AR_SLEEP1,
3063 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3064 | AR_SLEEP1_ASSUME_DTIM);
3066 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3067 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3069 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
3071 REG_WRITE(ah, AR_SLEEP2,
3072 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
3074 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3075 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3077 REG_SET_BIT(ah, AR_TIMER_MODE,
3078 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3081 /* TSF Out of Range Threshold */
3082 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
3084 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
3086 /*******************/
3087 /* HW Capabilities */
3088 /*******************/
3090 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
3092 struct ath9k_hw_capabilities *pCap = &ah->caps;
3093 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3094 struct ath_common *common = ath9k_hw_common(ah);
3095 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
3097 u16 capField = 0, eeval;
3099 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
3100 regulatory->current_rd = eeval;
3102 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
3103 if (AR_SREV_9285_10_OR_LATER(ah))
3104 eeval |= AR9285_RDEXT_DEFAULT;
3105 regulatory->current_rd_ext = eeval;
3107 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
3109 if (ah->opmode != NL80211_IFTYPE_AP &&
3110 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3111 if (regulatory->current_rd == 0x64 ||
3112 regulatory->current_rd == 0x65)
3113 regulatory->current_rd += 5;
3114 else if (regulatory->current_rd == 0x41)
3115 regulatory->current_rd = 0x43;
3116 ath_print(common, ATH_DBG_REGULATORY,
3117 "regdomain mapped to 0x%x\n", regulatory->current_rd);
3120 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
3121 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
3122 ath_print(common, ATH_DBG_FATAL,
3123 "no band has been marked as supported in EEPROM.\n");
3127 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
3129 if (eeval & AR5416_OPFLAGS_11A) {
3130 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3131 if (ah->config.ht_enable) {
3132 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3133 set_bit(ATH9K_MODE_11NA_HT20,
3134 pCap->wireless_modes);
3135 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3136 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3137 pCap->wireless_modes);
3138 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3139 pCap->wireless_modes);
3144 if (eeval & AR5416_OPFLAGS_11G) {
3145 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3146 if (ah->config.ht_enable) {
3147 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3148 set_bit(ATH9K_MODE_11NG_HT20,
3149 pCap->wireless_modes);
3150 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3151 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3152 pCap->wireless_modes);
3153 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3154 pCap->wireless_modes);
3159 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
3161 * For AR9271 we will temporarilly uses the rx chainmax as read from
3164 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
3165 !(eeval & AR5416_OPFLAGS_11A) &&
3166 !(AR_SREV_9271(ah)))
3167 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
3168 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
3170 /* Use rx_chainmask from EEPROM. */
3171 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
3173 if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
3174 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
3176 pCap->low_2ghz_chan = 2312;
3177 pCap->high_2ghz_chan = 2732;
3179 pCap->low_5ghz_chan = 4920;
3180 pCap->high_5ghz_chan = 6100;
3182 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3183 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3184 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3186 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3187 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3188 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3190 if (ah->config.ht_enable)
3191 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3193 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3195 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3196 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3197 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3198 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3200 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3201 pCap->total_queues =
3202 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3204 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3206 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3207 pCap->keycache_size =
3208 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3210 pCap->keycache_size = AR_KEYTABLE_SIZE;
3212 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3214 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
3215 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
3217 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3219 if (AR_SREV_9271(ah))
3220 pCap->num_gpio_pins = AR9271_NUM_GPIO;
3221 else if (AR_SREV_9285_10_OR_LATER(ah))
3222 pCap->num_gpio_pins = AR9285_NUM_GPIO;
3223 else if (AR_SREV_9280_10_OR_LATER(ah))
3224 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3226 pCap->num_gpio_pins = AR_NUM_GPIO;
3228 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3229 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3230 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3232 pCap->rts_aggr_limit = (8 * 1024);
3235 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3237 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3238 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
3239 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
3241 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
3242 ah->rfkill_polarity =
3243 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
3245 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3248 if (AR_SREV_9271(ah))
3249 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
3251 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3253 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
3254 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3256 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3258 if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
3260 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3261 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3262 AR_EEPROM_EEREGCAP_EN_KK_U2 |
3263 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3266 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3267 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3270 /* Advertise midband for AR5416 with FCC midband set in eeprom */
3271 if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
3273 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3275 pCap->num_antcfg_5ghz =
3276 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
3277 pCap->num_antcfg_2ghz =
3278 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
3280 if (AR_SREV_9280_10_OR_LATER(ah) &&
3281 ath9k_hw_btcoex_supported(ah)) {
3282 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
3283 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
3285 if (AR_SREV_9285(ah)) {
3286 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
3287 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
3289 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
3292 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
3298 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3299 u32 capability, u32 *result)
3301 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3303 case ATH9K_CAP_CIPHER:
3304 switch (capability) {
3305 case ATH9K_CIPHER_AES_CCM:
3306 case ATH9K_CIPHER_AES_OCB:
3307 case ATH9K_CIPHER_TKIP:
3308 case ATH9K_CIPHER_WEP:
3309 case ATH9K_CIPHER_MIC:
3310 case ATH9K_CIPHER_CLR:
3315 case ATH9K_CAP_TKIP_MIC:
3316 switch (capability) {
3320 return (ah->sta_id1_defaults &
3321 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3324 case ATH9K_CAP_TKIP_SPLIT:
3325 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
3327 case ATH9K_CAP_DIVERSITY:
3328 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3329 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3331 case ATH9K_CAP_MCAST_KEYSRCH:
3332 switch (capability) {
3336 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3339 return (ah->sta_id1_defaults &
3340 AR_STA_ID1_MCAST_KSRCH) ? true :
3345 case ATH9K_CAP_TXPOW:
3346 switch (capability) {
3350 *result = regulatory->power_limit;
3353 *result = regulatory->max_power_level;
3356 *result = regulatory->tp_scale;
3361 return (AR_SREV_9280_20_OR_LATER(ah) &&
3362 (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
3368 EXPORT_SYMBOL(ath9k_hw_getcapability);
3370 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3371 u32 capability, u32 setting, int *status)
3376 case ATH9K_CAP_TKIP_MIC:
3378 ah->sta_id1_defaults |=
3379 AR_STA_ID1_CRPT_MIC_ENABLE;
3381 ah->sta_id1_defaults &=
3382 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3384 case ATH9K_CAP_DIVERSITY:
3385 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3387 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3389 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3390 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3392 case ATH9K_CAP_MCAST_KEYSRCH:
3394 ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
3396 ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3402 EXPORT_SYMBOL(ath9k_hw_setcapability);
3404 /****************************/
3405 /* GPIO / RFKILL / Antennae */
3406 /****************************/
3408 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
3412 u32 gpio_shift, tmp;
3415 addr = AR_GPIO_OUTPUT_MUX3;
3417 addr = AR_GPIO_OUTPUT_MUX2;
3419 addr = AR_GPIO_OUTPUT_MUX1;
3421 gpio_shift = (gpio % 6) * 5;
3423 if (AR_SREV_9280_20_OR_LATER(ah)
3424 || (addr != AR_GPIO_OUTPUT_MUX1)) {
3425 REG_RMW(ah, addr, (type << gpio_shift),
3426 (0x1f << gpio_shift));
3428 tmp = REG_READ(ah, addr);
3429 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3430 tmp &= ~(0x1f << gpio_shift);
3431 tmp |= (type << gpio_shift);
3432 REG_WRITE(ah, addr, tmp);
3436 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
3440 BUG_ON(gpio >= ah->caps.num_gpio_pins);
3442 gpio_shift = gpio << 1;
3446 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3447 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3449 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
3451 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
3453 #define MS_REG_READ(x, y) \
3454 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3456 if (gpio >= ah->caps.num_gpio_pins)
3459 if (AR_SREV_9271(ah))
3460 return MS_REG_READ(AR9271, gpio) != 0;
3461 else if (AR_SREV_9287_10_OR_LATER(ah))
3462 return MS_REG_READ(AR9287, gpio) != 0;
3463 else if (AR_SREV_9285_10_OR_LATER(ah))
3464 return MS_REG_READ(AR9285, gpio) != 0;
3465 else if (AR_SREV_9280_10_OR_LATER(ah))
3466 return MS_REG_READ(AR928X, gpio) != 0;
3468 return MS_REG_READ(AR, gpio) != 0;
3470 EXPORT_SYMBOL(ath9k_hw_gpio_get);
3472 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
3477 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3479 gpio_shift = 2 * gpio;
3483 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3484 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3486 EXPORT_SYMBOL(ath9k_hw_cfg_output);
3488 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
3490 if (AR_SREV_9271(ah))
3493 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3496 EXPORT_SYMBOL(ath9k_hw_set_gpio);
3498 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
3500 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3502 EXPORT_SYMBOL(ath9k_hw_getdefantenna);
3504 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
3506 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3508 EXPORT_SYMBOL(ath9k_hw_setantenna);
3510 /*********************/
3511 /* General Operation */
3512 /*********************/
3514 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
3516 u32 bits = REG_READ(ah, AR_RX_FILTER);
3517 u32 phybits = REG_READ(ah, AR_PHY_ERR);
3519 if (phybits & AR_PHY_ERR_RADAR)
3520 bits |= ATH9K_RX_FILTER_PHYRADAR;
3521 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3522 bits |= ATH9K_RX_FILTER_PHYERR;
3526 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
3528 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
3532 REG_WRITE(ah, AR_RX_FILTER, bits);
3535 if (bits & ATH9K_RX_FILTER_PHYRADAR)
3536 phybits |= AR_PHY_ERR_RADAR;
3537 if (bits & ATH9K_RX_FILTER_PHYERR)
3538 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3539 REG_WRITE(ah, AR_PHY_ERR, phybits);
3542 REG_WRITE(ah, AR_RXCFG,
3543 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3545 REG_WRITE(ah, AR_RXCFG,
3546 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3548 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
3550 bool ath9k_hw_phy_disable(struct ath_hw *ah)
3552 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
3555 ath9k_hw_init_pll(ah, NULL);
3558 EXPORT_SYMBOL(ath9k_hw_phy_disable);
3560 bool ath9k_hw_disable(struct ath_hw *ah)
3562 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3565 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
3568 ath9k_hw_init_pll(ah, NULL);
3571 EXPORT_SYMBOL(ath9k_hw_disable);
3573 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
3575 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3576 struct ath9k_channel *chan = ah->curchan;
3577 struct ieee80211_channel *channel = chan->chan;
3579 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
3581 ah->eep_ops->set_txpower(ah, chan,
3582 ath9k_regd_get_ctl(regulatory, chan),
3583 channel->max_antenna_gain * 2,
3584 channel->max_power * 2,
3585 min((u32) MAX_RATE_POWER,
3586 (u32) regulatory->power_limit));
3588 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
3590 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
3592 memcpy(ath9k_hw_common(ah)->macaddr, mac, ETH_ALEN);
3594 EXPORT_SYMBOL(ath9k_hw_setmac);
3596 void ath9k_hw_setopmode(struct ath_hw *ah)
3598 ath9k_hw_set_operating_mode(ah, ah->opmode);
3600 EXPORT_SYMBOL(ath9k_hw_setopmode);
3602 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
3604 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3605 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
3607 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
3609 void ath9k_hw_write_associd(struct ath_hw *ah)
3611 struct ath_common *common = ath9k_hw_common(ah);
3613 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
3614 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
3615 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
3617 EXPORT_SYMBOL(ath9k_hw_write_associd);
3619 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
3623 tsf = REG_READ(ah, AR_TSF_U32);
3624 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
3628 EXPORT_SYMBOL(ath9k_hw_gettsf64);
3630 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
3632 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
3633 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
3635 EXPORT_SYMBOL(ath9k_hw_settsf64);
3637 void ath9k_hw_reset_tsf(struct ath_hw *ah)
3639 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
3640 AH_TSF_WRITE_TIMEOUT))
3641 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
3642 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
3644 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3646 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
3648 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
3651 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
3653 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
3655 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
3658 * Extend 15-bit time stamp from rx descriptor to
3659 * a full 64-bit TSF using the current h/w TSF.
3661 u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp)
3665 tsf = ath9k_hw_gettsf64(ah);
3666 if ((tsf & 0x7fff) < rstamp)
3668 return (tsf & ~0x7fff) | rstamp;
3670 EXPORT_SYMBOL(ath9k_hw_extend_tsf);
3672 void ath9k_hw_set11nmac2040(struct ath_hw *ah)
3674 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
3677 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
3678 macmode = AR_2040_JOINED_RX_CLEAR;
3682 REG_WRITE(ah, AR_2040_MODE, macmode);
3685 /* HW Generic timers configuration */
3687 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
3689 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3690 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3691 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3692 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3693 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3694 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3695 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3696 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3697 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
3698 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
3699 AR_NDP2_TIMER_MODE, 0x0002},
3700 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
3701 AR_NDP2_TIMER_MODE, 0x0004},
3702 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
3703 AR_NDP2_TIMER_MODE, 0x0008},
3704 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
3705 AR_NDP2_TIMER_MODE, 0x0010},
3706 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
3707 AR_NDP2_TIMER_MODE, 0x0020},
3708 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
3709 AR_NDP2_TIMER_MODE, 0x0040},
3710 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
3711 AR_NDP2_TIMER_MODE, 0x0080}
3714 /* HW generic timer primitives */
3716 /* compute and clear index of rightmost 1 */
3717 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
3727 return timer_table->gen_timer_index[b];
3730 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
3732 return REG_READ(ah, AR_TSF_L32);
3734 EXPORT_SYMBOL(ath9k_hw_gettsf32);
3736 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
3737 void (*trigger)(void *),
3738 void (*overflow)(void *),
3742 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3743 struct ath_gen_timer *timer;
3745 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
3747 if (timer == NULL) {
3748 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
3749 "Failed to allocate memory"
3750 "for hw timer[%d]\n", timer_index);
3754 /* allocate a hardware generic timer slot */
3755 timer_table->timers[timer_index] = timer;
3756 timer->index = timer_index;
3757 timer->trigger = trigger;
3758 timer->overflow = overflow;
3763 EXPORT_SYMBOL(ath_gen_timer_alloc);
3765 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
3766 struct ath_gen_timer *timer,
3770 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3773 BUG_ON(!timer_period);
3775 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
3777 tsf = ath9k_hw_gettsf32(ah);
3779 ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
3780 "curent tsf %x period %x"
3781 "timer_next %x\n", tsf, timer_period, timer_next);
3784 * Pull timer_next forward if the current TSF already passed it
3785 * because of software latency
3787 if (timer_next < tsf)
3788 timer_next = tsf + timer_period;
3791 * Program generic timer registers
3793 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
3795 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
3797 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3798 gen_tmr_configuration[timer->index].mode_mask);
3800 /* Enable both trigger and thresh interrupt masks */
3801 REG_SET_BIT(ah, AR_IMR_S5,
3802 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3803 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3805 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
3807 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
3809 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3811 if ((timer->index < AR_FIRST_NDP_TIMER) ||
3812 (timer->index >= ATH_MAX_GEN_TIMER)) {
3816 /* Clear generic timer enable bits. */
3817 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3818 gen_tmr_configuration[timer->index].mode_mask);
3820 /* Disable both trigger and thresh interrupt masks */
3821 REG_CLR_BIT(ah, AR_IMR_S5,
3822 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3823 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3825 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
3827 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
3829 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
3831 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3833 /* free the hardware generic timer slot */
3834 timer_table->timers[timer->index] = NULL;
3837 EXPORT_SYMBOL(ath_gen_timer_free);
3840 * Generic Timer Interrupts handling
3842 void ath_gen_timer_isr(struct ath_hw *ah)
3844 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3845 struct ath_gen_timer *timer;
3846 struct ath_common *common = ath9k_hw_common(ah);
3847 u32 trigger_mask, thresh_mask, index;
3849 /* get hardware generic timer interrupt status */
3850 trigger_mask = ah->intr_gen_timer_trigger;
3851 thresh_mask = ah->intr_gen_timer_thresh;
3852 trigger_mask &= timer_table->timer_mask.val;
3853 thresh_mask &= timer_table->timer_mask.val;
3855 trigger_mask &= ~thresh_mask;
3857 while (thresh_mask) {
3858 index = rightmost_index(timer_table, &thresh_mask);
3859 timer = timer_table->timers[index];
3861 ath_print(common, ATH_DBG_HWTIMER,
3862 "TSF overflow for Gen timer %d\n", index);
3863 timer->overflow(timer->arg);
3866 while (trigger_mask) {
3867 index = rightmost_index(timer_table, &trigger_mask);
3868 timer = timer_table->timers[index];
3870 ath_print(common, ATH_DBG_HWTIMER,
3871 "Gen timer[%d] trigger\n", index);
3872 timer->trigger(timer->arg);
3875 EXPORT_SYMBOL(ath_gen_timer_isr);
3881 void ath9k_hw_htc_resetinit(struct ath_hw *ah)
3883 ah->htc_reset_init = true;
3885 EXPORT_SYMBOL(ath9k_hw_htc_resetinit);
3890 } ath_mac_bb_names[] = {
3891 /* Devices with external radios */
3892 { AR_SREV_VERSION_5416_PCI, "5416" },
3893 { AR_SREV_VERSION_5416_PCIE, "5418" },
3894 { AR_SREV_VERSION_9100, "9100" },
3895 { AR_SREV_VERSION_9160, "9160" },
3896 /* Single-chip solutions */
3897 { AR_SREV_VERSION_9280, "9280" },
3898 { AR_SREV_VERSION_9285, "9285" },
3899 { AR_SREV_VERSION_9287, "9287" },
3900 { AR_SREV_VERSION_9271, "9271" },
3903 /* For devices with external radios */
3907 } ath_rf_names[] = {
3909 { AR_RAD5133_SREV_MAJOR, "5133" },
3910 { AR_RAD5122_SREV_MAJOR, "5122" },
3911 { AR_RAD2133_SREV_MAJOR, "2133" },
3912 { AR_RAD2122_SREV_MAJOR, "2122" }
3916 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3918 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
3922 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3923 if (ath_mac_bb_names[i].version == mac_bb_version) {
3924 return ath_mac_bb_names[i].name;
3932 * Return the RF name. "????" is returned if the RF is unknown.
3933 * Used for devices with external radios.
3935 static const char *ath9k_hw_rf_name(u16 rf_version)
3939 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3940 if (ath_rf_names[i].version == rf_version) {
3941 return ath_rf_names[i].name;
3948 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3952 /* chipsets >= AR9280 are single-chip */
3953 if (AR_SREV_9280_10_OR_LATER(ah)) {
3954 used = snprintf(hw_name, len,
3955 "Atheros AR%s Rev:%x",
3956 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3957 ah->hw_version.macRev);
3960 used = snprintf(hw_name, len,
3961 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3962 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3963 ah->hw_version.macRev,
3964 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
3965 AR_RADIO_SREV_MAJOR)),
3966 ah->hw_version.phyRev);
3969 hw_name[used] = '\0';
3971 EXPORT_SYMBOL(ath9k_hw_name);