drivers/net/wireless/ath/ath9k/hw.c

   1 /*
   2  * Copyright (c) 2008-2009 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/io.h>
  18 #include <asm/unaligned.h>
  19
  20 #include "hw.h"
  21 #include "hw-ops.h"
  22 #include "rc.h"
  23 #include "initvals.h"
  24
  25 #define ATH9K_CLOCK_RATE_CCK            22
  26 #define ATH9K_CLOCK_RATE_5GHZ_OFDM      40
  27 #define ATH9K_CLOCK_RATE_2GHZ_OFDM      44
  28
  29 static void ar9002_hw_attach_ops(struct ath_hw *ah);
  30
  31 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
  32 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan);
  33
  34 MODULE_AUTHOR("Atheros Communications");
  35 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
  36 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
  37 MODULE_LICENSE("Dual BSD/GPL");
  38
  39 static int __init ath9k_init(void)
  40 {
  41         return 0;
  42 }
  43 module_init(ath9k_init);
  44
  45 static void __exit ath9k_exit(void)
  46 {
  47         return;
  48 }
  49 module_exit(ath9k_exit);
  50
  51 /* Private hardware callbacks */
  52
  53 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
  54 {
  55         ath9k_hw_private_ops(ah)->init_cal_settings(ah);
  56 }
  57
  58 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
  59 {
  60         ath9k_hw_private_ops(ah)->init_mode_regs(ah);
  61 }
  62
  63 static bool ath9k_hw_macversion_supported(struct ath_hw *ah)
  64 {
  65         struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
  66
  67         return priv_ops->macversion_supported(ah->hw_version.macVersion);
  68 }
  69
  70 /********************/
  71 /* Helper Functions */
  72 /********************/
  73
  74 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
  75 {
  76         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
  77
  78         if (!ah->curchan) /* should really check for CCK instead */
  79                 return usecs *ATH9K_CLOCK_RATE_CCK;
  80         if (conf->channel->band == IEEE80211_BAND_2GHZ)
  81                 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
  82         return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
  83 }
  84
  85 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
  86 {
  87         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
  88
  89         if (conf_is_ht40(conf))
  90                 return ath9k_hw_mac_clks(ah, usecs) * 2;
  91         else
  92                 return ath9k_hw_mac_clks(ah, usecs);
  93 }
  94
  95 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
  96 {
  97         int i;
  98
  99         BUG_ON(timeout < AH_TIME_QUANTUM);
 100
 101         for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
 102                 if ((REG_READ(ah, reg) & mask) == val)
 103                         return true;
 104
 105                 udelay(AH_TIME_QUANTUM);
 106         }
 107
 108         ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
 109                   "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
 110                   timeout, reg, REG_READ(ah, reg), mask, val);
 111
 112         return false;
 113 }
 114 EXPORT_SYMBOL(ath9k_hw_wait);
 115
 116 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
 117 {
 118         u32 retval;
 119         int i;
 120
 121         for (i = 0, retval = 0; i < n; i++) {
 122                 retval = (retval << 1) | (val & 1);
 123                 val >>= 1;
 124         }
 125         return retval;
 126 }
 127
 128 bool ath9k_get_channel_edges(struct ath_hw *ah,
 129                              u16 flags, u16 *low,
 130                              u16 *high)
 131 {
 132         struct ath9k_hw_capabilities *pCap = &ah->caps;
 133
 134         if (flags & CHANNEL_5GHZ) {
 135                 *low = pCap->low_5ghz_chan;
 136                 *high = pCap->high_5ghz_chan;
 137                 return true;
 138         }
 139         if ((flags & CHANNEL_2GHZ)) {
 140                 *low = pCap->low_2ghz_chan;
 141                 *high = pCap->high_2ghz_chan;
 142                 return true;
 143         }
 144         return false;
 145 }
 146
 147 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
 148                            u8 phy, int kbps,
 149                            u32 frameLen, u16 rateix,
 150                            bool shortPreamble)
 151 {
 152         u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
 153
 154         if (kbps == 0)
 155                 return 0;
 156
 157         switch (phy) {
 158         case WLAN_RC_PHY_CCK:
 159                 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
 160                 if (shortPreamble)
 161                         phyTime >>= 1;
 162                 numBits = frameLen << 3;
 163                 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
 164                 break;
 165         case WLAN_RC_PHY_OFDM:
 166                 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
 167                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
 168                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 169                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 170                         txTime = OFDM_SIFS_TIME_QUARTER
 171                                 + OFDM_PREAMBLE_TIME_QUARTER
 172                                 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
 173                 } else if (ah->curchan &&
 174                            IS_CHAN_HALF_RATE(ah->curchan)) {
 175                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
 176                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 177                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 178                         txTime = OFDM_SIFS_TIME_HALF +
 179                                 OFDM_PREAMBLE_TIME_HALF
 180                                 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
 181                 } else {
 182                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
 183                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 184                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 185                         txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
 186                                 + (numSymbols * OFDM_SYMBOL_TIME);
 187                 }
 188                 break;
 189         default:
 190                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
 191                           "Unknown phy %u (rate ix %u)\n", phy, rateix);
 192                 txTime = 0;
 193                 break;
 194         }
 195
 196         return txTime;
 197 }
 198 EXPORT_SYMBOL(ath9k_hw_computetxtime);
 199
 200 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
 201                                   struct ath9k_channel *chan,
 202                                   struct chan_centers *centers)
 203 {
 204         int8_t extoff;
 205
 206         if (!IS_CHAN_HT40(chan)) {
 207                 centers->ctl_center = centers->ext_center =
 208                         centers->synth_center = chan->channel;
 209                 return;
 210         }
 211
 212         if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
 213             (chan->chanmode == CHANNEL_G_HT40PLUS)) {
 214                 centers->synth_center =
 215                         chan->channel + HT40_CHANNEL_CENTER_SHIFT;
 216                 extoff = 1;
 217         } else {
 218                 centers->synth_center =
 219                         chan->channel - HT40_CHANNEL_CENTER_SHIFT;
 220                 extoff = -1;
 221         }
 222
 223         centers->ctl_center =
 224                 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
 225         /* 25 MHz spacing is supported by hw but not on upper layers */
 226         centers->ext_center =
 227                 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
 228 }
 229
 230 /******************/
 231 /* Chip Revisions */
 232 /******************/
 233
 234 static void ath9k_hw_read_revisions(struct ath_hw *ah)
 235 {
 236         u32 val;
 237
 238         val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
 239
 240         if (val == 0xFF) {
 241                 val = REG_READ(ah, AR_SREV);
 242                 ah->hw_version.macVersion =
 243                         (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
 244                 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
 245                 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
 246         } else {
 247                 if (!AR_SREV_9100(ah))
 248                         ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
 249
 250                 ah->hw_version.macRev = val & AR_SREV_REVISION;
 251
 252                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
 253                         ah->is_pciexpress = true;
 254         }
 255 }
 256
 257 static int ath9k_hw_get_radiorev(struct ath_hw *ah)
 258 {
 259         u32 val;
 260         int i;
 261
 262         REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
 263
 264         for (i = 0; i < 8; i++)
 265                 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
 266         val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
 267         val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
 268
 269         return ath9k_hw_reverse_bits(val, 8);
 270 }
 271
 272 /************************************/
 273 /* HW Attach, Detach, Init Routines */
 274 /************************************/
 275
 276 static void ath9k_hw_disablepcie(struct ath_hw *ah)
 277 {
 278         if (AR_SREV_9100(ah))
 279                 return;
 280
 281         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
 282         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
 283         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
 284         REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
 285         REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
 286         REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
 287         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
 288         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
 289         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
 290
 291         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
 292 }
 293
 294 static bool ath9k_hw_chip_test(struct ath_hw *ah)
 295 {
 296         struct ath_common *common = ath9k_hw_common(ah);
 297         u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
 298         u32 regHold[2];
 299         u32 patternData[4] = { 0x55555555,
 300                                0xaaaaaaaa,
 301                                0x66666666,
 302                                0x99999999 };
 303         int i, j;
 304
 305         for (i = 0; i < 2; i++) {
 306                 u32 addr = regAddr[i];
 307                 u32 wrData, rdData;
 308
 309                 regHold[i] = REG_READ(ah, addr);
 310                 for (j = 0; j < 0x100; j++) {
 311                         wrData = (j << 16) | j;
 312                         REG_WRITE(ah, addr, wrData);
 313                         rdData = REG_READ(ah, addr);
 314                         if (rdData != wrData) {
 315                                 ath_print(common, ATH_DBG_FATAL,
 316                                           "address test failed "
 317                                           "addr: 0x%08x - wr:0x%08x != "
 318                                           "rd:0x%08x\n",
 319                                           addr, wrData, rdData);
 320                                 return false;
 321                         }
 322                 }
 323                 for (j = 0; j < 4; j++) {
 324                         wrData = patternData[j];
 325                         REG_WRITE(ah, addr, wrData);
 326                         rdData = REG_READ(ah, addr);
 327                         if (wrData != rdData) {
 328                                 ath_print(common, ATH_DBG_FATAL,
 329                                           "address test failed "
 330                                           "addr: 0x%08x - wr:0x%08x != "
 331                                           "rd:0x%08x\n",
 332                                           addr, wrData, rdData);
 333                                 return false;
 334                         }
 335                 }
 336                 REG_WRITE(ah, regAddr[i], regHold[i]);
 337         }
 338         udelay(100);
 339
 340         return true;
 341 }
 342
 343 static void ath9k_hw_init_config(struct ath_hw *ah)
 344 {
 345         int i;
 346
 347         ah->config.dma_beacon_response_time = 2;
 348         ah->config.sw_beacon_response_time = 10;
 349         ah->config.additional_swba_backoff = 0;
 350         ah->config.ack_6mb = 0x0;
 351         ah->config.cwm_ignore_extcca = 0;
 352         ah->config.pcie_powersave_enable = 0;
 353         ah->config.pcie_clock_req = 0;
 354         ah->config.pcie_waen = 0;
 355         ah->config.analog_shiftreg = 1;
 356         ah->config.ofdm_trig_low = 200;
 357         ah->config.ofdm_trig_high = 500;
 358         ah->config.cck_trig_high = 200;
 359         ah->config.cck_trig_low = 100;
 360         ah->config.enable_ani = 1;
 361
 362         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
 363                 ah->config.spurchans[i][0] = AR_NO_SPUR;
 364                 ah->config.spurchans[i][1] = AR_NO_SPUR;
 365         }
 366
 367         if (ah->hw_version.devid != AR2427_DEVID_PCIE)
 368                 ah->config.ht_enable = 1;
 369         else
 370                 ah->config.ht_enable = 0;
 371
 372         ah->config.rx_intr_mitigation = true;
 373
 374         /*
 375          * We need this for PCI devices only (Cardbus, PCI, miniPCI)
 376          * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
 377          * This means we use it for all AR5416 devices, and the few
 378          * minor PCI AR9280 devices out there.
 379          *
 380          * Serialization is required because these devices do not handle
 381          * well the case of two concurrent reads/writes due to the latency
 382          * involved. During one read/write another read/write can be issued
 383          * on another CPU while the previous read/write may still be working
 384          * on our hardware, if we hit this case the hardware poops in a loop.
 385          * We prevent this by serializing reads and writes.
 386          *
 387          * This issue is not present on PCI-Express devices or pre-AR5416
 388          * devices (legacy, 802.11abg).
 389          */
 390         if (num_possible_cpus() > 1)
 391                 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
 392 }
 393
 394 static void ath9k_hw_init_defaults(struct ath_hw *ah)
 395 {
 396         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
 397
 398         regulatory->country_code = CTRY_DEFAULT;
 399         regulatory->power_limit = MAX_RATE_POWER;
 400         regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
 401
 402         ah->hw_version.magic = AR5416_MAGIC;
 403         ah->hw_version.subvendorid = 0;
 404
 405         ah->ah_flags = 0;
 406         if (ah->hw_version.devid == AR5416_AR9100_DEVID)
 407                 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
 408         if (!AR_SREV_9100(ah))
 409                 ah->ah_flags = AH_USE_EEPROM;
 410
 411         ah->atim_window = 0;
 412         ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
 413         ah->beacon_interval = 100;
 414         ah->enable_32kHz_clock = DONT_USE_32KHZ;
 415         ah->slottime = (u32) -1;
 416         ah->globaltxtimeout = (u32) -1;
 417         ah->power_mode = ATH9K_PM_UNDEFINED;
 418 }
 419
 420 static int ath9k_hw_rf_claim(struct ath_hw *ah)
 421 {
 422         u32 val;
 423
 424         REG_WRITE(ah, AR_PHY(0), 0x00000007);
 425
 426         val = ath9k_hw_get_radiorev(ah);
 427         switch (val & AR_RADIO_SREV_MAJOR) {
 428         case 0:
 429                 val = AR_RAD5133_SREV_MAJOR;
 430                 break;
 431         case AR_RAD5133_SREV_MAJOR:
 432         case AR_RAD5122_SREV_MAJOR:
 433         case AR_RAD2133_SREV_MAJOR:
 434         case AR_RAD2122_SREV_MAJOR:
 435                 break;
 436         default:
 437                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
 438                           "Radio Chip Rev 0x%02X not supported\n",
 439                           val & AR_RADIO_SREV_MAJOR);
 440                 return -EOPNOTSUPP;
 441         }
 442
 443         ah->hw_version.analog5GhzRev = val;
 444
 445         return 0;
 446 }
 447
 448 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
 449 {
 450         struct ath_common *common = ath9k_hw_common(ah);
 451         u32 sum;
 452         int i;
 453         u16 eeval;
 454
 455         sum = 0;
 456         for (i = 0; i < 3; i++) {
 457                 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
 458                 sum += eeval;
 459                 common->macaddr[2 * i] = eeval >> 8;
 460                 common->macaddr[2 * i + 1] = eeval & 0xff;
 461         }
 462         if (sum == 0 || sum == 0xffff * 3)
 463                 return -EADDRNOTAVAIL;
 464
 465         return 0;
 466 }
 467
 468 static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
 469 {
 470         u32 rxgain_type;
 471
 472         if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
 473                 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
 474
 475                 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
 476                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 477                         ar9280Modes_backoff_13db_rxgain_9280_2,
 478                         ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
 479                 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
 480                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 481                         ar9280Modes_backoff_23db_rxgain_9280_2,
 482                         ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
 483                 else
 484                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 485                         ar9280Modes_original_rxgain_9280_2,
 486                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 487         } else {
 488                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 489                         ar9280Modes_original_rxgain_9280_2,
 490                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 491         }
 492 }
 493
 494 static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
 495 {
 496         u32 txgain_type;
 497
 498         if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
 499                 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
 500
 501                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
 502                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 503                         ar9280Modes_high_power_tx_gain_9280_2,
 504                         ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
 505                 else
 506                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 507                         ar9280Modes_original_tx_gain_9280_2,
 508                         ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 509         } else {
 510                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 511                 ar9280Modes_original_tx_gain_9280_2,
 512                 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 513         }
 514 }
 515
 516 static int ath9k_hw_post_init(struct ath_hw *ah)
 517 {
 518         int ecode;
 519
 520         if (!AR_SREV_9271(ah)) {
 521                 if (!ath9k_hw_chip_test(ah))
 522                         return -ENODEV;
 523         }
 524
 525         ecode = ath9k_hw_rf_claim(ah);
 526         if (ecode != 0)
 527                 return ecode;
 528
 529         ecode = ath9k_hw_eeprom_init(ah);
 530         if (ecode != 0)
 531                 return ecode;
 532
 533         ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
 534                   "Eeprom VER: %d, REV: %d\n",
 535                   ah->eep_ops->get_eeprom_ver(ah),
 536                   ah->eep_ops->get_eeprom_rev(ah));
 537
 538         if (!AR_SREV_9280_10_OR_LATER(ah)) {
 539                 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
 540                 if (ecode) {
 541                         ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
 542                                   "Failed allocating banks for "
 543                                   "external radio\n");
 544                         return ecode;
 545                 }
 546         }
 547
 548         if (!AR_SREV_9100(ah)) {
 549                 ath9k_hw_ani_setup(ah);
 550                 ath9k_hw_ani_init(ah);
 551         }
 552
 553         return 0;
 554 }
 555
 556 static bool ar9002_hw_macversion_supported(u32 macversion)
 557 {
 558         switch (macversion) {
 559         case AR_SREV_VERSION_5416_PCI:
 560         case AR_SREV_VERSION_5416_PCIE:
 561         case AR_SREV_VERSION_9160:
 562         case AR_SREV_VERSION_9100:
 563         case AR_SREV_VERSION_9280:
 564         case AR_SREV_VERSION_9285:
 565         case AR_SREV_VERSION_9287:
 566         case AR_SREV_VERSION_9271:
 567                 return true;
 568         default:
 569                 break;
 570         }
 571         return false;
 572 }
 573
 574 static void ar9002_hw_init_cal_settings(struct ath_hw *ah)
 575 {
 576         if (AR_SREV_9160_10_OR_LATER(ah)) {
 577                 if (AR_SREV_9280_10_OR_LATER(ah)) {
 578                         ah->iq_caldata.calData = &iq_cal_single_sample;
 579                         ah->adcgain_caldata.calData =
 580                                 &adc_gain_cal_single_sample;
 581                         ah->adcdc_caldata.calData =
 582                                 &adc_dc_cal_single_sample;
 583                         ah->adcdc_calinitdata.calData =
 584                                 &adc_init_dc_cal;
 585                 } else {
 586                         ah->iq_caldata.calData = &iq_cal_multi_sample;
 587                         ah->adcgain_caldata.calData =
 588                                 &adc_gain_cal_multi_sample;
 589                         ah->adcdc_caldata.calData =
 590                                 &adc_dc_cal_multi_sample;
 591                         ah->adcdc_calinitdata.calData =
 592                                 &adc_init_dc_cal;
 593                 }
 594                 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
 595         }
 596 }
 597
 598 static void ar9002_hw_init_mode_regs(struct ath_hw *ah)
 599 {
 600         if (AR_SREV_9271(ah)) {
 601                 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271,
 602                                ARRAY_SIZE(ar9271Modes_9271), 6);
 603                 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271,
 604                                ARRAY_SIZE(ar9271Common_9271), 2);
 605                 INIT_INI_ARRAY(&ah->iniCommon_normal_cck_fir_coeff_9271,
 606                                ar9271Common_normal_cck_fir_coeff_9271,
 607                                ARRAY_SIZE(ar9271Common_normal_cck_fir_coeff_9271), 2);
 608                 INIT_INI_ARRAY(&ah->iniCommon_japan_2484_cck_fir_coeff_9271,
 609                                ar9271Common_japan_2484_cck_fir_coeff_9271,
 610                                ARRAY_SIZE(ar9271Common_japan_2484_cck_fir_coeff_9271), 2);
 611                 INIT_INI_ARRAY(&ah->iniModes_9271_1_0_only,
 612                                ar9271Modes_9271_1_0_only,
 613                                ARRAY_SIZE(ar9271Modes_9271_1_0_only), 6);
 614                 INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg,
 615                                ARRAY_SIZE(ar9271Modes_9271_ANI_reg), 6);
 616                 INIT_INI_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
 617                                ar9271Modes_high_power_tx_gain_9271,
 618                                ARRAY_SIZE(ar9271Modes_high_power_tx_gain_9271), 6);
 619                 INIT_INI_ARRAY(&ah->iniModes_normal_power_tx_gain_9271,
 620                                ar9271Modes_normal_power_tx_gain_9271,
 621                                ARRAY_SIZE(ar9271Modes_normal_power_tx_gain_9271), 6);
 622                 return;
 623         }
 624
 625         if (AR_SREV_9287_11_OR_LATER(ah)) {
 626                 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
 627                                 ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
 628                 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
 629                                 ARRAY_SIZE(ar9287Common_9287_1_1), 2);
 630                 if (ah->config.pcie_clock_req)
 631                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 632                         ar9287PciePhy_clkreq_off_L1_9287_1_1,
 633                         ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
 634                 else
 635                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 636                         ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
 637                         ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
 638                                         2);
 639         } else if (AR_SREV_9287_10_OR_LATER(ah)) {
 640                 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0,
 641                                 ARRAY_SIZE(ar9287Modes_9287_1_0), 6);
 642                 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0,
 643                                 ARRAY_SIZE(ar9287Common_9287_1_0), 2);
 644
 645                 if (ah->config.pcie_clock_req)
 646                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 647                         ar9287PciePhy_clkreq_off_L1_9287_1_0,
 648                         ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2);
 649                 else
 650                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 651                         ar9287PciePhy_clkreq_always_on_L1_9287_1_0,
 652                         ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0),
 653                                   2);
 654         } else if (AR_SREV_9285_12_OR_LATER(ah)) {
 655
 656
 657                 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
 658                                ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
 659                 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
 660                                ARRAY_SIZE(ar9285Common_9285_1_2), 2);
 661
 662                 if (ah->config.pcie_clock_req) {
 663                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 664                         ar9285PciePhy_clkreq_off_L1_9285_1_2,
 665                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
 666                 } else {
 667                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 668                         ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
 669                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
 670                                   2);
 671                 }
 672         } else if (AR_SREV_9285_10_OR_LATER(ah)) {
 673                 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
 674                                ARRAY_SIZE(ar9285Modes_9285), 6);
 675                 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
 676                                ARRAY_SIZE(ar9285Common_9285), 2);
 677
 678                 if (ah->config.pcie_clock_req) {
 679                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 680                         ar9285PciePhy_clkreq_off_L1_9285,
 681                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
 682                 } else {
 683                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 684                         ar9285PciePhy_clkreq_always_on_L1_9285,
 685                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
 686                 }
 687         } else if (AR_SREV_9280_20_OR_LATER(ah)) {
 688                 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
 689                                ARRAY_SIZE(ar9280Modes_9280_2), 6);
 690                 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
 691                                ARRAY_SIZE(ar9280Common_9280_2), 2);
 692
 693                 if (ah->config.pcie_clock_req) {
 694                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 695                                ar9280PciePhy_clkreq_off_L1_9280,
 696                                ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
 697                 } else {
 698                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 699                                ar9280PciePhy_clkreq_always_on_L1_9280,
 700                                ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
 701                 }
 702                 INIT_INI_ARRAY(&ah->iniModesAdditional,
 703                                ar9280Modes_fast_clock_9280_2,
 704                                ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
 705         } else if (AR_SREV_9280_10_OR_LATER(ah)) {
 706                 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
 707                                ARRAY_SIZE(ar9280Modes_9280), 6);
 708                 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
 709                                ARRAY_SIZE(ar9280Common_9280), 2);
 710         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
 711                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
 712                                ARRAY_SIZE(ar5416Modes_9160), 6);
 713                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
 714                                ARRAY_SIZE(ar5416Common_9160), 2);
 715                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
 716                                ARRAY_SIZE(ar5416Bank0_9160), 2);
 717                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
 718                                ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
 719                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
 720                                ARRAY_SIZE(ar5416Bank1_9160), 2);
 721                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
 722                                ARRAY_SIZE(ar5416Bank2_9160), 2);
 723                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
 724                                ARRAY_SIZE(ar5416Bank3_9160), 3);
 725                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
 726                                ARRAY_SIZE(ar5416Bank6_9160), 3);
 727                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
 728                                ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
 729                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
 730                                ARRAY_SIZE(ar5416Bank7_9160), 2);
 731                 if (AR_SREV_9160_11(ah)) {
 732                         INIT_INI_ARRAY(&ah->iniAddac,
 733                                        ar5416Addac_91601_1,
 734                                        ARRAY_SIZE(ar5416Addac_91601_1), 2);
 735                 } else {
 736                         INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
 737                                        ARRAY_SIZE(ar5416Addac_9160), 2);
 738                 }
 739         } else if (AR_SREV_9100_OR_LATER(ah)) {
 740                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
 741                                ARRAY_SIZE(ar5416Modes_9100), 6);
 742                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
 743                                ARRAY_SIZE(ar5416Common_9100), 2);
 744                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
 745                                ARRAY_SIZE(ar5416Bank0_9100), 2);
 746                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
 747                                ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
 748                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
 749                                ARRAY_SIZE(ar5416Bank1_9100), 2);
 750                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
 751                                ARRAY_SIZE(ar5416Bank2_9100), 2);
 752                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
 753                                ARRAY_SIZE(ar5416Bank3_9100), 3);
 754                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
 755                                ARRAY_SIZE(ar5416Bank6_9100), 3);
 756                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
 757                                ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
 758                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
 759                                ARRAY_SIZE(ar5416Bank7_9100), 2);
 760                 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
 761                                ARRAY_SIZE(ar5416Addac_9100), 2);
 762         } else {
 763                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
 764                                ARRAY_SIZE(ar5416Modes), 6);
 765                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
 766                                ARRAY_SIZE(ar5416Common), 2);
 767                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
 768                                ARRAY_SIZE(ar5416Bank0), 2);
 769                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
 770                                ARRAY_SIZE(ar5416BB_RfGain), 3);
 771                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
 772                                ARRAY_SIZE(ar5416Bank1), 2);
 773                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
 774                                ARRAY_SIZE(ar5416Bank2), 2);
 775                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
 776                                ARRAY_SIZE(ar5416Bank3), 3);
 777                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
 778                                ARRAY_SIZE(ar5416Bank6), 3);
 779                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
 780                                ARRAY_SIZE(ar5416Bank6TPC), 3);
 781                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
 782                                ARRAY_SIZE(ar5416Bank7), 2);
 783                 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
 784                                ARRAY_SIZE(ar5416Addac), 2);
 785         }
 786 }
 787
 788 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
 789 {
 790         if (AR_SREV_9287_11_OR_LATER(ah))
 791                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 792                 ar9287Modes_rx_gain_9287_1_1,
 793                 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
 794         else if (AR_SREV_9287_10(ah))
 795                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 796                 ar9287Modes_rx_gain_9287_1_0,
 797                 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);
 798         else if (AR_SREV_9280_20(ah))
 799                 ath9k_hw_init_rxgain_ini(ah);
 800
 801         if (AR_SREV_9287_11_OR_LATER(ah)) {
 802                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 803                 ar9287Modes_tx_gain_9287_1_1,
 804                 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
 805         } else if (AR_SREV_9287_10(ah)) {
 806                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 807                 ar9287Modes_tx_gain_9287_1_0,
 808                 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);
 809         } else if (AR_SREV_9280_20(ah)) {
 810                 ath9k_hw_init_txgain_ini(ah);
 811         } else if (AR_SREV_9285_12_OR_LATER(ah)) {
 812                 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
 813
 814                 /* txgain table */
 815                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
 816                         if (AR_SREV_9285E_20(ah)) {
 817                                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 818                                 ar9285Modes_XE2_0_high_power,
 819                                 ARRAY_SIZE(
 820                                   ar9285Modes_XE2_0_high_power), 6);
 821                         } else {
 822                                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 823                                 ar9285Modes_high_power_tx_gain_9285_1_2,
 824                                 ARRAY_SIZE(
 825                                   ar9285Modes_high_power_tx_gain_9285_1_2), 6);
 826                         }
 827                 } else {
 828                         if (AR_SREV_9285E_20(ah)) {
 829                                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 830                                 ar9285Modes_XE2_0_normal_power,
 831                                 ARRAY_SIZE(
 832                                   ar9285Modes_XE2_0_normal_power), 6);
 833                         } else {
 834                                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 835                                 ar9285Modes_original_tx_gain_9285_1_2,
 836                                 ARRAY_SIZE(
 837                                   ar9285Modes_original_tx_gain_9285_1_2), 6);
 838                         }
 839                 }
 840         }
 841 }
 842
 843 static void ath9k_hw_init_eeprom_fix(struct ath_hw *ah)
 844 {
 845         struct base_eep_header *pBase = &(ah->eeprom.def.baseEepHeader);
 846         struct ath_common *common = ath9k_hw_common(ah);
 847
 848         ah->need_an_top2_fixup = (ah->hw_version.devid == AR9280_DEVID_PCI) &&
 849                                  (ah->eep_map != EEP_MAP_4KBITS) &&
 850                                  ((pBase->version & 0xff) > 0x0a) &&
 851                                  (pBase->pwdclkind == 0);
 852
 853         if (ah->need_an_top2_fixup)
 854                 ath_print(common, ATH_DBG_EEPROM,
 855                           "needs fixup for AR_AN_TOP2 register\n");
 856 }
 857
 858 /* Called for all hardware families */
 859 static int __ath9k_hw_init(struct ath_hw *ah)
 860 {
 861         struct ath_common *common = ath9k_hw_common(ah);
 862         int r = 0;
 863
 864         ath9k_hw_init_defaults(ah);
 865         ath9k_hw_init_config(ah);
 866
 867         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
 868                 ath_print(common, ATH_DBG_FATAL,
 869                           "Couldn't reset chip\n");
 870                 return -EIO;
 871         }
 872
 873         ar9002_hw_attach_ops(ah);
 874
 875         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
 876                 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
 877                 return -EIO;
 878         }
 879
 880         if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
 881                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
 882                     (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
 883                         ah->config.serialize_regmode =
 884                                 SER_REG_MODE_ON;
 885                 } else {
 886                         ah->config.serialize_regmode =
 887                                 SER_REG_MODE_OFF;
 888                 }
 889         }
 890
 891         ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
 892                 ah->config.serialize_regmode);
 893
 894         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
 895                 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
 896         else
 897                 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
 898
 899         if (!ath9k_hw_macversion_supported(ah)) {
 900                 ath_print(common, ATH_DBG_FATAL,
 901                           "Mac Chip Rev 0x%02x.%x is not supported by "
 902                           "this driver\n", ah->hw_version.macVersion,
 903                           ah->hw_version.macRev);
 904                 return -EOPNOTSUPP;
 905         }
 906
 907         if (AR_SREV_9100(ah)) {
 908                 ah->iq_caldata.calData = &iq_cal_multi_sample;
 909                 ah->supp_cals = IQ_MISMATCH_CAL;
 910                 ah->is_pciexpress = false;
 911         }
 912
 913         if (AR_SREV_9271(ah))
 914                 ah->is_pciexpress = false;
 915
 916         /* XXX: move this to its own hw op */
 917         ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
 918
 919         ath9k_hw_init_cal_settings(ah);
 920
 921         ah->ani_function = ATH9K_ANI_ALL;
 922         if (AR_SREV_9280_10_OR_LATER(ah)) {
 923                 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
 924                 ah->ath9k_hw_rf_set_freq = &ath9k_hw_ar9280_set_channel;
 925                 ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_9280_spur_mitigate;
 926         } else {
 927                 ah->ath9k_hw_rf_set_freq = &ath9k_hw_set_channel;
 928                 ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_spur_mitigate;
 929         }
 930
 931         ath9k_hw_init_mode_regs(ah);
 932
 933         if (ah->is_pciexpress)
 934                 ath9k_hw_configpcipowersave(ah, 0, 0);
 935         else
 936                 ath9k_hw_disablepcie(ah);
 937
 938         /* Support for Japan ch.14 (2484) spread */
 939         if (AR_SREV_9287_11_OR_LATER(ah)) {
 940                 INIT_INI_ARRAY(&ah->iniCckfirNormal,
 941                        ar9287Common_normal_cck_fir_coeff_92871_1,
 942                        ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_92871_1), 2);
 943                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 944                        ar9287Common_japan_2484_cck_fir_coeff_92871_1,
 945                        ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_92871_1), 2);
 946         }
 947
 948         r = ath9k_hw_post_init(ah);
 949         if (r)
 950                 return r;
 951
 952         ath9k_hw_init_mode_gain_regs(ah);
 953         r = ath9k_hw_fill_cap_info(ah);
 954         if (r)
 955                 return r;
 956
 957         ath9k_hw_init_eeprom_fix(ah);
 958
 959         r = ath9k_hw_init_macaddr(ah);
 960         if (r) {
 961                 ath_print(common, ATH_DBG_FATAL,
 962                           "Failed to initialize MAC address\n");
 963                 return r;
 964         }
 965
 966         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
 967                 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
 968         else
 969                 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
 970
 971         ath9k_init_nfcal_hist_buffer(ah);
 972
 973         common->state = ATH_HW_INITIALIZED;
 974
 975         return 0;
 976 }
 977
 978 int ath9k_hw_init(struct ath_hw *ah)
 979 {
 980         int ret;
 981         struct ath_common *common = ath9k_hw_common(ah);
 982
 983         /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
 984         switch (ah->hw_version.devid) {
 985         case AR5416_DEVID_PCI:
 986         case AR5416_DEVID_PCIE:
 987         case AR5416_AR9100_DEVID:
 988         case AR9160_DEVID_PCI:
 989         case AR9280_DEVID_PCI:
 990         case AR9280_DEVID_PCIE:
 991         case AR9285_DEVID_PCIE:
 992         case AR5416_DEVID_AR9287_PCI:
 993         case AR5416_DEVID_AR9287_PCIE:
 994         case AR2427_DEVID_PCIE:
 995                 break;
 996         default:
 997                 if (common->bus_ops->ath_bus_type == ATH_USB)
 998                         break;
 999                 ath_print(common, ATH_DBG_FATAL,
1000                           "Hardware device ID 0x%04x not supported\n",
1001                           ah->hw_version.devid);
1002                 return -EOPNOTSUPP;
1003         }
1004
1005         ret = __ath9k_hw_init(ah);
1006         if (ret) {
1007                 ath_print(common, ATH_DBG_FATAL,
1008                           "Unable to initialize hardware; "
1009                           "initialization status: %d\n", ret);
1010                 return ret;
1011         }
1012
1013         return 0;
1014 }
1015 EXPORT_SYMBOL(ath9k_hw_init);
1016
1017 static void ath9k_hw_init_bb(struct ath_hw *ah,
1018                              struct ath9k_channel *chan)
1019 {
1020         u32 synthDelay;
1021
1022         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1023         if (IS_CHAN_B(chan))
1024                 synthDelay = (4 * synthDelay) / 22;
1025         else
1026                 synthDelay /= 10;
1027
1028         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
1029
1030         udelay(synthDelay + BASE_ACTIVATE_DELAY);
1031 }
1032
1033 static void ath9k_hw_init_qos(struct ath_hw *ah)
1034 {
1035         REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
1036         REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
1037
1038         REG_WRITE(ah, AR_QOS_NO_ACK,
1039                   SM(2, AR_QOS_NO_ACK_TWO_BIT) |
1040                   SM(5, AR_QOS_NO_ACK_BIT_OFF) |
1041                   SM(0, AR_QOS_NO_ACK_BYTE_OFF));
1042
1043         REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
1044         REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
1045         REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
1046         REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
1047         REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
1048 }
1049
1050 static void ath9k_hw_init_pll(struct ath_hw *ah,
1051                               struct ath9k_channel *chan)
1052 {
1053         u32 pll;
1054
1055         if (AR_SREV_9100(ah)) {
1056                 if (chan && IS_CHAN_5GHZ(chan))
1057                         pll = 0x1450;
1058                 else
1059                         pll = 0x1458;
1060         } else {
1061                 if (AR_SREV_9280_10_OR_LATER(ah)) {
1062                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1063
1064                         if (chan && IS_CHAN_HALF_RATE(chan))
1065                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1066                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1067                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1068
1069                         if (chan && IS_CHAN_5GHZ(chan)) {
1070                                 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
1071
1072
1073                                 if (AR_SREV_9280_20(ah)) {
1074                                         if (((chan->channel % 20) == 0)
1075                                             || ((chan->channel % 10) == 0))
1076                                                 pll = 0x2850;
1077                                         else
1078                                                 pll = 0x142c;
1079                                 }
1080                         } else {
1081                                 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
1082                         }
1083
1084                 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1085
1086                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1087
1088                         if (chan && IS_CHAN_HALF_RATE(chan))
1089                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1090                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1091                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1092
1093                         if (chan && IS_CHAN_5GHZ(chan))
1094                                 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1095                         else
1096                                 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1097                 } else {
1098                         pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1099
1100                         if (chan && IS_CHAN_HALF_RATE(chan))
1101                                 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1102                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1103                                 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1104
1105                         if (chan && IS_CHAN_5GHZ(chan))
1106                                 pll |= SM(0xa, AR_RTC_PLL_DIV);
1107                         else
1108                                 pll |= SM(0xb, AR_RTC_PLL_DIV);
1109                 }
1110         }
1111         REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
1112
1113         /* Switch the core clock for ar9271 to 117Mhz */
1114         if (AR_SREV_9271(ah)) {
1115                 udelay(500);
1116                 REG_WRITE(ah, 0x50040, 0x304);
1117         }
1118
1119         udelay(RTC_PLL_SETTLE_DELAY);
1120
1121         REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1122 }
1123
1124 static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
1125 {
1126         int rx_chainmask, tx_chainmask;
1127
1128         rx_chainmask = ah->rxchainmask;
1129         tx_chainmask = ah->txchainmask;
1130
1131         switch (rx_chainmask) {
1132         case 0x5:
1133                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1134                             AR_PHY_SWAP_ALT_CHAIN);
1135         case 0x3:
1136                 if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) {
1137                         REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1138                         REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1139                         break;
1140                 }
1141         case 0x1:
1142         case 0x2:
1143         case 0x7:
1144                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1145                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1146                 break;
1147         default:
1148                 break;
1149         }
1150
1151         REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1152         if (tx_chainmask == 0x5) {
1153                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1154                             AR_PHY_SWAP_ALT_CHAIN);
1155         }
1156         if (AR_SREV_9100(ah))
1157                 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1158                           REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1159 }
1160
1161 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1162                                           enum nl80211_iftype opmode)
1163 {
1164         u32 imr_reg = AR_IMR_TXERR |
1165                 AR_IMR_TXURN |
1166                 AR_IMR_RXERR |
1167                 AR_IMR_RXORN |
1168                 AR_IMR_BCNMISC;
1169
1170         if (ah->config.rx_intr_mitigation)
1171                 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1172         else
1173                 imr_reg |= AR_IMR_RXOK;
1174
1175         imr_reg |= AR_IMR_TXOK;
1176
1177         if (opmode == NL80211_IFTYPE_AP)
1178                 imr_reg |= AR_IMR_MIB;
1179
1180         REG_WRITE(ah, AR_IMR, imr_reg);
1181         ah->imrs2_reg |= AR_IMR_S2_GTT;
1182         REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
1183
1184         if (!AR_SREV_9100(ah)) {
1185                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1186                 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1187                 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1188         }
1189 }
1190
1191 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
1192 {
1193         u32 val = ath9k_hw_mac_to_clks(ah, us);
1194         val = min(val, (u32) 0xFFFF);
1195         REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
1196 }
1197
1198 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1199 {
1200         u32 val = ath9k_hw_mac_to_clks(ah, us);
1201         val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
1202         REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
1203 }
1204
1205 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1206 {
1207         u32 val = ath9k_hw_mac_to_clks(ah, us);
1208         val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
1209         REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
1210 }
1211
1212 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1213 {
1214         if (tu > 0xFFFF) {
1215                 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
1216                           "bad global tx timeout %u\n", tu);
1217                 ah->globaltxtimeout = (u32) -1;
1218                 return false;
1219         } else {
1220                 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1221                 ah->globaltxtimeout = tu;
1222                 return true;
1223         }
1224 }
1225
1226 void ath9k_hw_init_global_settings(struct ath_hw *ah)
1227 {
1228         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
1229         int acktimeout;
1230         int slottime;
1231         int sifstime;
1232
1233         ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
1234                   ah->misc_mode);
1235
1236         if (ah->misc_mode != 0)
1237                 REG_WRITE(ah, AR_PCU_MISC,
1238                           REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
1239
1240         if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
1241                 sifstime = 16;
1242         else
1243                 sifstime = 10;
1244
1245         /* As defined by IEEE 802.11-2007 17.3.8.6 */
1246         slottime = ah->slottime + 3 * ah->coverage_class;
1247         acktimeout = slottime + sifstime;
1248
1249         /*
1250          * Workaround for early ACK timeouts, add an offset to match the
1251          * initval's 64us ack timeout value.
1252          * This was initially only meant to work around an issue with delayed
1253          * BA frames in some implementations, but it has been found to fix ACK
1254          * timeout issues in other cases as well.
1255          */
1256         if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
1257                 acktimeout += 64 - sifstime - ah->slottime;
1258
1259         ath9k_hw_setslottime(ah, slottime);
1260         ath9k_hw_set_ack_timeout(ah, acktimeout);
1261         ath9k_hw_set_cts_timeout(ah, acktimeout);
1262         if (ah->globaltxtimeout != (u32) -1)
1263                 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1264 }
1265 EXPORT_SYMBOL(ath9k_hw_init_global_settings);
1266
1267 void ath9k_hw_deinit(struct ath_hw *ah)
1268 {
1269         struct ath_common *common = ath9k_hw_common(ah);
1270
1271         if (common->state < ATH_HW_INITIALIZED)
1272                 goto free_hw;
1273
1274         if (!AR_SREV_9100(ah))
1275                 ath9k_hw_ani_disable(ah);
1276
1277         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1278
1279 free_hw:
1280         if (!AR_SREV_9280_10_OR_LATER(ah))
1281                 ath9k_hw_rf_free_ext_banks(ah);
1282 }
1283 EXPORT_SYMBOL(ath9k_hw_deinit);
1284
1285 /*******/
1286 /* INI */
1287 /*******/
1288
1289 static void ath9k_hw_override_ini(struct ath_hw *ah,
1290                                   struct ath9k_channel *chan)
1291 {
1292         u32 val;
1293
1294         /*
1295          * Set the RX_ABORT and RX_DIS and clear if off only after
1296          * RXE is set for MAC. This prevents frames with corrupted
1297          * descriptor status.
1298          */
1299         REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1300
1301         if (AR_SREV_9280_10_OR_LATER(ah)) {
1302                 val = REG_READ(ah, AR_PCU_MISC_MODE2);
1303
1304                 if (!AR_SREV_9271(ah))
1305                         val &= ~AR_PCU_MISC_MODE2_HWWAR1;
1306
1307                 if (AR_SREV_9287_10_OR_LATER(ah))
1308                         val = val & (~AR_PCU_MISC_MODE2_HWWAR2);
1309
1310                 REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
1311         }
1312
1313         if (!AR_SREV_5416_20_OR_LATER(ah) ||
1314             AR_SREV_9280_10_OR_LATER(ah))
1315                 return;
1316         /*
1317          * Disable BB clock gating
1318          * Necessary to avoid issues on AR5416 2.0
1319          */
1320         REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1321
1322         /*
1323          * Disable RIFS search on some chips to avoid baseband
1324          * hang issues.
1325          */
1326         if (AR_SREV_9100(ah) || AR_SREV_9160(ah)) {
1327                 val = REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS);
1328                 val &= ~AR_PHY_RIFS_INIT_DELAY;
1329                 REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val);
1330         }
1331 }
1332
1333 static void ath9k_olc_init(struct ath_hw *ah)
1334 {
1335         u32 i;
1336
1337         if (OLC_FOR_AR9287_10_LATER) {
1338                 REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,
1339                                 AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);
1340                 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0,
1341                                 AR9287_AN_TXPC0_TXPCMODE,
1342                                 AR9287_AN_TXPC0_TXPCMODE_S,
1343                                 AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE);
1344                 udelay(100);
1345         } else {
1346                 for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
1347                         ah->originalGain[i] =
1348                                 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
1349                                                 AR_PHY_TX_GAIN);
1350                 ah->PDADCdelta = 0;
1351         }
1352 }
1353
1354 static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
1355                               struct ath9k_channel *chan)
1356 {
1357         u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1358
1359         if (IS_CHAN_B(chan))
1360                 ctl |= CTL_11B;
1361         else if (IS_CHAN_G(chan))
1362                 ctl |= CTL_11G;
1363         else
1364                 ctl |= CTL_11A;
1365
1366         return ctl;
1367 }
1368
1369 static int ath9k_hw_process_ini(struct ath_hw *ah,
1370                                 struct ath9k_channel *chan)
1371 {
1372         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1373         int i, regWrites = 0;
1374         struct ieee80211_channel *channel = chan->chan;
1375         u32 modesIndex, freqIndex;
1376
1377         switch (chan->chanmode) {
1378         case CHANNEL_A:
1379         case CHANNEL_A_HT20:
1380                 modesIndex = 1;
1381                 freqIndex = 1;
1382                 break;
1383         case CHANNEL_A_HT40PLUS:
1384         case CHANNEL_A_HT40MINUS:
1385                 modesIndex = 2;
1386                 freqIndex = 1;
1387                 break;
1388         case CHANNEL_G:
1389         case CHANNEL_G_HT20:
1390         case CHANNEL_B:
1391                 modesIndex = 4;
1392                 freqIndex = 2;
1393                 break;
1394         case CHANNEL_G_HT40PLUS:
1395         case CHANNEL_G_HT40MINUS:
1396                 modesIndex = 3;
1397                 freqIndex = 2;
1398                 break;
1399
1400         default:
1401                 return -EINVAL;
1402         }
1403
1404         /* Set correct baseband to analog shift setting to access analog chips */
1405         REG_WRITE(ah, AR_PHY(0), 0x00000007);
1406
1407         /* Write ADDAC shifts */
1408         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1409         ah->eep_ops->set_addac(ah, chan);
1410
1411         if (AR_SREV_5416_22_OR_LATER(ah)) {
1412                 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
1413         } else {
1414                 struct ar5416IniArray temp;
1415                 u32 addacSize =
1416                         sizeof(u32) * ah->iniAddac.ia_rows *
1417                         ah->iniAddac.ia_columns;
1418
1419                 /* For AR5416 2.0/2.1 */
1420                 memcpy(ah->addac5416_21,
1421                        ah->iniAddac.ia_array, addacSize);
1422
1423                 /* override CLKDRV value at [row, column] = [31, 1] */
1424                 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
1425
1426                 temp.ia_array = ah->addac5416_21;
1427                 temp.ia_columns = ah->iniAddac.ia_columns;
1428                 temp.ia_rows = ah->iniAddac.ia_rows;
1429                 REG_WRITE_ARRAY(&temp, 1, regWrites);
1430         }
1431
1432         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1433
1434         for (i = 0; i < ah->iniModes.ia_rows; i++) {
1435                 u32 reg = INI_RA(&ah->iniModes, i, 0);
1436                 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
1437
1438                 if (reg == AR_AN_TOP2 && ah->need_an_top2_fixup)
1439                         val &= ~AR_AN_TOP2_PWDCLKIND;
1440
1441                 REG_WRITE(ah, reg, val);
1442
1443                 if (reg >= 0x7800 && reg < 0x78a0
1444                     && ah->config.analog_shiftreg) {
1445                         udelay(100);
1446                 }
1447
1448                 DO_DELAY(regWrites);
1449         }
1450
1451         if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah))
1452                 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
1453
1454         if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
1455             AR_SREV_9287_10_OR_LATER(ah))
1456                 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1457
1458         if (AR_SREV_9271_10(ah))
1459                 REG_WRITE_ARRAY(&ah->iniModes_9271_1_0_only,
1460                                 modesIndex, regWrites);
1461
1462         /* Write common array parameters */
1463         for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1464                 u32 reg = INI_RA(&ah->iniCommon, i, 0);
1465                 u32 val = INI_RA(&ah->iniCommon, i, 1);
1466
1467                 REG_WRITE(ah, reg, val);
1468
1469                 if (reg >= 0x7800 && reg < 0x78a0
1470                     && ah->config.analog_shiftreg) {
1471                         udelay(100);
1472                 }
1473
1474                 DO_DELAY(regWrites);
1475         }
1476
1477         if (AR_SREV_9271(ah)) {
1478                 if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) == 1)
1479                         REG_WRITE_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
1480                                         modesIndex, regWrites);
1481                 else
1482                         REG_WRITE_ARRAY(&ah->iniModes_normal_power_tx_gain_9271,
1483                                         modesIndex, regWrites);
1484         }
1485
1486         ath9k_hw_write_regs(ah, freqIndex, regWrites);
1487
1488         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1489                 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
1490                                 regWrites);
1491         }
1492
1493         ath9k_hw_override_ini(ah, chan);
1494         ath9k_hw_set_regs(ah, chan);
1495         ath9k_hw_init_chain_masks(ah);
1496
1497         if (OLC_FOR_AR9280_20_LATER)
1498                 ath9k_olc_init(ah);
1499
1500         /* Set TX power */
1501         ah->eep_ops->set_txpower(ah, chan,
1502                                  ath9k_regd_get_ctl(regulatory, chan),
1503                                  channel->max_antenna_gain * 2,
1504                                  channel->max_power * 2,
1505                                  min((u32) MAX_RATE_POWER,
1506                                  (u32) regulatory->power_limit));
1507
1508         /* Write analog registers */
1509         if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1510                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1511                           "ar5416SetRfRegs failed\n");
1512                 return -EIO;
1513         }
1514
1515         return 0;
1516 }
1517
1518 /****************************************/
1519 /* Reset and Channel Switching Routines */
1520 /****************************************/
1521
1522 static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
1523 {
1524         u32 rfMode = 0;
1525
1526         if (chan == NULL)
1527                 return;
1528
1529         rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1530                 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1531
1532         if (!AR_SREV_9280_10_OR_LATER(ah))
1533                 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1534                         AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1535
1536         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1537                 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1538
1539         REG_WRITE(ah, AR_PHY_MODE, rfMode);
1540 }
1541
1542 static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
1543 {
1544         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1545 }
1546
1547 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1548 {
1549         u32 regval;
1550
1551         /*
1552          * set AHB_MODE not to do cacheline prefetches
1553         */
1554         regval = REG_READ(ah, AR_AHB_MODE);
1555         REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1556
1557         /*
1558          * let mac dma reads be in 128 byte chunks
1559          */
1560         regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1561         REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1562
1563         /*
1564          * Restore TX Trigger Level to its pre-reset value.
1565          * The initial value depends on whether aggregation is enabled, and is
1566          * adjusted whenever underruns are detected.
1567          */
1568         REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1569
1570         /*
1571          * let mac dma writes be in 128 byte chunks
1572          */
1573         regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1574         REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1575
1576         /*
1577          * Setup receive FIFO threshold to hold off TX activities
1578          */
1579         REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1580
1581         /*
1582          * reduce the number of usable entries in PCU TXBUF to avoid
1583          * wrap around issues.
1584          */
1585         if (AR_SREV_9285(ah)) {
1586                 /* For AR9285 the number of Fifos are reduced to half.
1587                  * So set the usable tx buf size also to half to
1588                  * avoid data/delimiter underruns
1589                  */
1590                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1591                           AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1592         } else if (!AR_SREV_9271(ah)) {
1593                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1594                           AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1595         }
1596 }
1597
1598 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1599 {
1600         u32 val;
1601
1602         val = REG_READ(ah, AR_STA_ID1);
1603         val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1604         switch (opmode) {
1605         case NL80211_IFTYPE_AP:
1606                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1607                           | AR_STA_ID1_KSRCH_MODE);
1608                 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1609                 break;
1610         case NL80211_IFTYPE_ADHOC:
1611         case NL80211_IFTYPE_MESH_POINT:
1612                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1613                           | AR_STA_ID1_KSRCH_MODE);
1614                 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1615                 break;
1616         case NL80211_IFTYPE_STATION:
1617         case NL80211_IFTYPE_MONITOR:
1618                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1619                 break;
1620         }
1621 }
1622
1623 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
1624                                                  u32 coef_scaled,
1625                                                  u32 *coef_mantissa,
1626                                                  u32 *coef_exponent)
1627 {
1628         u32 coef_exp, coef_man;
1629
1630         for (coef_exp = 31; coef_exp > 0; coef_exp--)
1631                 if ((coef_scaled >> coef_exp) & 0x1)
1632                         break;
1633
1634         coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1635
1636         coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1637
1638         *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1639         *coef_exponent = coef_exp - 16;
1640 }
1641
1642 static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
1643                                      struct ath9k_channel *chan)
1644 {
1645         u32 coef_scaled, ds_coef_exp, ds_coef_man;
1646         u32 clockMhzScaled = 0x64000000;
1647         struct chan_centers centers;
1648
1649         if (IS_CHAN_HALF_RATE(chan))
1650                 clockMhzScaled = clockMhzScaled >> 1;
1651         else if (IS_CHAN_QUARTER_RATE(chan))
1652                 clockMhzScaled = clockMhzScaled >> 2;
1653
1654         ath9k_hw_get_channel_centers(ah, chan, &centers);
1655         coef_scaled = clockMhzScaled / centers.synth_center;
1656
1657         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1658                                       &ds_coef_exp);
1659
1660         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1661                       AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1662         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1663                       AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1664
1665         coef_scaled = (9 * coef_scaled) / 10;
1666
1667         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1668                                       &ds_coef_exp);
1669
1670         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1671                       AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1672         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1673                       AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1674 }
1675
1676 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1677 {
1678         u32 rst_flags;
1679         u32 tmpReg;
1680
1681         if (AR_SREV_9100(ah)) {
1682                 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1683                 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1684                 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1685                 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1686                 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1687         }
1688
1689         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1690                   AR_RTC_FORCE_WAKE_ON_INT);
1691
1692         if (AR_SREV_9100(ah)) {
1693                 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1694                         AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1695         } else {
1696                 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1697                 if (tmpReg &
1698                     (AR_INTR_SYNC_LOCAL_TIMEOUT |
1699                      AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1700                         u32 val;
1701                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1702
1703                         val = AR_RC_HOSTIF;
1704                         if (!AR_SREV_9300_20_OR_LATER(ah))
1705                                 val |= AR_RC_AHB;
1706                         REG_WRITE(ah, AR_RC, val);
1707
1708                 } else if (!AR_SREV_9300_20_OR_LATER(ah))
1709                         REG_WRITE(ah, AR_RC, AR_RC_AHB);
1710
1711                 rst_flags = AR_RTC_RC_MAC_WARM;
1712                 if (type == ATH9K_RESET_COLD)
1713                         rst_flags |= AR_RTC_RC_MAC_COLD;
1714         }
1715
1716         REG_WRITE(ah, AR_RTC_RC, rst_flags);
1717         udelay(50);
1718
1719         REG_WRITE(ah, AR_RTC_RC, 0);
1720         if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1721                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1722                           "RTC stuck in MAC reset\n");
1723                 return false;
1724         }
1725
1726         if (!AR_SREV_9100(ah))
1727                 REG_WRITE(ah, AR_RC, 0);
1728
1729         if (AR_SREV_9100(ah))
1730                 udelay(50);
1731
1732         return true;
1733 }
1734
1735 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1736 {
1737         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1738                   AR_RTC_FORCE_WAKE_ON_INT);
1739
1740         if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1741                 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1742
1743         REG_WRITE(ah, AR_RTC_RESET, 0);
1744         udelay(2);
1745
1746         if (!AR_SREV_9100(ah))
1747                 REG_WRITE(ah, AR_RC, 0);
1748
1749         REG_WRITE(ah, AR_RTC_RESET, 1);
1750
1751         if (!ath9k_hw_wait(ah,
1752                            AR_RTC_STATUS,
1753                            AR_RTC_STATUS_M,
1754                            AR_RTC_STATUS_ON,
1755                            AH_WAIT_TIMEOUT)) {
1756                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1757                           "RTC not waking up\n");
1758                 return false;
1759         }
1760
1761         ath9k_hw_read_revisions(ah);
1762
1763         return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1764 }
1765
1766 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1767 {
1768         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1769                   AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1770
1771         switch (type) {
1772         case ATH9K_RESET_POWER_ON:
1773                 return ath9k_hw_set_reset_power_on(ah);
1774         case ATH9K_RESET_WARM:
1775         case ATH9K_RESET_COLD:
1776                 return ath9k_hw_set_reset(ah, type);
1777         default:
1778                 return false;
1779         }
1780 }
1781
1782 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan)
1783 {
1784         u32 phymode;
1785         u32 enableDacFifo = 0;
1786
1787         if (AR_SREV_9285_10_OR_LATER(ah))
1788                 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1789                                          AR_PHY_FC_ENABLE_DAC_FIFO);
1790
1791         phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1792                 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1793
1794         if (IS_CHAN_HT40(chan)) {
1795                 phymode |= AR_PHY_FC_DYN2040_EN;
1796
1797                 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1798                     (chan->chanmode == CHANNEL_G_HT40PLUS))
1799                         phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1800
1801         }
1802         REG_WRITE(ah, AR_PHY_TURBO, phymode);
1803
1804         ath9k_hw_set11nmac2040(ah);
1805
1806         REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1807         REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1808 }
1809
1810 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1811                                 struct ath9k_channel *chan)
1812 {
1813         if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1814                 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1815                         return false;
1816         } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1817                 return false;
1818
1819         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1820                 return false;
1821
1822         ah->chip_fullsleep = false;
1823         ath9k_hw_init_pll(ah, chan);
1824         ath9k_hw_set_rfmode(ah, chan);
1825
1826         return true;
1827 }
1828
1829 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1830                                     struct ath9k_channel *chan)
1831 {
1832         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1833         struct ath_common *common = ath9k_hw_common(ah);
1834         struct ieee80211_channel *channel = chan->chan;
1835         u32 synthDelay, qnum;
1836         int r;
1837
1838         for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1839                 if (ath9k_hw_numtxpending(ah, qnum)) {
1840                         ath_print(common, ATH_DBG_QUEUE,
1841                                   "Transmit frames pending on "
1842                                   "queue %d\n", qnum);
1843                         return false;
1844                 }
1845         }
1846
1847         REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1848         if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1849                            AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
1850                 ath_print(common, ATH_DBG_FATAL,
1851                           "Could not kill baseband RX\n");
1852                 return false;
1853         }
1854
1855         ath9k_hw_set_regs(ah, chan);
1856
1857         r = ah->ath9k_hw_rf_set_freq(ah, chan);
1858         if (r) {
1859                 ath_print(common, ATH_DBG_FATAL,
1860                           "Failed to set channel\n");
1861                 return false;
1862         }
1863
1864         ah->eep_ops->set_txpower(ah, chan,
1865                              ath9k_regd_get_ctl(regulatory, chan),
1866                              channel->max_antenna_gain * 2,
1867                              channel->max_power * 2,
1868                              min((u32) MAX_RATE_POWER,
1869                              (u32) regulatory->power_limit));
1870
1871         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1872         if (IS_CHAN_B(chan))
1873                 synthDelay = (4 * synthDelay) / 22;
1874         else
1875                 synthDelay /= 10;
1876
1877         udelay(synthDelay + BASE_ACTIVATE_DELAY);
1878
1879         REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1880
1881         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1882                 ath9k_hw_set_delta_slope(ah, chan);
1883
1884         ah->ath9k_hw_spur_mitigate_freq(ah, chan);
1885
1886         if (!chan->oneTimeCalsDone)
1887                 chan->oneTimeCalsDone = true;
1888
1889         return true;
1890 }
1891
1892 static void ath9k_enable_rfkill(struct ath_hw *ah)
1893 {
1894         REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
1895                     AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
1896
1897         REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
1898                     AR_GPIO_INPUT_MUX2_RFSILENT);
1899
1900         ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
1901         REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
1902 }
1903
1904 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1905                     bool bChannelChange)
1906 {
1907         struct ath_common *common = ath9k_hw_common(ah);
1908         u32 saveLedState;
1909         struct ath9k_channel *curchan = ah->curchan;
1910         u32 saveDefAntenna;
1911         u32 macStaId1;
1912         u64 tsf = 0;
1913         int i, rx_chainmask, r;
1914
1915         ah->txchainmask = common->tx_chainmask;
1916         ah->rxchainmask = common->rx_chainmask;
1917
1918         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1919                 return -EIO;
1920
1921         if (curchan && !ah->chip_fullsleep)
1922                 ath9k_hw_getnf(ah, curchan);
1923
1924         if (bChannelChange &&
1925             (ah->chip_fullsleep != true) &&
1926             (ah->curchan != NULL) &&
1927             (chan->channel != ah->curchan->channel) &&
1928             ((chan->channelFlags & CHANNEL_ALL) ==
1929              (ah->curchan->channelFlags & CHANNEL_ALL)) &&
1930              !(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) ||
1931              IS_CHAN_A_5MHZ_SPACED(ah->curchan))) {
1932
1933                 if (ath9k_hw_channel_change(ah, chan)) {
1934                         ath9k_hw_loadnf(ah, ah->curchan);
1935                         ath9k_hw_start_nfcal(ah);
1936                         return 0;
1937                 }
1938         }
1939
1940         saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1941         if (saveDefAntenna == 0)
1942                 saveDefAntenna = 1;
1943
1944         macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1945
1946         /* For chips on which RTC reset is done, save TSF before it gets cleared */
1947         if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1948                 tsf = ath9k_hw_gettsf64(ah);
1949
1950         saveLedState = REG_READ(ah, AR_CFG_LED) &
1951                 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1952                  AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1953
1954         ath9k_hw_mark_phy_inactive(ah);
1955
1956         /* Only required on the first reset */
1957         if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1958                 REG_WRITE(ah,
1959                           AR9271_RESET_POWER_DOWN_CONTROL,
1960                           AR9271_RADIO_RF_RST);
1961                 udelay(50);
1962         }
1963
1964         if (!ath9k_hw_chip_reset(ah, chan)) {
1965                 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
1966                 return -EINVAL;
1967         }
1968
1969         /* Only required on the first reset */
1970         if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1971                 ah->htc_reset_init = false;
1972                 REG_WRITE(ah,
1973                           AR9271_RESET_POWER_DOWN_CONTROL,
1974                           AR9271_GATE_MAC_CTL);
1975                 udelay(50);
1976         }
1977
1978         /* Restore TSF */
1979         if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1980                 ath9k_hw_settsf64(ah, tsf);
1981
1982         if (AR_SREV_9280_10_OR_LATER(ah))
1983                 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1984
1985         if (AR_SREV_9287_12_OR_LATER(ah)) {
1986                 /* Enable ASYNC FIFO */
1987                 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
1988                                 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
1989                 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
1990                 REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
1991                                 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
1992                 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
1993                                 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
1994         }
1995         r = ath9k_hw_process_ini(ah, chan);
1996         if (r)
1997                 return r;
1998
1999         /* Setup MFP options for CCMP */
2000         if (AR_SREV_9280_20_OR_LATER(ah)) {
2001                 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
2002                  * frames when constructing CCMP AAD. */
2003                 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
2004                               0xc7ff);
2005                 ah->sw_mgmt_crypto = false;
2006         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2007                 /* Disable hardware crypto for management frames */
2008                 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
2009                             AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
2010                 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2011                             AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
2012                 ah->sw_mgmt_crypto = true;
2013         } else
2014                 ah->sw_mgmt_crypto = true;
2015
2016         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2017                 ath9k_hw_set_delta_slope(ah, chan);
2018
2019         ah->ath9k_hw_spur_mitigate_freq(ah, chan);
2020         ah->eep_ops->set_board_values(ah, chan);
2021
2022         REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
2023         REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
2024                   | macStaId1
2025                   | AR_STA_ID1_RTS_USE_DEF
2026                   | (ah->config.
2027                      ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2028                   | ah->sta_id1_defaults);
2029         ath9k_hw_set_operating_mode(ah, ah->opmode);
2030
2031         ath_hw_setbssidmask(common);
2032
2033         REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2034
2035         ath9k_hw_write_associd(ah);
2036
2037         REG_WRITE(ah, AR_ISR, ~0);
2038
2039         REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2040
2041         r = ah->ath9k_hw_rf_set_freq(ah, chan);
2042         if (r)
2043                 return r;
2044
2045         for (i = 0; i < AR_NUM_DCU; i++)
2046                 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2047
2048         ah->intr_txqs = 0;
2049         for (i = 0; i < ah->caps.total_queues; i++)
2050                 ath9k_hw_resettxqueue(ah, i);
2051
2052         ath9k_hw_init_interrupt_masks(ah, ah->opmode);
2053         ath9k_hw_init_qos(ah);
2054
2055         if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2056                 ath9k_enable_rfkill(ah);
2057
2058         ath9k_hw_init_global_settings(ah);
2059
2060         if (AR_SREV_9287_12_OR_LATER(ah)) {
2061                 REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
2062                           AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
2063                 REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
2064                           AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
2065                 REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
2066                           AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
2067
2068                 REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
2069                 REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
2070
2071                 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
2072                             AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
2073                 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
2074                               AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
2075         }
2076         if (AR_SREV_9287_12_OR_LATER(ah)) {
2077                 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2078                                 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
2079         }
2080
2081         REG_WRITE(ah, AR_STA_ID1,
2082                   REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2083
2084         ath9k_hw_set_dma(ah);
2085
2086         REG_WRITE(ah, AR_OBS, 8);
2087
2088         if (ah->config.rx_intr_mitigation) {
2089                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2090                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2091         }
2092
2093         ath9k_hw_init_bb(ah, chan);
2094
2095         if (!ath9k_hw_init_cal(ah, chan))
2096                 return -EIO;
2097
2098         rx_chainmask = ah->rxchainmask;
2099         if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2100                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2101                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2102         }
2103
2104         REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2105
2106         /*
2107          * For big endian systems turn on swapping for descriptors
2108          */
2109         if (AR_SREV_9100(ah)) {
2110                 u32 mask;
2111                 mask = REG_READ(ah, AR_CFG);
2112                 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2113                         ath_print(common, ATH_DBG_RESET,
2114                                 "CFG Byte Swap Set 0x%x\n", mask);
2115                 } else {
2116                         mask =
2117                                 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2118                         REG_WRITE(ah, AR_CFG, mask);
2119                         ath_print(common, ATH_DBG_RESET,
2120                                 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
2121                 }
2122         } else {
2123                 /* Configure AR9271 target WLAN */
2124                 if (AR_SREV_9271(ah))
2125                         REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
2126 #ifdef __BIG_ENDIAN
2127                 else
2128                         REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2129 #endif
2130         }
2131
2132         if (ah->btcoex_hw.enabled)
2133                 ath9k_hw_btcoex_enable(ah);
2134
2135         return 0;
2136 }
2137 EXPORT_SYMBOL(ath9k_hw_reset);
2138
2139 /************************/
2140 /* Key Cache Management */
2141 /************************/
2142
2143 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
2144 {
2145         u32 keyType;
2146
2147         if (entry >= ah->caps.keycache_size) {
2148                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2149                           "keychache entry %u out of range\n", entry);
2150                 return false;
2151         }
2152
2153         keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2154
2155         REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2156         REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2157         REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2158         REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2159         REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2160         REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2161         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2162         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2163
2164         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2165                 u16 micentry = entry + 64;
2166
2167                 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2168                 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2169                 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2170                 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2171
2172         }
2173
2174         return true;
2175 }
2176 EXPORT_SYMBOL(ath9k_hw_keyreset);
2177
2178 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
2179 {
2180         u32 macHi, macLo;
2181
2182         if (entry >= ah->caps.keycache_size) {
2183                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2184                           "keychache entry %u out of range\n", entry);
2185                 return false;
2186         }
2187
2188         if (mac != NULL) {
2189                 macHi = (mac[5] << 8) | mac[4];
2190                 macLo = (mac[3] << 24) |
2191                         (mac[2] << 16) |
2192                         (mac[1] << 8) |
2193                         mac[0];
2194                 macLo >>= 1;
2195                 macLo |= (macHi & 1) << 31;
2196                 macHi >>= 1;
2197         } else {
2198                 macLo = macHi = 0;
2199         }
2200         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2201         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2202
2203         return true;
2204 }
2205 EXPORT_SYMBOL(ath9k_hw_keysetmac);
2206
2207 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2208                                  const struct ath9k_keyval *k,
2209                                  const u8 *mac)
2210 {
2211         const struct ath9k_hw_capabilities *pCap = &ah->caps;
2212         struct ath_common *common = ath9k_hw_common(ah);
2213         u32 key0, key1, key2, key3, key4;
2214         u32 keyType;
2215
2216         if (entry >= pCap->keycache_size) {
2217                 ath_print(common, ATH_DBG_FATAL,
2218                           "keycache entry %u out of range\n", entry);
2219                 return false;
2220         }
2221
2222         switch (k->kv_type) {
2223         case ATH9K_CIPHER_AES_OCB:
2224                 keyType = AR_KEYTABLE_TYPE_AES;
2225                 break;
2226         case ATH9K_CIPHER_AES_CCM:
2227                 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2228                         ath_print(common, ATH_DBG_ANY,
2229                                   "AES-CCM not supported by mac rev 0x%x\n",
2230                                   ah->hw_version.macRev);
2231                         return false;
2232                 }
2233                 keyType = AR_KEYTABLE_TYPE_CCM;
2234                 break;
2235         case ATH9K_CIPHER_TKIP:
2236                 keyType = AR_KEYTABLE_TYPE_TKIP;
2237                 if (ATH9K_IS_MIC_ENABLED(ah)
2238                     && entry + 64 >= pCap->keycache_size) {
2239                         ath_print(common, ATH_DBG_ANY,
2240                                   "entry %u inappropriate for TKIP\n", entry);
2241                         return false;
2242                 }
2243                 break;
2244         case ATH9K_CIPHER_WEP:
2245                 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
2246                         ath_print(common, ATH_DBG_ANY,
2247                                   "WEP key length %u too small\n", k->kv_len);
2248                         return false;
2249                 }
2250                 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
2251                         keyType = AR_KEYTABLE_TYPE_40;
2252                 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2253                         keyType = AR_KEYTABLE_TYPE_104;
2254                 else
2255                         keyType = AR_KEYTABLE_TYPE_128;
2256                 break;
2257         case ATH9K_CIPHER_CLR:
2258                 keyType = AR_KEYTABLE_TYPE_CLR;
2259                 break;
2260         default:
2261                 ath_print(common, ATH_DBG_FATAL,
2262                           "cipher %u not supported\n", k->kv_type);
2263                 return false;
2264         }
2265
2266         key0 = get_unaligned_le32(k->kv_val + 0);
2267         key1 = get_unaligned_le16(k->kv_val + 4);
2268         key2 = get_unaligned_le32(k->kv_val + 6);
2269         key3 = get_unaligned_le16(k->kv_val + 10);
2270         key4 = get_unaligned_le32(k->kv_val + 12);
2271         if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2272                 key4 &= 0xff;
2273
2274         /*
2275          * Note: Key cache registers access special memory area that requires
2276          * two 32-bit writes to actually update the values in the internal
2277          * memory. Consequently, the exact order and pairs used here must be
2278          * maintained.
2279          */
2280
2281         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2282                 u16 micentry = entry + 64;
2283
2284                 /*
2285                  * Write inverted key[47:0] first to avoid Michael MIC errors
2286                  * on frames that could be sent or received at the same time.
2287                  * The correct key will be written in the end once everything
2288                  * else is ready.
2289                  */
2290                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2291                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2292
2293                 /* Write key[95:48] */
2294                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2295                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2296
2297                 /* Write key[127:96] and key type */
2298                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2299                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2300
2301                 /* Write MAC address for the entry */
2302                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2303
2304                 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
2305                         /*
2306                          * TKIP uses two key cache entries:
2307                          * Michael MIC TX/RX keys in the same key cache entry
2308                          * (idx = main index + 64):
2309                          * key0 [31:0] = RX key [31:0]
2310                          * key1 [15:0] = TX key [31:16]
2311                          * key1 [31:16] = reserved
2312                          * key2 [31:0] = RX key [63:32]
2313                          * key3 [15:0] = TX key [15:0]
2314                          * key3 [31:16] = reserved
2315                          * key4 [31:0] = TX key [63:32]
2316                          */
2317                         u32 mic0, mic1, mic2, mic3, mic4;
2318
2319                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2320                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2321                         mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2322                         mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2323                         mic4 = get_unaligned_le32(k->kv_txmic + 4);
2324
2325                         /* Write RX[31:0] and TX[31:16] */
2326                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2327                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2328
2329                         /* Write RX[63:32] and TX[15:0] */
2330                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2331                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2332
2333                         /* Write TX[63:32] and keyType(reserved) */
2334                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2335                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2336                                   AR_KEYTABLE_TYPE_CLR);
2337
2338                 } else {
2339                         /*
2340                          * TKIP uses four key cache entries (two for group
2341                          * keys):
2342                          * Michael MIC TX/RX keys are in different key cache
2343                          * entries (idx = main index + 64 for TX and
2344                          * main index + 32 + 96 for RX):
2345                          * key0 [31:0] = TX/RX MIC key [31:0]
2346                          * key1 [31:0] = reserved
2347                          * key2 [31:0] = TX/RX MIC key [63:32]
2348                          * key3 [31:0] = reserved
2349                          * key4 [31:0] = reserved
2350                          *
2351                          * Upper layer code will call this function separately
2352                          * for TX and RX keys when these registers offsets are
2353                          * used.
2354                          */
2355                         u32 mic0, mic2;
2356
2357                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2358                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2359
2360                         /* Write MIC key[31:0] */
2361                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2362                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2363
2364                         /* Write MIC key[63:32] */
2365                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2366                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2367
2368                         /* Write TX[63:32] and keyType(reserved) */
2369                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2370                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2371                                   AR_KEYTABLE_TYPE_CLR);
2372                 }
2373
2374                 /* MAC address registers are reserved for the MIC entry */
2375                 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2376                 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2377
2378                 /*
2379                  * Write the correct (un-inverted) key[47:0] last to enable
2380                  * TKIP now that all other registers are set with correct
2381                  * values.
2382                  */
2383                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2384                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2385         } else {
2386                 /* Write key[47:0] */
2387                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2388                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2389
2390                 /* Write key[95:48] */
2391                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2392                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2393
2394                 /* Write key[127:96] and key type */
2395                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2396                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2397
2398                 /* Write MAC address for the entry */
2399                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2400         }
2401
2402         return true;
2403 }
2404 EXPORT_SYMBOL(ath9k_hw_set_keycache_entry);
2405
2406 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
2407 {
2408         if (entry < ah->caps.keycache_size) {
2409                 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2410                 if (val & AR_KEYTABLE_VALID)
2411                         return true;
2412         }
2413         return false;
2414 }
2415 EXPORT_SYMBOL(ath9k_hw_keyisvalid);
2416
2417 /******************************/
2418 /* Power Management (Chipset) */
2419 /******************************/
2420
2421 /*
2422  * Notify Power Mgt is disabled in self-generated frames.
2423  * If requested, force chip to sleep.
2424  */
2425 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
2426 {
2427         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2428         if (setChip) {
2429                 /*
2430                  * Clear the RTC force wake bit to allow the
2431                  * mac to go to sleep.
2432                  */
2433                 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2434                             AR_RTC_FORCE_WAKE_EN);
2435                 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
2436                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2437
2438                 /* Shutdown chip. Active low */
2439                 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
2440                         REG_CLR_BIT(ah, (AR_RTC_RESET),
2441                                     AR_RTC_RESET_EN);
2442         }
2443 }
2444
2445 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2446 {
2447         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2448         if (setChip) {
2449                 struct ath9k_hw_capabilities *pCap = &ah->caps;
2450
2451                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2452                         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2453                                   AR_RTC_FORCE_WAKE_ON_INT);
2454                 } else {
2455                         REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2456                                     AR_RTC_FORCE_WAKE_EN);
2457                 }
2458         }
2459 }
2460
2461 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2462 {
2463         u32 val;
2464         int i;
2465
2466         if (setChip) {
2467                 if ((REG_READ(ah, AR_RTC_STATUS) &
2468                      AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2469                         if (ath9k_hw_set_reset_reg(ah,
2470                                            ATH9K_RESET_POWER_ON) != true) {
2471                                 return false;
2472                         }
2473                         ath9k_hw_init_pll(ah, NULL);
2474                 }
2475                 if (AR_SREV_9100(ah))
2476                         REG_SET_BIT(ah, AR_RTC_RESET,
2477                                     AR_RTC_RESET_EN);
2478
2479                 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2480                             AR_RTC_FORCE_WAKE_EN);
2481                 udelay(50);
2482
2483                 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2484                         val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2485                         if (val == AR_RTC_STATUS_ON)
2486                                 break;
2487                         udelay(50);
2488                         REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2489                                     AR_RTC_FORCE_WAKE_EN);
2490                 }
2491                 if (i == 0) {
2492                         ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2493                                   "Failed to wakeup in %uus\n",
2494                                   POWER_UP_TIME / 20);
2495                         return false;
2496                 }
2497         }
2498
2499         REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2500
2501         return true;
2502 }
2503
2504 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2505 {
2506         struct ath_common *common = ath9k_hw_common(ah);
2507         int status = true, setChip = true;
2508         static const char *modes[] = {
2509                 "AWAKE",
2510                 "FULL-SLEEP",
2511                 "NETWORK SLEEP",
2512                 "UNDEFINED"
2513         };
2514
2515         if (ah->power_mode == mode)
2516                 return status;
2517
2518         ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
2519                   modes[ah->power_mode], modes[mode]);
2520
2521         switch (mode) {
2522         case ATH9K_PM_AWAKE:
2523                 status = ath9k_hw_set_power_awake(ah, setChip);
2524                 break;
2525         case ATH9K_PM_FULL_SLEEP:
2526                 ath9k_set_power_sleep(ah, setChip);
2527                 ah->chip_fullsleep = true;
2528                 break;
2529         case ATH9K_PM_NETWORK_SLEEP:
2530                 ath9k_set_power_network_sleep(ah, setChip);
2531                 break;
2532         default:
2533                 ath_print(common, ATH_DBG_FATAL,
2534                           "Unknown power mode %u\n", mode);
2535                 return false;
2536         }
2537         ah->power_mode = mode;
2538
2539         return status;
2540 }
2541 EXPORT_SYMBOL(ath9k_hw_setpower);
2542
2543 /*
2544  * Helper for ASPM support.
2545  *
2546  * Disable PLL when in L0s as well as receiver clock when in L1.
2547  * This power saving option must be enabled through the SerDes.
2548  *
2549  * Programming the SerDes must go through the same 288 bit serial shift
2550  * register as the other analog registers.  Hence the 9 writes.
2551  */
2552 static void ar9002_hw_configpcipowersave(struct ath_hw *ah,
2553                                          int restore,
2554                                          int power_off)
2555 {
2556         u8 i;
2557         u32 val;
2558
2559         if (ah->is_pciexpress != true)
2560                 return;
2561
2562         /* Do not touch SerDes registers */
2563         if (ah->config.pcie_powersave_enable == 2)
2564                 return;
2565
2566         /* Nothing to do on restore for 11N */
2567         if (!restore) {
2568                 if (AR_SREV_9280_20_OR_LATER(ah)) {
2569                         /*
2570                          * AR9280 2.0 or later chips use SerDes values from the
2571                          * initvals.h initialized depending on chipset during
2572                          * __ath9k_hw_init()
2573                          */
2574                         for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
2575                                 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
2576                                           INI_RA(&ah->iniPcieSerdes, i, 1));
2577                         }
2578                 } else if (AR_SREV_9280(ah) &&
2579                            (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
2580                         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2581                         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2582
2583                         /* RX shut off when elecidle is asserted */
2584                         REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2585                         REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2586                         REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2587
2588                         /* Shut off CLKREQ active in L1 */
2589                         if (ah->config.pcie_clock_req)
2590                                 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2591                         else
2592                                 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2593
2594                         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2595                         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2596                         REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2597
2598                         /* Load the new settings */
2599                         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2600
2601                 } else {
2602                         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2603                         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2604
2605                         /* RX shut off when elecidle is asserted */
2606                         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2607                         REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2608                         REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2609
2610                         /*
2611                          * Ignore ah->ah_config.pcie_clock_req setting for
2612                          * pre-AR9280 11n
2613                          */
2614                         REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2615
2616                         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2617                         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2618                         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2619
2620                         /* Load the new settings */
2621                         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2622                 }
2623
2624                 udelay(1000);
2625
2626                 /* set bit 19 to allow forcing of pcie core into L1 state */
2627                 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2628
2629                 /* Several PCIe massages to ensure proper behaviour */
2630                 if (ah->config.pcie_waen) {
2631                         val = ah->config.pcie_waen;
2632                         if (!power_off)
2633                                 val &= (~AR_WA_D3_L1_DISABLE);
2634                 } else {
2635                         if (AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
2636                             AR_SREV_9287(ah)) {
2637                                 val = AR9285_WA_DEFAULT;
2638                                 if (!power_off)
2639                                         val &= (~AR_WA_D3_L1_DISABLE);
2640                         } else if (AR_SREV_9280(ah)) {
2641                                 /*
2642                                  * On AR9280 chips bit 22 of 0x4004 needs to be
2643                                  * set otherwise card may disappear.
2644                                  */
2645                                 val = AR9280_WA_DEFAULT;
2646                                 if (!power_off)
2647                                         val &= (~AR_WA_D3_L1_DISABLE);
2648                         } else
2649                                 val = AR_WA_DEFAULT;
2650                 }
2651
2652                 REG_WRITE(ah, AR_WA, val);
2653         }
2654
2655         if (power_off) {
2656                 /*
2657                  * Set PCIe workaround bits
2658                  * bit 14 in WA register (disable L1) should only
2659                  * be set when device enters D3 and be cleared
2660                  * when device comes back to D0.
2661                  */
2662                 if (ah->config.pcie_waen) {
2663                         if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)
2664                                 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
2665                 } else {
2666                         if (((AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
2667                               AR_SREV_9287(ah)) &&
2668                              (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) ||
2669                             (AR_SREV_9280(ah) &&
2670                              (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) {
2671                                 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
2672                         }
2673                 }
2674         }
2675 }
2676
2677 /**********************/
2678 /* Interrupt Handling */
2679 /**********************/
2680
2681 bool ath9k_hw_intrpend(struct ath_hw *ah)
2682 {
2683         u32 host_isr;
2684
2685         if (AR_SREV_9100(ah))
2686                 return true;
2687
2688         host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
2689         if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
2690                 return true;
2691
2692         host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
2693         if ((host_isr & AR_INTR_SYNC_DEFAULT)
2694             && (host_isr != AR_INTR_SPURIOUS))
2695                 return true;
2696
2697         return false;
2698 }
2699 EXPORT_SYMBOL(ath9k_hw_intrpend);
2700
2701 bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
2702 {
2703         u32 isr = 0;
2704         u32 mask2 = 0;
2705         struct ath9k_hw_capabilities *pCap = &ah->caps;
2706         u32 sync_cause = 0;
2707         bool fatal_int = false;
2708         struct ath_common *common = ath9k_hw_common(ah);
2709
2710         if (!AR_SREV_9100(ah)) {
2711                 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
2712                         if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
2713                             == AR_RTC_STATUS_ON) {
2714                                 isr = REG_READ(ah, AR_ISR);
2715                         }
2716                 }
2717
2718                 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
2719                         AR_INTR_SYNC_DEFAULT;
2720
2721                 *masked = 0;
2722
2723                 if (!isr && !sync_cause)
2724                         return false;
2725         } else {
2726                 *masked = 0;
2727                 isr = REG_READ(ah, AR_ISR);
2728         }
2729
2730         if (isr) {
2731                 if (isr & AR_ISR_BCNMISC) {
2732                         u32 isr2;
2733                         isr2 = REG_READ(ah, AR_ISR_S2);
2734                         if (isr2 & AR_ISR_S2_TIM)
2735                                 mask2 |= ATH9K_INT_TIM;
2736                         if (isr2 & AR_ISR_S2_DTIM)
2737                                 mask2 |= ATH9K_INT_DTIM;
2738                         if (isr2 & AR_ISR_S2_DTIMSYNC)
2739                                 mask2 |= ATH9K_INT_DTIMSYNC;
2740                         if (isr2 & (AR_ISR_S2_CABEND))
2741                                 mask2 |= ATH9K_INT_CABEND;
2742                         if (isr2 & AR_ISR_S2_GTT)
2743                                 mask2 |= ATH9K_INT_GTT;
2744                         if (isr2 & AR_ISR_S2_CST)
2745                                 mask2 |= ATH9K_INT_CST;
2746                         if (isr2 & AR_ISR_S2_TSFOOR)
2747                                 mask2 |= ATH9K_INT_TSFOOR;
2748                 }
2749
2750                 isr = REG_READ(ah, AR_ISR_RAC);
2751                 if (isr == 0xffffffff) {
2752                         *masked = 0;
2753                         return false;
2754                 }
2755
2756                 *masked = isr & ATH9K_INT_COMMON;
2757
2758                 if (ah->config.rx_intr_mitigation) {
2759                         if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
2760                                 *masked |= ATH9K_INT_RX;
2761                 }
2762
2763                 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
2764                         *masked |= ATH9K_INT_RX;
2765                 if (isr &
2766                     (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
2767                      AR_ISR_TXEOL)) {
2768                         u32 s0_s, s1_s;
2769
2770                         *masked |= ATH9K_INT_TX;
2771
2772                         s0_s = REG_READ(ah, AR_ISR_S0_S);
2773                         ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
2774                         ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
2775
2776                         s1_s = REG_READ(ah, AR_ISR_S1_S);
2777                         ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
2778                         ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
2779                 }
2780
2781                 if (isr & AR_ISR_RXORN) {
2782                         ath_print(common, ATH_DBG_INTERRUPT,
2783                                   "receive FIFO overrun interrupt\n");
2784                 }
2785
2786                 if (!AR_SREV_9100(ah)) {
2787                         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2788                                 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
2789                                 if (isr5 & AR_ISR_S5_TIM_TIMER)
2790                                         *masked |= ATH9K_INT_TIM_TIMER;
2791                         }
2792                 }
2793
2794                 *masked |= mask2;
2795         }
2796
2797         if (AR_SREV_9100(ah))
2798                 return true;
2799
2800         if (isr & AR_ISR_GENTMR) {
2801                 u32 s5_s;
2802
2803                 s5_s = REG_READ(ah, AR_ISR_S5_S);
2804                 if (isr & AR_ISR_GENTMR) {
2805                         ah->intr_gen_timer_trigger =
2806                                 MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
2807
2808                         ah->intr_gen_timer_thresh =
2809                                 MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
2810
2811                         if (ah->intr_gen_timer_trigger)
2812                                 *masked |= ATH9K_INT_GENTIMER;
2813
2814                 }
2815         }
2816
2817         if (sync_cause) {
2818                 fatal_int =
2819                         (sync_cause &
2820                          (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
2821                         ? true : false;
2822
2823                 if (fatal_int) {
2824                         if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
2825                                 ath_print(common, ATH_DBG_ANY,
2826                                           "received PCI FATAL interrupt\n");
2827                         }
2828                         if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
2829                                 ath_print(common, ATH_DBG_ANY,
2830                                           "received PCI PERR interrupt\n");
2831                         }
2832                         *masked |= ATH9K_INT_FATAL;
2833                 }
2834                 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
2835                         ath_print(common, ATH_DBG_INTERRUPT,
2836                                   "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
2837                         REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
2838                         REG_WRITE(ah, AR_RC, 0);
2839                         *masked |= ATH9K_INT_FATAL;
2840                 }
2841                 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
2842                         ath_print(common, ATH_DBG_INTERRUPT,
2843                                   "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
2844                 }
2845
2846                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
2847                 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
2848         }
2849
2850         return true;
2851 }
2852 EXPORT_SYMBOL(ath9k_hw_getisr);
2853
2854 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
2855 {
2856         enum ath9k_int omask = ah->imask;
2857         u32 mask, mask2;
2858         struct ath9k_hw_capabilities *pCap = &ah->caps;
2859         struct ath_common *common = ath9k_hw_common(ah);
2860
2861         ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
2862
2863         if (omask & ATH9K_INT_GLOBAL) {
2864                 ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n");
2865                 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
2866                 (void) REG_READ(ah, AR_IER);
2867                 if (!AR_SREV_9100(ah)) {
2868                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
2869                         (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
2870
2871                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
2872                         (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
2873                 }
2874         }
2875
2876         mask = ints & ATH9K_INT_COMMON;
2877         mask2 = 0;
2878
2879         if (ints & ATH9K_INT_TX) {
2880                 if (ah->txok_interrupt_mask)
2881                         mask |= AR_IMR_TXOK;
2882                 if (ah->txdesc_interrupt_mask)
2883                         mask |= AR_IMR_TXDESC;
2884                 if (ah->txerr_interrupt_mask)
2885                         mask |= AR_IMR_TXERR;
2886                 if (ah->txeol_interrupt_mask)
2887                         mask |= AR_IMR_TXEOL;
2888         }
2889         if (ints & ATH9K_INT_RX) {
2890                 mask |= AR_IMR_RXERR;
2891                 if (ah->config.rx_intr_mitigation)
2892                         mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
2893                 else
2894                         mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
2895                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
2896                         mask |= AR_IMR_GENTMR;
2897         }
2898
2899         if (ints & (ATH9K_INT_BMISC)) {
2900                 mask |= AR_IMR_BCNMISC;
2901                 if (ints & ATH9K_INT_TIM)
2902                         mask2 |= AR_IMR_S2_TIM;
2903                 if (ints & ATH9K_INT_DTIM)
2904                         mask2 |= AR_IMR_S2_DTIM;
2905                 if (ints & ATH9K_INT_DTIMSYNC)
2906                         mask2 |= AR_IMR_S2_DTIMSYNC;
2907                 if (ints & ATH9K_INT_CABEND)
2908                         mask2 |= AR_IMR_S2_CABEND;
2909                 if (ints & ATH9K_INT_TSFOOR)
2910                         mask2 |= AR_IMR_S2_TSFOOR;
2911         }
2912
2913         if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
2914                 mask |= AR_IMR_BCNMISC;
2915                 if (ints & ATH9K_INT_GTT)
2916                         mask2 |= AR_IMR_S2_GTT;
2917                 if (ints & ATH9K_INT_CST)
2918                         mask2 |= AR_IMR_S2_CST;
2919         }
2920
2921         ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
2922         REG_WRITE(ah, AR_IMR, mask);
2923         ah->imrs2_reg &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC |
2924                            AR_IMR_S2_CABEND | AR_IMR_S2_CABTO |
2925                            AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST);
2926         ah->imrs2_reg |= mask2;
2927         REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
2928
2929         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2930                 if (ints & ATH9K_INT_TIM_TIMER)
2931                         REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2932                 else
2933                         REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2934         }
2935
2936         if (ints & ATH9K_INT_GLOBAL) {
2937                 ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n");
2938                 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
2939                 if (!AR_SREV_9100(ah)) {
2940                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
2941                                   AR_INTR_MAC_IRQ);
2942                         REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
2943
2944
2945                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
2946                                   AR_INTR_SYNC_DEFAULT);
2947                         REG_WRITE(ah, AR_INTR_SYNC_MASK,
2948                                   AR_INTR_SYNC_DEFAULT);
2949                 }
2950                 ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
2951                           REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
2952         }
2953
2954         return omask;
2955 }
2956 EXPORT_SYMBOL(ath9k_hw_set_interrupts);
2957
2958 /*******************/
2959 /* Beacon Handling */
2960 /*******************/
2961
2962 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
2963 {
2964         int flags = 0;
2965
2966         ah->beacon_interval = beacon_period;
2967
2968         switch (ah->opmode) {
2969         case NL80211_IFTYPE_STATION:
2970         case NL80211_IFTYPE_MONITOR:
2971                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
2972                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
2973                 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
2974                 flags |= AR_TBTT_TIMER_EN;
2975                 break;
2976         case NL80211_IFTYPE_ADHOC:
2977         case NL80211_IFTYPE_MESH_POINT:
2978                 REG_SET_BIT(ah, AR_TXCFG,
2979                             AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
2980                 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
2981                           TU_TO_USEC(next_beacon +
2982                                      (ah->atim_window ? ah->
2983                                       atim_window : 1)));
2984                 flags |= AR_NDP_TIMER_EN;
2985         case NL80211_IFTYPE_AP:
2986                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
2987                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
2988                           TU_TO_USEC(next_beacon -
2989                                      ah->config.
2990                                      dma_beacon_response_time));
2991                 REG_WRITE(ah, AR_NEXT_SWBA,
2992                           TU_TO_USEC(next_beacon -
2993                                      ah->config.
2994                                      sw_beacon_response_time));
2995                 flags |=
2996                         AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
2997                 break;
2998         default:
2999                 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
3000                           "%s: unsupported opmode: %d\n",
3001                           __func__, ah->opmode);
3002                 return;
3003                 break;
3004         }
3005
3006         REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3007         REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3008         REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3009         REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3010
3011         beacon_period &= ~ATH9K_BEACON_ENA;
3012         if (beacon_period & ATH9K_BEACON_RESET_TSF) {
3013                 ath9k_hw_reset_tsf(ah);
3014         }
3015
3016         REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3017 }
3018 EXPORT_SYMBOL(ath9k_hw_beaconinit);
3019
3020 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
3021                                     const struct ath9k_beacon_state *bs)
3022 {
3023         u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
3024         struct ath9k_hw_capabilities *pCap = &ah->caps;
3025         struct ath_common *common = ath9k_hw_common(ah);
3026
3027         REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3028
3029         REG_WRITE(ah, AR_BEACON_PERIOD,
3030                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3031         REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3032                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3033
3034         REG_RMW_FIELD(ah, AR_RSSI_THR,
3035                       AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3036
3037         beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3038
3039         if (bs->bs_sleepduration > beaconintval)
3040                 beaconintval = bs->bs_sleepduration;
3041
3042         dtimperiod = bs->bs_dtimperiod;
3043         if (bs->bs_sleepduration > dtimperiod)
3044                 dtimperiod = bs->bs_sleepduration;
3045
3046         if (beaconintval == dtimperiod)
3047                 nextTbtt = bs->bs_nextdtim;
3048         else
3049                 nextTbtt = bs->bs_nexttbtt;
3050
3051         ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3052         ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3053         ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3054         ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3055
3056         REG_WRITE(ah, AR_NEXT_DTIM,
3057                   TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3058         REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
3059
3060         REG_WRITE(ah, AR_SLEEP1,
3061                   SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3062                   | AR_SLEEP1_ASSUME_DTIM);
3063
3064         if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3065                 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3066         else
3067                 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
3068
3069         REG_WRITE(ah, AR_SLEEP2,
3070                   SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
3071
3072         REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3073         REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3074
3075         REG_SET_BIT(ah, AR_TIMER_MODE,
3076                     AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3077                     AR_DTIM_TIMER_EN);
3078
3079         /* TSF Out of Range Threshold */
3080         REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
3081 }
3082 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
3083
3084 /*******************/
3085 /* HW Capabilities */
3086 /*******************/
3087
3088 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
3089 {
3090         struct ath9k_hw_capabilities *pCap = &ah->caps;
3091         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3092         struct ath_common *common = ath9k_hw_common(ah);
3093         struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
3094
3095         u16 capField = 0, eeval;
3096
3097         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
3098         regulatory->current_rd = eeval;
3099
3100         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
3101         if (AR_SREV_9285_10_OR_LATER(ah))
3102                 eeval |= AR9285_RDEXT_DEFAULT;
3103         regulatory->current_rd_ext = eeval;
3104
3105         capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
3106
3107         if (ah->opmode != NL80211_IFTYPE_AP &&
3108             ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3109                 if (regulatory->current_rd == 0x64 ||
3110                     regulatory->current_rd == 0x65)
3111                         regulatory->current_rd += 5;
3112                 else if (regulatory->current_rd == 0x41)
3113                         regulatory->current_rd = 0x43;
3114                 ath_print(common, ATH_DBG_REGULATORY,
3115                           "regdomain mapped to 0x%x\n", regulatory->current_rd);
3116         }
3117
3118         eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
3119         if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
3120                 ath_print(common, ATH_DBG_FATAL,
3121                           "no band has been marked as supported in EEPROM.\n");
3122                 return -EINVAL;
3123         }
3124
3125         bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
3126
3127         if (eeval & AR5416_OPFLAGS_11A) {
3128                 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3129                 if (ah->config.ht_enable) {
3130                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3131                                 set_bit(ATH9K_MODE_11NA_HT20,
3132                                         pCap->wireless_modes);
3133                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3134                                 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3135                                         pCap->wireless_modes);
3136                                 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3137                                         pCap->wireless_modes);
3138                         }
3139                 }
3140         }
3141
3142         if (eeval & AR5416_OPFLAGS_11G) {
3143                 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3144                 if (ah->config.ht_enable) {
3145                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3146                                 set_bit(ATH9K_MODE_11NG_HT20,
3147                                         pCap->wireless_modes);
3148                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3149                                 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3150                                         pCap->wireless_modes);
3151                                 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3152                                         pCap->wireless_modes);
3153                         }
3154                 }
3155         }
3156
3157         pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
3158         /*
3159          * For AR9271 we will temporarilly uses the rx chainmax as read from
3160          * the EEPROM.
3161          */
3162         if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
3163             !(eeval & AR5416_OPFLAGS_11A) &&
3164             !(AR_SREV_9271(ah)))
3165                 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
3166                 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
3167         else
3168                 /* Use rx_chainmask from EEPROM. */
3169                 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
3170
3171         if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
3172                 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
3173
3174         pCap->low_2ghz_chan = 2312;
3175         pCap->high_2ghz_chan = 2732;
3176
3177         pCap->low_5ghz_chan = 4920;
3178         pCap->high_5ghz_chan = 6100;
3179
3180         pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3181         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3182         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3183
3184         pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3185         pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3186         pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3187
3188         if (ah->config.ht_enable)
3189                 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3190         else
3191                 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3192
3193         pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3194         pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3195         pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3196         pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3197
3198         if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3199                 pCap->total_queues =
3200                         MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3201         else
3202                 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3203
3204         if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3205                 pCap->keycache_size =
3206                         1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3207         else
3208                 pCap->keycache_size = AR_KEYTABLE_SIZE;
3209
3210         pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3211
3212         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
3213                 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
3214         else
3215                 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3216
3217         if (AR_SREV_9271(ah))
3218                 pCap->num_gpio_pins = AR9271_NUM_GPIO;
3219         else if (AR_SREV_9285_10_OR_LATER(ah))
3220                 pCap->num_gpio_pins = AR9285_NUM_GPIO;
3221         else if (AR_SREV_9280_10_OR_LATER(ah))
3222                 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3223         else
3224                 pCap->num_gpio_pins = AR_NUM_GPIO;
3225
3226         if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3227                 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3228                 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3229         } else {
3230                 pCap->rts_aggr_limit = (8 * 1024);
3231         }
3232
3233         pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3234
3235 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3236         ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
3237         if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
3238                 ah->rfkill_gpio =
3239                         MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
3240                 ah->rfkill_polarity =
3241                         MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
3242
3243                 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3244         }
3245 #endif
3246         if (AR_SREV_9271(ah))
3247                 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
3248         else
3249                 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3250
3251         if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
3252                 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3253         else
3254                 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3255
3256         if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
3257                 pCap->reg_cap =
3258                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3259                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3260                         AR_EEPROM_EEREGCAP_EN_KK_U2 |
3261                         AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3262         } else {
3263                 pCap->reg_cap =
3264                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3265                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3266         }
3267
3268         /* Advertise midband for AR5416 with FCC midband set in eeprom */
3269         if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
3270             AR_SREV_5416(ah))
3271                 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3272
3273         pCap->num_antcfg_5ghz =
3274                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
3275         pCap->num_antcfg_2ghz =
3276                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
3277
3278         if (AR_SREV_9280_10_OR_LATER(ah) &&
3279             ath9k_hw_btcoex_supported(ah)) {
3280                 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
3281                 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
3282
3283                 if (AR_SREV_9285(ah)) {
3284                         btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
3285                         btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
3286                 } else {
3287                         btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
3288                 }
3289         } else {
3290                 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
3291         }
3292
3293         return 0;
3294 }
3295
3296 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3297                             u32 capability, u32 *result)
3298 {
3299         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3300         switch (type) {
3301         case ATH9K_CAP_CIPHER:
3302                 switch (capability) {
3303                 case ATH9K_CIPHER_AES_CCM:
3304                 case ATH9K_CIPHER_AES_OCB:
3305                 case ATH9K_CIPHER_TKIP:
3306                 case ATH9K_CIPHER_WEP:
3307                 case ATH9K_CIPHER_MIC:
3308                 case ATH9K_CIPHER_CLR:
3309                         return true;
3310                 default:
3311                         return false;
3312                 }
3313         case ATH9K_CAP_TKIP_MIC:
3314                 switch (capability) {
3315                 case 0:
3316                         return true;
3317                 case 1:
3318                         return (ah->sta_id1_defaults &
3319                                 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3320                         false;
3321                 }
3322         case ATH9K_CAP_TKIP_SPLIT:
3323                 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
3324                         false : true;
3325         case ATH9K_CAP_DIVERSITY:
3326                 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3327                         AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3328                         true : false;
3329         case ATH9K_CAP_MCAST_KEYSRCH:
3330                 switch (capability) {
3331                 case 0:
3332                         return true;
3333                 case 1:
3334                         if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3335                                 return false;
3336                         } else {
3337                                 return (ah->sta_id1_defaults &
3338                                         AR_STA_ID1_MCAST_KSRCH) ? true :
3339                                         false;
3340                         }
3341                 }
3342                 return false;
3343         case ATH9K_CAP_TXPOW:
3344                 switch (capability) {
3345                 case 0:
3346                         return 0;
3347                 case 1:
3348                         *result = regulatory->power_limit;
3349                         return 0;
3350                 case 2:
3351                         *result = regulatory->max_power_level;
3352                         return 0;
3353                 case 3:
3354                         *result = regulatory->tp_scale;
3355                         return 0;
3356                 }
3357                 return false;
3358         case ATH9K_CAP_DS:
3359                 return (AR_SREV_9280_20_OR_LATER(ah) &&
3360                         (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
3361                         ? false : true;
3362         default:
3363                 return false;
3364         }
3365 }
3366 EXPORT_SYMBOL(ath9k_hw_getcapability);
3367
3368 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3369                             u32 capability, u32 setting, int *status)
3370 {
3371         u32 v;
3372
3373         switch (type) {
3374         case ATH9K_CAP_TKIP_MIC:
3375                 if (setting)
3376                         ah->sta_id1_defaults |=
3377                                 AR_STA_ID1_CRPT_MIC_ENABLE;
3378                 else
3379                         ah->sta_id1_defaults &=
3380                                 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3381                 return true;
3382         case ATH9K_CAP_DIVERSITY:
3383                 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3384                 if (setting)
3385                         v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3386                 else
3387                         v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3388                 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3389                 return true;
3390         case ATH9K_CAP_MCAST_KEYSRCH:
3391                 if (setting)
3392                         ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
3393                 else
3394                         ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3395                 return true;
3396         default:
3397                 return false;
3398         }
3399 }
3400 EXPORT_SYMBOL(ath9k_hw_setcapability);
3401
3402 /****************************/
3403 /* GPIO / RFKILL / Antennae */
3404 /****************************/
3405
3406 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
3407                                          u32 gpio, u32 type)
3408 {
3409         int addr;
3410         u32 gpio_shift, tmp;
3411
3412         if (gpio > 11)
3413                 addr = AR_GPIO_OUTPUT_MUX3;
3414         else if (gpio > 5)
3415                 addr = AR_GPIO_OUTPUT_MUX2;
3416         else
3417                 addr = AR_GPIO_OUTPUT_MUX1;
3418
3419         gpio_shift = (gpio % 6) * 5;
3420
3421         if (AR_SREV_9280_20_OR_LATER(ah)
3422             || (addr != AR_GPIO_OUTPUT_MUX1)) {
3423                 REG_RMW(ah, addr, (type << gpio_shift),
3424                         (0x1f << gpio_shift));
3425         } else {
3426                 tmp = REG_READ(ah, addr);
3427                 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3428                 tmp &= ~(0x1f << gpio_shift);
3429                 tmp |= (type << gpio_shift);
3430                 REG_WRITE(ah, addr, tmp);
3431         }
3432 }
3433
3434 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
3435 {
3436         u32 gpio_shift;
3437
3438         BUG_ON(gpio >= ah->caps.num_gpio_pins);
3439
3440         gpio_shift = gpio << 1;
3441
3442         REG_RMW(ah,
3443                 AR_GPIO_OE_OUT,
3444                 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3445                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3446 }
3447 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
3448
3449 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
3450 {
3451 #define MS_REG_READ(x, y) \
3452         (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3453
3454         if (gpio >= ah->caps.num_gpio_pins)
3455                 return 0xffffffff;
3456
3457         if (AR_SREV_9300_20_OR_LATER(ah))
3458                 return MS_REG_READ(AR9300, gpio) != 0;
3459         else if (AR_SREV_9271(ah))
3460                 return MS_REG_READ(AR9271, gpio) != 0;
3461         else if (AR_SREV_9287_10_OR_LATER(ah))
3462                 return MS_REG_READ(AR9287, gpio) != 0;
3463         else if (AR_SREV_9285_10_OR_LATER(ah))
3464                 return MS_REG_READ(AR9285, gpio) != 0;
3465         else if (AR_SREV_9280_10_OR_LATER(ah))
3466                 return MS_REG_READ(AR928X, gpio) != 0;
3467         else
3468                 return MS_REG_READ(AR, gpio) != 0;
3469 }
3470 EXPORT_SYMBOL(ath9k_hw_gpio_get);
3471
3472 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
3473                          u32 ah_signal_type)
3474 {
3475         u32 gpio_shift;
3476
3477         ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3478
3479         gpio_shift = 2 * gpio;
3480
3481         REG_RMW(ah,
3482                 AR_GPIO_OE_OUT,
3483                 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3484                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3485 }
3486 EXPORT_SYMBOL(ath9k_hw_cfg_output);
3487
3488 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
3489 {
3490         if (AR_SREV_9271(ah))
3491                 val = ~val;
3492
3493         REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3494                 AR_GPIO_BIT(gpio));
3495 }
3496 EXPORT_SYMBOL(ath9k_hw_set_gpio);
3497
3498 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
3499 {
3500         return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3501 }
3502 EXPORT_SYMBOL(ath9k_hw_getdefantenna);
3503
3504 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
3505 {
3506         REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3507 }
3508 EXPORT_SYMBOL(ath9k_hw_setantenna);
3509
3510 /*********************/
3511 /* General Operation */
3512 /*********************/
3513
3514 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
3515 {
3516         u32 bits = REG_READ(ah, AR_RX_FILTER);
3517         u32 phybits = REG_READ(ah, AR_PHY_ERR);
3518
3519         if (phybits & AR_PHY_ERR_RADAR)
3520                 bits |= ATH9K_RX_FILTER_PHYRADAR;
3521         if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3522                 bits |= ATH9K_RX_FILTER_PHYERR;
3523
3524         return bits;
3525 }
3526 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
3527
3528 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
3529 {
3530         u32 phybits;
3531
3532         REG_WRITE(ah, AR_RX_FILTER, bits);
3533
3534         phybits = 0;
3535         if (bits & ATH9K_RX_FILTER_PHYRADAR)
3536                 phybits |= AR_PHY_ERR_RADAR;
3537         if (bits & ATH9K_RX_FILTER_PHYERR)
3538                 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3539         REG_WRITE(ah, AR_PHY_ERR, phybits);
3540
3541         if (phybits)
3542                 REG_WRITE(ah, AR_RXCFG,
3543                           REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3544         else
3545                 REG_WRITE(ah, AR_RXCFG,
3546                           REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3547 }
3548 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
3549
3550 bool ath9k_hw_phy_disable(struct ath_hw *ah)
3551 {
3552         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
3553                 return false;
3554
3555         ath9k_hw_init_pll(ah, NULL);
3556         return true;
3557 }
3558 EXPORT_SYMBOL(ath9k_hw_phy_disable);
3559
3560 bool ath9k_hw_disable(struct ath_hw *ah)
3561 {
3562         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3563                 return false;
3564
3565         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
3566                 return false;
3567
3568         ath9k_hw_init_pll(ah, NULL);
3569         return true;
3570 }
3571 EXPORT_SYMBOL(ath9k_hw_disable);
3572
3573 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
3574 {
3575         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3576         struct ath9k_channel *chan = ah->curchan;
3577         struct ieee80211_channel *channel = chan->chan;
3578
3579         regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
3580
3581         ah->eep_ops->set_txpower(ah, chan,
3582                                  ath9k_regd_get_ctl(regulatory, chan),
3583                                  channel->max_antenna_gain * 2,
3584                                  channel->max_power * 2,
3585                                  min((u32) MAX_RATE_POWER,
3586                                  (u32) regulatory->power_limit));
3587 }
3588 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
3589
3590 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
3591 {
3592         memcpy(ath9k_hw_common(ah)->macaddr, mac, ETH_ALEN);
3593 }
3594 EXPORT_SYMBOL(ath9k_hw_setmac);
3595
3596 void ath9k_hw_setopmode(struct ath_hw *ah)
3597 {
3598         ath9k_hw_set_operating_mode(ah, ah->opmode);
3599 }
3600 EXPORT_SYMBOL(ath9k_hw_setopmode);
3601
3602 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
3603 {
3604         REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3605         REG_WRITE(ah, AR_MCAST_FIL1, filter1);
3606 }
3607 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
3608
3609 void ath9k_hw_write_associd(struct ath_hw *ah)
3610 {
3611         struct ath_common *common = ath9k_hw_common(ah);
3612
3613         REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
3614         REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
3615                   ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
3616 }
3617 EXPORT_SYMBOL(ath9k_hw_write_associd);
3618
3619 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
3620 {
3621         u64 tsf;
3622
3623         tsf = REG_READ(ah, AR_TSF_U32);
3624         tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
3625
3626         return tsf;
3627 }
3628 EXPORT_SYMBOL(ath9k_hw_gettsf64);
3629
3630 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
3631 {
3632         REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
3633         REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
3634 }
3635 EXPORT_SYMBOL(ath9k_hw_settsf64);
3636
3637 void ath9k_hw_reset_tsf(struct ath_hw *ah)
3638 {
3639         if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
3640                            AH_TSF_WRITE_TIMEOUT))
3641                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
3642                           "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
3643
3644         REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3645 }
3646 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
3647
3648 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
3649 {
3650         if (setting)
3651                 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
3652         else
3653                 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
3654 }
3655 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
3656
3657 /*
3658  *  Extend 15-bit time stamp from rx descriptor to
3659  *  a full 64-bit TSF using the current h/w TSF.
3660 */
3661 u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp)
3662 {
3663         u64 tsf;
3664
3665         tsf = ath9k_hw_gettsf64(ah);
3666         if ((tsf & 0x7fff) < rstamp)
3667                 tsf -= 0x8000;
3668         return (tsf & ~0x7fff) | rstamp;
3669 }
3670 EXPORT_SYMBOL(ath9k_hw_extend_tsf);
3671
3672 void ath9k_hw_set11nmac2040(struct ath_hw *ah)
3673 {
3674         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
3675         u32 macmode;
3676
3677         if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
3678                 macmode = AR_2040_JOINED_RX_CLEAR;
3679         else
3680                 macmode = 0;
3681
3682         REG_WRITE(ah, AR_2040_MODE, macmode);
3683 }
3684
3685 /* HW Generic timers configuration */
3686
3687 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
3688 {
3689         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3690         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3691         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3692         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3693         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3694         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3695         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3696         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3697         {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
3698         {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
3699                                 AR_NDP2_TIMER_MODE, 0x0002},
3700         {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
3701                                 AR_NDP2_TIMER_MODE, 0x0004},
3702         {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
3703                                 AR_NDP2_TIMER_MODE, 0x0008},
3704         {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
3705                                 AR_NDP2_TIMER_MODE, 0x0010},
3706         {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
3707                                 AR_NDP2_TIMER_MODE, 0x0020},
3708         {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
3709                                 AR_NDP2_TIMER_MODE, 0x0040},
3710         {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
3711                                 AR_NDP2_TIMER_MODE, 0x0080}
3712 };
3713
3714 /* HW generic timer primitives */
3715
3716 /* compute and clear index of rightmost 1 */
3717 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
3718 {
3719         u32 b;
3720
3721         b = *mask;
3722         b &= (0-b);
3723         *mask &= ~b;
3724         b *= debruijn32;
3725         b >>= 27;
3726
3727         return timer_table->gen_timer_index[b];
3728 }
3729
3730 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
3731 {
3732         return REG_READ(ah, AR_TSF_L32);
3733 }
3734 EXPORT_SYMBOL(ath9k_hw_gettsf32);
3735
3736 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
3737                                           void (*trigger)(void *),
3738                                           void (*overflow)(void *),
3739                                           void *arg,
3740                                           u8 timer_index)
3741 {
3742         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3743         struct ath_gen_timer *timer;
3744
3745         timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
3746
3747         if (timer == NULL) {
3748                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
3749                           "Failed to allocate memory"
3750                           "for hw timer[%d]\n", timer_index);
3751                 return NULL;
3752         }
3753
3754         /* allocate a hardware generic timer slot */
3755         timer_table->timers[timer_index] = timer;
3756         timer->index = timer_index;
3757         timer->trigger = trigger;
3758         timer->overflow = overflow;
3759         timer->arg = arg;
3760
3761         return timer;
3762 }
3763 EXPORT_SYMBOL(ath_gen_timer_alloc);
3764
3765 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
3766                               struct ath_gen_timer *timer,
3767                               u32 timer_next,
3768                               u32 timer_period)
3769 {
3770         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3771         u32 tsf;
3772
3773         BUG_ON(!timer_period);
3774
3775         set_bit(timer->index, &timer_table->timer_mask.timer_bits);
3776
3777         tsf = ath9k_hw_gettsf32(ah);
3778
3779         ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
3780                   "curent tsf %x period %x"
3781                   "timer_next %x\n", tsf, timer_period, timer_next);
3782
3783         /*
3784          * Pull timer_next forward if the current TSF already passed it
3785          * because of software latency
3786          */
3787         if (timer_next < tsf)
3788                 timer_next = tsf + timer_period;
3789
3790         /*
3791          * Program generic timer registers
3792          */
3793         REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
3794                  timer_next);
3795         REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
3796                   timer_period);
3797         REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3798                     gen_tmr_configuration[timer->index].mode_mask);
3799
3800         /* Enable both trigger and thresh interrupt masks */
3801         REG_SET_BIT(ah, AR_IMR_S5,
3802                 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3803                 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3804 }
3805 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
3806
3807 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
3808 {
3809         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3810
3811         if ((timer->index < AR_FIRST_NDP_TIMER) ||
3812                 (timer->index >= ATH_MAX_GEN_TIMER)) {
3813                 return;
3814         }
3815
3816         /* Clear generic timer enable bits. */
3817         REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3818                         gen_tmr_configuration[timer->index].mode_mask);
3819
3820         /* Disable both trigger and thresh interrupt masks */
3821         REG_CLR_BIT(ah, AR_IMR_S5,
3822                 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3823                 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3824
3825         clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
3826 }
3827 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
3828
3829 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
3830 {
3831         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3832
3833         /* free the hardware generic timer slot */
3834         timer_table->timers[timer->index] = NULL;
3835         kfree(timer);
3836 }
3837 EXPORT_SYMBOL(ath_gen_timer_free);
3838
3839 /*
3840  * Generic Timer Interrupts handling
3841  */
3842 void ath_gen_timer_isr(struct ath_hw *ah)
3843 {
3844         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3845         struct ath_gen_timer *timer;
3846         struct ath_common *common = ath9k_hw_common(ah);
3847         u32 trigger_mask, thresh_mask, index;
3848
3849         /* get hardware generic timer interrupt status */
3850         trigger_mask = ah->intr_gen_timer_trigger;
3851         thresh_mask = ah->intr_gen_timer_thresh;
3852         trigger_mask &= timer_table->timer_mask.val;
3853         thresh_mask &= timer_table->timer_mask.val;
3854
3855         trigger_mask &= ~thresh_mask;
3856
3857         while (thresh_mask) {
3858                 index = rightmost_index(timer_table, &thresh_mask);
3859                 timer = timer_table->timers[index];
3860                 BUG_ON(!timer);
3861                 ath_print(common, ATH_DBG_HWTIMER,
3862                           "TSF overflow for Gen timer %d\n", index);
3863                 timer->overflow(timer->arg);
3864         }
3865
3866         while (trigger_mask) {
3867                 index = rightmost_index(timer_table, &trigger_mask);
3868                 timer = timer_table->timers[index];
3869                 BUG_ON(!timer);
3870                 ath_print(common, ATH_DBG_HWTIMER,
3871                           "Gen timer[%d] trigger\n", index);
3872                 timer->trigger(timer->arg);
3873         }
3874 }
3875 EXPORT_SYMBOL(ath_gen_timer_isr);
3876
3877 /********/
3878 /* HTC  */
3879 /********/
3880
3881 void ath9k_hw_htc_resetinit(struct ath_hw *ah)
3882 {
3883         ah->htc_reset_init = true;
3884 }
3885 EXPORT_SYMBOL(ath9k_hw_htc_resetinit);
3886
3887 static struct {
3888         u32 version;
3889         const char * name;
3890 } ath_mac_bb_names[] = {
3891         /* Devices with external radios */
3892         { AR_SREV_VERSION_5416_PCI,     "5416" },
3893         { AR_SREV_VERSION_5416_PCIE,    "5418" },
3894         { AR_SREV_VERSION_9100,         "9100" },
3895         { AR_SREV_VERSION_9160,         "9160" },
3896         /* Single-chip solutions */
3897         { AR_SREV_VERSION_9280,         "9280" },
3898         { AR_SREV_VERSION_9285,         "9285" },
3899         { AR_SREV_VERSION_9287,         "9287" },
3900         { AR_SREV_VERSION_9271,         "9271" },
3901 };
3902
3903 /* For devices with external radios */
3904 static struct {
3905         u16 version;
3906         const char * name;
3907 } ath_rf_names[] = {
3908         { 0,                            "5133" },
3909         { AR_RAD5133_SREV_MAJOR,        "5133" },
3910         { AR_RAD5122_SREV_MAJOR,        "5122" },
3911         { AR_RAD2133_SREV_MAJOR,        "2133" },
3912         { AR_RAD2122_SREV_MAJOR,        "2122" }
3913 };
3914
3915 /*
3916  * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3917  */
3918 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
3919 {
3920         int i;
3921
3922         for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3923                 if (ath_mac_bb_names[i].version == mac_bb_version) {
3924                         return ath_mac_bb_names[i].name;
3925                 }
3926         }
3927
3928         return "????";
3929 }
3930
3931 /*
3932  * Return the RF name. "????" is returned if the RF is unknown.
3933  * Used for devices with external radios.
3934  */
3935 static const char *ath9k_hw_rf_name(u16 rf_version)
3936 {
3937         int i;
3938
3939         for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3940                 if (ath_rf_names[i].version == rf_version) {
3941                         return ath_rf_names[i].name;
3942                 }
3943         }
3944
3945         return "????";
3946 }
3947
3948 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3949 {
3950         int used;
3951
3952         /* chipsets >= AR9280 are single-chip */
3953         if (AR_SREV_9280_10_OR_LATER(ah)) {
3954                 used = snprintf(hw_name, len,
3955                                "Atheros AR%s Rev:%x",
3956                                ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3957                                ah->hw_version.macRev);
3958         }
3959         else {
3960                 used = snprintf(hw_name, len,
3961                                "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3962                                ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3963                                ah->hw_version.macRev,
3964                                ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
3965                                                 AR_RADIO_SREV_MAJOR)),
3966                                ah->hw_version.phyRev);
3967         }
3968
3969         hw_name[used] = '\0';
3970 }
3971 EXPORT_SYMBOL(ath9k_hw_name);
3972
3973 /* Sets up the AR5008/AR9001/AR9002 hardware familiy callbacks */
3974 static void ar9002_hw_attach_ops(struct ath_hw *ah)
3975 {
3976         struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
3977         struct ath_hw_ops *ops = ath9k_hw_ops(ah);
3978
3979         priv_ops->init_cal_settings = ar9002_hw_init_cal_settings;
3980         priv_ops->init_mode_regs = ar9002_hw_init_mode_regs;
3981         priv_ops->macversion_supported = ar9002_hw_macversion_supported;
3982
3983         ops->config_pci_powersave = ar9002_hw_configpcipowersave;
3984 }