2 * Copyright (c) 2008-2010 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include <linux/slab.h>
19 #include <asm/unaligned.h>
24 #include "ar9003_mac.h"
26 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
28 MODULE_AUTHOR("Atheros Communications");
29 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
30 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
31 MODULE_LICENSE("Dual BSD/GPL");
33 static int __init ath9k_init(void)
37 module_init(ath9k_init);
39 static void __exit ath9k_exit(void)
43 module_exit(ath9k_exit);
45 /* Private hardware callbacks */
47 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
49 ath9k_hw_private_ops(ah)->init_cal_settings(ah);
52 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
54 ath9k_hw_private_ops(ah)->init_mode_regs(ah);
57 static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
58 struct ath9k_channel *chan)
60 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
63 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
65 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
68 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
71 static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah)
73 /* You will not have this callback if using the old ANI */
74 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs)
77 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah);
80 /********************/
81 /* Helper Functions */
82 /********************/
84 static void ath9k_hw_set_clockrate(struct ath_hw *ah)
86 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
87 struct ath_common *common = ath9k_hw_common(ah);
88 unsigned int clockrate;
90 if (!ah->curchan) /* should really check for CCK instead */
91 clockrate = ATH9K_CLOCK_RATE_CCK;
92 else if (conf->channel->band == IEEE80211_BAND_2GHZ)
93 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
94 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
95 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
97 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
99 if (conf_is_ht40(conf))
102 common->clockrate = clockrate;
105 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
107 struct ath_common *common = ath9k_hw_common(ah);
109 return usecs * common->clockrate;
112 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
116 BUG_ON(timeout < AH_TIME_QUANTUM);
118 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
119 if ((REG_READ(ah, reg) & mask) == val)
122 udelay(AH_TIME_QUANTUM);
125 ath_dbg(ath9k_hw_common(ah), ATH_DBG_ANY,
126 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
127 timeout, reg, REG_READ(ah, reg), mask, val);
131 EXPORT_SYMBOL(ath9k_hw_wait);
133 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
138 for (i = 0, retval = 0; i < n; i++) {
139 retval = (retval << 1) | (val & 1);
145 bool ath9k_get_channel_edges(struct ath_hw *ah,
149 struct ath9k_hw_capabilities *pCap = &ah->caps;
151 if (flags & CHANNEL_5GHZ) {
152 *low = pCap->low_5ghz_chan;
153 *high = pCap->high_5ghz_chan;
156 if ((flags & CHANNEL_2GHZ)) {
157 *low = pCap->low_2ghz_chan;
158 *high = pCap->high_2ghz_chan;
164 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
166 u32 frameLen, u16 rateix,
169 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
175 case WLAN_RC_PHY_CCK:
176 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
179 numBits = frameLen << 3;
180 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
182 case WLAN_RC_PHY_OFDM:
183 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
184 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
185 numBits = OFDM_PLCP_BITS + (frameLen << 3);
186 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
187 txTime = OFDM_SIFS_TIME_QUARTER
188 + OFDM_PREAMBLE_TIME_QUARTER
189 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
190 } else if (ah->curchan &&
191 IS_CHAN_HALF_RATE(ah->curchan)) {
192 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
193 numBits = OFDM_PLCP_BITS + (frameLen << 3);
194 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
195 txTime = OFDM_SIFS_TIME_HALF +
196 OFDM_PREAMBLE_TIME_HALF
197 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
199 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
200 numBits = OFDM_PLCP_BITS + (frameLen << 3);
201 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
202 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
203 + (numSymbols * OFDM_SYMBOL_TIME);
207 ath_err(ath9k_hw_common(ah),
208 "Unknown phy %u (rate ix %u)\n", phy, rateix);
215 EXPORT_SYMBOL(ath9k_hw_computetxtime);
217 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
218 struct ath9k_channel *chan,
219 struct chan_centers *centers)
223 if (!IS_CHAN_HT40(chan)) {
224 centers->ctl_center = centers->ext_center =
225 centers->synth_center = chan->channel;
229 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
230 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
231 centers->synth_center =
232 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
235 centers->synth_center =
236 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
240 centers->ctl_center =
241 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
242 /* 25 MHz spacing is supported by hw but not on upper layers */
243 centers->ext_center =
244 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
251 static void ath9k_hw_read_revisions(struct ath_hw *ah)
255 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
258 val = REG_READ(ah, AR_SREV);
259 ah->hw_version.macVersion =
260 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
261 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
262 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
264 if (!AR_SREV_9100(ah))
265 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
267 ah->hw_version.macRev = val & AR_SREV_REVISION;
269 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
270 ah->is_pciexpress = true;
274 /************************************/
275 /* HW Attach, Detach, Init Routines */
276 /************************************/
278 static void ath9k_hw_disablepcie(struct ath_hw *ah)
280 if (!AR_SREV_5416(ah))
283 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
284 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
285 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
286 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
287 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
288 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
289 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
290 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
291 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
293 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
296 /* This should work for all families including legacy */
297 static bool ath9k_hw_chip_test(struct ath_hw *ah)
299 struct ath_common *common = ath9k_hw_common(ah);
300 u32 regAddr[2] = { AR_STA_ID0 };
302 static const u32 patternData[4] = {
303 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
307 if (!AR_SREV_9300_20_OR_LATER(ah)) {
309 regAddr[1] = AR_PHY_BASE + (8 << 2);
313 for (i = 0; i < loop_max; i++) {
314 u32 addr = regAddr[i];
317 regHold[i] = REG_READ(ah, addr);
318 for (j = 0; j < 0x100; j++) {
319 wrData = (j << 16) | j;
320 REG_WRITE(ah, addr, wrData);
321 rdData = REG_READ(ah, addr);
322 if (rdData != wrData) {
324 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
325 addr, wrData, rdData);
329 for (j = 0; j < 4; j++) {
330 wrData = patternData[j];
331 REG_WRITE(ah, addr, wrData);
332 rdData = REG_READ(ah, addr);
333 if (wrData != rdData) {
335 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
336 addr, wrData, rdData);
340 REG_WRITE(ah, regAddr[i], regHold[i]);
347 static void ath9k_hw_init_config(struct ath_hw *ah)
351 ah->config.dma_beacon_response_time = 2;
352 ah->config.sw_beacon_response_time = 10;
353 ah->config.additional_swba_backoff = 0;
354 ah->config.ack_6mb = 0x0;
355 ah->config.cwm_ignore_extcca = 0;
356 ah->config.pcie_powersave_enable = 0;
357 ah->config.pcie_clock_req = 0;
358 ah->config.pcie_waen = 0;
359 ah->config.analog_shiftreg = 1;
360 ah->config.enable_ani = true;
362 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
363 ah->config.spurchans[i][0] = AR_NO_SPUR;
364 ah->config.spurchans[i][1] = AR_NO_SPUR;
367 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
368 ah->config.ht_enable = 1;
370 ah->config.ht_enable = 0;
372 ah->config.rx_intr_mitigation = true;
373 ah->config.pcieSerDesWrite = true;
376 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
377 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
378 * This means we use it for all AR5416 devices, and the few
379 * minor PCI AR9280 devices out there.
381 * Serialization is required because these devices do not handle
382 * well the case of two concurrent reads/writes due to the latency
383 * involved. During one read/write another read/write can be issued
384 * on another CPU while the previous read/write may still be working
385 * on our hardware, if we hit this case the hardware poops in a loop.
386 * We prevent this by serializing reads and writes.
388 * This issue is not present on PCI-Express devices or pre-AR5416
389 * devices (legacy, 802.11abg).
391 if (num_possible_cpus() > 1)
392 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
395 static void ath9k_hw_init_defaults(struct ath_hw *ah)
397 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
399 regulatory->country_code = CTRY_DEFAULT;
400 regulatory->power_limit = MAX_RATE_POWER;
401 regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
403 ah->hw_version.magic = AR5416_MAGIC;
404 ah->hw_version.subvendorid = 0;
407 ah->sta_id1_defaults =
408 AR_STA_ID1_CRPT_MIC_ENABLE |
409 AR_STA_ID1_MCAST_KSRCH;
410 ah->enable_32kHz_clock = DONT_USE_32KHZ;
412 ah->globaltxtimeout = (u32) -1;
413 ah->power_mode = ATH9K_PM_UNDEFINED;
416 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
418 struct ath_common *common = ath9k_hw_common(ah);
422 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
425 for (i = 0; i < 3; i++) {
426 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
428 common->macaddr[2 * i] = eeval >> 8;
429 common->macaddr[2 * i + 1] = eeval & 0xff;
431 if (sum == 0 || sum == 0xffff * 3)
432 return -EADDRNOTAVAIL;
437 static int ath9k_hw_post_init(struct ath_hw *ah)
441 if (!AR_SREV_9271(ah)) {
442 if (!ath9k_hw_chip_test(ah))
446 if (!AR_SREV_9300_20_OR_LATER(ah)) {
447 ecode = ar9002_hw_rf_claim(ah);
452 ecode = ath9k_hw_eeprom_init(ah);
456 ath_dbg(ath9k_hw_common(ah), ATH_DBG_CONFIG,
457 "Eeprom VER: %d, REV: %d\n",
458 ah->eep_ops->get_eeprom_ver(ah),
459 ah->eep_ops->get_eeprom_rev(ah));
461 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
463 ath_err(ath9k_hw_common(ah),
464 "Failed allocating banks for external radio\n");
465 ath9k_hw_rf_free_ext_banks(ah);
469 if (!AR_SREV_9100(ah)) {
470 ath9k_hw_ani_setup(ah);
471 ath9k_hw_ani_init(ah);
477 static void ath9k_hw_attach_ops(struct ath_hw *ah)
479 if (AR_SREV_9300_20_OR_LATER(ah))
480 ar9003_hw_attach_ops(ah);
482 ar9002_hw_attach_ops(ah);
485 /* Called for all hardware families */
486 static int __ath9k_hw_init(struct ath_hw *ah)
488 struct ath_common *common = ath9k_hw_common(ah);
491 if (ah->hw_version.devid == AR5416_AR9100_DEVID)
492 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
494 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
495 ath_err(common, "Couldn't reset chip\n");
499 ath9k_hw_init_defaults(ah);
500 ath9k_hw_init_config(ah);
502 ath9k_hw_attach_ops(ah);
504 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
505 ath_err(common, "Couldn't wakeup chip\n");
509 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
510 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
511 ((AR_SREV_9160(ah) || AR_SREV_9280(ah)) &&
512 !ah->is_pciexpress)) {
513 ah->config.serialize_regmode =
516 ah->config.serialize_regmode =
521 ath_dbg(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
522 ah->config.serialize_regmode);
524 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
525 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
527 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
529 switch (ah->hw_version.macVersion) {
530 case AR_SREV_VERSION_5416_PCI:
531 case AR_SREV_VERSION_5416_PCIE:
532 case AR_SREV_VERSION_9160:
533 case AR_SREV_VERSION_9100:
534 case AR_SREV_VERSION_9280:
535 case AR_SREV_VERSION_9285:
536 case AR_SREV_VERSION_9287:
537 case AR_SREV_VERSION_9271:
538 case AR_SREV_VERSION_9300:
539 case AR_SREV_VERSION_9485:
543 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
544 ah->hw_version.macVersion, ah->hw_version.macRev);
548 if (AR_SREV_9271(ah) || AR_SREV_9100(ah))
549 ah->is_pciexpress = false;
551 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
552 ath9k_hw_init_cal_settings(ah);
554 ah->ani_function = ATH9K_ANI_ALL;
555 if (AR_SREV_9280_20_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
556 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
557 if (!AR_SREV_9300_20_OR_LATER(ah))
558 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
560 ath9k_hw_init_mode_regs(ah);
563 * Read back AR_WA into a permanent copy and set bits 14 and 17.
564 * We need to do this to avoid RMW of this register. We cannot
565 * read the reg when chip is asleep.
567 ah->WARegVal = REG_READ(ah, AR_WA);
568 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
569 AR_WA_ASPM_TIMER_BASED_DISABLE);
571 if (ah->is_pciexpress)
572 ath9k_hw_configpcipowersave(ah, 0, 0);
574 ath9k_hw_disablepcie(ah);
576 if (!AR_SREV_9300_20_OR_LATER(ah))
577 ar9002_hw_cck_chan14_spread(ah);
579 r = ath9k_hw_post_init(ah);
583 ath9k_hw_init_mode_gain_regs(ah);
584 r = ath9k_hw_fill_cap_info(ah);
588 r = ath9k_hw_init_macaddr(ah);
590 ath_err(common, "Failed to initialize MAC address\n");
594 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
595 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
597 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
599 ah->bb_watchdog_timeout_ms = 25;
601 common->state = ATH_HW_INITIALIZED;
606 int ath9k_hw_init(struct ath_hw *ah)
609 struct ath_common *common = ath9k_hw_common(ah);
611 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
612 switch (ah->hw_version.devid) {
613 case AR5416_DEVID_PCI:
614 case AR5416_DEVID_PCIE:
615 case AR5416_AR9100_DEVID:
616 case AR9160_DEVID_PCI:
617 case AR9280_DEVID_PCI:
618 case AR9280_DEVID_PCIE:
619 case AR9285_DEVID_PCIE:
620 case AR9287_DEVID_PCI:
621 case AR9287_DEVID_PCIE:
622 case AR2427_DEVID_PCIE:
623 case AR9300_DEVID_PCIE:
624 case AR9300_DEVID_AR9485_PCIE:
627 if (common->bus_ops->ath_bus_type == ATH_USB)
629 ath_err(common, "Hardware device ID 0x%04x not supported\n",
630 ah->hw_version.devid);
634 ret = __ath9k_hw_init(ah);
637 "Unable to initialize hardware; initialization status: %d\n",
644 EXPORT_SYMBOL(ath9k_hw_init);
646 static void ath9k_hw_init_qos(struct ath_hw *ah)
648 ENABLE_REGWRITE_BUFFER(ah);
650 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
651 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
653 REG_WRITE(ah, AR_QOS_NO_ACK,
654 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
655 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
656 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
658 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
659 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
660 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
661 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
662 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
664 REGWRITE_BUFFER_FLUSH(ah);
667 static void ath9k_hw_init_pll(struct ath_hw *ah,
668 struct ath9k_channel *chan)
672 if (AR_SREV_9485(ah))
673 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, 0x886666);
675 pll = ath9k_hw_compute_pll_control(ah, chan);
677 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
679 /* Switch the core clock for ar9271 to 117Mhz */
680 if (AR_SREV_9271(ah)) {
682 REG_WRITE(ah, 0x50040, 0x304);
685 udelay(RTC_PLL_SETTLE_DELAY);
687 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
690 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
691 enum nl80211_iftype opmode)
693 u32 imr_reg = AR_IMR_TXERR |
699 if (AR_SREV_9300_20_OR_LATER(ah)) {
700 imr_reg |= AR_IMR_RXOK_HP;
701 if (ah->config.rx_intr_mitigation)
702 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
704 imr_reg |= AR_IMR_RXOK_LP;
707 if (ah->config.rx_intr_mitigation)
708 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
710 imr_reg |= AR_IMR_RXOK;
713 if (ah->config.tx_intr_mitigation)
714 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
716 imr_reg |= AR_IMR_TXOK;
718 if (opmode == NL80211_IFTYPE_AP)
719 imr_reg |= AR_IMR_MIB;
721 ENABLE_REGWRITE_BUFFER(ah);
723 REG_WRITE(ah, AR_IMR, imr_reg);
724 ah->imrs2_reg |= AR_IMR_S2_GTT;
725 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
727 if (!AR_SREV_9100(ah)) {
728 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
729 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
730 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
733 REGWRITE_BUFFER_FLUSH(ah);
735 if (AR_SREV_9300_20_OR_LATER(ah)) {
736 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
737 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
738 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
739 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
743 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
745 u32 val = ath9k_hw_mac_to_clks(ah, us);
746 val = min(val, (u32) 0xFFFF);
747 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
750 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
752 u32 val = ath9k_hw_mac_to_clks(ah, us);
753 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
754 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
757 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
759 u32 val = ath9k_hw_mac_to_clks(ah, us);
760 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
761 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
764 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
767 ath_dbg(ath9k_hw_common(ah), ATH_DBG_XMIT,
768 "bad global tx timeout %u\n", tu);
769 ah->globaltxtimeout = (u32) -1;
772 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
773 ah->globaltxtimeout = tu;
778 void ath9k_hw_init_global_settings(struct ath_hw *ah)
780 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
785 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
788 if (ah->misc_mode != 0)
789 REG_WRITE(ah, AR_PCU_MISC,
790 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
792 if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
797 /* As defined by IEEE 802.11-2007 17.3.8.6 */
798 slottime = ah->slottime + 3 * ah->coverage_class;
799 acktimeout = slottime + sifstime;
802 * Workaround for early ACK timeouts, add an offset to match the
803 * initval's 64us ack timeout value.
804 * This was initially only meant to work around an issue with delayed
805 * BA frames in some implementations, but it has been found to fix ACK
806 * timeout issues in other cases as well.
808 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
809 acktimeout += 64 - sifstime - ah->slottime;
811 ath9k_hw_setslottime(ah, ah->slottime);
812 ath9k_hw_set_ack_timeout(ah, acktimeout);
813 ath9k_hw_set_cts_timeout(ah, acktimeout);
814 if (ah->globaltxtimeout != (u32) -1)
815 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
817 EXPORT_SYMBOL(ath9k_hw_init_global_settings);
819 void ath9k_hw_deinit(struct ath_hw *ah)
821 struct ath_common *common = ath9k_hw_common(ah);
823 if (common->state < ATH_HW_INITIALIZED)
826 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
829 ath9k_hw_rf_free_ext_banks(ah);
831 EXPORT_SYMBOL(ath9k_hw_deinit);
837 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
839 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
843 else if (IS_CHAN_G(chan))
851 /****************************************/
852 /* Reset and Channel Switching Routines */
853 /****************************************/
855 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
857 struct ath_common *common = ath9k_hw_common(ah);
860 ENABLE_REGWRITE_BUFFER(ah);
863 * set AHB_MODE not to do cacheline prefetches
865 if (!AR_SREV_9300_20_OR_LATER(ah)) {
866 regval = REG_READ(ah, AR_AHB_MODE);
867 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
871 * let mac dma reads be in 128 byte chunks
873 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
874 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
876 REGWRITE_BUFFER_FLUSH(ah);
879 * Restore TX Trigger Level to its pre-reset value.
880 * The initial value depends on whether aggregation is enabled, and is
881 * adjusted whenever underruns are detected.
883 if (!AR_SREV_9300_20_OR_LATER(ah))
884 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
886 ENABLE_REGWRITE_BUFFER(ah);
889 * let mac dma writes be in 128 byte chunks
891 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
892 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
895 * Setup receive FIFO threshold to hold off TX activities
897 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
899 if (AR_SREV_9300_20_OR_LATER(ah)) {
900 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
901 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
903 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
904 ah->caps.rx_status_len);
908 * reduce the number of usable entries in PCU TXBUF to avoid
909 * wrap around issues.
911 if (AR_SREV_9285(ah)) {
912 /* For AR9285 the number of Fifos are reduced to half.
913 * So set the usable tx buf size also to half to
914 * avoid data/delimiter underruns
916 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
917 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
918 } else if (!AR_SREV_9271(ah)) {
919 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
920 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
923 REGWRITE_BUFFER_FLUSH(ah);
925 if (AR_SREV_9300_20_OR_LATER(ah))
926 ath9k_hw_reset_txstatus_ring(ah);
929 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
933 val = REG_READ(ah, AR_STA_ID1);
934 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
936 case NL80211_IFTYPE_AP:
937 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
938 | AR_STA_ID1_KSRCH_MODE);
939 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
941 case NL80211_IFTYPE_ADHOC:
942 case NL80211_IFTYPE_MESH_POINT:
943 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
944 | AR_STA_ID1_KSRCH_MODE);
945 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
947 case NL80211_IFTYPE_STATION:
948 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
951 if (ah->is_monitoring)
952 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
957 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
958 u32 *coef_mantissa, u32 *coef_exponent)
960 u32 coef_exp, coef_man;
962 for (coef_exp = 31; coef_exp > 0; coef_exp--)
963 if ((coef_scaled >> coef_exp) & 0x1)
966 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
968 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
970 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
971 *coef_exponent = coef_exp - 16;
974 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
979 if (AR_SREV_9100(ah)) {
980 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
981 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
982 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
983 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
984 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
987 ENABLE_REGWRITE_BUFFER(ah);
989 if (AR_SREV_9300_20_OR_LATER(ah)) {
990 REG_WRITE(ah, AR_WA, ah->WARegVal);
994 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
995 AR_RTC_FORCE_WAKE_ON_INT);
997 if (AR_SREV_9100(ah)) {
998 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
999 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1001 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1003 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1004 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1006 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1009 if (!AR_SREV_9300_20_OR_LATER(ah))
1011 REG_WRITE(ah, AR_RC, val);
1013 } else if (!AR_SREV_9300_20_OR_LATER(ah))
1014 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1016 rst_flags = AR_RTC_RC_MAC_WARM;
1017 if (type == ATH9K_RESET_COLD)
1018 rst_flags |= AR_RTC_RC_MAC_COLD;
1021 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1023 REGWRITE_BUFFER_FLUSH(ah);
1027 REG_WRITE(ah, AR_RTC_RC, 0);
1028 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1029 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
1030 "RTC stuck in MAC reset\n");
1034 if (!AR_SREV_9100(ah))
1035 REG_WRITE(ah, AR_RC, 0);
1037 if (AR_SREV_9100(ah))
1043 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1045 ENABLE_REGWRITE_BUFFER(ah);
1047 if (AR_SREV_9300_20_OR_LATER(ah)) {
1048 REG_WRITE(ah, AR_WA, ah->WARegVal);
1052 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1053 AR_RTC_FORCE_WAKE_ON_INT);
1055 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1056 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1058 REG_WRITE(ah, AR_RTC_RESET, 0);
1061 REGWRITE_BUFFER_FLUSH(ah);
1063 if (!AR_SREV_9300_20_OR_LATER(ah))
1066 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1067 REG_WRITE(ah, AR_RC, 0);
1069 REG_WRITE(ah, AR_RTC_RESET, 1);
1071 if (!ath9k_hw_wait(ah,
1076 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
1077 "RTC not waking up\n");
1081 ath9k_hw_read_revisions(ah);
1083 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1086 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1088 if (AR_SREV_9300_20_OR_LATER(ah)) {
1089 REG_WRITE(ah, AR_WA, ah->WARegVal);
1093 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1094 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1097 case ATH9K_RESET_POWER_ON:
1098 return ath9k_hw_set_reset_power_on(ah);
1099 case ATH9K_RESET_WARM:
1100 case ATH9K_RESET_COLD:
1101 return ath9k_hw_set_reset(ah, type);
1107 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1108 struct ath9k_channel *chan)
1110 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1111 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1113 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1116 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1119 ah->chip_fullsleep = false;
1120 ath9k_hw_init_pll(ah, chan);
1121 ath9k_hw_set_rfmode(ah, chan);
1126 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1127 struct ath9k_channel *chan)
1129 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1130 struct ath_common *common = ath9k_hw_common(ah);
1131 struct ieee80211_channel *channel = chan->chan;
1135 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1136 if (ath9k_hw_numtxpending(ah, qnum)) {
1137 ath_dbg(common, ATH_DBG_QUEUE,
1138 "Transmit frames pending on queue %d\n", qnum);
1143 if (!ath9k_hw_rfbus_req(ah)) {
1144 ath_err(common, "Could not kill baseband RX\n");
1148 ath9k_hw_set_channel_regs(ah, chan);
1150 r = ath9k_hw_rf_set_freq(ah, chan);
1152 ath_err(common, "Failed to set channel\n");
1155 ath9k_hw_set_clockrate(ah);
1157 ah->eep_ops->set_txpower(ah, chan,
1158 ath9k_regd_get_ctl(regulatory, chan),
1159 channel->max_antenna_gain * 2,
1160 channel->max_power * 2,
1161 min((u32) MAX_RATE_POWER,
1162 (u32) regulatory->power_limit), false);
1164 ath9k_hw_rfbus_done(ah);
1166 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1167 ath9k_hw_set_delta_slope(ah, chan);
1169 ath9k_hw_spur_mitigate_freq(ah, chan);
1174 bool ath9k_hw_check_alive(struct ath_hw *ah)
1179 if (AR_SREV_9285_12_OR_LATER(ah))
1183 reg = REG_READ(ah, AR_OBS_BUS_1);
1185 if ((reg & 0x7E7FFFEF) == 0x00702400)
1188 switch (reg & 0x7E000B00) {
1196 } while (count-- > 0);
1200 EXPORT_SYMBOL(ath9k_hw_check_alive);
1202 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1203 struct ath9k_hw_cal_data *caldata, bool bChannelChange)
1205 struct ath_common *common = ath9k_hw_common(ah);
1207 struct ath9k_channel *curchan = ah->curchan;
1213 ah->txchainmask = common->tx_chainmask;
1214 ah->rxchainmask = common->rx_chainmask;
1216 if (!ah->chip_fullsleep) {
1217 ath9k_hw_abortpcurecv(ah);
1218 if (!ath9k_hw_stopdmarecv(ah)) {
1219 ath_dbg(common, ATH_DBG_XMIT,
1220 "Failed to stop receive dma\n");
1221 bChannelChange = false;
1225 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1228 if (curchan && !ah->chip_fullsleep)
1229 ath9k_hw_getnf(ah, curchan);
1231 ah->caldata = caldata;
1233 (chan->channel != caldata->channel ||
1234 (chan->channelFlags & ~CHANNEL_CW_INT) !=
1235 (caldata->channelFlags & ~CHANNEL_CW_INT))) {
1236 /* Operating channel changed, reset channel calibration data */
1237 memset(caldata, 0, sizeof(*caldata));
1238 ath9k_init_nfcal_hist_buffer(ah, chan);
1241 if (bChannelChange &&
1242 (ah->chip_fullsleep != true) &&
1243 (ah->curchan != NULL) &&
1244 (chan->channel != ah->curchan->channel) &&
1245 ((chan->channelFlags & CHANNEL_ALL) ==
1246 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
1247 (!AR_SREV_9280(ah) || AR_DEVID_7010(ah))) {
1249 if (ath9k_hw_channel_change(ah, chan)) {
1250 ath9k_hw_loadnf(ah, ah->curchan);
1251 ath9k_hw_start_nfcal(ah, true);
1252 if (AR_SREV_9271(ah))
1253 ar9002_hw_load_ani_reg(ah, chan);
1258 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1259 if (saveDefAntenna == 0)
1262 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1264 /* For chips on which RTC reset is done, save TSF before it gets cleared */
1265 if (AR_SREV_9100(ah) ||
1266 (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)))
1267 tsf = ath9k_hw_gettsf64(ah);
1269 saveLedState = REG_READ(ah, AR_CFG_LED) &
1270 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1271 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1273 ath9k_hw_mark_phy_inactive(ah);
1275 ah->paprd_table_write_done = false;
1277 /* Only required on the first reset */
1278 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1280 AR9271_RESET_POWER_DOWN_CONTROL,
1281 AR9271_RADIO_RF_RST);
1285 if (!ath9k_hw_chip_reset(ah, chan)) {
1286 ath_err(common, "Chip reset failed\n");
1290 /* Only required on the first reset */
1291 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1292 ah->htc_reset_init = false;
1294 AR9271_RESET_POWER_DOWN_CONTROL,
1295 AR9271_GATE_MAC_CTL);
1301 ath9k_hw_settsf64(ah, tsf);
1303 if (AR_SREV_9280_20_OR_LATER(ah))
1304 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1306 if (!AR_SREV_9300_20_OR_LATER(ah))
1307 ar9002_hw_enable_async_fifo(ah);
1309 r = ath9k_hw_process_ini(ah, chan);
1314 * Some AR91xx SoC devices frequently fail to accept TSF writes
1315 * right after the chip reset. When that happens, write a new
1316 * value after the initvals have been applied, with an offset
1317 * based on measured time difference
1319 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
1321 ath9k_hw_settsf64(ah, tsf);
1324 /* Setup MFP options for CCMP */
1325 if (AR_SREV_9280_20_OR_LATER(ah)) {
1326 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1327 * frames when constructing CCMP AAD. */
1328 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1330 ah->sw_mgmt_crypto = false;
1331 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1332 /* Disable hardware crypto for management frames */
1333 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1334 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1335 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1336 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1337 ah->sw_mgmt_crypto = true;
1339 ah->sw_mgmt_crypto = true;
1341 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1342 ath9k_hw_set_delta_slope(ah, chan);
1344 ath9k_hw_spur_mitigate_freq(ah, chan);
1345 ah->eep_ops->set_board_values(ah, chan);
1347 ath9k_hw_set_operating_mode(ah, ah->opmode);
1349 ENABLE_REGWRITE_BUFFER(ah);
1351 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1352 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
1354 | AR_STA_ID1_RTS_USE_DEF
1356 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
1357 | ah->sta_id1_defaults);
1358 ath_hw_setbssidmask(common);
1359 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1360 ath9k_hw_write_associd(ah);
1361 REG_WRITE(ah, AR_ISR, ~0);
1362 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1364 REGWRITE_BUFFER_FLUSH(ah);
1366 r = ath9k_hw_rf_set_freq(ah, chan);
1370 ath9k_hw_set_clockrate(ah);
1372 ENABLE_REGWRITE_BUFFER(ah);
1374 for (i = 0; i < AR_NUM_DCU; i++)
1375 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1377 REGWRITE_BUFFER_FLUSH(ah);
1380 for (i = 0; i < ah->caps.total_queues; i++)
1381 ath9k_hw_resettxqueue(ah, i);
1383 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
1384 ath9k_hw_ani_cache_ini_regs(ah);
1385 ath9k_hw_init_qos(ah);
1387 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1388 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
1390 ath9k_hw_init_global_settings(ah);
1392 if (!AR_SREV_9300_20_OR_LATER(ah)) {
1393 ar9002_hw_update_async_fifo(ah);
1394 ar9002_hw_enable_wep_aggregation(ah);
1397 REG_WRITE(ah, AR_STA_ID1,
1398 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
1400 ath9k_hw_set_dma(ah);
1402 REG_WRITE(ah, AR_OBS, 8);
1404 if (ah->config.rx_intr_mitigation) {
1405 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1406 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1409 if (ah->config.tx_intr_mitigation) {
1410 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1411 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1414 ath9k_hw_init_bb(ah, chan);
1416 if (!ath9k_hw_init_cal(ah, chan))
1419 ENABLE_REGWRITE_BUFFER(ah);
1421 ath9k_hw_restore_chainmask(ah);
1422 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1424 REGWRITE_BUFFER_FLUSH(ah);
1427 * For big endian systems turn on swapping for descriptors
1429 if (AR_SREV_9100(ah)) {
1431 mask = REG_READ(ah, AR_CFG);
1432 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1433 ath_dbg(common, ATH_DBG_RESET,
1434 "CFG Byte Swap Set 0x%x\n", mask);
1437 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1438 REG_WRITE(ah, AR_CFG, mask);
1439 ath_dbg(common, ATH_DBG_RESET,
1440 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
1443 if (common->bus_ops->ath_bus_type == ATH_USB) {
1444 /* Configure AR9271 target WLAN */
1445 if (AR_SREV_9271(ah))
1446 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1448 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1452 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1456 if (ah->btcoex_hw.enabled)
1457 ath9k_hw_btcoex_enable(ah);
1459 if (AR_SREV_9300_20_OR_LATER(ah))
1460 ar9003_hw_bb_watchdog_config(ah);
1464 EXPORT_SYMBOL(ath9k_hw_reset);
1466 /******************************/
1467 /* Power Management (Chipset) */
1468 /******************************/
1471 * Notify Power Mgt is disabled in self-generated frames.
1472 * If requested, force chip to sleep.
1474 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
1476 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1479 * Clear the RTC force wake bit to allow the
1480 * mac to go to sleep.
1482 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1483 AR_RTC_FORCE_WAKE_EN);
1484 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1485 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1487 /* Shutdown chip. Active low */
1488 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
1489 REG_CLR_BIT(ah, (AR_RTC_RESET),
1493 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
1494 if (AR_SREV_9300_20_OR_LATER(ah))
1495 REG_WRITE(ah, AR_WA,
1496 ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
1500 * Notify Power Management is enabled in self-generating
1501 * frames. If request, set power mode of chip to
1502 * auto/normal. Duration in units of 128us (1/8 TU).
1504 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
1506 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1508 struct ath9k_hw_capabilities *pCap = &ah->caps;
1510 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1511 /* Set WakeOnInterrupt bit; clear ForceWake bit */
1512 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1513 AR_RTC_FORCE_WAKE_ON_INT);
1516 * Clear the RTC force wake bit to allow the
1517 * mac to go to sleep.
1519 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1520 AR_RTC_FORCE_WAKE_EN);
1524 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
1525 if (AR_SREV_9300_20_OR_LATER(ah))
1526 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
1529 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
1534 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
1535 if (AR_SREV_9300_20_OR_LATER(ah)) {
1536 REG_WRITE(ah, AR_WA, ah->WARegVal);
1541 if ((REG_READ(ah, AR_RTC_STATUS) &
1542 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
1543 if (ath9k_hw_set_reset_reg(ah,
1544 ATH9K_RESET_POWER_ON) != true) {
1547 if (!AR_SREV_9300_20_OR_LATER(ah))
1548 ath9k_hw_init_pll(ah, NULL);
1550 if (AR_SREV_9100(ah))
1551 REG_SET_BIT(ah, AR_RTC_RESET,
1554 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1555 AR_RTC_FORCE_WAKE_EN);
1558 for (i = POWER_UP_TIME / 50; i > 0; i--) {
1559 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
1560 if (val == AR_RTC_STATUS_ON)
1563 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1564 AR_RTC_FORCE_WAKE_EN);
1567 ath_err(ath9k_hw_common(ah),
1568 "Failed to wakeup in %uus\n",
1569 POWER_UP_TIME / 20);
1574 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1579 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
1581 struct ath_common *common = ath9k_hw_common(ah);
1582 int status = true, setChip = true;
1583 static const char *modes[] = {
1590 if (ah->power_mode == mode)
1593 ath_dbg(common, ATH_DBG_RESET, "%s -> %s\n",
1594 modes[ah->power_mode], modes[mode]);
1597 case ATH9K_PM_AWAKE:
1598 status = ath9k_hw_set_power_awake(ah, setChip);
1600 case ATH9K_PM_FULL_SLEEP:
1601 ath9k_set_power_sleep(ah, setChip);
1602 ah->chip_fullsleep = true;
1604 case ATH9K_PM_NETWORK_SLEEP:
1605 ath9k_set_power_network_sleep(ah, setChip);
1608 ath_err(common, "Unknown power mode %u\n", mode);
1611 ah->power_mode = mode;
1614 * XXX: If this warning never comes up after a while then
1615 * simply keep the ATH_DBG_WARN_ON_ONCE() but make
1616 * ath9k_hw_setpower() return type void.
1619 if (!(ah->ah_flags & AH_UNPLUGGED))
1620 ATH_DBG_WARN_ON_ONCE(!status);
1624 EXPORT_SYMBOL(ath9k_hw_setpower);
1626 /*******************/
1627 /* Beacon Handling */
1628 /*******************/
1630 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
1634 ENABLE_REGWRITE_BUFFER(ah);
1636 switch (ah->opmode) {
1637 case NL80211_IFTYPE_ADHOC:
1638 case NL80211_IFTYPE_MESH_POINT:
1639 REG_SET_BIT(ah, AR_TXCFG,
1640 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
1641 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
1642 TU_TO_USEC(next_beacon +
1643 (ah->atim_window ? ah->
1645 flags |= AR_NDP_TIMER_EN;
1646 case NL80211_IFTYPE_AP:
1647 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
1648 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
1649 TU_TO_USEC(next_beacon -
1651 dma_beacon_response_time));
1652 REG_WRITE(ah, AR_NEXT_SWBA,
1653 TU_TO_USEC(next_beacon -
1655 sw_beacon_response_time));
1657 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
1660 ath_dbg(ath9k_hw_common(ah), ATH_DBG_BEACON,
1661 "%s: unsupported opmode: %d\n",
1662 __func__, ah->opmode);
1667 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
1668 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
1669 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
1670 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
1672 REGWRITE_BUFFER_FLUSH(ah);
1674 beacon_period &= ~ATH9K_BEACON_ENA;
1675 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
1676 ath9k_hw_reset_tsf(ah);
1679 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
1681 EXPORT_SYMBOL(ath9k_hw_beaconinit);
1683 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
1684 const struct ath9k_beacon_state *bs)
1686 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
1687 struct ath9k_hw_capabilities *pCap = &ah->caps;
1688 struct ath_common *common = ath9k_hw_common(ah);
1690 ENABLE_REGWRITE_BUFFER(ah);
1692 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
1694 REG_WRITE(ah, AR_BEACON_PERIOD,
1695 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1696 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
1697 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1699 REGWRITE_BUFFER_FLUSH(ah);
1701 REG_RMW_FIELD(ah, AR_RSSI_THR,
1702 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
1704 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
1706 if (bs->bs_sleepduration > beaconintval)
1707 beaconintval = bs->bs_sleepduration;
1709 dtimperiod = bs->bs_dtimperiod;
1710 if (bs->bs_sleepduration > dtimperiod)
1711 dtimperiod = bs->bs_sleepduration;
1713 if (beaconintval == dtimperiod)
1714 nextTbtt = bs->bs_nextdtim;
1716 nextTbtt = bs->bs_nexttbtt;
1718 ath_dbg(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
1719 ath_dbg(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
1720 ath_dbg(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
1721 ath_dbg(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
1723 ENABLE_REGWRITE_BUFFER(ah);
1725 REG_WRITE(ah, AR_NEXT_DTIM,
1726 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
1727 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
1729 REG_WRITE(ah, AR_SLEEP1,
1730 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
1731 | AR_SLEEP1_ASSUME_DTIM);
1733 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
1734 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
1736 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
1738 REG_WRITE(ah, AR_SLEEP2,
1739 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
1741 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
1742 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
1744 REGWRITE_BUFFER_FLUSH(ah);
1746 REG_SET_BIT(ah, AR_TIMER_MODE,
1747 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
1750 /* TSF Out of Range Threshold */
1751 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
1753 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
1755 /*******************/
1756 /* HW Capabilities */
1757 /*******************/
1759 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
1761 struct ath9k_hw_capabilities *pCap = &ah->caps;
1762 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1763 struct ath_common *common = ath9k_hw_common(ah);
1764 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
1766 u16 capField = 0, eeval;
1767 u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
1769 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
1770 regulatory->current_rd = eeval;
1772 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
1773 if (AR_SREV_9285_12_OR_LATER(ah))
1774 eeval |= AR9285_RDEXT_DEFAULT;
1775 regulatory->current_rd_ext = eeval;
1777 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
1779 if (ah->opmode != NL80211_IFTYPE_AP &&
1780 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
1781 if (regulatory->current_rd == 0x64 ||
1782 regulatory->current_rd == 0x65)
1783 regulatory->current_rd += 5;
1784 else if (regulatory->current_rd == 0x41)
1785 regulatory->current_rd = 0x43;
1786 ath_dbg(common, ATH_DBG_REGULATORY,
1787 "regdomain mapped to 0x%x\n", regulatory->current_rd);
1790 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
1791 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
1793 "no band has been marked as supported in EEPROM\n");
1797 if (eeval & AR5416_OPFLAGS_11A)
1798 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
1800 if (eeval & AR5416_OPFLAGS_11G)
1801 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
1803 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
1805 * For AR9271 we will temporarilly uses the rx chainmax as read from
1808 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
1809 !(eeval & AR5416_OPFLAGS_11A) &&
1810 !(AR_SREV_9271(ah)))
1811 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
1812 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
1814 /* Use rx_chainmask from EEPROM. */
1815 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
1817 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
1819 /* enable key search for every frame in an aggregate */
1820 if (AR_SREV_9300_20_OR_LATER(ah))
1821 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
1823 pCap->low_2ghz_chan = 2312;
1824 pCap->high_2ghz_chan = 2732;
1826 pCap->low_5ghz_chan = 4920;
1827 pCap->high_5ghz_chan = 6100;
1829 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
1831 if (ah->config.ht_enable)
1832 pCap->hw_caps |= ATH9K_HW_CAP_HT;
1834 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
1836 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
1837 pCap->total_queues =
1838 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
1840 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
1842 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
1843 pCap->keycache_size =
1844 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
1846 pCap->keycache_size = AR_KEYTABLE_SIZE;
1848 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
1849 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
1851 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
1853 if (AR_SREV_9271(ah))
1854 pCap->num_gpio_pins = AR9271_NUM_GPIO;
1855 else if (AR_DEVID_7010(ah))
1856 pCap->num_gpio_pins = AR7010_NUM_GPIO;
1857 else if (AR_SREV_9285_12_OR_LATER(ah))
1858 pCap->num_gpio_pins = AR9285_NUM_GPIO;
1859 else if (AR_SREV_9280_20_OR_LATER(ah))
1860 pCap->num_gpio_pins = AR928X_NUM_GPIO;
1862 pCap->num_gpio_pins = AR_NUM_GPIO;
1864 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
1865 pCap->hw_caps |= ATH9K_HW_CAP_CST;
1866 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
1868 pCap->rts_aggr_limit = (8 * 1024);
1871 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
1873 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1874 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
1875 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
1877 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
1878 ah->rfkill_polarity =
1879 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
1881 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
1884 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
1885 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
1887 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
1889 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
1890 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
1892 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
1894 if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
1896 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
1897 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
1898 AR_EEPROM_EEREGCAP_EN_KK_U2 |
1899 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
1902 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
1903 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
1906 /* Advertise midband for AR5416 with FCC midband set in eeprom */
1907 if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
1909 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
1911 if (AR_SREV_9280_20_OR_LATER(ah) && common->btcoex_enabled) {
1912 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
1913 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
1915 if (AR_SREV_9285(ah)) {
1916 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
1917 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
1919 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
1922 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
1925 if (AR_SREV_9300_20_OR_LATER(ah)) {
1926 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
1927 if (!AR_SREV_9485(ah))
1928 pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
1930 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
1931 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
1932 pCap->rx_status_len = sizeof(struct ar9003_rxs);
1933 pCap->tx_desc_len = sizeof(struct ar9003_txc);
1934 pCap->txs_len = sizeof(struct ar9003_txs);
1935 if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
1936 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
1938 pCap->tx_desc_len = sizeof(struct ath_desc);
1939 if (AR_SREV_9280_20(ah) &&
1940 ((ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) <=
1941 AR5416_EEP_MINOR_VER_16) ||
1942 ah->eep_ops->get_eeprom(ah, EEP_FSTCLK_5G)))
1943 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
1946 if (AR_SREV_9300_20_OR_LATER(ah))
1947 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
1949 if (AR_SREV_9300_20_OR_LATER(ah))
1950 ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
1952 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
1953 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
1955 if (AR_SREV_9285(ah))
1956 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
1958 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
1959 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1))
1960 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
1962 if (AR_SREV_9300_20_OR_LATER(ah)) {
1963 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
1964 pCap->hw_caps |= ATH9K_HW_CAP_APM;
1969 if (AR_SREV_9485_10(ah)) {
1970 pCap->pcie_lcr_extsync_en = true;
1971 pCap->pcie_lcr_offset = 0x80;
1974 tx_chainmask = pCap->tx_chainmask;
1975 rx_chainmask = pCap->rx_chainmask;
1976 while (tx_chainmask || rx_chainmask) {
1977 if (tx_chainmask & BIT(0))
1978 pCap->max_txchains++;
1979 if (rx_chainmask & BIT(0))
1980 pCap->max_rxchains++;
1989 /****************************/
1990 /* GPIO / RFKILL / Antennae */
1991 /****************************/
1993 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
1997 u32 gpio_shift, tmp;
2000 addr = AR_GPIO_OUTPUT_MUX3;
2002 addr = AR_GPIO_OUTPUT_MUX2;
2004 addr = AR_GPIO_OUTPUT_MUX1;
2006 gpio_shift = (gpio % 6) * 5;
2008 if (AR_SREV_9280_20_OR_LATER(ah)
2009 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2010 REG_RMW(ah, addr, (type << gpio_shift),
2011 (0x1f << gpio_shift));
2013 tmp = REG_READ(ah, addr);
2014 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2015 tmp &= ~(0x1f << gpio_shift);
2016 tmp |= (type << gpio_shift);
2017 REG_WRITE(ah, addr, tmp);
2021 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
2025 BUG_ON(gpio >= ah->caps.num_gpio_pins);
2027 if (AR_DEVID_7010(ah)) {
2029 REG_RMW(ah, AR7010_GPIO_OE,
2030 (AR7010_GPIO_OE_AS_INPUT << gpio_shift),
2031 (AR7010_GPIO_OE_MASK << gpio_shift));
2035 gpio_shift = gpio << 1;
2038 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2039 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2041 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
2043 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
2045 #define MS_REG_READ(x, y) \
2046 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2048 if (gpio >= ah->caps.num_gpio_pins)
2051 if (AR_DEVID_7010(ah)) {
2053 val = REG_READ(ah, AR7010_GPIO_IN);
2054 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
2055 } else if (AR_SREV_9300_20_OR_LATER(ah))
2056 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) &
2057 AR_GPIO_BIT(gpio)) != 0;
2058 else if (AR_SREV_9271(ah))
2059 return MS_REG_READ(AR9271, gpio) != 0;
2060 else if (AR_SREV_9287_11_OR_LATER(ah))
2061 return MS_REG_READ(AR9287, gpio) != 0;
2062 else if (AR_SREV_9285_12_OR_LATER(ah))
2063 return MS_REG_READ(AR9285, gpio) != 0;
2064 else if (AR_SREV_9280_20_OR_LATER(ah))
2065 return MS_REG_READ(AR928X, gpio) != 0;
2067 return MS_REG_READ(AR, gpio) != 0;
2069 EXPORT_SYMBOL(ath9k_hw_gpio_get);
2071 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
2076 if (AR_DEVID_7010(ah)) {
2078 REG_RMW(ah, AR7010_GPIO_OE,
2079 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift),
2080 (AR7010_GPIO_OE_MASK << gpio_shift));
2084 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
2085 gpio_shift = 2 * gpio;
2088 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2089 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2091 EXPORT_SYMBOL(ath9k_hw_cfg_output);
2093 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
2095 if (AR_DEVID_7010(ah)) {
2097 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio),
2102 if (AR_SREV_9271(ah))
2105 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2108 EXPORT_SYMBOL(ath9k_hw_set_gpio);
2110 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
2112 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
2114 EXPORT_SYMBOL(ath9k_hw_getdefantenna);
2116 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
2118 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
2120 EXPORT_SYMBOL(ath9k_hw_setantenna);
2122 /*********************/
2123 /* General Operation */
2124 /*********************/
2126 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
2128 u32 bits = REG_READ(ah, AR_RX_FILTER);
2129 u32 phybits = REG_READ(ah, AR_PHY_ERR);
2131 if (phybits & AR_PHY_ERR_RADAR)
2132 bits |= ATH9K_RX_FILTER_PHYRADAR;
2133 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2134 bits |= ATH9K_RX_FILTER_PHYERR;
2138 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
2140 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
2144 ENABLE_REGWRITE_BUFFER(ah);
2146 REG_WRITE(ah, AR_RX_FILTER, bits);
2149 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2150 phybits |= AR_PHY_ERR_RADAR;
2151 if (bits & ATH9K_RX_FILTER_PHYERR)
2152 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2153 REG_WRITE(ah, AR_PHY_ERR, phybits);
2156 REG_WRITE(ah, AR_RXCFG,
2157 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
2159 REG_WRITE(ah, AR_RXCFG,
2160 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
2162 REGWRITE_BUFFER_FLUSH(ah);
2164 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
2166 bool ath9k_hw_phy_disable(struct ath_hw *ah)
2168 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2171 ath9k_hw_init_pll(ah, NULL);
2174 EXPORT_SYMBOL(ath9k_hw_phy_disable);
2176 bool ath9k_hw_disable(struct ath_hw *ah)
2178 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2181 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2184 ath9k_hw_init_pll(ah, NULL);
2187 EXPORT_SYMBOL(ath9k_hw_disable);
2189 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
2191 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2192 struct ath9k_channel *chan = ah->curchan;
2193 struct ieee80211_channel *channel = chan->chan;
2195 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
2197 ah->eep_ops->set_txpower(ah, chan,
2198 ath9k_regd_get_ctl(regulatory, chan),
2199 channel->max_antenna_gain * 2,
2200 channel->max_power * 2,
2201 min((u32) MAX_RATE_POWER,
2202 (u32) regulatory->power_limit), test);
2204 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
2206 void ath9k_hw_setopmode(struct ath_hw *ah)
2208 ath9k_hw_set_operating_mode(ah, ah->opmode);
2210 EXPORT_SYMBOL(ath9k_hw_setopmode);
2212 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
2214 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2215 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
2217 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
2219 void ath9k_hw_write_associd(struct ath_hw *ah)
2221 struct ath_common *common = ath9k_hw_common(ah);
2223 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2224 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2225 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2227 EXPORT_SYMBOL(ath9k_hw_write_associd);
2229 #define ATH9K_MAX_TSF_READ 10
2231 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
2233 u32 tsf_lower, tsf_upper1, tsf_upper2;
2236 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2237 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2238 tsf_lower = REG_READ(ah, AR_TSF_L32);
2239 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2240 if (tsf_upper2 == tsf_upper1)
2242 tsf_upper1 = tsf_upper2;
2245 WARN_ON( i == ATH9K_MAX_TSF_READ );
2247 return (((u64)tsf_upper1 << 32) | tsf_lower);
2249 EXPORT_SYMBOL(ath9k_hw_gettsf64);
2251 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
2253 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
2254 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
2256 EXPORT_SYMBOL(ath9k_hw_settsf64);
2258 void ath9k_hw_reset_tsf(struct ath_hw *ah)
2260 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2261 AH_TSF_WRITE_TIMEOUT))
2262 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
2263 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
2265 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2267 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
2269 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
2272 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
2274 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
2276 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
2278 void ath9k_hw_set11nmac2040(struct ath_hw *ah)
2280 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
2283 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
2284 macmode = AR_2040_JOINED_RX_CLEAR;
2288 REG_WRITE(ah, AR_2040_MODE, macmode);
2291 /* HW Generic timers configuration */
2293 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2295 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2296 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2297 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2298 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2299 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2300 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2301 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2302 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2303 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2304 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2305 AR_NDP2_TIMER_MODE, 0x0002},
2306 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2307 AR_NDP2_TIMER_MODE, 0x0004},
2308 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2309 AR_NDP2_TIMER_MODE, 0x0008},
2310 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2311 AR_NDP2_TIMER_MODE, 0x0010},
2312 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2313 AR_NDP2_TIMER_MODE, 0x0020},
2314 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2315 AR_NDP2_TIMER_MODE, 0x0040},
2316 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2317 AR_NDP2_TIMER_MODE, 0x0080}
2320 /* HW generic timer primitives */
2322 /* compute and clear index of rightmost 1 */
2323 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2333 return timer_table->gen_timer_index[b];
2336 static u32 ath9k_hw_gettsf32(struct ath_hw *ah)
2338 return REG_READ(ah, AR_TSF_L32);
2341 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2342 void (*trigger)(void *),
2343 void (*overflow)(void *),
2347 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2348 struct ath_gen_timer *timer;
2350 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2352 if (timer == NULL) {
2353 ath_err(ath9k_hw_common(ah),
2354 "Failed to allocate memory for hw timer[%d]\n",
2359 /* allocate a hardware generic timer slot */
2360 timer_table->timers[timer_index] = timer;
2361 timer->index = timer_index;
2362 timer->trigger = trigger;
2363 timer->overflow = overflow;
2368 EXPORT_SYMBOL(ath_gen_timer_alloc);
2370 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2371 struct ath_gen_timer *timer,
2375 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2378 BUG_ON(!timer_period);
2380 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
2382 tsf = ath9k_hw_gettsf32(ah);
2384 ath_dbg(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
2385 "current tsf %x period %x timer_next %x\n",
2386 tsf, timer_period, timer_next);
2389 * Pull timer_next forward if the current TSF already passed it
2390 * because of software latency
2392 if (timer_next < tsf)
2393 timer_next = tsf + timer_period;
2396 * Program generic timer registers
2398 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
2400 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
2402 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2403 gen_tmr_configuration[timer->index].mode_mask);
2405 /* Enable both trigger and thresh interrupt masks */
2406 REG_SET_BIT(ah, AR_IMR_S5,
2407 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2408 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2410 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
2412 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
2414 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2416 if ((timer->index < AR_FIRST_NDP_TIMER) ||
2417 (timer->index >= ATH_MAX_GEN_TIMER)) {
2421 /* Clear generic timer enable bits. */
2422 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2423 gen_tmr_configuration[timer->index].mode_mask);
2425 /* Disable both trigger and thresh interrupt masks */
2426 REG_CLR_BIT(ah, AR_IMR_S5,
2427 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2428 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2430 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
2432 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
2434 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
2436 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2438 /* free the hardware generic timer slot */
2439 timer_table->timers[timer->index] = NULL;
2442 EXPORT_SYMBOL(ath_gen_timer_free);
2445 * Generic Timer Interrupts handling
2447 void ath_gen_timer_isr(struct ath_hw *ah)
2449 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2450 struct ath_gen_timer *timer;
2451 struct ath_common *common = ath9k_hw_common(ah);
2452 u32 trigger_mask, thresh_mask, index;
2454 /* get hardware generic timer interrupt status */
2455 trigger_mask = ah->intr_gen_timer_trigger;
2456 thresh_mask = ah->intr_gen_timer_thresh;
2457 trigger_mask &= timer_table->timer_mask.val;
2458 thresh_mask &= timer_table->timer_mask.val;
2460 trigger_mask &= ~thresh_mask;
2462 while (thresh_mask) {
2463 index = rightmost_index(timer_table, &thresh_mask);
2464 timer = timer_table->timers[index];
2466 ath_dbg(common, ATH_DBG_HWTIMER,
2467 "TSF overflow for Gen timer %d\n", index);
2468 timer->overflow(timer->arg);
2471 while (trigger_mask) {
2472 index = rightmost_index(timer_table, &trigger_mask);
2473 timer = timer_table->timers[index];
2475 ath_dbg(common, ATH_DBG_HWTIMER,
2476 "Gen timer[%d] trigger\n", index);
2477 timer->trigger(timer->arg);
2480 EXPORT_SYMBOL(ath_gen_timer_isr);
2486 void ath9k_hw_htc_resetinit(struct ath_hw *ah)
2488 ah->htc_reset_init = true;
2490 EXPORT_SYMBOL(ath9k_hw_htc_resetinit);
2495 } ath_mac_bb_names[] = {
2496 /* Devices with external radios */
2497 { AR_SREV_VERSION_5416_PCI, "5416" },
2498 { AR_SREV_VERSION_5416_PCIE, "5418" },
2499 { AR_SREV_VERSION_9100, "9100" },
2500 { AR_SREV_VERSION_9160, "9160" },
2501 /* Single-chip solutions */
2502 { AR_SREV_VERSION_9280, "9280" },
2503 { AR_SREV_VERSION_9285, "9285" },
2504 { AR_SREV_VERSION_9287, "9287" },
2505 { AR_SREV_VERSION_9271, "9271" },
2506 { AR_SREV_VERSION_9300, "9300" },
2509 /* For devices with external radios */
2513 } ath_rf_names[] = {
2515 { AR_RAD5133_SREV_MAJOR, "5133" },
2516 { AR_RAD5122_SREV_MAJOR, "5122" },
2517 { AR_RAD2133_SREV_MAJOR, "2133" },
2518 { AR_RAD2122_SREV_MAJOR, "2122" }
2522 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2524 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2528 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2529 if (ath_mac_bb_names[i].version == mac_bb_version) {
2530 return ath_mac_bb_names[i].name;
2538 * Return the RF name. "????" is returned if the RF is unknown.
2539 * Used for devices with external radios.
2541 static const char *ath9k_hw_rf_name(u16 rf_version)
2545 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2546 if (ath_rf_names[i].version == rf_version) {
2547 return ath_rf_names[i].name;
2554 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
2558 /* chipsets >= AR9280 are single-chip */
2559 if (AR_SREV_9280_20_OR_LATER(ah)) {
2560 used = snprintf(hw_name, len,
2561 "Atheros AR%s Rev:%x",
2562 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2563 ah->hw_version.macRev);
2566 used = snprintf(hw_name, len,
2567 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
2568 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2569 ah->hw_version.macRev,
2570 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
2571 AR_RADIO_SREV_MAJOR)),
2572 ah->hw_version.phyRev);
2575 hw_name[used] = '\0';
2577 EXPORT_SYMBOL(ath9k_hw_name);