2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include <linux/if_ether.h>
21 #include <linux/delay.h>
23 #include <linux/firmware.h>
36 #define ATHEROS_VENDOR_ID 0x168c
38 #define AR5416_DEVID_PCI 0x0023
39 #define AR5416_DEVID_PCIE 0x0024
40 #define AR9160_DEVID_PCI 0x0027
41 #define AR9280_DEVID_PCI 0x0029
42 #define AR9280_DEVID_PCIE 0x002a
43 #define AR9285_DEVID_PCIE 0x002b
44 #define AR2427_DEVID_PCIE 0x002c
45 #define AR9287_DEVID_PCI 0x002d
46 #define AR9287_DEVID_PCIE 0x002e
47 #define AR9300_DEVID_PCIE 0x0030
48 #define AR9300_DEVID_AR9340 0x0031
49 #define AR9300_DEVID_AR9485_PCIE 0x0032
50 #define AR9300_DEVID_AR9580 0x0033
51 #define AR9300_DEVID_AR9462 0x0034
52 #define AR9300_DEVID_AR9330 0x0035
53 #define AR9300_DEVID_QCA955X 0x0038
54 #define AR9485_DEVID_AR1111 0x0037
55 #define AR9300_DEVID_AR9565 0x0036
56 #define AR9300_DEVID_AR953X 0x003d
57 #define AR9300_DEVID_QCA956X 0x003f
59 #define AR5416_AR9100_DEVID 0x000b
61 #define AR_SUBVENDOR_ID_NOG 0x0e11
62 #define AR_SUBVENDOR_ID_NEW_A 0x7065
63 #define AR5416_MAGIC 0x19641014
65 #define AR9280_COEX2WIRE_SUBSYSID 0x309b
66 #define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa
67 #define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab
69 #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1)
71 #define ATH_DEFAULT_NOISE_FLOOR -95
73 #define ATH9K_RSSI_BAD -128
75 #define ATH9K_NUM_CHANNELS 38
77 /* Register read/write primitives */
78 #define REG_WRITE(_ah, _reg, _val) \
79 (_ah)->reg_ops.write((_ah), (_val), (_reg))
81 #define REG_READ(_ah, _reg) \
82 (_ah)->reg_ops.read((_ah), (_reg))
84 #define REG_READ_MULTI(_ah, _addr, _val, _cnt) \
85 (_ah)->reg_ops.multi_read((_ah), (_addr), (_val), (_cnt))
87 #define REG_RMW(_ah, _reg, _set, _clr) \
88 (_ah)->reg_ops.rmw((_ah), (_reg), (_set), (_clr))
90 #define ENABLE_REGWRITE_BUFFER(_ah) \
92 if ((_ah)->reg_ops.enable_write_buffer) \
93 (_ah)->reg_ops.enable_write_buffer((_ah)); \
96 #define REGWRITE_BUFFER_FLUSH(_ah) \
98 if ((_ah)->reg_ops.write_flush) \
99 (_ah)->reg_ops.write_flush((_ah)); \
102 #define PR_EEP(_s, _val) \
104 len += scnprintf(buf + len, size - len, "%20s : %10d\n",\
108 #define SM(_v, _f) (((_v) << _f##_S) & _f)
109 #define MS(_v, _f) (((_v) & _f) >> _f##_S)
110 #define REG_RMW_FIELD(_a, _r, _f, _v) \
111 REG_RMW(_a, _r, (((_v) << _f##_S) & _f), (_f))
112 #define REG_READ_FIELD(_a, _r, _f) \
113 (((REG_READ(_a, _r) & _f) >> _f##_S))
114 #define REG_SET_BIT(_a, _r, _f) \
115 REG_RMW(_a, _r, (_f), 0)
116 #define REG_CLR_BIT(_a, _r, _f) \
117 REG_RMW(_a, _r, 0, (_f))
119 #define DO_DELAY(x) do { \
120 if (((++(x) % 64) == 0) && \
121 (ath9k_hw_common(ah)->bus_ops->ath_bus_type \
126 #define REG_WRITE_ARRAY(iniarray, column, regWr) \
127 ath9k_hw_write_array(ah, iniarray, column, &(regWr))
129 #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
130 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
131 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
132 #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3
133 #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4
134 #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
135 #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
136 #define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA 0x16
137 #define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK 0x17
138 #define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA 0x18
139 #define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK 0x19
140 #define AR_GPIO_OUTPUT_MUX_AS_WL_IN_TX 0x14
141 #define AR_GPIO_OUTPUT_MUX_AS_WL_IN_RX 0x13
142 #define AR_GPIO_OUTPUT_MUX_AS_BT_IN_TX 9
143 #define AR_GPIO_OUTPUT_MUX_AS_BT_IN_RX 8
144 #define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_STROBE 0x1d
145 #define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_DATA 0x1e
147 #define AR_GPIOD_MASK 0x00001FFF
148 #define AR_GPIO_BIT(_gpio) (1 << (_gpio))
150 #define BASE_ACTIVATE_DELAY 100
151 #define RTC_PLL_SETTLE_DELAY (AR_SREV_9340(ah) ? 1000 : 100)
152 #define COEF_SCALE_S 24
153 #define HT40_CHANNEL_CENTER_SHIFT 10
155 #define ATH9K_ANTENNA0_CHAINMASK 0x1
156 #define ATH9K_ANTENNA1_CHAINMASK 0x2
158 #define ATH9K_NUM_DMA_DEBUG_REGS 8
159 #define ATH9K_NUM_QUEUES 10
161 #define MAX_RATE_POWER 63
162 #define AH_WAIT_TIMEOUT 100000 /* (us) */
163 #define AH_TSF_WRITE_TIMEOUT 100 /* (us) */
164 #define AH_TIME_QUANTUM 10
165 #define AR_KEYTABLE_SIZE 128
166 #define POWER_UP_TIME 10000
167 #define SPUR_RSSI_THRESH 40
168 #define UPPER_5G_SUB_BAND_START 5700
169 #define MID_5G_SUB_BAND_START 5400
171 #define CAB_TIMEOUT_VAL 10
172 #define BEACON_TIMEOUT_VAL 10
173 #define MIN_BEACON_TIMEOUT_VAL 1
174 #define SLEEP_SLOP TU_TO_USEC(3)
176 #define INIT_CONFIG_STATUS 0x00000000
177 #define INIT_RSSI_THR 0x00000700
178 #define INIT_BCON_CNTRL_REG 0x00000000
180 #define TU_TO_USEC(_tu) ((_tu) << 10)
182 #define ATH9K_HW_RX_HP_QDEPTH 16
183 #define ATH9K_HW_RX_LP_QDEPTH 128
185 #define PAPRD_GAIN_TABLE_ENTRIES 32
186 #define PAPRD_TABLE_SZ 24
187 #define PAPRD_IDEAL_AGC2_PWR_RANGE 0xe0
193 /* Keep Alive Frame */
194 #define KAL_FRAME_LEN 28
195 #define KAL_FRAME_TYPE 0x2 /* data frame */
196 #define KAL_FRAME_SUB_TYPE 0x4 /* null data frame */
197 #define KAL_DURATION_ID 0x3d
198 #define KAL_NUM_DATA_WORDS 6
199 #define KAL_NUM_DESC_WORDS 12
200 #define KAL_ANTENNA_MODE 1
202 #define KAL_DELAY 4 /*delay of 4ms between 2 KAL frames */
203 #define KAL_TIMEOUT 900
205 #define MAX_PATTERN_SIZE 256
206 #define MAX_PATTERN_MASK_SIZE 32
207 #define MAX_NUM_PATTERN 8
208 #define MAX_NUM_USER_PATTERN 6 /* deducting the disassociate and
209 deauthenticate packets */
212 * WoW trigger mapping to hardware code
215 #define AH_WOW_USER_PATTERN_EN BIT(0)
216 #define AH_WOW_MAGIC_PATTERN_EN BIT(1)
217 #define AH_WOW_LINK_CHANGE BIT(2)
218 #define AH_WOW_BEACON_MISS BIT(3)
220 enum ath_hw_txq_subtype {
227 enum ath_ini_subsys {
235 ATH9K_HW_CAP_HT = BIT(0),
236 ATH9K_HW_CAP_RFSILENT = BIT(1),
237 ATH9K_HW_CAP_AUTOSLEEP = BIT(2),
238 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(3),
239 ATH9K_HW_CAP_EDMA = BIT(4),
240 ATH9K_HW_CAP_RAC_SUPPORTED = BIT(5),
241 ATH9K_HW_CAP_LDPC = BIT(6),
242 ATH9K_HW_CAP_FASTCLOCK = BIT(7),
243 ATH9K_HW_CAP_SGI_20 = BIT(8),
244 ATH9K_HW_CAP_ANT_DIV_COMB = BIT(10),
245 ATH9K_HW_CAP_2GHZ = BIT(11),
246 ATH9K_HW_CAP_5GHZ = BIT(12),
247 ATH9K_HW_CAP_APM = BIT(13),
248 #ifdef CONFIG_ATH9K_PCOEM
249 ATH9K_HW_CAP_RTT = BIT(14),
250 ATH9K_HW_CAP_MCI = BIT(15),
251 ATH9K_HW_WOW_DEVICE_CAPABLE = BIT(16),
252 ATH9K_HW_CAP_BT_ANT_DIV = BIT(17),
254 ATH9K_HW_CAP_RTT = 0,
255 ATH9K_HW_CAP_MCI = 0,
256 ATH9K_HW_WOW_DEVICE_CAPABLE = 0,
257 ATH9K_HW_CAP_BT_ANT_DIV = 0,
259 ATH9K_HW_CAP_DFS = BIT(18),
260 ATH9K_HW_CAP_PAPRD = BIT(19),
261 ATH9K_HW_CAP_FCC_BAND_SWITCH = BIT(20),
265 * WoW device capabilities
266 * @ATH9K_HW_WOW_DEVICE_CAPABLE: device revision is capable of WoW.
267 * @ATH9K_HW_WOW_PATTERN_MATCH_EXACT: device is capable of matching
268 * an exact user defined pattern or de-authentication/disassoc pattern.
269 * @ATH9K_HW_WOW_PATTERN_MATCH_DWORD: device requires the first four
270 * bytes of the pattern for user defined pattern, de-authentication and
271 * disassociation patterns for all types of possible frames recieved
275 struct ath9k_hw_capabilities {
276 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
291 #define AR_NO_SPUR 0x8000
292 #define AR_BASE_FREQ_2GHZ 2300
293 #define AR_BASE_FREQ_5GHZ 4900
294 #define AR_SPUR_FEEQ_BOUND_HT40 19
295 #define AR_SPUR_FEEQ_BOUND_HT20 10
297 enum ath9k_hw_hang_checks {
298 HW_BB_WATCHDOG = BIT(0),
299 HW_PHYRESTART_CLC_WAR = BIT(1),
300 HW_BB_RIFS_HANG = BIT(2),
301 HW_BB_DFS_HANG = BIT(3),
302 HW_BB_RX_CLEAR_STUCK_HANG = BIT(4),
303 HW_MAC_HANG = BIT(5),
306 struct ath9k_ops_config {
307 int dma_beacon_response_time;
308 int sw_beacon_response_time;
309 u32 cwm_ignore_extcca;
317 int serialize_regmode;
318 bool rx_intr_mitigation;
319 bool tx_intr_mitigation;
321 u16 ani_poll_interval; /* ANI poll interval in ms */
326 /* Platform specific config */
329 u32 ant_ctrl_comm2g_switch_enable;
330 bool xatten_margin_cfg;
333 bool tx_gain_buffalo;
334 bool led_active_high;
338 ATH9K_INT_RX = 0x00000001,
339 ATH9K_INT_RXDESC = 0x00000002,
340 ATH9K_INT_RXHP = 0x00000001,
341 ATH9K_INT_RXLP = 0x00000002,
342 ATH9K_INT_RXNOFRM = 0x00000008,
343 ATH9K_INT_RXEOL = 0x00000010,
344 ATH9K_INT_RXORN = 0x00000020,
345 ATH9K_INT_TX = 0x00000040,
346 ATH9K_INT_TXDESC = 0x00000080,
347 ATH9K_INT_TIM_TIMER = 0x00000100,
348 ATH9K_INT_MCI = 0x00000200,
349 ATH9K_INT_BB_WATCHDOG = 0x00000400,
350 ATH9K_INT_TXURN = 0x00000800,
351 ATH9K_INT_MIB = 0x00001000,
352 ATH9K_INT_RXPHY = 0x00004000,
353 ATH9K_INT_RXKCM = 0x00008000,
354 ATH9K_INT_SWBA = 0x00010000,
355 ATH9K_INT_BMISS = 0x00040000,
356 ATH9K_INT_BNR = 0x00100000,
357 ATH9K_INT_TIM = 0x00200000,
358 ATH9K_INT_DTIM = 0x00400000,
359 ATH9K_INT_DTIMSYNC = 0x00800000,
360 ATH9K_INT_GPIO = 0x01000000,
361 ATH9K_INT_CABEND = 0x02000000,
362 ATH9K_INT_TSFOOR = 0x04000000,
363 ATH9K_INT_GENTIMER = 0x08000000,
364 ATH9K_INT_CST = 0x10000000,
365 ATH9K_INT_GTT = 0x20000000,
366 ATH9K_INT_FATAL = 0x40000000,
367 ATH9K_INT_GLOBAL = 0x80000000,
368 ATH9K_INT_BMISC = ATH9K_INT_TIM |
373 ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
385 ATH9K_INT_NOCARD = 0xffffffff
388 #define MAX_RTT_TABLE_ENTRY 6
389 #define MAX_IQCAL_MEASUREMENT 8
390 #define MAX_CL_TAB_ENTRY 16
391 #define CL_TAB_ENTRY(reg_base) (reg_base + (4 * j))
393 enum ath9k_cal_flags {
404 struct ath9k_hw_cal_data {
407 unsigned long cal_flags;
412 u16 small_signal_gain[AR9300_MAX_CHAINS];
413 u32 pa_table[AR9300_MAX_CHAINS][PAPRD_TABLE_SZ];
414 u32 num_measures[AR9300_MAX_CHAINS];
415 int tx_corr_coeff[MAX_IQCAL_MEASUREMENT][AR9300_MAX_CHAINS];
416 u32 tx_clcal[AR9300_MAX_CHAINS][MAX_CL_TAB_ENTRY];
417 u32 rtt_table[AR9300_MAX_CHAINS][MAX_RTT_TABLE_ENTRY];
418 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
421 struct ath9k_channel {
422 struct ieee80211_channel *chan;
428 #define CHANNEL_5GHZ BIT(0)
429 #define CHANNEL_HALF BIT(1)
430 #define CHANNEL_QUARTER BIT(2)
431 #define CHANNEL_HT BIT(3)
432 #define CHANNEL_HT40PLUS BIT(4)
433 #define CHANNEL_HT40MINUS BIT(5)
435 #define IS_CHAN_5GHZ(_c) (!!((_c)->channelFlags & CHANNEL_5GHZ))
436 #define IS_CHAN_2GHZ(_c) (!IS_CHAN_5GHZ(_c))
438 #define IS_CHAN_HALF_RATE(_c) (!!((_c)->channelFlags & CHANNEL_HALF))
439 #define IS_CHAN_QUARTER_RATE(_c) (!!((_c)->channelFlags & CHANNEL_QUARTER))
440 #define IS_CHAN_A_FAST_CLOCK(_ah, _c) \
441 (IS_CHAN_5GHZ(_c) && ((_ah)->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK))
443 #define IS_CHAN_HT(_c) ((_c)->channelFlags & CHANNEL_HT)
445 #define IS_CHAN_HT20(_c) (IS_CHAN_HT(_c) && !IS_CHAN_HT40(_c))
447 #define IS_CHAN_HT40(_c) \
448 (!!((_c)->channelFlags & (CHANNEL_HT40PLUS | CHANNEL_HT40MINUS)))
450 #define IS_CHAN_HT40PLUS(_c) ((_c)->channelFlags & CHANNEL_HT40PLUS)
451 #define IS_CHAN_HT40MINUS(_c) ((_c)->channelFlags & CHANNEL_HT40MINUS)
453 enum ath9k_power_mode {
456 ATH9K_PM_NETWORK_SLEEP,
461 SER_REG_MODE_OFF = 0,
463 SER_REG_MODE_AUTO = 2,
466 enum ath9k_rx_qtype {
472 struct ath9k_beacon_state {
476 #define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */
478 u16 bs_bmissthreshold;
479 u32 bs_sleepduration;
480 u32 bs_tsfoor_threshold;
483 struct chan_centers {
490 ATH9K_RESET_POWER_ON,
495 struct ath9k_hw_version {
504 enum ath_usb_dev usbdev;
507 /* Generic TSF timer definitions */
509 #define ATH_MAX_GEN_TIMER 16
511 #define AR_GENTMR_BIT(_index) (1 << (_index))
513 struct ath_gen_timer_configuration {
520 struct ath_gen_timer {
521 void (*trigger)(void *arg);
522 void (*overflow)(void *arg);
527 struct ath_gen_timer_table {
528 struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER];
533 struct ath_hw_antcomb_conf {
540 int lna1_lna2_switch_delta;
545 * struct ath_hw_radar_conf - radar detection initialization parameters
547 * @pulse_inband: threshold for checking the ratio of in-band power
548 * to total power for short radar pulses (half dB steps)
549 * @pulse_inband_step: threshold for checking an in-band power to total
550 * power ratio increase for short radar pulses (half dB steps)
551 * @pulse_height: threshold for detecting the beginning of a short
552 * radar pulse (dB step)
553 * @pulse_rssi: threshold for detecting if a short radar pulse is
555 * @pulse_maxlen: maximum pulse length (0.8 us steps)
557 * @radar_rssi: RSSI threshold for starting long radar detection (dB steps)
558 * @radar_inband: threshold for checking the ratio of in-band power
559 * to total power for long radar pulses (half dB steps)
560 * @fir_power: threshold for detecting the end of a long radar pulse (dB)
562 * @ext_channel: enable extension channel radar detection
564 struct ath_hw_radar_conf {
565 unsigned int pulse_inband;
566 unsigned int pulse_inband_step;
567 unsigned int pulse_height;
568 unsigned int pulse_rssi;
569 unsigned int pulse_maxlen;
571 unsigned int radar_rssi;
572 unsigned int radar_inband;
579 * struct ath_hw_private_ops - callbacks used internally by hardware code
581 * This structure contains private callbacks designed to only be used internally
582 * by the hardware core.
584 * @init_cal_settings: setup types of calibrations supported
585 * @init_cal: starts actual calibration
587 * @init_mode_gain_regs: Initialize TX/RX gain registers
589 * @rf_set_freq: change frequency
590 * @spur_mitigate_freq: spur mitigation
592 * @compute_pll_control: compute the PLL control value to use for
593 * AR_RTC_PLL_CONTROL for a given channel
594 * @setup_calibration: set up calibration
595 * @iscal_supported: used to query if a type of calibration is supported
597 * @ani_cache_ini_regs: cache the values for ANI from the initial
598 * register settings through the register initialization.
600 struct ath_hw_private_ops {
601 void (*init_hang_checks)(struct ath_hw *ah);
602 bool (*detect_mac_hang)(struct ath_hw *ah);
603 bool (*detect_bb_hang)(struct ath_hw *ah);
605 /* Calibration ops */
606 void (*init_cal_settings)(struct ath_hw *ah);
607 bool (*init_cal)(struct ath_hw *ah, struct ath9k_channel *chan);
609 void (*init_mode_gain_regs)(struct ath_hw *ah);
610 void (*setup_calibration)(struct ath_hw *ah,
611 struct ath9k_cal_list *currCal);
614 int (*rf_set_freq)(struct ath_hw *ah,
615 struct ath9k_channel *chan);
616 void (*spur_mitigate_freq)(struct ath_hw *ah,
617 struct ath9k_channel *chan);
618 bool (*set_rf_regs)(struct ath_hw *ah,
619 struct ath9k_channel *chan,
621 void (*set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan);
622 void (*init_bb)(struct ath_hw *ah,
623 struct ath9k_channel *chan);
624 int (*process_ini)(struct ath_hw *ah, struct ath9k_channel *chan);
625 void (*olc_init)(struct ath_hw *ah);
626 void (*set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan);
627 void (*mark_phy_inactive)(struct ath_hw *ah);
628 void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan);
629 bool (*rfbus_req)(struct ath_hw *ah);
630 void (*rfbus_done)(struct ath_hw *ah);
631 void (*restore_chainmask)(struct ath_hw *ah);
632 u32 (*compute_pll_control)(struct ath_hw *ah,
633 struct ath9k_channel *chan);
634 bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd,
636 void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]);
637 void (*set_radar_params)(struct ath_hw *ah,
638 struct ath_hw_radar_conf *conf);
639 int (*fast_chan_change)(struct ath_hw *ah, struct ath9k_channel *chan,
643 void (*ani_cache_ini_regs)(struct ath_hw *ah);
647 * struct ath_spec_scan - parameters for Atheros spectral scan
649 * @enabled: enable/disable spectral scan
650 * @short_repeat: controls whether the chip is in spectral scan mode
651 * for 4 usec (enabled) or 204 usec (disabled)
652 * @count: number of scan results requested. There are special meanings
653 * in some chip revisions:
654 * AR92xx: highest bit set (>=128) for endless mode
655 * (spectral scan won't stopped until explicitly disabled)
656 * AR9300 and newer: 0 for endless mode
657 * @endless: true if endless mode is intended. Otherwise, count value is
658 * corrected to the next possible value.
659 * @period: time duration between successive spectral scan entry points
660 * (period*256*Tclk). Tclk = ath_common->clockrate
661 * @fft_period: PHY passes FFT frames to MAC every (fft_period+1)*4uS
663 * Note: Tclk = 40MHz or 44MHz depending upon operating mode.
664 * Typically it's 44MHz in 2/5GHz on later chips, but there's
665 * a "fast clock" check for this in 5GHz.
668 struct ath_spec_scan {
678 * struct ath_hw_ops - callbacks used by hardware code and driver code
680 * This structure contains callbacks designed to to be used internally by
681 * hardware code and also by the lower level driver.
683 * @config_pci_powersave:
684 * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC
686 * @spectral_scan_config: set parameters for spectral scan and enable/disable it
687 * @spectral_scan_trigger: trigger a spectral scan run
688 * @spectral_scan_wait: wait for a spectral scan run to finish
691 void (*config_pci_powersave)(struct ath_hw *ah,
693 void (*rx_enable)(struct ath_hw *ah);
694 void (*set_desc_link)(void *ds, u32 link);
695 int (*calibrate)(struct ath_hw *ah, struct ath9k_channel *chan,
696 u8 rxchainmask, bool longcal);
697 bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked,
699 void (*set_txdesc)(struct ath_hw *ah, void *ds,
700 struct ath_tx_info *i);
701 int (*proc_txdesc)(struct ath_hw *ah, void *ds,
702 struct ath_tx_status *ts);
703 int (*get_duration)(struct ath_hw *ah, const void *ds, int index);
704 void (*antdiv_comb_conf_get)(struct ath_hw *ah,
705 struct ath_hw_antcomb_conf *antconf);
706 void (*antdiv_comb_conf_set)(struct ath_hw *ah,
707 struct ath_hw_antcomb_conf *antconf);
708 void (*spectral_scan_config)(struct ath_hw *ah,
709 struct ath_spec_scan *param);
710 void (*spectral_scan_trigger)(struct ath_hw *ah);
711 void (*spectral_scan_wait)(struct ath_hw *ah);
713 void (*tx99_start)(struct ath_hw *ah, u32 qnum);
714 void (*tx99_stop)(struct ath_hw *ah);
715 void (*tx99_set_txpower)(struct ath_hw *ah, u8 power);
717 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
718 void (*set_bt_ant_diversity)(struct ath_hw *hw, bool enable);
722 struct ath_nf_limits {
730 TX_IQ_ON_AGC_CAL = BIT(1),
735 #define AH_USE_EEPROM 0x1
736 #define AH_UNPLUGGED 0x2 /* The card has been physically removed. */
737 #define AH_FASTCC 0x4
738 #define AH_NO_EEP_SWAP 0x8 /* Do not swap EEPROM data */
741 struct ath_ops reg_ops;
744 struct ieee80211_hw *hw;
745 struct ath_common common;
746 struct ath9k_hw_version hw_version;
747 struct ath9k_ops_config config;
748 struct ath9k_hw_capabilities caps;
749 struct ath9k_channel channels[ATH9K_NUM_CHANNELS];
750 struct ath9k_channel *curchan;
753 struct ar5416_eeprom_def def;
754 struct ar5416_eeprom_4k map4k;
755 struct ar9287_eeprom map9287;
756 struct ar9300_eeprom ar9300_eep;
758 const struct eeprom_ops *eep_ops;
760 bool sw_mgmt_crypto_tx;
761 bool sw_mgmt_crypto_rx;
765 bool need_an_top2_fixup;
769 struct ath_nf_limits nf_2g;
770 struct ath_nf_limits nf_5g;
779 enum nl80211_iftype opmode;
780 enum ath9k_power_mode power_mode;
783 struct ath9k_hw_cal_data *caldata;
784 struct ath9k_pacal_info pacal_info;
785 struct ar5416Stats stats;
786 struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES];
788 enum ath9k_int imask;
790 u32 txok_interrupt_mask;
791 u32 txerr_interrupt_mask;
792 u32 txdesc_interrupt_mask;
793 u32 txeol_interrupt_mask;
794 u32 txurn_interrupt_mask;
795 atomic_t intr_ref_cnt;
801 struct ath9k_cal_list iq_caldata;
802 struct ath9k_cal_list adcgain_caldata;
803 struct ath9k_cal_list adcdc_caldata;
804 struct ath9k_cal_list *cal_list;
805 struct ath9k_cal_list *cal_list_last;
806 struct ath9k_cal_list *cal_list_curr;
807 #define totalPowerMeasI meas0.unsign
808 #define totalPowerMeasQ meas1.unsign
809 #define totalIqCorrMeas meas2.sign
810 #define totalAdcIOddPhase meas0.unsign
811 #define totalAdcIEvenPhase meas1.unsign
812 #define totalAdcQOddPhase meas2.unsign
813 #define totalAdcQEvenPhase meas3.unsign
814 #define totalAdcDcOffsetIOddPhase meas0.sign
815 #define totalAdcDcOffsetIEvenPhase meas1.sign
816 #define totalAdcDcOffsetQOddPhase meas2.sign
817 #define totalAdcDcOffsetQEvenPhase meas3.sign
819 u32 unsign[AR5416_MAX_CHAINS];
820 int32_t sign[AR5416_MAX_CHAINS];
823 u32 unsign[AR5416_MAX_CHAINS];
824 int32_t sign[AR5416_MAX_CHAINS];
827 u32 unsign[AR5416_MAX_CHAINS];
828 int32_t sign[AR5416_MAX_CHAINS];
831 u32 unsign[AR5416_MAX_CHAINS];
832 int32_t sign[AR5416_MAX_CHAINS];
837 u32 sta_id1_defaults;
840 /* Private to hardware code */
841 struct ath_hw_private_ops private_ops;
842 /* Accessed by the lower level driver */
843 struct ath_hw_ops ops;
845 /* Used to program the radio on non single-chip devices */
846 u32 *analogBank6Data;
854 enum ath9k_ani_cmd ani_function;
856 struct ar5416AniState ani;
858 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
859 struct ath_btcoex_hw btcoex_hw;
866 struct ath_hw_radar_conf radar_conf;
868 u32 originalGain[22];
875 struct ar5416IniArray ini_dfs;
876 struct ar5416IniArray iniModes;
877 struct ar5416IniArray iniCommon;
878 struct ar5416IniArray iniBB_RfGain;
879 struct ar5416IniArray iniBank6;
880 struct ar5416IniArray iniAddac;
881 struct ar5416IniArray iniPcieSerdes;
882 struct ar5416IniArray iniPcieSerdesLowPower;
883 struct ar5416IniArray iniModesFastClock;
884 struct ar5416IniArray iniAdditional;
885 struct ar5416IniArray iniModesRxGain;
886 struct ar5416IniArray ini_modes_rx_gain_bounds;
887 struct ar5416IniArray iniModesTxGain;
888 struct ar5416IniArray iniCckfirNormal;
889 struct ar5416IniArray iniCckfirJapan2484;
890 struct ar5416IniArray iniModes_9271_ANI_reg;
891 struct ar5416IniArray ini_radio_post_sys2ant;
892 struct ar5416IniArray ini_modes_rxgain_5g_xlna;
893 struct ar5416IniArray ini_modes_rxgain_bb_core;
894 struct ar5416IniArray ini_modes_rxgain_bb_postamble;
896 struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT];
897 struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT];
898 struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT];
899 struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT];
901 u32 intr_gen_timer_trigger;
902 u32 intr_gen_timer_thresh;
903 struct ath_gen_timer_table hw_gen_timers;
905 struct ar9003_txs *ts_ring;
911 u32 bb_watchdog_last_status;
912 u32 bb_watchdog_timeout_ms; /* in ms, 0 to disable */
913 u8 bb_hang_rx_ofdm; /* true if bb hang due to rx_ofdm */
915 unsigned int paprd_target_power;
916 unsigned int paprd_training_power;
917 unsigned int paprd_ratemask;
918 unsigned int paprd_ratemask_ht40;
919 bool paprd_table_write_done;
920 u32 paprd_gain_table_entries[PAPRD_GAIN_TABLE_ENTRIES];
921 u8 paprd_gain_table_index[PAPRD_GAIN_TABLE_ENTRIES];
923 * Store the permanent value of Reg 0x4004in WARegVal
924 * so we dont have to R/M/W. We should not be reading
925 * this register when in sleep states.
929 /* Enterprise mode cap */
932 #ifdef CONFIG_ATH9K_WOW
936 int (*get_mac_revision)(void);
937 int (*external_reset)(void);
941 const struct firmware *eeprom_blob;
943 struct ath_dynack dynack;
946 u8 tx_power[Ar5416RateSize];
947 u8 tx_power_stbc[Ar5416RateSize];
951 enum ath_bus_type ath_bus_type;
952 void (*read_cachesize)(struct ath_common *common, int *csz);
953 bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data);
954 void (*bt_coex_prep)(struct ath_common *common);
955 void (*aspm_init)(struct ath_common *common);
958 static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
963 static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah)
965 return &(ath9k_hw_common(ah)->regulatory);
968 static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah)
970 return &ah->private_ops;
973 static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah)
978 static inline u8 get_streams(int mask)
980 return !!(mask & BIT(0)) + !!(mask & BIT(1)) + !!(mask & BIT(2));
983 /* Initialization, Detach, Reset */
984 void ath9k_hw_deinit(struct ath_hw *ah);
985 int ath9k_hw_init(struct ath_hw *ah);
986 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
987 struct ath9k_hw_cal_data *caldata, bool fastcc);
988 int ath9k_hw_fill_cap_info(struct ath_hw *ah);
989 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan);
991 /* GPIO / RFKILL / Antennae */
992 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio);
993 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio);
994 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
996 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val);
997 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna);
999 /* General Operation */
1000 void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan,
1002 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
1003 void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array,
1004 int column, unsigned int *writecnt);
1005 u32 ath9k_hw_reverse_bits(u32 val, u32 n);
1006 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
1008 u32 frameLen, u16 rateix, bool shortPreamble);
1009 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
1010 struct ath9k_channel *chan,
1011 struct chan_centers *centers);
1012 u32 ath9k_hw_getrxfilter(struct ath_hw *ah);
1013 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits);
1014 bool ath9k_hw_phy_disable(struct ath_hw *ah);
1015 bool ath9k_hw_disable(struct ath_hw *ah);
1016 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test);
1017 void ath9k_hw_setopmode(struct ath_hw *ah);
1018 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
1019 void ath9k_hw_write_associd(struct ath_hw *ah);
1020 u32 ath9k_hw_gettsf32(struct ath_hw *ah);
1021 u64 ath9k_hw_gettsf64(struct ath_hw *ah);
1022 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
1023 void ath9k_hw_reset_tsf(struct ath_hw *ah);
1024 u32 ath9k_hw_get_tsf_offset(struct timespec *last, struct timespec *cur);
1025 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set);
1026 void ath9k_hw_init_global_settings(struct ath_hw *ah);
1027 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah);
1028 void ath9k_hw_set11nmac2040(struct ath_hw *ah, struct ath9k_channel *chan);
1029 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
1030 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
1031 const struct ath9k_beacon_state *bs);
1032 void ath9k_hw_check_nav(struct ath_hw *ah);
1033 bool ath9k_hw_check_alive(struct ath_hw *ah);
1035 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode);
1037 /* Generic hw timer primitives */
1038 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
1039 void (*trigger)(void *),
1040 void (*overflow)(void *),
1043 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
1044 struct ath_gen_timer *timer,
1047 void ath9k_hw_gen_timer_start_tsf2(struct ath_hw *ah);
1048 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer);
1050 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer);
1051 void ath_gen_timer_isr(struct ath_hw *hw);
1053 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len);
1056 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1057 u32 *coef_mantissa, u32 *coef_exponent);
1058 void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan,
1062 * Code Specific to AR5008, AR9001 or AR9002,
1063 * we stuff these here to avoid callbacks for AR9003.
1065 int ar9002_hw_rf_claim(struct ath_hw *ah);
1066 void ar9002_hw_enable_async_fifo(struct ath_hw *ah);
1069 * Code specific to AR9003, we stuff these here to avoid callbacks
1070 * for older families
1072 bool ar9003_hw_bb_watchdog_check(struct ath_hw *ah);
1073 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah);
1074 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah);
1075 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah);
1076 void ar9003_hw_disable_phy_restart(struct ath_hw *ah);
1077 void ar9003_paprd_enable(struct ath_hw *ah, bool val);
1078 void ar9003_paprd_populate_single_table(struct ath_hw *ah,
1079 struct ath9k_hw_cal_data *caldata,
1081 int ar9003_paprd_create_curve(struct ath_hw *ah,
1082 struct ath9k_hw_cal_data *caldata, int chain);
1083 void ar9003_paprd_setup_gain_table(struct ath_hw *ah, int chain);
1084 int ar9003_paprd_init_table(struct ath_hw *ah);
1085 bool ar9003_paprd_is_done(struct ath_hw *ah);
1086 bool ar9003_is_paprd_enabled(struct ath_hw *ah);
1087 void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx);
1088 void ar9003_hw_init_rate_txpower(struct ath_hw *ah, u8 *rate_array,
1089 struct ath9k_channel *chan);
1091 /* Hardware family op attach helpers */
1092 int ar5008_hw_attach_phy_ops(struct ath_hw *ah);
1093 void ar9002_hw_attach_phy_ops(struct ath_hw *ah);
1094 void ar9003_hw_attach_phy_ops(struct ath_hw *ah);
1096 void ar9002_hw_attach_calib_ops(struct ath_hw *ah);
1097 void ar9003_hw_attach_calib_ops(struct ath_hw *ah);
1099 int ar9002_hw_attach_ops(struct ath_hw *ah);
1100 void ar9003_hw_attach_ops(struct ath_hw *ah);
1102 void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan);
1104 void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning);
1105 void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan);
1107 void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us);
1108 void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us);
1109 void ath9k_hw_setslottime(struct ath_hw *ah, u32 us);
1111 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
1112 static inline bool ath9k_hw_btcoex_is_enabled(struct ath_hw *ah)
1114 return ah->btcoex_hw.enabled;
1116 static inline bool ath9k_hw_mci_is_enabled(struct ath_hw *ah)
1118 return ah->common.btcoex_enabled &&
1119 (ah->caps.hw_caps & ATH9K_HW_CAP_MCI);
1122 void ath9k_hw_btcoex_enable(struct ath_hw *ah);
1123 static inline enum ath_btcoex_scheme
1124 ath9k_hw_get_btcoex_scheme(struct ath_hw *ah)
1126 return ah->btcoex_hw.scheme;
1129 static inline bool ath9k_hw_btcoex_is_enabled(struct ath_hw *ah)
1133 static inline bool ath9k_hw_mci_is_enabled(struct ath_hw *ah)
1137 static inline void ath9k_hw_btcoex_enable(struct ath_hw *ah)
1140 static inline enum ath_btcoex_scheme
1141 ath9k_hw_get_btcoex_scheme(struct ath_hw *ah)
1143 return ATH_BTCOEX_CFG_NONE;
1145 #endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */
1148 #ifdef CONFIG_ATH9K_WOW
1149 const char *ath9k_hw_wow_event_to_string(u32 wow_event);
1150 void ath9k_hw_wow_apply_pattern(struct ath_hw *ah, u8 *user_pattern,
1151 u8 *user_mask, int pattern_count,
1153 u32 ath9k_hw_wow_wakeup(struct ath_hw *ah);
1154 void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable);
1156 static inline const char *ath9k_hw_wow_event_to_string(u32 wow_event)
1160 static inline void ath9k_hw_wow_apply_pattern(struct ath_hw *ah,
1167 static inline u32 ath9k_hw_wow_wakeup(struct ath_hw *ah)
1171 static inline void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable)
1176 #define ATH9K_CLOCK_RATE_CCK 22
1177 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
1178 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
1179 #define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44