2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include <linux/if_ether.h>
21 #include <linux/delay.h>
35 #define ATHEROS_VENDOR_ID 0x168c
37 #define AR5416_DEVID_PCI 0x0023
38 #define AR5416_DEVID_PCIE 0x0024
39 #define AR9160_DEVID_PCI 0x0027
40 #define AR9280_DEVID_PCI 0x0029
41 #define AR9280_DEVID_PCIE 0x002a
42 #define AR9285_DEVID_PCIE 0x002b
43 #define AR2427_DEVID_PCIE 0x002c
45 #define AR5416_AR9100_DEVID 0x000b
47 #define AR_SUBVENDOR_ID_NOG 0x0e11
48 #define AR_SUBVENDOR_ID_NEW_A 0x7065
49 #define AR5416_MAGIC 0x19641014
51 #define AR5416_DEVID_AR9287_PCI 0x002D
52 #define AR5416_DEVID_AR9287_PCIE 0x002E
54 #define AR9280_COEX2WIRE_SUBSYSID 0x309b
55 #define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa
56 #define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab
58 #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1)
60 #define ATH_DEFAULT_NOISE_FLOOR -95
62 #define ATH9K_RSSI_BAD -128
64 /* Register read/write primitives */
65 #define REG_WRITE(_ah, _reg, _val) \
66 ath9k_hw_common(_ah)->ops->write((_ah), (_val), (_reg))
68 #define REG_READ(_ah, _reg) \
69 ath9k_hw_common(_ah)->ops->read((_ah), (_reg))
71 #define SM(_v, _f) (((_v) << _f##_S) & _f)
72 #define MS(_v, _f) (((_v) & _f) >> _f##_S)
73 #define REG_RMW(_a, _r, _set, _clr) \
74 REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set))
75 #define REG_RMW_FIELD(_a, _r, _f, _v) \
77 (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))
78 #define REG_SET_BIT(_a, _r, _f) \
79 REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
80 #define REG_CLR_BIT(_a, _r, _f) \
81 REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f)
83 #define DO_DELAY(x) do { \
84 if ((++(x) % 64) == 0) \
88 #define REG_WRITE_ARRAY(iniarray, column, regWr) do { \
90 for (r = 0; r < ((iniarray)->ia_rows); r++) { \
91 REG_WRITE(ah, INI_RA((iniarray), (r), 0), \
92 INI_RA((iniarray), r, (column))); \
97 #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
98 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
99 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
100 #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3
101 #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4
102 #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
103 #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
105 #define AR_GPIOD_MASK 0x00001FFF
106 #define AR_GPIO_BIT(_gpio) (1 << (_gpio))
108 #define BASE_ACTIVATE_DELAY 100
109 #define RTC_PLL_SETTLE_DELAY 100
110 #define COEF_SCALE_S 24
111 #define HT40_CHANNEL_CENTER_SHIFT 10
113 #define ATH9K_ANTENNA0_CHAINMASK 0x1
114 #define ATH9K_ANTENNA1_CHAINMASK 0x2
116 #define ATH9K_NUM_DMA_DEBUG_REGS 8
117 #define ATH9K_NUM_QUEUES 10
119 #define MAX_RATE_POWER 63
120 #define AH_WAIT_TIMEOUT 100000 /* (us) */
121 #define AH_TSF_WRITE_TIMEOUT 100 /* (us) */
122 #define AH_TIME_QUANTUM 10
123 #define AR_KEYTABLE_SIZE 128
124 #define POWER_UP_TIME 10000
125 #define SPUR_RSSI_THRESH 40
127 #define CAB_TIMEOUT_VAL 10
128 #define BEACON_TIMEOUT_VAL 10
129 #define MIN_BEACON_TIMEOUT_VAL 1
132 #define INIT_CONFIG_STATUS 0x00000000
133 #define INIT_RSSI_THR 0x00000700
134 #define INIT_BCON_CNTRL_REG 0x00000000
136 #define TU_TO_USEC(_tu) ((_tu) << 10)
141 ATH9K_MODE_11NA_HT20,
142 ATH9K_MODE_11NG_HT20,
143 ATH9K_MODE_11NA_HT40PLUS,
144 ATH9K_MODE_11NA_HT40MINUS,
145 ATH9K_MODE_11NG_HT40PLUS,
146 ATH9K_MODE_11NG_HT40MINUS,
151 ATH9K_HW_CAP_MIC_AESCCM = BIT(0),
152 ATH9K_HW_CAP_MIC_CKIP = BIT(1),
153 ATH9K_HW_CAP_MIC_TKIP = BIT(2),
154 ATH9K_HW_CAP_CIPHER_AESCCM = BIT(3),
155 ATH9K_HW_CAP_CIPHER_CKIP = BIT(4),
156 ATH9K_HW_CAP_CIPHER_TKIP = BIT(5),
157 ATH9K_HW_CAP_VEOL = BIT(6),
158 ATH9K_HW_CAP_BSSIDMASK = BIT(7),
159 ATH9K_HW_CAP_MCAST_KEYSEARCH = BIT(8),
160 ATH9K_HW_CAP_HT = BIT(9),
161 ATH9K_HW_CAP_GTT = BIT(10),
162 ATH9K_HW_CAP_FASTCC = BIT(11),
163 ATH9K_HW_CAP_RFSILENT = BIT(12),
164 ATH9K_HW_CAP_CST = BIT(13),
165 ATH9K_HW_CAP_ENHANCEDPM = BIT(14),
166 ATH9K_HW_CAP_AUTOSLEEP = BIT(15),
167 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(16),
170 enum ath9k_capability_type {
171 ATH9K_CAP_CIPHER = 0,
173 ATH9K_CAP_TKIP_SPLIT,
176 ATH9K_CAP_MCAST_KEYSRCH,
180 struct ath9k_hw_capabilities {
181 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
182 DECLARE_BITMAP(wireless_modes, ATH9K_MODE_MAX); /* ATH9K_MODE_* */
185 u16 low_5ghz_chan, high_5ghz_chan;
186 u16 low_2ghz_chan, high_2ghz_chan;
190 u16 tx_triglevel_max;
197 struct ath9k_ops_config {
198 int dma_beacon_response_time;
199 int sw_beacon_response_time;
200 int additional_swba_backoff;
202 int cwm_ignore_extcca;
203 u8 pcie_powersave_enable;
213 int serialize_regmode;
214 bool rx_intr_mitigation;
215 #define SPUR_DISABLE 0
216 #define SPUR_ENABLE_IOCTL 1
217 #define SPUR_ENABLE_EEPROM 2
218 #define AR_EEPROM_MODAL_SPURS 5
219 #define AR_SPUR_5413_1 1640
220 #define AR_SPUR_5413_2 1200
221 #define AR_NO_SPUR 0x8000
222 #define AR_BASE_FREQ_2GHZ 2300
223 #define AR_BASE_FREQ_5GHZ 4900
224 #define AR_SPUR_FEEQ_BOUND_HT40 19
225 #define AR_SPUR_FEEQ_BOUND_HT20 10
227 u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
232 ATH9K_INT_RX = 0x00000001,
233 ATH9K_INT_RXDESC = 0x00000002,
234 ATH9K_INT_RXNOFRM = 0x00000008,
235 ATH9K_INT_RXEOL = 0x00000010,
236 ATH9K_INT_RXORN = 0x00000020,
237 ATH9K_INT_TX = 0x00000040,
238 ATH9K_INT_TXDESC = 0x00000080,
239 ATH9K_INT_TIM_TIMER = 0x00000100,
240 ATH9K_INT_TXURN = 0x00000800,
241 ATH9K_INT_MIB = 0x00001000,
242 ATH9K_INT_RXPHY = 0x00004000,
243 ATH9K_INT_RXKCM = 0x00008000,
244 ATH9K_INT_SWBA = 0x00010000,
245 ATH9K_INT_BMISS = 0x00040000,
246 ATH9K_INT_BNR = 0x00100000,
247 ATH9K_INT_TIM = 0x00200000,
248 ATH9K_INT_DTIM = 0x00400000,
249 ATH9K_INT_DTIMSYNC = 0x00800000,
250 ATH9K_INT_GPIO = 0x01000000,
251 ATH9K_INT_CABEND = 0x02000000,
252 ATH9K_INT_TSFOOR = 0x04000000,
253 ATH9K_INT_GENTIMER = 0x08000000,
254 ATH9K_INT_CST = 0x10000000,
255 ATH9K_INT_GTT = 0x20000000,
256 ATH9K_INT_FATAL = 0x40000000,
257 ATH9K_INT_GLOBAL = 0x80000000,
258 ATH9K_INT_BMISC = ATH9K_INT_TIM |
263 ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
275 ATH9K_INT_NOCARD = 0xffffffff
278 #define CHANNEL_CW_INT 0x00002
279 #define CHANNEL_CCK 0x00020
280 #define CHANNEL_OFDM 0x00040
281 #define CHANNEL_2GHZ 0x00080
282 #define CHANNEL_5GHZ 0x00100
283 #define CHANNEL_PASSIVE 0x00200
284 #define CHANNEL_DYN 0x00400
285 #define CHANNEL_HALF 0x04000
286 #define CHANNEL_QUARTER 0x08000
287 #define CHANNEL_HT20 0x10000
288 #define CHANNEL_HT40PLUS 0x20000
289 #define CHANNEL_HT40MINUS 0x40000
291 #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
292 #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
293 #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
294 #define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20)
295 #define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20)
296 #define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
297 #define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
298 #define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
299 #define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
300 #define CHANNEL_ALL \
309 struct ath9k_channel {
310 struct ieee80211_channel *chan;
315 bool oneTimeCalsDone;
318 int16_t rawNoiseFloor;
321 #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
322 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
323 (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
324 (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
325 #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
326 #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
327 #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
328 #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
329 #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
330 #define IS_CHAN_A_5MHZ_SPACED(_c) \
331 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \
332 (((_c)->channel % 20) != 0) && \
333 (((_c)->channel % 10) != 0))
335 /* These macros check chanmode and not channelFlags */
336 #define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B)
337 #define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
338 ((_c)->chanmode == CHANNEL_G_HT20))
339 #define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \
340 ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \
341 ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \
342 ((_c)->chanmode == CHANNEL_G_HT40MINUS))
343 #define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
345 enum ath9k_power_mode {
348 ATH9K_PM_NETWORK_SLEEP,
352 enum ath9k_tp_scale {
353 ATH9K_TP_SCALE_MAX = 0,
361 SER_REG_MODE_OFF = 0,
363 SER_REG_MODE_AUTO = 2,
366 struct ath9k_beacon_state {
370 #define ATH9K_BEACON_PERIOD 0x0000ffff
371 #define ATH9K_BEACON_ENA 0x00800000
372 #define ATH9K_BEACON_RESET_TSF 0x01000000
373 #define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */
376 u16 bs_cfpmaxduration;
379 u16 bs_bmissthreshold;
380 u32 bs_sleepduration;
381 u32 bs_tsfoor_threshold;
384 struct chan_centers {
391 ATH9K_RESET_POWER_ON,
396 struct ath9k_hw_version {
408 /* Generic TSF timer definitions */
410 #define ATH_MAX_GEN_TIMER 16
412 #define AR_GENTMR_BIT(_index) (1 << (_index))
415 * Using de Bruijin sequence to to look up 1's index in a 32 bit number
416 * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001
418 #define debruijn32 0x077CB531U
420 struct ath_gen_timer_configuration {
427 struct ath_gen_timer {
428 void (*trigger)(void *arg);
429 void (*overflow)(void *arg);
434 struct ath_gen_timer_table {
435 u32 gen_timer_index[32];
436 struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER];
438 unsigned long timer_bits;
444 struct ieee80211_hw *hw;
445 struct ath_common common;
446 struct ath9k_hw_version hw_version;
447 struct ath9k_ops_config config;
448 struct ath9k_hw_capabilities caps;
449 struct ath9k_channel channels[38];
450 struct ath9k_channel *curchan;
453 struct ar5416_eeprom_def def;
454 struct ar5416_eeprom_4k map4k;
455 struct ar9287_eeprom map9287;
457 const struct eeprom_ops *eep_ops;
458 enum ath9k_eep_map eep_map;
470 enum nl80211_iftype opmode;
471 enum ath9k_power_mode power_mode;
473 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
474 struct ath9k_pacal_info pacal_info;
475 struct ar5416Stats stats;
476 struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES];
478 int16_t curchan_rad_index;
479 enum ath9k_int imask;
481 u32 txok_interrupt_mask;
482 u32 txerr_interrupt_mask;
483 u32 txdesc_interrupt_mask;
484 u32 txeol_interrupt_mask;
485 u32 txurn_interrupt_mask;
490 enum ath9k_cal_types supp_cals;
491 struct ath9k_cal_list iq_caldata;
492 struct ath9k_cal_list adcgain_caldata;
493 struct ath9k_cal_list adcdc_calinitdata;
494 struct ath9k_cal_list adcdc_caldata;
495 struct ath9k_cal_list *cal_list;
496 struct ath9k_cal_list *cal_list_last;
497 struct ath9k_cal_list *cal_list_curr;
498 #define totalPowerMeasI meas0.unsign
499 #define totalPowerMeasQ meas1.unsign
500 #define totalIqCorrMeas meas2.sign
501 #define totalAdcIOddPhase meas0.unsign
502 #define totalAdcIEvenPhase meas1.unsign
503 #define totalAdcQOddPhase meas2.unsign
504 #define totalAdcQEvenPhase meas3.unsign
505 #define totalAdcDcOffsetIOddPhase meas0.sign
506 #define totalAdcDcOffsetIEvenPhase meas1.sign
507 #define totalAdcDcOffsetQOddPhase meas2.sign
508 #define totalAdcDcOffsetQEvenPhase meas3.sign
510 u32 unsign[AR5416_MAX_CHAINS];
511 int32_t sign[AR5416_MAX_CHAINS];
514 u32 unsign[AR5416_MAX_CHAINS];
515 int32_t sign[AR5416_MAX_CHAINS];
518 u32 unsign[AR5416_MAX_CHAINS];
519 int32_t sign[AR5416_MAX_CHAINS];
522 u32 unsign[AR5416_MAX_CHAINS];
523 int32_t sign[AR5416_MAX_CHAINS];
527 u32 sta_id1_defaults;
533 } enable_32kHz_clock;
535 /* Callback for radio frequency change */
536 int (*ath9k_hw_rf_set_freq)(struct ath_hw *ah, struct ath9k_channel *chan);
538 /* Callback for baseband spur frequency */
539 void (*ath9k_hw_spur_mitigate_freq)(struct ath_hw *ah,
540 struct ath9k_channel *chan);
542 /* Used to program the radio on non single-chip devices */
543 u32 *analogBank0Data;
544 u32 *analogBank1Data;
545 u32 *analogBank2Data;
546 u32 *analogBank3Data;
547 u32 *analogBank6Data;
548 u32 *analogBank6TPCData;
549 u32 *analogBank7Data;
553 int16_t txpower_indexoffset;
562 struct ar5416AniState *curani;
563 struct ar5416AniState ani[255];
564 int totalSizeDesired[5];
568 enum ath9k_ani_cmd ani_function;
570 /* Bluetooth coexistance */
571 struct ath_btcoex_hw btcoex_hw;
577 u32 originalGain[22];
582 struct ar5416IniArray iniModes;
583 struct ar5416IniArray iniCommon;
584 struct ar5416IniArray iniBank0;
585 struct ar5416IniArray iniBB_RfGain;
586 struct ar5416IniArray iniBank1;
587 struct ar5416IniArray iniBank2;
588 struct ar5416IniArray iniBank3;
589 struct ar5416IniArray iniBank6;
590 struct ar5416IniArray iniBank6TPC;
591 struct ar5416IniArray iniBank7;
592 struct ar5416IniArray iniAddac;
593 struct ar5416IniArray iniPcieSerdes;
594 struct ar5416IniArray iniModesAdditional;
595 struct ar5416IniArray iniModesRxGain;
596 struct ar5416IniArray iniModesTxGain;
597 struct ar5416IniArray iniModes_9271_1_0_only;
598 struct ar5416IniArray iniCckfirNormal;
599 struct ar5416IniArray iniCckfirJapan2484;
600 struct ar5416IniArray iniCommon_normal_cck_fir_coeff_9271;
601 struct ar5416IniArray iniCommon_japan_2484_cck_fir_coeff_9271;
602 struct ar5416IniArray iniModes_9271_ANI_reg;
603 struct ar5416IniArray iniModes_high_power_tx_gain_9271;
604 struct ar5416IniArray iniModes_normal_power_tx_gain_9271;
606 u32 intr_gen_timer_trigger;
607 u32 intr_gen_timer_thresh;
608 struct ath_gen_timer_table hw_gen_timers;
611 static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
616 static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah)
618 return &(ath9k_hw_common(ah)->regulatory);
621 /* Initialization, Detach, Reset */
622 const char *ath9k_hw_probe(u16 vendorid, u16 devid);
623 void ath9k_hw_deinit(struct ath_hw *ah);
624 int ath9k_hw_init(struct ath_hw *ah);
625 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
626 bool bChannelChange);
627 int ath9k_hw_fill_cap_info(struct ath_hw *ah);
628 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
629 u32 capability, u32 *result);
630 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
631 u32 capability, u32 setting, int *status);
633 /* Key Cache Management */
634 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry);
635 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac);
636 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
637 const struct ath9k_keyval *k,
639 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry);
641 /* GPIO / RFKILL / Antennae */
642 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio);
643 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio);
644 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
646 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val);
647 u32 ath9k_hw_getdefantenna(struct ath_hw *ah);
648 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna);
650 /* General Operation */
651 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
652 u32 ath9k_hw_reverse_bits(u32 val, u32 n);
653 bool ath9k_get_channel_edges(struct ath_hw *ah, u16 flags, u16 *low, u16 *high);
654 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
656 u32 frameLen, u16 rateix, bool shortPreamble);
657 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
658 struct ath9k_channel *chan,
659 struct chan_centers *centers);
660 u32 ath9k_hw_getrxfilter(struct ath_hw *ah);
661 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits);
662 bool ath9k_hw_phy_disable(struct ath_hw *ah);
663 bool ath9k_hw_disable(struct ath_hw *ah);
664 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit);
665 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac);
666 void ath9k_hw_setopmode(struct ath_hw *ah);
667 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
668 void ath9k_hw_setbssidmask(struct ath_hw *ah);
669 void ath9k_hw_write_associd(struct ath_hw *ah);
670 u64 ath9k_hw_gettsf64(struct ath_hw *ah);
671 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
672 void ath9k_hw_reset_tsf(struct ath_hw *ah);
673 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting);
674 u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp);
675 void ath9k_hw_init_global_settings(struct ath_hw *ah);
676 void ath9k_hw_set11nmac2040(struct ath_hw *ah);
677 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
678 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
679 const struct ath9k_beacon_state *bs);
681 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode);
683 void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off);
685 /* Interrupt Handling */
686 bool ath9k_hw_intrpend(struct ath_hw *ah);
687 bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked);
688 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints);
690 /* Generic hw timer primitives */
691 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
692 void (*trigger)(void *),
693 void (*overflow)(void *),
696 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
697 struct ath_gen_timer *timer,
700 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer);
702 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer);
703 void ath_gen_timer_isr(struct ath_hw *hw);
704 u32 ath9k_hw_gettsf32(struct ath_hw *ah);
706 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len);
709 void ath9k_hw_htc_resetinit(struct ath_hw *ah);
711 #define ATH_PCIE_CAP_LINK_CTRL 0x70
712 #define ATH_PCIE_CAP_LINK_L0S 1
713 #define ATH_PCIE_CAP_LINK_L1 2