2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19 #include <linux/dma-mapping.h>
20 #include <linux/slab.h>
21 #include <linux/ath9k_platform.h>
22 #include <linux/module.h>
23 #include <linux/relay.h>
24 #include <net/ieee80211_radiotap.h>
28 struct ath9k_eeprom_ctx {
29 struct completion complete;
33 static char *dev_info = "ath9k";
35 MODULE_AUTHOR("Atheros Communications");
36 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
37 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
38 MODULE_LICENSE("Dual BSD/GPL");
40 static unsigned int ath9k_debug = ATH_DBG_DEFAULT;
41 module_param_named(debug, ath9k_debug, uint, 0);
42 MODULE_PARM_DESC(debug, "Debugging mask");
44 int ath9k_modparam_nohwcrypt;
45 module_param_named(nohwcrypt, ath9k_modparam_nohwcrypt, int, 0444);
46 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
49 module_param_named(blink, ath9k_led_blink, int, 0444);
50 MODULE_PARM_DESC(blink, "Enable LED blink on activity");
52 static int ath9k_btcoex_enable;
53 module_param_named(btcoex_enable, ath9k_btcoex_enable, int, 0444);
54 MODULE_PARM_DESC(btcoex_enable, "Enable wifi-BT coexistence");
56 static int ath9k_bt_ant_diversity;
57 module_param_named(bt_ant_diversity, ath9k_bt_ant_diversity, int, 0444);
58 MODULE_PARM_DESC(bt_ant_diversity, "Enable WLAN/BT RX antenna diversity");
60 static int ath9k_ps_enable;
61 module_param_named(ps_enable, ath9k_ps_enable, int, 0444);
62 MODULE_PARM_DESC(ps_enable, "Enable WLAN PowerSave");
64 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
66 int ath9k_use_chanctx;
67 module_param_named(use_chanctx, ath9k_use_chanctx, int, 0444);
68 MODULE_PARM_DESC(use_chanctx, "Enable channel context for concurrency");
70 #endif /* CONFIG_ATH9K_CHANNEL_CONTEXT */
72 bool is_ath9k_unloaded;
74 #ifdef CONFIG_MAC80211_LEDS
75 static const struct ieee80211_tpt_blink ath9k_tpt_blink[] = {
76 { .throughput = 0 * 1024, .blink_time = 334 },
77 { .throughput = 1 * 1024, .blink_time = 260 },
78 { .throughput = 5 * 1024, .blink_time = 220 },
79 { .throughput = 10 * 1024, .blink_time = 190 },
80 { .throughput = 20 * 1024, .blink_time = 170 },
81 { .throughput = 50 * 1024, .blink_time = 150 },
82 { .throughput = 70 * 1024, .blink_time = 130 },
83 { .throughput = 100 * 1024, .blink_time = 110 },
84 { .throughput = 200 * 1024, .blink_time = 80 },
85 { .throughput = 300 * 1024, .blink_time = 50 },
89 static void ath9k_deinit_softc(struct ath_softc *sc);
91 static void ath9k_op_ps_wakeup(struct ath_common *common)
93 ath9k_ps_wakeup((struct ath_softc *) common->priv);
96 static void ath9k_op_ps_restore(struct ath_common *common)
98 ath9k_ps_restore((struct ath_softc *) common->priv);
101 static struct ath_ps_ops ath9k_ps_ops = {
102 .wakeup = ath9k_op_ps_wakeup,
103 .restore = ath9k_op_ps_restore,
107 * Read and write, they both share the same lock. We do this to serialize
108 * reads and writes on Atheros 802.11n PCI devices only. This is required
109 * as the FIFO on these devices can only accept sanely 2 requests.
112 static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
114 struct ath_hw *ah = (struct ath_hw *) hw_priv;
115 struct ath_common *common = ath9k_hw_common(ah);
116 struct ath_softc *sc = (struct ath_softc *) common->priv;
118 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) {
120 spin_lock_irqsave(&sc->sc_serial_rw, flags);
121 iowrite32(val, sc->mem + reg_offset);
122 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
124 iowrite32(val, sc->mem + reg_offset);
127 static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset)
129 struct ath_hw *ah = (struct ath_hw *) hw_priv;
130 struct ath_common *common = ath9k_hw_common(ah);
131 struct ath_softc *sc = (struct ath_softc *) common->priv;
134 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) {
136 spin_lock_irqsave(&sc->sc_serial_rw, flags);
137 val = ioread32(sc->mem + reg_offset);
138 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
140 val = ioread32(sc->mem + reg_offset);
144 static void ath9k_multi_ioread32(void *hw_priv, u32 *addr,
149 for (i = 0; i < count; i++)
150 val[i] = ath9k_ioread32(hw_priv, addr[i]);
154 static unsigned int __ath9k_reg_rmw(struct ath_softc *sc, u32 reg_offset,
159 val = ioread32(sc->mem + reg_offset);
162 iowrite32(val, sc->mem + reg_offset);
167 static unsigned int ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr)
169 struct ath_hw *ah = (struct ath_hw *) hw_priv;
170 struct ath_common *common = ath9k_hw_common(ah);
171 struct ath_softc *sc = (struct ath_softc *) common->priv;
172 unsigned long uninitialized_var(flags);
175 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) {
176 spin_lock_irqsave(&sc->sc_serial_rw, flags);
177 val = __ath9k_reg_rmw(sc, reg_offset, set, clr);
178 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
180 val = __ath9k_reg_rmw(sc, reg_offset, set, clr);
185 /**************************/
187 /**************************/
189 static void ath9k_reg_notifier(struct wiphy *wiphy,
190 struct regulatory_request *request)
192 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
193 struct ath_softc *sc = hw->priv;
194 struct ath_hw *ah = sc->sc_ah;
195 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
197 ath_reg_notifier_apply(wiphy, request, reg);
203 sc->cur_chan->txpower = 2 * ah->curchan->chan->max_power;
205 ath9k_hw_set_txpowerlimit(ah, sc->cur_chan->txpower, false);
206 ath9k_cmn_update_txpow(ah, sc->cur_chan->cur_txpower,
207 sc->cur_chan->txpower,
208 &sc->cur_chan->cur_txpower);
209 /* synchronize DFS detector if regulatory domain changed */
210 if (sc->dfs_detector != NULL)
211 sc->dfs_detector->set_dfs_domain(sc->dfs_detector,
212 request->dfs_region);
213 ath9k_ps_restore(sc);
217 * This function will allocate both the DMA descriptor structure, and the
218 * buffers it contains. These are used to contain the descriptors used
221 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
222 struct list_head *head, const char *name,
223 int nbuf, int ndesc, bool is_tx)
225 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
227 int i, bsize, desc_len;
229 ath_dbg(common, CONFIG, "%s DMA: %u buffers %u desc/buf\n",
232 INIT_LIST_HEAD(head);
235 desc_len = sc->sc_ah->caps.tx_desc_len;
237 desc_len = sizeof(struct ath_desc);
239 /* ath_desc must be a multiple of DWORDs */
240 if ((desc_len % 4) != 0) {
241 ath_err(common, "ath_desc not DWORD aligned\n");
242 BUG_ON((desc_len % 4) != 0);
246 dd->dd_desc_len = desc_len * nbuf * ndesc;
249 * Need additional DMA memory because we can't use
250 * descriptors that cross the 4K page boundary. Assume
251 * one skipped descriptor per 4K page.
253 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
255 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
258 while (ndesc_skipped) {
259 dma_len = ndesc_skipped * desc_len;
260 dd->dd_desc_len += dma_len;
262 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
266 /* allocate descriptors */
267 dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len,
268 &dd->dd_desc_paddr, GFP_KERNEL);
272 ds = (u8 *) dd->dd_desc;
273 ath_dbg(common, CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
274 name, ds, (u32) dd->dd_desc_len,
275 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
277 /* allocate buffers */
281 bsize = sizeof(struct ath_buf) * nbuf;
282 bf = devm_kzalloc(sc->dev, bsize, GFP_KERNEL);
286 for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) {
288 bf->bf_daddr = DS2PHYS(dd, ds);
290 if (!(sc->sc_ah->caps.hw_caps &
291 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
293 * Skip descriptor addresses which can cause 4KB
294 * boundary crossing (addr + length) with a 32 dword
297 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
298 BUG_ON((caddr_t) bf->bf_desc >=
299 ((caddr_t) dd->dd_desc +
302 ds += (desc_len * ndesc);
304 bf->bf_daddr = DS2PHYS(dd, ds);
307 list_add_tail(&bf->list, head);
310 struct ath_rxbuf *bf;
312 bsize = sizeof(struct ath_rxbuf) * nbuf;
313 bf = devm_kzalloc(sc->dev, bsize, GFP_KERNEL);
317 for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) {
319 bf->bf_daddr = DS2PHYS(dd, ds);
321 if (!(sc->sc_ah->caps.hw_caps &
322 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
324 * Skip descriptor addresses which can cause 4KB
325 * boundary crossing (addr + length) with a 32 dword
328 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
329 BUG_ON((caddr_t) bf->bf_desc >=
330 ((caddr_t) dd->dd_desc +
333 ds += (desc_len * ndesc);
335 bf->bf_daddr = DS2PHYS(dd, ds);
338 list_add_tail(&bf->list, head);
344 static int ath9k_init_queues(struct ath_softc *sc)
348 sc->beacon.beaconq = ath9k_hw_beaconq_setup(sc->sc_ah);
349 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
352 sc->tx.uapsdq = ath_txq_setup(sc, ATH9K_TX_QUEUE_UAPSD, 0);
354 for (i = 0; i < IEEE80211_NUM_ACS; i++) {
355 sc->tx.txq_map[i] = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, i);
356 sc->tx.txq_map[i]->mac80211_qnum = i;
357 sc->tx.txq_max_pending[i] = ATH_MAX_QDEPTH;
362 static void ath9k_init_misc(struct ath_softc *sc)
364 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
367 setup_timer(&common->ani.timer, ath_ani_calibrate, (unsigned long)sc);
369 common->last_rssi = ATH_RSSI_DUMMY_MARKER;
370 memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
371 sc->beacon.slottime = ATH9K_SLOT_TIME_9;
373 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++)
374 sc->beacon.bslot[i] = NULL;
376 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB)
377 sc->ant_comb.count = ATH_ANT_DIV_COMB_INIT_COUNT;
379 sc->spec_priv.ah = sc->sc_ah;
380 sc->spec_priv.spec_config.enabled = 0;
381 sc->spec_priv.spec_config.short_repeat = true;
382 sc->spec_priv.spec_config.count = 8;
383 sc->spec_priv.spec_config.endless = false;
384 sc->spec_priv.spec_config.period = 0xFF;
385 sc->spec_priv.spec_config.fft_period = 0xF;
388 static void ath9k_init_pcoem_platform(struct ath_softc *sc)
390 struct ath_hw *ah = sc->sc_ah;
391 struct ath9k_hw_capabilities *pCap = &ah->caps;
392 struct ath_common *common = ath9k_hw_common(ah);
394 if (!IS_ENABLED(CONFIG_ATH9K_PCOEM))
397 if (common->bus_ops->ath_bus_type != ATH_PCI)
400 if (sc->driver_data & (ATH9K_PCI_CUS198 |
402 ah->config.xlna_gpio = 9;
403 ah->config.xatten_margin_cfg = true;
404 ah->config.alt_mingainidx = true;
405 ah->config.ant_ctrl_comm2g_switch_enable = 0x000BBB88;
406 sc->ant_comb.low_rssi_thresh = 20;
407 sc->ant_comb.fast_div_bias = 3;
409 ath_info(common, "Set parameters for %s\n",
410 (sc->driver_data & ATH9K_PCI_CUS198) ?
411 "CUS198" : "CUS230");
414 if (sc->driver_data & ATH9K_PCI_CUS217)
415 ath_info(common, "CUS217 card detected\n");
417 if (sc->driver_data & ATH9K_PCI_CUS252)
418 ath_info(common, "CUS252 card detected\n");
420 if (sc->driver_data & ATH9K_PCI_AR9565_1ANT)
421 ath_info(common, "WB335 1-ANT card detected\n");
423 if (sc->driver_data & ATH9K_PCI_AR9565_2ANT)
424 ath_info(common, "WB335 2-ANT card detected\n");
426 if (sc->driver_data & ATH9K_PCI_KILLER)
427 ath_info(common, "Killer Wireless card detected\n");
430 * Some WB335 cards do not support antenna diversity. Since
431 * we use a hardcoded value for AR9565 instead of using the
432 * EEPROM/OTP data, remove the combining feature from
433 * the HW capabilities bitmap.
435 if (sc->driver_data & (ATH9K_PCI_AR9565_1ANT | ATH9K_PCI_AR9565_2ANT)) {
436 if (!(sc->driver_data & ATH9K_PCI_BT_ANT_DIV))
437 pCap->hw_caps &= ~ATH9K_HW_CAP_ANT_DIV_COMB;
440 if (sc->driver_data & ATH9K_PCI_BT_ANT_DIV) {
441 pCap->hw_caps |= ATH9K_HW_CAP_BT_ANT_DIV;
442 ath_info(common, "Set BT/WLAN RX diversity capability\n");
445 if (sc->driver_data & ATH9K_PCI_D3_L1_WAR) {
446 ah->config.pcie_waen = 0x0040473b;
447 ath_info(common, "Enable WAR for ASPM D3/L1\n");
451 * The default value of pll_pwrsave is 1.
452 * For certain AR9485 cards, it is set to 0.
453 * For AR9462, AR9565 it's set to 7.
455 ah->config.pll_pwrsave = 1;
457 if (sc->driver_data & ATH9K_PCI_NO_PLL_PWRSAVE) {
458 ah->config.pll_pwrsave = 0;
459 ath_info(common, "Disable PLL PowerSave\n");
462 if (sc->driver_data & ATH9K_PCI_LED_ACT_HI)
463 ah->config.led_active_high = true;
466 static void ath9k_eeprom_request_cb(const struct firmware *eeprom_blob,
469 struct ath9k_eeprom_ctx *ec = ctx;
472 ec->ah->eeprom_blob = eeprom_blob;
474 complete(&ec->complete);
477 static int ath9k_eeprom_request(struct ath_softc *sc, const char *name)
479 struct ath9k_eeprom_ctx ec;
480 struct ath_hw *ah = ah = sc->sc_ah;
483 /* try to load the EEPROM content asynchronously */
484 init_completion(&ec.complete);
487 err = request_firmware_nowait(THIS_MODULE, 1, name, sc->dev, GFP_KERNEL,
488 &ec, ath9k_eeprom_request_cb);
490 ath_err(ath9k_hw_common(ah),
491 "EEPROM request failed\n");
495 wait_for_completion(&ec.complete);
497 if (!ah->eeprom_blob) {
498 ath_err(ath9k_hw_common(ah),
499 "Unable to load EEPROM file %s\n", name);
506 static void ath9k_eeprom_release(struct ath_softc *sc)
508 release_firmware(sc->sc_ah->eeprom_blob);
511 static int ath9k_init_soc_platform(struct ath_softc *sc)
513 struct ath9k_platform_data *pdata = sc->dev->platform_data;
514 struct ath_hw *ah = sc->sc_ah;
520 if (pdata->eeprom_name) {
521 ret = ath9k_eeprom_request(sc, pdata->eeprom_name);
526 if (pdata->tx_gain_buffalo)
527 ah->config.tx_gain_buffalo = true;
532 static int ath9k_init_softc(u16 devid, struct ath_softc *sc,
533 const struct ath_bus_ops *bus_ops)
535 struct ath9k_platform_data *pdata = sc->dev->platform_data;
536 struct ath_hw *ah = NULL;
537 struct ath9k_hw_capabilities *pCap;
538 struct ath_common *common;
542 ah = devm_kzalloc(sc->dev, sizeof(struct ath_hw), GFP_KERNEL);
548 ah->hw_version.devid = devid;
549 ah->reg_ops.read = ath9k_ioread32;
550 ah->reg_ops.multi_read = ath9k_multi_ioread32;
551 ah->reg_ops.write = ath9k_iowrite32;
552 ah->reg_ops.rmw = ath9k_reg_rmw;
555 common = ath9k_hw_common(ah);
557 /* Will be cleared in ath9k_start() */
558 set_bit(ATH_OP_INVALID, &common->op_flags);
561 sc->dfs_detector = dfs_pattern_detector_init(common, NL80211_DFS_UNSET);
562 sc->tx99_power = MAX_RATE_POWER + 1;
563 init_waitqueue_head(&sc->tx_wait);
564 sc->cur_chan = &sc->chanctx[0];
565 if (!ath9k_is_chanctx_enabled())
566 sc->cur_chan->hw_queue_base = 0;
568 if (!pdata || pdata->use_eeprom) {
569 ah->ah_flags |= AH_USE_EEPROM;
570 sc->sc_ah->led_pin = -1;
572 sc->sc_ah->gpio_mask = pdata->gpio_mask;
573 sc->sc_ah->gpio_val = pdata->gpio_val;
574 sc->sc_ah->led_pin = pdata->led_pin;
575 ah->is_clk_25mhz = pdata->is_clk_25mhz;
576 ah->get_mac_revision = pdata->get_mac_revision;
577 ah->external_reset = pdata->external_reset;
578 ah->disable_2ghz = pdata->disable_2ghz;
579 ah->disable_5ghz = pdata->disable_5ghz;
580 if (!pdata->endian_check)
581 ah->ah_flags |= AH_NO_EEP_SWAP;
584 common->ops = &ah->reg_ops;
585 common->bus_ops = bus_ops;
586 common->ps_ops = &ath9k_ps_ops;
590 common->debug_mask = ath9k_debug;
591 common->btcoex_enabled = ath9k_btcoex_enable == 1;
592 common->disable_ani = false;
597 ath9k_init_pcoem_platform(sc);
599 ret = ath9k_init_soc_platform(sc);
604 * Enable WLAN/BT RX Antenna diversity only when:
606 * - BTCOEX is disabled.
607 * - the user manually requests the feature.
608 * - the HW cap is set using the platform data.
610 if (!common->btcoex_enabled && ath9k_bt_ant_diversity &&
611 (pCap->hw_caps & ATH9K_HW_CAP_BT_ANT_DIV))
612 common->bt_ant_diversity = 1;
614 spin_lock_init(&common->cc_lock);
615 spin_lock_init(&sc->sc_serial_rw);
616 spin_lock_init(&sc->sc_pm_lock);
617 spin_lock_init(&sc->chan_lock);
618 mutex_init(&sc->mutex);
619 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
620 tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet,
623 setup_timer(&sc->sleep_timer, ath_ps_full_sleep, (unsigned long)sc);
624 INIT_WORK(&sc->hw_reset_work, ath_reset_work);
625 INIT_WORK(&sc->paprd_work, ath_paprd_calibrate);
626 INIT_DELAYED_WORK(&sc->hw_pll_work, ath_hw_pll_work);
628 ath9k_init_channel_context(sc);
631 * Cache line size is used to size and align various
632 * structures used to communicate with the hardware.
634 ath_read_cachesize(common, &csz);
635 common->cachelsz = csz << 2; /* convert to bytes */
637 /* Initializes the hardware for all supported chipsets */
638 ret = ath9k_hw_init(ah);
642 if (pdata && pdata->macaddr)
643 memcpy(common->macaddr, pdata->macaddr, ETH_ALEN);
645 ret = ath9k_init_queues(sc);
649 ret = ath9k_init_btcoex(sc);
653 ret = ath9k_cmn_init_channels_rates(common);
657 ret = ath9k_init_p2p(sc);
661 ath9k_cmn_init_crypto(sc->sc_ah);
663 ath_fill_led_pin(sc);
664 ath_chanctx_init(sc);
665 ath9k_offchannel_init(sc);
667 if (common->bus_ops->aspm_init)
668 common->bus_ops->aspm_init(common);
673 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
674 if (ATH_TXQ_SETUP(sc, i))
675 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
679 ath9k_eeprom_release(sc);
680 dev_kfree_skb_any(sc->tx99_skb);
684 static void ath9k_init_band_txpower(struct ath_softc *sc, int band)
686 struct ieee80211_supported_band *sband;
687 struct ieee80211_channel *chan;
688 struct ath_hw *ah = sc->sc_ah;
689 struct ath_common *common = ath9k_hw_common(ah);
690 struct cfg80211_chan_def chandef;
693 sband = &common->sbands[band];
694 for (i = 0; i < sband->n_channels; i++) {
695 chan = &sband->channels[i];
696 ah->curchan = &ah->channels[chan->hw_value];
697 cfg80211_chandef_create(&chandef, chan, NL80211_CHAN_HT20);
698 ath9k_cmn_get_channel(sc->hw, ah, &chandef);
699 ath9k_hw_set_txpowerlimit(ah, MAX_RATE_POWER, true);
703 static void ath9k_init_txpower_limits(struct ath_softc *sc)
705 struct ath_hw *ah = sc->sc_ah;
706 struct ath9k_channel *curchan = ah->curchan;
708 if (ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
709 ath9k_init_band_txpower(sc, IEEE80211_BAND_2GHZ);
710 if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
711 ath9k_init_band_txpower(sc, IEEE80211_BAND_5GHZ);
713 ah->curchan = curchan;
716 static const struct ieee80211_iface_limit if_limits[] = {
717 { .max = 2048, .types = BIT(NL80211_IFTYPE_STATION) },
719 #ifdef CONFIG_MAC80211_MESH
720 BIT(NL80211_IFTYPE_MESH_POINT) |
722 BIT(NL80211_IFTYPE_AP) },
723 { .max = 1, .types = BIT(NL80211_IFTYPE_P2P_CLIENT) |
724 BIT(NL80211_IFTYPE_P2P_GO) },
727 static const struct ieee80211_iface_limit wds_limits[] = {
728 { .max = 2048, .types = BIT(NL80211_IFTYPE_WDS) },
731 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
733 static const struct ieee80211_iface_limit if_limits_multi[] = {
734 { .max = 2, .types = BIT(NL80211_IFTYPE_STATION) |
735 BIT(NL80211_IFTYPE_AP) |
736 BIT(NL80211_IFTYPE_P2P_CLIENT) |
737 BIT(NL80211_IFTYPE_P2P_GO) },
738 { .max = 1, .types = BIT(NL80211_IFTYPE_ADHOC) },
739 { .max = 1, .types = BIT(NL80211_IFTYPE_P2P_DEVICE) },
742 static const struct ieee80211_iface_combination if_comb_multi[] = {
744 .limits = if_limits_multi,
745 .n_limits = ARRAY_SIZE(if_limits_multi),
747 .num_different_channels = 2,
748 .beacon_int_infra_match = true,
752 #endif /* CONFIG_ATH9K_CHANNEL_CONTEXT */
754 static const struct ieee80211_iface_limit if_dfs_limits[] = {
755 { .max = 1, .types = BIT(NL80211_IFTYPE_AP) |
756 #ifdef CONFIG_MAC80211_MESH
757 BIT(NL80211_IFTYPE_MESH_POINT) |
759 BIT(NL80211_IFTYPE_ADHOC) },
762 static const struct ieee80211_iface_combination if_comb[] = {
765 .n_limits = ARRAY_SIZE(if_limits),
766 .max_interfaces = 2048,
767 .num_different_channels = 1,
768 .beacon_int_infra_match = true,
771 .limits = wds_limits,
772 .n_limits = ARRAY_SIZE(wds_limits),
773 .max_interfaces = 2048,
774 .num_different_channels = 1,
775 .beacon_int_infra_match = true,
777 #ifdef CONFIG_ATH9K_DFS_CERTIFIED
779 .limits = if_dfs_limits,
780 .n_limits = ARRAY_SIZE(if_dfs_limits),
782 .num_different_channels = 1,
783 .beacon_int_infra_match = true,
784 .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) |
785 BIT(NL80211_CHAN_WIDTH_20) |
786 BIT(NL80211_CHAN_WIDTH_40),
791 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
792 static void ath9k_set_mcc_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
794 struct ath_hw *ah = sc->sc_ah;
795 struct ath_common *common = ath9k_hw_common(ah);
797 if (!ath9k_is_chanctx_enabled())
800 ieee80211_hw_set(hw, QUEUE_CONTROL);
801 hw->queues = ATH9K_NUM_TX_QUEUES;
802 hw->offchannel_tx_hw_queue = hw->queues - 1;
803 hw->wiphy->interface_modes &= ~ BIT(NL80211_IFTYPE_WDS);
804 hw->wiphy->iface_combinations = if_comb_multi;
805 hw->wiphy->n_iface_combinations = ARRAY_SIZE(if_comb_multi);
806 hw->wiphy->max_scan_ssids = 255;
807 hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN;
808 hw->wiphy->max_remain_on_channel_duration = 10000;
809 hw->chanctx_data_size = sizeof(void *);
810 hw->extra_beacon_tailroom =
811 sizeof(struct ieee80211_p2p_noa_attr) + 9;
813 ath_dbg(common, CHAN_CTX, "Use channel contexts\n");
815 #endif /* CONFIG_ATH9K_CHANNEL_CONTEXT */
817 static void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
819 struct ath_hw *ah = sc->sc_ah;
820 struct ath_common *common = ath9k_hw_common(ah);
822 ieee80211_hw_set(hw, SUPPORTS_HT_CCK_RATES);
823 ieee80211_hw_set(hw, SUPPORTS_RC_TABLE);
824 ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS);
825 ieee80211_hw_set(hw, SPECTRUM_MGMT);
826 ieee80211_hw_set(hw, PS_NULLFUNC_STACK);
827 ieee80211_hw_set(hw, SIGNAL_DBM);
828 ieee80211_hw_set(hw, RX_INCLUDES_FCS);
829 ieee80211_hw_set(hw, HOST_BROADCAST_PS_BUFFERING);
830 ieee80211_hw_set(hw, SUPPORT_FAST_XMIT);
833 ieee80211_hw_set(hw, SUPPORTS_PS);
835 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
836 ieee80211_hw_set(hw, AMPDU_AGGREGATION);
838 if (AR_SREV_9280_20_OR_LATER(ah))
839 hw->radiotap_mcs_details |=
840 IEEE80211_RADIOTAP_MCS_HAVE_STBC;
843 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || ath9k_modparam_nohwcrypt)
844 ieee80211_hw_set(hw, MFP_CAPABLE);
846 hw->wiphy->features |= NL80211_FEATURE_ACTIVE_MONITOR |
847 NL80211_FEATURE_AP_MODE_CHAN_WIDTH_CHANGE |
848 NL80211_FEATURE_P2P_GO_CTWIN;
850 if (!config_enabled(CONFIG_ATH9K_TX99)) {
851 hw->wiphy->interface_modes =
852 BIT(NL80211_IFTYPE_P2P_GO) |
853 BIT(NL80211_IFTYPE_P2P_CLIENT) |
854 BIT(NL80211_IFTYPE_AP) |
855 BIT(NL80211_IFTYPE_STATION) |
856 BIT(NL80211_IFTYPE_ADHOC) |
857 BIT(NL80211_IFTYPE_MESH_POINT) |
858 BIT(NL80211_IFTYPE_WDS);
860 if (ath9k_is_chanctx_enabled())
861 hw->wiphy->interface_modes |=
862 BIT(NL80211_IFTYPE_P2P_DEVICE);
864 hw->wiphy->iface_combinations = if_comb;
865 hw->wiphy->n_iface_combinations = ARRAY_SIZE(if_comb);
868 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
870 hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
871 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS;
872 hw->wiphy->flags |= WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL;
873 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_5_10_MHZ;
874 hw->wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH;
875 hw->wiphy->flags |= WIPHY_FLAG_AP_UAPSD;
879 hw->max_listen_interval = 10;
880 hw->max_rate_tries = 10;
881 hw->sta_data_size = sizeof(struct ath_node);
882 hw->vif_data_size = sizeof(struct ath_vif);
883 hw->extra_tx_headroom = 4;
885 hw->wiphy->available_antennas_rx = BIT(ah->caps.max_rxchains) - 1;
886 hw->wiphy->available_antennas_tx = BIT(ah->caps.max_txchains) - 1;
888 /* single chain devices with rx diversity */
889 if (ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB)
890 hw->wiphy->available_antennas_rx = BIT(0) | BIT(1);
892 sc->ant_rx = hw->wiphy->available_antennas_rx;
893 sc->ant_tx = hw->wiphy->available_antennas_tx;
895 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
896 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
897 &common->sbands[IEEE80211_BAND_2GHZ];
898 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
899 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
900 &common->sbands[IEEE80211_BAND_5GHZ];
902 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
903 ath9k_set_mcc_capab(sc, hw);
906 ath9k_cmn_reload_chainmask(ah);
908 SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
911 int ath9k_init_device(u16 devid, struct ath_softc *sc,
912 const struct ath_bus_ops *bus_ops)
914 struct ieee80211_hw *hw = sc->hw;
915 struct ath_common *common;
918 struct ath_regulatory *reg;
920 /* Bring up device */
921 error = ath9k_init_softc(devid, sc, bus_ops);
926 common = ath9k_hw_common(ah);
927 ath9k_set_hw_capab(sc, hw);
929 /* Initialize regulatory */
930 error = ath_regd_init(&common->regulatory, sc->hw->wiphy,
935 reg = &common->regulatory;
938 error = ath_tx_init(sc, ATH_TXBUF);
943 error = ath_rx_init(sc, ATH_RXBUF);
947 ath9k_init_txpower_limits(sc);
949 #ifdef CONFIG_MAC80211_LEDS
950 /* must be initialized before ieee80211_register_hw */
951 sc->led_cdev.default_trigger = ieee80211_create_tpt_led_trigger(sc->hw,
952 IEEE80211_TPT_LEDTRIG_FL_RADIO, ath9k_tpt_blink,
953 ARRAY_SIZE(ath9k_tpt_blink));
956 /* Register with mac80211 */
957 error = ieee80211_register_hw(hw);
961 error = ath9k_init_debug(ah);
963 ath_err(common, "Unable to create debugfs files\n");
967 /* Handle world regulatory */
968 if (!ath_is_world_regd(reg)) {
969 error = regulatory_hint(hw->wiphy, reg->alpha2);
975 ath_start_rfkill_poll(sc);
980 ath9k_deinit_debug(sc);
982 ieee80211_unregister_hw(hw);
986 ath9k_deinit_softc(sc);
990 /*****************************/
991 /* De-Initialization */
992 /*****************************/
994 static void ath9k_deinit_softc(struct ath_softc *sc)
998 ath9k_deinit_p2p(sc);
999 ath9k_deinit_btcoex(sc);
1001 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1002 if (ATH_TXQ_SETUP(sc, i))
1003 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1005 del_timer_sync(&sc->sleep_timer);
1006 ath9k_hw_deinit(sc->sc_ah);
1007 if (sc->dfs_detector != NULL)
1008 sc->dfs_detector->exit(sc->dfs_detector);
1010 ath9k_eeprom_release(sc);
1013 void ath9k_deinit_device(struct ath_softc *sc)
1015 struct ieee80211_hw *hw = sc->hw;
1017 ath9k_ps_wakeup(sc);
1019 wiphy_rfkill_stop_polling(sc->hw->wiphy);
1020 ath_deinit_leds(sc);
1022 ath9k_ps_restore(sc);
1024 ath9k_deinit_debug(sc);
1025 ath9k_deinit_wow(hw);
1026 ieee80211_unregister_hw(hw);
1028 ath9k_deinit_softc(sc);
1031 /************************/
1033 /************************/
1035 static int __init ath9k_init(void)
1039 error = ath_pci_init();
1041 pr_err("No PCI devices found, driver not installed\n");
1046 error = ath_ahb_init();
1059 module_init(ath9k_init);
1061 static void __exit ath9k_exit(void)
1063 is_ath9k_unloaded = true;
1066 pr_info("%s: Driver unloaded\n", dev_info);
1068 module_exit(ath9k_exit);