2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19 #include <linux/dma-mapping.h>
20 #include <linux/slab.h>
21 #include <linux/ath9k_platform.h>
22 #include <linux/module.h>
23 #include <linux/relay.h>
24 #include <net/ieee80211_radiotap.h>
28 struct ath9k_eeprom_ctx {
29 struct completion complete;
33 static char *dev_info = "ath9k";
35 MODULE_AUTHOR("Atheros Communications");
36 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
37 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
38 MODULE_LICENSE("Dual BSD/GPL");
40 static unsigned int ath9k_debug = ATH_DBG_DEFAULT;
41 module_param_named(debug, ath9k_debug, uint, 0);
42 MODULE_PARM_DESC(debug, "Debugging mask");
44 int ath9k_modparam_nohwcrypt;
45 module_param_named(nohwcrypt, ath9k_modparam_nohwcrypt, int, 0444);
46 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
49 module_param_named(blink, led_blink, int, 0444);
50 MODULE_PARM_DESC(blink, "Enable LED blink on activity");
52 static int ath9k_btcoex_enable;
53 module_param_named(btcoex_enable, ath9k_btcoex_enable, int, 0444);
54 MODULE_PARM_DESC(btcoex_enable, "Enable wifi-BT coexistence");
56 static int ath9k_bt_ant_diversity;
57 module_param_named(bt_ant_diversity, ath9k_bt_ant_diversity, int, 0444);
58 MODULE_PARM_DESC(bt_ant_diversity, "Enable WLAN/BT RX antenna diversity");
60 bool is_ath9k_unloaded;
61 /* We use the hw_value as an index into our private channel structure */
63 #define CHAN2G(_freq, _idx) { \
64 .band = IEEE80211_BAND_2GHZ, \
65 .center_freq = (_freq), \
70 #define CHAN5G(_freq, _idx) { \
71 .band = IEEE80211_BAND_5GHZ, \
72 .center_freq = (_freq), \
77 /* Some 2 GHz radios are actually tunable on 2312-2732
78 * on 5 MHz steps, we support the channels which we know
79 * we have calibration data for all cards though to make
81 static const struct ieee80211_channel ath9k_2ghz_chantable[] = {
82 CHAN2G(2412, 0), /* Channel 1 */
83 CHAN2G(2417, 1), /* Channel 2 */
84 CHAN2G(2422, 2), /* Channel 3 */
85 CHAN2G(2427, 3), /* Channel 4 */
86 CHAN2G(2432, 4), /* Channel 5 */
87 CHAN2G(2437, 5), /* Channel 6 */
88 CHAN2G(2442, 6), /* Channel 7 */
89 CHAN2G(2447, 7), /* Channel 8 */
90 CHAN2G(2452, 8), /* Channel 9 */
91 CHAN2G(2457, 9), /* Channel 10 */
92 CHAN2G(2462, 10), /* Channel 11 */
93 CHAN2G(2467, 11), /* Channel 12 */
94 CHAN2G(2472, 12), /* Channel 13 */
95 CHAN2G(2484, 13), /* Channel 14 */
98 /* Some 5 GHz radios are actually tunable on XXXX-YYYY
99 * on 5 MHz steps, we support the channels which we know
100 * we have calibration data for all cards though to make
102 static const struct ieee80211_channel ath9k_5ghz_chantable[] = {
103 /* _We_ call this UNII 1 */
104 CHAN5G(5180, 14), /* Channel 36 */
105 CHAN5G(5200, 15), /* Channel 40 */
106 CHAN5G(5220, 16), /* Channel 44 */
107 CHAN5G(5240, 17), /* Channel 48 */
108 /* _We_ call this UNII 2 */
109 CHAN5G(5260, 18), /* Channel 52 */
110 CHAN5G(5280, 19), /* Channel 56 */
111 CHAN5G(5300, 20), /* Channel 60 */
112 CHAN5G(5320, 21), /* Channel 64 */
113 /* _We_ call this "Middle band" */
114 CHAN5G(5500, 22), /* Channel 100 */
115 CHAN5G(5520, 23), /* Channel 104 */
116 CHAN5G(5540, 24), /* Channel 108 */
117 CHAN5G(5560, 25), /* Channel 112 */
118 CHAN5G(5580, 26), /* Channel 116 */
119 CHAN5G(5600, 27), /* Channel 120 */
120 CHAN5G(5620, 28), /* Channel 124 */
121 CHAN5G(5640, 29), /* Channel 128 */
122 CHAN5G(5660, 30), /* Channel 132 */
123 CHAN5G(5680, 31), /* Channel 136 */
124 CHAN5G(5700, 32), /* Channel 140 */
125 /* _We_ call this UNII 3 */
126 CHAN5G(5745, 33), /* Channel 149 */
127 CHAN5G(5765, 34), /* Channel 153 */
128 CHAN5G(5785, 35), /* Channel 157 */
129 CHAN5G(5805, 36), /* Channel 161 */
130 CHAN5G(5825, 37), /* Channel 165 */
133 /* Atheros hardware rate code addition for short premble */
134 #define SHPCHECK(__hw_rate, __flags) \
135 ((__flags & IEEE80211_RATE_SHORT_PREAMBLE) ? (__hw_rate | 0x04 ) : 0)
137 #define RATE(_bitrate, _hw_rate, _flags) { \
138 .bitrate = (_bitrate), \
140 .hw_value = (_hw_rate), \
141 .hw_value_short = (SHPCHECK(_hw_rate, _flags)) \
144 static struct ieee80211_rate ath9k_legacy_rates[] = {
146 RATE(20, 0x1a, IEEE80211_RATE_SHORT_PREAMBLE),
147 RATE(55, 0x19, IEEE80211_RATE_SHORT_PREAMBLE),
148 RATE(110, 0x18, IEEE80211_RATE_SHORT_PREAMBLE),
149 RATE(60, 0x0b, (IEEE80211_RATE_SUPPORTS_5MHZ |
150 IEEE80211_RATE_SUPPORTS_10MHZ)),
151 RATE(90, 0x0f, (IEEE80211_RATE_SUPPORTS_5MHZ |
152 IEEE80211_RATE_SUPPORTS_10MHZ)),
153 RATE(120, 0x0a, (IEEE80211_RATE_SUPPORTS_5MHZ |
154 IEEE80211_RATE_SUPPORTS_10MHZ)),
155 RATE(180, 0x0e, (IEEE80211_RATE_SUPPORTS_5MHZ |
156 IEEE80211_RATE_SUPPORTS_10MHZ)),
157 RATE(240, 0x09, (IEEE80211_RATE_SUPPORTS_5MHZ |
158 IEEE80211_RATE_SUPPORTS_10MHZ)),
159 RATE(360, 0x0d, (IEEE80211_RATE_SUPPORTS_5MHZ |
160 IEEE80211_RATE_SUPPORTS_10MHZ)),
161 RATE(480, 0x08, (IEEE80211_RATE_SUPPORTS_5MHZ |
162 IEEE80211_RATE_SUPPORTS_10MHZ)),
163 RATE(540, 0x0c, (IEEE80211_RATE_SUPPORTS_5MHZ |
164 IEEE80211_RATE_SUPPORTS_10MHZ)),
167 #ifdef CONFIG_MAC80211_LEDS
168 static const struct ieee80211_tpt_blink ath9k_tpt_blink[] = {
169 { .throughput = 0 * 1024, .blink_time = 334 },
170 { .throughput = 1 * 1024, .blink_time = 260 },
171 { .throughput = 5 * 1024, .blink_time = 220 },
172 { .throughput = 10 * 1024, .blink_time = 190 },
173 { .throughput = 20 * 1024, .blink_time = 170 },
174 { .throughput = 50 * 1024, .blink_time = 150 },
175 { .throughput = 70 * 1024, .blink_time = 130 },
176 { .throughput = 100 * 1024, .blink_time = 110 },
177 { .throughput = 200 * 1024, .blink_time = 80 },
178 { .throughput = 300 * 1024, .blink_time = 50 },
182 static void ath9k_deinit_softc(struct ath_softc *sc);
185 * Read and write, they both share the same lock. We do this to serialize
186 * reads and writes on Atheros 802.11n PCI devices only. This is required
187 * as the FIFO on these devices can only accept sanely 2 requests.
190 static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
192 struct ath_hw *ah = (struct ath_hw *) hw_priv;
193 struct ath_common *common = ath9k_hw_common(ah);
194 struct ath_softc *sc = (struct ath_softc *) common->priv;
196 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) {
198 spin_lock_irqsave(&sc->sc_serial_rw, flags);
199 iowrite32(val, sc->mem + reg_offset);
200 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
202 iowrite32(val, sc->mem + reg_offset);
205 static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset)
207 struct ath_hw *ah = (struct ath_hw *) hw_priv;
208 struct ath_common *common = ath9k_hw_common(ah);
209 struct ath_softc *sc = (struct ath_softc *) common->priv;
212 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) {
214 spin_lock_irqsave(&sc->sc_serial_rw, flags);
215 val = ioread32(sc->mem + reg_offset);
216 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
218 val = ioread32(sc->mem + reg_offset);
222 static unsigned int __ath9k_reg_rmw(struct ath_softc *sc, u32 reg_offset,
227 val = ioread32(sc->mem + reg_offset);
230 iowrite32(val, sc->mem + reg_offset);
235 static unsigned int ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr)
237 struct ath_hw *ah = (struct ath_hw *) hw_priv;
238 struct ath_common *common = ath9k_hw_common(ah);
239 struct ath_softc *sc = (struct ath_softc *) common->priv;
240 unsigned long uninitialized_var(flags);
243 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) {
244 spin_lock_irqsave(&sc->sc_serial_rw, flags);
245 val = __ath9k_reg_rmw(sc, reg_offset, set, clr);
246 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
248 val = __ath9k_reg_rmw(sc, reg_offset, set, clr);
253 /**************************/
255 /**************************/
257 static void setup_ht_cap(struct ath_softc *sc,
258 struct ieee80211_sta_ht_cap *ht_info)
260 struct ath_hw *ah = sc->sc_ah;
261 struct ath_common *common = ath9k_hw_common(ah);
262 u8 tx_streams, rx_streams;
265 ht_info->ht_supported = true;
266 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
267 IEEE80211_HT_CAP_SM_PS |
268 IEEE80211_HT_CAP_SGI_40 |
269 IEEE80211_HT_CAP_DSSSCCK40;
271 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_LDPC)
272 ht_info->cap |= IEEE80211_HT_CAP_LDPC_CODING;
274 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_SGI_20)
275 ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
277 ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
278 ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
280 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah))
282 else if (AR_SREV_9462(ah))
284 else if (AR_SREV_9300_20_OR_LATER(ah))
289 if (AR_SREV_9280_20_OR_LATER(ah)) {
290 if (max_streams >= 2)
291 ht_info->cap |= IEEE80211_HT_CAP_TX_STBC;
292 ht_info->cap |= (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT);
295 /* set up supported mcs set */
296 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
297 tx_streams = ath9k_cmn_count_streams(ah->txchainmask, max_streams);
298 rx_streams = ath9k_cmn_count_streams(ah->rxchainmask, max_streams);
300 ath_dbg(common, CONFIG, "TX streams %d, RX streams: %d\n",
301 tx_streams, rx_streams);
303 if (tx_streams != rx_streams) {
304 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
305 ht_info->mcs.tx_params |= ((tx_streams - 1) <<
306 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
309 for (i = 0; i < rx_streams; i++)
310 ht_info->mcs.rx_mask[i] = 0xff;
312 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
315 static void ath9k_reg_notifier(struct wiphy *wiphy,
316 struct regulatory_request *request)
318 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
319 struct ath_softc *sc = hw->priv;
320 struct ath_hw *ah = sc->sc_ah;
321 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
323 ath_reg_notifier_apply(wiphy, request, reg);
327 sc->config.txpowlimit = 2 * ah->curchan->chan->max_power;
329 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit, false);
330 sc->curtxpow = ath9k_hw_regulatory(ah)->power_limit;
331 /* synchronize DFS detector if regulatory domain changed */
332 if (sc->dfs_detector != NULL)
333 sc->dfs_detector->set_dfs_domain(sc->dfs_detector,
334 request->dfs_region);
335 ath9k_ps_restore(sc);
340 * This function will allocate both the DMA descriptor structure, and the
341 * buffers it contains. These are used to contain the descriptors used
344 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
345 struct list_head *head, const char *name,
346 int nbuf, int ndesc, bool is_tx)
348 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
350 int i, bsize, desc_len;
352 ath_dbg(common, CONFIG, "%s DMA: %u buffers %u desc/buf\n",
355 INIT_LIST_HEAD(head);
358 desc_len = sc->sc_ah->caps.tx_desc_len;
360 desc_len = sizeof(struct ath_desc);
362 /* ath_desc must be a multiple of DWORDs */
363 if ((desc_len % 4) != 0) {
364 ath_err(common, "ath_desc not DWORD aligned\n");
365 BUG_ON((desc_len % 4) != 0);
369 dd->dd_desc_len = desc_len * nbuf * ndesc;
372 * Need additional DMA memory because we can't use
373 * descriptors that cross the 4K page boundary. Assume
374 * one skipped descriptor per 4K page.
376 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
378 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
381 while (ndesc_skipped) {
382 dma_len = ndesc_skipped * desc_len;
383 dd->dd_desc_len += dma_len;
385 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
389 /* allocate descriptors */
390 dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len,
391 &dd->dd_desc_paddr, GFP_KERNEL);
395 ds = (u8 *) dd->dd_desc;
396 ath_dbg(common, CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
397 name, ds, (u32) dd->dd_desc_len,
398 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
400 /* allocate buffers */
404 bsize = sizeof(struct ath_buf) * nbuf;
405 bf = devm_kzalloc(sc->dev, bsize, GFP_KERNEL);
409 for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) {
411 bf->bf_daddr = DS2PHYS(dd, ds);
413 if (!(sc->sc_ah->caps.hw_caps &
414 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
416 * Skip descriptor addresses which can cause 4KB
417 * boundary crossing (addr + length) with a 32 dword
420 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
421 BUG_ON((caddr_t) bf->bf_desc >=
422 ((caddr_t) dd->dd_desc +
425 ds += (desc_len * ndesc);
427 bf->bf_daddr = DS2PHYS(dd, ds);
430 list_add_tail(&bf->list, head);
433 struct ath_rxbuf *bf;
435 bsize = sizeof(struct ath_rxbuf) * nbuf;
436 bf = devm_kzalloc(sc->dev, bsize, GFP_KERNEL);
440 for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) {
442 bf->bf_daddr = DS2PHYS(dd, ds);
444 if (!(sc->sc_ah->caps.hw_caps &
445 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
447 * Skip descriptor addresses which can cause 4KB
448 * boundary crossing (addr + length) with a 32 dword
451 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
452 BUG_ON((caddr_t) bf->bf_desc >=
453 ((caddr_t) dd->dd_desc +
456 ds += (desc_len * ndesc);
458 bf->bf_daddr = DS2PHYS(dd, ds);
461 list_add_tail(&bf->list, head);
467 static int ath9k_init_queues(struct ath_softc *sc)
471 sc->beacon.beaconq = ath9k_hw_beaconq_setup(sc->sc_ah);
472 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
474 sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
477 sc->tx.uapsdq = ath_txq_setup(sc, ATH9K_TX_QUEUE_UAPSD, 0);
479 for (i = 0; i < IEEE80211_NUM_ACS; i++) {
480 sc->tx.txq_map[i] = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, i);
481 sc->tx.txq_map[i]->mac80211_qnum = i;
482 sc->tx.txq_max_pending[i] = ATH_MAX_QDEPTH;
487 static int ath9k_init_channels_rates(struct ath_softc *sc)
491 BUILD_BUG_ON(ARRAY_SIZE(ath9k_2ghz_chantable) +
492 ARRAY_SIZE(ath9k_5ghz_chantable) !=
495 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) {
496 channels = devm_kzalloc(sc->dev,
497 sizeof(ath9k_2ghz_chantable), GFP_KERNEL);
501 memcpy(channels, ath9k_2ghz_chantable,
502 sizeof(ath9k_2ghz_chantable));
503 sc->sbands[IEEE80211_BAND_2GHZ].channels = channels;
504 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
505 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
506 ARRAY_SIZE(ath9k_2ghz_chantable);
507 sc->sbands[IEEE80211_BAND_2GHZ].bitrates = ath9k_legacy_rates;
508 sc->sbands[IEEE80211_BAND_2GHZ].n_bitrates =
509 ARRAY_SIZE(ath9k_legacy_rates);
512 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) {
513 channels = devm_kzalloc(sc->dev,
514 sizeof(ath9k_5ghz_chantable), GFP_KERNEL);
518 memcpy(channels, ath9k_5ghz_chantable,
519 sizeof(ath9k_5ghz_chantable));
520 sc->sbands[IEEE80211_BAND_5GHZ].channels = channels;
521 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
522 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
523 ARRAY_SIZE(ath9k_5ghz_chantable);
524 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
525 ath9k_legacy_rates + 4;
526 sc->sbands[IEEE80211_BAND_5GHZ].n_bitrates =
527 ARRAY_SIZE(ath9k_legacy_rates) - 4;
532 static void ath9k_init_misc(struct ath_softc *sc)
534 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
537 setup_timer(&common->ani.timer, ath_ani_calibrate, (unsigned long)sc);
539 sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
540 sc->config.txpowlimit = ATH_TXPOWER_MAX;
541 memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
542 sc->beacon.slottime = ATH9K_SLOT_TIME_9;
544 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++)
545 sc->beacon.bslot[i] = NULL;
547 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB)
548 sc->ant_comb.count = ATH_ANT_DIV_COMB_INIT_COUNT;
550 sc->spec_config.enabled = 0;
551 sc->spec_config.short_repeat = true;
552 sc->spec_config.count = 8;
553 sc->spec_config.endless = false;
554 sc->spec_config.period = 0xFF;
555 sc->spec_config.fft_period = 0xF;
558 static void ath9k_init_platform(struct ath_softc *sc)
560 struct ath_hw *ah = sc->sc_ah;
561 struct ath9k_hw_capabilities *pCap = &ah->caps;
562 struct ath_common *common = ath9k_hw_common(ah);
564 if (common->bus_ops->ath_bus_type != ATH_PCI)
567 if (sc->driver_data & (ATH9K_PCI_CUS198 |
569 ah->config.xlna_gpio = 9;
570 ah->config.xatten_margin_cfg = true;
571 ah->config.alt_mingainidx = true;
572 ah->config.ant_ctrl_comm2g_switch_enable = 0x000BBB88;
573 sc->ant_comb.low_rssi_thresh = 20;
574 sc->ant_comb.fast_div_bias = 3;
576 ath_info(common, "Set parameters for %s\n",
577 (sc->driver_data & ATH9K_PCI_CUS198) ?
578 "CUS198" : "CUS230");
581 if (sc->driver_data & ATH9K_PCI_CUS217)
582 ath_info(common, "CUS217 card detected\n");
584 if (sc->driver_data & ATH9K_PCI_CUS252)
585 ath_info(common, "CUS252 card detected\n");
587 if (sc->driver_data & ATH9K_PCI_AR9565_1ANT)
588 ath_info(common, "WB335 1-ANT card detected\n");
590 if (sc->driver_data & ATH9K_PCI_AR9565_2ANT)
591 ath_info(common, "WB335 2-ANT card detected\n");
594 * Some WB335 cards do not support antenna diversity. Since
595 * we use a hardcoded value for AR9565 instead of using the
596 * EEPROM/OTP data, remove the combining feature from
597 * the HW capabilities bitmap.
599 if (sc->driver_data & (ATH9K_PCI_AR9565_1ANT | ATH9K_PCI_AR9565_2ANT)) {
600 if (!(sc->driver_data & ATH9K_PCI_BT_ANT_DIV))
601 pCap->hw_caps &= ~ATH9K_HW_CAP_ANT_DIV_COMB;
604 if (sc->driver_data & ATH9K_PCI_BT_ANT_DIV) {
605 pCap->hw_caps |= ATH9K_HW_CAP_BT_ANT_DIV;
606 ath_info(common, "Set BT/WLAN RX diversity capability\n");
609 if (sc->driver_data & ATH9K_PCI_D3_L1_WAR) {
610 ah->config.pcie_waen = 0x0040473b;
611 ath_info(common, "Enable WAR for ASPM D3/L1\n");
615 static void ath9k_eeprom_request_cb(const struct firmware *eeprom_blob,
618 struct ath9k_eeprom_ctx *ec = ctx;
621 ec->ah->eeprom_blob = eeprom_blob;
623 complete(&ec->complete);
626 static int ath9k_eeprom_request(struct ath_softc *sc, const char *name)
628 struct ath9k_eeprom_ctx ec;
629 struct ath_hw *ah = ah = sc->sc_ah;
632 /* try to load the EEPROM content asynchronously */
633 init_completion(&ec.complete);
636 err = request_firmware_nowait(THIS_MODULE, 1, name, sc->dev, GFP_KERNEL,
637 &ec, ath9k_eeprom_request_cb);
639 ath_err(ath9k_hw_common(ah),
640 "EEPROM request failed\n");
644 wait_for_completion(&ec.complete);
646 if (!ah->eeprom_blob) {
647 ath_err(ath9k_hw_common(ah),
648 "Unable to load EEPROM file %s\n", name);
655 static void ath9k_eeprom_release(struct ath_softc *sc)
657 release_firmware(sc->sc_ah->eeprom_blob);
660 static int ath9k_init_softc(u16 devid, struct ath_softc *sc,
661 const struct ath_bus_ops *bus_ops)
663 struct ath9k_platform_data *pdata = sc->dev->platform_data;
664 struct ath_hw *ah = NULL;
665 struct ath9k_hw_capabilities *pCap;
666 struct ath_common *common;
670 ah = devm_kzalloc(sc->dev, sizeof(struct ath_hw), GFP_KERNEL);
676 ah->hw_version.devid = devid;
677 ah->reg_ops.read = ath9k_ioread32;
678 ah->reg_ops.write = ath9k_iowrite32;
679 ah->reg_ops.rmw = ath9k_reg_rmw;
680 atomic_set(&ah->intr_ref_cnt, -1);
684 sc->dfs_detector = dfs_pattern_detector_init(ah, NL80211_DFS_UNSET);
687 ah->ah_flags |= AH_USE_EEPROM;
688 sc->sc_ah->led_pin = -1;
690 sc->sc_ah->gpio_mask = pdata->gpio_mask;
691 sc->sc_ah->gpio_val = pdata->gpio_val;
692 sc->sc_ah->led_pin = pdata->led_pin;
693 ah->is_clk_25mhz = pdata->is_clk_25mhz;
694 ah->get_mac_revision = pdata->get_mac_revision;
695 ah->external_reset = pdata->external_reset;
698 common = ath9k_hw_common(ah);
699 common->ops = &ah->reg_ops;
700 common->bus_ops = bus_ops;
704 common->debug_mask = ath9k_debug;
705 common->btcoex_enabled = ath9k_btcoex_enable == 1;
706 common->disable_ani = false;
711 ath9k_init_platform(sc);
714 * Enable WLAN/BT RX Antenna diversity only when:
716 * - BTCOEX is disabled.
717 * - the user manually requests the feature.
718 * - the HW cap is set using the platform data.
720 if (!common->btcoex_enabled && ath9k_bt_ant_diversity &&
721 (pCap->hw_caps & ATH9K_HW_CAP_BT_ANT_DIV))
722 common->bt_ant_diversity = 1;
724 spin_lock_init(&common->cc_lock);
726 spin_lock_init(&sc->sc_serial_rw);
727 spin_lock_init(&sc->sc_pm_lock);
728 mutex_init(&sc->mutex);
729 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
730 tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet,
733 INIT_WORK(&sc->hw_reset_work, ath_reset_work);
734 INIT_WORK(&sc->hw_check_work, ath_hw_check);
735 INIT_WORK(&sc->paprd_work, ath_paprd_calibrate);
736 INIT_DELAYED_WORK(&sc->hw_pll_work, ath_hw_pll_work);
737 setup_timer(&sc->rx_poll_timer, ath_rx_poll, (unsigned long)sc);
740 * Cache line size is used to size and align various
741 * structures used to communicate with the hardware.
743 ath_read_cachesize(common, &csz);
744 common->cachelsz = csz << 2; /* convert to bytes */
746 if (pdata && pdata->eeprom_name) {
747 ret = ath9k_eeprom_request(sc, pdata->eeprom_name);
752 /* Initializes the hardware for all supported chipsets */
753 ret = ath9k_hw_init(ah);
757 if (pdata && pdata->macaddr)
758 memcpy(common->macaddr, pdata->macaddr, ETH_ALEN);
760 ret = ath9k_init_queues(sc);
764 ret = ath9k_init_btcoex(sc);
768 ret = ath9k_init_channels_rates(sc);
772 ath9k_cmn_init_crypto(sc->sc_ah);
774 ath_fill_led_pin(sc);
776 if (common->bus_ops->aspm_init)
777 common->bus_ops->aspm_init(common);
782 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
783 if (ATH_TXQ_SETUP(sc, i))
784 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
788 ath9k_eeprom_release(sc);
792 static void ath9k_init_band_txpower(struct ath_softc *sc, int band)
794 struct ieee80211_supported_band *sband;
795 struct ieee80211_channel *chan;
796 struct ath_hw *ah = sc->sc_ah;
797 struct cfg80211_chan_def chandef;
800 sband = &sc->sbands[band];
801 for (i = 0; i < sband->n_channels; i++) {
802 chan = &sband->channels[i];
803 ah->curchan = &ah->channels[chan->hw_value];
804 cfg80211_chandef_create(&chandef, chan, NL80211_CHAN_HT20);
805 ath9k_cmn_get_channel(sc->hw, ah, &chandef);
806 ath9k_hw_set_txpowerlimit(ah, MAX_RATE_POWER, true);
810 static void ath9k_init_txpower_limits(struct ath_softc *sc)
812 struct ath_hw *ah = sc->sc_ah;
813 struct ath9k_channel *curchan = ah->curchan;
815 if (ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
816 ath9k_init_band_txpower(sc, IEEE80211_BAND_2GHZ);
817 if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
818 ath9k_init_band_txpower(sc, IEEE80211_BAND_5GHZ);
820 ah->curchan = curchan;
823 void ath9k_reload_chainmask_settings(struct ath_softc *sc)
825 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT))
828 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
829 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
830 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
831 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
834 static const struct ieee80211_iface_limit if_limits[] = {
835 { .max = 2048, .types = BIT(NL80211_IFTYPE_STATION) |
836 BIT(NL80211_IFTYPE_P2P_CLIENT) |
837 BIT(NL80211_IFTYPE_WDS) },
839 #ifdef CONFIG_MAC80211_MESH
840 BIT(NL80211_IFTYPE_MESH_POINT) |
842 BIT(NL80211_IFTYPE_AP) |
843 BIT(NL80211_IFTYPE_P2P_GO) },
847 static const struct ieee80211_iface_limit if_dfs_limits[] = {
848 { .max = 1, .types = BIT(NL80211_IFTYPE_AP) },
851 static const struct ieee80211_iface_combination if_comb[] = {
854 .n_limits = ARRAY_SIZE(if_limits),
855 .max_interfaces = 2048,
856 .num_different_channels = 1,
857 .beacon_int_infra_match = true,
860 .limits = if_dfs_limits,
861 .n_limits = ARRAY_SIZE(if_dfs_limits),
863 .num_different_channels = 1,
864 .beacon_int_infra_match = true,
865 .radar_detect_widths = BIT(NL80211_CHAN_NO_HT) |
866 BIT(NL80211_CHAN_HT20),
871 static const struct wiphy_wowlan_support ath9k_wowlan_support = {
872 .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT,
873 .n_patterns = MAX_NUM_USER_PATTERN,
874 .pattern_min_len = 1,
875 .pattern_max_len = MAX_PATTERN_SIZE,
879 void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
881 struct ath_hw *ah = sc->sc_ah;
882 struct ath_common *common = ath9k_hw_common(ah);
884 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
885 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
886 IEEE80211_HW_SIGNAL_DBM |
887 IEEE80211_HW_SUPPORTS_PS |
888 IEEE80211_HW_PS_NULLFUNC_STACK |
889 IEEE80211_HW_SPECTRUM_MGMT |
890 IEEE80211_HW_REPORTS_TX_ACK_STATUS |
891 IEEE80211_HW_SUPPORTS_RC_TABLE |
892 IEEE80211_HW_SUPPORTS_HT_CCK_RATES;
894 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
895 hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION;
897 if (AR_SREV_9280_20_OR_LATER(ah))
898 hw->radiotap_mcs_details |=
899 IEEE80211_RADIOTAP_MCS_HAVE_STBC;
902 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || ath9k_modparam_nohwcrypt)
903 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
905 hw->wiphy->features |= NL80211_FEATURE_ACTIVE_MONITOR;
907 hw->wiphy->interface_modes =
908 BIT(NL80211_IFTYPE_P2P_GO) |
909 BIT(NL80211_IFTYPE_P2P_CLIENT) |
910 BIT(NL80211_IFTYPE_AP) |
911 BIT(NL80211_IFTYPE_WDS) |
912 BIT(NL80211_IFTYPE_STATION) |
913 BIT(NL80211_IFTYPE_ADHOC) |
914 BIT(NL80211_IFTYPE_MESH_POINT);
916 hw->wiphy->iface_combinations = if_comb;
917 hw->wiphy->n_iface_combinations = ARRAY_SIZE(if_comb);
919 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
921 hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
922 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS;
923 hw->wiphy->flags |= WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL;
924 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_5_10_MHZ;
925 hw->wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH;
927 #ifdef CONFIG_PM_SLEEP
928 if ((ah->caps.hw_caps & ATH9K_HW_WOW_DEVICE_CAPABLE) &&
929 (sc->driver_data & ATH9K_PCI_WOW) &&
930 device_can_wakeup(sc->dev))
931 hw->wiphy->wowlan = &ath9k_wowlan_support;
933 atomic_set(&sc->wow_sleep_proc_intr, -1);
934 atomic_set(&sc->wow_got_bmiss_intr, -1);
939 hw->channel_change_time = 5000;
940 hw->max_listen_interval = 1;
941 hw->max_rate_tries = 10;
942 hw->sta_data_size = sizeof(struct ath_node);
943 hw->vif_data_size = sizeof(struct ath_vif);
945 hw->wiphy->available_antennas_rx = BIT(ah->caps.max_rxchains) - 1;
946 hw->wiphy->available_antennas_tx = BIT(ah->caps.max_txchains) - 1;
948 /* single chain devices with rx diversity */
949 if (ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB)
950 hw->wiphy->available_antennas_rx = BIT(0) | BIT(1);
952 sc->ant_rx = hw->wiphy->available_antennas_rx;
953 sc->ant_tx = hw->wiphy->available_antennas_tx;
955 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
956 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
957 &sc->sbands[IEEE80211_BAND_2GHZ];
958 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
959 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
960 &sc->sbands[IEEE80211_BAND_5GHZ];
962 ath9k_reload_chainmask_settings(sc);
964 SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
967 int ath9k_init_device(u16 devid, struct ath_softc *sc,
968 const struct ath_bus_ops *bus_ops)
970 struct ieee80211_hw *hw = sc->hw;
971 struct ath_common *common;
974 struct ath_regulatory *reg;
976 /* Bring up device */
977 error = ath9k_init_softc(devid, sc, bus_ops);
982 common = ath9k_hw_common(ah);
983 ath9k_set_hw_capab(sc, hw);
985 /* Initialize regulatory */
986 error = ath_regd_init(&common->regulatory, sc->hw->wiphy,
991 reg = &common->regulatory;
994 error = ath_tx_init(sc, ATH_TXBUF);
999 error = ath_rx_init(sc, ATH_RXBUF);
1003 ath9k_init_txpower_limits(sc);
1005 #ifdef CONFIG_MAC80211_LEDS
1006 /* must be initialized before ieee80211_register_hw */
1007 sc->led_cdev.default_trigger = ieee80211_create_tpt_led_trigger(sc->hw,
1008 IEEE80211_TPT_LEDTRIG_FL_RADIO, ath9k_tpt_blink,
1009 ARRAY_SIZE(ath9k_tpt_blink));
1012 /* Register with mac80211 */
1013 error = ieee80211_register_hw(hw);
1017 error = ath9k_init_debug(ah);
1019 ath_err(common, "Unable to create debugfs files\n");
1023 /* Handle world regulatory */
1024 if (!ath_is_world_regd(reg)) {
1025 error = regulatory_hint(hw->wiphy, reg->alpha2);
1031 ath_start_rfkill_poll(sc);
1036 ath9k_deinit_debug(sc);
1038 ieee80211_unregister_hw(hw);
1042 ath9k_deinit_softc(sc);
1046 /*****************************/
1047 /* De-Initialization */
1048 /*****************************/
1050 static void ath9k_deinit_softc(struct ath_softc *sc)
1054 ath9k_deinit_btcoex(sc);
1056 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1057 if (ATH_TXQ_SETUP(sc, i))
1058 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1060 ath9k_hw_deinit(sc->sc_ah);
1061 if (sc->dfs_detector != NULL)
1062 sc->dfs_detector->exit(sc->dfs_detector);
1064 ath9k_eeprom_release(sc);
1067 void ath9k_deinit_device(struct ath_softc *sc)
1069 struct ieee80211_hw *hw = sc->hw;
1071 ath9k_ps_wakeup(sc);
1073 wiphy_rfkill_stop_polling(sc->hw->wiphy);
1074 ath_deinit_leds(sc);
1076 ath9k_ps_restore(sc);
1078 ath9k_deinit_debug(sc);
1079 ieee80211_unregister_hw(hw);
1081 ath9k_deinit_softc(sc);
1084 /************************/
1086 /************************/
1088 static int __init ath9k_init(void)
1092 /* Register rate control algorithm */
1093 error = ath_rate_control_register();
1095 pr_err("Unable to register rate control algorithm: %d\n",
1100 error = ath_pci_init();
1102 pr_err("No PCI devices found, driver not installed\n");
1104 goto err_rate_unregister;
1107 error = ath_ahb_init();
1118 err_rate_unregister:
1119 ath_rate_control_unregister();
1123 module_init(ath9k_init);
1125 static void __exit ath9k_exit(void)
1127 is_ath9k_unloaded = true;
1130 ath_rate_control_unregister();
1131 pr_info("%s: Driver unloaded\n", dev_info);
1133 module_exit(ath9k_exit);