2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19 #include <linux/nl80211.h>
20 #include <linux/pci.h>
21 #include <linux/pci-aspm.h>
22 #include <linux/ath9k_platform.h>
23 #include <linux/module.h>
26 static DEFINE_PCI_DEVICE_TABLE(ath_pci_id_table) = {
27 { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */
28 { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
29 { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */
30 { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */
31 { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
33 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
37 .driver_data = ATH9K_PCI_D3_L1_WAR },
38 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
40 PCI_VENDOR_ID_FOXCONN,
42 .driver_data = ATH9K_PCI_D3_L1_WAR },
43 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
47 .driver_data = ATH9K_PCI_D3_L1_WAR },
48 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
52 .driver_data = ATH9K_PCI_D3_L1_WAR },
53 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
57 .driver_data = ATH9K_PCI_D3_L1_WAR },
58 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
62 .driver_data = ATH9K_PCI_D3_L1_WAR },
63 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
67 .driver_data = ATH9K_PCI_D3_L1_WAR },
68 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
72 .driver_data = ATH9K_PCI_D3_L1_WAR },
73 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
77 .driver_data = ATH9K_PCI_D3_L1_WAR },
79 /* AR9285 card for Asus */
80 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
84 .driver_data = ATH9K_PCI_BT_ANT_DIV },
86 { PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */
87 { PCI_VDEVICE(ATHEROS, 0x002C) }, /* PCI-E 802.11n bonded out */
88 { PCI_VDEVICE(ATHEROS, 0x002D) }, /* PCI */
89 { PCI_VDEVICE(ATHEROS, 0x002E) }, /* PCI-E */
90 { PCI_VDEVICE(ATHEROS, 0x0030) }, /* PCI-E AR9300 */
93 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
97 .driver_data = ATH9K_PCI_CUS198 | ATH9K_PCI_BT_ANT_DIV },
98 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
100 PCI_VENDOR_ID_AZWAVE,
102 .driver_data = ATH9K_PCI_CUS198 | ATH9K_PCI_BT_ANT_DIV },
103 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
105 PCI_VENDOR_ID_AZWAVE,
107 .driver_data = ATH9K_PCI_CUS198 | ATH9K_PCI_BT_ANT_DIV },
108 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
110 PCI_VENDOR_ID_AZWAVE,
112 .driver_data = ATH9K_PCI_CUS198 | ATH9K_PCI_BT_ANT_DIV },
115 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
117 PCI_VENDOR_ID_AZWAVE,
119 .driver_data = ATH9K_PCI_CUS230 | ATH9K_PCI_BT_ANT_DIV },
120 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
122 PCI_VENDOR_ID_FOXCONN,
124 .driver_data = ATH9K_PCI_CUS230 | ATH9K_PCI_BT_ANT_DIV },
127 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
129 PCI_VENDOR_ID_ATHEROS,
131 .driver_data = ATH9K_PCI_BT_ANT_DIV },
132 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
134 PCI_VENDOR_ID_ATHEROS,
136 .driver_data = ATH9K_PCI_BT_ANT_DIV },
137 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
141 .driver_data = ATH9K_PCI_BT_ANT_DIV },
142 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
146 .driver_data = ATH9K_PCI_BT_ANT_DIV },
147 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
149 PCI_VENDOR_ID_SAMSUNG,
151 .driver_data = ATH9K_PCI_BT_ANT_DIV },
152 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
154 PCI_VENDOR_ID_SAMSUNG,
156 .driver_data = ATH9K_PCI_BT_ANT_DIV },
157 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
159 PCI_VENDOR_ID_SAMSUNG,
161 .driver_data = ATH9K_PCI_BT_ANT_DIV },
162 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
164 PCI_VENDOR_ID_SAMSUNG,
166 .driver_data = ATH9K_PCI_BT_ANT_DIV },
167 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
169 PCI_VENDOR_ID_SAMSUNG,
171 .driver_data = ATH9K_PCI_BT_ANT_DIV },
172 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
174 PCI_VENDOR_ID_SAMSUNG,
176 .driver_data = ATH9K_PCI_BT_ANT_DIV },
177 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
179 PCI_VENDOR_ID_SAMSUNG,
181 .driver_data = ATH9K_PCI_BT_ANT_DIV },
182 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
184 PCI_VENDOR_ID_SAMSUNG,
186 .driver_data = ATH9K_PCI_BT_ANT_DIV },
187 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
189 PCI_VENDOR_ID_LENOVO,
191 .driver_data = ATH9K_PCI_BT_ANT_DIV },
192 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
194 PCI_VENDOR_ID_LENOVO,
196 .driver_data = ATH9K_PCI_BT_ANT_DIV },
198 { PCI_VDEVICE(ATHEROS, 0x0032) }, /* PCI-E AR9485 */
199 { PCI_VDEVICE(ATHEROS, 0x0033) }, /* PCI-E AR9580 */
202 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
204 PCI_VENDOR_ID_AZWAVE,
206 .driver_data = ATH9K_PCI_CUS217 },
207 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
211 .driver_data = ATH9K_PCI_CUS217 },
213 /* AR9462 with WoW support */
214 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
216 PCI_VENDOR_ID_ATHEROS,
218 .driver_data = ATH9K_PCI_WOW },
219 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
221 PCI_VENDOR_ID_LENOVO,
223 .driver_data = ATH9K_PCI_WOW },
224 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
226 PCI_VENDOR_ID_ATTANSIC,
228 .driver_data = ATH9K_PCI_WOW },
229 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
231 PCI_VENDOR_ID_AZWAVE,
233 .driver_data = ATH9K_PCI_WOW },
234 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
236 PCI_VENDOR_ID_ASUSTEK,
238 .driver_data = ATH9K_PCI_WOW },
239 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
243 .driver_data = ATH9K_PCI_WOW },
244 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
248 .driver_data = ATH9K_PCI_WOW },
249 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
253 .driver_data = ATH9K_PCI_WOW },
254 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
258 .driver_data = ATH9K_PCI_WOW },
259 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
263 .driver_data = ATH9K_PCI_WOW },
264 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
266 0x10CF, /* Fujitsu */
268 .driver_data = ATH9K_PCI_WOW },
270 { PCI_VDEVICE(ATHEROS, 0x0034) }, /* PCI-E AR9462 */
271 { PCI_VDEVICE(ATHEROS, 0x0037) }, /* PCI-E AR1111/AR9485 */
274 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
276 PCI_VENDOR_ID_ATHEROS,
278 .driver_data = ATH9K_PCI_CUS252 | ATH9K_PCI_BT_ANT_DIV },
279 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
281 PCI_VENDOR_ID_AZWAVE,
283 .driver_data = ATH9K_PCI_CUS252 | ATH9K_PCI_BT_ANT_DIV },
285 /* PCI-E AR9565 (WB335) */
286 { PCI_VDEVICE(ATHEROS, 0x0036),
287 .driver_data = ATH9K_PCI_BT_ANT_DIV },
293 /* return bus cachesize in 4B word units */
294 static void ath_pci_read_cachesize(struct ath_common *common, int *csz)
296 struct ath_softc *sc = (struct ath_softc *) common->priv;
299 pci_read_config_byte(to_pci_dev(sc->dev), PCI_CACHE_LINE_SIZE, &u8tmp);
303 * This check was put in to avoid "unpleasant" consequences if
304 * the bootrom has not fully initialized all PCI devices.
305 * Sometimes the cache line size register is not set
309 *csz = DEFAULT_CACHELINE >> 2; /* Use the default size */
312 static bool ath_pci_eeprom_read(struct ath_common *common, u32 off, u16 *data)
314 struct ath_softc *sc = (struct ath_softc *) common->priv;
315 struct ath9k_platform_data *pdata = sc->dev->platform_data;
318 if (off >= (ARRAY_SIZE(pdata->eeprom_data))) {
320 "%s: eeprom read failed, offset %08x is out of range\n",
324 *data = pdata->eeprom_data[off];
326 struct ath_hw *ah = (struct ath_hw *) common->ah;
328 common->ops->read(ah, AR5416_EEPROM_OFFSET +
329 (off << AR5416_EEPROM_S));
331 if (!ath9k_hw_wait(ah,
332 AR_EEPROM_STATUS_DATA,
333 AR_EEPROM_STATUS_DATA_BUSY |
334 AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0,
339 *data = MS(common->ops->read(ah, AR_EEPROM_STATUS_DATA),
340 AR_EEPROM_STATUS_DATA_VAL);
346 /* Need to be called after we discover btcoex capabilities */
347 static void ath_pci_aspm_init(struct ath_common *common)
349 struct ath_softc *sc = (struct ath_softc *) common->priv;
350 struct ath_hw *ah = sc->sc_ah;
351 struct pci_dev *pdev = to_pci_dev(sc->dev);
352 struct pci_dev *parent;
355 if (!ah->is_pciexpress)
358 parent = pdev->bus->self;
362 if ((ath9k_hw_get_btcoex_scheme(ah) != ATH_BTCOEX_CFG_NONE) &&
363 (AR_SREV_9285(ah))) {
364 /* Bluetooth coexistence requires disabling ASPM. */
365 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
366 PCI_EXP_LNKCTL_ASPM_L0S | PCI_EXP_LNKCTL_ASPM_L1);
369 * Both upstream and downstream PCIe components should
370 * have the same ASPM settings.
372 pcie_capability_clear_word(parent, PCI_EXP_LNKCTL,
373 PCI_EXP_LNKCTL_ASPM_L0S | PCI_EXP_LNKCTL_ASPM_L1);
375 ath_info(common, "Disabling ASPM since BTCOEX is enabled\n");
380 * 0x70c - Ack Frequency Register.
382 * Bits 27:29 - DEFAULT_L1_ENTRANCE_LATENCY.
392 if (AR_SREV_9462(ah))
393 pci_read_config_dword(pdev, 0x70c, &ah->config.aspm_l1_fix);
395 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &aspm);
396 if (aspm & (PCI_EXP_LNKCTL_ASPM_L0S | PCI_EXP_LNKCTL_ASPM_L1)) {
397 ah->aspm_enabled = true;
398 /* Initialize PCIe PM and SERDES registers. */
399 ath9k_hw_configpcipowersave(ah, false);
400 ath_info(common, "ASPM enabled: 0x%x\n", aspm);
404 static const struct ath_bus_ops ath_pci_bus_ops = {
405 .ath_bus_type = ATH_PCI,
406 .read_cachesize = ath_pci_read_cachesize,
407 .eeprom_read = ath_pci_eeprom_read,
408 .aspm_init = ath_pci_aspm_init,
411 static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
413 struct ath_softc *sc;
414 struct ieee80211_hw *hw;
420 if (pcim_enable_device(pdev))
423 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
425 pr_err("32-bit DMA not available\n");
429 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
431 pr_err("32-bit DMA consistent DMA enable failed\n");
436 * Cache line size is used to size and align various
437 * structures used to communicate with the hardware.
439 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
442 * Linux 2.4.18 (at least) writes the cache line size
443 * register as a 16-bit wide register which is wrong.
444 * We must have this setup properly for rx buffer
445 * DMA to work so force a reasonable value here if it
448 csz = L1_CACHE_BYTES / sizeof(u32);
449 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
452 * The default setting of latency timer yields poor results,
453 * set it to the value used by other systems. It may be worth
454 * tweaking this setting more.
456 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
458 pci_set_master(pdev);
461 * Disable the RETRY_TIMEOUT register (0x41) to keep
462 * PCI Tx retries from interfering with C3 CPU state.
464 pci_read_config_dword(pdev, 0x40, &val);
465 if ((val & 0x0000ff00) != 0)
466 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
468 ret = pcim_iomap_regions(pdev, BIT(0), "ath9k");
470 dev_err(&pdev->dev, "PCI memory region reserve error\n");
474 hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops);
476 dev_err(&pdev->dev, "No memory for ieee80211_hw\n");
480 SET_IEEE80211_DEV(hw, &pdev->dev);
481 pci_set_drvdata(pdev, hw);
485 sc->dev = &pdev->dev;
486 sc->mem = pcim_iomap_table(pdev)[0];
487 sc->driver_data = id->driver_data;
489 /* Will be cleared in ath9k_start() */
490 set_bit(SC_OP_INVALID, &sc->sc_flags);
492 ret = request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath9k", sc);
494 dev_err(&pdev->dev, "request_irq failed\n");
500 ret = ath9k_init_device(id->device, sc, &ath_pci_bus_ops);
502 dev_err(&pdev->dev, "Failed to initialize device\n");
506 ath9k_hw_name(sc->sc_ah, hw_name, sizeof(hw_name));
507 wiphy_info(hw->wiphy, "%s mem=0x%lx, irq=%d\n",
508 hw_name, (unsigned long)sc->mem, pdev->irq);
513 free_irq(sc->irq, sc);
515 ieee80211_free_hw(hw);
519 static void ath_pci_remove(struct pci_dev *pdev)
521 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
522 struct ath_softc *sc = hw->priv;
524 if (!is_ath9k_unloaded)
525 sc->sc_ah->ah_flags |= AH_UNPLUGGED;
526 ath9k_deinit_device(sc);
527 free_irq(sc->irq, sc);
528 ieee80211_free_hw(sc->hw);
531 #ifdef CONFIG_PM_SLEEP
533 static int ath_pci_suspend(struct device *device)
535 struct pci_dev *pdev = to_pci_dev(device);
536 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
537 struct ath_softc *sc = hw->priv;
542 /* The device has to be moved to FULLSLEEP forcibly.
543 * Otherwise the chip never moved to full sleep,
544 * when no interface is up.
546 ath9k_stop_btcoex(sc);
547 ath9k_hw_disable(sc->sc_ah);
548 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
553 static int ath_pci_resume(struct device *device)
555 struct pci_dev *pdev = to_pci_dev(device);
556 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
557 struct ath_softc *sc = hw->priv;
558 struct ath_hw *ah = sc->sc_ah;
559 struct ath_common *common = ath9k_hw_common(ah);
563 * Suspend/Resume resets the PCI configuration space, so we have to
564 * re-disable the RETRY_TIMEOUT register (0x41) to keep
565 * PCI Tx retries from interfering with C3 CPU state
567 pci_read_config_dword(pdev, 0x40, &val);
568 if ((val & 0x0000ff00) != 0)
569 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
571 ath_pci_aspm_init(common);
572 ah->reset_power_on = false;
577 static SIMPLE_DEV_PM_OPS(ath9k_pm_ops, ath_pci_suspend, ath_pci_resume);
579 #define ATH9K_PM_OPS (&ath9k_pm_ops)
581 #else /* !CONFIG_PM_SLEEP */
583 #define ATH9K_PM_OPS NULL
585 #endif /* !CONFIG_PM_SLEEP */
588 MODULE_DEVICE_TABLE(pci, ath_pci_id_table);
590 static struct pci_driver ath_pci_driver = {
592 .id_table = ath_pci_id_table,
593 .probe = ath_pci_probe,
594 .remove = ath_pci_remove,
595 .driver.pm = ATH9K_PM_OPS,
598 int ath_pci_init(void)
600 return pci_register_driver(&ath_pci_driver);
603 void ath_pci_exit(void)
605 pci_unregister_driver(&ath_pci_driver);