2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/dma-mapping.h>
19 #include "ar9003_mac.h"
21 #define BITS_PER_BYTE 8
22 #define OFDM_PLCP_BITS 22
23 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
29 #define HT_LTF(_ns) (4 * (_ns))
30 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
31 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
32 #define TIME_SYMBOLS(t) ((t) >> 2)
33 #define TIME_SYMBOLS_HALFGI(t) (((t) * 5 - 4) / 18)
34 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
35 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
38 static u16 bits_per_symbol[][2] = {
40 { 26, 54 }, /* 0: BPSK */
41 { 52, 108 }, /* 1: QPSK 1/2 */
42 { 78, 162 }, /* 2: QPSK 3/4 */
43 { 104, 216 }, /* 3: 16-QAM 1/2 */
44 { 156, 324 }, /* 4: 16-QAM 3/4 */
45 { 208, 432 }, /* 5: 64-QAM 2/3 */
46 { 234, 486 }, /* 6: 64-QAM 3/4 */
47 { 260, 540 }, /* 7: 64-QAM 5/6 */
50 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
51 struct ath_atx_tid *tid, struct sk_buff *skb);
52 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
53 int tx_flags, struct ath_txq *txq);
54 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
55 struct ath_txq *txq, struct list_head *bf_q,
56 struct ath_tx_status *ts, int txok);
57 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
58 struct list_head *head, bool internal);
59 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
60 struct ath_tx_status *ts, int nframes, int nbad,
62 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
64 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
66 struct ath_atx_tid *tid,
76 /*********************/
77 /* Aggregation logic */
78 /*********************/
80 void ath_txq_lock(struct ath_softc *sc, struct ath_txq *txq)
81 __acquires(&txq->axq_lock)
83 spin_lock_bh(&txq->axq_lock);
86 void ath_txq_unlock(struct ath_softc *sc, struct ath_txq *txq)
87 __releases(&txq->axq_lock)
89 spin_unlock_bh(&txq->axq_lock);
92 void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq)
93 __releases(&txq->axq_lock)
95 struct sk_buff_head q;
98 __skb_queue_head_init(&q);
99 skb_queue_splice_init(&txq->complete_q, &q);
100 spin_unlock_bh(&txq->axq_lock);
102 while ((skb = __skb_dequeue(&q)))
103 ieee80211_tx_status(sc->hw, skb);
106 static void ath_tx_queue_tid(struct ath_softc *sc, struct ath_txq *txq,
107 struct ath_atx_tid *tid)
109 struct ath_atx_ac *ac = tid->ac;
110 struct list_head *list;
111 struct ath_vif *avp = (struct ath_vif *) tid->an->vif->drv_priv;
112 struct ath_chanctx *ctx = avp->chanctx;
121 list_add_tail(&tid->list, &ac->tid_q);
128 list = &ctx->acq[TID_TO_WME_AC(tid->tidno)];
129 list_add_tail(&ac->list, list);
132 static struct ath_frame_info *get_frame_info(struct sk_buff *skb)
134 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
135 BUILD_BUG_ON(sizeof(struct ath_frame_info) >
136 sizeof(tx_info->rate_driver_data));
137 return (struct ath_frame_info *) &tx_info->rate_driver_data[0];
140 static void ath_send_bar(struct ath_atx_tid *tid, u16 seqno)
145 ieee80211_send_bar(tid->an->vif, tid->an->sta->addr, tid->tidno,
146 seqno << IEEE80211_SEQ_SEQ_SHIFT);
149 static void ath_set_rates(struct ieee80211_vif *vif, struct ieee80211_sta *sta,
152 ieee80211_get_tx_rates(vif, sta, bf->bf_mpdu, bf->rates,
153 ARRAY_SIZE(bf->rates));
156 static void ath_txq_skb_done(struct ath_softc *sc, struct ath_txq *txq,
159 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
160 struct ath_frame_info *fi = get_frame_info(skb);
166 txq = sc->tx.txq_map[q];
167 if (WARN_ON(--txq->pending_frames < 0))
168 txq->pending_frames = 0;
171 txq->pending_frames < sc->tx.txq_max_pending[q]) {
172 ieee80211_wake_queue(sc->hw, info->hw_queue);
173 txq->stopped = false;
177 static struct ath_atx_tid *
178 ath_get_skb_tid(struct ath_softc *sc, struct ath_node *an, struct sk_buff *skb)
180 u8 tidno = skb->priority & IEEE80211_QOS_CTL_TID_MASK;
181 return ATH_AN_2_TID(an, tidno);
184 static bool ath_tid_has_buffered(struct ath_atx_tid *tid)
186 return !skb_queue_empty(&tid->buf_q) || !skb_queue_empty(&tid->retry_q);
189 static struct sk_buff *ath_tid_dequeue(struct ath_atx_tid *tid)
193 skb = __skb_dequeue(&tid->retry_q);
195 skb = __skb_dequeue(&tid->buf_q);
201 * ath_tx_tid_change_state:
202 * - clears a-mpdu flag of previous session
203 * - force sequence number allocation to fix next BlockAck Window
206 ath_tx_tid_change_state(struct ath_softc *sc, struct ath_atx_tid *tid)
208 struct ath_txq *txq = tid->ac->txq;
209 struct ieee80211_tx_info *tx_info;
210 struct sk_buff *skb, *tskb;
212 struct ath_frame_info *fi;
214 skb_queue_walk_safe(&tid->buf_q, skb, tskb) {
215 fi = get_frame_info(skb);
218 tx_info = IEEE80211_SKB_CB(skb);
219 tx_info->flags &= ~IEEE80211_TX_CTL_AMPDU;
224 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
226 __skb_unlink(skb, &tid->buf_q);
227 ath_txq_skb_done(sc, txq, skb);
228 ieee80211_free_txskb(sc->hw, skb);
235 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
237 struct ath_txq *txq = tid->ac->txq;
240 struct list_head bf_head;
241 struct ath_tx_status ts;
242 struct ath_frame_info *fi;
243 bool sendbar = false;
245 INIT_LIST_HEAD(&bf_head);
247 memset(&ts, 0, sizeof(ts));
249 while ((skb = __skb_dequeue(&tid->retry_q))) {
250 fi = get_frame_info(skb);
253 ath_txq_skb_done(sc, txq, skb);
254 ieee80211_free_txskb(sc->hw, skb);
258 if (fi->baw_tracked) {
259 ath_tx_update_baw(sc, tid, bf->bf_state.seqno);
263 list_add_tail(&bf->list, &bf_head);
264 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
268 ath_txq_unlock(sc, txq);
269 ath_send_bar(tid, tid->seq_start);
270 ath_txq_lock(sc, txq);
274 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
279 index = ATH_BA_INDEX(tid->seq_start, seqno);
280 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
282 __clear_bit(cindex, tid->tx_buf);
284 while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) {
285 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
286 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
287 if (tid->bar_index >= 0)
292 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
295 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
296 u16 seqno = bf->bf_state.seqno;
299 index = ATH_BA_INDEX(tid->seq_start, seqno);
300 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
301 __set_bit(cindex, tid->tx_buf);
304 if (index >= ((tid->baw_tail - tid->baw_head) &
305 (ATH_TID_MAX_BUFS - 1))) {
306 tid->baw_tail = cindex;
307 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
311 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
312 struct ath_atx_tid *tid)
317 struct list_head bf_head;
318 struct ath_tx_status ts;
319 struct ath_frame_info *fi;
321 memset(&ts, 0, sizeof(ts));
322 INIT_LIST_HEAD(&bf_head);
324 while ((skb = ath_tid_dequeue(tid))) {
325 fi = get_frame_info(skb);
329 ath_tx_complete(sc, skb, ATH_TX_ERROR, txq);
333 list_add_tail(&bf->list, &bf_head);
334 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
338 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
339 struct sk_buff *skb, int count)
341 struct ath_frame_info *fi = get_frame_info(skb);
342 struct ath_buf *bf = fi->bf;
343 struct ieee80211_hdr *hdr;
344 int prev = fi->retries;
346 TX_STAT_INC(txq->axq_qnum, a_retries);
347 fi->retries += count;
352 hdr = (struct ieee80211_hdr *)skb->data;
353 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
354 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
355 sizeof(*hdr), DMA_TO_DEVICE);
358 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
360 struct ath_buf *bf = NULL;
362 spin_lock_bh(&sc->tx.txbuflock);
364 if (unlikely(list_empty(&sc->tx.txbuf))) {
365 spin_unlock_bh(&sc->tx.txbuflock);
369 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
372 spin_unlock_bh(&sc->tx.txbuflock);
377 static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf)
379 spin_lock_bh(&sc->tx.txbuflock);
380 list_add_tail(&bf->list, &sc->tx.txbuf);
381 spin_unlock_bh(&sc->tx.txbuflock);
384 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
388 tbf = ath_tx_get_buffer(sc);
392 ATH_TXBUF_RESET(tbf);
394 tbf->bf_mpdu = bf->bf_mpdu;
395 tbf->bf_buf_addr = bf->bf_buf_addr;
396 memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
397 tbf->bf_state = bf->bf_state;
398 tbf->bf_state.stale = false;
403 static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf,
404 struct ath_tx_status *ts, int txok,
405 int *nframes, int *nbad)
407 struct ath_frame_info *fi;
409 u32 ba[WME_BA_BMP_SIZE >> 5];
416 isaggr = bf_isaggr(bf);
418 seq_st = ts->ts_seqnum;
419 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
423 fi = get_frame_info(bf->bf_mpdu);
424 ba_index = ATH_BA_INDEX(seq_st, bf->bf_state.seqno);
427 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
435 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
436 struct ath_buf *bf, struct list_head *bf_q,
437 struct ath_tx_status *ts, int txok)
439 struct ath_node *an = NULL;
441 struct ieee80211_sta *sta;
442 struct ieee80211_hw *hw = sc->hw;
443 struct ieee80211_hdr *hdr;
444 struct ieee80211_tx_info *tx_info;
445 struct ath_atx_tid *tid = NULL;
446 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
447 struct list_head bf_head;
448 struct sk_buff_head bf_pending;
449 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0, seq_first;
450 u32 ba[WME_BA_BMP_SIZE >> 5];
451 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
452 bool rc_update = true, isba;
453 struct ieee80211_tx_rate rates[4];
454 struct ath_frame_info *fi;
456 bool flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
461 hdr = (struct ieee80211_hdr *)skb->data;
463 tx_info = IEEE80211_SKB_CB(skb);
465 memcpy(rates, bf->rates, sizeof(rates));
467 retries = ts->ts_longretry + 1;
468 for (i = 0; i < ts->ts_rateindex; i++)
469 retries += rates[i].count;
473 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2);
477 INIT_LIST_HEAD(&bf_head);
479 bf_next = bf->bf_next;
481 if (!bf->bf_state.stale || bf_next != NULL)
482 list_move_tail(&bf->list, &bf_head);
484 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts, 0);
491 an = (struct ath_node *)sta->drv_priv;
492 tid = ath_get_skb_tid(sc, an, skb);
493 seq_first = tid->seq_start;
494 isba = ts->ts_flags & ATH9K_TX_BA;
497 * The hardware occasionally sends a tx status for the wrong TID.
498 * In this case, the BA status cannot be considered valid and all
499 * subframes need to be retransmitted
501 * Only BlockAcks have a TID and therefore normal Acks cannot be
504 if (isba && tid->tidno != ts->tid)
507 isaggr = bf_isaggr(bf);
508 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
510 if (isaggr && txok) {
511 if (ts->ts_flags & ATH9K_TX_BA) {
512 seq_st = ts->ts_seqnum;
513 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
516 * AR5416 can become deaf/mute when BA
517 * issue happens. Chip needs to be reset.
518 * But AP code may have sychronization issues
519 * when perform internal reset in this routine.
520 * Only enable reset in STA mode for now.
522 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
527 __skb_queue_head_init(&bf_pending);
529 ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad);
531 u16 seqno = bf->bf_state.seqno;
533 txfail = txpending = sendbar = 0;
534 bf_next = bf->bf_next;
537 tx_info = IEEE80211_SKB_CB(skb);
538 fi = get_frame_info(skb);
540 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno) ||
543 * Outside of the current BlockAck window,
544 * maybe part of a previous session
547 } else if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, seqno))) {
548 /* transmit completion, subframe is
549 * acked by block ack */
551 } else if (!isaggr && txok) {
552 /* transmit completion */
556 } else if (fi->retries < ATH_MAX_SW_RETRIES) {
557 if (txok || !an->sleeping)
558 ath_tx_set_retry(sc, txq, bf->bf_mpdu,
565 bar_index = max_t(int, bar_index,
566 ATH_BA_INDEX(seq_first, seqno));
570 * Make sure the last desc is reclaimed if it
571 * not a holding desc.
573 INIT_LIST_HEAD(&bf_head);
574 if (bf_next != NULL || !bf_last->bf_state.stale)
575 list_move_tail(&bf->list, &bf_head);
579 * complete the acked-ones/xretried ones; update
582 ath_tx_update_baw(sc, tid, seqno);
584 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
585 memcpy(tx_info->control.rates, rates, sizeof(rates));
586 ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok);
588 if (bf == bf->bf_lastbf)
589 ath_dynack_sample_tx_ts(sc->sc_ah,
594 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
597 if (tx_info->flags & IEEE80211_TX_STATUS_EOSP) {
598 tx_info->flags &= ~IEEE80211_TX_STATUS_EOSP;
599 ieee80211_sta_eosp(sta);
601 /* retry the un-acked ones */
602 if (bf->bf_next == NULL && bf_last->bf_state.stale) {
605 tbf = ath_clone_txbuf(sc, bf_last);
607 * Update tx baw and complete the
608 * frame with failed status if we
612 ath_tx_update_baw(sc, tid, seqno);
614 ath_tx_complete_buf(sc, bf, txq,
616 bar_index = max_t(int, bar_index,
617 ATH_BA_INDEX(seq_first, seqno));
625 * Put this buffer to the temporary pending
626 * queue to retain ordering
628 __skb_queue_tail(&bf_pending, skb);
634 /* prepend un-acked frames to the beginning of the pending frame queue */
635 if (!skb_queue_empty(&bf_pending)) {
637 ieee80211_sta_set_buffered(sta, tid->tidno, true);
639 skb_queue_splice_tail(&bf_pending, &tid->retry_q);
641 ath_tx_queue_tid(sc, txq, tid);
643 if (ts->ts_status & (ATH9K_TXERR_FILT | ATH9K_TXERR_XRETRY))
644 tid->ac->clear_ps_filter = true;
648 if (bar_index >= 0) {
649 u16 bar_seq = ATH_BA_INDEX2SEQ(seq_first, bar_index);
651 if (BAW_WITHIN(tid->seq_start, tid->baw_size, bar_seq))
652 tid->bar_index = ATH_BA_INDEX(tid->seq_start, bar_seq);
654 ath_txq_unlock(sc, txq);
655 ath_send_bar(tid, ATH_BA_INDEX2SEQ(seq_first, bar_index + 1));
656 ath_txq_lock(sc, txq);
662 ath9k_queue_reset(sc, RESET_TYPE_TX_ERROR);
665 static bool bf_is_ampdu_not_probing(struct ath_buf *bf)
667 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu);
668 return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
671 static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq,
672 struct ath_tx_status *ts, struct ath_buf *bf,
673 struct list_head *bf_head)
675 struct ieee80211_tx_info *info;
678 txok = !(ts->ts_status & ATH9K_TXERR_MASK);
679 flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
680 txq->axq_tx_inprogress = false;
683 if (bf_is_ampdu_not_probing(bf))
684 txq->axq_ampdu_depth--;
686 if (!bf_isampdu(bf)) {
688 info = IEEE80211_SKB_CB(bf->bf_mpdu);
689 memcpy(info->control.rates, bf->rates,
690 sizeof(info->control.rates));
691 ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok);
692 ath_dynack_sample_tx_ts(sc->sc_ah, bf->bf_mpdu, ts);
694 ath_tx_complete_buf(sc, bf, txq, bf_head, ts, txok);
696 ath_tx_complete_aggr(sc, txq, bf, bf_head, ts, txok);
699 ath_txq_schedule(sc, txq);
702 static bool ath_lookup_legacy(struct ath_buf *bf)
705 struct ieee80211_tx_info *tx_info;
706 struct ieee80211_tx_rate *rates;
710 tx_info = IEEE80211_SKB_CB(skb);
711 rates = tx_info->control.rates;
713 for (i = 0; i < 4; i++) {
714 if (!rates[i].count || rates[i].idx < 0)
717 if (!(rates[i].flags & IEEE80211_TX_RC_MCS))
724 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
725 struct ath_atx_tid *tid)
728 struct ieee80211_tx_info *tx_info;
729 struct ieee80211_tx_rate *rates;
730 u32 max_4ms_framelen, frmlen;
731 u16 aggr_limit, bt_aggr_limit, legacy = 0;
732 int q = tid->ac->txq->mac80211_qnum;
736 tx_info = IEEE80211_SKB_CB(skb);
740 * Find the lowest frame length among the rate series that will have a
741 * 4ms (or TXOP limited) transmit duration.
743 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
745 for (i = 0; i < 4; i++) {
751 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) {
756 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
761 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
764 frmlen = sc->tx.max_aggr_framelen[q][modeidx][rates[i].idx];
765 max_4ms_framelen = min(max_4ms_framelen, frmlen);
769 * limit aggregate size by the minimum rate if rate selected is
770 * not a probe rate, if rate selected is a probe rate then
771 * avoid aggregation of this packet.
773 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
776 aggr_limit = min(max_4ms_framelen, (u32)ATH_AMPDU_LIMIT_MAX);
779 * Override the default aggregation limit for BTCOEX.
781 bt_aggr_limit = ath9k_btcoex_aggr_limit(sc, max_4ms_framelen);
783 aggr_limit = bt_aggr_limit;
785 if (tid->an->maxampdu)
786 aggr_limit = min(aggr_limit, tid->an->maxampdu);
792 * Returns the number of delimiters to be added to
793 * meet the minimum required mpdudensity.
795 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
796 struct ath_buf *bf, u16 frmlen,
799 #define FIRST_DESC_NDELIMS 60
800 u32 nsymbits, nsymbols;
803 int width, streams, half_gi, ndelim, mindelim;
804 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
806 /* Select standard number of delimiters based on frame length alone */
807 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
810 * If encryption enabled, hardware requires some more padding between
812 * TODO - this could be improved to be dependent on the rate.
813 * The hardware can keep up at lower rates, but not higher rates
815 if ((fi->keyix != ATH9K_TXKEYIX_INVALID) &&
816 !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))
817 ndelim += ATH_AGGR_ENCRYPTDELIM;
820 * Add delimiter when using RTS/CTS with aggregation
821 * and non enterprise AR9003 card
823 if (first_subfrm && !AR_SREV_9580_10_OR_LATER(sc->sc_ah) &&
824 (sc->sc_ah->ent_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE))
825 ndelim = max(ndelim, FIRST_DESC_NDELIMS);
828 * Convert desired mpdu density from microeconds to bytes based
829 * on highest rate in rate series (i.e. first rate) to determine
830 * required minimum length for subframe. Take into account
831 * whether high rate is 20 or 40Mhz and half or full GI.
833 * If there is no mpdu density restriction, no further calculation
837 if (tid->an->mpdudensity == 0)
840 rix = bf->rates[0].idx;
841 flags = bf->rates[0].flags;
842 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
843 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
846 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity);
848 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity);
853 streams = HT_RC_2_STREAMS(rix);
854 nsymbits = bits_per_symbol[rix % 8][width] * streams;
855 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
857 if (frmlen < minlen) {
858 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
859 ndelim = max(mindelim, ndelim);
865 static struct ath_buf *
866 ath_tx_get_tid_subframe(struct ath_softc *sc, struct ath_txq *txq,
867 struct ath_atx_tid *tid, struct sk_buff_head **q)
869 struct ieee80211_tx_info *tx_info;
870 struct ath_frame_info *fi;
877 if (skb_queue_empty(*q))
884 fi = get_frame_info(skb);
887 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
889 bf->bf_state.stale = false;
892 __skb_unlink(skb, *q);
893 ath_txq_skb_done(sc, txq, skb);
894 ieee80211_free_txskb(sc->hw, skb);
901 tx_info = IEEE80211_SKB_CB(skb);
902 tx_info->flags &= ~IEEE80211_TX_CTL_CLEAR_PS_FILT;
905 * No aggregation session is running, but there may be frames
906 * from a previous session or a failed attempt in the queue.
907 * Send them out as normal data frames
910 tx_info->flags &= ~IEEE80211_TX_CTL_AMPDU;
912 if (!(tx_info->flags & IEEE80211_TX_CTL_AMPDU)) {
913 bf->bf_state.bf_type = 0;
917 bf->bf_state.bf_type = BUF_AMPDU | BUF_AGGR;
918 seqno = bf->bf_state.seqno;
920 /* do not step over block-ack window */
921 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno))
924 if (tid->bar_index > ATH_BA_INDEX(tid->seq_start, seqno)) {
925 struct ath_tx_status ts = {};
926 struct list_head bf_head;
928 INIT_LIST_HEAD(&bf_head);
929 list_add(&bf->list, &bf_head);
930 __skb_unlink(skb, *q);
931 ath_tx_update_baw(sc, tid, seqno);
932 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
943 ath_tx_form_aggr(struct ath_softc *sc, struct ath_txq *txq,
944 struct ath_atx_tid *tid, struct list_head *bf_q,
945 struct ath_buf *bf_first, struct sk_buff_head *tid_q,
948 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
949 struct ath_buf *bf = bf_first, *bf_prev = NULL;
950 int nframes = 0, ndelim;
951 u16 aggr_limit = 0, al = 0, bpad = 0,
952 al_delta, h_baw = tid->baw_size / 2;
953 struct ieee80211_tx_info *tx_info;
954 struct ath_frame_info *fi;
959 aggr_limit = ath_lookup_rate(sc, bf, tid);
963 fi = get_frame_info(skb);
965 /* do not exceed aggregation limit */
966 al_delta = ATH_AGGR_DELIM_SZ + fi->framelen;
968 if (aggr_limit < al + bpad + al_delta ||
969 ath_lookup_legacy(bf) || nframes >= h_baw)
972 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
973 if ((tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) ||
974 !(tx_info->flags & IEEE80211_TX_CTL_AMPDU))
978 /* add padding for previous frame to aggregation length */
979 al += bpad + al_delta;
982 * Get the delimiters needed to meet the MPDU
983 * density for this node.
985 ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen,
987 bpad = PADBYTES(al_delta) + (ndelim << 2);
992 /* link buffers of this frame to the aggregate */
993 if (!fi->baw_tracked)
994 ath_tx_addto_baw(sc, tid, bf);
995 bf->bf_state.ndelim = ndelim;
997 __skb_unlink(skb, tid_q);
998 list_add_tail(&bf->list, bf_q);
1000 bf_prev->bf_next = bf;
1004 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q);
1009 } while (ath_tid_has_buffered(tid));
1012 bf->bf_lastbf = bf_prev;
1014 if (bf == bf_prev) {
1015 al = get_frame_info(bf->bf_mpdu)->framelen;
1016 bf->bf_state.bf_type = BUF_AMPDU;
1018 TX_STAT_INC(txq->axq_qnum, a_aggr);
1029 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
1030 * width - 0 for 20 MHz, 1 for 40 MHz
1031 * half_gi - to use 4us v/s 3.6 us for symbol time
1033 static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen,
1034 int width, int half_gi, bool shortPreamble)
1036 u32 nbits, nsymbits, duration, nsymbols;
1039 /* find number of symbols: PLCP + data */
1040 streams = HT_RC_2_STREAMS(rix);
1041 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
1042 nsymbits = bits_per_symbol[rix % 8][width] * streams;
1043 nsymbols = (nbits + nsymbits - 1) / nsymbits;
1046 duration = SYMBOL_TIME(nsymbols);
1048 duration = SYMBOL_TIME_HALFGI(nsymbols);
1050 /* addup duration for legacy/ht training and signal fields */
1051 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1056 static int ath_max_framelen(int usec, int mcs, bool ht40, bool sgi)
1058 int streams = HT_RC_2_STREAMS(mcs);
1062 usec -= L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1063 symbols = sgi ? TIME_SYMBOLS_HALFGI(usec) : TIME_SYMBOLS(usec);
1064 bits = symbols * bits_per_symbol[mcs % 8][ht40] * streams;
1065 bits -= OFDM_PLCP_BITS;
1073 void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop)
1075 u16 *cur_ht20, *cur_ht20_sgi, *cur_ht40, *cur_ht40_sgi;
1078 /* 4ms is the default (and maximum) duration */
1079 if (!txop || txop > 4096)
1082 cur_ht20 = sc->tx.max_aggr_framelen[queue][MCS_HT20];
1083 cur_ht20_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT20_SGI];
1084 cur_ht40 = sc->tx.max_aggr_framelen[queue][MCS_HT40];
1085 cur_ht40_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT40_SGI];
1086 for (mcs = 0; mcs < 32; mcs++) {
1087 cur_ht20[mcs] = ath_max_framelen(txop, mcs, false, false);
1088 cur_ht20_sgi[mcs] = ath_max_framelen(txop, mcs, false, true);
1089 cur_ht40[mcs] = ath_max_framelen(txop, mcs, true, false);
1090 cur_ht40_sgi[mcs] = ath_max_framelen(txop, mcs, true, true);
1094 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf,
1095 struct ath_tx_info *info, int len, bool rts)
1097 struct ath_hw *ah = sc->sc_ah;
1098 struct ath_common *common = ath9k_hw_common(ah);
1099 struct sk_buff *skb;
1100 struct ieee80211_tx_info *tx_info;
1101 struct ieee80211_tx_rate *rates;
1102 const struct ieee80211_rate *rate;
1103 struct ieee80211_hdr *hdr;
1104 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
1105 u32 rts_thresh = sc->hw->wiphy->rts_threshold;
1110 tx_info = IEEE80211_SKB_CB(skb);
1112 hdr = (struct ieee80211_hdr *)skb->data;
1114 /* set dur_update_en for l-sig computation except for PS-Poll frames */
1115 info->dur_update = !ieee80211_is_pspoll(hdr->frame_control);
1116 info->rtscts_rate = fi->rtscts_rate;
1118 for (i = 0; i < ARRAY_SIZE(bf->rates); i++) {
1119 bool is_40, is_sgi, is_sp;
1122 if (!rates[i].count || (rates[i].idx < 0))
1126 info->rates[i].Tries = rates[i].count;
1129 * Handle RTS threshold for unaggregated HT frames.
1131 if (bf_isampdu(bf) && !bf_isaggr(bf) &&
1132 (rates[i].flags & IEEE80211_TX_RC_MCS) &&
1133 unlikely(rts_thresh != (u32) -1)) {
1134 if (!rts_thresh || (len > rts_thresh))
1138 if (rts || rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1139 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1140 info->flags |= ATH9K_TXDESC_RTSENA;
1141 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1142 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1143 info->flags |= ATH9K_TXDESC_CTSENA;
1146 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
1147 info->rates[i].RateFlags |= ATH9K_RATESERIES_2040;
1148 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
1149 info->rates[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
1151 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI);
1152 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
1153 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
1155 if (rates[i].flags & IEEE80211_TX_RC_MCS) {
1157 info->rates[i].Rate = rix | 0x80;
1158 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1159 ah->txchainmask, info->rates[i].Rate);
1160 info->rates[i].PktDuration = ath_pkt_duration(sc, rix, len,
1161 is_40, is_sgi, is_sp);
1162 if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC))
1163 info->rates[i].RateFlags |= ATH9K_RATESERIES_STBC;
1168 rate = &common->sbands[tx_info->band].bitrates[rates[i].idx];
1169 if ((tx_info->band == IEEE80211_BAND_2GHZ) &&
1170 !(rate->flags & IEEE80211_RATE_ERP_G))
1171 phy = WLAN_RC_PHY_CCK;
1173 phy = WLAN_RC_PHY_OFDM;
1175 info->rates[i].Rate = rate->hw_value;
1176 if (rate->hw_value_short) {
1177 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
1178 info->rates[i].Rate |= rate->hw_value_short;
1183 if (bf->bf_state.bfs_paprd)
1184 info->rates[i].ChSel = ah->txchainmask;
1186 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1187 ah->txchainmask, info->rates[i].Rate);
1189 info->rates[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
1190 phy, rate->bitrate * 100, len, rix, is_sp);
1193 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1194 if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit))
1195 info->flags &= ~ATH9K_TXDESC_RTSENA;
1197 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
1198 if (info->flags & ATH9K_TXDESC_RTSENA)
1199 info->flags &= ~ATH9K_TXDESC_CTSENA;
1202 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1204 struct ieee80211_hdr *hdr;
1205 enum ath9k_pkt_type htype;
1208 hdr = (struct ieee80211_hdr *)skb->data;
1209 fc = hdr->frame_control;
1211 if (ieee80211_is_beacon(fc))
1212 htype = ATH9K_PKT_TYPE_BEACON;
1213 else if (ieee80211_is_probe_resp(fc))
1214 htype = ATH9K_PKT_TYPE_PROBE_RESP;
1215 else if (ieee80211_is_atim(fc))
1216 htype = ATH9K_PKT_TYPE_ATIM;
1217 else if (ieee80211_is_pspoll(fc))
1218 htype = ATH9K_PKT_TYPE_PSPOLL;
1220 htype = ATH9K_PKT_TYPE_NORMAL;
1225 static void ath_tx_fill_desc(struct ath_softc *sc, struct ath_buf *bf,
1226 struct ath_txq *txq, int len)
1228 struct ath_hw *ah = sc->sc_ah;
1229 struct ath_buf *bf_first = NULL;
1230 struct ath_tx_info info;
1231 u32 rts_thresh = sc->hw->wiphy->rts_threshold;
1234 memset(&info, 0, sizeof(info));
1235 info.is_first = true;
1236 info.is_last = true;
1237 info.txpower = MAX_RATE_POWER;
1238 info.qcu = txq->axq_qnum;
1241 struct sk_buff *skb = bf->bf_mpdu;
1242 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1243 struct ath_frame_info *fi = get_frame_info(skb);
1244 bool aggr = !!(bf->bf_state.bf_type & BUF_AGGR);
1246 info.type = get_hw_packet_type(skb);
1248 info.link = bf->bf_next->bf_daddr;
1250 info.link = (sc->tx99_state) ? bf->bf_daddr : 0;
1255 if (!sc->tx99_state)
1256 info.flags = ATH9K_TXDESC_INTREQ;
1257 if ((tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT) ||
1258 txq == sc->tx.uapsdq)
1259 info.flags |= ATH9K_TXDESC_CLRDMASK;
1261 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1262 info.flags |= ATH9K_TXDESC_NOACK;
1263 if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
1264 info.flags |= ATH9K_TXDESC_LDPC;
1266 if (bf->bf_state.bfs_paprd)
1267 info.flags |= (u32) bf->bf_state.bfs_paprd <<
1268 ATH9K_TXDESC_PAPRD_S;
1271 * mac80211 doesn't handle RTS threshold for HT because
1272 * the decision has to be taken based on AMPDU length
1273 * and aggregation is done entirely inside ath9k.
1274 * Set the RTS/CTS flag for the first subframe based
1277 if (aggr && (bf == bf_first) &&
1278 unlikely(rts_thresh != (u32) -1)) {
1280 * "len" is the size of the entire AMPDU.
1282 if (!rts_thresh || (len > rts_thresh))
1289 ath_buf_set_rate(sc, bf, &info, len, rts);
1292 info.buf_addr[0] = bf->bf_buf_addr;
1293 info.buf_len[0] = skb->len;
1294 info.pkt_len = fi->framelen;
1295 info.keyix = fi->keyix;
1296 info.keytype = fi->keytype;
1300 info.aggr = AGGR_BUF_FIRST;
1301 else if (bf == bf_first->bf_lastbf)
1302 info.aggr = AGGR_BUF_LAST;
1304 info.aggr = AGGR_BUF_MIDDLE;
1306 info.ndelim = bf->bf_state.ndelim;
1307 info.aggr_len = len;
1310 if (bf == bf_first->bf_lastbf)
1313 ath9k_hw_set_txdesc(ah, bf->bf_desc, &info);
1319 ath_tx_form_burst(struct ath_softc *sc, struct ath_txq *txq,
1320 struct ath_atx_tid *tid, struct list_head *bf_q,
1321 struct ath_buf *bf_first, struct sk_buff_head *tid_q)
1323 struct ath_buf *bf = bf_first, *bf_prev = NULL;
1324 struct sk_buff *skb;
1328 struct ieee80211_tx_info *tx_info;
1332 __skb_unlink(skb, tid_q);
1333 list_add_tail(&bf->list, bf_q);
1335 bf_prev->bf_next = bf;
1341 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q);
1345 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1346 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
1349 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1353 static bool ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
1354 struct ath_atx_tid *tid, bool *stop)
1357 struct ieee80211_tx_info *tx_info;
1358 struct sk_buff_head *tid_q;
1359 struct list_head bf_q;
1361 bool aggr, last = true;
1363 if (!ath_tid_has_buffered(tid))
1366 INIT_LIST_HEAD(&bf_q);
1368 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q);
1372 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1373 aggr = !!(tx_info->flags & IEEE80211_TX_CTL_AMPDU);
1374 if ((aggr && txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) ||
1375 (!aggr && txq->axq_depth >= ATH_NON_AGGR_MIN_QDEPTH)) {
1380 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1382 last = ath_tx_form_aggr(sc, txq, tid, &bf_q, bf,
1385 ath_tx_form_burst(sc, txq, tid, &bf_q, bf, tid_q);
1387 if (list_empty(&bf_q))
1390 if (tid->ac->clear_ps_filter || tid->an->no_ps_filter) {
1391 tid->ac->clear_ps_filter = false;
1392 tx_info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
1395 ath_tx_fill_desc(sc, bf, txq, aggr_len);
1396 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1400 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
1403 struct ath_atx_tid *txtid;
1404 struct ath_txq *txq;
1405 struct ath_node *an;
1408 an = (struct ath_node *)sta->drv_priv;
1409 txtid = ATH_AN_2_TID(an, tid);
1410 txq = txtid->ac->txq;
1412 ath_txq_lock(sc, txq);
1414 /* update ampdu factor/density, they may have changed. This may happen
1415 * in HT IBSS when a beacon with HT-info is received after the station
1416 * has already been added.
1418 if (sta->ht_cap.ht_supported) {
1419 an->maxampdu = (1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
1420 sta->ht_cap.ampdu_factor)) - 1;
1421 density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density);
1422 an->mpdudensity = density;
1425 /* force sequence number allocation for pending frames */
1426 ath_tx_tid_change_state(sc, txtid);
1428 txtid->active = true;
1429 *ssn = txtid->seq_start = txtid->seq_next;
1430 txtid->bar_index = -1;
1432 memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf));
1433 txtid->baw_head = txtid->baw_tail = 0;
1435 ath_txq_unlock_complete(sc, txq);
1440 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
1442 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1443 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
1444 struct ath_txq *txq = txtid->ac->txq;
1446 ath_txq_lock(sc, txq);
1447 txtid->active = false;
1448 ath_tx_flush_tid(sc, txtid);
1449 ath_tx_tid_change_state(sc, txtid);
1450 ath_txq_unlock_complete(sc, txq);
1453 void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc,
1454 struct ath_node *an)
1456 struct ath_atx_tid *tid;
1457 struct ath_atx_ac *ac;
1458 struct ath_txq *txq;
1462 for (tidno = 0, tid = &an->tid[tidno];
1463 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
1468 ath_txq_lock(sc, txq);
1471 ath_txq_unlock(sc, txq);
1475 buffered = ath_tid_has_buffered(tid);
1478 list_del(&tid->list);
1482 list_del(&ac->list);
1485 ath_txq_unlock(sc, txq);
1487 ieee80211_sta_set_buffered(sta, tidno, buffered);
1491 void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an)
1493 struct ath_atx_tid *tid;
1494 struct ath_atx_ac *ac;
1495 struct ath_txq *txq;
1498 for (tidno = 0, tid = &an->tid[tidno];
1499 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
1504 ath_txq_lock(sc, txq);
1505 ac->clear_ps_filter = true;
1507 if (ath_tid_has_buffered(tid)) {
1508 ath_tx_queue_tid(sc, txq, tid);
1509 ath_txq_schedule(sc, txq);
1512 ath_txq_unlock_complete(sc, txq);
1516 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta,
1519 struct ath_atx_tid *tid;
1520 struct ath_node *an;
1521 struct ath_txq *txq;
1523 an = (struct ath_node *)sta->drv_priv;
1524 tid = ATH_AN_2_TID(an, tidno);
1527 ath_txq_lock(sc, txq);
1529 tid->baw_size = IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
1531 if (ath_tid_has_buffered(tid)) {
1532 ath_tx_queue_tid(sc, txq, tid);
1533 ath_txq_schedule(sc, txq);
1536 ath_txq_unlock_complete(sc, txq);
1539 void ath9k_release_buffered_frames(struct ieee80211_hw *hw,
1540 struct ieee80211_sta *sta,
1541 u16 tids, int nframes,
1542 enum ieee80211_frame_release_type reason,
1545 struct ath_softc *sc = hw->priv;
1546 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1547 struct ath_txq *txq = sc->tx.uapsdq;
1548 struct ieee80211_tx_info *info;
1549 struct list_head bf_q;
1550 struct ath_buf *bf_tail = NULL, *bf;
1551 struct sk_buff_head *tid_q;
1555 INIT_LIST_HEAD(&bf_q);
1556 for (i = 0; tids && nframes; i++, tids >>= 1) {
1557 struct ath_atx_tid *tid;
1562 tid = ATH_AN_2_TID(an, i);
1564 ath_txq_lock(sc, tid->ac->txq);
1565 while (nframes > 0) {
1566 bf = ath_tx_get_tid_subframe(sc, sc->tx.uapsdq, tid, &tid_q);
1570 __skb_unlink(bf->bf_mpdu, tid_q);
1571 list_add_tail(&bf->list, &bf_q);
1572 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1573 if (bf_isampdu(bf)) {
1574 ath_tx_addto_baw(sc, tid, bf);
1575 bf->bf_state.bf_type &= ~BUF_AGGR;
1578 bf_tail->bf_next = bf;
1583 TX_STAT_INC(txq->axq_qnum, a_queued_hw);
1585 if (an->sta && !ath_tid_has_buffered(tid))
1586 ieee80211_sta_set_buffered(an->sta, i, false);
1588 ath_txq_unlock_complete(sc, tid->ac->txq);
1591 if (list_empty(&bf_q))
1594 info = IEEE80211_SKB_CB(bf_tail->bf_mpdu);
1595 info->flags |= IEEE80211_TX_STATUS_EOSP;
1597 bf = list_first_entry(&bf_q, struct ath_buf, list);
1598 ath_txq_lock(sc, txq);
1599 ath_tx_fill_desc(sc, bf, txq, 0);
1600 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1601 ath_txq_unlock(sc, txq);
1604 /********************/
1605 /* Queue Management */
1606 /********************/
1608 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
1610 struct ath_hw *ah = sc->sc_ah;
1611 struct ath9k_tx_queue_info qi;
1612 static const int subtype_txq_to_hwq[] = {
1613 [IEEE80211_AC_BE] = ATH_TXQ_AC_BE,
1614 [IEEE80211_AC_BK] = ATH_TXQ_AC_BK,
1615 [IEEE80211_AC_VI] = ATH_TXQ_AC_VI,
1616 [IEEE80211_AC_VO] = ATH_TXQ_AC_VO,
1620 memset(&qi, 0, sizeof(qi));
1621 qi.tqi_subtype = subtype_txq_to_hwq[subtype];
1622 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
1623 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
1624 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
1625 qi.tqi_physCompBuf = 0;
1628 * Enable interrupts only for EOL and DESC conditions.
1629 * We mark tx descriptors to receive a DESC interrupt
1630 * when a tx queue gets deep; otherwise waiting for the
1631 * EOL to reap descriptors. Note that this is done to
1632 * reduce interrupt load and this only defers reaping
1633 * descriptors, never transmitting frames. Aside from
1634 * reducing interrupts this also permits more concurrency.
1635 * The only potential downside is if the tx queue backs
1636 * up in which case the top half of the kernel may backup
1637 * due to a lack of tx descriptors.
1639 * The UAPSD queue is an exception, since we take a desc-
1640 * based intr on the EOSP frames.
1642 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1643 qi.tqi_qflags = TXQ_FLAG_TXINT_ENABLE;
1645 if (qtype == ATH9K_TX_QUEUE_UAPSD)
1646 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
1648 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
1649 TXQ_FLAG_TXDESCINT_ENABLE;
1651 axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
1652 if (axq_qnum == -1) {
1654 * NB: don't print a message, this happens
1655 * normally on parts with too few tx queues
1659 if (!ATH_TXQ_SETUP(sc, axq_qnum)) {
1660 struct ath_txq *txq = &sc->tx.txq[axq_qnum];
1662 txq->axq_qnum = axq_qnum;
1663 txq->mac80211_qnum = -1;
1664 txq->axq_link = NULL;
1665 __skb_queue_head_init(&txq->complete_q);
1666 INIT_LIST_HEAD(&txq->axq_q);
1667 spin_lock_init(&txq->axq_lock);
1669 txq->axq_ampdu_depth = 0;
1670 txq->axq_tx_inprogress = false;
1671 sc->tx.txqsetup |= 1<<axq_qnum;
1673 txq->txq_headidx = txq->txq_tailidx = 0;
1674 for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
1675 INIT_LIST_HEAD(&txq->txq_fifo[i]);
1677 return &sc->tx.txq[axq_qnum];
1680 int ath_txq_update(struct ath_softc *sc, int qnum,
1681 struct ath9k_tx_queue_info *qinfo)
1683 struct ath_hw *ah = sc->sc_ah;
1685 struct ath9k_tx_queue_info qi;
1687 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum);
1689 ath9k_hw_get_txq_props(ah, qnum, &qi);
1690 qi.tqi_aifs = qinfo->tqi_aifs;
1691 qi.tqi_cwmin = qinfo->tqi_cwmin;
1692 qi.tqi_cwmax = qinfo->tqi_cwmax;
1693 qi.tqi_burstTime = qinfo->tqi_burstTime;
1694 qi.tqi_readyTime = qinfo->tqi_readyTime;
1696 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
1697 ath_err(ath9k_hw_common(sc->sc_ah),
1698 "Unable to update hardware queue %u!\n", qnum);
1701 ath9k_hw_resettxqueue(ah, qnum);
1707 int ath_cabq_update(struct ath_softc *sc)
1709 struct ath9k_tx_queue_info qi;
1710 struct ath_beacon_config *cur_conf = &sc->cur_chan->beacon;
1711 int qnum = sc->beacon.cabq->axq_qnum;
1713 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
1715 qi.tqi_readyTime = (TU_TO_USEC(cur_conf->beacon_interval) *
1716 ATH_CABQ_READY_TIME) / 100;
1717 ath_txq_update(sc, qnum, &qi);
1722 static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq,
1723 struct list_head *list)
1725 struct ath_buf *bf, *lastbf;
1726 struct list_head bf_head;
1727 struct ath_tx_status ts;
1729 memset(&ts, 0, sizeof(ts));
1730 ts.ts_status = ATH9K_TX_FLUSH;
1731 INIT_LIST_HEAD(&bf_head);
1733 while (!list_empty(list)) {
1734 bf = list_first_entry(list, struct ath_buf, list);
1736 if (bf->bf_state.stale) {
1737 list_del(&bf->list);
1739 ath_tx_return_buffer(sc, bf);
1743 lastbf = bf->bf_lastbf;
1744 list_cut_position(&bf_head, list, &lastbf->list);
1745 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
1750 * Drain a given TX queue (could be Beacon or Data)
1752 * This assumes output has been stopped and
1753 * we do not need to block ath_tx_tasklet.
1755 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq)
1757 ath_txq_lock(sc, txq);
1759 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1760 int idx = txq->txq_tailidx;
1762 while (!list_empty(&txq->txq_fifo[idx])) {
1763 ath_drain_txq_list(sc, txq, &txq->txq_fifo[idx]);
1765 INCR(idx, ATH_TXFIFO_DEPTH);
1767 txq->txq_tailidx = idx;
1770 txq->axq_link = NULL;
1771 txq->axq_tx_inprogress = false;
1772 ath_drain_txq_list(sc, txq, &txq->axq_q);
1774 ath_txq_unlock_complete(sc, txq);
1777 bool ath_drain_all_txq(struct ath_softc *sc)
1779 struct ath_hw *ah = sc->sc_ah;
1780 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1781 struct ath_txq *txq;
1785 if (test_bit(ATH_OP_INVALID, &common->op_flags))
1788 ath9k_hw_abort_tx_dma(ah);
1790 /* Check if any queue remains active */
1791 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1792 if (!ATH_TXQ_SETUP(sc, i))
1795 if (!sc->tx.txq[i].axq_depth)
1798 if (ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum))
1803 ath_err(common, "Failed to stop TX DMA, queues=0x%03x!\n", npend);
1805 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1806 if (!ATH_TXQ_SETUP(sc, i))
1810 * The caller will resume queues with ieee80211_wake_queues.
1811 * Mark the queue as not stopped to prevent ath_tx_complete
1812 * from waking the queue too early.
1814 txq = &sc->tx.txq[i];
1815 txq->stopped = false;
1816 ath_draintxq(sc, txq);
1822 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1824 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1825 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1828 /* For each acq entry, for each tid, try to schedule packets
1829 * for transmit until ampdu_depth has reached min Q depth.
1831 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1833 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1834 struct ath_atx_ac *ac, *last_ac;
1835 struct ath_atx_tid *tid, *last_tid;
1836 struct list_head *ac_list;
1839 if (txq->mac80211_qnum < 0)
1842 spin_lock_bh(&sc->chan_lock);
1843 ac_list = &sc->cur_chan->acq[txq->mac80211_qnum];
1844 spin_unlock_bh(&sc->chan_lock);
1846 if (test_bit(ATH_OP_HW_RESET, &common->op_flags) ||
1847 list_empty(ac_list))
1850 spin_lock_bh(&sc->chan_lock);
1853 last_ac = list_entry(ac_list->prev, struct ath_atx_ac, list);
1854 while (!list_empty(ac_list)) {
1857 if (sc->cur_chan->stopped)
1860 ac = list_first_entry(ac_list, struct ath_atx_ac, list);
1861 last_tid = list_entry(ac->tid_q.prev, struct ath_atx_tid, list);
1862 list_del(&ac->list);
1865 while (!list_empty(&ac->tid_q)) {
1867 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid,
1869 list_del(&tid->list);
1872 if (ath_tx_sched_aggr(sc, txq, tid, &stop))
1876 * add tid to round-robin queue if more frames
1877 * are pending for the tid
1879 if (ath_tid_has_buffered(tid))
1880 ath_tx_queue_tid(sc, txq, tid);
1882 if (stop || tid == last_tid)
1886 if (!list_empty(&ac->tid_q) && !ac->sched) {
1888 list_add_tail(&ac->list, ac_list);
1894 if (ac == last_ac) {
1899 last_ac = list_entry(ac_list->prev,
1900 struct ath_atx_ac, list);
1905 spin_unlock_bh(&sc->chan_lock);
1908 void ath_txq_schedule_all(struct ath_softc *sc)
1910 struct ath_txq *txq;
1913 for (i = 0; i < IEEE80211_NUM_ACS; i++) {
1914 txq = sc->tx.txq_map[i];
1916 spin_lock_bh(&txq->axq_lock);
1917 ath_txq_schedule(sc, txq);
1918 spin_unlock_bh(&txq->axq_lock);
1927 * Insert a chain of ath_buf (descriptors) on a txq and
1928 * assume the descriptors are already chained together by caller.
1930 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1931 struct list_head *head, bool internal)
1933 struct ath_hw *ah = sc->sc_ah;
1934 struct ath_common *common = ath9k_hw_common(ah);
1935 struct ath_buf *bf, *bf_last;
1936 bool puttxbuf = false;
1940 * Insert the frame on the outbound list and
1941 * pass it on to the hardware.
1944 if (list_empty(head))
1947 edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1948 bf = list_first_entry(head, struct ath_buf, list);
1949 bf_last = list_entry(head->prev, struct ath_buf, list);
1951 ath_dbg(common, QUEUE, "qnum: %d, txq depth: %d\n",
1952 txq->axq_qnum, txq->axq_depth);
1954 if (edma && list_empty(&txq->txq_fifo[txq->txq_headidx])) {
1955 list_splice_tail_init(head, &txq->txq_fifo[txq->txq_headidx]);
1956 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
1959 list_splice_tail_init(head, &txq->axq_q);
1961 if (txq->axq_link) {
1962 ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr);
1963 ath_dbg(common, XMIT, "link[%u] (%p)=%llx (%p)\n",
1964 txq->axq_qnum, txq->axq_link,
1965 ito64(bf->bf_daddr), bf->bf_desc);
1969 txq->axq_link = bf_last->bf_desc;
1973 TX_STAT_INC(txq->axq_qnum, puttxbuf);
1974 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1975 ath_dbg(common, XMIT, "TXDP[%u] = %llx (%p)\n",
1976 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
1979 if (!edma || sc->tx99_state) {
1980 TX_STAT_INC(txq->axq_qnum, txstart);
1981 ath9k_hw_txstart(ah, txq->axq_qnum);
1987 if (bf_is_ampdu_not_probing(bf))
1988 txq->axq_ampdu_depth++;
1990 bf_last = bf->bf_lastbf;
1991 bf = bf_last->bf_next;
1992 bf_last->bf_next = NULL;
1997 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
1998 struct ath_atx_tid *tid, struct sk_buff *skb)
2000 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2001 struct ath_frame_info *fi = get_frame_info(skb);
2002 struct list_head bf_head;
2003 struct ath_buf *bf = fi->bf;
2005 INIT_LIST_HEAD(&bf_head);
2006 list_add_tail(&bf->list, &bf_head);
2007 bf->bf_state.bf_type = 0;
2008 if (tid && (tx_info->flags & IEEE80211_TX_CTL_AMPDU)) {
2009 bf->bf_state.bf_type = BUF_AMPDU;
2010 ath_tx_addto_baw(sc, tid, bf);
2015 ath_tx_fill_desc(sc, bf, txq, fi->framelen);
2016 ath_tx_txqaddbuf(sc, txq, &bf_head, false);
2017 TX_STAT_INC(txq->axq_qnum, queued);
2020 static void setup_frame_info(struct ieee80211_hw *hw,
2021 struct ieee80211_sta *sta,
2022 struct sk_buff *skb,
2025 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2026 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key;
2027 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2028 const struct ieee80211_rate *rate;
2029 struct ath_frame_info *fi = get_frame_info(skb);
2030 struct ath_node *an = NULL;
2031 enum ath9k_key_type keytype;
2032 bool short_preamble = false;
2035 * We check if Short Preamble is needed for the CTS rate by
2036 * checking the BSS's global flag.
2037 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
2039 if (tx_info->control.vif &&
2040 tx_info->control.vif->bss_conf.use_short_preamble)
2041 short_preamble = true;
2043 rate = ieee80211_get_rts_cts_rate(hw, tx_info);
2044 keytype = ath9k_cmn_get_hw_crypto_keytype(skb);
2047 an = (struct ath_node *) sta->drv_priv;
2049 memset(fi, 0, sizeof(*fi));
2052 fi->keyix = hw_key->hw_key_idx;
2053 else if (an && ieee80211_is_data(hdr->frame_control) && an->ps_key > 0)
2054 fi->keyix = an->ps_key;
2056 fi->keyix = ATH9K_TXKEYIX_INVALID;
2057 fi->keytype = keytype;
2058 fi->framelen = framelen;
2062 fi->rtscts_rate = rate->hw_value;
2064 fi->rtscts_rate |= rate->hw_value_short;
2067 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate)
2069 struct ath_hw *ah = sc->sc_ah;
2070 struct ath9k_channel *curchan = ah->curchan;
2072 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && IS_CHAN_5GHZ(curchan) &&
2073 (chainmask == 0x7) && (rate < 0x90))
2075 else if (AR_SREV_9462(ah) && ath9k_hw_btcoex_is_enabled(ah) &&
2083 * Assign a descriptor (and sequence number if necessary,
2084 * and map buffer for DMA. Frees skb on error
2086 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
2087 struct ath_txq *txq,
2088 struct ath_atx_tid *tid,
2089 struct sk_buff *skb)
2091 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2092 struct ath_frame_info *fi = get_frame_info(skb);
2093 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2098 bf = ath_tx_get_buffer(sc);
2100 ath_dbg(common, XMIT, "TX buffers are full\n");
2104 ATH_TXBUF_RESET(bf);
2106 if (tid && ieee80211_is_data_present(hdr->frame_control)) {
2107 fragno = le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG;
2108 seqno = tid->seq_next;
2109 hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT);
2112 hdr->seq_ctrl |= cpu_to_le16(fragno);
2114 if (!ieee80211_has_morefrags(hdr->frame_control))
2115 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
2117 bf->bf_state.seqno = seqno;
2122 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
2123 skb->len, DMA_TO_DEVICE);
2124 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
2126 bf->bf_buf_addr = 0;
2127 ath_err(ath9k_hw_common(sc->sc_ah),
2128 "dma_mapping_error() on TX\n");
2129 ath_tx_return_buffer(sc, bf);
2138 static int ath_tx_prepare(struct ieee80211_hw *hw, struct sk_buff *skb,
2139 struct ath_tx_control *txctl)
2141 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2142 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2143 struct ieee80211_sta *sta = txctl->sta;
2144 struct ieee80211_vif *vif = info->control.vif;
2145 struct ath_vif *avp;
2146 struct ath_softc *sc = hw->priv;
2147 int frmlen = skb->len + FCS_LEN;
2148 int padpos, padsize;
2150 /* NOTE: sta can be NULL according to net/mac80211.h */
2152 txctl->an = (struct ath_node *)sta->drv_priv;
2153 else if (vif && ieee80211_is_data(hdr->frame_control)) {
2154 avp = (void *)vif->drv_priv;
2155 txctl->an = &avp->mcast_node;
2158 if (info->control.hw_key)
2159 frmlen += info->control.hw_key->icv_len;
2162 * As a temporary workaround, assign seq# here; this will likely need
2163 * to be cleaned up to work better with Beacon transmission and virtual
2166 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2167 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2168 sc->tx.seq_no += 0x10;
2169 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2170 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
2173 if ((vif && vif->type != NL80211_IFTYPE_AP &&
2174 vif->type != NL80211_IFTYPE_AP_VLAN) ||
2175 !ieee80211_is_data(hdr->frame_control))
2176 info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
2178 /* Add the padding after the header if this is not already done */
2179 padpos = ieee80211_hdrlen(hdr->frame_control);
2180 padsize = padpos & 3;
2181 if (padsize && skb->len > padpos) {
2182 if (skb_headroom(skb) < padsize)
2185 skb_push(skb, padsize);
2186 memmove(skb->data, skb->data + padsize, padpos);
2189 setup_frame_info(hw, sta, skb, frmlen);
2194 /* Upon failure caller should free skb */
2195 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
2196 struct ath_tx_control *txctl)
2198 struct ieee80211_hdr *hdr;
2199 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2200 struct ieee80211_sta *sta = txctl->sta;
2201 struct ieee80211_vif *vif = info->control.vif;
2202 struct ath_frame_info *fi = get_frame_info(skb);
2203 struct ath_vif *avp = NULL;
2204 struct ath_softc *sc = hw->priv;
2205 struct ath_txq *txq = txctl->txq;
2206 struct ath_atx_tid *tid = NULL;
2212 avp = (void *)vif->drv_priv;
2214 if (info->flags & IEEE80211_TX_CTL_TX_OFFCHAN)
2215 txctl->force_channel = true;
2217 ret = ath_tx_prepare(hw, skb, txctl);
2221 hdr = (struct ieee80211_hdr *) skb->data;
2223 * At this point, the vif, hw_key and sta pointers in the tx control
2224 * info are no longer valid (overwritten by the ath_frame_info data.
2227 q = skb_get_queue_mapping(skb);
2229 ath_txq_lock(sc, txq);
2230 if (txq == sc->tx.txq_map[q]) {
2232 if (++txq->pending_frames > sc->tx.txq_max_pending[q] &&
2234 ieee80211_stop_queue(sc->hw, info->hw_queue);
2235 txq->stopped = true;
2239 queue = ieee80211_is_data_present(hdr->frame_control);
2241 /* Force queueing of all frames that belong to a virtual interface on
2242 * a different channel context, to ensure that they are sent on the
2245 if (((avp && avp->chanctx != sc->cur_chan) ||
2246 sc->cur_chan->stopped) && !txctl->force_channel) {
2248 txctl->an = &avp->mcast_node;
2249 info->flags &= ~IEEE80211_TX_CTL_PS_RESPONSE;
2253 if (txctl->an && queue)
2254 tid = ath_get_skb_tid(sc, txctl->an, skb);
2256 if (info->flags & (IEEE80211_TX_CTL_PS_RESPONSE |
2257 IEEE80211_TX_CTL_TX_OFFCHAN)) {
2258 ath_txq_unlock(sc, txq);
2259 txq = sc->tx.uapsdq;
2260 ath_txq_lock(sc, txq);
2261 } else if (txctl->an && queue) {
2262 WARN_ON(tid->ac->txq != txctl->txq);
2264 if (info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT)
2265 tid->ac->clear_ps_filter = true;
2268 * Add this frame to software queue for scheduling later
2271 TX_STAT_INC(txq->axq_qnum, a_queued_sw);
2272 __skb_queue_tail(&tid->buf_q, skb);
2273 if (!txctl->an->sleeping)
2274 ath_tx_queue_tid(sc, txq, tid);
2276 ath_txq_schedule(sc, txq);
2280 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
2282 ath_txq_skb_done(sc, txq, skb);
2284 dev_kfree_skb_any(skb);
2286 ieee80211_free_txskb(sc->hw, skb);
2290 bf->bf_state.bfs_paprd = txctl->paprd;
2293 bf->bf_state.bfs_paprd_timestamp = jiffies;
2295 ath_set_rates(vif, sta, bf);
2296 ath_tx_send_normal(sc, txq, tid, skb);
2299 ath_txq_unlock(sc, txq);
2304 void ath_tx_cabq(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2305 struct sk_buff *skb)
2307 struct ath_softc *sc = hw->priv;
2308 struct ath_tx_control txctl = {
2309 .txq = sc->beacon.cabq
2311 struct ath_tx_info info = {};
2312 struct ieee80211_hdr *hdr;
2313 struct ath_buf *bf_tail = NULL;
2320 sc->cur_chan->beacon.beacon_interval * 1000 *
2321 sc->cur_chan->beacon.dtim_period / ATH_BCBUF;
2324 struct ath_frame_info *fi = get_frame_info(skb);
2326 if (ath_tx_prepare(hw, skb, &txctl))
2329 bf = ath_tx_setup_buffer(sc, txctl.txq, NULL, skb);
2334 ath_set_rates(vif, NULL, bf);
2335 ath_buf_set_rate(sc, bf, &info, fi->framelen, false);
2336 duration += info.rates[0].PktDuration;
2338 bf_tail->bf_next = bf;
2340 list_add_tail(&bf->list, &bf_q);
2344 if (duration > max_duration)
2347 skb = ieee80211_get_buffered_bc(hw, vif);
2351 ieee80211_free_txskb(hw, skb);
2353 if (list_empty(&bf_q))
2356 bf = list_first_entry(&bf_q, struct ath_buf, list);
2357 hdr = (struct ieee80211_hdr *) bf->bf_mpdu->data;
2359 if (hdr->frame_control & IEEE80211_FCTL_MOREDATA) {
2360 hdr->frame_control &= ~IEEE80211_FCTL_MOREDATA;
2361 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
2362 sizeof(*hdr), DMA_TO_DEVICE);
2365 ath_txq_lock(sc, txctl.txq);
2366 ath_tx_fill_desc(sc, bf, txctl.txq, 0);
2367 ath_tx_txqaddbuf(sc, txctl.txq, &bf_q, false);
2368 TX_STAT_INC(txctl.txq->axq_qnum, queued);
2369 ath_txq_unlock(sc, txctl.txq);
2376 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
2377 int tx_flags, struct ath_txq *txq)
2379 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2380 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2381 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
2382 int padpos, padsize;
2383 unsigned long flags;
2385 ath_dbg(common, XMIT, "TX complete: skb: %p\n", skb);
2387 if (sc->sc_ah->caldata)
2388 set_bit(PAPRD_PACKET_SENT, &sc->sc_ah->caldata->cal_flags);
2390 if (!(tx_flags & ATH_TX_ERROR))
2391 /* Frame was ACKed */
2392 tx_info->flags |= IEEE80211_TX_STAT_ACK;
2394 padpos = ieee80211_hdrlen(hdr->frame_control);
2395 padsize = padpos & 3;
2396 if (padsize && skb->len>padpos+padsize) {
2398 * Remove MAC header padding before giving the frame back to
2401 memmove(skb->data + padsize, skb->data, padpos);
2402 skb_pull(skb, padsize);
2405 spin_lock_irqsave(&sc->sc_pm_lock, flags);
2406 if ((sc->ps_flags & PS_WAIT_FOR_TX_ACK) && !txq->axq_depth) {
2407 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
2409 "Going back to sleep after having received TX status (0x%lx)\n",
2410 sc->ps_flags & (PS_WAIT_FOR_BEACON |
2412 PS_WAIT_FOR_PSPOLL_DATA |
2413 PS_WAIT_FOR_TX_ACK));
2415 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
2417 __skb_queue_tail(&txq->complete_q, skb);
2418 ath_txq_skb_done(sc, txq, skb);
2421 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
2422 struct ath_txq *txq, struct list_head *bf_q,
2423 struct ath_tx_status *ts, int txok)
2425 struct sk_buff *skb = bf->bf_mpdu;
2426 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2427 unsigned long flags;
2431 tx_flags |= ATH_TX_ERROR;
2433 if (ts->ts_status & ATH9K_TXERR_FILT)
2434 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
2436 dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE);
2437 bf->bf_buf_addr = 0;
2439 goto skip_tx_complete;
2441 if (bf->bf_state.bfs_paprd) {
2442 if (time_after(jiffies,
2443 bf->bf_state.bfs_paprd_timestamp +
2444 msecs_to_jiffies(ATH_PAPRD_TIMEOUT)))
2445 dev_kfree_skb_any(skb);
2447 complete(&sc->paprd_complete);
2449 ath_debug_stat_tx(sc, bf, ts, txq, tx_flags);
2450 ath_tx_complete(sc, skb, tx_flags, txq);
2453 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
2454 * accidentally reference it later.
2459 * Return the list of ath_buf of this mpdu to free queue
2461 spin_lock_irqsave(&sc->tx.txbuflock, flags);
2462 list_splice_tail_init(bf_q, &sc->tx.txbuf);
2463 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
2466 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
2467 struct ath_tx_status *ts, int nframes, int nbad,
2470 struct sk_buff *skb = bf->bf_mpdu;
2471 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2472 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2473 struct ieee80211_hw *hw = sc->hw;
2474 struct ath_hw *ah = sc->sc_ah;
2478 tx_info->status.ack_signal = ts->ts_rssi;
2480 tx_rateindex = ts->ts_rateindex;
2481 WARN_ON(tx_rateindex >= hw->max_rates);
2483 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
2484 tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
2486 BUG_ON(nbad > nframes);
2488 tx_info->status.ampdu_len = nframes;
2489 tx_info->status.ampdu_ack_len = nframes - nbad;
2491 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
2492 (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) == 0) {
2494 * If an underrun error is seen assume it as an excessive
2495 * retry only if max frame trigger level has been reached
2496 * (2 KB for single stream, and 4 KB for dual stream).
2497 * Adjust the long retry as if the frame was tried
2498 * hw->max_rate_tries times to affect how rate control updates
2499 * PER for the failed rate.
2500 * In case of congestion on the bus penalizing this type of
2501 * underruns should help hardware actually transmit new frames
2502 * successfully by eventually preferring slower rates.
2503 * This itself should also alleviate congestion on the bus.
2505 if (unlikely(ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN |
2506 ATH9K_TX_DELIM_UNDERRUN)) &&
2507 ieee80211_is_data(hdr->frame_control) &&
2508 ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level)
2509 tx_info->status.rates[tx_rateindex].count =
2513 for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
2514 tx_info->status.rates[i].count = 0;
2515 tx_info->status.rates[i].idx = -1;
2518 tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1;
2521 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
2523 struct ath_hw *ah = sc->sc_ah;
2524 struct ath_common *common = ath9k_hw_common(ah);
2525 struct ath_buf *bf, *lastbf, *bf_held = NULL;
2526 struct list_head bf_head;
2527 struct ath_desc *ds;
2528 struct ath_tx_status ts;
2531 ath_dbg(common, QUEUE, "tx queue %d (%x), link %p\n",
2532 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
2535 ath_txq_lock(sc, txq);
2537 if (test_bit(ATH_OP_HW_RESET, &common->op_flags))
2540 if (list_empty(&txq->axq_q)) {
2541 txq->axq_link = NULL;
2542 ath_txq_schedule(sc, txq);
2545 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
2548 * There is a race condition that a BH gets scheduled
2549 * after sw writes TxE and before hw re-load the last
2550 * descriptor to get the newly chained one.
2551 * Software must keep the last DONE descriptor as a
2552 * holding descriptor - software does so by marking
2553 * it with the STALE flag.
2556 if (bf->bf_state.stale) {
2558 if (list_is_last(&bf_held->list, &txq->axq_q))
2561 bf = list_entry(bf_held->list.next, struct ath_buf,
2565 lastbf = bf->bf_lastbf;
2566 ds = lastbf->bf_desc;
2568 memset(&ts, 0, sizeof(ts));
2569 status = ath9k_hw_txprocdesc(ah, ds, &ts);
2570 if (status == -EINPROGRESS)
2573 TX_STAT_INC(txq->axq_qnum, txprocdesc);
2576 * Remove ath_buf's of the same transmit unit from txq,
2577 * however leave the last descriptor back as the holding
2578 * descriptor for hw.
2580 lastbf->bf_state.stale = true;
2581 INIT_LIST_HEAD(&bf_head);
2582 if (!list_is_singular(&lastbf->list))
2583 list_cut_position(&bf_head,
2584 &txq->axq_q, lastbf->list.prev);
2587 list_del(&bf_held->list);
2588 ath_tx_return_buffer(sc, bf_held);
2591 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2593 ath_txq_unlock_complete(sc, txq);
2596 void ath_tx_tasklet(struct ath_softc *sc)
2598 struct ath_hw *ah = sc->sc_ah;
2599 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1) & ah->intr_txqs;
2602 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2603 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2604 ath_tx_processq(sc, &sc->tx.txq[i]);
2608 void ath_tx_edma_tasklet(struct ath_softc *sc)
2610 struct ath_tx_status ts;
2611 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2612 struct ath_hw *ah = sc->sc_ah;
2613 struct ath_txq *txq;
2614 struct ath_buf *bf, *lastbf;
2615 struct list_head bf_head;
2616 struct list_head *fifo_list;
2620 if (test_bit(ATH_OP_HW_RESET, &common->op_flags))
2623 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts);
2624 if (status == -EINPROGRESS)
2626 if (status == -EIO) {
2627 ath_dbg(common, XMIT, "Error processing tx status\n");
2631 /* Process beacon completions separately */
2632 if (ts.qid == sc->beacon.beaconq) {
2633 sc->beacon.tx_processed = true;
2634 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
2636 if (ath9k_is_chanctx_enabled()) {
2637 ath_chanctx_event(sc, NULL,
2638 ATH_CHANCTX_EVENT_BEACON_SENT);
2641 ath9k_csa_update(sc);
2645 txq = &sc->tx.txq[ts.qid];
2647 ath_txq_lock(sc, txq);
2649 TX_STAT_INC(txq->axq_qnum, txprocdesc);
2651 fifo_list = &txq->txq_fifo[txq->txq_tailidx];
2652 if (list_empty(fifo_list)) {
2653 ath_txq_unlock(sc, txq);
2657 bf = list_first_entry(fifo_list, struct ath_buf, list);
2658 if (bf->bf_state.stale) {
2659 list_del(&bf->list);
2660 ath_tx_return_buffer(sc, bf);
2661 bf = list_first_entry(fifo_list, struct ath_buf, list);
2664 lastbf = bf->bf_lastbf;
2666 INIT_LIST_HEAD(&bf_head);
2667 if (list_is_last(&lastbf->list, fifo_list)) {
2668 list_splice_tail_init(fifo_list, &bf_head);
2669 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
2671 if (!list_empty(&txq->axq_q)) {
2672 struct list_head bf_q;
2674 INIT_LIST_HEAD(&bf_q);
2675 txq->axq_link = NULL;
2676 list_splice_tail_init(&txq->axq_q, &bf_q);
2677 ath_tx_txqaddbuf(sc, txq, &bf_q, true);
2680 lastbf->bf_state.stale = true;
2682 list_cut_position(&bf_head, fifo_list,
2686 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2687 ath_txq_unlock_complete(sc, txq);
2695 static int ath_txstatus_setup(struct ath_softc *sc, int size)
2697 struct ath_descdma *dd = &sc->txsdma;
2698 u8 txs_len = sc->sc_ah->caps.txs_len;
2700 dd->dd_desc_len = size * txs_len;
2701 dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len,
2702 &dd->dd_desc_paddr, GFP_KERNEL);
2709 static int ath_tx_edma_init(struct ath_softc *sc)
2713 err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE);
2715 ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc,
2716 sc->txsdma.dd_desc_paddr,
2717 ATH_TXSTATUS_RING_SIZE);
2722 int ath_tx_init(struct ath_softc *sc, int nbufs)
2724 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2727 spin_lock_init(&sc->tx.txbuflock);
2729 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2733 "Failed to allocate tx descriptors: %d\n", error);
2737 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2738 "beacon", ATH_BCBUF, 1, 1);
2741 "Failed to allocate beacon descriptors: %d\n", error);
2745 INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work);
2747 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
2748 error = ath_tx_edma_init(sc);
2753 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2755 struct ath_atx_tid *tid;
2756 struct ath_atx_ac *ac;
2759 for (tidno = 0, tid = &an->tid[tidno];
2760 tidno < IEEE80211_NUM_TIDS;
2764 tid->seq_start = tid->seq_next = 0;
2765 tid->baw_size = WME_MAX_BA;
2766 tid->baw_head = tid->baw_tail = 0;
2768 tid->active = false;
2769 __skb_queue_head_init(&tid->buf_q);
2770 __skb_queue_head_init(&tid->retry_q);
2771 acno = TID_TO_WME_AC(tidno);
2772 tid->ac = &an->ac[acno];
2775 for (acno = 0, ac = &an->ac[acno];
2776 acno < IEEE80211_NUM_ACS; acno++, ac++) {
2778 ac->clear_ps_filter = true;
2779 ac->txq = sc->tx.txq_map[acno];
2780 INIT_LIST_HEAD(&ac->tid_q);
2784 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2786 struct ath_atx_ac *ac;
2787 struct ath_atx_tid *tid;
2788 struct ath_txq *txq;
2791 for (tidno = 0, tid = &an->tid[tidno];
2792 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
2797 ath_txq_lock(sc, txq);
2800 list_del(&tid->list);
2805 list_del(&ac->list);
2806 tid->ac->sched = false;
2809 ath_tid_drain(sc, txq, tid);
2810 tid->active = false;
2812 ath_txq_unlock(sc, txq);
2816 #ifdef CONFIG_ATH9K_TX99
2818 int ath9k_tx99_send(struct ath_softc *sc, struct sk_buff *skb,
2819 struct ath_tx_control *txctl)
2821 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2822 struct ath_frame_info *fi = get_frame_info(skb);
2823 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2825 int padpos, padsize;
2827 padpos = ieee80211_hdrlen(hdr->frame_control);
2828 padsize = padpos & 3;
2830 if (padsize && skb->len > padpos) {
2831 if (skb_headroom(skb) < padsize) {
2832 ath_dbg(common, XMIT,
2833 "tx99 padding failed\n");
2837 skb_push(skb, padsize);
2838 memmove(skb->data, skb->data + padsize, padpos);
2841 fi->keyix = ATH9K_TXKEYIX_INVALID;
2842 fi->framelen = skb->len + FCS_LEN;
2843 fi->keytype = ATH9K_KEY_TYPE_CLEAR;
2845 bf = ath_tx_setup_buffer(sc, txctl->txq, NULL, skb);
2847 ath_dbg(common, XMIT, "tx99 buffer setup failed\n");
2851 ath_set_rates(sc->tx99_vif, NULL, bf);
2853 ath9k_hw_set_desc_link(sc->sc_ah, bf->bf_desc, bf->bf_daddr);
2854 ath9k_hw_tx99_start(sc->sc_ah, txctl->txq->axq_qnum);
2856 ath_tx_send_normal(sc, txctl->txq, NULL, skb);
2861 #endif /* CONFIG_ATH9K_TX99 */