2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/dma-mapping.h>
19 #include "ar9003_mac.h"
21 #define BITS_PER_BYTE 8
22 #define OFDM_PLCP_BITS 22
23 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
29 #define HT_LTF(_ns) (4 * (_ns))
30 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
31 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
32 #define TIME_SYMBOLS(t) ((t) >> 2)
33 #define TIME_SYMBOLS_HALFGI(t) (((t) * 5 - 4) / 18)
34 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
35 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
38 static u16 bits_per_symbol[][2] = {
40 { 26, 54 }, /* 0: BPSK */
41 { 52, 108 }, /* 1: QPSK 1/2 */
42 { 78, 162 }, /* 2: QPSK 3/4 */
43 { 104, 216 }, /* 3: 16-QAM 1/2 */
44 { 156, 324 }, /* 4: 16-QAM 3/4 */
45 { 208, 432 }, /* 5: 64-QAM 2/3 */
46 { 234, 486 }, /* 6: 64-QAM 3/4 */
47 { 260, 540 }, /* 7: 64-QAM 5/6 */
50 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
51 struct ath_atx_tid *tid, struct sk_buff *skb);
52 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
53 int tx_flags, struct ath_txq *txq);
54 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
55 struct ath_txq *txq, struct list_head *bf_q,
56 struct ath_tx_status *ts, int txok);
57 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
58 struct list_head *head, bool internal);
59 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
60 struct ath_tx_status *ts, int nframes, int nbad,
62 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
64 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
66 struct ath_atx_tid *tid,
76 /*********************/
77 /* Aggregation logic */
78 /*********************/
80 void ath_txq_lock(struct ath_softc *sc, struct ath_txq *txq)
81 __acquires(&txq->axq_lock)
83 spin_lock_bh(&txq->axq_lock);
86 void ath_txq_unlock(struct ath_softc *sc, struct ath_txq *txq)
87 __releases(&txq->axq_lock)
89 spin_unlock_bh(&txq->axq_lock);
92 void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq)
93 __releases(&txq->axq_lock)
95 struct sk_buff_head q;
98 __skb_queue_head_init(&q);
99 skb_queue_splice_init(&txq->complete_q, &q);
100 spin_unlock_bh(&txq->axq_lock);
102 while ((skb = __skb_dequeue(&q)))
103 ieee80211_tx_status(sc->hw, skb);
106 static void ath_tx_queue_tid(struct ath_softc *sc, struct ath_txq *txq,
107 struct ath_atx_tid *tid)
109 struct ath_atx_ac *ac = tid->ac;
110 struct list_head *list;
111 struct ath_vif *avp = (struct ath_vif *) tid->an->vif->drv_priv;
112 struct ath_chanctx *ctx = avp->chanctx;
121 list_add_tail(&tid->list, &ac->tid_q);
128 list = &ctx->acq[TID_TO_WME_AC(tid->tidno)];
129 list_add_tail(&ac->list, list);
132 static struct ath_frame_info *get_frame_info(struct sk_buff *skb)
134 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
135 BUILD_BUG_ON(sizeof(struct ath_frame_info) >
136 sizeof(tx_info->rate_driver_data));
137 return (struct ath_frame_info *) &tx_info->rate_driver_data[0];
140 static void ath_send_bar(struct ath_atx_tid *tid, u16 seqno)
145 ieee80211_send_bar(tid->an->vif, tid->an->sta->addr, tid->tidno,
146 seqno << IEEE80211_SEQ_SEQ_SHIFT);
149 static void ath_set_rates(struct ieee80211_vif *vif, struct ieee80211_sta *sta,
152 ieee80211_get_tx_rates(vif, sta, bf->bf_mpdu, bf->rates,
153 ARRAY_SIZE(bf->rates));
156 static void ath_txq_skb_done(struct ath_softc *sc, struct ath_txq *txq,
159 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
160 struct ath_frame_info *fi = get_frame_info(skb);
166 txq = sc->tx.txq_map[q];
167 if (WARN_ON(--txq->pending_frames < 0))
168 txq->pending_frames = 0;
171 txq->pending_frames < sc->tx.txq_max_pending[q]) {
172 ieee80211_wake_queue(sc->hw, info->hw_queue);
173 txq->stopped = false;
177 static struct ath_atx_tid *
178 ath_get_skb_tid(struct ath_softc *sc, struct ath_node *an, struct sk_buff *skb)
180 u8 tidno = skb->priority & IEEE80211_QOS_CTL_TID_MASK;
181 return ATH_AN_2_TID(an, tidno);
184 static bool ath_tid_has_buffered(struct ath_atx_tid *tid)
186 return !skb_queue_empty(&tid->buf_q) || !skb_queue_empty(&tid->retry_q);
189 static struct sk_buff *ath_tid_dequeue(struct ath_atx_tid *tid)
193 skb = __skb_dequeue(&tid->retry_q);
195 skb = __skb_dequeue(&tid->buf_q);
201 * ath_tx_tid_change_state:
202 * - clears a-mpdu flag of previous session
203 * - force sequence number allocation to fix next BlockAck Window
206 ath_tx_tid_change_state(struct ath_softc *sc, struct ath_atx_tid *tid)
208 struct ath_txq *txq = tid->ac->txq;
209 struct ieee80211_tx_info *tx_info;
210 struct sk_buff *skb, *tskb;
212 struct ath_frame_info *fi;
214 skb_queue_walk_safe(&tid->buf_q, skb, tskb) {
215 fi = get_frame_info(skb);
218 tx_info = IEEE80211_SKB_CB(skb);
219 tx_info->flags &= ~IEEE80211_TX_CTL_AMPDU;
224 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
226 __skb_unlink(skb, &tid->buf_q);
227 ath_txq_skb_done(sc, txq, skb);
228 ieee80211_free_txskb(sc->hw, skb);
235 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
237 struct ath_txq *txq = tid->ac->txq;
240 struct list_head bf_head;
241 struct ath_tx_status ts;
242 struct ath_frame_info *fi;
243 bool sendbar = false;
245 INIT_LIST_HEAD(&bf_head);
247 memset(&ts, 0, sizeof(ts));
249 while ((skb = __skb_dequeue(&tid->retry_q))) {
250 fi = get_frame_info(skb);
253 ath_txq_skb_done(sc, txq, skb);
254 ieee80211_free_txskb(sc->hw, skb);
258 if (fi->baw_tracked) {
259 ath_tx_update_baw(sc, tid, bf->bf_state.seqno);
263 list_add_tail(&bf->list, &bf_head);
264 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
268 ath_txq_unlock(sc, txq);
269 ath_send_bar(tid, tid->seq_start);
270 ath_txq_lock(sc, txq);
274 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
279 index = ATH_BA_INDEX(tid->seq_start, seqno);
280 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
282 __clear_bit(cindex, tid->tx_buf);
284 while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) {
285 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
286 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
287 if (tid->bar_index >= 0)
292 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
295 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
296 u16 seqno = bf->bf_state.seqno;
299 index = ATH_BA_INDEX(tid->seq_start, seqno);
300 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
301 __set_bit(cindex, tid->tx_buf);
304 if (index >= ((tid->baw_tail - tid->baw_head) &
305 (ATH_TID_MAX_BUFS - 1))) {
306 tid->baw_tail = cindex;
307 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
311 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
312 struct ath_atx_tid *tid)
317 struct list_head bf_head;
318 struct ath_tx_status ts;
319 struct ath_frame_info *fi;
321 memset(&ts, 0, sizeof(ts));
322 INIT_LIST_HEAD(&bf_head);
324 while ((skb = ath_tid_dequeue(tid))) {
325 fi = get_frame_info(skb);
329 ath_tx_complete(sc, skb, ATH_TX_ERROR, txq);
333 list_add_tail(&bf->list, &bf_head);
334 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
338 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
339 struct sk_buff *skb, int count)
341 struct ath_frame_info *fi = get_frame_info(skb);
342 struct ath_buf *bf = fi->bf;
343 struct ieee80211_hdr *hdr;
344 int prev = fi->retries;
346 TX_STAT_INC(txq->axq_qnum, a_retries);
347 fi->retries += count;
352 hdr = (struct ieee80211_hdr *)skb->data;
353 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
354 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
355 sizeof(*hdr), DMA_TO_DEVICE);
358 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
360 struct ath_buf *bf = NULL;
362 spin_lock_bh(&sc->tx.txbuflock);
364 if (unlikely(list_empty(&sc->tx.txbuf))) {
365 spin_unlock_bh(&sc->tx.txbuflock);
369 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
372 spin_unlock_bh(&sc->tx.txbuflock);
377 static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf)
379 spin_lock_bh(&sc->tx.txbuflock);
380 list_add_tail(&bf->list, &sc->tx.txbuf);
381 spin_unlock_bh(&sc->tx.txbuflock);
384 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
388 tbf = ath_tx_get_buffer(sc);
392 ATH_TXBUF_RESET(tbf);
394 tbf->bf_mpdu = bf->bf_mpdu;
395 tbf->bf_buf_addr = bf->bf_buf_addr;
396 memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
397 tbf->bf_state = bf->bf_state;
398 tbf->bf_state.stale = false;
403 static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf,
404 struct ath_tx_status *ts, int txok,
405 int *nframes, int *nbad)
407 struct ath_frame_info *fi;
409 u32 ba[WME_BA_BMP_SIZE >> 5];
416 isaggr = bf_isaggr(bf);
418 seq_st = ts->ts_seqnum;
419 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
423 fi = get_frame_info(bf->bf_mpdu);
424 ba_index = ATH_BA_INDEX(seq_st, bf->bf_state.seqno);
427 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
435 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
436 struct ath_buf *bf, struct list_head *bf_q,
437 struct ath_tx_status *ts, int txok)
439 struct ath_node *an = NULL;
441 struct ieee80211_sta *sta;
442 struct ieee80211_hw *hw = sc->hw;
443 struct ieee80211_hdr *hdr;
444 struct ieee80211_tx_info *tx_info;
445 struct ath_atx_tid *tid = NULL;
446 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
447 struct list_head bf_head;
448 struct sk_buff_head bf_pending;
449 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0, seq_first;
450 u32 ba[WME_BA_BMP_SIZE >> 5];
451 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
452 bool rc_update = true, isba;
453 struct ieee80211_tx_rate rates[4];
454 struct ath_frame_info *fi;
456 bool flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
461 hdr = (struct ieee80211_hdr *)skb->data;
463 tx_info = IEEE80211_SKB_CB(skb);
465 memcpy(rates, bf->rates, sizeof(rates));
467 retries = ts->ts_longretry + 1;
468 for (i = 0; i < ts->ts_rateindex; i++)
469 retries += rates[i].count;
473 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2);
477 INIT_LIST_HEAD(&bf_head);
479 bf_next = bf->bf_next;
481 if (!bf->bf_state.stale || bf_next != NULL)
482 list_move_tail(&bf->list, &bf_head);
484 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts, 0);
491 an = (struct ath_node *)sta->drv_priv;
492 tid = ath_get_skb_tid(sc, an, skb);
493 seq_first = tid->seq_start;
494 isba = ts->ts_flags & ATH9K_TX_BA;
497 * The hardware occasionally sends a tx status for the wrong TID.
498 * In this case, the BA status cannot be considered valid and all
499 * subframes need to be retransmitted
501 * Only BlockAcks have a TID and therefore normal Acks cannot be
504 if (isba && tid->tidno != ts->tid)
507 isaggr = bf_isaggr(bf);
508 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
510 if (isaggr && txok) {
511 if (ts->ts_flags & ATH9K_TX_BA) {
512 seq_st = ts->ts_seqnum;
513 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
516 * AR5416 can become deaf/mute when BA
517 * issue happens. Chip needs to be reset.
518 * But AP code may have sychronization issues
519 * when perform internal reset in this routine.
520 * Only enable reset in STA mode for now.
522 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
527 __skb_queue_head_init(&bf_pending);
529 ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad);
531 u16 seqno = bf->bf_state.seqno;
533 txfail = txpending = sendbar = 0;
534 bf_next = bf->bf_next;
537 tx_info = IEEE80211_SKB_CB(skb);
538 fi = get_frame_info(skb);
540 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno) ||
543 * Outside of the current BlockAck window,
544 * maybe part of a previous session
547 } else if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, seqno))) {
548 /* transmit completion, subframe is
549 * acked by block ack */
551 } else if (!isaggr && txok) {
552 /* transmit completion */
556 } else if (fi->retries < ATH_MAX_SW_RETRIES) {
557 if (txok || !an->sleeping)
558 ath_tx_set_retry(sc, txq, bf->bf_mpdu,
565 bar_index = max_t(int, bar_index,
566 ATH_BA_INDEX(seq_first, seqno));
570 * Make sure the last desc is reclaimed if it
571 * not a holding desc.
573 INIT_LIST_HEAD(&bf_head);
574 if (bf_next != NULL || !bf_last->bf_state.stale)
575 list_move_tail(&bf->list, &bf_head);
579 * complete the acked-ones/xretried ones; update
582 ath_tx_update_baw(sc, tid, seqno);
584 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
585 memcpy(tx_info->control.rates, rates, sizeof(rates));
586 ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok);
588 if (bf == bf->bf_lastbf)
589 ath_dynack_sample_tx_ts(sc->sc_ah,
594 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
597 if (tx_info->flags & IEEE80211_TX_STATUS_EOSP) {
598 tx_info->flags &= ~IEEE80211_TX_STATUS_EOSP;
599 ieee80211_sta_eosp(sta);
601 /* retry the un-acked ones */
602 if (bf->bf_next == NULL && bf_last->bf_state.stale) {
605 tbf = ath_clone_txbuf(sc, bf_last);
607 * Update tx baw and complete the
608 * frame with failed status if we
612 ath_tx_update_baw(sc, tid, seqno);
614 ath_tx_complete_buf(sc, bf, txq,
616 bar_index = max_t(int, bar_index,
617 ATH_BA_INDEX(seq_first, seqno));
625 * Put this buffer to the temporary pending
626 * queue to retain ordering
628 __skb_queue_tail(&bf_pending, skb);
634 /* prepend un-acked frames to the beginning of the pending frame queue */
635 if (!skb_queue_empty(&bf_pending)) {
637 ieee80211_sta_set_buffered(sta, tid->tidno, true);
639 skb_queue_splice_tail(&bf_pending, &tid->retry_q);
641 ath_tx_queue_tid(sc, txq, tid);
643 if (ts->ts_status & (ATH9K_TXERR_FILT | ATH9K_TXERR_XRETRY))
644 tid->ac->clear_ps_filter = true;
648 if (bar_index >= 0) {
649 u16 bar_seq = ATH_BA_INDEX2SEQ(seq_first, bar_index);
651 if (BAW_WITHIN(tid->seq_start, tid->baw_size, bar_seq))
652 tid->bar_index = ATH_BA_INDEX(tid->seq_start, bar_seq);
654 ath_txq_unlock(sc, txq);
655 ath_send_bar(tid, ATH_BA_INDEX2SEQ(seq_first, bar_index + 1));
656 ath_txq_lock(sc, txq);
662 ath9k_queue_reset(sc, RESET_TYPE_TX_ERROR);
665 static bool bf_is_ampdu_not_probing(struct ath_buf *bf)
667 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu);
668 return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
671 static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq,
672 struct ath_tx_status *ts, struct ath_buf *bf,
673 struct list_head *bf_head)
675 struct ieee80211_tx_info *info;
678 txok = !(ts->ts_status & ATH9K_TXERR_MASK);
679 flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
680 txq->axq_tx_inprogress = false;
683 if (bf_is_ampdu_not_probing(bf))
684 txq->axq_ampdu_depth--;
686 ts->duration = ath9k_hw_get_duration(sc->sc_ah, bf->bf_desc,
688 if (!bf_isampdu(bf)) {
690 info = IEEE80211_SKB_CB(bf->bf_mpdu);
691 memcpy(info->control.rates, bf->rates,
692 sizeof(info->control.rates));
693 ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok);
694 ath_dynack_sample_tx_ts(sc->sc_ah, bf->bf_mpdu, ts);
696 ath_tx_complete_buf(sc, bf, txq, bf_head, ts, txok);
698 ath_tx_complete_aggr(sc, txq, bf, bf_head, ts, txok);
701 ath_txq_schedule(sc, txq);
704 static bool ath_lookup_legacy(struct ath_buf *bf)
707 struct ieee80211_tx_info *tx_info;
708 struct ieee80211_tx_rate *rates;
712 tx_info = IEEE80211_SKB_CB(skb);
713 rates = tx_info->control.rates;
715 for (i = 0; i < 4; i++) {
716 if (!rates[i].count || rates[i].idx < 0)
719 if (!(rates[i].flags & IEEE80211_TX_RC_MCS))
726 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
727 struct ath_atx_tid *tid)
730 struct ieee80211_tx_info *tx_info;
731 struct ieee80211_tx_rate *rates;
732 u32 max_4ms_framelen, frmlen;
733 u16 aggr_limit, bt_aggr_limit, legacy = 0;
734 int q = tid->ac->txq->mac80211_qnum;
738 tx_info = IEEE80211_SKB_CB(skb);
742 * Find the lowest frame length among the rate series that will have a
743 * 4ms (or TXOP limited) transmit duration.
745 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
747 for (i = 0; i < 4; i++) {
753 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) {
758 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
763 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
766 frmlen = sc->tx.max_aggr_framelen[q][modeidx][rates[i].idx];
767 max_4ms_framelen = min(max_4ms_framelen, frmlen);
771 * limit aggregate size by the minimum rate if rate selected is
772 * not a probe rate, if rate selected is a probe rate then
773 * avoid aggregation of this packet.
775 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
778 aggr_limit = min(max_4ms_framelen, (u32)ATH_AMPDU_LIMIT_MAX);
781 * Override the default aggregation limit for BTCOEX.
783 bt_aggr_limit = ath9k_btcoex_aggr_limit(sc, max_4ms_framelen);
785 aggr_limit = bt_aggr_limit;
787 if (tid->an->maxampdu)
788 aggr_limit = min(aggr_limit, tid->an->maxampdu);
794 * Returns the number of delimiters to be added to
795 * meet the minimum required mpdudensity.
797 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
798 struct ath_buf *bf, u16 frmlen,
801 #define FIRST_DESC_NDELIMS 60
802 u32 nsymbits, nsymbols;
805 int width, streams, half_gi, ndelim, mindelim;
806 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
808 /* Select standard number of delimiters based on frame length alone */
809 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
812 * If encryption enabled, hardware requires some more padding between
814 * TODO - this could be improved to be dependent on the rate.
815 * The hardware can keep up at lower rates, but not higher rates
817 if ((fi->keyix != ATH9K_TXKEYIX_INVALID) &&
818 !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))
819 ndelim += ATH_AGGR_ENCRYPTDELIM;
822 * Add delimiter when using RTS/CTS with aggregation
823 * and non enterprise AR9003 card
825 if (first_subfrm && !AR_SREV_9580_10_OR_LATER(sc->sc_ah) &&
826 (sc->sc_ah->ent_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE))
827 ndelim = max(ndelim, FIRST_DESC_NDELIMS);
830 * Convert desired mpdu density from microeconds to bytes based
831 * on highest rate in rate series (i.e. first rate) to determine
832 * required minimum length for subframe. Take into account
833 * whether high rate is 20 or 40Mhz and half or full GI.
835 * If there is no mpdu density restriction, no further calculation
839 if (tid->an->mpdudensity == 0)
842 rix = bf->rates[0].idx;
843 flags = bf->rates[0].flags;
844 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
845 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
848 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity);
850 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity);
855 streams = HT_RC_2_STREAMS(rix);
856 nsymbits = bits_per_symbol[rix % 8][width] * streams;
857 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
859 if (frmlen < minlen) {
860 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
861 ndelim = max(mindelim, ndelim);
867 static struct ath_buf *
868 ath_tx_get_tid_subframe(struct ath_softc *sc, struct ath_txq *txq,
869 struct ath_atx_tid *tid, struct sk_buff_head **q)
871 struct ieee80211_tx_info *tx_info;
872 struct ath_frame_info *fi;
879 if (skb_queue_empty(*q))
886 fi = get_frame_info(skb);
889 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
891 bf->bf_state.stale = false;
894 __skb_unlink(skb, *q);
895 ath_txq_skb_done(sc, txq, skb);
896 ieee80211_free_txskb(sc->hw, skb);
903 tx_info = IEEE80211_SKB_CB(skb);
904 tx_info->flags &= ~IEEE80211_TX_CTL_CLEAR_PS_FILT;
907 * No aggregation session is running, but there may be frames
908 * from a previous session or a failed attempt in the queue.
909 * Send them out as normal data frames
912 tx_info->flags &= ~IEEE80211_TX_CTL_AMPDU;
914 if (!(tx_info->flags & IEEE80211_TX_CTL_AMPDU)) {
915 bf->bf_state.bf_type = 0;
919 bf->bf_state.bf_type = BUF_AMPDU | BUF_AGGR;
920 seqno = bf->bf_state.seqno;
922 /* do not step over block-ack window */
923 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno))
926 if (tid->bar_index > ATH_BA_INDEX(tid->seq_start, seqno)) {
927 struct ath_tx_status ts = {};
928 struct list_head bf_head;
930 INIT_LIST_HEAD(&bf_head);
931 list_add(&bf->list, &bf_head);
932 __skb_unlink(skb, *q);
933 ath_tx_update_baw(sc, tid, seqno);
934 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
945 ath_tx_form_aggr(struct ath_softc *sc, struct ath_txq *txq,
946 struct ath_atx_tid *tid, struct list_head *bf_q,
947 struct ath_buf *bf_first, struct sk_buff_head *tid_q,
950 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
951 struct ath_buf *bf = bf_first, *bf_prev = NULL;
952 int nframes = 0, ndelim;
953 u16 aggr_limit = 0, al = 0, bpad = 0,
954 al_delta, h_baw = tid->baw_size / 2;
955 struct ieee80211_tx_info *tx_info;
956 struct ath_frame_info *fi;
961 aggr_limit = ath_lookup_rate(sc, bf, tid);
965 fi = get_frame_info(skb);
967 /* do not exceed aggregation limit */
968 al_delta = ATH_AGGR_DELIM_SZ + fi->framelen;
970 if (aggr_limit < al + bpad + al_delta ||
971 ath_lookup_legacy(bf) || nframes >= h_baw)
974 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
975 if ((tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) ||
976 !(tx_info->flags & IEEE80211_TX_CTL_AMPDU))
980 /* add padding for previous frame to aggregation length */
981 al += bpad + al_delta;
984 * Get the delimiters needed to meet the MPDU
985 * density for this node.
987 ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen,
989 bpad = PADBYTES(al_delta) + (ndelim << 2);
994 /* link buffers of this frame to the aggregate */
995 if (!fi->baw_tracked)
996 ath_tx_addto_baw(sc, tid, bf);
997 bf->bf_state.ndelim = ndelim;
999 __skb_unlink(skb, tid_q);
1000 list_add_tail(&bf->list, bf_q);
1002 bf_prev->bf_next = bf;
1006 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q);
1011 } while (ath_tid_has_buffered(tid));
1014 bf->bf_lastbf = bf_prev;
1016 if (bf == bf_prev) {
1017 al = get_frame_info(bf->bf_mpdu)->framelen;
1018 bf->bf_state.bf_type = BUF_AMPDU;
1020 TX_STAT_INC(txq->axq_qnum, a_aggr);
1031 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
1032 * width - 0 for 20 MHz, 1 for 40 MHz
1033 * half_gi - to use 4us v/s 3.6 us for symbol time
1035 static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen,
1036 int width, int half_gi, bool shortPreamble)
1038 u32 nbits, nsymbits, duration, nsymbols;
1041 /* find number of symbols: PLCP + data */
1042 streams = HT_RC_2_STREAMS(rix);
1043 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
1044 nsymbits = bits_per_symbol[rix % 8][width] * streams;
1045 nsymbols = (nbits + nsymbits - 1) / nsymbits;
1048 duration = SYMBOL_TIME(nsymbols);
1050 duration = SYMBOL_TIME_HALFGI(nsymbols);
1052 /* addup duration for legacy/ht training and signal fields */
1053 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1058 static int ath_max_framelen(int usec, int mcs, bool ht40, bool sgi)
1060 int streams = HT_RC_2_STREAMS(mcs);
1064 usec -= L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1065 symbols = sgi ? TIME_SYMBOLS_HALFGI(usec) : TIME_SYMBOLS(usec);
1066 bits = symbols * bits_per_symbol[mcs % 8][ht40] * streams;
1067 bits -= OFDM_PLCP_BITS;
1075 void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop)
1077 u16 *cur_ht20, *cur_ht20_sgi, *cur_ht40, *cur_ht40_sgi;
1080 /* 4ms is the default (and maximum) duration */
1081 if (!txop || txop > 4096)
1084 cur_ht20 = sc->tx.max_aggr_framelen[queue][MCS_HT20];
1085 cur_ht20_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT20_SGI];
1086 cur_ht40 = sc->tx.max_aggr_framelen[queue][MCS_HT40];
1087 cur_ht40_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT40_SGI];
1088 for (mcs = 0; mcs < 32; mcs++) {
1089 cur_ht20[mcs] = ath_max_framelen(txop, mcs, false, false);
1090 cur_ht20_sgi[mcs] = ath_max_framelen(txop, mcs, false, true);
1091 cur_ht40[mcs] = ath_max_framelen(txop, mcs, true, false);
1092 cur_ht40_sgi[mcs] = ath_max_framelen(txop, mcs, true, true);
1096 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf,
1097 struct ath_tx_info *info, int len, bool rts)
1099 struct ath_hw *ah = sc->sc_ah;
1100 struct ath_common *common = ath9k_hw_common(ah);
1101 struct sk_buff *skb;
1102 struct ieee80211_tx_info *tx_info;
1103 struct ieee80211_tx_rate *rates;
1104 const struct ieee80211_rate *rate;
1105 struct ieee80211_hdr *hdr;
1106 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
1107 u32 rts_thresh = sc->hw->wiphy->rts_threshold;
1112 tx_info = IEEE80211_SKB_CB(skb);
1114 hdr = (struct ieee80211_hdr *)skb->data;
1116 /* set dur_update_en for l-sig computation except for PS-Poll frames */
1117 info->dur_update = !ieee80211_is_pspoll(hdr->frame_control);
1118 info->rtscts_rate = fi->rtscts_rate;
1120 for (i = 0; i < ARRAY_SIZE(bf->rates); i++) {
1121 bool is_40, is_sgi, is_sp;
1124 if (!rates[i].count || (rates[i].idx < 0))
1128 info->rates[i].Tries = rates[i].count;
1131 * Handle RTS threshold for unaggregated HT frames.
1133 if (bf_isampdu(bf) && !bf_isaggr(bf) &&
1134 (rates[i].flags & IEEE80211_TX_RC_MCS) &&
1135 unlikely(rts_thresh != (u32) -1)) {
1136 if (!rts_thresh || (len > rts_thresh))
1140 if (rts || rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1141 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1142 info->flags |= ATH9K_TXDESC_RTSENA;
1143 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1144 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1145 info->flags |= ATH9K_TXDESC_CTSENA;
1148 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
1149 info->rates[i].RateFlags |= ATH9K_RATESERIES_2040;
1150 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
1151 info->rates[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
1153 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI);
1154 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
1155 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
1157 if (rates[i].flags & IEEE80211_TX_RC_MCS) {
1159 info->rates[i].Rate = rix | 0x80;
1160 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1161 ah->txchainmask, info->rates[i].Rate);
1162 info->rates[i].PktDuration = ath_pkt_duration(sc, rix, len,
1163 is_40, is_sgi, is_sp);
1164 if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC))
1165 info->rates[i].RateFlags |= ATH9K_RATESERIES_STBC;
1170 rate = &common->sbands[tx_info->band].bitrates[rates[i].idx];
1171 if ((tx_info->band == IEEE80211_BAND_2GHZ) &&
1172 !(rate->flags & IEEE80211_RATE_ERP_G))
1173 phy = WLAN_RC_PHY_CCK;
1175 phy = WLAN_RC_PHY_OFDM;
1177 info->rates[i].Rate = rate->hw_value;
1178 if (rate->hw_value_short) {
1179 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
1180 info->rates[i].Rate |= rate->hw_value_short;
1185 if (bf->bf_state.bfs_paprd)
1186 info->rates[i].ChSel = ah->txchainmask;
1188 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1189 ah->txchainmask, info->rates[i].Rate);
1191 info->rates[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
1192 phy, rate->bitrate * 100, len, rix, is_sp);
1195 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1196 if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit))
1197 info->flags &= ~ATH9K_TXDESC_RTSENA;
1199 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
1200 if (info->flags & ATH9K_TXDESC_RTSENA)
1201 info->flags &= ~ATH9K_TXDESC_CTSENA;
1204 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1206 struct ieee80211_hdr *hdr;
1207 enum ath9k_pkt_type htype;
1210 hdr = (struct ieee80211_hdr *)skb->data;
1211 fc = hdr->frame_control;
1213 if (ieee80211_is_beacon(fc))
1214 htype = ATH9K_PKT_TYPE_BEACON;
1215 else if (ieee80211_is_probe_resp(fc))
1216 htype = ATH9K_PKT_TYPE_PROBE_RESP;
1217 else if (ieee80211_is_atim(fc))
1218 htype = ATH9K_PKT_TYPE_ATIM;
1219 else if (ieee80211_is_pspoll(fc))
1220 htype = ATH9K_PKT_TYPE_PSPOLL;
1222 htype = ATH9K_PKT_TYPE_NORMAL;
1227 static void ath_tx_fill_desc(struct ath_softc *sc, struct ath_buf *bf,
1228 struct ath_txq *txq, int len)
1230 struct ath_hw *ah = sc->sc_ah;
1231 struct ath_buf *bf_first = NULL;
1232 struct ath_tx_info info;
1233 u32 rts_thresh = sc->hw->wiphy->rts_threshold;
1236 memset(&info, 0, sizeof(info));
1237 info.is_first = true;
1238 info.is_last = true;
1239 info.txpower = MAX_RATE_POWER;
1240 info.qcu = txq->axq_qnum;
1243 struct sk_buff *skb = bf->bf_mpdu;
1244 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1245 struct ath_frame_info *fi = get_frame_info(skb);
1246 bool aggr = !!(bf->bf_state.bf_type & BUF_AGGR);
1248 info.type = get_hw_packet_type(skb);
1250 info.link = bf->bf_next->bf_daddr;
1252 info.link = (sc->tx99_state) ? bf->bf_daddr : 0;
1257 if (!sc->tx99_state)
1258 info.flags = ATH9K_TXDESC_INTREQ;
1259 if ((tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT) ||
1260 txq == sc->tx.uapsdq)
1261 info.flags |= ATH9K_TXDESC_CLRDMASK;
1263 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1264 info.flags |= ATH9K_TXDESC_NOACK;
1265 if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
1266 info.flags |= ATH9K_TXDESC_LDPC;
1268 if (bf->bf_state.bfs_paprd)
1269 info.flags |= (u32) bf->bf_state.bfs_paprd <<
1270 ATH9K_TXDESC_PAPRD_S;
1273 * mac80211 doesn't handle RTS threshold for HT because
1274 * the decision has to be taken based on AMPDU length
1275 * and aggregation is done entirely inside ath9k.
1276 * Set the RTS/CTS flag for the first subframe based
1279 if (aggr && (bf == bf_first) &&
1280 unlikely(rts_thresh != (u32) -1)) {
1282 * "len" is the size of the entire AMPDU.
1284 if (!rts_thresh || (len > rts_thresh))
1291 ath_buf_set_rate(sc, bf, &info, len, rts);
1294 info.buf_addr[0] = bf->bf_buf_addr;
1295 info.buf_len[0] = skb->len;
1296 info.pkt_len = fi->framelen;
1297 info.keyix = fi->keyix;
1298 info.keytype = fi->keytype;
1302 info.aggr = AGGR_BUF_FIRST;
1303 else if (bf == bf_first->bf_lastbf)
1304 info.aggr = AGGR_BUF_LAST;
1306 info.aggr = AGGR_BUF_MIDDLE;
1308 info.ndelim = bf->bf_state.ndelim;
1309 info.aggr_len = len;
1312 if (bf == bf_first->bf_lastbf)
1315 ath9k_hw_set_txdesc(ah, bf->bf_desc, &info);
1321 ath_tx_form_burst(struct ath_softc *sc, struct ath_txq *txq,
1322 struct ath_atx_tid *tid, struct list_head *bf_q,
1323 struct ath_buf *bf_first, struct sk_buff_head *tid_q)
1325 struct ath_buf *bf = bf_first, *bf_prev = NULL;
1326 struct sk_buff *skb;
1330 struct ieee80211_tx_info *tx_info;
1334 __skb_unlink(skb, tid_q);
1335 list_add_tail(&bf->list, bf_q);
1337 bf_prev->bf_next = bf;
1343 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q);
1347 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1348 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
1351 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1355 static bool ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
1356 struct ath_atx_tid *tid, bool *stop)
1359 struct ieee80211_tx_info *tx_info;
1360 struct sk_buff_head *tid_q;
1361 struct list_head bf_q;
1363 bool aggr, last = true;
1365 if (!ath_tid_has_buffered(tid))
1368 INIT_LIST_HEAD(&bf_q);
1370 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q);
1374 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1375 aggr = !!(tx_info->flags & IEEE80211_TX_CTL_AMPDU);
1376 if ((aggr && txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) ||
1377 (!aggr && txq->axq_depth >= ATH_NON_AGGR_MIN_QDEPTH)) {
1382 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1384 last = ath_tx_form_aggr(sc, txq, tid, &bf_q, bf,
1387 ath_tx_form_burst(sc, txq, tid, &bf_q, bf, tid_q);
1389 if (list_empty(&bf_q))
1392 if (tid->ac->clear_ps_filter || tid->an->no_ps_filter) {
1393 tid->ac->clear_ps_filter = false;
1394 tx_info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
1397 ath_tx_fill_desc(sc, bf, txq, aggr_len);
1398 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1402 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
1405 struct ath_atx_tid *txtid;
1406 struct ath_txq *txq;
1407 struct ath_node *an;
1410 an = (struct ath_node *)sta->drv_priv;
1411 txtid = ATH_AN_2_TID(an, tid);
1412 txq = txtid->ac->txq;
1414 ath_txq_lock(sc, txq);
1416 /* update ampdu factor/density, they may have changed. This may happen
1417 * in HT IBSS when a beacon with HT-info is received after the station
1418 * has already been added.
1420 if (sta->ht_cap.ht_supported) {
1421 an->maxampdu = (1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
1422 sta->ht_cap.ampdu_factor)) - 1;
1423 density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density);
1424 an->mpdudensity = density;
1427 /* force sequence number allocation for pending frames */
1428 ath_tx_tid_change_state(sc, txtid);
1430 txtid->active = true;
1431 *ssn = txtid->seq_start = txtid->seq_next;
1432 txtid->bar_index = -1;
1434 memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf));
1435 txtid->baw_head = txtid->baw_tail = 0;
1437 ath_txq_unlock_complete(sc, txq);
1442 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
1444 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1445 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
1446 struct ath_txq *txq = txtid->ac->txq;
1448 ath_txq_lock(sc, txq);
1449 txtid->active = false;
1450 ath_tx_flush_tid(sc, txtid);
1451 ath_tx_tid_change_state(sc, txtid);
1452 ath_txq_unlock_complete(sc, txq);
1455 void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc,
1456 struct ath_node *an)
1458 struct ath_atx_tid *tid;
1459 struct ath_atx_ac *ac;
1460 struct ath_txq *txq;
1464 for (tidno = 0, tid = &an->tid[tidno];
1465 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
1470 ath_txq_lock(sc, txq);
1473 ath_txq_unlock(sc, txq);
1477 buffered = ath_tid_has_buffered(tid);
1480 list_del(&tid->list);
1484 list_del(&ac->list);
1487 ath_txq_unlock(sc, txq);
1489 ieee80211_sta_set_buffered(sta, tidno, buffered);
1493 void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an)
1495 struct ath_atx_tid *tid;
1496 struct ath_atx_ac *ac;
1497 struct ath_txq *txq;
1500 for (tidno = 0, tid = &an->tid[tidno];
1501 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
1506 ath_txq_lock(sc, txq);
1507 ac->clear_ps_filter = true;
1509 if (ath_tid_has_buffered(tid)) {
1510 ath_tx_queue_tid(sc, txq, tid);
1511 ath_txq_schedule(sc, txq);
1514 ath_txq_unlock_complete(sc, txq);
1518 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta,
1521 struct ath_atx_tid *tid;
1522 struct ath_node *an;
1523 struct ath_txq *txq;
1525 an = (struct ath_node *)sta->drv_priv;
1526 tid = ATH_AN_2_TID(an, tidno);
1529 ath_txq_lock(sc, txq);
1531 tid->baw_size = IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
1533 if (ath_tid_has_buffered(tid)) {
1534 ath_tx_queue_tid(sc, txq, tid);
1535 ath_txq_schedule(sc, txq);
1538 ath_txq_unlock_complete(sc, txq);
1541 void ath9k_release_buffered_frames(struct ieee80211_hw *hw,
1542 struct ieee80211_sta *sta,
1543 u16 tids, int nframes,
1544 enum ieee80211_frame_release_type reason,
1547 struct ath_softc *sc = hw->priv;
1548 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1549 struct ath_txq *txq = sc->tx.uapsdq;
1550 struct ieee80211_tx_info *info;
1551 struct list_head bf_q;
1552 struct ath_buf *bf_tail = NULL, *bf;
1553 struct sk_buff_head *tid_q;
1557 INIT_LIST_HEAD(&bf_q);
1558 for (i = 0; tids && nframes; i++, tids >>= 1) {
1559 struct ath_atx_tid *tid;
1564 tid = ATH_AN_2_TID(an, i);
1566 ath_txq_lock(sc, tid->ac->txq);
1567 while (nframes > 0) {
1568 bf = ath_tx_get_tid_subframe(sc, sc->tx.uapsdq, tid, &tid_q);
1572 __skb_unlink(bf->bf_mpdu, tid_q);
1573 list_add_tail(&bf->list, &bf_q);
1574 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1575 if (bf_isampdu(bf)) {
1576 ath_tx_addto_baw(sc, tid, bf);
1577 bf->bf_state.bf_type &= ~BUF_AGGR;
1580 bf_tail->bf_next = bf;
1585 TX_STAT_INC(txq->axq_qnum, a_queued_hw);
1587 if (an->sta && !ath_tid_has_buffered(tid))
1588 ieee80211_sta_set_buffered(an->sta, i, false);
1590 ath_txq_unlock_complete(sc, tid->ac->txq);
1593 if (list_empty(&bf_q))
1596 info = IEEE80211_SKB_CB(bf_tail->bf_mpdu);
1597 info->flags |= IEEE80211_TX_STATUS_EOSP;
1599 bf = list_first_entry(&bf_q, struct ath_buf, list);
1600 ath_txq_lock(sc, txq);
1601 ath_tx_fill_desc(sc, bf, txq, 0);
1602 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1603 ath_txq_unlock(sc, txq);
1606 /********************/
1607 /* Queue Management */
1608 /********************/
1610 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
1612 struct ath_hw *ah = sc->sc_ah;
1613 struct ath9k_tx_queue_info qi;
1614 static const int subtype_txq_to_hwq[] = {
1615 [IEEE80211_AC_BE] = ATH_TXQ_AC_BE,
1616 [IEEE80211_AC_BK] = ATH_TXQ_AC_BK,
1617 [IEEE80211_AC_VI] = ATH_TXQ_AC_VI,
1618 [IEEE80211_AC_VO] = ATH_TXQ_AC_VO,
1622 memset(&qi, 0, sizeof(qi));
1623 qi.tqi_subtype = subtype_txq_to_hwq[subtype];
1624 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
1625 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
1626 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
1627 qi.tqi_physCompBuf = 0;
1630 * Enable interrupts only for EOL and DESC conditions.
1631 * We mark tx descriptors to receive a DESC interrupt
1632 * when a tx queue gets deep; otherwise waiting for the
1633 * EOL to reap descriptors. Note that this is done to
1634 * reduce interrupt load and this only defers reaping
1635 * descriptors, never transmitting frames. Aside from
1636 * reducing interrupts this also permits more concurrency.
1637 * The only potential downside is if the tx queue backs
1638 * up in which case the top half of the kernel may backup
1639 * due to a lack of tx descriptors.
1641 * The UAPSD queue is an exception, since we take a desc-
1642 * based intr on the EOSP frames.
1644 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1645 qi.tqi_qflags = TXQ_FLAG_TXINT_ENABLE;
1647 if (qtype == ATH9K_TX_QUEUE_UAPSD)
1648 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
1650 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
1651 TXQ_FLAG_TXDESCINT_ENABLE;
1653 axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
1654 if (axq_qnum == -1) {
1656 * NB: don't print a message, this happens
1657 * normally on parts with too few tx queues
1661 if (!ATH_TXQ_SETUP(sc, axq_qnum)) {
1662 struct ath_txq *txq = &sc->tx.txq[axq_qnum];
1664 txq->axq_qnum = axq_qnum;
1665 txq->mac80211_qnum = -1;
1666 txq->axq_link = NULL;
1667 __skb_queue_head_init(&txq->complete_q);
1668 INIT_LIST_HEAD(&txq->axq_q);
1669 spin_lock_init(&txq->axq_lock);
1671 txq->axq_ampdu_depth = 0;
1672 txq->axq_tx_inprogress = false;
1673 sc->tx.txqsetup |= 1<<axq_qnum;
1675 txq->txq_headidx = txq->txq_tailidx = 0;
1676 for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
1677 INIT_LIST_HEAD(&txq->txq_fifo[i]);
1679 return &sc->tx.txq[axq_qnum];
1682 int ath_txq_update(struct ath_softc *sc, int qnum,
1683 struct ath9k_tx_queue_info *qinfo)
1685 struct ath_hw *ah = sc->sc_ah;
1687 struct ath9k_tx_queue_info qi;
1689 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum);
1691 ath9k_hw_get_txq_props(ah, qnum, &qi);
1692 qi.tqi_aifs = qinfo->tqi_aifs;
1693 qi.tqi_cwmin = qinfo->tqi_cwmin;
1694 qi.tqi_cwmax = qinfo->tqi_cwmax;
1695 qi.tqi_burstTime = qinfo->tqi_burstTime;
1696 qi.tqi_readyTime = qinfo->tqi_readyTime;
1698 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
1699 ath_err(ath9k_hw_common(sc->sc_ah),
1700 "Unable to update hardware queue %u!\n", qnum);
1703 ath9k_hw_resettxqueue(ah, qnum);
1709 int ath_cabq_update(struct ath_softc *sc)
1711 struct ath9k_tx_queue_info qi;
1712 struct ath_beacon_config *cur_conf = &sc->cur_chan->beacon;
1713 int qnum = sc->beacon.cabq->axq_qnum;
1715 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
1717 qi.tqi_readyTime = (TU_TO_USEC(cur_conf->beacon_interval) *
1718 ATH_CABQ_READY_TIME) / 100;
1719 ath_txq_update(sc, qnum, &qi);
1724 static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq,
1725 struct list_head *list)
1727 struct ath_buf *bf, *lastbf;
1728 struct list_head bf_head;
1729 struct ath_tx_status ts;
1731 memset(&ts, 0, sizeof(ts));
1732 ts.ts_status = ATH9K_TX_FLUSH;
1733 INIT_LIST_HEAD(&bf_head);
1735 while (!list_empty(list)) {
1736 bf = list_first_entry(list, struct ath_buf, list);
1738 if (bf->bf_state.stale) {
1739 list_del(&bf->list);
1741 ath_tx_return_buffer(sc, bf);
1745 lastbf = bf->bf_lastbf;
1746 list_cut_position(&bf_head, list, &lastbf->list);
1747 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
1752 * Drain a given TX queue (could be Beacon or Data)
1754 * This assumes output has been stopped and
1755 * we do not need to block ath_tx_tasklet.
1757 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq)
1759 ath_txq_lock(sc, txq);
1761 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1762 int idx = txq->txq_tailidx;
1764 while (!list_empty(&txq->txq_fifo[idx])) {
1765 ath_drain_txq_list(sc, txq, &txq->txq_fifo[idx]);
1767 INCR(idx, ATH_TXFIFO_DEPTH);
1769 txq->txq_tailidx = idx;
1772 txq->axq_link = NULL;
1773 txq->axq_tx_inprogress = false;
1774 ath_drain_txq_list(sc, txq, &txq->axq_q);
1776 ath_txq_unlock_complete(sc, txq);
1779 bool ath_drain_all_txq(struct ath_softc *sc)
1781 struct ath_hw *ah = sc->sc_ah;
1782 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1783 struct ath_txq *txq;
1787 if (test_bit(ATH_OP_INVALID, &common->op_flags))
1790 ath9k_hw_abort_tx_dma(ah);
1792 /* Check if any queue remains active */
1793 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1794 if (!ATH_TXQ_SETUP(sc, i))
1797 if (!sc->tx.txq[i].axq_depth)
1800 if (ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum))
1805 ath_err(common, "Failed to stop TX DMA, queues=0x%03x!\n", npend);
1807 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1808 if (!ATH_TXQ_SETUP(sc, i))
1812 * The caller will resume queues with ieee80211_wake_queues.
1813 * Mark the queue as not stopped to prevent ath_tx_complete
1814 * from waking the queue too early.
1816 txq = &sc->tx.txq[i];
1817 txq->stopped = false;
1818 ath_draintxq(sc, txq);
1824 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1826 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1827 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1830 /* For each acq entry, for each tid, try to schedule packets
1831 * for transmit until ampdu_depth has reached min Q depth.
1833 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1835 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1836 struct ath_atx_ac *ac, *last_ac;
1837 struct ath_atx_tid *tid, *last_tid;
1838 struct list_head *ac_list;
1841 if (txq->mac80211_qnum < 0)
1844 if (test_bit(ATH_OP_HW_RESET, &common->op_flags))
1847 spin_lock_bh(&sc->chan_lock);
1848 ac_list = &sc->cur_chan->acq[txq->mac80211_qnum];
1850 if (list_empty(ac_list)) {
1851 spin_unlock_bh(&sc->chan_lock);
1857 last_ac = list_entry(ac_list->prev, struct ath_atx_ac, list);
1858 while (!list_empty(ac_list)) {
1861 if (sc->cur_chan->stopped)
1864 ac = list_first_entry(ac_list, struct ath_atx_ac, list);
1865 last_tid = list_entry(ac->tid_q.prev, struct ath_atx_tid, list);
1866 list_del(&ac->list);
1869 while (!list_empty(&ac->tid_q)) {
1871 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid,
1873 list_del(&tid->list);
1876 if (ath_tx_sched_aggr(sc, txq, tid, &stop))
1880 * add tid to round-robin queue if more frames
1881 * are pending for the tid
1883 if (ath_tid_has_buffered(tid))
1884 ath_tx_queue_tid(sc, txq, tid);
1886 if (stop || tid == last_tid)
1890 if (!list_empty(&ac->tid_q) && !ac->sched) {
1892 list_add_tail(&ac->list, ac_list);
1898 if (ac == last_ac) {
1903 last_ac = list_entry(ac_list->prev,
1904 struct ath_atx_ac, list);
1909 spin_unlock_bh(&sc->chan_lock);
1912 void ath_txq_schedule_all(struct ath_softc *sc)
1914 struct ath_txq *txq;
1917 for (i = 0; i < IEEE80211_NUM_ACS; i++) {
1918 txq = sc->tx.txq_map[i];
1920 spin_lock_bh(&txq->axq_lock);
1921 ath_txq_schedule(sc, txq);
1922 spin_unlock_bh(&txq->axq_lock);
1931 * Insert a chain of ath_buf (descriptors) on a txq and
1932 * assume the descriptors are already chained together by caller.
1934 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1935 struct list_head *head, bool internal)
1937 struct ath_hw *ah = sc->sc_ah;
1938 struct ath_common *common = ath9k_hw_common(ah);
1939 struct ath_buf *bf, *bf_last;
1940 bool puttxbuf = false;
1944 * Insert the frame on the outbound list and
1945 * pass it on to the hardware.
1948 if (list_empty(head))
1951 edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1952 bf = list_first_entry(head, struct ath_buf, list);
1953 bf_last = list_entry(head->prev, struct ath_buf, list);
1955 ath_dbg(common, QUEUE, "qnum: %d, txq depth: %d\n",
1956 txq->axq_qnum, txq->axq_depth);
1958 if (edma && list_empty(&txq->txq_fifo[txq->txq_headidx])) {
1959 list_splice_tail_init(head, &txq->txq_fifo[txq->txq_headidx]);
1960 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
1963 list_splice_tail_init(head, &txq->axq_q);
1965 if (txq->axq_link) {
1966 ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr);
1967 ath_dbg(common, XMIT, "link[%u] (%p)=%llx (%p)\n",
1968 txq->axq_qnum, txq->axq_link,
1969 ito64(bf->bf_daddr), bf->bf_desc);
1973 txq->axq_link = bf_last->bf_desc;
1977 TX_STAT_INC(txq->axq_qnum, puttxbuf);
1978 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1979 ath_dbg(common, XMIT, "TXDP[%u] = %llx (%p)\n",
1980 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
1983 if (!edma || sc->tx99_state) {
1984 TX_STAT_INC(txq->axq_qnum, txstart);
1985 ath9k_hw_txstart(ah, txq->axq_qnum);
1991 if (bf_is_ampdu_not_probing(bf))
1992 txq->axq_ampdu_depth++;
1994 bf_last = bf->bf_lastbf;
1995 bf = bf_last->bf_next;
1996 bf_last->bf_next = NULL;
2001 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
2002 struct ath_atx_tid *tid, struct sk_buff *skb)
2004 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2005 struct ath_frame_info *fi = get_frame_info(skb);
2006 struct list_head bf_head;
2007 struct ath_buf *bf = fi->bf;
2009 INIT_LIST_HEAD(&bf_head);
2010 list_add_tail(&bf->list, &bf_head);
2011 bf->bf_state.bf_type = 0;
2012 if (tid && (tx_info->flags & IEEE80211_TX_CTL_AMPDU)) {
2013 bf->bf_state.bf_type = BUF_AMPDU;
2014 ath_tx_addto_baw(sc, tid, bf);
2019 ath_tx_fill_desc(sc, bf, txq, fi->framelen);
2020 ath_tx_txqaddbuf(sc, txq, &bf_head, false);
2021 TX_STAT_INC(txq->axq_qnum, queued);
2024 static void setup_frame_info(struct ieee80211_hw *hw,
2025 struct ieee80211_sta *sta,
2026 struct sk_buff *skb,
2029 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2030 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key;
2031 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2032 const struct ieee80211_rate *rate;
2033 struct ath_frame_info *fi = get_frame_info(skb);
2034 struct ath_node *an = NULL;
2035 enum ath9k_key_type keytype;
2036 bool short_preamble = false;
2039 * We check if Short Preamble is needed for the CTS rate by
2040 * checking the BSS's global flag.
2041 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
2043 if (tx_info->control.vif &&
2044 tx_info->control.vif->bss_conf.use_short_preamble)
2045 short_preamble = true;
2047 rate = ieee80211_get_rts_cts_rate(hw, tx_info);
2048 keytype = ath9k_cmn_get_hw_crypto_keytype(skb);
2051 an = (struct ath_node *) sta->drv_priv;
2053 memset(fi, 0, sizeof(*fi));
2056 fi->keyix = hw_key->hw_key_idx;
2057 else if (an && ieee80211_is_data(hdr->frame_control) && an->ps_key > 0)
2058 fi->keyix = an->ps_key;
2060 fi->keyix = ATH9K_TXKEYIX_INVALID;
2061 fi->keytype = keytype;
2062 fi->framelen = framelen;
2066 fi->rtscts_rate = rate->hw_value;
2068 fi->rtscts_rate |= rate->hw_value_short;
2071 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate)
2073 struct ath_hw *ah = sc->sc_ah;
2074 struct ath9k_channel *curchan = ah->curchan;
2076 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && IS_CHAN_5GHZ(curchan) &&
2077 (chainmask == 0x7) && (rate < 0x90))
2079 else if (AR_SREV_9462(ah) && ath9k_hw_btcoex_is_enabled(ah) &&
2087 * Assign a descriptor (and sequence number if necessary,
2088 * and map buffer for DMA. Frees skb on error
2090 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
2091 struct ath_txq *txq,
2092 struct ath_atx_tid *tid,
2093 struct sk_buff *skb)
2095 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2096 struct ath_frame_info *fi = get_frame_info(skb);
2097 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2102 bf = ath_tx_get_buffer(sc);
2104 ath_dbg(common, XMIT, "TX buffers are full\n");
2108 ATH_TXBUF_RESET(bf);
2110 if (tid && ieee80211_is_data_present(hdr->frame_control)) {
2111 fragno = le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG;
2112 seqno = tid->seq_next;
2113 hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT);
2116 hdr->seq_ctrl |= cpu_to_le16(fragno);
2118 if (!ieee80211_has_morefrags(hdr->frame_control))
2119 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
2121 bf->bf_state.seqno = seqno;
2126 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
2127 skb->len, DMA_TO_DEVICE);
2128 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
2130 bf->bf_buf_addr = 0;
2131 ath_err(ath9k_hw_common(sc->sc_ah),
2132 "dma_mapping_error() on TX\n");
2133 ath_tx_return_buffer(sc, bf);
2142 void ath_assign_seq(struct ath_common *common, struct sk_buff *skb)
2144 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2145 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2146 struct ieee80211_vif *vif = info->control.vif;
2147 struct ath_vif *avp;
2149 if (!(info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ))
2155 avp = (struct ath_vif *)vif->drv_priv;
2157 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2158 avp->seq_no += 0x10;
2160 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2161 hdr->seq_ctrl |= cpu_to_le16(avp->seq_no);
2164 static int ath_tx_prepare(struct ieee80211_hw *hw, struct sk_buff *skb,
2165 struct ath_tx_control *txctl)
2167 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2168 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2169 struct ieee80211_sta *sta = txctl->sta;
2170 struct ieee80211_vif *vif = info->control.vif;
2171 struct ath_vif *avp;
2172 struct ath_softc *sc = hw->priv;
2173 int frmlen = skb->len + FCS_LEN;
2174 int padpos, padsize;
2176 /* NOTE: sta can be NULL according to net/mac80211.h */
2178 txctl->an = (struct ath_node *)sta->drv_priv;
2179 else if (vif && ieee80211_is_data(hdr->frame_control)) {
2180 avp = (void *)vif->drv_priv;
2181 txctl->an = &avp->mcast_node;
2184 if (info->control.hw_key)
2185 frmlen += info->control.hw_key->icv_len;
2187 ath_assign_seq(ath9k_hw_common(sc->sc_ah), skb);
2189 if ((vif && vif->type != NL80211_IFTYPE_AP &&
2190 vif->type != NL80211_IFTYPE_AP_VLAN) ||
2191 !ieee80211_is_data(hdr->frame_control))
2192 info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
2194 /* Add the padding after the header if this is not already done */
2195 padpos = ieee80211_hdrlen(hdr->frame_control);
2196 padsize = padpos & 3;
2197 if (padsize && skb->len > padpos) {
2198 if (skb_headroom(skb) < padsize)
2201 skb_push(skb, padsize);
2202 memmove(skb->data, skb->data + padsize, padpos);
2205 setup_frame_info(hw, sta, skb, frmlen);
2210 /* Upon failure caller should free skb */
2211 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
2212 struct ath_tx_control *txctl)
2214 struct ieee80211_hdr *hdr;
2215 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2216 struct ieee80211_sta *sta = txctl->sta;
2217 struct ieee80211_vif *vif = info->control.vif;
2218 struct ath_frame_info *fi = get_frame_info(skb);
2219 struct ath_vif *avp = NULL;
2220 struct ath_softc *sc = hw->priv;
2221 struct ath_txq *txq = txctl->txq;
2222 struct ath_atx_tid *tid = NULL;
2224 bool queue, skip_uapsd = false;
2228 avp = (void *)vif->drv_priv;
2230 if (info->flags & IEEE80211_TX_CTL_TX_OFFCHAN)
2231 txctl->force_channel = true;
2233 ret = ath_tx_prepare(hw, skb, txctl);
2237 hdr = (struct ieee80211_hdr *) skb->data;
2239 * At this point, the vif, hw_key and sta pointers in the tx control
2240 * info are no longer valid (overwritten by the ath_frame_info data.
2243 q = skb_get_queue_mapping(skb);
2245 ath_txq_lock(sc, txq);
2246 if (txq == sc->tx.txq_map[q]) {
2248 if (++txq->pending_frames > sc->tx.txq_max_pending[q] &&
2250 ieee80211_stop_queue(sc->hw, info->hw_queue);
2251 txq->stopped = true;
2255 queue = ieee80211_is_data_present(hdr->frame_control);
2257 /* Force queueing of all frames that belong to a virtual interface on
2258 * a different channel context, to ensure that they are sent on the
2261 if (((avp && avp->chanctx != sc->cur_chan) ||
2262 sc->cur_chan->stopped) && !txctl->force_channel) {
2264 txctl->an = &avp->mcast_node;
2269 if (txctl->an && queue)
2270 tid = ath_get_skb_tid(sc, txctl->an, skb);
2272 if (!skip_uapsd && (info->flags & IEEE80211_TX_CTL_PS_RESPONSE)) {
2273 ath_txq_unlock(sc, txq);
2274 txq = sc->tx.uapsdq;
2275 ath_txq_lock(sc, txq);
2276 } else if (txctl->an && queue) {
2277 WARN_ON(tid->ac->txq != txctl->txq);
2279 if (info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT)
2280 tid->ac->clear_ps_filter = true;
2283 * Add this frame to software queue for scheduling later
2286 TX_STAT_INC(txq->axq_qnum, a_queued_sw);
2287 __skb_queue_tail(&tid->buf_q, skb);
2288 if (!txctl->an->sleeping)
2289 ath_tx_queue_tid(sc, txq, tid);
2291 ath_txq_schedule(sc, txq);
2295 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
2297 ath_txq_skb_done(sc, txq, skb);
2299 dev_kfree_skb_any(skb);
2301 ieee80211_free_txskb(sc->hw, skb);
2305 bf->bf_state.bfs_paprd = txctl->paprd;
2308 bf->bf_state.bfs_paprd_timestamp = jiffies;
2310 ath_set_rates(vif, sta, bf);
2311 ath_tx_send_normal(sc, txq, tid, skb);
2314 ath_txq_unlock(sc, txq);
2319 void ath_tx_cabq(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2320 struct sk_buff *skb)
2322 struct ath_softc *sc = hw->priv;
2323 struct ath_tx_control txctl = {
2324 .txq = sc->beacon.cabq
2326 struct ath_tx_info info = {};
2327 struct ieee80211_hdr *hdr;
2328 struct ath_buf *bf_tail = NULL;
2335 sc->cur_chan->beacon.beacon_interval * 1000 *
2336 sc->cur_chan->beacon.dtim_period / ATH_BCBUF;
2339 struct ath_frame_info *fi = get_frame_info(skb);
2341 if (ath_tx_prepare(hw, skb, &txctl))
2344 bf = ath_tx_setup_buffer(sc, txctl.txq, NULL, skb);
2349 ath_set_rates(vif, NULL, bf);
2350 ath_buf_set_rate(sc, bf, &info, fi->framelen, false);
2351 duration += info.rates[0].PktDuration;
2353 bf_tail->bf_next = bf;
2355 list_add_tail(&bf->list, &bf_q);
2359 if (duration > max_duration)
2362 skb = ieee80211_get_buffered_bc(hw, vif);
2366 ieee80211_free_txskb(hw, skb);
2368 if (list_empty(&bf_q))
2371 bf = list_first_entry(&bf_q, struct ath_buf, list);
2372 hdr = (struct ieee80211_hdr *) bf->bf_mpdu->data;
2374 if (hdr->frame_control & IEEE80211_FCTL_MOREDATA) {
2375 hdr->frame_control &= ~IEEE80211_FCTL_MOREDATA;
2376 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
2377 sizeof(*hdr), DMA_TO_DEVICE);
2380 ath_txq_lock(sc, txctl.txq);
2381 ath_tx_fill_desc(sc, bf, txctl.txq, 0);
2382 ath_tx_txqaddbuf(sc, txctl.txq, &bf_q, false);
2383 TX_STAT_INC(txctl.txq->axq_qnum, queued);
2384 ath_txq_unlock(sc, txctl.txq);
2391 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
2392 int tx_flags, struct ath_txq *txq)
2394 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2395 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2396 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
2397 int padpos, padsize;
2398 unsigned long flags;
2400 ath_dbg(common, XMIT, "TX complete: skb: %p\n", skb);
2402 if (sc->sc_ah->caldata)
2403 set_bit(PAPRD_PACKET_SENT, &sc->sc_ah->caldata->cal_flags);
2405 if (!(tx_flags & ATH_TX_ERROR))
2406 /* Frame was ACKed */
2407 tx_info->flags |= IEEE80211_TX_STAT_ACK;
2409 padpos = ieee80211_hdrlen(hdr->frame_control);
2410 padsize = padpos & 3;
2411 if (padsize && skb->len>padpos+padsize) {
2413 * Remove MAC header padding before giving the frame back to
2416 memmove(skb->data + padsize, skb->data, padpos);
2417 skb_pull(skb, padsize);
2420 spin_lock_irqsave(&sc->sc_pm_lock, flags);
2421 if ((sc->ps_flags & PS_WAIT_FOR_TX_ACK) && !txq->axq_depth) {
2422 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
2424 "Going back to sleep after having received TX status (0x%lx)\n",
2425 sc->ps_flags & (PS_WAIT_FOR_BEACON |
2427 PS_WAIT_FOR_PSPOLL_DATA |
2428 PS_WAIT_FOR_TX_ACK));
2430 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
2432 __skb_queue_tail(&txq->complete_q, skb);
2433 ath_txq_skb_done(sc, txq, skb);
2436 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
2437 struct ath_txq *txq, struct list_head *bf_q,
2438 struct ath_tx_status *ts, int txok)
2440 struct sk_buff *skb = bf->bf_mpdu;
2441 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2442 unsigned long flags;
2446 tx_flags |= ATH_TX_ERROR;
2448 if (ts->ts_status & ATH9K_TXERR_FILT)
2449 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
2451 dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE);
2452 bf->bf_buf_addr = 0;
2454 goto skip_tx_complete;
2456 if (bf->bf_state.bfs_paprd) {
2457 if (time_after(jiffies,
2458 bf->bf_state.bfs_paprd_timestamp +
2459 msecs_to_jiffies(ATH_PAPRD_TIMEOUT)))
2460 dev_kfree_skb_any(skb);
2462 complete(&sc->paprd_complete);
2464 ath_debug_stat_tx(sc, bf, ts, txq, tx_flags);
2465 ath_tx_complete(sc, skb, tx_flags, txq);
2468 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
2469 * accidentally reference it later.
2474 * Return the list of ath_buf of this mpdu to free queue
2476 spin_lock_irqsave(&sc->tx.txbuflock, flags);
2477 list_splice_tail_init(bf_q, &sc->tx.txbuf);
2478 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
2481 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
2482 struct ath_tx_status *ts, int nframes, int nbad,
2485 struct sk_buff *skb = bf->bf_mpdu;
2486 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2487 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2488 struct ieee80211_hw *hw = sc->hw;
2489 struct ath_hw *ah = sc->sc_ah;
2493 tx_info->status.ack_signal = ts->ts_rssi;
2495 tx_rateindex = ts->ts_rateindex;
2496 WARN_ON(tx_rateindex >= hw->max_rates);
2498 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
2499 tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
2501 BUG_ON(nbad > nframes);
2503 tx_info->status.ampdu_len = nframes;
2504 tx_info->status.ampdu_ack_len = nframes - nbad;
2506 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
2507 (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) == 0) {
2509 * If an underrun error is seen assume it as an excessive
2510 * retry only if max frame trigger level has been reached
2511 * (2 KB for single stream, and 4 KB for dual stream).
2512 * Adjust the long retry as if the frame was tried
2513 * hw->max_rate_tries times to affect how rate control updates
2514 * PER for the failed rate.
2515 * In case of congestion on the bus penalizing this type of
2516 * underruns should help hardware actually transmit new frames
2517 * successfully by eventually preferring slower rates.
2518 * This itself should also alleviate congestion on the bus.
2520 if (unlikely(ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN |
2521 ATH9K_TX_DELIM_UNDERRUN)) &&
2522 ieee80211_is_data(hdr->frame_control) &&
2523 ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level)
2524 tx_info->status.rates[tx_rateindex].count =
2528 for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
2529 tx_info->status.rates[i].count = 0;
2530 tx_info->status.rates[i].idx = -1;
2533 tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1;
2536 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
2538 struct ath_hw *ah = sc->sc_ah;
2539 struct ath_common *common = ath9k_hw_common(ah);
2540 struct ath_buf *bf, *lastbf, *bf_held = NULL;
2541 struct list_head bf_head;
2542 struct ath_desc *ds;
2543 struct ath_tx_status ts;
2546 ath_dbg(common, QUEUE, "tx queue %d (%x), link %p\n",
2547 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
2550 ath_txq_lock(sc, txq);
2552 if (test_bit(ATH_OP_HW_RESET, &common->op_flags))
2555 if (list_empty(&txq->axq_q)) {
2556 txq->axq_link = NULL;
2557 ath_txq_schedule(sc, txq);
2560 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
2563 * There is a race condition that a BH gets scheduled
2564 * after sw writes TxE and before hw re-load the last
2565 * descriptor to get the newly chained one.
2566 * Software must keep the last DONE descriptor as a
2567 * holding descriptor - software does so by marking
2568 * it with the STALE flag.
2571 if (bf->bf_state.stale) {
2573 if (list_is_last(&bf_held->list, &txq->axq_q))
2576 bf = list_entry(bf_held->list.next, struct ath_buf,
2580 lastbf = bf->bf_lastbf;
2581 ds = lastbf->bf_desc;
2583 memset(&ts, 0, sizeof(ts));
2584 status = ath9k_hw_txprocdesc(ah, ds, &ts);
2585 if (status == -EINPROGRESS)
2588 TX_STAT_INC(txq->axq_qnum, txprocdesc);
2591 * Remove ath_buf's of the same transmit unit from txq,
2592 * however leave the last descriptor back as the holding
2593 * descriptor for hw.
2595 lastbf->bf_state.stale = true;
2596 INIT_LIST_HEAD(&bf_head);
2597 if (!list_is_singular(&lastbf->list))
2598 list_cut_position(&bf_head,
2599 &txq->axq_q, lastbf->list.prev);
2602 list_del(&bf_held->list);
2603 ath_tx_return_buffer(sc, bf_held);
2606 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2608 ath_txq_unlock_complete(sc, txq);
2611 void ath_tx_tasklet(struct ath_softc *sc)
2613 struct ath_hw *ah = sc->sc_ah;
2614 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1) & ah->intr_txqs;
2617 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2618 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2619 ath_tx_processq(sc, &sc->tx.txq[i]);
2623 void ath_tx_edma_tasklet(struct ath_softc *sc)
2625 struct ath_tx_status ts;
2626 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2627 struct ath_hw *ah = sc->sc_ah;
2628 struct ath_txq *txq;
2629 struct ath_buf *bf, *lastbf;
2630 struct list_head bf_head;
2631 struct list_head *fifo_list;
2635 if (test_bit(ATH_OP_HW_RESET, &common->op_flags))
2638 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts);
2639 if (status == -EINPROGRESS)
2641 if (status == -EIO) {
2642 ath_dbg(common, XMIT, "Error processing tx status\n");
2646 /* Process beacon completions separately */
2647 if (ts.qid == sc->beacon.beaconq) {
2648 sc->beacon.tx_processed = true;
2649 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
2651 if (ath9k_is_chanctx_enabled()) {
2652 ath_chanctx_event(sc, NULL,
2653 ATH_CHANCTX_EVENT_BEACON_SENT);
2656 ath9k_csa_update(sc);
2660 txq = &sc->tx.txq[ts.qid];
2662 ath_txq_lock(sc, txq);
2664 TX_STAT_INC(txq->axq_qnum, txprocdesc);
2666 fifo_list = &txq->txq_fifo[txq->txq_tailidx];
2667 if (list_empty(fifo_list)) {
2668 ath_txq_unlock(sc, txq);
2672 bf = list_first_entry(fifo_list, struct ath_buf, list);
2673 if (bf->bf_state.stale) {
2674 list_del(&bf->list);
2675 ath_tx_return_buffer(sc, bf);
2676 bf = list_first_entry(fifo_list, struct ath_buf, list);
2679 lastbf = bf->bf_lastbf;
2681 INIT_LIST_HEAD(&bf_head);
2682 if (list_is_last(&lastbf->list, fifo_list)) {
2683 list_splice_tail_init(fifo_list, &bf_head);
2684 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
2686 if (!list_empty(&txq->axq_q)) {
2687 struct list_head bf_q;
2689 INIT_LIST_HEAD(&bf_q);
2690 txq->axq_link = NULL;
2691 list_splice_tail_init(&txq->axq_q, &bf_q);
2692 ath_tx_txqaddbuf(sc, txq, &bf_q, true);
2695 lastbf->bf_state.stale = true;
2697 list_cut_position(&bf_head, fifo_list,
2701 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2702 ath_txq_unlock_complete(sc, txq);
2710 static int ath_txstatus_setup(struct ath_softc *sc, int size)
2712 struct ath_descdma *dd = &sc->txsdma;
2713 u8 txs_len = sc->sc_ah->caps.txs_len;
2715 dd->dd_desc_len = size * txs_len;
2716 dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len,
2717 &dd->dd_desc_paddr, GFP_KERNEL);
2724 static int ath_tx_edma_init(struct ath_softc *sc)
2728 err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE);
2730 ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc,
2731 sc->txsdma.dd_desc_paddr,
2732 ATH_TXSTATUS_RING_SIZE);
2737 int ath_tx_init(struct ath_softc *sc, int nbufs)
2739 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2742 spin_lock_init(&sc->tx.txbuflock);
2744 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2748 "Failed to allocate tx descriptors: %d\n", error);
2752 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2753 "beacon", ATH_BCBUF, 1, 1);
2756 "Failed to allocate beacon descriptors: %d\n", error);
2760 INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work);
2762 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
2763 error = ath_tx_edma_init(sc);
2768 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2770 struct ath_atx_tid *tid;
2771 struct ath_atx_ac *ac;
2774 for (tidno = 0, tid = &an->tid[tidno];
2775 tidno < IEEE80211_NUM_TIDS;
2779 tid->seq_start = tid->seq_next = 0;
2780 tid->baw_size = WME_MAX_BA;
2781 tid->baw_head = tid->baw_tail = 0;
2783 tid->active = false;
2784 __skb_queue_head_init(&tid->buf_q);
2785 __skb_queue_head_init(&tid->retry_q);
2786 acno = TID_TO_WME_AC(tidno);
2787 tid->ac = &an->ac[acno];
2790 for (acno = 0, ac = &an->ac[acno];
2791 acno < IEEE80211_NUM_ACS; acno++, ac++) {
2793 ac->clear_ps_filter = true;
2794 ac->txq = sc->tx.txq_map[acno];
2795 INIT_LIST_HEAD(&ac->tid_q);
2799 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2801 struct ath_atx_ac *ac;
2802 struct ath_atx_tid *tid;
2803 struct ath_txq *txq;
2806 for (tidno = 0, tid = &an->tid[tidno];
2807 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
2812 ath_txq_lock(sc, txq);
2815 list_del(&tid->list);
2820 list_del(&ac->list);
2821 tid->ac->sched = false;
2824 ath_tid_drain(sc, txq, tid);
2825 tid->active = false;
2827 ath_txq_unlock(sc, txq);
2831 #ifdef CONFIG_ATH9K_TX99
2833 int ath9k_tx99_send(struct ath_softc *sc, struct sk_buff *skb,
2834 struct ath_tx_control *txctl)
2836 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2837 struct ath_frame_info *fi = get_frame_info(skb);
2838 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2840 int padpos, padsize;
2842 padpos = ieee80211_hdrlen(hdr->frame_control);
2843 padsize = padpos & 3;
2845 if (padsize && skb->len > padpos) {
2846 if (skb_headroom(skb) < padsize) {
2847 ath_dbg(common, XMIT,
2848 "tx99 padding failed\n");
2852 skb_push(skb, padsize);
2853 memmove(skb->data, skb->data + padsize, padpos);
2856 fi->keyix = ATH9K_TXKEYIX_INVALID;
2857 fi->framelen = skb->len + FCS_LEN;
2858 fi->keytype = ATH9K_KEY_TYPE_CLEAR;
2860 bf = ath_tx_setup_buffer(sc, txctl->txq, NULL, skb);
2862 ath_dbg(common, XMIT, "tx99 buffer setup failed\n");
2866 ath_set_rates(sc->tx99_vif, NULL, bf);
2868 ath9k_hw_set_desc_link(sc->sc_ah, bf->bf_desc, bf->bf_daddr);
2869 ath9k_hw_tx99_start(sc->sc_ah, txctl->txq->axq_qnum);
2871 ath_tx_send_normal(sc, txctl->txq, NULL, skb);
2876 #endif /* CONFIG_ATH9K_TX99 */