drivers/net/wireless/ath/wil6210/interrupt.c

   1 /*
   2  * Copyright (c) 2012-2014 Qualcomm Atheros, Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/interrupt.h>
  18
  19 #include "wil6210.h"
  20 #include "trace.h"
  21
  22 /**
  23  * Theory of operation:
  24  *
  25  * There is ISR pseudo-cause register,
  26  * dma_rgf->DMA_RGF.PSEUDO_CAUSE.PSEUDO_CAUSE
  27  * Its bits represents OR'ed bits from 3 real ISR registers:
  28  * TX, RX, and MISC.
  29  *
  30  * Registers may be configured to either "write 1 to clear" or
  31  * "clear on read" mode
  32  *
  33  * When handling interrupt, one have to mask/unmask interrupts for the
  34  * real ISR registers, or hardware may malfunction.
  35  *
  36  */
  37
  38 #define WIL6210_IRQ_DISABLE     (0xFFFFFFFFUL)
  39 #define WIL6210_IMC_RX          (BIT_DMA_EP_RX_ICR_RX_DONE | \
  40                                  BIT_DMA_EP_RX_ICR_RX_HTRSH)
  41 #define WIL6210_IMC_TX          (BIT_DMA_EP_TX_ICR_TX_DONE | \
  42                                 BIT_DMA_EP_TX_ICR_TX_DONE_N(0))
  43 #define WIL6210_IMC_MISC        (ISR_MISC_FW_READY | \
  44                                  ISR_MISC_MBOX_EVT | \
  45                                  ISR_MISC_FW_ERROR)
  46
  47 #define WIL6210_IRQ_PSEUDO_MASK (u32)(~(BIT_DMA_PSEUDO_CAUSE_RX | \
  48                                         BIT_DMA_PSEUDO_CAUSE_TX | \
  49                                         BIT_DMA_PSEUDO_CAUSE_MISC))
  50
  51 #if defined(CONFIG_WIL6210_ISR_COR)
  52 /* configure to Clear-On-Read mode */
  53 #define WIL_ICR_ICC_VALUE       (0xFFFFFFFFUL)
  54
  55 static inline void wil_icr_clear(u32 x, void __iomem *addr)
  56 {
  57 }
  58 #else /* defined(CONFIG_WIL6210_ISR_COR) */
  59 /* configure to Write-1-to-Clear mode */
  60 #define WIL_ICR_ICC_VALUE       (0UL)
  61
  62 static inline void wil_icr_clear(u32 x, void __iomem *addr)
  63 {
  64         iowrite32(x, addr);
  65 }
  66 #endif /* defined(CONFIG_WIL6210_ISR_COR) */
  67
  68 static inline u32 wil_ioread32_and_clear(void __iomem *addr)
  69 {
  70         u32 x = ioread32(addr);
  71
  72         wil_icr_clear(x, addr);
  73
  74         return x;
  75 }
  76
  77 static void wil6210_mask_irq_tx(struct wil6210_priv *wil)
  78 {
  79         iowrite32(WIL6210_IRQ_DISABLE, wil->csr +
  80                   HOSTADDR(RGF_DMA_EP_TX_ICR) +
  81                   offsetof(struct RGF_ICR, IMS));
  82 }
  83
  84 static void wil6210_mask_irq_rx(struct wil6210_priv *wil)
  85 {
  86         iowrite32(WIL6210_IRQ_DISABLE, wil->csr +
  87                   HOSTADDR(RGF_DMA_EP_RX_ICR) +
  88                   offsetof(struct RGF_ICR, IMS));
  89 }
  90
  91 static void wil6210_mask_irq_misc(struct wil6210_priv *wil)
  92 {
  93         iowrite32(WIL6210_IRQ_DISABLE, wil->csr +
  94                   HOSTADDR(RGF_DMA_EP_MISC_ICR) +
  95                   offsetof(struct RGF_ICR, IMS));
  96 }
  97
  98 static void wil6210_mask_irq_pseudo(struct wil6210_priv *wil)
  99 {
 100         wil_dbg_irq(wil, "%s()\n", __func__);
 101
 102         iowrite32(WIL6210_IRQ_DISABLE, wil->csr +
 103                   HOSTADDR(RGF_DMA_PSEUDO_CAUSE_MASK_SW));
 104
 105         clear_bit(wil_status_irqen, wil->status);
 106 }
 107
 108 void wil6210_unmask_irq_tx(struct wil6210_priv *wil)
 109 {
 110         iowrite32(WIL6210_IMC_TX, wil->csr +
 111                   HOSTADDR(RGF_DMA_EP_TX_ICR) +
 112                   offsetof(struct RGF_ICR, IMC));
 113 }
 114
 115 void wil6210_unmask_irq_rx(struct wil6210_priv *wil)
 116 {
 117         iowrite32(WIL6210_IMC_RX, wil->csr +
 118                   HOSTADDR(RGF_DMA_EP_RX_ICR) +
 119                   offsetof(struct RGF_ICR, IMC));
 120 }
 121
 122 static void wil6210_unmask_irq_misc(struct wil6210_priv *wil)
 123 {
 124         iowrite32(WIL6210_IMC_MISC, wil->csr +
 125                   HOSTADDR(RGF_DMA_EP_MISC_ICR) +
 126                   offsetof(struct RGF_ICR, IMC));
 127 }
 128
 129 static void wil6210_unmask_irq_pseudo(struct wil6210_priv *wil)
 130 {
 131         wil_dbg_irq(wil, "%s()\n", __func__);
 132
 133         set_bit(wil_status_irqen, wil->status);
 134
 135         iowrite32(WIL6210_IRQ_PSEUDO_MASK, wil->csr +
 136                   HOSTADDR(RGF_DMA_PSEUDO_CAUSE_MASK_SW));
 137 }
 138
 139 void wil_mask_irq(struct wil6210_priv *wil)
 140 {
 141         wil_dbg_irq(wil, "%s()\n", __func__);
 142
 143         wil6210_mask_irq_tx(wil);
 144         wil6210_mask_irq_rx(wil);
 145         wil6210_mask_irq_misc(wil);
 146         wil6210_mask_irq_pseudo(wil);
 147 }
 148
 149 void wil_unmask_irq(struct wil6210_priv *wil)
 150 {
 151         wil_dbg_irq(wil, "%s()\n", __func__);
 152
 153         iowrite32(WIL_ICR_ICC_VALUE, wil->csr + HOSTADDR(RGF_DMA_EP_RX_ICR) +
 154                   offsetof(struct RGF_ICR, ICC));
 155         iowrite32(WIL_ICR_ICC_VALUE, wil->csr + HOSTADDR(RGF_DMA_EP_TX_ICR) +
 156                   offsetof(struct RGF_ICR, ICC));
 157         iowrite32(WIL_ICR_ICC_VALUE, wil->csr + HOSTADDR(RGF_DMA_EP_MISC_ICR) +
 158                   offsetof(struct RGF_ICR, ICC));
 159
 160         /* interrupt moderation parameters */
 161         wil_set_itr_trsh(wil);
 162
 163         wil6210_unmask_irq_pseudo(wil);
 164         wil6210_unmask_irq_tx(wil);
 165         wil6210_unmask_irq_rx(wil);
 166         wil6210_unmask_irq_misc(wil);
 167 }
 168
 169 static irqreturn_t wil6210_irq_rx(int irq, void *cookie)
 170 {
 171         struct wil6210_priv *wil = cookie;
 172         u32 isr = wil_ioread32_and_clear(wil->csr +
 173                                          HOSTADDR(RGF_DMA_EP_RX_ICR) +
 174                                          offsetof(struct RGF_ICR, ICR));
 175         bool need_unmask = true;
 176
 177         trace_wil6210_irq_rx(isr);
 178         wil_dbg_irq(wil, "ISR RX 0x%08x\n", isr);
 179
 180         if (!isr) {
 181                 wil_err(wil, "spurious IRQ: RX\n");
 182                 return IRQ_NONE;
 183         }
 184
 185         wil6210_mask_irq_rx(wil);
 186
 187         /* RX_DONE and RX_HTRSH interrupts are the same if interrupt
 188          * moderation is not used. Interrupt moderation may cause RX
 189          * buffer overflow while RX_DONE is delayed. The required
 190          * action is always the same - should empty the accumulated
 191          * packets from the RX ring.
 192          */
 193         if (isr & (BIT_DMA_EP_RX_ICR_RX_DONE | BIT_DMA_EP_RX_ICR_RX_HTRSH)) {
 194                 wil_dbg_irq(wil, "RX done\n");
 195
 196                 if (isr & BIT_DMA_EP_RX_ICR_RX_HTRSH)
 197                         wil_err_ratelimited(wil,
 198                                             "Received \"Rx buffer is in risk of overflow\" interrupt\n");
 199
 200                 isr &= ~(BIT_DMA_EP_RX_ICR_RX_DONE |
 201                          BIT_DMA_EP_RX_ICR_RX_HTRSH);
 202                 if (test_bit(wil_status_reset_done, wil->status)) {
 203                         if (test_bit(wil_status_napi_en, wil->status)) {
 204                                 wil_dbg_txrx(wil, "NAPI(Rx) schedule\n");
 205                                 need_unmask = false;
 206                                 napi_schedule(&wil->napi_rx);
 207                         } else {
 208                                 wil_err(wil,
 209                                         "Got Rx interrupt while stopping interface\n");
 210                         }
 211                 } else {
 212                         wil_err(wil, "Got Rx interrupt while in reset\n");
 213                 }
 214         }
 215
 216         if (isr)
 217                 wil_err(wil, "un-handled RX ISR bits 0x%08x\n", isr);
 218
 219         /* Rx IRQ will be enabled when NAPI processing finished */
 220
 221         atomic_inc(&wil->isr_count_rx);
 222
 223         if (unlikely(need_unmask))
 224                 wil6210_unmask_irq_rx(wil);
 225
 226         return IRQ_HANDLED;
 227 }
 228
 229 static irqreturn_t wil6210_irq_tx(int irq, void *cookie)
 230 {
 231         struct wil6210_priv *wil = cookie;
 232         u32 isr = wil_ioread32_and_clear(wil->csr +
 233                                          HOSTADDR(RGF_DMA_EP_TX_ICR) +
 234                                          offsetof(struct RGF_ICR, ICR));
 235         bool need_unmask = true;
 236
 237         trace_wil6210_irq_tx(isr);
 238         wil_dbg_irq(wil, "ISR TX 0x%08x\n", isr);
 239
 240         if (!isr) {
 241                 wil_err(wil, "spurious IRQ: TX\n");
 242                 return IRQ_NONE;
 243         }
 244
 245         wil6210_mask_irq_tx(wil);
 246
 247         if (isr & BIT_DMA_EP_TX_ICR_TX_DONE) {
 248                 wil_dbg_irq(wil, "TX done\n");
 249                 isr &= ~BIT_DMA_EP_TX_ICR_TX_DONE;
 250                 /* clear also all VRING interrupts */
 251                 isr &= ~(BIT(25) - 1UL);
 252                 if (test_bit(wil_status_reset_done, wil->status)) {
 253                         wil_dbg_txrx(wil, "NAPI(Tx) schedule\n");
 254                         need_unmask = false;
 255                         napi_schedule(&wil->napi_tx);
 256                 } else {
 257                         wil_err(wil, "Got Tx interrupt while in reset\n");
 258                 }
 259         }
 260
 261         if (isr)
 262                 wil_err(wil, "un-handled TX ISR bits 0x%08x\n", isr);
 263
 264         /* Tx IRQ will be enabled when NAPI processing finished */
 265
 266         atomic_inc(&wil->isr_count_tx);
 267
 268         if (unlikely(need_unmask))
 269                 wil6210_unmask_irq_tx(wil);
 270
 271         return IRQ_HANDLED;
 272 }
 273
 274 static void wil_notify_fw_error(struct wil6210_priv *wil)
 275 {
 276         struct device *dev = &wil_to_ndev(wil)->dev;
 277         char *envp[3] = {
 278                 [0] = "SOURCE=wil6210",
 279                 [1] = "EVENT=FW_ERROR",
 280                 [2] = NULL,
 281         };
 282         wil_err(wil, "Notify about firmware error\n");
 283         kobject_uevent_env(&dev->kobj, KOBJ_CHANGE, envp);
 284 }
 285
 286 static void wil_cache_mbox_regs(struct wil6210_priv *wil)
 287 {
 288         /* make shadow copy of registers that should not change on run time */
 289         wil_memcpy_fromio_32(&wil->mbox_ctl, wil->csr + HOST_MBOX,
 290                              sizeof(struct wil6210_mbox_ctl));
 291         wil_mbox_ring_le2cpus(&wil->mbox_ctl.rx);
 292         wil_mbox_ring_le2cpus(&wil->mbox_ctl.tx);
 293 }
 294
 295 static irqreturn_t wil6210_irq_misc(int irq, void *cookie)
 296 {
 297         struct wil6210_priv *wil = cookie;
 298         u32 isr = wil_ioread32_and_clear(wil->csr +
 299                                          HOSTADDR(RGF_DMA_EP_MISC_ICR) +
 300                                          offsetof(struct RGF_ICR, ICR));
 301
 302         trace_wil6210_irq_misc(isr);
 303         wil_dbg_irq(wil, "ISR MISC 0x%08x\n", isr);
 304
 305         if (!isr) {
 306                 wil_err(wil, "spurious IRQ: MISC\n");
 307                 return IRQ_NONE;
 308         }
 309
 310         wil6210_mask_irq_misc(wil);
 311
 312         if (isr & ISR_MISC_FW_ERROR) {
 313                 wil_err(wil, "Firmware error detected\n");
 314                 clear_bit(wil_status_fwready, wil->status);
 315                 /*
 316                  * do not clear @isr here - we do 2-nd part in thread
 317                  * there, user space get notified, and it should be done
 318                  * in non-atomic context
 319                  */
 320         }
 321
 322         if (isr & ISR_MISC_FW_READY) {
 323                 wil_dbg_irq(wil, "IRQ: FW ready\n");
 324                 wil_cache_mbox_regs(wil);
 325                 set_bit(wil_status_reset_done, wil->status);
 326                 /**
 327                  * Actual FW ready indicated by the
 328                  * WMI_FW_READY_EVENTID
 329                  */
 330                 isr &= ~ISR_MISC_FW_READY;
 331         }
 332
 333         wil->isr_misc = isr;
 334
 335         if (isr) {
 336                 return IRQ_WAKE_THREAD;
 337         } else {
 338                 wil6210_unmask_irq_misc(wil);
 339                 return IRQ_HANDLED;
 340         }
 341 }
 342
 343 static irqreturn_t wil6210_irq_misc_thread(int irq, void *cookie)
 344 {
 345         struct wil6210_priv *wil = cookie;
 346         u32 isr = wil->isr_misc;
 347
 348         trace_wil6210_irq_misc_thread(isr);
 349         wil_dbg_irq(wil, "Thread ISR MISC 0x%08x\n", isr);
 350
 351         if (isr & ISR_MISC_FW_ERROR) {
 352                 wil_notify_fw_error(wil);
 353                 isr &= ~ISR_MISC_FW_ERROR;
 354                 wil_fw_error_recovery(wil);
 355         }
 356
 357         if (isr & ISR_MISC_MBOX_EVT) {
 358                 wil_dbg_irq(wil, "MBOX event\n");
 359                 wmi_recv_cmd(wil);
 360                 isr &= ~ISR_MISC_MBOX_EVT;
 361         }
 362
 363         if (isr)
 364                 wil_dbg_irq(wil, "un-handled MISC ISR bits 0x%08x\n", isr);
 365
 366         wil->isr_misc = 0;
 367
 368         wil6210_unmask_irq_misc(wil);
 369
 370         return IRQ_HANDLED;
 371 }
 372
 373 /**
 374  * thread IRQ handler
 375  */
 376 static irqreturn_t wil6210_thread_irq(int irq, void *cookie)
 377 {
 378         struct wil6210_priv *wil = cookie;
 379
 380         wil_dbg_irq(wil, "Thread IRQ\n");
 381         /* Discover real IRQ cause */
 382         if (wil->isr_misc)
 383                 wil6210_irq_misc_thread(irq, cookie);
 384
 385         wil6210_unmask_irq_pseudo(wil);
 386
 387         return IRQ_HANDLED;
 388 }
 389
 390 /* DEBUG
 391  * There is subtle bug in hardware that causes IRQ to raise when it should be
 392  * masked. It is quite rare and hard to debug.
 393  *
 394  * Catch irq issue if it happens and print all I can.
 395  */
 396 static int wil6210_debug_irq_mask(struct wil6210_priv *wil, u32 pseudo_cause)
 397 {
 398         if (!test_bit(wil_status_irqen, wil->status)) {
 399                 u32 icm_rx = wil_ioread32_and_clear(wil->csr +
 400                                 HOSTADDR(RGF_DMA_EP_RX_ICR) +
 401                                 offsetof(struct RGF_ICR, ICM));
 402                 u32 icr_rx = wil_ioread32_and_clear(wil->csr +
 403                                 HOSTADDR(RGF_DMA_EP_RX_ICR) +
 404                                 offsetof(struct RGF_ICR, ICR));
 405                 u32 imv_rx = ioread32(wil->csr +
 406                                 HOSTADDR(RGF_DMA_EP_RX_ICR) +
 407                                 offsetof(struct RGF_ICR, IMV));
 408                 u32 icm_tx = wil_ioread32_and_clear(wil->csr +
 409                                 HOSTADDR(RGF_DMA_EP_TX_ICR) +
 410                                 offsetof(struct RGF_ICR, ICM));
 411                 u32 icr_tx = wil_ioread32_and_clear(wil->csr +
 412                                 HOSTADDR(RGF_DMA_EP_TX_ICR) +
 413                                 offsetof(struct RGF_ICR, ICR));
 414                 u32 imv_tx = ioread32(wil->csr +
 415                                 HOSTADDR(RGF_DMA_EP_TX_ICR) +
 416                                 offsetof(struct RGF_ICR, IMV));
 417                 u32 icm_misc = wil_ioread32_and_clear(wil->csr +
 418                                 HOSTADDR(RGF_DMA_EP_MISC_ICR) +
 419                                 offsetof(struct RGF_ICR, ICM));
 420                 u32 icr_misc = wil_ioread32_and_clear(wil->csr +
 421                                 HOSTADDR(RGF_DMA_EP_MISC_ICR) +
 422                                 offsetof(struct RGF_ICR, ICR));
 423                 u32 imv_misc = ioread32(wil->csr +
 424                                 HOSTADDR(RGF_DMA_EP_MISC_ICR) +
 425                                 offsetof(struct RGF_ICR, IMV));
 426                 wil_err(wil, "IRQ when it should be masked: pseudo 0x%08x\n"
 427                                 "Rx   icm:icr:imv 0x%08x 0x%08x 0x%08x\n"
 428                                 "Tx   icm:icr:imv 0x%08x 0x%08x 0x%08x\n"
 429                                 "Misc icm:icr:imv 0x%08x 0x%08x 0x%08x\n",
 430                                 pseudo_cause,
 431                                 icm_rx, icr_rx, imv_rx,
 432                                 icm_tx, icr_tx, imv_tx,
 433                                 icm_misc, icr_misc, imv_misc);
 434
 435                 return -EINVAL;
 436         }
 437
 438         return 0;
 439 }
 440
 441 static irqreturn_t wil6210_hardirq(int irq, void *cookie)
 442 {
 443         irqreturn_t rc = IRQ_HANDLED;
 444         struct wil6210_priv *wil = cookie;
 445         u32 pseudo_cause = ioread32(wil->csr + HOSTADDR(RGF_DMA_PSEUDO_CAUSE));
 446
 447         /**
 448          * pseudo_cause is Clear-On-Read, no need to ACK
 449          */
 450         if ((pseudo_cause == 0) || ((pseudo_cause & 0xff) == 0xff))
 451                 return IRQ_NONE;
 452
 453         /* FIXME: IRQ mask debug */
 454         if (wil6210_debug_irq_mask(wil, pseudo_cause))
 455                 return IRQ_NONE;
 456
 457         trace_wil6210_irq_pseudo(pseudo_cause);
 458         wil_dbg_irq(wil, "Pseudo IRQ 0x%08x\n", pseudo_cause);
 459
 460         wil6210_mask_irq_pseudo(wil);
 461
 462         /* Discover real IRQ cause
 463          * There are 2 possible phases for every IRQ:
 464          * - hard IRQ handler called right here
 465          * - threaded handler called later
 466          *
 467          * Hard IRQ handler reads and clears ISR.
 468          *
 469          * If threaded handler requested, hard IRQ handler
 470          * returns IRQ_WAKE_THREAD and saves ISR register value
 471          * for the threaded handler use.
 472          *
 473          * voting for wake thread - need at least 1 vote
 474          */
 475         if ((pseudo_cause & BIT_DMA_PSEUDO_CAUSE_RX) &&
 476             (wil6210_irq_rx(irq, cookie) == IRQ_WAKE_THREAD))
 477                 rc = IRQ_WAKE_THREAD;
 478
 479         if ((pseudo_cause & BIT_DMA_PSEUDO_CAUSE_TX) &&
 480             (wil6210_irq_tx(irq, cookie) == IRQ_WAKE_THREAD))
 481                 rc = IRQ_WAKE_THREAD;
 482
 483         if ((pseudo_cause & BIT_DMA_PSEUDO_CAUSE_MISC) &&
 484             (wil6210_irq_misc(irq, cookie) == IRQ_WAKE_THREAD))
 485                 rc = IRQ_WAKE_THREAD;
 486
 487         /* if thread is requested, it will unmask IRQ */
 488         if (rc != IRQ_WAKE_THREAD)
 489                 wil6210_unmask_irq_pseudo(wil);
 490
 491         return rc;
 492 }
 493
 494 static int wil6210_request_3msi(struct wil6210_priv *wil, int irq)
 495 {
 496         int rc;
 497         /*
 498          * IRQ's are in the following order:
 499          * - Tx
 500          * - Rx
 501          * - Misc
 502          */
 503
 504         rc = request_irq(irq, wil6210_irq_tx, IRQF_SHARED,
 505                          WIL_NAME"_tx", wil);
 506         if (rc)
 507                 return rc;
 508
 509         rc = request_irq(irq + 1, wil6210_irq_rx, IRQF_SHARED,
 510                          WIL_NAME"_rx", wil);
 511         if (rc)
 512                 goto free0;
 513
 514         rc = request_threaded_irq(irq + 2, wil6210_irq_misc,
 515                                   wil6210_irq_misc_thread,
 516                                   IRQF_SHARED, WIL_NAME"_misc", wil);
 517         if (rc)
 518                 goto free1;
 519
 520         return 0;
 521         /* error branch */
 522 free1:
 523         free_irq(irq + 1, wil);
 524 free0:
 525         free_irq(irq, wil);
 526
 527         return rc;
 528 }
 529
 530 /* can't use wil_ioread32_and_clear because ICC value is not set yet */
 531 static inline void wil_clear32(void __iomem *addr)
 532 {
 533         u32 x = ioread32(addr);
 534
 535         iowrite32(x, addr);
 536 }
 537
 538 void wil6210_clear_irq(struct wil6210_priv *wil)
 539 {
 540         wil_clear32(wil->csr + HOSTADDR(RGF_DMA_EP_RX_ICR) +
 541                     offsetof(struct RGF_ICR, ICR));
 542         wil_clear32(wil->csr + HOSTADDR(RGF_DMA_EP_TX_ICR) +
 543                     offsetof(struct RGF_ICR, ICR));
 544         wil_clear32(wil->csr + HOSTADDR(RGF_DMA_EP_MISC_ICR) +
 545                     offsetof(struct RGF_ICR, ICR));
 546         wmb(); /* make sure write completed */
 547 }
 548
 549 int wil6210_init_irq(struct wil6210_priv *wil, int irq)
 550 {
 551         int rc;
 552
 553         wil_dbg_misc(wil, "%s() n_msi=%d\n", __func__, wil->n_msi);
 554
 555         if (wil->n_msi == 3)
 556                 rc = wil6210_request_3msi(wil, irq);
 557         else
 558                 rc = request_threaded_irq(irq, wil6210_hardirq,
 559                                           wil6210_thread_irq,
 560                                           wil->n_msi ? 0 : IRQF_SHARED,
 561                                           WIL_NAME, wil);
 562         return rc;
 563 }
 564
 565 void wil6210_fini_irq(struct wil6210_priv *wil, int irq)
 566 {
 567         wil_dbg_misc(wil, "%s()\n", __func__);
 568
 569         wil_mask_irq(wil);
 570         free_irq(irq, wil);
 571         if (wil->n_msi == 3) {
 572                 free_irq(irq + 1, wil);
 573                 free_irq(irq + 2, wil);
 574         }
 575 }