drivers/net/wireless/ath/wil6210/interrupt.c

   1 /*
   2  * Copyright (c) 2012-2014 Qualcomm Atheros, Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/interrupt.h>
  18
  19 #include "wil6210.h"
  20 #include "trace.h"
  21
  22 /**
  23  * Theory of operation:
  24  *
  25  * There is ISR pseudo-cause register,
  26  * dma_rgf->DMA_RGF.PSEUDO_CAUSE.PSEUDO_CAUSE
  27  * Its bits represents OR'ed bits from 3 real ISR registers:
  28  * TX, RX, and MISC.
  29  *
  30  * Registers may be configured to either "write 1 to clear" or
  31  * "clear on read" mode
  32  *
  33  * When handling interrupt, one have to mask/unmask interrupts for the
  34  * real ISR registers, or hardware may malfunction.
  35  *
  36  */
  37
  38 #define WIL6210_IRQ_DISABLE     (0xFFFFFFFFUL)
  39 #define WIL6210_IMC_RX          BIT_DMA_EP_RX_ICR_RX_DONE
  40 #define WIL6210_IMC_TX          (BIT_DMA_EP_TX_ICR_TX_DONE | \
  41                                 BIT_DMA_EP_TX_ICR_TX_DONE_N(0))
  42 #define WIL6210_IMC_MISC        (ISR_MISC_FW_READY | \
  43                                  ISR_MISC_MBOX_EVT | \
  44                                  ISR_MISC_FW_ERROR)
  45
  46 #define WIL6210_IRQ_PSEUDO_MASK (u32)(~(BIT_DMA_PSEUDO_CAUSE_RX | \
  47                                         BIT_DMA_PSEUDO_CAUSE_TX | \
  48                                         BIT_DMA_PSEUDO_CAUSE_MISC))
  49
  50 #if defined(CONFIG_WIL6210_ISR_COR)
  51 /* configure to Clear-On-Read mode */
  52 #define WIL_ICR_ICC_VALUE       (0xFFFFFFFFUL)
  53
  54 static inline void wil_icr_clear(u32 x, void __iomem *addr)
  55 {
  56 }
  57 #else /* defined(CONFIG_WIL6210_ISR_COR) */
  58 /* configure to Write-1-to-Clear mode */
  59 #define WIL_ICR_ICC_VALUE       (0UL)
  60
  61 static inline void wil_icr_clear(u32 x, void __iomem *addr)
  62 {
  63         iowrite32(x, addr);
  64 }
  65 #endif /* defined(CONFIG_WIL6210_ISR_COR) */
  66
  67 static inline u32 wil_ioread32_and_clear(void __iomem *addr)
  68 {
  69         u32 x = ioread32(addr);
  70
  71         wil_icr_clear(x, addr);
  72
  73         return x;
  74 }
  75
  76 static void wil6210_mask_irq_tx(struct wil6210_priv *wil)
  77 {
  78         iowrite32(WIL6210_IRQ_DISABLE, wil->csr +
  79                   HOSTADDR(RGF_DMA_EP_TX_ICR) +
  80                   offsetof(struct RGF_ICR, IMS));
  81 }
  82
  83 static void wil6210_mask_irq_rx(struct wil6210_priv *wil)
  84 {
  85         iowrite32(WIL6210_IRQ_DISABLE, wil->csr +
  86                   HOSTADDR(RGF_DMA_EP_RX_ICR) +
  87                   offsetof(struct RGF_ICR, IMS));
  88 }
  89
  90 static void wil6210_mask_irq_misc(struct wil6210_priv *wil)
  91 {
  92         iowrite32(WIL6210_IRQ_DISABLE, wil->csr +
  93                   HOSTADDR(RGF_DMA_EP_MISC_ICR) +
  94                   offsetof(struct RGF_ICR, IMS));
  95 }
  96
  97 static void wil6210_mask_irq_pseudo(struct wil6210_priv *wil)
  98 {
  99         wil_dbg_irq(wil, "%s()\n", __func__);
 100
 101         iowrite32(WIL6210_IRQ_DISABLE, wil->csr +
 102                   HOSTADDR(RGF_DMA_PSEUDO_CAUSE_MASK_SW));
 103
 104         clear_bit(wil_status_irqen, &wil->status);
 105 }
 106
 107 void wil6210_unmask_irq_tx(struct wil6210_priv *wil)
 108 {
 109         iowrite32(WIL6210_IMC_TX, wil->csr +
 110                   HOSTADDR(RGF_DMA_EP_TX_ICR) +
 111                   offsetof(struct RGF_ICR, IMC));
 112 }
 113
 114 void wil6210_unmask_irq_rx(struct wil6210_priv *wil)
 115 {
 116         iowrite32(WIL6210_IMC_RX, wil->csr +
 117                   HOSTADDR(RGF_DMA_EP_RX_ICR) +
 118                   offsetof(struct RGF_ICR, IMC));
 119 }
 120
 121 static void wil6210_unmask_irq_misc(struct wil6210_priv *wil)
 122 {
 123         iowrite32(WIL6210_IMC_MISC, wil->csr +
 124                   HOSTADDR(RGF_DMA_EP_MISC_ICR) +
 125                   offsetof(struct RGF_ICR, IMC));
 126 }
 127
 128 static void wil6210_unmask_irq_pseudo(struct wil6210_priv *wil)
 129 {
 130         wil_dbg_irq(wil, "%s()\n", __func__);
 131
 132         set_bit(wil_status_irqen, &wil->status);
 133
 134         iowrite32(WIL6210_IRQ_PSEUDO_MASK, wil->csr +
 135                   HOSTADDR(RGF_DMA_PSEUDO_CAUSE_MASK_SW));
 136 }
 137
 138 void wil_mask_irq(struct wil6210_priv *wil)
 139 {
 140         wil_dbg_irq(wil, "%s()\n", __func__);
 141
 142         wil6210_mask_irq_tx(wil);
 143         wil6210_mask_irq_rx(wil);
 144         wil6210_mask_irq_misc(wil);
 145         wil6210_mask_irq_pseudo(wil);
 146 }
 147
 148 void wil_unmask_irq(struct wil6210_priv *wil)
 149 {
 150         wil_dbg_irq(wil, "%s()\n", __func__);
 151
 152         iowrite32(WIL_ICR_ICC_VALUE, wil->csr + HOSTADDR(RGF_DMA_EP_RX_ICR) +
 153                   offsetof(struct RGF_ICR, ICC));
 154         iowrite32(WIL_ICR_ICC_VALUE, wil->csr + HOSTADDR(RGF_DMA_EP_TX_ICR) +
 155                   offsetof(struct RGF_ICR, ICC));
 156         iowrite32(WIL_ICR_ICC_VALUE, wil->csr + HOSTADDR(RGF_DMA_EP_MISC_ICR) +
 157                   offsetof(struct RGF_ICR, ICC));
 158
 159         /* interrupt moderation parameters */
 160         if (wil->wdev->iftype == NL80211_IFTYPE_MONITOR) {
 161                 /* disable interrupt moderation for monitor
 162                  * to get better timestamp precision
 163                  */
 164                 iowrite32(0, wil->csr + HOSTADDR(RGF_DMA_ITR_CNT_CRL));
 165         } else {
 166                 iowrite32(WIL6210_ITR_TRSH,
 167                           wil->csr + HOSTADDR(RGF_DMA_ITR_CNT_TRSH));
 168                 iowrite32(BIT_DMA_ITR_CNT_CRL_EN,
 169                           wil->csr + HOSTADDR(RGF_DMA_ITR_CNT_CRL));
 170         }
 171
 172         wil6210_unmask_irq_pseudo(wil);
 173         wil6210_unmask_irq_tx(wil);
 174         wil6210_unmask_irq_rx(wil);
 175         wil6210_unmask_irq_misc(wil);
 176 }
 177
 178 static irqreturn_t wil6210_irq_rx(int irq, void *cookie)
 179 {
 180         struct wil6210_priv *wil = cookie;
 181         u32 isr = wil_ioread32_and_clear(wil->csr +
 182                                          HOSTADDR(RGF_DMA_EP_RX_ICR) +
 183                                          offsetof(struct RGF_ICR, ICR));
 184
 185         trace_wil6210_irq_rx(isr);
 186         wil_dbg_irq(wil, "ISR RX 0x%08x\n", isr);
 187
 188         if (!isr) {
 189                 wil_err(wil, "spurious IRQ: RX\n");
 190                 return IRQ_NONE;
 191         }
 192
 193         wil6210_mask_irq_rx(wil);
 194
 195         if (isr & BIT_DMA_EP_RX_ICR_RX_DONE) {
 196                 wil_dbg_irq(wil, "RX done\n");
 197                 isr &= ~BIT_DMA_EP_RX_ICR_RX_DONE;
 198                 if (test_bit(wil_status_reset_done, &wil->status)) {
 199                         if (test_bit(wil_status_napi_en, &wil->status)) {
 200                                 wil_dbg_txrx(wil, "NAPI(Rx) schedule\n");
 201                                 napi_schedule(&wil->napi_rx);
 202                         } else {
 203                                 wil_err(wil, "Got Rx interrupt while "
 204                                         "stopping interface\n");
 205                         }
 206                 } else {
 207                         wil_err(wil, "Got Rx interrupt while in reset\n");
 208                 }
 209         }
 210
 211         if (isr)
 212                 wil_err(wil, "un-handled RX ISR bits 0x%08x\n", isr);
 213
 214         /* Rx IRQ will be enabled when NAPI processing finished */
 215
 216         atomic_inc(&wil->isr_count_rx);
 217         return IRQ_HANDLED;
 218 }
 219
 220 static irqreturn_t wil6210_irq_tx(int irq, void *cookie)
 221 {
 222         struct wil6210_priv *wil = cookie;
 223         u32 isr = wil_ioread32_and_clear(wil->csr +
 224                                          HOSTADDR(RGF_DMA_EP_TX_ICR) +
 225                                          offsetof(struct RGF_ICR, ICR));
 226
 227         trace_wil6210_irq_tx(isr);
 228         wil_dbg_irq(wil, "ISR TX 0x%08x\n", isr);
 229
 230         if (!isr) {
 231                 wil_err(wil, "spurious IRQ: TX\n");
 232                 return IRQ_NONE;
 233         }
 234
 235         wil6210_mask_irq_tx(wil);
 236
 237         if (isr & BIT_DMA_EP_TX_ICR_TX_DONE) {
 238                 wil_dbg_irq(wil, "TX done\n");
 239                 isr &= ~BIT_DMA_EP_TX_ICR_TX_DONE;
 240                 /* clear also all VRING interrupts */
 241                 isr &= ~(BIT(25) - 1UL);
 242                 if (test_bit(wil_status_reset_done, &wil->status)) {
 243                         wil_dbg_txrx(wil, "NAPI(Tx) schedule\n");
 244                         napi_schedule(&wil->napi_tx);
 245                 } else {
 246                         wil_err(wil, "Got Tx interrupt while in reset\n");
 247                 }
 248         }
 249
 250         if (isr)
 251                 wil_err(wil, "un-handled TX ISR bits 0x%08x\n", isr);
 252
 253         /* Tx IRQ will be enabled when NAPI processing finished */
 254
 255         atomic_inc(&wil->isr_count_tx);
 256         return IRQ_HANDLED;
 257 }
 258
 259 static void wil_notify_fw_error(struct wil6210_priv *wil)
 260 {
 261         struct device *dev = &wil_to_ndev(wil)->dev;
 262         char *envp[3] = {
 263                 [0] = "SOURCE=wil6210",
 264                 [1] = "EVENT=FW_ERROR",
 265                 [2] = NULL,
 266         };
 267         wil_err(wil, "Notify about firmware error\n");
 268         kobject_uevent_env(&dev->kobj, KOBJ_CHANGE, envp);
 269 }
 270
 271 static void wil_cache_mbox_regs(struct wil6210_priv *wil)
 272 {
 273         /* make shadow copy of registers that should not change on run time */
 274         wil_memcpy_fromio_32(&wil->mbox_ctl, wil->csr + HOST_MBOX,
 275                              sizeof(struct wil6210_mbox_ctl));
 276         wil_mbox_ring_le2cpus(&wil->mbox_ctl.rx);
 277         wil_mbox_ring_le2cpus(&wil->mbox_ctl.tx);
 278 }
 279
 280 static irqreturn_t wil6210_irq_misc(int irq, void *cookie)
 281 {
 282         struct wil6210_priv *wil = cookie;
 283         u32 isr = wil_ioread32_and_clear(wil->csr +
 284                                          HOSTADDR(RGF_DMA_EP_MISC_ICR) +
 285                                          offsetof(struct RGF_ICR, ICR));
 286
 287         trace_wil6210_irq_misc(isr);
 288         wil_dbg_irq(wil, "ISR MISC 0x%08x\n", isr);
 289
 290         if (!isr) {
 291                 wil_err(wil, "spurious IRQ: MISC\n");
 292                 return IRQ_NONE;
 293         }
 294
 295         wil6210_mask_irq_misc(wil);
 296
 297         if (isr & ISR_MISC_FW_ERROR) {
 298                 wil_err(wil, "Firmware error detected\n");
 299                 clear_bit(wil_status_fwready, &wil->status);
 300                 /*
 301                  * do not clear @isr here - we do 2-nd part in thread
 302                  * there, user space get notified, and it should be done
 303                  * in non-atomic context
 304                  */
 305         }
 306
 307         if (isr & ISR_MISC_FW_READY) {
 308                 wil_dbg_irq(wil, "IRQ: FW ready\n");
 309                 wil_cache_mbox_regs(wil);
 310                 set_bit(wil_status_reset_done, &wil->status);
 311                 /**
 312                  * Actual FW ready indicated by the
 313                  * WMI_FW_READY_EVENTID
 314                  */
 315                 isr &= ~ISR_MISC_FW_READY;
 316         }
 317
 318         wil->isr_misc = isr;
 319
 320         if (isr) {
 321                 return IRQ_WAKE_THREAD;
 322         } else {
 323                 wil6210_unmask_irq_misc(wil);
 324                 return IRQ_HANDLED;
 325         }
 326 }
 327
 328 static irqreturn_t wil6210_irq_misc_thread(int irq, void *cookie)
 329 {
 330         struct wil6210_priv *wil = cookie;
 331         u32 isr = wil->isr_misc;
 332
 333         trace_wil6210_irq_misc_thread(isr);
 334         wil_dbg_irq(wil, "Thread ISR MISC 0x%08x\n", isr);
 335
 336         if (isr & ISR_MISC_FW_ERROR) {
 337                 wil_notify_fw_error(wil);
 338                 isr &= ~ISR_MISC_FW_ERROR;
 339                 wil_fw_error_recovery(wil);
 340         }
 341
 342         if (isr & ISR_MISC_MBOX_EVT) {
 343                 wil_dbg_irq(wil, "MBOX event\n");
 344                 wmi_recv_cmd(wil);
 345                 isr &= ~ISR_MISC_MBOX_EVT;
 346         }
 347
 348         if (isr)
 349                 wil_dbg_irq(wil, "un-handled MISC ISR bits 0x%08x\n", isr);
 350
 351         wil->isr_misc = 0;
 352
 353         wil6210_unmask_irq_misc(wil);
 354
 355         return IRQ_HANDLED;
 356 }
 357
 358 /**
 359  * thread IRQ handler
 360  */
 361 static irqreturn_t wil6210_thread_irq(int irq, void *cookie)
 362 {
 363         struct wil6210_priv *wil = cookie;
 364
 365         wil_dbg_irq(wil, "Thread IRQ\n");
 366         /* Discover real IRQ cause */
 367         if (wil->isr_misc)
 368                 wil6210_irq_misc_thread(irq, cookie);
 369
 370         wil6210_unmask_irq_pseudo(wil);
 371
 372         return IRQ_HANDLED;
 373 }
 374
 375 /* DEBUG
 376  * There is subtle bug in hardware that causes IRQ to raise when it should be
 377  * masked. It is quite rare and hard to debug.
 378  *
 379  * Catch irq issue if it happens and print all I can.
 380  */
 381 static int wil6210_debug_irq_mask(struct wil6210_priv *wil, u32 pseudo_cause)
 382 {
 383         if (!test_bit(wil_status_irqen, &wil->status)) {
 384                 u32 icm_rx = wil_ioread32_and_clear(wil->csr +
 385                                 HOSTADDR(RGF_DMA_EP_RX_ICR) +
 386                                 offsetof(struct RGF_ICR, ICM));
 387                 u32 icr_rx = wil_ioread32_and_clear(wil->csr +
 388                                 HOSTADDR(RGF_DMA_EP_RX_ICR) +
 389                                 offsetof(struct RGF_ICR, ICR));
 390                 u32 imv_rx = ioread32(wil->csr +
 391                                 HOSTADDR(RGF_DMA_EP_RX_ICR) +
 392                                 offsetof(struct RGF_ICR, IMV));
 393                 u32 icm_tx = wil_ioread32_and_clear(wil->csr +
 394                                 HOSTADDR(RGF_DMA_EP_TX_ICR) +
 395                                 offsetof(struct RGF_ICR, ICM));
 396                 u32 icr_tx = wil_ioread32_and_clear(wil->csr +
 397                                 HOSTADDR(RGF_DMA_EP_TX_ICR) +
 398                                 offsetof(struct RGF_ICR, ICR));
 399                 u32 imv_tx = ioread32(wil->csr +
 400                                 HOSTADDR(RGF_DMA_EP_TX_ICR) +
 401                                 offsetof(struct RGF_ICR, IMV));
 402                 u32 icm_misc = wil_ioread32_and_clear(wil->csr +
 403                                 HOSTADDR(RGF_DMA_EP_MISC_ICR) +
 404                                 offsetof(struct RGF_ICR, ICM));
 405                 u32 icr_misc = wil_ioread32_and_clear(wil->csr +
 406                                 HOSTADDR(RGF_DMA_EP_MISC_ICR) +
 407                                 offsetof(struct RGF_ICR, ICR));
 408                 u32 imv_misc = ioread32(wil->csr +
 409                                 HOSTADDR(RGF_DMA_EP_MISC_ICR) +
 410                                 offsetof(struct RGF_ICR, IMV));
 411                 wil_err(wil, "IRQ when it should be masked: pseudo 0x%08x\n"
 412                                 "Rx   icm:icr:imv 0x%08x 0x%08x 0x%08x\n"
 413                                 "Tx   icm:icr:imv 0x%08x 0x%08x 0x%08x\n"
 414                                 "Misc icm:icr:imv 0x%08x 0x%08x 0x%08x\n",
 415                                 pseudo_cause,
 416                                 icm_rx, icr_rx, imv_rx,
 417                                 icm_tx, icr_tx, imv_tx,
 418                                 icm_misc, icr_misc, imv_misc);
 419
 420                 return -EINVAL;
 421         }
 422
 423         return 0;
 424 }
 425
 426 static irqreturn_t wil6210_hardirq(int irq, void *cookie)
 427 {
 428         irqreturn_t rc = IRQ_HANDLED;
 429         struct wil6210_priv *wil = cookie;
 430         u32 pseudo_cause = ioread32(wil->csr + HOSTADDR(RGF_DMA_PSEUDO_CAUSE));
 431
 432         /**
 433          * pseudo_cause is Clear-On-Read, no need to ACK
 434          */
 435         if ((pseudo_cause == 0) || ((pseudo_cause & 0xff) == 0xff))
 436                 return IRQ_NONE;
 437
 438         /* FIXME: IRQ mask debug */
 439         if (wil6210_debug_irq_mask(wil, pseudo_cause))
 440                 return IRQ_NONE;
 441
 442         trace_wil6210_irq_pseudo(pseudo_cause);
 443         wil_dbg_irq(wil, "Pseudo IRQ 0x%08x\n", pseudo_cause);
 444
 445         wil6210_mask_irq_pseudo(wil);
 446
 447         /* Discover real IRQ cause
 448          * There are 2 possible phases for every IRQ:
 449          * - hard IRQ handler called right here
 450          * - threaded handler called later
 451          *
 452          * Hard IRQ handler reads and clears ISR.
 453          *
 454          * If threaded handler requested, hard IRQ handler
 455          * returns IRQ_WAKE_THREAD and saves ISR register value
 456          * for the threaded handler use.
 457          *
 458          * voting for wake thread - need at least 1 vote
 459          */
 460         if ((pseudo_cause & BIT_DMA_PSEUDO_CAUSE_RX) &&
 461             (wil6210_irq_rx(irq, cookie) == IRQ_WAKE_THREAD))
 462                 rc = IRQ_WAKE_THREAD;
 463
 464         if ((pseudo_cause & BIT_DMA_PSEUDO_CAUSE_TX) &&
 465             (wil6210_irq_tx(irq, cookie) == IRQ_WAKE_THREAD))
 466                 rc = IRQ_WAKE_THREAD;
 467
 468         if ((pseudo_cause & BIT_DMA_PSEUDO_CAUSE_MISC) &&
 469             (wil6210_irq_misc(irq, cookie) == IRQ_WAKE_THREAD))
 470                 rc = IRQ_WAKE_THREAD;
 471
 472         /* if thread is requested, it will unmask IRQ */
 473         if (rc != IRQ_WAKE_THREAD)
 474                 wil6210_unmask_irq_pseudo(wil);
 475
 476         return rc;
 477 }
 478
 479 static int wil6210_request_3msi(struct wil6210_priv *wil, int irq)
 480 {
 481         int rc;
 482         /*
 483          * IRQ's are in the following order:
 484          * - Tx
 485          * - Rx
 486          * - Misc
 487          */
 488
 489         rc = request_irq(irq, wil6210_irq_tx, IRQF_SHARED,
 490                          WIL_NAME"_tx", wil);
 491         if (rc)
 492                 return rc;
 493
 494         rc = request_irq(irq + 1, wil6210_irq_rx, IRQF_SHARED,
 495                          WIL_NAME"_rx", wil);
 496         if (rc)
 497                 goto free0;
 498
 499         rc = request_threaded_irq(irq + 2, wil6210_irq_misc,
 500                                   wil6210_irq_misc_thread,
 501                                   IRQF_SHARED, WIL_NAME"_misc", wil);
 502         if (rc)
 503                 goto free1;
 504
 505         return 0;
 506         /* error branch */
 507 free1:
 508         free_irq(irq + 1, wil);
 509 free0:
 510         free_irq(irq, wil);
 511
 512         return rc;
 513 }
 514
 515 /* can't use wil_ioread32_and_clear because ICC value is not set yet */
 516 static inline void wil_clear32(void __iomem *addr)
 517 {
 518         u32 x = ioread32(addr);
 519
 520         iowrite32(x, addr);
 521 }
 522
 523 void wil6210_clear_irq(struct wil6210_priv *wil)
 524 {
 525         wil_clear32(wil->csr + HOSTADDR(RGF_DMA_EP_RX_ICR) +
 526                     offsetof(struct RGF_ICR, ICR));
 527         wil_clear32(wil->csr + HOSTADDR(RGF_DMA_EP_TX_ICR) +
 528                     offsetof(struct RGF_ICR, ICR));
 529         wil_clear32(wil->csr + HOSTADDR(RGF_DMA_EP_MISC_ICR) +
 530                     offsetof(struct RGF_ICR, ICR));
 531         wmb(); /* make sure write completed */
 532 }
 533
 534 int wil6210_init_irq(struct wil6210_priv *wil, int irq)
 535 {
 536         int rc;
 537
 538         wil_dbg_misc(wil, "%s() n_msi=%d\n", __func__, wil->n_msi);
 539
 540         if (wil->n_msi == 3)
 541                 rc = wil6210_request_3msi(wil, irq);
 542         else
 543                 rc = request_threaded_irq(irq, wil6210_hardirq,
 544                                           wil6210_thread_irq,
 545                                           wil->n_msi ? 0 : IRQF_SHARED,
 546                                           WIL_NAME, wil);
 547         return rc;
 548 }
 549
 550 void wil6210_fini_irq(struct wil6210_priv *wil, int irq)
 551 {
 552         wil_dbg_misc(wil, "%s()\n", __func__);
 553
 554         wil_mask_irq(wil);
 555         free_irq(irq, wil);
 556         if (wil->n_msi == 3) {
 557                 free_irq(irq + 1, wil);
 558                 free_irq(irq + 2, wil);
 559         }
 560 }